AIM:
To implement the given logic function verify its operation in Quartus using Verilog programming.
F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D
F2=xy’z+x’y’z+w’xy+wx’y+wxy
Equipment Required:
Hardware – PCs, Cyclone II , USB flasher
Software – Quartus prime
Theory
Logic Diagram
Procedure
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Type the program in Quartus software.
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Compile and run the program.
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Generate the RTL schematic and save the logic diagram.
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Create nodes for inputs and outputs to generate the timing diagram.
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For different input combinations generate the timing diagram.
Program:
module functi(a, b,c,d, f1);
input a,b,c,d;
output f1;
assign f1=((~b &~d)|(~a & b & d)|(a & b & ~c));
endmodule
module funct2(w,x,y,z, f2);
input w,x,y,z;
output f2;
assign f2=((~y & z)(w & y )I(x & y));
endmodule
Developed by: Yugabharathi.M RegisterNumber: 212224230314
RTL realization
Output:
RTL
Timing Diagram
Result:
Thus the given logic functions are implemented using and their operations are verified using Verilog programming.