Rework x86 SHA SIMD kernels: AVX2 2-block + SIMD-schedule SSE2#95
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x86_64: - AVX2 slot now runs the 2-block kernel (sha512_block_data_order_avx2): two blocks scheduled together in 256-bit lanes. - SSE2 kernel rewritten with a SIMD message schedule (downported from the AVX single-block, interleaved with the GPR compression rounds). - Remove the SSSE3 kernel; SSSE3-capable CPUs now use the faster SSE2. i386: - SSE2 kernel replaced with a port of OpenSSL's sha512-586, its MMX core mechanically converted to pure SSE2 (state in xmm0-xmm7). - Remove the SSSE3 kernel (it was slower than the new SSE2). - Add a shared unit-level K512_Doubled table (each constant stored twice) feeding both the 256-bit AVX2 and 128-bit x86_64 SSE2 reads; the plain K512 table is left unchanged.
Replace the two-phase SHA-256 kernels with OpenSSL/CRYPTOGAMS interleaved SIMD-schedule designs, mirroring the earlier SHA-512 work. x86_64: - AVX2: port sha256_block_data_order_avx2 (two blocks scheduled together in 256-bit lanes; compression stays serial). - SSE2: port OpenSSL's SSSE3 kernel with its two SSSE3-only ops emulated in SSE2 (pshufb dword byte-swap -> psrlw/psllw/por + pshuflw/pshufhw; palignr -> psrldq/pslldq/por). Remove the SSSE3 tier. i386: - SSE2: port sha256-586's SSSE3 kernel with the same emulation (scratch xmm chosen per site by liveness), K strides doubled so it shares K256_Doubled. Remove the SSSE3 tier.
eplace the two-phase SHA-1 kernels with OpenSSL/CRYPTOGAMS interleaved SIMD-schedule designs, mirroring the SHA-256/SHA-512 work. x86_64: - AVX2: port the two-block path from sha1-x86_64.pl (two message blocks scheduled together in 256-bit lanes; the 80 rounds interleaved with the schedule). AVX2/BMI (rorx/andn/shlx) ops are db-encoded for assembler compatibility. - SSE2: port OpenSSL's SSSE3 kernel with its one SSSE3-only op emulated in SSE2 (pshufb byte-swap -> psrlw/psllw/por + pshuflw/pshufhw). Remove the SSSE3 tier. i386: - SSE2: port sha1-586's SSSE3 kernel with the same emulation, K strides doubled so it shares K_SHA1_Doubled. Remove the SSSE3 tier. Add K_SHA1_Doubled: each round constant replicated across a 128-bit lane and stored twice, so one table feeds both the 256-bit AVX2 read and the 128-bit SSE2 reads at a 32-byte stride; the AVX2 byte-swap/reverse masks are appended.
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Reworks the x86 (i386 + x86-64) SIMD kernels for SHA-1, SHA-256, and SHA-512