Refactor SIMD architecture for agnostic dispatch and cleanup#129
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Split every SIMD-accelerated family into an architecture-neutral dispatch
facade (Clp<Family>Simd) over a per-arch backend (Clp<Family>X86Backend),
so algorithm/mode units no longer carry {$IFDEF CRYPTOLIB_X86_SIMD} gating,
inline asm, or direct TCpuFeatures/TIntrinsicsVector probes. Off-SIMD builds
fall through to the existing scalar reference paths unchanged.
Families routed through a facade: AES engine, ChaCha, Salsa20, Poly1305,
GHASH/GF(2^128), GCM-SIV POLYVAL, binary-polynomial multiply, and the fused
AES AEAD resolver.
Made the six AEAD mode units architecture-agnostic (GCM, CCM, EAX, OCB,
GCM-SIV, GcmUtilities): removed all x86 guards and lifted the GCM inline asm
(block XOR, byte-reverse, fused shuffled-GHASH, the PSHUFB mask) out of
ClpGcmBlockCipher into ClpGhashX86Backend behind the TGhashSimd facade.
The fused-kernel registry and IFused*Kernel interfaces are arch-neutral and
return nil off-SIMD, so no compile-time gating remains in the mode layer.
Naming/clarity:
- ClpAesNiAeadResolver -> ClpAesFusedAeadX86Backend
- TGhashSimd.HasPclmul -> HasCarrylessMultiply (neutral over PCLMULQDQ/PMULL)
- Neutralized PCLMULQDQ wording in resourcestrings
- Introduced shared TPoly1305State record unit (breaks engine<->backend cycle)
- Trimmed comments that rot: "x86 today, arm later" speculation, specific
SSE/AVX version tiers in backend docs, and "off-x86" -> "off-SIMD" in the
arch-neutral units. The SIMD feature-detection layer still names tiers
(its job); x86 backends keep AES-NI/PCLMULQDQ where those identify a kernel.
Behavior is byte-for-byte identical on x86; the moved asm and capability
gates are the same instructions/tiers relocated.
Each Clp<Family>Simd facade carried a {$ELSEIF DEFINED(CRYPTOLIB_ARM_SIMD)}
branch (uses import + one call per method) pointing at ARM backend units that
do not exist yet. The branch is never compiled (CRYPTOLIB_ARM_SIMD is undefined),
so it was a dangling reference to units that aren't there. ARM implementations
are deferred, so drop the reserved slots now; they'll be re-added alongside the
real ARM backends later.
Collapses each dispatch to:
{$IF X86} <x86 call> {$ELSE} Result := False / no-op {$IFEND}
Facades cleaned (8), with the reserved unit/class removed from each:
- ClpAesSimd -> ClpAesEngineArm / TAesEngineArm
- ClpBinPolySimd -> ClpBinPolyArmV128Backend / TBinPolyArmV128Backend
- ClpPoly1305Simd -> ClpPoly1305ArmBackend / TPoly1305ArmBackend
- ClpGhashSimd -> ClpGhashArmBackend / TGhashArmBackend
- ClpGcmSivSimd -> ClpGcmSivArmBackend / TGcmSivArmBackend
- ClpAesFusedAeadSimd -> ClpAesFusedAeadArmBackend / TAesFusedAeadArmBackend
- ClpSalsaSimd -> ClpSalsaArmBackend / TSalsaArmBackend
- ClpChaChaSimd -> ClpChaChaArmBackend / TChaChaArmBackend
No behavior change on any target: only the never-compiled ARM branch is
removed; the x86 path and the scalar fallback are untouched. The ARM
build/detection infrastructure (CRYPTOLIB_ARM_SIMD/FORCE_NEON/FORCE_SVE in
CryptoLib.inc, and ClpArmSimdFeatures/ClpArmHwCapProvider) is intentionally
kept as the foundation for future ARM backends.
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