Skip to content

Fix typos in Vitis_ToolFlow.md #507

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Swag4Yolo wants to merge 1 commit into
base: 2025.2
Choose a base branch
from
Open

Fix typos in Vitis_ToolFlow.md #507

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions Getting_Started/Vitis/Vitis_ToolFlow.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -89,7 +89,7 @@ In the previous section chapter we created all the components required as a buil
Vitis uses the Vivado generated extensible hardware platform (XSA) and add software (SW) components and create an embedded platform **XPFM**.
XPFM = XSA + SW platform (Linux/Baremetal + boot components)

In this flow, the Vitis backend uses System Device Tree (SDT) generator, Yocto/PetaLinux and Lopper to deliver the SW compoenents.
In this flow, the Vitis backend uses System Device Tree (SDT) generator, Yocto/PetaLinux and Lopper to deliver the SW components.

```mermaid
graph TD;
Expand Down Expand Up @@ -155,7 +155,7 @@ Vitis Tool: Detailed summary of available Vitis tools and its usages
| Vitis HLS | ☒ | ☑ | ☒ | To create PL kernels using C/C++ files |
| AI Engine Tools | &#x2612; | &#x2612; | &#x2611; | Vitis AIE compiler, x86sim, and aiesimulator for AI Engine designing. <br> **Vitis AIE compiler** uses AI Engine targeted C/C++ source files to output libadf.a (AIE Kernels). <br> **x86sim** is the functional simulator for AI Engines that helps to test, debug, and verify the functionality. <br> **aiesimulator** simulates a cycle approximate SystemC model of AI Engine. |
| Vitis Linker | &#x2612; | &#x2611; | &#x2611; | Works on existing platform and provides connection between AI Engine, PL and NoC. Also takes care of clock connections and data width conversions. |
| Vitis Packager | &#x2611; | &#x2611; | &#x2611; | Pack all necessaey hardware and software components and also to configure boot of the device |
| Vitis Packager | &#x2611; | &#x2611; | &#x2611; | Pack all necessary hardware and software components and also to configure boot of the device |
| Hardware Emulation | &#x2611; | &#x2611; | &#x2611; | To simulate the PS+PL+AIE, where PS gets simulated using QEMU and PL and AIE with simulators like XSIM |
| Vitis Analyzer | &#x2612; | &#x2611; | &#x2611; | Helps to review and debug the AI Engine and PL targetted output files |

Expand Down