Fix two syn correctness bugs#10755
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Signed-off-by: Martin Povišer <povik@cutebit.org>
Signed-off-by: Martin Povišer <povik@cutebit.org>
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Code Review
This pull request updates the elaboration and target import flow to correctly handle macro cell connections when the Verilog instantiation port order does not match the Liberty definition. It introduces port-name-based mapping using offset maps, adds robust validation for port existence and width mismatches, and includes a new integration test with a dummy RAM macro. Additionally, elaborateText now accepts an optional sta::dbSta pointer, and combinational mapping tests are updated. The review feedback suggests replacing C-style casts with static_cast in import.cc to improve type safety and adhere to modern C++ standards.
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@codex review |
seems familiar from a PR from @hzeller |
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2 participants
Summary
Fix omitted mapping for feedthrough inverters, and port order confusion if both
.liband.svsupply competing definitions for a given macroType of Change
Impact
Verification
./etc/Build.sh).Related Issues
Fixes #10745 #10746 #10747