dbSta: keep top-level supply ports visible in pin iterator (#10414)#10723
dbSta: keep top-level supply ports visible in pin iterator (#10414)#10723saurav-fermions wants to merge 2 commits into
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…OAD-Project#10414) write_verilog stopped emitting the "assign <port> = <net>;" aliases that connect power/ground ports to an internal supply net whose name differs from the port name. This dropped the only representation of those connections in the Verilog netlist and broke LVS, even though the DB and DEF export were correct. Root cause: commit "dbsta: skip supply nets when iterating over pins" added supply-pin filtering to the top-instance branch of DbInstancePinIterator::hasNext(). The Verilog writer's writeAssigns() walks the top instance's pins to emit port/net aliases, so once supply BTerms were filtered out it never saw the power/ground ports and emitted no assigns. Fix: restore the pre-regression behavior of the top-instance branch so top-level block ports (the design's primary I/O, including power/ground pins) stay visible. Leaf instance iterm filtering is unchanged. Adds dbSta regression test write_verilog10 (two power ports + two ground ports each tied to a single supply net with a mismatched name) which fails before this change (no assigns emitted) and passes after. Signed-off-by: Saurav Singh <saurav.singh@fermions.co>
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Code Review
This pull request modifies DbInstancePinIterator::hasNext() in dbNetwork.cc to retain power and ground supply boundary terms (BTerms) for the top-level block. This ensures top-level ports remain visible to consumers like write_verilog, which requires them to emit the correct assign statements connecting ports to internal supply nets with different names, fixing issue #10414. Additionally, a new test case write_verilog10 has been added to verify this fix. There are no review comments, so I have no feedback to provide.
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Needs fixed |
Move the write_verilog10 file-deps entry after write_verilog1 to satisfy buildifier's unsorted-dict-items check (BUILD:290). Addresses @maliberty review on The-OpenROAD-Project#10723. Signed-off-by: Saurav Singh <saurav.singh@fermions.co>
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Fixed — moved the |
dsengupta0628
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This is partial revert of the change by @gadfort #8957
Bug Peter's PR fixed: power/ground nets connected to leaf instances whose LEF does not mark pins as POWER/GROUND (real case: COVER BUMP cells with INOUT pins). OpenSTA then builds a timing graph over those supply nets --> memory blows. Fix: added isPGSupply() and filtered supply terms out of 4 iterators:
- DbInstancePinIterator - top branch (BTerms)
- DbInstancePinIterator - leaf branch (ITerms)
- DbNetPinIterator
- DbNetTermIterator
What PR #10723 reverts
Only 1 from above--> the top-level BTerm branch. Other 3 filters stay.
The memory blowup likely came from leaf instance ITerms (COVER BUMP cells) : that path (2, 3) stays filtered. This PR only re-exposes top-level primary I/O ports, a different code path.
Now exposing top supply BTerms could let OpenSTA add graph vertices/edges at the top boundary for supply nets. But the heavy blowup in Peter's case was leaf-instance traversal, not top ports so maybe unlikely to reproduce #8957's symptom. I would still prefer this to be verified.
Another concern. After this PR,
- DbInstancePinIterator (top branch) --> supply BTerm visible
- DbNetTermIterator::next() + DbNetPinIterator --> supply BTerm/ITerm still filtered
Same supply BTerm now appears when you walk the top instance's pins but is hidden when you walk its net's terminals. Any consumer that cross-references pins to net-terms assumes symmetry --> could mismatch.
write_verilog likely fine (it walks instance pins to emit assigns), but please confirm no other consumer of DbInstancePinIterator (e.g. graph builder, sta sdc, parasitics) chokes on supply ports reappearing.
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Summary
write_verilog -include_pwr_gndstopped emittingassign <port> = <net>;for top-level supply ports wired to an internal supply net of a different name (e.g.vccd1/vccd2->vdpwr), breaking LVS. This keeps top-level supply ports visible in the pin iterator so the assigns are restored.Type of Change
Impact
Power/ground port connections reappear in written Verilog; fixes the LVS breakage.
Verification
ctest -R '^dbSta\.'71/71.Related Issues
Fixes #10414
Developed with SAIGE, Fermions' autonomous RTL/EDA debugging agent; root-caused, tested, and signed off by the submitter (@saurav-fermions).