- RV32I Zicsr ISA
- Single-core single-cycle CPU
- Interruption subsystem
- Load-Store Unit (LSU)
- Control and Status Registers unit (CSR)
- Peripheral device support
Shuregg/riscv-simple-cpu
Folders and files
| Name | Name | Last commit date | ||
|---|---|---|---|---|
| Name | Name | Last commit date | ||
|---|---|---|---|---|