Create PMLL.py

[drQedwards]

Concept
Description
Memory Line
A single experience vector: {key, value, context, timestamp, recency, novelty, similarity} Anchor Chain
64-bit BLAKE2 hash linking consecutive lines: anchorₙ = hash(anchorₙ₋₁ ⊕ key ⊕ value ⊕ ctx) Race / Trace
Dual process: Race runs parallel candidate updates; Trace commits the winning anchor and decays others. Concert Heuristic
Weighted tri-blend controlling bias output: α (recency) + β (similarity) + γ (novelty) ΔW Overlay
Optional low-rank weight delta applied to LM head or attention projection

[drQedwards]

🧠 Persistent Memory Logic Loop (PMLL)

Extended Technical Overview — v2.0.0 (October 2025)

Author: Dr. Josef Kurk Edwards (Dr. Q) & John Trompeter
License: MIT — for research and reproducibility

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1. Purpose

The Persistent Memory Logic Loop is a plug-in memory architecture for transformers and reasoning systems.
It replaces transient KV-cache behavior with a persistent lattice of hashed “memory lines,” enabling models to remember, revise, and reason recursively without retraining.

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2. Core Concepts

Concept	Description
Memory Line	A single experience vector: {key, value, context, timestamp, recency, novelty, similarity}
Anchor Chain	64-bit BLAKE2 hash linking consecutive lines: anchorₙ = hash(anchorₙ₋₁ ⊕ key ⊕ value ⊕ ctx)
Race / Trace	Dual process: Race runs parallel candidate updates; Trace commits the winning anchor and decays others.
Concert Heuristic	Weighted tri-blend controlling bias output: α (recency) + β (similarity) + γ (novelty)
ΔW Overlay	Optional low-rank weight delta applied to LM head or attention projection.

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3. Mathematical Heuristics

Recency Decay

r_i = e^{-(t_now - t_i)/τ}

with default τ = 6 hours.

Novelty

n_i = 1 - max_j sim(k_i, k_j)

Composite Weight

w_i = αr_i + βs_i + γn_i
b = Σ w_i v_i / Σ w_i

Defaults: α = 0.35, β = 0.50, γ = 0.08, similarity floor = 0.15.

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4. System Architecture

        ┌──────────────┐
        │ Transformer  │
        │ (HF / Nano)  │
        └──────┬───────┘
               │ query_vec
               ▼
      ┌────────────────────┐
      │ PMLL Service       │
      │  • LMDB + FAISS    │
      │  • Anchor Chain    │
      └────────────────────┘
               │ bias_vector / ΔW
               ▼
        ┌──────────────┐
        │ RTM Controller│
        │ (PLAN→REFLECT)│
        └──────────────┘

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5. API Endpoints (local mode)

put(key, value, ctx, prev_anchor=None) → anchor

Stores a new vector pair with context. Automatically computes similarity and novelty.

query(query_vec, k=5) → List[MemoryLine]

Retrieves top-k entries by cosine similarity and recency decay.

bias_vector(query_vec, k=5) → np.ndarray

Aggregates weighted values for logit-bias or adapter injection.

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6. Integration Patterns

HF Transformers (Logits Bias)

logits += alpha * pmll.bias_vector(hidden[-1])

LoRA Adapter (ΔW Overlay)

delta = pmll.bias_vector(q)
W_eff = W_base + beta * low_rank(delta)

Controller Loop (Recursive RTM)

y, anchor = model.step(x)
pmll.put(x, y, {"stage": "reflect"})

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7. Storage Options

Backend	Use Case	Notes
JSON (default)	Rapid prototyping	Human-readable, slower for >10⁴ lines
LMDB	Embedded cache	Fast key/value persistence
DuckDB	Analytical mode	Enables temporal queries, joins
Faiss/ScaNN	Vector index	Accelerates nearest-neighbor lookup

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8. Security & Integrity

• Anchors use BLAKE2b-64 hash chains for tamper detection.
• Each session can export seal.json containing final anchor and FNV-1a/64 checksum.
• Optional AES or libsodium encryption layer (pmll_secure.py) for sensitive memory.

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9. Future Extensions

Module	Description	ETA
pmll_server.py	gRPC service for remote RTM calls	Q4 2025
pmll_graphiti.py	Neo4j / GraphRAG adapter	Q1 2026
pmll_cuda.cu	GPU-accelerated similarity kernel	Q2 2026
pmll_visualizer.ipynb	Grafana / Plotly dash for recency & novelty	Q1 2026

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10. Example Session

$ python3 PMLL.py
Anchor A: ed1f79b3c2a19d42
Queried 1 memory lines.
Bias Vector: [0.18 -0.02 … 0.33]

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11. References

1. Edwards & Trompeter (2025) Persistent Memory Logic Loop Architecture: Memory Footprint Reduction in Large Language Models — TechRxiv.
2. Edwards (2025) The Recursive Transformer Model: Architecture, Theory, and Implementation with Persistent Memory Logic Loops — ResearchGate.
3. Edwards et al. (2025) Hybrid TRM–RTM Controller Integration — ESS Open Archive.

[drQedwards]

Please see
karpathy/nanochat#89 (comment)

in Karparthy’s nano project for a different context example of this logic loop in recursive implementations for models!