[MOD-16730] Fix SIGSEGV in FP32/L2 SSE kernel: unaligned load in residual-3 path

[dor-forer]

Describe the changes in the pull request

Fix a SIGSEGV in the FP32/L2 SSE distance kernel. The residual % 4 == 3 path of FP32_L2SqrSIMD16_SSE used _mm_loadr_ps, which compiles to movaps and requires a 16-byte-aligned address. Vectors are never guaranteed that alignment: VecSimAllocator::allocate() returns malloc + 8 (allocation header), and the dispatcher only sets an alignment hint when dim % 4 == 0 — while this path requires dim % 4 == 3. On machines whose dispatcher selects the SSE tier (no AVX), any FP32/L2 query with dim % 16 ∈ {3, 7, 11, 15} crashed inside VecSimIndex_TopKQuery.

The fix replaces the reversed aligned load with an unaligned load + in-register reverse shuffle (_mm_loadu_ps + _mm_shuffle_ps(v, v, _MM_SHUFFLE(0,1,2,3))). Register contents are identical to the old _mm_loadr_ps, so the _mm_move_ss masking trick and all results are unchanged; at machine level this swaps movaps for movups with the same shufps the compiler already emitted — zero added instructions (verified by disassembly). _mm_blend_ps was rejected (SSE4.1; this TU compiles with -msse for pre-SSE4.1 hardware). Setting the alignment hint was rejected (it aligns allocation bases only; stride dim*4 ≡ 12 (mod 16) keeps 3 of 4 vectors misaligned regardless).

Includes a regression test that feeds the kernel buffers at the allocator's exact placement (16-aligned base + 8): segfaults on the previous kernel (reproduced locally and in CI on #987), passes with this fix. All FP32 spaces optimization tests pass with exact equality vs. the scalar baseline.

Which issues this PR fixes

1. MOD-16730
2. Crash demonstration / CI evidence: [MOD-16730] Repro: SIGSEGV in FP32/L2 SSE kernel (_mm_loadr_ps on unaligned allocator-placed vectors) #987; found while reviewing [MOD-16688] x86 distance kernels: multi-accumulator unrolling + SIMD for smaller dimensions #984

Main objects this PR modified

1. src/VecSim/spaces/L2/L2_SSE_FP32.h — FP32_L2SqrSIMD16_SSE residual % 4 == 3 load path
2. tests/unit/test_spaces.cpp — new regression test SpacesTest.FP32_L2Sqr_SSE_misaligned_residual3

Mark if applicable

• This PR introduces API changes
• This PR introduces serialization changes

---

Note

Medium Risk
Touches the FP32 L2 SIMD hot path used during TopK search, but the change is narrowly scoped to one residual branch and is guarded by a targeted regression test with exact scalar equality.

Overview
Fixes a SIGSEGV in the FP32 L2 SSE distance kernel when vectors are not 16-byte aligned—a common case for allocator placement and dimensions where dim % 4 != 0.

In FP32_L2SqrSIMD16_SSE, the residual % 4 == 3 prologue no longer uses _mm_loadr_ps (movaps). It now uses _mm_loadu_ps plus an in-register shuffle and zeroing so only the three valid lanes contribute to the partial sum, matching the prior masking behavior without requiring alignment. diff is computed inside each residual branch instead of after the pointer bump.

Adds SpacesTest.FP32_L2Sqr_SSE_misaligned_residual3 (dim 19, buffers at 16-aligned base + 8) to assert the SSE implementation matches the scalar FP32_L2Sqr baseline on misaligned data.

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[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 97.10%. Comparing base (45daaf3) to head (9795480).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #990      +/-   ##
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- Coverage   97.12%   97.10%   -0.02%     
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  Files         141      141              
  Lines        8164     8179      +15     
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+ Hits         7929     7942      +13     
- Misses        235      237       +2     

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[GuyAv46]

Consider shuffling v1 and v2 together, to get the _mm_move_ss effect in 1 operation instead of 3