[None][perf] Router GEMM: Triton GEMV + CuTe DSL gate GEMM - #17451
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[None][perf] Router GEMM: Triton GEMV + CuTe DSL gate GEMM#17451brb-nv wants to merge 5 commits into
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…plit-K The router keeps its weight in fp32 to match SGLang, but cuBLAS has no good path for that at decode shapes. For [4, 6144] x [6144, 128] it picks a 32-way split-K TF32 kernel plus a splitKreduce, and the fp32 activation it wants costs a separate cast of the bf16 hidden states first. Three kernels on the serial chain ahead of the expert GEMMs, and the TF32 tensor cores round both operands to a 10-bit mantissa on the way in -- so the stated intent is not being met today either. Nothing in the tree could be reused: dsv3_router_gemm_op hard-codes 256 experts, so M3's 128 reach its cuBLAS fallback, and both it and tinygemm2 require a bf16 weight, which is the one thing an fp32 router cannot concede. This is a GEMV band instead. One CTA per expert reduces over the hidden dimension with plain fp32 FMA, widening the bf16 activation in-register, so the cast disappears, there are no partials to reduce, and the multiply keeps the full fp32 mantissa. tl.sum over an fp32 product rather than tl.dot, which would put it back on the tensor cores and reintroduce the TF32 rounding. Measured on B200 at 128 experts / 6144 hidden against the full cuBLAS sequence: 3.32x at 4 tokens, 1.53x at 16. Past 16 tokens cuBLAS wins and the call falls back to F.linear, so prefill is unchanged. Numerics move, and toward the reference: this is the first version of the gate that is actually fp32, so it wants an eval rather than a bitwise comparison. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Times the GEMV against the full cuBLAS sequence it replaces -- the bf16->fp32 cast, the TF32 split-K GEMM and the splitKreduce -- across the token range, so the fallback threshold is set from measurement rather than assumed. Also reports cuBLAS with TF32 disabled, which is what establishes that the deployed router really is running on TF32 tensor cores despite intending fp32. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
The router multiplies bf16 hidden states by an fp32 weight. cuBLAS cannot take those two dtypes together, so the model casts the activation to fp32 first -- at 16k tokens that materializes a 400MB temporary and then feeds a CUDA-core SGEMM, and between them they run at about 4% of what the memory system can deliver. This kernel hands the bf16 activation straight to the tensor cores and puts the precision back on the weight side, where it is cheap: the fp32 weight is rewritten as a sum of two bf16 terms, each holding what the previous rounding threw away, and the GEMM accumulates both into one fp32 accumulator. Two terms buy about 16 mantissa bits, 67x better than the TF32 path; a third was measured and buys only 1.5x more, because past that point the accumulation order dominates. Landed unwired on purpose. It is the large-batch counterpart to the decode GEMV, which covers up to 16 tokens, and the dispatch between them belongs in a separate change alongside the load-time weight split. Nothing imports it yet, so there is no call site to review here -- only the kernel, its runner, an FP64-referenced correctness test and the tuning harness the tile and split-K defaults came from. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
The kernel and its runner landed unwired. Expose them the way every other CuTe DSL kernel here is exposed -- a custom op with a fake, inside the IS_CUTLASS_DSL_AVAILABLE guard -- so the model can reach it without making nvidia-cutlass-dsl a hard dependency, and so a traced graph sees one opaque node rather than a kernel it cannot trace through. The op is functional, so it needs no inplace_info entry. is_supported and the load-time weight split are re-exported alongside it for callers that would rather test the geometry than catch an exception on the hot path, matching the indexer scorer. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
…ernels The GEMV covers the decode band it was shaped for and the gate GEMM takes everything above it, leaving cuBLAS only the shapes neither claims. The crossover sits at MAX_GEMV_TOKENS, which is where the GEMV's register tile stops paying: the activation block is BLOCK_M x BLOCK_K, so past 16 tokens BLOCK_K shrinks faster than the extra rows earn back. Both branches turn on shape alone, so a captured graph keeps whichever kernel it was captured with. The gate GEMM wants the fp32 router weight rewritten as stacked bf16 terms; that is done once at load, and costs a second copy of a 3MB per-layer weight. Where the CuTe DSL package is missing there is no split weight and the wide band falls back bitwise to what the model did before. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
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