This repository contains my academic RTL design and simulation projects that I successfully completed at University College Dublin, earning perfect grades for originality and fulfilment of all system requirements. It also contains my solutions to numerous online RTL design and simulation challenges. I'll keep updating the repository as I complete new exercises. The aim of this repo (like my other FPGA repos) is to reference past designs built predominantly from scratch for learning purposes.
MUDAL/Personal_FPGA_Reference_Designs
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