riscv: allow Zfa fli.d on RV32

[carlosqwqqwq]

Fixes #278

riscv: allow Zfa fli.d on RV32

Commit message

riscv: allow Zfa fli.d on RV32

fli.d is defined by the Zfa extension whenever the D extension is
implemented, on both RV32 and RV64. The 0xF2000000 decode block gated
both fmv.d.x (RV64-only) and fli.d behind vm->rv64, so RV32 machines
raised an illegal-instruction exception for every legal fli.d.

Handle fli.d (rs2=1) unconditionally and keep the vm->rv64 gate only
on fmv.d.x (rs2=0).

Description

src/cpu/riscv_fpu.c, case 0xF2000000UL: move the fli.d branch out of the vm->rv64 check. fmv.d.x remains gated to RV64. No other decode path changes.

Validation

• RV32 guest (rv32imafdc_zfa) probe with fli.d 1.0/fli.d 2.0/fli.s/fadd.s: patched RVVM output bit-identical to QEMU qemu-riscv32 -cpu max.
• RV64 regression: fli.d/fround.d/fcvtmod probes byte-identical to pre-patch RV64 runs.