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feat: add support for risc-v #39

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23 changes: 19 additions & 4 deletions app/perfregisterinfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,8 @@ const int PerfRegisterInfo::s_numRegisters[PerfRegisterInfo::ARCH_INVALID][PerfR
{ 0, 0},
{ 0, 0},
{ 9, 17},
{ 0, 0},
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@milianw milianw May 29, 2025

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here and below: the indentation looks off - is this really correct?

{32, 32},
};

const int PerfRegisterInfo::s_wordWidth[PerfRegisterInfo::ARCH_INVALID][PerfRegisterInfo::s_numAbis] = {
Expand All @@ -41,6 +43,8 @@ const int PerfRegisterInfo::s_wordWidth[PerfRegisterInfo::ARCH_INVALID][PerfRegi
{0, 0},
{0, 0},
{4, 8},
{0, 0},
{4, 8},
};

// Perf and Dwarf register layouts are the same for ARM and ARM64
Expand All @@ -59,6 +63,9 @@ static int x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23, 8
static int mips[] = { 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31};

static int riscv[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};

static int none[] = {0};

const int *PerfRegisterInfo::s_perfToDwarf[PerfRegisterInfo::ARCH_INVALID][PerfRegisterInfo::s_numAbis] = {
Expand All @@ -70,14 +77,15 @@ const int *PerfRegisterInfo::s_perfToDwarf[PerfRegisterInfo::ARCH_INVALID][PerfR
{none, none },
{x86, x86_64 },
{mips, mips },
{riscv, riscv },
};

const int PerfRegisterInfo::s_perfIp[ARCH_INVALID] = {
15, 32, 0xffff, 0xffff, 0xffff, 0xffff, 8
15, 32, 0xffff, 0xffff, 0xffff, 0xffff, 8, 0xffff, 0
};

const int PerfRegisterInfo::s_perfSp[ARCH_INVALID] = {
13, 31, 0xffff, 0xffff, 0xffff, 0xffff, 7
13, 31, 0xffff, 0xffff, 0xffff, 0xffff, 7, 0xffff, 2
};

const int PerfRegisterInfo::s_dwarfLr[ARCH_INVALID][s_numAbis] = {
Expand All @@ -87,7 +95,9 @@ const int PerfRegisterInfo::s_dwarfLr[ARCH_INVALID][s_numAbis] = {
{0xffff, 0xffff},
{0xffff, 0xffff},
{0xffff, 0xffff},
{0xffff, 0xffff}
{0xffff, 0xffff},
{0xffff, 0xffff},
{1, 1}
};

const int PerfRegisterInfo::s_dwarfIp[ARCH_INVALID][s_numAbis] = {
Expand All @@ -97,7 +107,9 @@ const int PerfRegisterInfo::s_dwarfIp[ARCH_INVALID][s_numAbis] = {
{0xffff, 0xffff},
{0xffff, 0xffff},
{0xffff, 0xffff},
{8, 16}
{8, 16},
{0xffff, 0xffff},
{0, 0}
};

const int PerfRegisterInfo::s_dummyRegisters[ARCH_INVALID][2] = {
Expand Down Expand Up @@ -158,5 +170,8 @@ PerfRegisterInfo::Architecture PerfRegisterInfo::archByName(const QByteArray &na
if (name.startsWith("mips"))
return ARCH_MIPS;

if (name.startsWith("risc"))
return ARCH_RISCV;

return ARCH_INVALID;
}
8 changes: 5 additions & 3 deletions app/perfregisterinfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@
class PerfRegisterInfo
{
public:
enum Architecture {
enum Architecture
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@milianw milianw May 29, 2025

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unrelated?

{
ARCH_ARM = 0,
ARCH_AARCH64,
ARCH_POWERPC,
Expand All @@ -34,18 +35,19 @@ class PerfRegisterInfo
ARCH_SPARC,
ARCH_X86,
ARCH_MIPS,
ARCH_RISCV,
ARCH_INVALID
};

static const int s_numAbis = 2; // maybe more for some archs?

static Architecture archByName(const QByteArray &name);
static Architecture archByName(const QByteArray& name);
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@milianw milianw May 29, 2025

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unrelated?

static const int s_numRegisters[ARCH_INVALID][s_numAbis];
static const int s_wordWidth[ARCH_INVALID][s_numAbis];

// Translation table for converting perf register layout to dwarf register layout
// This is specific to ABI as the different ABIs may have different numbers of registers.
static const int *s_perfToDwarf[ARCH_INVALID][s_numAbis];
static const int* s_perfToDwarf[ARCH_INVALID][s_numAbis];
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@milianw milianw May 29, 2025

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unrelated?


// location of IP register or equivalent in perf register layout for each arch/abi
// This is not specific to ABI as perf makes sure IP is always in the same spot
Expand Down