simple-5-stage-pipeline-processor-design-VERILOG

a simple design for 5 stage pipeline processor created for few combinations

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
ControlUnit.v		ControlUnit.v
DataMem.v		DataMem.v
Exp 2 ALUs.v		Exp 2 ALUs.v
Exp 2 FA and MUX8_1.v		Exp 2 FA and MUX8_1.v
Exp 3 Decoders and RegFile.v		Exp 3 Decoders and RegFile.v
Exp 3 REG32 and MUX32_1.v		Exp 3 REG32 and MUX32_1.v
Exp6 modules.v		Exp6 modules.v
Exp7 modules.v		Exp7 modules.v
Exp8 modules.v		Exp8 modules.v
Exp9 module.v		Exp9 module.v
Instruction_memory.v		Instruction_memory.v
LICENSE		LICENSE
Library439.v		Library439.v
Processor_CH.v		Processor_CH.v
README.md		README.md
pipeline_test.v		pipeline_test.v

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