[AMDGPU] Perf: set force-vector-interleave=8 in JIT pipeline#772
[AMDGPU] Perf: set force-vector-interleave=8 in JIT pipeline#772paveltc wants to merge 4 commits into
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paveltc
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Co-authored-by: Cursor <cursoragent@cursor.com>
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| struct AMDGPUSetLoopInterleavePass | ||
| : public llvm::PassInfoMixin<AMDGPUSetLoopInterleavePass> { |
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AGENTS.md requires minimizing contact area for new/experimental features; this AMDGPU-specific pass is defined in the shared llvm_context_pass.h outside the AMDGPU guard, so every CPU/CUDA LLVM include site now compiles and depends on the new LoopInfo/LoopPassManager code even though only jit_amdgpu.cpp registers it. Please keep the pass private to the AMDGPU JIT file, or at least under QD_WITH_AMDGPU, to avoid expanding the common LLVM surface area for this backend knob.
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Good call — fixed in the latest push. I moved AMDGPUSetLoopInterleavePass out of the shared llvm_context_pass.h and into an anonymous namespace in jit_amdgpu.cpp (its only user), under the existing QD_WITH_AMDGPU guard, with the LoopInfo/LoopPassManager includes local to that file. The common LLVM header no longer pulls in this backend-specific pass, so CPU/CUDA include sites are unaffected. Pure relocation — the pass logic and pipeline registration are unchanged. Rebuilt clean on the ROCm image (AMDGPU + CPU/CUDA include sites) and re-ran a loop-kernel smoke test on MI300X (exact match); the prior full not slow run still stands since codegen is identical.
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Move AMDGPUSetLoopInterleavePass out of the shared llvm_context_pass.h and into an anonymous namespace in jit_amdgpu.cpp (its only user), under the existing QD_WITH_AMDGPU guard, with the LoopInfo/LoopPassManager includes local to that translation unit. This keeps the common LLVM header free of backend-specific code so CPU/CUDA include sites no longer compile or depend on it. Pure relocation: pass logic and pipeline registration are unchanged. Co-authored-by: Cursor <cursoragent@cursor.com>
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| #include "llvm/Transforms/IPO.h" | ||
| #include "llvm/IR/Instructions.h" | ||
| #include "llvm/IR/IRBuilder.h" | ||
| #include "llvm/IR/Metadata.h" |
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do we still need these header changes?
| #if defined(QD_WITH_AMDGPU) | ||
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| namespace { | ||
| // New-PM loop pass: annotates innermost loops with llvm.loop.interleave.count |
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comments should be 120c wrapped, not 80c wrapped
| pb.registerLoopAnalyses(lam); | ||
| pb.crossRegisterProxies(lam, fam, cgam, mam); | ||
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| // Annotate innermost loops with interleave-count=8 via IR metadata so the |
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| pb.registerLoopOptimizerEndEPCallback( | ||
| [](llvm::LoopPassManager &lpm, llvm::OptimizationLevel) { | ||
| lpm.addPass(AMDGPUSetLoopInterleavePass(8)); | ||
| }); |
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When print_kernel_amdgcn is enabled, the earlier dump path builds and runs a separate PassBuilder for module_clone without this callback, while the HSACO path below does get the interleave metadata. That means the emitted quadrants_kernel_amdgcn_*.gcn no longer represents the code being linked for this perf change, which can mislead AMDGPU tuning/debugging; register the same callback on the clone pipeline or share a helper.
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| #include "llvm/Analysis/LoopInfo.h" | ||
| #include "llvm/Transforms/Scalar/LoopPassManager.h" |
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The repo AGENTS.md asks reviewers to flag unnecessary contact area, and these loop-pass headers are only needed by the private AMDGPU pass in jit_amdgpu.cpp where they are already included. Since llvm_context_pass.h is included by common/CPU/CUDA code too, adding these dependencies expands the rebuild and dependency surface for unrelated backends; keep them local to the AMDGPU translation unit.
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…dump - Remove AMDGPU-only includes (Metadata.h, LoopInfo.h, LoopPassManager.h) from the shared llvm_context_pass.h; they are only needed by the private pass in jit_amdgpu.cpp, which already includes them. Keeps the common LLVM header off CPU/CUDA include sites. - Rewrap the loop-interleave comments to 120 columns. - Register the interleave pass on the print_kernel_amdgcn dump pipeline via a shared register_loop_interleave() helper so the emitted .gcn matches the linked HSACO object. pre-commit run -a passes (black, clang-format, ruff, pylint, whitespace).
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Thanks for the reviews — addressed all the open comments in the latest push: @hughperkins — "do we still need these header changes?" / @codex P3 (AMDGPU-only includes in shared header) Removed the three includes this PR had added to llvm_context_pass.h (llvm/IR/Metadata.h, llvm/Analysis/LoopInfo.h, llvm/Transforms/Scalar/LoopPassManager.h). They were only needed by the pass, which now lives entirely in jit_amdgpu.cpp (and already includes them). The shared header is back to its pre-PR state, so CPU/CUDA include sites no longer pull in the loop-pass headers. @hughperkins — 120c comment wrap Rewrapped both flagged comment blocks to 120 columns. @codex P2 — keep the GCN dump pipeline in sync. Factored the registration into a small register_loop_interleave(PassBuilder&) helper and now call it on both the HSACO pipeline and the print_kernel_amdgcn clone pipeline, so the emitted .gcn reflects the same interleave metadata as the linked object. @hughperkins — run pre-commit run -a Ran it repo-wide; all hooks pass (black, clang-format, trailing-whitespace, end-of-file, ruff, pylint) with only these two files touched. No change to the actual HSACO codegen — the only behavioral difference is the debug-only print_kernel_amdgcn dump path gaining parity with the linked pipeline; the rest is header/comment/formatting cleanup. |
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Codex Review: Didn't find any major issues. Breezy! Reviewed commit: ℹ️ About Codex in GitHubCodex has been enabled to automatically review pull requests in this repo. Reviews are triggered when you
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checklist:
Question: how can we measure the benefit of this PR? Is there some benchmarks you are running? What are those benchmarks? What the results of those benchmarks before/after this PR? |
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This PR improves the performance of latency-bound compute loops. I ran a small benchmark which showed a 2.6x speed up on such a loop. It improves the performance loops that are latency-bound and can be interleaved by LLVM. More specifically, the loops it helps on are those that are innermost and countable and have no complex internal control flow. Please let me know if you have any other questions. |
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Summary
Sets loop interleave count = 8 for the AMDGPU JIT pipeline. Instead of mutating process-wide LLVM command-line state, a small new-PM loop pass (AMDGPUSetLoopInterleavePass) annotates innermost loops with llvm.loop.interleave.count IR metadata; it's registered via registerLoopOptimizerEndEPCallback in compile_module_to_hsaco, so it's scoped to this compilation pipeline only. Vector interleaving lets the LLVM backend unroll/software-pipeline loops, keeping more functional units busy across the wider CDNA wavefronts. The value 8 matches the recommended setting for MI200/MI300 series. No correctness change.
The pass is defined privately in jit_amdgpu.cpp (anonymous namespace, under QD_WITH_AMDGPU) to keep the shared LLVM headers free of backend-specific code.
Verified with a full not slow test suite run on AMD MI300X with QD_AMDGPU_FORCE_PERMLANE64_FALLBACK=1: 4166 passed, 0 AMD-related failures (1 pre-existing flaky x64 timing test unrelated to this change).
Ported from ROCm#8.