HORNET-RV32IMF is an academic-grade, 5-stage pipelined RISC-V soft-core processor designed for high-efficiency floating-point arithmetic and Edge AI applications. It implements the RV32IMF Instruction Set Architecture (ISA) and is optimized for deployment across Xilinx Artix-7 platforms, including the Nexys Video and Nexys-4-DDR.
This project is the result of collaborative engineering at the Istanbul Technical University (ITU) and the GSTL Lab.
- Prof. Dr. Sıddıka Berna Örs Yalçın - ITU Academic Profile
- Salih Daysal
- Mehmet Emin Tuzcu
- Yusuf Tekin & Ahmet Tolga Özkan- 🔗 HORNET-RV32IMF-For-AI-Applications
The initial design of Hornet core is detailed in the following conference paper:
Y. S. Tozlu, Y. Yilmaz, B. Ors, “Design and Implementation Of a 32-Bit RISC-V Core”, 12th International Conference on Electrical and Electronics Engineering (ELECO), 2021.
The verification methodologies used in this core are detailed in the following conference paper:
D. Z. Eroglu, M. K. Ozden, B. Ors, “Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools”, 9th International Symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT), 2025.
| Parameter | Specification |
|---|---|
| ISA | RV32IMF (Integer, Multiply/Divide, Single-Precision Floating Point) |
| Pipeline | 5-Stage In-Order |
| FPU | IEEE-754 Single-Precision Hardware Unit |
| Max Frequency | 26.25 MHz (Target: Nexys-4-DDR & Nexys Video) |
| Interconnect | Wishbone |
| Peripherals | UART (Interrupt-driven), GPIO, MTIME, Debug Interface |
- Toolchain:
riscv32-unknown-elf-gcc(RV32IMF / ILP32F) - Simulation: Vivado Simulator / Verilator
- Python: 3.x (with
pyserialfor hardware-in-the-loop tests)
- FPGA: Nexys-4-DDR (Artix-7 100t) or Nexys Video (Artix-7 200t)
- Vivado Version: Verified on Vivado 2025.2
source/: RTL Verilog files for the core, FPU, and Wishbone peripherals.drivers/: Bare-metal C drivers for UART, GPIO, and Interrupt handling.test/: Comprehensive test suites including FPU arithmetic, Bubble Sort, and MLP Neural Network inference.rom_gen/: Custom tools to convert compiled binaries into FPGA-ready.memfiles.
- Generate Firmware: Navigate to
test/gpioortest/uart-fpu-fpgaand runmake build. - Synthesis: Load the
source/files into Vivado 2025.2. Ensure the generatedmemory_init.memis linked to the BRAM initialization. - Deploy: Program the Nexys-4-DDR and monitor the output via the USB-UART bridge (Baud: 115200).
For technical inquiries or bug reports, please open an issue in this repository or contact the organizers:
- Yusuf Tekin: tekiny20@itu.edu.tr - GitHub Profile
- Deniz Zakir Eroglu: eroglud20@itu.edu.tr - GitHub Profile
Developed at Istanbul Technical University. 🐝