feat: End-to-End eSim to OpenROAD Automation Bridge (UI + Backend)

[Divinesoumyadip]

Related Issues

Resolves the end-to-end flow requirement for the GSoC 2026 eSim-OpenROAD integration project.
Follows up on PR #467 (Netlist Validator) by adding the UI trigger and physical design handoff.

Purpose

Currently, transitioning from an eSim schematic to an OpenROAD-driven GDSII requires manual netlist-to-RTL conversion, manual config.mk creation, and manual terminal execution. The purpose of this PR is to completely automate this physical design handoff directly from the eSim GUI, fulfilling the "End-to-End Flow" requirement for ASIC design within eSim.

Approach

I Added a dedicated "OpenROAD-GDSII" QAction button to the left toolbar in the PyQt5 interface.I also Implemented a logic class that dynamically detects the active eSim workspace, extracts the project name, and validates the presence of the Ngspice netlist (.cir.out).Auto-generates the Verilog (.v) RTL file natively inside the active project folder. Also auto-generates the OpenROAD config.mk file, populating DESIGN_NAME, PLATFORM (sky130hd), and VERILOG_FILES.Utilizes Python's subprocess to natively trigger the make command targeting the local OpenROAD-flow-scripts (ORFS) directory.LastlyAdded checks to ensure the flow fails gracefully (with UI pop-ups and terminal notices) if the local ORFS environment or Makefile is missing, preventing hard crashes. Tested successfully on WSLg.