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[mppa] Add Mppa PMU counters
Add support for Mppa specific counters in the existing interface for PMU counters. These counters are extracted from the list of all counters, and processed separately. All counters are available in each KVX PE, so some post-processing is required to reduce the raw measured values. Several reduction functions are available, on both the PEs and clusters: - avg: average - min: minimum - max: maximum - sum: sum - <id>: select one specific cluster/PE id Host counters are still working. Only one csrcs perf_event function has been overridden, to enable Mppa counters by reseting previous values
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‎Makefile‎

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@@ -58,6 +58,7 @@ check-lit-nvgpu:
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check-lit-mppa:
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env XTC_MLIR_TARGET=mppa lit -v -j 1 tests/filecheck/backends/target_mppa
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env XTC_MLIR_TARGET=mppa lit -v -j 1 tests/filecheck/evaluation/test_matmul_pmu_counters_mppa.py
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check-pytest:
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scripts/pytest/run_pytest.sh -v

‎src/xtc/csrcs/runtimes/accelerator/mppa/perf_event_mppa.h‎

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/*
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* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2024-2026 The XTC Project Authors
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*/
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#ifndef __PERF_EVENT_MPPA_H__
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#define __PERF_EVENT_MPPA_H__
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#include "perf_event.h"
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#define mppa_OPEN_PERF_EVENT open_perf_event /* reuse host */
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#define mppa_READ_PERF_EVENT read_perf_event /* reuse host */
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#define mppa_CLOSE_PERF_EVENT close_perf_event /* reuse host */
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#define mppa_OPEN_PERF_EVENTS open_perf_events /* reuse host */
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#define mppa_ENABLE_PERF_EVENTS mppa_enable_perf_events
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#define mppa_CLOSE_PERF_EVENTS close_perf_events /* reuse host */
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#define mppa_RESET_PERF_EVENTS reset_perf_events /* reuse host */
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#define mppa_START_PERF_EVENTS start_perf_events /* reuse host */
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#define mppa_STOP_PERF_EVENTS stop_perf_events /* reuse host */
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#define mppa_GET_PERF_EVENT_CONFIG get_perf_event_config /* reuse host */
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#define mppa_PERF_EVENT_ARGS_DESTROY perf_event_args_destroy /* reuse host */
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extern void mppa_reset_perf_events();
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void mppa_enable_perf_events(int n_events, const int *fds) {
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mppa_reset_perf_events();
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enable_perf_events(n_events, fds);
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}
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#endif
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‎src/xtc/csrcs/runtimes/accelerator/mppa/perf_events.c‎

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/*
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* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2024-2026 The XTC Project Authors
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*/
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#include "host_structures.h"
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#include "mppa_management_host.h"
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#include <mppa_offload_host.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <stddef.h>
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#include <stdint.h>
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#define MAX_NB_PM_COUNTERS 8 /* value of _COS_PM_NB for Coolidge V2 */
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typedef struct {
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const char *name;
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int id;
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const char *description;
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} kvx_pm_counter_t;
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#define NB_COUNTERS_AVAILABLE 55
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static const kvx_pm_counter_t kvx_pm_counters[NB_COUNTERS_AVAILABLE] = {
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{ "PCC" , 0 /* _COS_PM_PCC */, "Processor Clock CycleSAT" },
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{ "ICC" , 1 /* _COS_PM_ICC */, "Idle Clock Cycle" },
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{ "EBE" , 2 /* _COS_PM_EBE */, "Executed Bundle Event" },
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{ "ENIE" , 3 /* _COS_PM_ENIE */, "Executed N Instructions Event" },
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{ "ENSE" , 4 /* _COS_PM_ENSE */, "Executed N Syllables Event" },
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{ "ICHE" , 5 /* _COS_PM_ICHE */, "I$ Hit Event" },
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{ "ICME" , 6 /* _COS_PM_ICME */, "I$ Miss Event" },
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{ "ICMABE" , 7 /* _COS_PM_ICMABE */, "I$ Memory Accesses Burst Event" },
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{ "MNGIC" , 8 /* _COS_PM_MNGIC */, "Memory Not Granting Instruction cache access Cycle" },
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{ "MIMHE" , 9 /* _COS_PM_MIMHE */, "MMU Instruction Micro-tlb Hit Event" },
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{ "MIMME" , 10 /* _COS_PM_MIMME */, "MMU Instruction Micro-tlb Miss Event" },
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{ "IATSC" , 11 /* _COS_PM_IATSC */, "Instruction Address Translation Stall Cycle" },
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{ "FE" , 12 /* _COS_PM_FE */, "Fetch Event" },
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{ "PBSC" , 13 /* _COS_PM_PBSC */, "Prefetch Buffer Starvation Cycle" },
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{ "PNVC" , 14 /* _COS_PM_PNVC */, "Pipeline No Valid Cycle" },
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{ "PSC" , 15 /* _COS_PM_PSC */, "Pipeline Starvation Cycle" },
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{ "TADBE" , 16 /* _COS_PM_TADBE */, "Taken Applicative Direct Branch Event" },
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{ "TABE" , 17 /* _COS_PM_TABE */, "Taken Applicative Branch Event" },
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{ "TBE" , 18 /* _COS_PM_TBE */, "Taken Branch Event" },
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{ "MDMHE" , 19 /* _COS_PM_MDMHE */, "MMU Data Micro-tlb Hit Event" },
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{ "MDMME" , 20 /* _COS_PM_MDMME */, "MMU Data Micro-tlb Miss Event" },
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{ "DATSC" , 21 /* _COS_PM_DATSC */, "Data Address Translation Stall Cycle" },
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{ "DCLHE" , 22 /* _COS_PM_DCLHE */, "D$ Load Hit Event" },
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{ "DCHE" , 23 /* _COS_PM_DCHE */, "D$ Hit Event" },
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{ "DCLME" , 24 /* _COS_PM_DCLME */, "D$ Load Miss Event" },
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{ "DCME" , 25 /* _COS_PM_DCME */, "D$ Miss Event" },
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{ "DARSC" , 26 /* _COS_PM_DARSC */, "Data Access Related Stall Cycle" },
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{ "LDSC" , 27 /* _COS_PM_LDSC */, "Load Dependency Stall Cycle" },
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{ "DCNGC" , 28 /* _COS_PM_DCNGC */, "Data Cache Not Granting Cycle" },
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{ "DMAE" , 29 /* _COS_PM_DMAE */, "Data Misaligned Access Event" },
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{ "LCFSC" , 30 /* _COS_PM_LCFSC */, "Load Cam Full Stall Cycle" },
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{ "MNGDC" , 31 /* _COS_PM_MNGDC */, "Memory Not Granting Data cache access Cycle" },
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{ "MACC" , 32 /* _COS_PM_MACC */, "Memory Accesses Conflict Cycle" },
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{ "TACC" , 33 /* _COS_PM_TACC */, "TLB Accesses Conflict Cycle" },
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{ "IWC" , 34 /* _COS_PM_IWC */, "Idle Wait Cycle" },
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{ "WISC" , 35 /* _COS_PM_WISC */, "Wait Instruction Stall Cycle" },
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{ "SISC" , 36 /* _COS_PM_SISC */, "Synchronization Instruction Stall Cycle" },
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{ "DDSC" , 37 /* _COS_PM_DDSC */, "Data Dependency Stall Cycle" },
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{ "SC" , 38 /* _COS_PM_SC */, "Stall Cycle" },
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{ "ELE" , 39 /* _COS_PM_ELE */, "Executed Load Event" },
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{ "ELNBE" , 40 /* _COS_PM_ELNBE */, "Executed Load N Bytes Event" },
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{ "ELUE" , 41 /* _COS_PM_ELUE */, "Executed Load Uncached Event" },
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{ "ELUNBE" , 42 /* _COS_PM_ELUNBE */, "Executed Load Uncached N Bytes Event" },
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{ "ESE" , 43 /* _COS_PM_ESE */, "Executed Store Event" },
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{ "ESNBE" , 44 /* _COS_PM_ESNBE */, "Executed Store N Bytes Event" },
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{ "EAE" , 45 /* _COS_PM_EAE */, "Executed Atomics Event" },
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{ "CIRE" , 46 /* _COS_PM_CIRE */, "Coherency Invalidation Request Event" },
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{ "CIE" , 47 /* _COS_PM_CIE */, "Coherency Invalidation Event" },
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{ "SE" , 48 /* _COS_PM_SE */, "Stop Event" },
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{ "RE" , 49 /* _COS_PM_RE */, "Reset Event" },
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{ "FSC" , 50 /* _COS_PM_FSC */, "Fetch Stall Cycle" },
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/* PMC available only on Coolidge V2 */
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{ "CPIRE" , 51 /* _COS_PM_CPIRE */, "Coherency Precise Invalidation Request Event" },
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{ "CPIE" , 52 /* _COS_PM_CPIE */, "Coherency Precise Invalidation Event" },
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{ "HUPEVICT" , 53 /* _COS_PM_HUPEVICT */, "Hit-Under-Prefetch Line Eviction Event" },
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{ "HUPHIT" , 54 /* _COS_PM_HUPHIT */, "Hit-Under-Prefetch Hit Event" },
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};
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void mppa_setup_perf_events(char* event_names[], int n_events) {
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assert(n_events <= MAX_NB_PM_COUNTERS);
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int counter_ids[MAX_NB_PM_COUNTERS] = {0};
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for (int i = 0; i < n_events; i++) {
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const char *event_name = event_names[i];
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int j = 0;
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for (j = 0; j < NB_COUNTERS_AVAILABLE; j++) {
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if (strcmp(event_name, kvx_pm_counters[j].name) == 0) {
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counter_ids[i] = kvx_pm_counters[j].id;
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break;
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}
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}
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if (j == NB_COUNTERS_AVAILABLE) {
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printf("Event %s not found in the list of available events\n", event_name);
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assert(false);
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}
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}
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// Call runtime function
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mppa_setup_pm_counters(counter_ids, n_events);
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}
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void mppa_read_perf_events_results(void* dst_handle) {
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mppa_copy_out_pm_counters_buffer(dst_handle);
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}
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void mppa_reset_perf_events() {
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mppa_reset_pm_counters_buffer();
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}
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// uint64_t mppa_get_frequency() already exists in the runtime, just need to call it

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