sync_preset_register.v

/**
 * Synchronous Preset Register
 * 
 * This module implements a register with multiple reset/preset options:
 * asynchronous reset, synchronous reset, and synchronous preset. This provides
 * flexible control over register initialization and state management.
 * 
 * Key Features:
 * - Asynchronous reset: Highest priority, resets to 0
 * - Synchronous reset: Second priority, resets to 0 on clock edge
 * - Synchronous preset: Third priority, sets to 1 on clock edge
 * - Enable control: Normal operation when enabled
 * - Priority ordering: Async reset > Sync reset > Sync preset > Enable
 * 
 * Reset/Preset Priority:
 * 1. Asynchronous reset (rst_n): Highest priority, immediate
 * 2. Synchronous reset (sync_rst): Second priority, clocked
 * 3. Synchronous preset (sync_preset): Third priority, clocked
 * 4. Enable (enable): Normal operation, lowest priority
 * 
 * Operation:
 * - Async reset: When rst_n is low, output is 0 (immediate, not clocked)
 * - Sync reset: When sync_rst is high, output is 0 (on next clock edge)
 * - Sync preset: When sync_preset is high, output is 1 (on next clock edge)
 * - Normal: When enable is high and no reset/preset, output follows input
 * 
 * Use Cases:
 * - State machines with multiple reset options
 * - Control registers with preset values
 * - Initialization sequences
 * - Error recovery
 * 
 * @param WIDTH Width of register (default: 8 bits)
 * 
 * @input clk Clock signal
 * @input rst_n Active-low asynchronous reset (highest priority)
 * @input sync_rst Synchronous reset (active high, second priority)
 * @input sync_preset Synchronous preset (active high, third priority)
 * @input enable Enable signal (high to update, lowest priority)
 * @input data_in[WIDTH-1:0] Data input
 * @output data_out[WIDTH-1:0] Register output
 */
module sync_preset_register #(
    parameter WIDTH = 8
)(
    input wire clk,                    // Clock input
    input wire rst_n,                  // Active low asynchronous reset
    input wire sync_rst,               // Synchronous reset (active high)
    input wire sync_preset,            // Synchronous preset (active high)
    input wire enable,                 // Enable signal
    input wire [WIDTH-1:0] data_in,    // Data input
    output reg [WIDTH-1:0] data_out    // Output data
);

    // Reset/preset value constants
    localparam [WIDTH-1:0] RESET_VAL = {WIDTH{1'b0}};
    localparam [WIDTH-1:0] PRESET_VAL = {WIDTH{1'b1}};

    // ============================================================================
    // Register Logic with Multiple Reset/Preset Options
    // ============================================================================
    // Implements priority-based reset/preset logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            // ====================================================================
            // Asynchronous Reset (Highest Priority)
            // ====================================================================
            // Asynchronous reset takes highest priority
            // Immediate reset, not dependent on clock edge
            data_out <= RESET_VAL;
        end else begin
            // ====================================================================
            // Synchronous Operations
            // ====================================================================
            // All synchronous operations occur on clock edge
            if (sync_rst) begin
                // ================================================================
                // Synchronous Reset (Second Priority)
                // ================================================================
                // Synchronous reset: resets to 0 on next clock edge
                // Takes priority over preset and enable
                data_out <= RESET_VAL;
            end else if (sync_preset) begin
                // ================================================================
                // Synchronous Preset (Third Priority)
                // ================================================================
                // Synchronous preset: sets to 1 on next clock edge
                // Takes priority over enable, but not over sync reset
                data_out <= PRESET_VAL;
            end else if (enable) begin
                // ================================================================
                // Normal Operation (Lowest Priority)
                // ================================================================
                // Normal register operation: output follows input
                // Only occurs when no reset/preset is active
                data_out <= data_in;
            end
            // ====================================================================
            // Hold Mode
            // ====================================================================
            // When enable is low and no reset/preset, register holds current value
            // (implicit: no assignment means value is maintained)
        end
    end

endmodule