shift_register_left.v

/**
 * Left Shift Register
 * 
 * This module implements a left shift register that shifts data from LSB to MSB.
 * It supports both serial and parallel operations, making it useful for serial
 * communication, data manipulation, and shift operations.
 * 
 * Key Features:
 * - Left shift operation: Data moves from LSB to MSB
 * - Serial input: New data enters at LSB position
 * - Serial output: Data exits from MSB position
 * - Parallel load: Load entire register in one cycle
 * - Parallel output: Access all bits simultaneously
 * 
 * Left Shift Operation:
 * - Data flow: LSB ← serial_in, MSB → serial_out
 * - Shift direction: Bits move left (toward MSB)
 * - MSB is shifted out: Available at serial_out
 * - New bit enters at LSB: From serial_in
 * 
 * Operation Modes:
 * - Load mode: When load is high, loads parallel_in
 * - Shift mode: When enable is high and load is low, shifts left
 * - Hold mode: When both enable and load are low, holds current value
 * 
 * Use Cases:
 * - Serial-to-parallel conversion
 * - Data alignment
 * - Multiplication by powers of 2
 * - Communication protocols
 * - Barrel shifter components
 * 
 * @param WIDTH Width of shift register (default: 8 bits)
 * 
 * @input clk Clock signal
 * @input rst_n Active-low reset signal
 * @input en Enable signal (high to shift)
 * @input load Load enable (high to load, takes priority over shift)
 * @input serial_in Serial data input (enters at LSB)
 * @input parallel_in[WIDTH-1:0] Parallel input data
 * @output serial_out Serial data output (exits from MSB)
 * @output parallel_out[WIDTH-1:0] Parallel output data
 */
module shift_register_left #(
    parameter WIDTH = 8
) (
    input wire clk,
    input wire rst_n,
    input wire en,
    input wire load,
    input wire serial_in,
    input wire [WIDTH-1:0] parallel_in,
    output wire serial_out,
    output reg [WIDTH-1:0] parallel_out
);

    // ============================================================================
    // Serial Output Assignment
    // ============================================================================
    // Serial output is MSB for left shift
    // MSB is the bit that exits during left shift operation
    assign serial_out = parallel_out[WIDTH-1];

    // ============================================================================
    // Shift Register Logic
    // ============================================================================
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            // ====================================================================
            // Reset State
            // ====================================================================
            // Reset all bits to zero
            parallel_out <= {WIDTH{1'b0}};
        end
        else if (load) begin
            // ====================================================================
            // Parallel Load Mode
            // ====================================================================
            // Load operation takes priority over shift
            // Load entire register from parallel input
            parallel_out <= parallel_in;
        end
        else if (en) begin
            // ====================================================================
            // Left Shift Operation
            // ====================================================================
            // Left shift - bits move left, MSB shifted out, new bit at LSB
            // Format: {existing_bits[WIDTH-2:0], new_bit}
            // Example: 0b1010 → 0b0101 (with serial_in=1)
            parallel_out <= {parallel_out[WIDTH-2:0], serial_in};
        end
        // ========================================================================
        // Hold Mode
        // ========================================================================
        // When both load and en are low, register holds current value
        // (implicit: no assignment means value is maintained)
    end

endmodule