scan_register.v

/**
 * Scan Register
 * 
 * This module implements a scan register that supports both normal operation
 * and scan chain operation for design-for-test (DFT) purposes. Scan chains
 * are essential for testing digital circuits by providing serial access to
 * internal flip-flops.
 * 
 * Key Features:
 * - Normal mode: Standard register operation (parallel load)
 * - Scan mode: Serial shift operation for test access
 * - Scan chain: Connects to other scan registers for full chain
 * - Test access: Allows observation and control of internal state
 * 
 * Operation Modes:
 * - Normal mode (scan_en=0): Loads data_in in parallel
 * - Scan mode (scan_en=1): Shifts data serially through scan chain
 * 
 * Scan Chain:
 * - scan_in: Serial input from previous scan register
 * - scan_out: Serial output to next scan register
 * - Shifts right: scan_in → ... → scan_out
 * 
 * Scan Testing:
 * - Allows shifting test patterns into registers
 * - Captures circuit state for observation
 * - Essential for stuck-at fault testing
 * - Industry standard DFT technique
 * 
 * Use Cases:
 * - Design-for-test (DFT) implementation
 * - Built-in self-test (BIST)
 * - Production testing
 * - Debug and diagnostics
 * 
 * @param WIDTH Width of register (default: 8 bits)
 * 
 * @input clk Clock signal
 * @input rst_n Active-low reset signal
 * @input data_in[WIDTH-1:0] Normal mode data input
 * @output data_out[WIDTH-1:0] Register output
 * 
 * @input scan_en Scan enable (1=scan mode, 0=normal mode)
 * @input scan_in Scan chain serial input
 * @output scan_out Scan chain serial output
 */
module scan_register #(
    parameter WIDTH = 8
)(
    input wire clk,
    input wire rst_n,
    
    // Normal operation
    input wire [WIDTH-1:0] data_in,
    output reg [WIDTH-1:0] data_out,
    
    // Scan chain operation
    input wire scan_en,      // Scan enable (1: scan mode, 0: normal mode)
    input wire scan_in,      // Scan input
    output wire scan_out     // Scan output
);

    // Internal scan chain registers
    reg [WIDTH-1:0] scan_reg;
    
    // Scan output is the last bit of the scan register
    assign scan_out = scan_reg[WIDTH-1];
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            scan_reg <= {WIDTH{1'b0}};
            data_out <= {WIDTH{1'b0}};
        end
        else begin
            if (scan_en) begin
                // ================================================================
                // Scan Mode
                // ================================================================
                // Shift scan chain: new bit enters at LSB, old LSB shifts out
                // This allows serial access to register contents for testing
                scan_reg <= {scan_reg[WIDTH-2:0], scan_in};
                // Also update data_out to reflect current scan register state
                // This allows observation of scan data during test
                data_out <= {scan_reg[WIDTH-2:0], scan_in};
            end
            else begin
                // ================================================================
                // Normal Mode
                // ================================================================
                // Load parallel data: standard register operation
                scan_reg <= data_in;
                // Output previous register value (registered output)
                data_out <= scan_reg;
            end
        end
    end

endmodule