parameterized_updown_counter.v

/**
 * Parameterized Up/Down Counter
 * 
 * This module implements a bidirectional counter that can count up or down based
 * on a control signal. It includes overflow/underflow detection and automatic
 * wraparound when limits are reached.
 * 
 * Key Features:
 * - Bidirectional: Counts up or down based on up_down signal
 * - Overflow detection: Flags when counter wraps around
 * - Automatic wraparound: Wraps to 0 when counting up past MAX_COUNT
 * - Wraps to MAX_COUNT when counting down past 0
 * - Configurable width and maximum count
 * 
 * Operation:
 * - Up counting: Increments until MAX_COUNT, then wraps to 0 and sets overflow
 * - Down counting: Decrements until 0, then wraps to MAX_COUNT and sets overflow
 * - Overflow flag: High for one cycle when wraparound occurs
 * 
 * Use Cases:
 * - Event counting (up/down based on conditions)
 * - Position tracking
 * - Frequency dividers
 * - Accumulators
 * 
 * @param WIDTH Counter width in bits (default: 4)
 * @param MAX_COUNT Maximum count value (default: 2^WIDTH - 1)
 * 
 * @input clk Clock signal
 * @input rst_n Active-low reset signal
 * @input enable Enable counting (high to count)
 * @input up_down Direction: 1 = count up, 0 = count down
 * @output count[WIDTH-1:0] Current counter value
 * @output overflow Overflow/underflow indicator (high for one cycle on wraparound)
 */
module parameterized_updown_counter #(
    parameter WIDTH = 4,
    parameter MAX_COUNT = (1 << WIDTH) - 1
)(
    input wire clk,
    input wire rst_n,        // Active low reset
    input wire enable,       // Enable signal
    input wire up_down,      // Direction control (1 for up, 0 for down)
    output wire [WIDTH-1:0] count,
    output wire overflow     // Overflow/underflow indicator
);

    // ============================================================================
    // Internal Registers
    // ============================================================================
    reg [WIDTH-1:0] counter_reg;  // Counter register
    reg overflow_reg;             // Overflow flag register
    
    // ============================================================================
    // Counter Logic
    // ============================================================================
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            // ====================================================================
            // Reset State
            // ====================================================================
            counter_reg <= {WIDTH{1'b0}};  // Reset to 0
            overflow_reg <= 1'b0;          // Clear overflow flag
        end else if (enable) begin
            // ====================================================================
            // Count Operation
            // ====================================================================
            // Clear overflow flag (will be set if wraparound occurs)
            overflow_reg <= 1'b0;
            
            if (up_down) begin
                // ================================================================
                // Count Up
                // ================================================================
                if (counter_reg == MAX_COUNT) begin
                    // Reached maximum: wrap around to 0 and set overflow
                    counter_reg <= {WIDTH{1'b0}};
                    overflow_reg <= 1'b1;  // Indicate overflow occurred
                end else begin
                    // Normal increment
                    counter_reg <= counter_reg + 1'b1;
                end
            end else begin
                // ================================================================
                // Count Down
                // ================================================================
                if (counter_reg == {WIDTH{1'b0}}) begin
                    // Reached zero: wrap around to MAX_COUNT and set overflow
                    counter_reg <= MAX_COUNT;
                    overflow_reg <= 1'b1;  // Indicate underflow occurred
                end else begin
                    // Normal decrement
                    counter_reg <= counter_reg - 1'b1;
                end
            end
        end
        // Note: If enable is low, counter holds current value
    end
    
    // ============================================================================
    // Output Assignments
    // ============================================================================
    assign count = counter_reg;
    assign overflow = overflow_reg;

endmodule