parameterized_sync_reset_counter.v

/**
 * Parameterized Synchronous Reset Counter
 * 
 * This module implements a counter with synchronous reset. Unlike asynchronous
 * reset, synchronous reset occurs on the clock edge, making it useful for
 * controlled reset sequences and state machine initialization.
 * 
 * Key Features:
 * - Synchronous reset: Reset occurs on clock edge (not immediate)
 * - Configurable width: Any bit width via WIDTH parameter
 * - Configurable maximum: Can set MAX_COUNT (default: 2^WIDTH - 1)
 * - Terminal count: Signal indicates when counter reaches maximum
 * - Wrap-around: Automatically wraps to 0 after reaching MAX_COUNT
 * 
 * Counter Operation:
 * - Count sequence: 0, 1, 2, ..., MAX_COUNT, 0, 1, ...
 * - Wrap-around: After MAX_COUNT, next value is 0
 * - Terminal count: tc is high when count = MAX_COUNT
 * 
 * Synchronous Reset:
 * - Reset occurs on clock edge: sync_rst sampled on clock
 * - Controlled reset: Allows reset in specific clock cycles
 * - State machine friendly: Works well with synchronous state machines
 * 
 * Use Cases:
 * - Frequency division
 * - Time measurement
 * - Event counting
 * - State machine counters
 * 
 * @param WIDTH Width of counter (default: 8 bits)
 *             Must be sufficient to represent MAX_COUNT
 * @param MAX_COUNT Maximum count value (default: 2^WIDTH - 1)
 *                 Counter counts from 0 to MAX_COUNT
 * 
 * @input clk Clock signal
 * @input sync_rst Synchronous reset (active high)
 * @input enable Enable signal (high to count)
 * @output count[WIDTH-1:0] Counter output value
 * @output tc Terminal count signal (high when count = MAX_COUNT)
 */
module parameterized_sync_reset_counter #(
    parameter WIDTH = 8,
    parameter MAX_COUNT = (1 << WIDTH) - 1
)(
    input wire clk,
    input wire sync_rst,  // Synchronous reset (active high)
    input wire enable,    // Enable signal
    output wire [WIDTH-1:0] count,
    output wire tc        // Terminal count signal (high when count = MAX_COUNT)
);

    reg [WIDTH-1:0] counter_reg;
    
    // ============================================================================
    // Counter Logic (Synchronous Reset)
    // ============================================================================
    // Note: Only posedge clk (no async reset) - reset is synchronous
    always @(posedge clk) begin
        if (sync_rst) begin
            // ====================================================================
            // Synchronous Reset
            // ====================================================================
            // Reset occurs on clock edge (synchronous)
            // This allows controlled reset in specific clock cycles
            counter_reg <= {WIDTH{1'b0}};
        end else if (enable) begin
            // ====================================================================
            // Counter Operation
            // ====================================================================
            if (counter_reg == MAX_COUNT) begin
                // ================================================================
                // Wrap-Around
                // ================================================================
                // Counter reached maximum: wrap around to 0
                counter_reg <= {WIDTH{1'b0}};
            end else begin
                // ================================================================
                // Increment
                // ================================================================
                // Counter not at maximum: increment
                counter_reg <= counter_reg + 1'b1;
            end
        end
        // ========================================================================
        // Hold Mode
        // ========================================================================
        // When enable is low and sync_rst is low, counter holds current value
        // (implicit: no assignment means value is maintained)
    end
    
    assign count = counter_reg;
    assign tc = (counter_reg == MAX_COUNT) ? 1'b1 : 1'b0;

endmodule