parameterized_johnson_counter.v

/**
 * Parameterized Johnson Counter
 * 
 * This module implements a Johnson counter (also known as a twisted ring counter
 * or Möbius counter). A Johnson counter is a modified ring counter where the
 * inverted MSB is fed back to the LSB, creating a sequence that is 2×WIDTH
 * states long.
 * 
 * Key Features:
 * - Modified ring counter: Inverted feedback from MSB to LSB
 * - Sequence length: 2×WIDTH states (twice that of a ring counter)
 * - One-hot encoding: Only one bit changes per state transition
 * - Configurable width: Any bit width via WIDTH parameter
 * 
 * Johnson Counter Operation:
 * - Initial state: All zeros (e.g., 0000 for WIDTH=4)
 * - Operation: Shift left, feed inverted MSB to LSB
 * - Sequence (WIDTH=4): 0000 → 0001 → 0011 → 0111 → 1111 → 1110 → 1100 → 1000 → 0000
 * - Sequence length: 8 states (2×4)
 * 
 * Shift and Invert:
 * - Left shift: counter_reg << 1
 * - Inverted MSB: ~counter_reg[WIDTH-1]
 * - Feedback: Inverted MSB becomes new LSB
 * - Format: {counter_reg[WIDTH-2:0], ~counter_reg[WIDTH-1]}
 * 
 * Use Cases:
 * - State machines with 2×WIDTH states
 * - Frequency division (divide by 2×WIDTH)
 * - Sequence generation
 * - Phase generation
 * 
 * Advantages:
 * - More states than ring counter (2×WIDTH vs WIDTH)
 * - Simple decoding: Only one bit changes per transition
 * - Low power: Only one flip-flop toggles per cycle
 * 
 * @param WIDTH Width of Johnson counter (default: 4 bits)
 *              Sequence length = 2×WIDTH states
 * 
 * @input clk Clock signal
 * @input rst_n Active-low reset signal
 * @input enable Enable signal (high to count)
 * @output count[WIDTH-1:0] Johnson counter output
 */
module parameterized_johnson_counter #(
    parameter WIDTH = 4  // Default width is 4 bits
)(
    input wire clk,
    input wire rst_n,    // Active low reset
    input wire enable,   // Enable signal
    output wire [WIDTH-1:0] count
);

    reg [WIDTH-1:0] counter_reg;
    
    // ============================================================================
    // Johnson Counter Logic
    // ============================================================================
    // Implements shift-left with inverted feedback
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            // ====================================================================
            // Reset State
            // ====================================================================
            // Initialize with all zeros
            // This is the starting state of the Johnson counter sequence
            counter_reg <= 0;
        end else if (enable) begin
            // ====================================================================
            // Johnson Counter Operation
            // ====================================================================
            // Shift left and feed inverted MSB to LSB
            // Format: {lower_bits[WIDTH-2:0], inverted_MSB}
            // This creates the characteristic Johnson counter sequence
            // Example (WIDTH=4): 0000 → 0001 → 0011 → 0111 → 1111 → 1110 → 1100 → 1000 → 0000
            counter_reg <= {counter_reg[WIDTH-2:0], ~counter_reg[WIDTH-1]};
        end
        // ========================================================================
        // Hold Mode
        // ========================================================================
        // When enable is low, counter holds current value
        // (implicit: no assignment means value is maintained)
    end
    
    assign count = counter_reg;

endmodule