Makefile

# ============================================================================
# CORE Project Makefile
# ============================================================================
# This Makefile provides a comprehensive build and verification system for
# the CORE RTL library project. It automates:
#
# 1. Verilog compilation using Verilator
# 2. Testbench execution and verification
# 3. Synthesis using Yosys
# 4. Report generation
# 5. Module discovery and dependency management
#
# Key Features:
# - Automatic module discovery from libraries directory
# - Dynamic target generation for all modules
# - Group verification by category
# - Synthesis support with Yosys
# - Comprehensive reporting tools
#
# Usage:
#   make help              # Show all available targets
#   make verify_<module>   # Verify a specific module
#   make verify_all        # Verify all modules
#   make synth_<module>    # Synthesize a specific module
#   make report            # Generate verification report
# ============================================================================

# ============================================================================
# Tool Configuration
# ============================================================================
VERILATOR = verilator  # Verilator simulator/compiler
# Verilator flags:
#   -Wall: Enable all warnings
#   -Wno-EOFNEWLINE: Suppress EOF newline warnings
#   --trace: Enable VCD waveform tracing
#   --cc: Generate C++ code
#   --build: Build the executable
#   -j: Parallel compilation
#   --Mdir: Output directory for generated files
VERILATOR_FLAGS = -Wall -Wno-EOFNEWLINE --trace --cc --build -j --Mdir $(OBJDIR)
VERILATOR_CPP_FLAGS = --exe  # Link testbench as executable

# ============================================================================
# Directory Configuration
# ============================================================================
OBJDIR = build          # Output directory for all build products
LIB_DIR = libraries     # Root directory containing all Verilog modules

# ============================================================================
# Warning Suppressions
# ============================================================================
# Common warning suppressions for most modules to reduce noise:
#   -Wno-EOFNEWLINE: Ignore missing newline at end of file
#   -Wno-UNUSEDSIGNAL: Ignore unused signal warnings
#   -Wno-WIDTHTRUNC: Ignore width truncation warnings
#   -Wno-WIDTHEXPAND: Ignore width expansion warnings
#   -Wno-UNUSEDPARAM: Ignore unused parameter warnings
COMMON_WARNINGS = -Wno-EOFNEWLINE -Wno-UNUSEDSIGNAL -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND -Wno-UNUSEDPARAM

# ============================================================================
# File Discovery
# ============================================================================
# Automatically discover all Verilog modules and testbenches
VERILOG_FILES := $(shell find $(LIB_DIR) -name "*.v")
TESTBENCH_FILES := $(shell find $(LIB_DIR) -name "tb_*.cpp")

# Extract module names from Verilog files (strip path and extension)
MODULES := $(sort $(basename $(notdir $(VERILOG_FILES))))

# Create list of modules with testbenches available
# This identifies which modules can actually be verified
TESTBENCH_MODULES := $(basename $(notdir $(TESTBENCH_FILES)))
TESTABLE_MODULES := $(sort $(patsubst tb_%,%,$(TESTBENCH_MODULES)))

# ============================================================================
# Dynamic Target Generation
# ============================================================================
# Generate build, run, and clean targets for each testable module
# These are created dynamically based on discovered modules
BUILD_TARGETS := $(addprefix build_,$(TESTABLE_MODULES))
RUN_TARGETS := $(addprefix run_,$(TESTABLE_MODULES))
CLEAN_MOD_TARGETS := $(addprefix clean_,$(TESTABLE_MODULES))

# ============================================================================
# Helper Functions
# ============================================================================
# Function to find Verilog source file for a module
# Usage: $(call get_module_src,module_name)
define get_module_src
$(shell find $(LIB_DIR) -name "$(1).v")
endef

# Function to find testbench file for a module
# Usage: $(call get_module_tb,module_name)
define get_module_tb
$(shell find $(LIB_DIR) -name "tb_$(1).cpp")
endef

# Default target to list available commands
help:
	@echo "CORE Project Makefile"
	@echo ""
	@echo "Basic targets:"
	@echo "  help            - Display this help message"
	@echo "  init            - Create necessary build directories"
	@echo "  list_modules    - List all available modules and testable modules"
	@echo ""
	@echo "Verification targets:"
	@echo "  verify <module> - Verify a specific module (e.g., make verify shift_register)"
	@echo "  verify_all      - Verify all modules with testbenches"
	@echo ""
	@echo "Synthesis targets:"
	@echo "  synth <module>  - Synthesize a specific module using Yosys (e.g., make synth_shift_register)"
	@echo "  synth_all       - Synthesize all available modules"
	@echo ""
	@echo "Cleaning targets:"
	@echo "  clean           - Clean all build products"
	@echo "  clean_<module>  - Clean specific module build products"
	@echo ""
	@echo "Group verification targets:"
	@echo "  verify_adders     - Verify all adder modules"
	@echo "  verify_fifos      - Verify all FIFO and buffer modules"
	@echo "  verify_registers  - Verify all register and counter modules"
	@echo "  verify_alu        - Verify ALU module"
	@echo "  verify_cordic     - Verify CORDIC and trigonometric modules"
	@echo "  verify_counters   - Verify counter modules"
	@echo "  verify_dividers   - Verify divider modules"
	@echo "  verify_arbiters   - Verify arbiter modules"
	@echo "  verify_codings    - Verify encoder/decoder/CRC modules"
	@echo "  verify_noc        - Verify Network-on-Chip related modules"
	@echo "  verify_dsp        - Verify DSP modules (FFT, filters, etc.)"
	@echo "  verify_mems       - Verify memory modules (RAM, CAM, etc.)"
	@echo "  verify_filters    - Verify filter modules"
	@echo "  verify_fsm        - Verify finite state machine modules"
	@echo "  verify_comms      - Verify communication modules (UART, SPI, I2C)"
	@echo "  verify_signals    - Verify signal processing modules"
	@echo "  verify_voters     - Verify voter modules"
	@echo "  verify_interfaces - Verify interface modules"
	@echo ""
	@echo "Reports:"
	@echo "  report          - Generate verification report (REPORT.md)"
	@echo "  analyze         - Analyze dataset and synthesis (DATASET.md)"
	@echo "  standards       - Generate Verilog standards report (VERILOG_STANDARDS.md)"
	@echo ""
	@echo "Output directories:"
	@echo "  build/          - Contains all build products and synthesis results"
	@echo ""
	@echo "Example usage:"
	@echo "  make list_modules"
	@echo "  make verify_shift_register"
	@echo "  make synth_alu"
	@echo "  make clean"

# Create directories
init:
	@mkdir -p $(OBJDIR)

# Target to find and display all available modules
list_modules:
	@echo "Found $(words $(MODULES)) Verilog modules:"
	@for module in $(sort $(MODULES)); do \
		echo "  $$module"; \
	done
	@echo ""
	@echo "Found $(words $(TESTABLE_MODULES)) modules with testbenches:"
	@for module in $(sort $(TESTABLE_MODULES)); do \
		echo "  $$module"; \
	done

# ============================================================================
# Generic Build and Run Functions
# ============================================================================
# Generic function to build a module using Verilator
# This function:
# 1. Finds the Verilog source file
# 2. Finds the testbench file
# 3. Compiles with Verilator
# 4. Creates a build marker file
# Usage: $(call build_module,module_name)
define build_module
	MODULE="$(1)"; \
	VERILOG_FILE=$$(find $(LIB_DIR) -name "$$MODULE.v"); \
	TESTBENCH_FILE=$$(find $(LIB_DIR) -name "tb_$$MODULE.cpp"); \
	if [ -n "$$VERILOG_FILE" ] && [ -n "$$TESTBENCH_FILE" ]; then \
		echo "Building $$MODULE from $$(dirname $$VERILOG_FILE)..."; \
		$(VERILATOR) $(VERILATOR_FLAGS) $(COMMON_WARNINGS) $(VERILATOR_CPP_FLAGS) "$$VERILOG_FILE" "$$TESTBENCH_FILE"; \
		touch $(OBJDIR)/.$$MODULE.built; \
	else \
		echo "Module $$MODULE not found or missing testbench"; \
		echo "  Verilog file: $$VERILOG_FILE"; \
		echo "  Testbench file: $$TESTBENCH_FILE"; \
		exit 1; \
	fi
endef

# Generic function to run a module's testbench
# This function:
# 1. Checks if the executable exists
# 2. Runs the testbench executable
# Usage: $(call run_module,module_name)
define run_module
	@MODULE=$(1); \
	if [ -f "$(OBJDIR)/V$$MODULE" ]; then \
		echo "Running verification for $$MODULE..."; \
		$(OBJDIR)/V$$MODULE; \
	else \
		echo "Error: Module $$MODULE not built or missing executable"; \
		exit 1; \
	fi
endef

# ============================================================================
# Verification Targets
# ============================================================================
# Generic verification target: builds and runs testbench for a module
# Usage: make verify_<module_name>
# Example: make verify_adder
verify_%: init
	$(call build_module,$*)
	$(call run_module,$*)

# Special verification target for modules with dependencies
# sine_cosine_generator requires cordic_core, so we include it explicitly
verify_sine_cosine_generator: init
	@VERILOG_FILE=`find $(LIB_DIR) -name "sine_cosine_generator.v"`; \
	CORDIC_FILE=`find $(LIB_DIR) -name "cordic_core.v"`; \
	TESTBENCH_FILE=`find $(LIB_DIR) -name "tb_sine_cosine_generator.cpp"`; \
	if [ -n "$$VERILOG_FILE" ] && [ -n "$$CORDIC_FILE" ] && [ -n "$$TESTBENCH_FILE" ]; then \
		echo "Building sine_cosine_generator with dependencies..."; \
		$(VERILATOR) $(VERILATOR_FLAGS) $(COMMON_WARNINGS) -I`dirname $$CORDIC_FILE` $(VERILATOR_CPP_FLAGS) $$VERILOG_FILE $$CORDIC_FILE $$TESTBENCH_FILE; \
		echo "Running verification for sine_cosine_generator..."; \
		$(OBJDIR)/Vsine_cosine_generator; \
	else \
		echo "Skipping sine_cosine_generator (missing source or testbench)"; \
		echo "  Verilog file: $$VERILOG_FILE"; \
		echo "  CORDIC file: $$CORDIC_FILE"; \
		echo "  Testbench file: $$TESTBENCH_FILE"; \
	fi

# ============================================================================
# Cleaning Targets
# ============================================================================
# Clean build products for a specific module
# Usage: make clean_<module_name>
clean_%:
	@echo "Cleaning module $*..."
	@rm -f $(OBJDIR)/V$*
	@rm -f $(OBJDIR)/.$*.built
	@rm -f $(OBJDIR)/$**.o
	@rm -f $(OBJDIR)/V$**.cpp
	@rm -f $(OBJDIR)/V$**.h

# Clean all build products and generated files
# Removes build directory and VCD waveform files
clean:
	@echo "Cleaning all build products..."
	@rm -rf $(OBJDIR)
	@rm -f *.vcd

# Verify all modules with testbenches
# Iterates through all testable modules and verifies each one
verify_all: init
	@for module in $(TESTABLE_MODULES); do \
		echo "\n=== Verifying $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll verifications completed."

# ============================================================================
# Report Generation Targets
# ============================================================================
# Generate comprehensive verification report (REPORT.md)
# Includes test results, statistics, and tool versions
report:
	@echo "Generating REPORT.md..."
	@python3 scripts/report.py

# Analyze dataset and generate statistics (DATASET.md)
# Includes code metrics, design patterns, and synthesis statistics
analyze:
	@echo "Generating DATASET.md..."
	@python3 scripts/analyze_verilog_dataset.py --synth --output DATASET.md --loglevel INFO

# Generate Verilog standard compliance report (VERILOG_STANDARDS.md)
# Analyzes which Verilog/SystemVerilog standard each module requires
standards:
	@echo "Generating VERILOG_STANDARDS.md..."
	@python3 scripts/verilog_standard_report.py --output VERILOG_STANDARDS.md --loglevel INFO

# ============================================================================
# Category-Based Verification Targets
# ============================================================================
# These targets allow verification of modules grouped by category
# Useful for testing specific functional areas of the codebase

# Verify all adder modules (Brent-Kung, Kogge-Stone, Carry-Lookahead, etc.)
verify_adders: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_configurable_% build_dadda_%,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying adder: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll adder verifications completed."

# Verify all FIFO and buffer modules (sync, async, dual-clock, etc.)
verify_fifos: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%fifo build_%buffer build_%queue,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying FIFO: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll FIFO verifications completed."

# Verify all register and shift register modules
verify_registers: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%register build_%counter build_barrel_% build_lfsr,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying register: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll register verifications completed."

# Verify ALU (Arithmetic Logic Unit) module
verify_alu: init
	@if [ -f "$(LIB_DIR)/alu/alu.v" ] && [ -f "$(LIB_DIR)/alu/tb_alu.cpp" ]; then \
		echo "\n=== Verifying ALU ==="; \
		$(call build_module,alu) && $(call run_module,alu) || echo "Verification of alu failed"; \
	else \
		echo "Error: ALU module or testbench not found in $(LIB_DIR)/alu/"; \
		exit 1; \
	fi
	@echo "\nALU verification completed."

# Verify CORDIC and trigonometric function modules
verify_cordic: init
	@for module in cordic_core sine_cosine_generator; do \
		if [ -n "$$(find $(LIB_DIR) -name "$$module.v")" ] && [ -n "$$(find $(LIB_DIR) -name "tb_$$module.cpp")" ]; then \
			echo "\n=== Verifying CORDIC: $$module ==="; \
			$(call build_module,$$module) && $(call run_module,$$module) || echo "Verification of $$module failed"; \
		fi; \
	done
	@echo "\nAll CORDIC verifications completed."

# Verify all counter modules (Gray, Johnson, up/down, etc.)
verify_counters: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%counter build_%synchronizer,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying counter: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll counter verifications completed."

# Verify all divider modules
verify_dividers: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%divider,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying divider: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll divider verifications completed."

# Verify all arbiter modules (round-robin, matrix, priority, etc.)
verify_arbiters: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%arbiter,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying arbiter: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll arbiter verifications completed."

# Verify all encoding/decoding modules (Gray, binary, CRC, scrambler, etc.)
verify_codings: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%encoder build_%decoder build_%crc% build_%scrambler build_%binary build_%gray,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying coding: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll coding verifications completed."

# Verify Network-on-Chip modules (routers, switches, network interfaces)
verify_noc: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%router build_%switch build_%network,$(BUILD_TARGETS))),$(TESTABLE_MODULES)) network_interface_cdc; do \
		echo "\n=== Verifying NoC: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll NoC verifications completed."

# Verify DSP modules (FFT, DDS, filters, etc.)
verify_dsp: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%fft build_%dds build_%filter,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying DSP: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll DSP verifications completed."

# Verify memory modules (RAM, CAM, memory controllers, etc.)
verify_mems: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%ram build_%cam build_%memory,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying memory: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll memory verifications completed."

# Verify filter modules (FIR, IIR, etc.)
verify_filters: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%filter,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying filter: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll filter verifications completed."

# Verify finite state machine modules
verify_fsm: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%fsm build_%detector build_%machine,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying FSM: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll FSM verifications completed."

# Verify communication protocol modules (UART, SPI, I2C, SERDES, etc.)
verify_comms: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%uart% build_%spi% build_%i2c% build_%serdes% build_%serializer build_%deserializer build_%master build_%slave build_jtag_controller,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying communication: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll communication verifications completed."

# Verify signal processing modules (PWM, detectors, generators, PRNG, etc.)
verify_signals: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%pwm% build_%detector build_%gating build_%generator build_%controller build_%prng,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying signal: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll signal verifications completed."

# Verify voter modules (majority voter, etc.)
verify_voters: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%voter,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying voter: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll voter verifications completed."

# Verify interface modules (AXI, AHB, Wishbone, PCIe, etc.)
verify_interfaces: init
	@for module in $(filter $(patsubst build_%,%,$(filter build_%interface build_%protocol build_%bus,$(BUILD_TARGETS))),$(TESTABLE_MODULES)); do \
		echo "\n=== Verifying interface: $$module ==="; \
		$(MAKE) verify_$$module || echo "Verification of $$module failed"; \
	done
	@echo "\nAll interface verifications completed."

# ============================================================================
# Phony Target Declarations
# ============================================================================
# Declare targets that don't produce files with the same name
# This prevents Make from confusing targets with files
.PHONY: help init list_modules verify_all clean $(CLEAN_MOD_TARGETS) \
verify_adders verify_fifos verify_registers verify_alu verify_cordic \
verify_counters verify_dividers verify_arbiters verify_codings \
verify_noc verify_dsp verify_mems verify_filters verify_fsm \
verify_comms verify_signals verify_voters verify_interfaces \
synth_all report analyze standards

# ============================================================================
# Synthesis Targets (Yosys)
# ============================================================================
YOSYS = yosys  # Yosys synthesis tool

# Generic synthesis target for a module
# Synthesizes Verilog to gate-level netlist and generates statistics
# Usage: make synth_<module_name>
# Output: $(OBJDIR)/<module>.yosys.log and $(OBJDIR)/<module>.yosys.json
synth_%:
	@MODULE=$*; \
	VERILOG_FILE=$$(find $(LIB_DIR) -name "$$MODULE.v"); \
	if [ -n "$$VERILOG_FILE" ]; then \
		echo "Synthesizing $$MODULE..."; \
		$(YOSYS) -L $(OBJDIR)/$$MODULE.yosys.log \
			-p "read_verilog $$VERILOG_FILE; hierarchy -check -top $$MODULE; synth -top $$MODULE; stat -top $$MODULE; write_json $(OBJDIR)/$$MODULE.yosys.json;"; \
	else \
		echo "Module $$MODULE not found"; \
		exit 1; \
	fi

# Synthesize all modules using Yosys
# Generates synthesis statistics for all Verilog modules
synth_all: init
	@for module in $(MODULES); do \
		$(MAKE) synth_$$module; \
	done