diff --git a/.editorconfig b/.editorconfig index f270d4cdaa8..bbe49c058ad 100644 --- a/.editorconfig +++ b/.editorconfig @@ -4,6 +4,7 @@ root = true [*] indent_style = tab +indent_size = 8 tab_width = 8 charset = utf-8 insert_final_newline = true diff --git a/.gitignore b/.gitignore index 5a429b5e3c8..19f268cc587 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ +extended-junit.xml junit.xml abuild*.xml .config diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 0a6d270fb36..588da8d6deb 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 0a6d270fb36f726b26909c3369f155e44afeedc4 +Subproject commit 588da8d6deb4b9be60ccedfa76e721c6a2ea9464 diff --git a/3rdparty/fsp b/3rdparty/fsp index 81399b3b614..66b307a45fe 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 81399b3b61479abc379c2d01362d4b6dc6f515c9 +Subproject commit 66b307a45fe4d2f194e411ea73ba8e31d1fd214d diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 250941fb670..98f8d817ca3 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 250941fb670645d7d91f761cc63656ad3a1ec367 +Subproject commit 98f8d817ca3d560c48ae988bd805d1b53b48a631 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3c3828add50..7e08e5d2803 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3c3828add50024e90e57d6fbe0e660d1b66302d9 +Subproject commit 7e08e5d2803914af4e46280b558ec1307ead9031 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index 584629b9f47..5bd7c1101c0 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit 584629b9f4771b7618951cec57df2ca3af9c6981 +Subproject commit 5bd7c1101c0b8610949e0172b0e1a0072fd03638 diff --git a/AUTHORS b/AUTHORS index 21e1cd567f3..2cb957954e0 100644 --- a/AUTHORS +++ b/AUTHORS @@ -12,6 +12,7 @@ 9elements Agency GmbH Aamir Bohra Aaron Durbin +Abdelkader Boudih Abe Levkoy Abel Briggs Abhinav Hardikar @@ -22,13 +23,15 @@ Adam Mills Advanced Computing Lab, LANL Advanced Micro Devices, Inc. AG Electronics Ltd. -Agogo +Agogo Huang Ahamed Husni +Akshai Murari Akshu Agrawal Al Hirani Alan Huang AlanKY Lee Alec Wang +Alex Gan Alex James Alex Levin Alex Miao @@ -90,6 +93,7 @@ Avi Uday Avinash Munduru Balaji Manigandan Balázs Vinarz +Baozhen Yang BAP - Bruhnspace Advanced Projects Bartłomiej Grzesik Baruch Siach @@ -113,6 +117,7 @@ Brandon Weeks Brian Hsu Brian Norris Bryant Ou +Cai Chen Carl-Daniel Hailfinger Carlos López Casper Chang @@ -124,13 +129,16 @@ Chen-Tsung Hsieh Chen. Gang C Chia-Ling Hou Chien-Chih Tseng +Chou Pierce Chris Wang Christian Gmeiner +Christian Schrötter Christian Walter Christoph Grenz Christopher Meis Chuangwei Technology Co., Ltd Chun-Jie Chen +Cindy Lu Cirrus Logic, Inc. CK HU Clay Daniels @@ -146,6 +154,7 @@ Curt Brune Curtis Chen Custom Ideas Cyberus Technology GmbH +Cyril Chao Da Lao Daisuke Nojiri Damien Zammit @@ -157,6 +166,7 @@ Daniel Kang Daniel Maslowski Daniel Peng Daniel Rosa Franzini +Daniel Schaefer Dave Airlie David Brownell David Greenman @@ -185,9 +195,12 @@ Divya S Sasidharan Dmitry Ponamorev Dmitry Torokhov DMP Electronics Inc. +Dmytro Aleksandrov +Dodoid Dolan Liu Dominik Behr Donghwa Lee +Doris Hsu Drew Eckhardt Dtrain Hsu Duan Huayang @@ -201,12 +214,13 @@ Edward O'Callaghan Edward-JW Yang Egbert Eich Elias Souza +Elmo Lan Eloy Degen ELSOFT AG -Eltan B.V Eltan B.V. Elyes Haouas Emilie Roberts +Enzo Potenza Eran Mitrani Eren Peng Eric Biederman @@ -215,15 +229,18 @@ Eric Peers EricKY Cheng EricR Lai Erik van den Bogaert +Erin Liang Eswar Nallusamy Ethan Tsao Eugene Myers Evan Green Evgeny Zinoviev +Evie (Ivi) Ballou Fabian Groffen Fabian Kunkel Fabian Meyer Fabio Aiuto +Fabio Baltieri Fabrice Bellard Facebook, Inc. Federico Amedeo Izzo @@ -231,10 +248,13 @@ Fei Yan Felix Friedlander Felix Held Felix Singer +Felix Zimmer Fengquan Chen Filip Brozovic +Filip Gołaś Filip Lewiński Flora Fu +Florian Jung Florian Laufenböck Francois Toguo Fotso Frank Chu @@ -265,10 +285,13 @@ Guangjie Song Guennadi Liakhovetski Guodong Liu Gwendal Grignou +Haikun Zhou +Hailong Fan Hal Martin Hao Chou Hao Wang HardenedLinux +Haril Harrie Paijmans Harsha B R Harshit Sharma @@ -280,7 +303,7 @@ Himanshu Sahdev Hope Wang Housong Zhang Hsiao Chien Sung -Hsin-hsiung wang +Hsin-Hsiung Wang Hsin-Te Yuan Hsuan Ting Chen Hualin Wei @@ -304,13 +327,16 @@ INSPUR Co., Ltd Intel Corporation Inventec Corp Iru Cai +Irving-CH Lin Isaac Lee Isaku Yamahata Ivan Chen +Ivan Kuzneczov Ivan Vatlin Ivy Jian Jack Rosenthal Jacob Garber +Jaiganes Jairaj Arava Jakub Czapiga James Chao @@ -329,8 +355,8 @@ Jason Nein Jason V Le Jason Z Chen Jason Zhao -jason-ch chen -Jason-jh Lin +Jason-CH Chen +Jason-JH Lin Jay Patel Jayvik Desai Jean Lucas @@ -338,6 +364,7 @@ Jędrzej Ciupis Jeff Chase Jeff Daly Jeff Li +Jeff Xu Jérémy Compostella Jeremy Soller Jes Klinke @@ -345,10 +372,13 @@ Jesper Lin Jessy Jiang Jett Rink Jg Daolongzhu +Jhan Bo Chao Jian Tong +Jian-Jia Su Jianeng Ceng Jianjun Wang Jim Lai +Jimmy Cheng Jimmy Su Jincheng Li Jingle Hsu @@ -359,13 +389,14 @@ Joel Bueno Joel Kitching Joel Linn Joey Peng +Johann C. Rode Johanna Schander Johannes Hahn John Su John Zhao Johnny Li Johnny Lin -johnson wang +Johnson Wang Jon Murphy Jonas 'Sortie' Termansen Jonas Loeffelholz @@ -377,18 +408,23 @@ Jordan Crouse Jörg Mische Joseph Smith Josie Nordrum +Joyce Ciou Juan José García-Castro Crespo Julia Kittlinger Julia Tsai +Julian Braha Julian Intronati Julian Schroeder Julian Stecklina Julien Viard de Galbert Julius Werner +Justin Yeh Kacper Stojek +Kai-Chun Huang Kaiyen Chang Kane Chen Kangheui Won +KangMin Wang Kapil Porwal Karol Zmyslowski Karthik Ramasubramanian @@ -406,15 +442,20 @@ Kevin Keijzer Kevin O'Connor Kevin Yang Kevin3 Yang -kewei xu +Kewei Xu Kilari Raasi +Kilian Krause Kirk Wang +Kirubakaran E +kisekinopureya Kiwi Liu Konrad Adamczyk Kontron Europe GmbH Kornel Dulęba Krishna P Bhat D +Krishnan Manivannan Krystian Hebel +Krzysztof Sokol Kshitij Kshitiz Godara Kulkarni. Srinivas @@ -422,10 +463,12 @@ Kun Liu KunYi Chen Kyle Lin Kyösti Mälkki +Lai Kaiden Lance Zhao Lawrence Chang Leah Rowe Lean Sheng Tan +Lei Cao Lei Wen Lennart Eichhorn Lenovo Group Ltd @@ -434,25 +477,31 @@ Li-Ta Lo Li1 Feng Liam Flaherty Libra Li +Libreandre Libretrend LDA Lijian Zhao Liju-Clr Chen +LiLiang Chen Linaro Limited linear Linus Torvalds Linux Networx, Inc. LiPPERT ADLINK Technology GmbH Liu Liu +Liu Gary Liya Li +lizheng Lu Tang Lu. Pen-ChunX Lubomir Rintel Luc Verhaegen Luca Lai Lucas Chen +Lukas Wunner Mac Chiang Maciej Matuszczyk Maciej Pijanowski +Maciej Strozek Macpaul Lin Madhusudanarao Amara Magf @@ -467,7 +516,6 @@ Marek Maślanka Marek Vasut Mario Scheithauer Marius Gröger -Mariusz Szafranski Mariusz Szafrański Mark Chang Mark Hasemeyer @@ -494,16 +542,15 @@ Matthew Blecker Matthew Ziegelbaum Mattias Nissler Maulik V Vaghela -MAULIK V VAGHELA -Maulik Vaghela Max Fritz Maxim Polyakov Maximilian Brune -Mediatek Inc. MediaTek Inc. Meera Ravindranath +Megha Verma Melongmelong Meng-Huan Yu +Mengqi Zhang Meta Platforms, Inc mgabryelski1 Mice Lin @@ -522,6 +569,7 @@ Mika Westerberg Mike Banon Mike Lin Mike Shih +Mike Lee Mingjin Ge Miriam Polzer mkurumel @@ -534,7 +582,6 @@ MontaVista Software, Inc. Morgan Jang Moritz Fischer Morris Hsu -mtk15698 mturney mturney Musse Abdullahi Myles Watson @@ -542,6 +589,7 @@ Nancy Lin Naresh Solanki Nathan Lu Naveen R. Iyer +NaveenVenturi1203 Neill Corlett Network Appliance Inc. Nicholas Chin @@ -557,11 +605,14 @@ Nicola Corna Nicolas Boichat Nicole Faerber Nigel Tao +Niklaus Liu Nikolai Vyssotski Nils Jacobs Nina Wu +Nir Lichtman Nir Tzachar Nokia Corporation +Norman Bintang Nuvoton Technology Corporation NVIDIA Corporation Olivier Langlois @@ -570,12 +621,14 @@ Omar Pakker Online SAS Opal Voravootivat Orion Technologies, LLC -Ot_chhao.chang +Ot_chhao Chang Ot_hao.han +ot_ryanw Wang Ot_song Fan Pablo Pablo Ceballos Pablo Stebler +Padmanabhan Komanduru Pan Gao Patrick Georgi Patrick Huang @@ -588,6 +641,7 @@ Paul2 Huang Paulo Alcantara Pavan Holla Pavel Sayekat +Payne Lin Paz Zcharya PC Engines GmbH Pegatron Corp @@ -603,6 +657,7 @@ Philipp Bartsch Philipp Degler Philipp Deppenwiese Philipp Hug +Pierce Chou Piotr Kleinschmidt Po Xu Poornima Tom @@ -610,10 +665,10 @@ Pranava Y N Prasad Malisetty Prashant Malani Pratik Vishwakarma -Pratikkumar Prajapati Pratikkumar V Prajapati Protectli PugzAreCute +Purdea Andrei Purism, SPC Qii Wang Qinghong Zeng @@ -622,6 +677,7 @@ Quanta Computer INC Raihow Shi Rajat Jain Rajesh Patil +Raphaël Mélotte Raptor Engineering, LLC Rasheed Hsueh Raul Rangel @@ -631,6 +687,7 @@ Ravindra Ravishankar Sarawadi Ray Han Lim Ng Raymond Chung +Raymond Sun Reagan Red Hat, Inc ReddestDream @@ -668,6 +725,7 @@ Romain Lievin Roman Zippel Ron Lee Ron Minnich +Ron Nazarov Ronak Kanabar Ronald Claveau Ronald G. Minnich @@ -689,10 +747,12 @@ Sam Ravnborg Samsung Electronics Samuel Holland Sandeep Maheswaram +Sasirekaa Madhesu Sathya Prakash M R Satya Priya Kakitapalli Satya SreenivasL Saurabh Mishra +Schumi Chu SciTech Software, Inc. Scott Chao SDC Systems Ltd @@ -709,6 +769,7 @@ Serin Yeh Seven Lee SH Kim Shahina Shaik +Shaik Sameeruddin Shaocheng Wang Shaoming Chen Shaunak Saha @@ -734,6 +795,7 @@ Solomon Alan-Dei Song Fan Sowmya Aralguppe Sridhar Siricilla +Srijan Chaurasia Srinidhi N Kaushik Srinivasa Rao Mandadapu ST Microelectronics @@ -755,10 +817,12 @@ Sumeet R Pawnikar Sunwei Li SUSE LINUX AG Sven Schnelle +Swathi Tamilselvan Syed Mohammed Khasim System76, Inc. szarpaj T Michael Turney +Tangjiankai TangYiwei Taniya Das Tao Xia @@ -781,9 +845,10 @@ Tim Van Patten Tim Wawrzynczak Timofey Komarov Timothy Pearson -tinghan shen +Tinghan Shen Tobias Diedrich Tom Hiller +Tomasz Michalec Tommie Lin Tongtong Pan Tony Huang @@ -797,6 +862,7 @@ Tzung-Bi Shih U.S. National Security Agency ucRobotics Inc. Uday Bhat +Ulysse Ballesteros University of Heidelberg Usha P Uwe Hermann @@ -806,13 +872,16 @@ Václav Straka Vadim Bendebury Valentyn Sudomyr Van Chen +Varadarajan Narayanan Varshit B Pandya Varun Upadhyay Veerabhadrarao Badiganti Venkat Thogaru Venkata Krishna Nimmagadda +Venkateshwar S VIA Technologies, Inc Victor Ding +Victor Shih Vidya Gopalakrishnan Vikram Narayanan Vikrant L Jadeja @@ -820,12 +889,16 @@ Vince Liu Vinod Polimera Vipin Kumar Vitaly Rodionov +Vladimir Epifantsev Vladimir Serbinenko Vlado Cibic Vsujithk +Walter Sonius Wang Qing Pei Wanghao11 +wangzhao5 Ward Vandewege +Wayby Zhai Wayne Wang Weimin Wu Weiyi Lu @@ -841,7 +914,6 @@ Wim Vervoorn Win Enterprises Wisley Chen Wistron Corp -Wiwynn Corp. Wiwynn Corporation Wizard Shen Wojciech Macek @@ -849,6 +921,7 @@ Wolfgang Denk Won Chung Wonkyu Kim Wuxy +Xiandong Wang Xiang W Xin Ji Xiwen Shao @@ -860,6 +933,7 @@ YADRO Yan Liu Yang Wu Yann Collet +Yanqiong Huang Yaroslav Kurlaev YH Lin Yidi Lin @@ -869,6 +943,8 @@ Yolk Shih Yong Zhi Yongkun Yu Yongqiang Niu +Yoshihisa Harada +Youwen Huang Yu-hsuan Hsu Yu-Ping Wu Yuanliding @@ -880,8 +956,13 @@ Yuval Peress Zachary Yedidia Zanxi Chen Zebreus +Zengqinghong +Zeroway Lin +Zexin Wang Zhanyong Wang +Zhaoming Luo Zhaoqing Jiu +Zhaoxiong Lv Zheng Bao Zhenguo Li Zhi7 Li @@ -894,6 +975,7 @@ Zhuohao Lee Ziang Wang Zoey Wu Zoltan Baldaszti +一颗小土豆 小田喜陽彦 忧郁沙茶 -陳建宏 \ No newline at end of file +陳建宏 diff --git a/Documentation/getting_started/customizing.md b/Documentation/getting_started/customizing.md new file mode 100644 index 00000000000..5554ec11e52 --- /dev/null +++ b/Documentation/getting_started/customizing.md @@ -0,0 +1,77 @@ +# Customizing Module Behavior + +A common pattern in software development to allow "more specific" modules +customize behavior of "more foundational" modules (or to hook into them) is +dynamic _dependency injection_, which many developers might be used to. + +coreboot modules also vary in their degree of specialization; the following +list goes from "foundational" to "specific" and is by no means complete: +* **commonlib:** Library and helper code shared by many modules. +* **Platform code:** Code that supports a computing platform, e.g. `arch/x86` + (including bootblock, romstage, ramstage) or `arch/arm64`. +* **drivers** **CPU, SoC, North-/Southbridge code:** Code that supports a + specific CPU platform, like "Intel Alder Lake". +* **mainboard:** Mainboard-specific setup code, configuration data and hooks. +* **Mainboard variants:** Optional; a mainboard can have multiple variants + which differ in details only. + +In some contexts, coreboot exhibits a static variant of this design pattern +where, instead of registering function pointers at runtime, the configurability +is achieved **statically**, assisted by the linker. + +## Configurability in coreboot + +Various modules offer **customization points** in form of functions with +default or no-op implementations that defined as **weak symbols**. They +can be overridden by more specialized implementation as needed. Note that +outside of certain cases, using weak functions over function pointers has its +disadvantages and is therefore discouraged. (More below.) + +For example, `lib/bootblock.c` offers the definition +`__weak void bootblock_mainboard_early_init(void) { /* no-op */ }`. Mainboard +implementations are free to re-define this symbol to perform any early +initialization they need (e.g. early GPIO init). + +The linker will always prefer the non-weak definition over a weak definition +and discard the latter, rather than throwing a "duplicate definition" error. +Only if no other definition of the symbol exists, the linker will take the +`__weak` implementation, rather than throwing an "undefined symbol" error. + +## The role of Kconfig and Makefiles +As `git grep` reveals, lots of files inside the `mainboard/` directory +implement the `bootblock_mainboard_early_init(void)` function; usually in files +named `early_init.c` or `bootblock.c`, but this is only convention. + +In order to select _which_ of these implementations is actually used, we +leverage the [build system](build_system.md). Only _one_ of these source +files implementing a particular symbol is actually built and linked into the +final result, for any given build configuration. + +Note that when there is a function call into code which only gets included when +a specific Kconfig option is selected, it's preferable to also make that call +itself conditional on the Kconfig option in order to improve readability. + +## Identifying customization points + +Unfortunately, there is currently no exhaustive list of these customization +points. An easy way to identify them, however, is `git grep -w __weak`. This +shows their default definition in the `.c` files; looking up their declaration +in the `.h` files often reveals some additional documentation. + +## Use Cases and Non-Use Cases + +Using weak symbols comes with its disadvantages, e.g. bad discoverability and +surprising behavior when a wrong overridden function is included in the build +or when the default implementation is used instead of the desired override. +These problems are hard to debug because there are no build errors that could +indicate the problem. + +As a rule of thumb, usages with limited or clear scope are ok, such as +mainboard variants, the SMBIOS table overrides and hooks in common code that +mainboards or SoCs can override. Weak symbols enable easy hooking here without +requiring RAM to be functional already. + +Outside of those cases, it is usually better to resort to other patterns, like +e.g. function pointers. Like described above, these come with the advantage of +causing clear build errors when used incorrectly, rather than failing in +surprising ways at runtime. diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 8b2ce3a31c6..236f569ad60 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -4,6 +4,7 @@ :maxdepth: 1 coreboot architecture +Customizing Module Behavior Build System Submodules Kconfig diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 4aa00a224ef..2917c53aae8 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -888,11 +888,6 @@ string <expr> \[if <expr>\] string default "southbridge/amd/pi/hudson/bootblock.c" - config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - depends on HUDSON_GEC_FWM - - ##### Notes: - Putting the prompt after the 'string' keyword is the same as using a 'prompt' keyword later. See the prompt keyword for more notes. diff --git a/Documentation/mainboard/asrock/h370m-itx_ac.md b/Documentation/mainboard/asrock/h370m-itx_ac.md new file mode 100644 index 00000000000..1d8736fe093 --- /dev/null +++ b/Documentation/mainboard/asrock/h370m-itx_ac.md @@ -0,0 +1,276 @@ +# ASRock H370M-ITX/ac Mini-ITX Motherboard + +This page describes how to run coreboot on the [ASRock H370m-ITX/ac]. + +## Technology + +```{eval-rst} ++---------+---------------------------------------------------------------+ +| CPU | | Intel 8th/9th Gen (Coffeelake-S) Core Processors (LGA-1151) | +| | | CPUs over 95W will be limited due to power design | ++---------+---------------------------------------------------------------+ +| DRAM | 2 DIMM slots, DDR4 2666/2400/2133 MT/s | ++---------+---------------------------------------------------------------+ +| Chipset | Intel H370 | ++---------+---------------------------------------------------------------+ +| SuperIO | Nuvoton NCT5567D-B | ++---------+---------------------------------------------------------------+ +| Boot | USB, SATA, NVMe | ++---------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build full working image of coreboot, the following blobs are required: + +```{eval-rst} ++-----------------+-------------------------------------------+-------------------------+ +| Binary file | Apply | Required/Optional | ++=================+===========================================+=========================+ +| FSP-M & FSP-S | Intel Firmware Support Package 2.1 | Required | +| | 9th Generation Intel® Core™ processors | | +| | and chipsets (formerly Coffee Lake) | | ++-----------------+-------------------------------------------+-------------------------+ +| IFD | Intel Flash Descriptor | Required | ++-----------------+-------------------------------------------+-------------------------+ +| ME | Intel Management Engine | Required | ++-----------------+-------------------------------------------+-------------------------+ +| GBE | Gigabit Ethernet Configuration | Optional | +| | | (MAC for LAN2) | ++-----------------+-------------------------------------------+-------------------------+ +``` + +### FSP + +Intel company provides [Firmware Support Package (2.1)](../../soc/intel/fsp/index.md) +to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). + +### IFD, ME, GBE + +Use the [vendor's firmware] version 1.80 to extract the IFD, ME, GBE blobs from it, according to +the [Intel IFD Binary Extraction Tutorial](../../util/ifdtool/binary_extraction.md). + +```bash +wget --tries=5 "https://web.archive.org/web/20260412110351/https://download.asrock.com/BIOS/1151/H370M-ITXac(4.30E)ROM.zip" +unzip "H370M-ITXac\(4.30E\)ROM.zip" +ifdtool --platform cnl -x H37MIA4.30E +File H37MIA4.30E is 16777216 bytes + Flash Region 0 (Flash Descriptor): 00000000 - 00000fff + Flash Region 1 (BIOS): 00300000 - 00ffffff + Flash Region 2 (Intel ME): 00003000 - 002fffff + Flash Region 3 (GbE): 00001000 - 00002fff +``` + +## Building coreboot + +The following commands will help quickly configure and build a project for this board: + +```bash +make distclean && \ +touch .config && \ +./util/scripts/config --enable VENDOR_ASROCK --enable BOARD_ASROCK_H370M_ITX && \ +make olddefconfig +make +``` + +## Payloads + +```{eval-rst} ++---------------+------+---------+ +| OS / Payload | EDK2 | SeaBIOS | ++===============+======+=========+ +| Ubuntu 24.04 | | V | ++---------------+------+---------+ +| Nix 23.11 | V | V | ++---------------+------+---------+ +| Windows 10 | | V | ++---------------+------+---------+ +| Windows 11 | V | | ++---------------+------+---------+ +``` + +- SeaBIOS (1.17.0) +- EDK2 (mrchromebox, tag: uefipayload_2603) + +### Additional information + +- Ubuntu 24.04 (Linux 6.8.0-41-generic) +- NixOS 23.11 (Linux 6.19.2-cachyos-lto) +- Microsoft Windows 10 Pro (22H2 2022) +- Microsoft Windows 11 Pro (25H2) + +## Flashing coreboot + +```{eval-rst} ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | W25Q128JVSIQ | ++---------------------+--------------------------+ +| Size | 16 MiB | ++---------------------+--------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------+ +| Write protection | chipset PRR | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | after flashing coreboot | ++---------------------+--------------------------+ +``` + +The SPI flash can be accessed using [flashrom]. By default, only the +BIOS region of the flash is writable: + +```bash +flashrom -p internal -N -w coreboot.rom --ifd -i bios +``` + +If you wish to change any other region, such as the Management Engine +or firmware descriptor, then an external programmer is required. More +information about this [here](../../tutorial/flashing_firmware/index.md). + +## External flashing pinout + +The SPI flash is an 8-pin SOIC device. A nearby 10-pin header (`PH1`) exposes the SPI signals. + +**Orientation:** Top view, CPU socket is at the top. + +```text + CPU SOCKET (TOP) + ──────────────── + +DI (IO0 / MOSI) - 01 10 - GND +CLK - 02 09 - NC + __ 08 - DO (IO1 / MISO) +VCC (3.3V) - 04 07 - /CS +HOLD#/RESET (IO3) - 05 06 - /WP (IO2) +``` + +**Notes:** + +* Pin **3 is not present** on this header. +* Pin **9 is not connected (NC)**. +* Signals correspond directly to the SPI flash pins. +* Use a **3.3V-compatible programmer only**. +* Incorrect wiring may permanently damage the board. + +## Working + +- Dual Channel DDR4 2666/2400/2133 MHz +- Intel UHD Graphics + - DP + - HDMI + - VGA Option ROM + - libgfxinit + - GOP +- PCIe x16 Slot (Gen3) +- SATA ports +- USB 2.0 ports +- USB 3.2 ports +- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0) +- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3, needs manual switching see next chapter) +- LAN1 Intel I211AT, 10/100/1000 Mbps +- LAN2 Intel I219V, 10/100/1000 Mbps +- Realtek ALC892 HD Audio (line-out, mic-in) +- S3 suspend and wake +- Wake on LAN on both ports +- fTPM +- disabling ME with me_cleaner [XutaxKamay fork] (v1.2-9-gf20532d) + +## Unknown/untested + +- external TPM + +## Display output notes + +### libgfxinit GMBUS pin patch required for HDMI 2 + +libgfxinit uses Broxton-era GMBUS pin assignments which are incorrect for the Cannon Point PCH (H370). Without patching, HDMI 2 (DDI D) fails to read EDID and produces no output in SeaBIOS. All ports work correctly under Linux since i915 has its own CNP-specific pin table. + +A patch to `3rdparty/libgfxinit/common/hw-gfx-gma-i2c.adb` is required. In the `GMBUS_Alternative_Pins` branch of `GMBUS0_PIN_PAIR_SELECT`, apply the following: + +```{eval-rst} ++-------+-----------------------+--------------------+ +| DDI | Correct GMBUS Pin | libgfxinit Default | ++=======+=======================+====================+ +| DDI B | 4 (GMBUS_PIN_4_CNP) | 1 (BXT_B) ✗ | ++-------+-----------------------+--------------------+ +| DDI C | 2 (GMBUS_PIN_2_BXT) | 2 (BXT_C) ✓ | ++-------+-----------------------+--------------------+ +| DDI D | 1 (GMBUS_PIN_1_BXT) | 3 (BXT_D) ✗ | ++-------+-----------------------+--------------------+ +``` + +This board's DDC wiring swaps DDI B and DDI D relative to the CNP reference design. The pin values match the VBT DDC pin fields from the vendor firmware. + +### Display port mapping + +```{eval-rst} ++---------------------+-------+---------------------+ +| Physical Connector | DDI | libgfxinit Port | ++=====================+=======+=====================+ +| DisplayPort | DDI B | DP1 | ++---------------------+-------+---------------------+ +| HDMI 1 | DDI C | HDMI2 | ++---------------------+-------+---------------------+ +| HDMI 2 | DDI D | HDMI3 | ++---------------------+-------+---------------------+ +``` + +DDI A (eDP) and DDI E are not routed to any physical connector. + +### VBT patching + +The vendor VBT declares two phantom child devices: an eDP panel on DDI A (LFP1, device type `0x78c6`) and a DisplayPort output on DDI E (EFP4, device type `0x68c6`). These can be removed by zeroing out the respective device type fields in the VBT binary. + +## SATA/PCIe muxing on M.2 slot + +The ASRock H370M-ITX features a single M.2 Key-M slot that supports both SATA and PCIe (NVMe) storage devices. Unlike some boards that use physical jumper pins or automatic hardware sensing, ASRock implements this switching via **Intel Soft Straps** within the Flash Descriptor (FD). + +The PCH uses High Speed I/O (HSIO) lanes that are multiplexed. Depending on the values of specific soft straps, the HSIO lanes connected to the M.2 slot are routed either to the internal SATA controller or the PCIe controller. + +### Configuration Straps + +The protocol is determined by the following PCH Straps: + +| Strap | Offset | PCIe (NVMe) Value | SATA Value | +|-------|--------|-------------------|------------| +| **PCHSTRP28** | `0x170` | `0x00000000` | `0x00010000` | +| **PCHSTRP81** | `0x244` | `0x77775555` | `0x77577555` | + +*Note: In PCHSTRP81, the nibble for Lane 25 switches from 5 to 7, and Lane 27 switches from 7 to 5 when moving from PCIe to SATA.* + +### Switching Protocols + +Since these settings reside in the Flash Descriptor, they cannot be changed by the BIOS at runtime. To switch the protocol, the Flash Descriptor must be modified and reflashed. + +You can use `ifdtool` from the coreboot tree to manually set these straps using the `-S` and `-V` flags + +```bash +# To switch to SATA mode using ifdtool: +ifdtool -S 28 -V 0x00010000 -S 81 -V 0x77577555 your_bios.bin + +# To switch to PCIe mode using ifdtool: +ifdtool -S 28 -V 0x00000000 -S 81 -V 0x77775555 your_bios.bin +``` + +> **Warning:** These straps are specific to the electrical routing of the ASRock H370M-ITX. Applying these values to other H370 boards may disable HSIO lanes used for USB, Ethernet, or other critical peripherals. + +For more information on how the PCH handles these configurations, see the [Soft Straps](../../getting_started/gpio.md#soft-straps) section. + +### SATA Port Conflict + +**Important:** Due to HSIO lane sharing, using a SATA-type M.2 device has a hardware trade-off: +* If the M.2 slot is set to **SATA mode** and a device is present, physical port **SATA3_1** will be disabled. +* If using an **NVMe (PCIe) device**, all physical SATA ports remain functional. + +## Extra links + +[ASRock H370M-ITXac]: https://web.archive.org/web/20250504092857/https://www.asrock.com/mb/Intel/H370M-ITXac/index.de.asp +[vendor's firmware]: https://web.archive.org/web/20260412110351/https://download.asrock.com/BIOS/1151/H370M-ITXac(4.30E)ROM.zip +[flashrom]: https://flashrom.org/ +[XutaxKamay fork]: https://github.com/XutaxKamay/me_cleaner diff --git a/Documentation/mainboard/asus/h610m-k.md b/Documentation/mainboard/asus/h610m-k.md new file mode 100644 index 00000000000..8ed9085870d --- /dev/null +++ b/Documentation/mainboard/asus/h610m-k.md @@ -0,0 +1,51 @@ +# ASUS PRIME H610M-K + +This is an entry level H610 mainboard from ASUS. + +## Variants + +- ASUS PRIME H610M-K: uses DDR5 RAM, unsupported (for now) +- ASUS PRIME H610M-K D4: uses DDR4 RAM, supported + +## Flashing + +This mainboard uses 3.3V SOIC-8 SPI flash IC with 16MiB of capacity. +The vendor firmware enables write protection, thus for initial installation +an external programmer is required. Thereafter, coreboot can be updated internally +using `flashrom -p internal`. + + +## Working + +- CPU is an i3-12000 +- DDR4 RAM in both slots +- USB ports +- SATA ports +- PCIe x16 slot +- M.2 slot +- Realtek gigabit ethernet +- ALC897 audio output +- HDMI audio output +- HDMI video output +- SeaBIOS boot into Ubuntu 24.04 +- Power states: S3, S5 +- Fan control +- Serial port + - coreboot console over serial + - Linux serial with IRQs + + +## Untested (should work) + +- PCIe x1 slot +- ALC897 audio input +- ALC897 SPDIF output +- VGA video output +- PS/2 keyboard +- Port 80 header +- RGB header + +## Unsupported + +- SPI TPM +- Intel PTT fTPM diff --git a/Documentation/mainboard/asus/h81m-k.md b/Documentation/mainboard/asus/h81m-k.md new file mode 100644 index 00000000000..e9450c99359 --- /dev/null +++ b/Documentation/mainboard/asus/h81m-k.md @@ -0,0 +1,119 @@ +# ASUS H81M-K + +This page describes how to run coreboot on the [ASUS H81M-K]. + +## Required proprietary blobs + +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin.md). + +## Building coreboot + +A fully working image should be possible just by setting your MAC +address and obtaining the Haswell mrc. You can set the basic config +with the following commands. However, it is strongly advised to use +`make menuconfig` afterwards (or instead), so that you can see all of +the settings. + +```bash +make distclean # Note: this will remove your current config, if it exists. +touch .config +./util/scripts/config --enable VENDOR_ASUS +./util/scripts/config --enable BOARD_ASUS_H81M_K +./util/scripts/config --enable HAVE_MRC +./util/scripts/config --set-str MRC_FILE "path/to/mrc.bin" +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in! +make olddefconfig +``` + +If you don't plan on using coreboot's serial console to collect logs, +you might want to disable it at this point (`./util/scripts/config +--disable CONSOLE_SERIAL`). It should reduce the boot time by several +seconds. However, a more flexible method is to change the console log +level from within an OS using `util/nvramtool`, or with the `nvramcui` +payload, which requires enabling CMOS options. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash cannot be written internally from stock bios. +To install coreboot for the first time, the flash chip must be removed and +flashed with an external programmer; flashing in-circuit doesn't work. +The flash chip is socketed, so it's easy to remove and reflash. Thereafter, +coreboot can be updated internally using `flashrom -p internal`. + +### External programming + +The flash chip is a 8 MiB socketed DIP-8 chip. Specifically, it's a +GigaDevice GD25B64C, whose datasheet can be found [here][GD25B64C]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.2.3 (Motherboard Layout) of the +[board manual], where the chip is labelled "64Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- There is no automatic, OS-independent fan control. This is because + the Super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, but the required driver doesn't exist + in coreboot. The `coretemp` driver can still be used for accurate CPU + temperature readings from an OS. + +Please also see [Known issues with Haswell](../../northbridge/intel/haswell/known-issues.md). + +## Working + +- USB +- S3 suspend/resume +- Gigabit Ethernet +- Wake-on-LAN +- PCIe +- integrated graphics +- graphics init with libgfxinit +- Discrete GPU with VGA Option ROM +- SATA +- hardware monitor (see [Known issues](#known-issues)) +- onboard audio +- PS/2 keyboard & mouse +- initialisation with Haswell mrc +- flashrom under coreboot +- Using `me_cleaner` +- Haswell NRI + +## Untested + +- parallel port +- EHCI debug +- infrared module +- serial port +- chassis intrusion header +- chassis speaker header +- front panel audio + + +## Technology + +```{eval-rst} ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/haswell/index` | ++------------------+--------------------------------------------------+ +| Southbridge | Intel Lynx Point (H81) | ++------------------+--------------------------------------------------+ +| CPU | Intel Haswell (LGA1150) | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT5539D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASUS H81M-K]: https://www.asus.com/motherboards-components/motherboards/business/h81mk/ +[GD25B64C]: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00092-GD25B64C-Rev2.1.pdf +[flashrom]: https://flashrom.org/ +[Board manual]: https://www.asus.com/motherboards-components/motherboards/business/h81mk/helpdesk_manual?model2Name=H81MK diff --git a/Documentation/mainboard/framework/marigold.md b/Documentation/mainboard/framework/marigold.md new file mode 100644 index 00000000000..c3927fb42d5 --- /dev/null +++ b/Documentation/mainboard/framework/marigold.md @@ -0,0 +1,105 @@ +# Framework Laptop 13 Intel Core Ultra Series 1 (Marigold) + +## Support Status + +This port is currently not officially supported by Framework. +It is a proof of concept for internal evaluation of the technical feasability +of coreboot at Framework. + +All mainboards sold to customers ship with BootGuard enabled. While it is +possible for end users to build the image with publicly available source and +binaries, flashing will not result in a bootable system. + +## Specs + +- CPU (full processor specs available at ) + - Intel Core Ultra Series 1 (Meteor Lake), one of: + - Ultra 5 125H, Ultra 7 155H, Ultra 7 165H +- EC + - Nuvoton NPCX 993 with Chrome EC firmware + - Backlit keyboard, with standard PS/2 keycodes and I2C HID hotkeys + - Battery + - Suspend / resume (S0ix, not S3) +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - HDMI video + - USB-C DisplayPort video +- Memory + - 2x SODIMM slots for up to 48GB DDR5-5600 each +- Networking + - AX210 M.2 2230 PCIe Gen3 x4 WiFi / Bluetooth +- Sound + - Realtek ALC285 HDA Codec + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - USB-C DisplayPort/HDMI audio +- Built-in devices + - I2C HID PTP Touchpad + - I2C HID ALS Sensor + - I2C HID Mediakeys + - Intel fTPM + - Intel RAPL power reporting + - USB Camera + - USB Fingerprint reader + - eSPI PS2 Keyboard + - eSPI PS2 emulated mouse/touchpad (if OS has no I2C driver) +- Storage + - M.2 2280 PCIe Gen4 x4 SSD +- 4 Type-C Ports + - USB 3.2 Gen 2x2 + - Thunderbolt 4 + - 100W USB PD 3.0 Charging + - DisplayPort 2.0 Alt-Mode + +### Build + +The following commands will build a working image: + +```bash +make distclean # Note: this will remove your current config, if it exists. +touch .config +./util/scripts/config --enable VENDOR_FRAMEWORK +./util/scripts/config --enable BOARD_FRAMEWORK_MARIGOLD +make olddefconfig +make -j$(nproc) +``` + +If you don’t plan on using coreboot’s serial console to collect logs, you might want to disable it at this point (./util/scripts/config --disable CONSOLE_SERIAL). It should reduce the boot time by several seconds. + +If you would like to boot your existing SSD with UEFI compatible Linux/Windows installation, enable EDK2 Payload (./util/scripts/config --enable PAYLOAD_EDK2). + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256JV | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | WSON-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Flashing example with BusPirate 5 connected to socketed ROM: + +``` +flashrom --ifd -i bios --noverify-all -w build/coreboot.rom --progress -p buspirate_spi:dev=/dev/ttyACM1,serialspeed=115200 +``` + +## Serial Console + +Serial console is available through JECDB header (unpopulated on MP) or Type-C CCD UART on the front right port. + +See [FrameworkDebugger](https://github.com/frameworkComputer/FrameworkDebugger) for details. diff --git a/Documentation/mainboard/framework/sakura.md b/Documentation/mainboard/framework/sakura.md new file mode 100644 index 00000000000..4f1e22586b6 --- /dev/null +++ b/Documentation/mainboard/framework/sakura.md @@ -0,0 +1,105 @@ +# Framework Laptop 13 Pro Intel Core Ultra Series 3 (Sakura) + +## Support Status + +This port is currently not officially supported by Framework. +It is a proof of concept for internal evaluation of the technical feasability +of coreboot at Framework. + +All mainboards sold to customers ship with BootGuard enabled. While it is +possible for end users to build the image with publicly available source and +binaries, flashing will not result in a bootable system. + +## Specs + +- CPU (full processor specs available at ) + - Intel Core Ultra Series 3 (Panther Lake), one of: + - Ultra 5, Ultra 7, Ultra 9 +- EC + - Nuvoton NPCX 993 with Framework forked Chrome EC firmware + - Backlit keyboard, with standard PS/2 keycodes and I2C HID hotkeys + - Battery + - Suspend / resume (S0ix, not S3) +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - HDMI video + - USB-C DisplayPort video +- Memory + - 1x LPCAMM2 slot for up to 96GB LPDDR5 +- Networking + - BE211 M.2 2230 CNVio3 WiFi / Bluetooth + - Or backwards compatible with PCIe Gen3 x2 WiFi, USB2 Bluetooth +- Sound + - Realtek ALC285 HDA Codec + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - USB-C DisplayPort/HDMI audio +- Built-in devices + - I2C HID Touchscreen + - I2C HID PTP Touchpad + - I2C HID ALS Sensor + - I2C HID Mediakeys + - Intel fTPM + - Intel RAPL power reporting + - USB Camera + - USB Fingerprint reader + - eSPI PS2 Keyboard + - eSPI PS2 emulated mouse/touchpad (if OS has no I2C driver) +- Storage + - M.2 2280 PCIe Gen5 x4 SSD +- 4 Type-C Ports + - USB 3.2 Gen 2x2 + - Thunderbolt 4 + - 100W USB PD 3.0 Charging + - DisplayPort 2.0 Alt-Mode + +### Build + +The following commands will build a working image: + +```bash +make distclean # Note: this will remove your current config, if it exists. +touch .config +./util/scripts/config --enable VENDOR_FRAMEWORK +./util/scripts/config --enable BOARD_FRAMEWORK_SAKURA +make olddefconfig +make -j$(nproc) +``` + +If you don’t plan on using coreboot’s serial console to collect logs, you might want to disable it at this point (./util/scripts/config --disable CONSOLE_SERIAL). It should reduce the boot time by several seconds. + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256JV | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | WSON-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Flashing example with BusPirate 5 connected to socketed ROM: + +``` +flashrom --ifd -i bios --noverify-all -w build/coreboot.rom --progress -p buspirate_spi:dev=/dev/ttyACM1,serialspeed=115200 +``` + +## Serial Console + +Serial console is available through JECDB header (unpopulated on MP) or Type-C CCD UART on the front right port. + +See [FrameworkDebugger](https://github.com/frameworkComputer/FrameworkDebugger) for details. diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md index a07d9d02c74..9429a92008c 100644 --- a/Documentation/mainboard/hp/hp_sure_start.md +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -7,6 +7,9 @@ It is implemented in HP notebooks since 2013, and desktops since 2015. This document talks about some mechanism of HP Sure Start on some machines, and the method to bypass it. +The method may no longer be applicable to more recent boards. HP has a later +[revision of the whitepaper] from 2019 and there may be others. + ## Laptops with SMSC MEC1322 embedded controller Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller. @@ -57,4 +60,5 @@ located at the high address of the flash chip (and in the protected region), we can leave it untouched, and do not need to extract the EC firmware to put it in the coreboot image. -[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 +[HP Sure Start Technical Whitepaper]: https://h10032.www1.hp.com/ctg/Manual/c05163901.pdf +[revision of the whitepaper]: https://h10032.www1.hp.com/ctg/Manual/c06216928.pdf diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a90e3f2396e..29f1c98ae2d 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -33,6 +33,7 @@ pademelon H77 Pro4-M H81M-HDS H110M-DVS +H370m-ITX/ac IMB-1222 ``` @@ -44,6 +45,7 @@ IMB-1222 A88XM-E F2A85-M H610i-PLUS D4 +H81M-K P2B-LS P3B-F P5Q @@ -56,6 +58,7 @@ P8Z77-M Pro P8Z77-V P8Z77-V LE PLUS wifigo_v1 +PRIME H610M-K D4 ``` ## Cavium @@ -116,6 +119,14 @@ FBG-1701 Monolith ``` +## Framework + +```{toctree} +:maxdepth: 1 + +Laptop 13 Intel Core Ultra Series 1 (Marigold) +Laptop 13 Intel Core Ultra Series 3 (Sakura) +``` ## Foxconn ```{toctree} @@ -195,12 +206,12 @@ M920 Tiny vboot ``` -### GM45 series +### GM45 / GM965 series ```{toctree} :maxdepth: 1 -X200 / T400 / T500 / X301 common +X200 / T400 / T500 / X301 / X61 common X301 ``` @@ -356,6 +367,7 @@ StarLite Mk IV StarLite Mk V StarBook Mk V StarBook Mk VI +StarBook Mk VI AMD StarBook Mk VII (N200) StarBook Mk VII (165H) StarBook Horizon diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/gm45_gm965_series.md similarity index 98% rename from Documentation/mainboard/lenovo/montevina_series.md rename to Documentation/mainboard/lenovo/gm45_gm965_series.md index 120a161e90e..a601b0b1f26 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/gm45_gm965_series.md @@ -1,4 +1,4 @@ -# Lenovo X200 / T400 / T500 / X301 common +# Lenovo X200 / T400 / T500 / X301 / X61 common These models are sold with either 8 MiB or 4 MiB flash chip. You can identify the chip in your machine through flashrom: @@ -26,7 +26,7 @@ touch any other regions: ``gbe`` region), so the process would be a little different for that model. ``` -On Montevina machines it's possible to disable ME and remove its firmware from +On these machines it's possible to disable ME and remove its firmware from SPI flash by modifying the flash descriptor. This also makes it possible to use the flash region the ME used for `bios` region, allowing for much larger payloads. diff --git a/Documentation/mainboard/starlabs/starbook_czn.md b/Documentation/mainboard/starlabs/starbook_czn.md new file mode 100644 index 00000000000..889fc027926 --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_czn.md @@ -0,0 +1,89 @@ +# StarBook Mk VI (Ryzen 7 5800U) + +## Specs + +- CPU (full processor specs available at ) + - AMD Ryzen 7 5800U (Cezanne) +- EC + - ITE IT5570E (Star Labs Merlin EC) + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - USB-C PD charger + - Suspend / resume (S3) +- GPU + - Integrated AMD Radeon Graphics + - eDP internal display + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR4 SODIMM +- Networking + - M.2 2230 WLAN (PCIe) + - Bluetooth (internal USB) +- Sound + - Conexant CX20632 (HDA) + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 2280 NVMe SSD + - M.2 SATA SSD + - Micro-SD card reader +- USB + - Camera (internal USB) + - Fingerprint reader (internal USB) + - USB 3.x Type-A ports (left + right) + - USB Type-C port (USB + DisplayPort alt-mode) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_czn` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* AMD Cezanne PSP/SMU firmware binaries (used by `src/mainboard/starlabs/cezanne/fw.cfg`) +* ITE Embedded Controller firmware (ec.bin) + +If you enable `CONFIG_ADD_APCB_SOURCES`, additional APCB files are required (see `src/mainboard/starlabs/cezanne/Makefile.mk`). + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_czn +make +``` + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q128JW | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index c24305eb7ed..2f31da377a2 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -27,87 +27,10 @@ Now, place `mrc.bin` in the root of the coreboot directory. Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to its location when building coreboot. -## SPD Addresses - -When porting a board from vendor firmware, the SPD addresses can be obtained -through `i2c-tools`, which can be found in many GNU/Linux distributions. A more -[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of -the procedure and beyond can be found in -[Hannu Hartikainen's blog](https://hannuhartikainen.fi). - -First load the kernel modules: - -```bash -modprobe i2c-dev -modprobe eeprom -``` - -Find the SMBus and the addresses of the DIMM's EEPROMs (example output): -```bash -$ decode-dimms | grep Decoding -Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 -Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 -``` - -Alternatively, look at the sys filesystem: -```bash -$ ls -l /sys/bus/i2c/drivers/eeprom/ -total 0 -lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ -lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ -lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ ---w------- 1 root root 4096 Apr 4 01:47 bind -lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ ---w------- 1 root root 4096 Apr 4 01:46 uevent ---w------- 1 root root 4096 Apr 4 01:47 unbind -``` - -The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. -Note that the above values are actually hex values. - -You can check the correctness of the SMBus and the addresses of the EEPROMs via -`i2cdetect`: - -```bash -$ i2cdetect -l -i2c-3 unknown i915 gmbus dpc N/A -i2c-1 unknown i915 gmbus vga N/A -i2c-6 unknown DPDDC-A N/A -i2c-4 unknown i915 gmbus dpb N/A -i2c-2 unknown i915 gmbus panel N/A -i2c-0 unknown i915 gmbus ssc N/A -i2c-7 unknown SMBus I801 adapter at f040 N/A -i2c-5 unknown i915 gmbus dpd N/A -``` - -Probing the SMBus: - -```bash -$ i2cdetect -r 7 -WARNING! This program can confuse your I2C bus, cause data loss and worse! -I will probe file /dev/i2c-7 using receive byte commands. -I will probe address range 0x03-0x77. -Continue? [Y/n] - 0 1 2 3 4 5 6 7 8 9 a b c d e f -00: -- -- -- -- -- -- -- -- -- -- -- -- -- -10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- -50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- -60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -70: -- -- -- -- -- -- -- -- -``` - -The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied -by 2. For example, if the addresses read through `i2c-tools` when booted from -vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and -`0xa4`. This is because the I2C addresses are 7 bits long. - ## ECC DRAM When `mrc.bin` has finished executing, ECC is active on the channels populated with ECC DIMMs. However, `mrc.bin` was tailored specifically -for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM. +for Haswell Chromebooks and Chromeboxes, none of which support ECC DRAM. While ECC likely functions correctly, it is advised to further validate the correct operation of ECC if data integrity is absolutely critical. diff --git a/Documentation/releases/coreboot-26.03-relnotes.md b/Documentation/releases/coreboot-26.03-relnotes.md index 6e302db11e3..fc7c82fd160 100644 --- a/Documentation/releases/coreboot-26.03-relnotes.md +++ b/Documentation/releases/coreboot-26.03-relnotes.md @@ -1,8 +1,8 @@ -Upcoming release - coreboot 26.03 +coreboot 26.03 release ======================================================================== The coreboot project is pleased to announce the release of coreboot 26.03. -This release incorporates 856 commits from 95 contributors, reflecting +This release incorporates 876 commits from 95 contributors, reflecting continued focus on runtime configuration, security hardening, platform enablement, and memory/display data reliability across supported systems. @@ -218,15 +218,15 @@ Platform Updates Statistics from the 25.12 to the 26.03 release -------------------------------------------- -* Total Commits: 856 -* Average Commits per day: 9.42 -* Total lines added: 107457 -* Average lines added per commit: 125.53 -* Number of patches adding more than 100 lines: 72 -* Average lines added per small commit: 41.11 -* Total lines removed: 22154 -* Average lines removed per commit: 25.88 -* Total difference between added and removed: 85303 +* Total Commits: 876 +* Average Commits per day: 9.53 +* Total lines added: 113570 +* Average lines added per commit: 129.65 +* Number of patches adding more than 100 lines: 78 +* Average lines added per small commit: 40.96 +* Total lines removed: 22309 +* Average lines removed per commit: 25.47 +* Total difference between added and removed: 91261 * Total authors: 95 diff --git a/Documentation/releases/coreboot-26.06-relnotes.md b/Documentation/releases/coreboot-26.06-relnotes.md index 4f89398649a..22d6cdaadd2 100644 --- a/Documentation/releases/coreboot-26.06-relnotes.md +++ b/Documentation/releases/coreboot-26.06-relnotes.md @@ -1,37 +1,247 @@ Upcoming release - coreboot 26.06 ======================================================================== -The 26.06 release is scheduled for the end of June, 2026 +The coreboot project is pleased to announce the release of coreboot +26.06. In the roughly three months since the 26.03 release, 101 authors +(including 22 new authors) have landed well over a thousand commits of +new features, platform enablement, cleanup, and bug fixes across the +tree. +This release exists because of the people who wrote, reviewed, tested, +and reported against it. Thank you. Whether you landed a new SoC port or +fixed a single typo, your work is in here, and the project is better for +it. -Update this document with changes that should be in the release notes. - -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. -* Note that all changes before the release are done are marked upcoming. - A final version of the notes are done after the release. +The next coreboot release, 26.09, is scheduled for the end of September +2026. Significant or interesting changes ---------------------------------- -* Add changes that need a full description here - -* This section should have full descriptions and can or should have - a link to the referenced commits. +### soc/intel/novalake: Initial Nova Lake SoC support + +This release lays down the foundation for Intel's Nova Lake (NVL) +platform. The SoC was brought up in stages, with separate commits taking +the code through bootblock (5fd6ad6644), romstage (a8c9ecfaa9), and +ramstage (cfa90f7a03), followed by FSP-M (0beffbd0be) and FSP-S +(a6798f2eb5) programming. GPIO definitions (0abe0a6f0b) and the SoC ACPI +directory (9b6d29c2ec) round out the basic enablement. + +Several supporting pieces landed alongside the core code. The chipset.cb +mechanism is used to link PCIe root port operations (1945d07700), the +Intel Flash Descriptor chipset is configured (0f171a217f), and IOC 1MB +LGMR support is enabled (2a2ab9e0cc). The heap size was increased to +make room for high-quality firmware splash rendering (fabe57c3f7). +Tooling keeps pace as well: the NVL FSP headers were imported from +v3150.22 (e6bc275fdb), ifdtool gained NVL support under IFD2 +(2f9ab09057), and spd_tools learned about the Nova Lake SoC +(61dc9a4916). + +Note that this is early enablement work. DDR5 is not yet supported, and +some FSP workarounds remain in place pending upstream FSP fixes. The +Google Atria baseboard and its variants were also migrated from the +Panther Lake SoC to Nova Lake during this cycle as the bring-up matured +(cff044285b). + + +### soc/amd/strix_halo: Initial Strix Halo SoC support + +AMD's Strix Halo SoC received its first code in this cycle. The initial +commit (ee148cc689) introduces the SoC based on a rename of glinda, and +subsequent patches adjust it for the new part: the maximum CPU count was +tuned (c108ccb930), the fw.cfg was adapted (29f93567c5), the APOB region +was grown from 256K to 576K (eedd292f32), and the CPUID match was +updated (7982c6e172). A dummy FSP was added to keep builds working until +the real binaries are available (bddc56d7fe), and the VBIOS path was +hooked up (d381d33a39). The new SoC also picked up maintainers +(847b42fa69). + +The first board to use Strix Halo is the AMD Maple reference mainboard, +introduced in this release (47f124abba) with its EC, GPIO, and blob +plumbing (7f8e7842fc, d5d8446831, 995eb78c64). As with Nova Lake, this +is work-in-progress enablement and is not yet intended for use on real +hardware. + + +### soc/qualcomm/calypso: Initial Calypso SoC support + +The Qualcomm Calypso SoC was bootstrapped from the X1P42100 codebase +with SoC-specific pieces removed, providing a foundation for incremental +development (38e8eadfa7). From that skeleton the platform gained ARM +Trusted Firmware support (230f210d2d), basic PCIe (30b8524ff5), QUPv3 +clock initialization (e4cae1a62b) and Serial Engine entries +(8dbf88a300), the SPMI driver in romstage and ramstage (49e3595e1f), and +QSPI/QUPv3 bring-up in the bootblock (421c21c6cf). + +Firmware loading and memory layout were fleshed out with CPUCP and PDP +firmware loading (192fdf75e0), a split of the CPUCP binary into RO and +RW regions (1c79360b44), CBFS preloading for BL31 and BL32 (03aaebef7e), +and memory layout alignment for the new SoC (22a67b77d6, 6995ef7c91). +Calypso is consumed by the new Google Calypso, Mensa, and C1nv +mainboards; the directory itself was renamed from the earlier "mensa" +directory as the work matured (201392d363, e187893fa9). + + +### security/amd: ROM Armor 2 and A/B recovery infrastructure + +AMD platforms gained a substantial expansion of firmware-integrity and +recovery tooling. ROM Armor 2 support was implemented in the PSP common +block (16a69e9619), backed by a PSP mailbox interface (8121a3dd72), +HSTI- based state reporting (cd8072191d), and enforcement checks in the +SPI path (3bc8a9fec1, 2ff5b9c0ff, d72d7d1ba0). The PSP now talks to the +SPI controller through the ROM Armor mailbox interface (c4bd58b02d), and +the AMD fTPM driver learned to operate under ROM Armor with backup SPI +flash support (63fff936cd, 3a87b84f7c). + +In parallel, A/B recovery support was added at the SoC level +(4ca21336b4), introducing a new FMAP layout with EFS, RECOVERY_A, and +RECOVERY_B partitions. The PSP gained commands for A/B recovery +(492b7c7c09), the ability to boot from a second flash device +(b6385bcf0d), and logic to preserve the recovery flag across boots +(2059d08bbf). Cezanne was the first SoC wired up for the new flow with +A/B recovery and PSP_AB_NVRAM support (f78ba958e5, 302ea069ef). On the +tooling side, amdfwtool learned to split the A/B level 2 directory from +PSP level 1 (ac8bd296ee) and fix backup PSP L1 generation (dee0bfdbc0), +while amdfwread gained A/B recovery parsing (0aaeff81e3). + + +### mb/google: Qualcomm mobile charging and battery management + +The Qualcomm-based Google Bluey and Calypso boards received an extensive +set of charging, battery, and low-power-boot improvements. Calypso +gained a charging framework (07ce3b92a0) and a low-power charging boot +sequence (ae5b0d713c), while Bluey implemented slow-to-fast charging +transition logic (eda62af9dd), falling back to slow charging when the +battery is below 2% (8e57010d88) and monitoring thermal sensors +throughout the charging process (86b3901ba5). + +Robustness in degraded power states was a recurring theme. Bluey now +handles a dedicated "no-battery" boot mode (9dc937c982), carries dead +battery boot-flag configuration (2115ec3b4a), and includes battery +ship-mode and cutoff recovery handling in romstage (d300ef280c, +17b825ae1c). Boot mode and battery status are cached early and reused to +streamline mainboard init (99b53e5a84, 7c75b0655f), and NVMe power +sequencing was optimized in romstage to bring the rail up earlier +(69f0093d54, 38addfb24f). Several of these behaviors were iterated on +through the cycle, including reverts that backed out boot-count and +reboot changes pending further work (a2f401da5b, 0b2d5a6e7a). + + +### nb/intel/haswell: Broadwell enablement and CPU power tuning + +Two goals drove this work: unifying the Haswell and Broadwell codebases, +and getting Broadwell "trad" (non-ULT) parts working in coreboot. The +latter only works with native raminit (NRI), since neither the Haswell +nor the Broadwell MRC supports those parts. As part of this effort, +Broadwell's native graphics init was backported to Haswell: the driver +gained Broadwell device IDs (6e95ade0cb), GT power-management init +(aa9ff8895f), and CDCLK programming (f7412bf209), along with a series of +cleanups that bring the two graphics paths closer together (b75d086f86, +892d68a8c8, f2e24e5230). + +On the CPU side, a new OC mailbox undervolt driver was introduced +(fa68b66686) and wired up for Haswell (aaa396d571), Skylake +(e9239d2308), and Cannonlake (1654e0a1de). Haswell also gained +option-backed PL1/PL2 power-limit overrides with package-limit locking +(1dc346e61e) and now finalizes the CPU in ramstage (f841e98bca). This +work pairs with a wave of newly added ASUS Haswell-era boards, including +the Maximus VI and VII series, the Z87-K, and the H81M-K. + + +### soc/intel/pantherlake: Initial Panther Lake SoC and baseboard support + +Intel's Panther Lake (PTL) SoC enablement saw significant development +this cycle, alongside extensive work on the Google Fatcat and Ocelot +reference platforms. The core SoC gained UFS inline encryption support +(dfe5b08978), CNVi WWAN coexistence (d9956b0bcf), VCCSA shutdown +mitigation (eeca9d6f77), and transitioned to a common CBFS preload +implementation (084a7ea69c). + +At the board level, the Google Fatcat and Ocelot baseboards and their +variants (ruby, lapis, moonstone, etc.) received major feature +additions. Highlights include lid-closed power-off options (a5d2a225a1), +tablet-mode support, active display limiting for portrait panels +(a5fb73a737), and dedicated UFS inline encryption enablement across +multiple board variants. Additional coreboot changes --------------------------- -The following are changes across a number of patches, or changes worth -noting, but not needing a full description. - -* Changes that only need a line or two of description go here. +* The Lynx Point and Wildcat Point southbridges were heavily unified, + with Wildcat Point now reusing Lynx Point's ME, PCIe, HDA, PMC, and + SMI code rather than maintaining its own copies (1f376aebde, + ffce7b6ae7, 73b325e337, 82b7a33abf, 23de5b5288). The shared ME path + also picked up Wildcat Point finalisation and a use-after-free fix + along the way (f64c1fb9c3, 574c7e116d). +* Continued progress on C23 compatibility, replacing `__typeof__` with + `typeof` treewide (b084eef118) and applying the `nonstring` attribute + to unterminated string buffers (e57478e238). +* `WARNINGS_ARE_ERRORS` was removed treewide (e8a3bb81db), simplifying + the build configuration. +* SPI flash handling gained JEDEC SFDP parsing (67845716da) and now uses + larger block erases where possible (95edd07bca). +* Boot performance work continued with cooperative-multitasking support + on arm64 (2227096f55), optimized cached LZMA decompression + (cd7f369416), ROM3 caching on AMD (72da5e8f41), and microcode caching + in DRAM on Intel (bc61158f64). +* Default FMAP generation was reworked, and the x86 FMAP region size was + increased from 0x200 to 0x1000 to accommodate larger layouts + (5b71cd5f15, d55ed29d85). +* The Intel FSP 2.0 driver gained Zstd decompression support + (bc7976277b). +* Support was added for secondary-resolution boot splash logos, letting + boards pick a logo based on panel resolution (5b811635e7). +* The Realtek r8168 driver had its ERI programming reworked and a stale + Kconfig option dropped (0c5d76977c), and a shared Nuvoton HWM + fan-control helper was introduced for Super I/O boards (a46373fcfa). +* Lenovo H8-based ThinkPads gained FnLock and logo LED control + (b01c7d6642, cf541343a9), alongside improved ThinkLight, keyboard + backlight and primary Fn-key handling (07981ca1c0, 6078f59a7c). + Additionally, ACPI battery power units were fixed and basic charge + behaviour was added to supported models (a06042792d, b247bf183d). +* Star Labs boards picked up CFR-based power-profile and per-port PCIe + power-management controls (046a35f84f, 6f3c6558f3, 21c424ae9a). +* In-Band ECC (IBECC) can now be controlled at runtime: the FSP enable + bit is driven from an option backend rather than only the devicetree + on Alder Lake, Elkhart Lake, Meteor Lake, and Tiger Lake + (c2d06ca3be), and Star Labs boards expose it through CFR (0c555f171d). +* Apollo Lake and Gemini Lake gained a native IFWI stitcher that + assembles the final flash image from Kconfig-selected descriptor, CSE + image, and signing inputs using OpenSSL, without invoking Intel FIT or + MEU (00793280d1). +* AMD platforms can keep the ACP XTAL running in S0i3 via a new Kconfig, + allowing wake from sources such as a microphone (241287f596, + 41f67ad2a7, 7d474cda77), with Jaguar opting in (8df29f19d7). +* MediaTek common code added a shared resource mutex for DMA safety + (5b49e6d976), and the RISC-V QEMU target now initializes its PCI root + bus (f1e95c5536). +* Qualcomm common code received major updates, adding support for PCIe + Gen5 (687780fca9), delta DCB loading (589ff5b60b), and asynchronous + PCIe initialization. +* The Qualcomm X1P42100 SoC matured substantially, gaining eDP display + support (c6e0f28814), runtime SoC identification (574166edf9), support + for both Hamoa and X1P42100 firmware blobs in CBFS (2ac9b3d715), and + PCIe endpoint power-off (2a6b546ca2). +* amdfwtool saw a large cleanup and modernization pass: combo support + was dropped (c3a82354fa), the config file and `--location` argument + became mandatory (8c7c9ad484, 02579e43be), platform-specific quirks + were moved into a dedicated file (5ffe9ff224), AIFv1 BIOS directory + tables are now supported (c3e0cb75fa), and the Mullins platform was + added (e9487cafa0). amdfwread additionally gained UEFI image parsing + (2c43cd5be0). +* Retro-enablement continued with the addition of support for the Intel + GM965 northbridge (Core 2 Duo era), including MRC cache for fast boot + and SMBIOS memory information setup (6457201fe6, c094305a92). +* Numerous platform-specific enhancements across Intel, AMD, MediaTek, + and Qualcomm SoCs, including additional setup options, + power-management tuning, and memory-initialization fixes. +* The libpayload library saw arm64 fixes, adding the pre-allocated + framebuffer to its used-memory ranges (5c77449b8b) and correcting an + unrecognized linker option in its Makefile (82de37d171). @@ -40,49 +250,97 @@ Changes to external resources ### Toolchain updates +* Update GCC from 14.2.0 to 15.2.0 (e518885dce) +* Update NASM from 2.16.03 to 3.01 (5267cae13a), with a fix for a + parallel-build race in the nasm crossgcc build (ced4028bff) +* Update binutils from 2.45 to 2.45.1 (b6ca7755f3) +* Update ACPICA from 20250807 to 20251212 (3ef459a968) ### Git submodule pointers +* amd_blobs: Update from commit id 0a6d270fb3 to 588da8d6de (2 commits) +* fsp: Update from commit id 81399b3b61 to ca4f8b702d (13 commits) +* intel-microcode: Update from commit 250941fb67 to 98f8d817ca (1 + commit) + ### External payloads +* edk2 builds a local FMP certificate PCD in support of capsule updates + (4064b5de37), with the serial driver disabled when serial output is + off (f71e7624c4), and the default MrChromebox branch was updated from + 2511 to 2603 (25d3809ea3). + Platform Updates ---------------- -### Added mainboards: -* To be filled in immediately before the release by the release team - - -### Removed Mainboards -* To be filled in immediately before the release by the release team - - -### Updated SoCs -* To be filled in immediately before the release by the release team - - - -Plans to move platform support to a branch ------------------------------------------- -* To be filled in immediately before the release by the release team +### Added mainboards + +* AMD Crater for V2000A SoC +* AMD Jaguar for Faegan SoC +* AMD Maple for Strix Halo SoC +* ASRock H370M-ITX/ac +* ASRock Z87 Extreme6 +* ASUS H81M-K +* ASUS Maximus VI EXTREME +* ASUS Maximus VI FORMULA +* ASUS Maximus VI HERO +* ASUS Maximus VII IMPACT +* ASUS Maximus VI IMPACT +* ASUS Maximus VII RANGER +* ASUS P8H61-I R2.0 +* ASUS P8H61-M LX2 +* ASUS PRIME H610M-K D4 +* ASUS Z87-K +* Framework Laptop 13 (Intel Core Ultra Series 1) +* Framework Laptop 13 Pro (Intel Core Ultra Series 3) +* Google Atria +* Google C1nv +* Google Calypso +* Google Dirkson +* Google Mensa +* Google Penghu +* Google R2d2 +* Google Sheev +* Lenovo ThinkPad X61 / X61s +* Star Labs Star Labs Byte Mk I (Ryzen 7 5800U) +* Star Labs Star Labs StarBook Mk VI (Ryzen 7 5800U) +* System76 bonw15-b +* System76 gaze20 + + +### Removed mainboards + +* AMD Crater (Renoir) — replaced by AMD Crater for V2000A SoC +* Google Myst + + +## SoC Changes + +* added amd/strix_halo +* added intel/novalake +* added intel/pantherlake +* added qualcomm/calypso Statistics from the 26.03 to the 26.06 release -------------------------------------------- -* To be filled in immediately before the release by the release team - - - -Significant Known and Open Issues ---------------------------------- - -Issues from the coreboot bugtracker: -* To be filled in immediately before the release by the release team +* Total Commits: 1141 +* Average Commits per day: 12.61 +* Total lines added: 121779 +* Average lines added per commit: 106.73 +* Number of patches adding more than 100 lines: 114 +* Average lines added per small commit: 37.88 +* Total lines removed: 20660 +* Average lines removed per commit: 18.11 +* Total difference between added and removed: 101119 +* Total authors: 101 +* New authors: 22 coreboot Links and Contact Information diff --git a/Documentation/releases/coreboot-26.09-relnotes.md b/Documentation/releases/coreboot-26.09-relnotes.md new file mode 100644 index 00000000000..2d3bec06562 --- /dev/null +++ b/Documentation/releases/coreboot-26.09-relnotes.md @@ -0,0 +1,90 @@ +Upcoming release - coreboot 26.09 +======================================================================== + +The 26.09 release is scheduled for late September, 2026 + + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. +* Note that all changes before the release are done are marked upcoming. + A final version of the notes are done after the release. + + + +Significant or interesting changes +---------------------------------- + +* Add changes that need a full description here + +* This section should have full descriptions and can or should have + a link to the referenced commits. + + + +Additional coreboot changes +--------------------------- + +The following are changes across a number of patches, or changes worth +noting, but not needing a full description. + +* Changes that only need a line or two of description go here. + + + +Changes to external resources +----------------------------- + +### Toolchain updates + + + +### Git submodule pointers + + + +### External payloads + + + +Platform Updates +---------------- + +### Added mainboards: +* To be filled in immediately before the release by the release team + + +### Removed Mainboards +* To be filled in immediately before the release by the release team + + +### Updated SoCs +* To be filled in immediately before the release by the release team + + + +Plans to move platform support to a branch +------------------------------------------ +* To be filled in immediately before the release by the release team + + + +Statistics from the 26.06 to the 26.09 release +-------------------------------------------- +* To be filled in immediately before the release by the release team + + + +coreboot Links and Contact Information +-------------------------------------- + +* Main Web site: +* Downloads: +* Source control: +* Documentation: +* Issue tracker: +* Donations: + diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 5f7d9347f19..42ca16093c9 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -6,7 +6,7 @@ Please add to the release notes as changes are added: ```{toctree} :maxdepth: 1 -26.06 - June 2026 +26.09 - September 2026 ``` The [checklist] contains instructions to ensure that a release covers all @@ -22,6 +22,7 @@ important is taken care of. ```{toctree} :maxdepth: 1 +26.06 - June 2026 26.03 - March 2026 25.12 - December 2025 25.09 - September 2025 diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 77a79547073..69f40a98103 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -4,10 +4,8 @@ - Birman for Phoenix SoC using FSP - Birman for Phoenix SoC using openSIL - Birman for Glinda SoC -- BirmanPlus for Phoenix SoC -- BirmanPlus for Glinda SoC - Chausie -- Crater for Renoir SoC +- Crater for V2000A SoC - Majolica - Mayan for Phoenix SoC @@ -26,6 +24,8 @@ - Asurada - Hayato (ASUS Chromebook Flip CM3 (CM3200)) - Spherion (Acer Chromebook 514 (CB514-2H, CB514-2HT)) +- Atria +- Penghu - Auron_Paine (Acer C740 Chromebook) - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531)) - Buddy (Acer Chromebase 24) @@ -65,6 +65,7 @@ - Constitution (Google Meet Series Two) - Crota (Multiple devices - See help text) - Dirks (Acer Chromebox Mini CXM2 (TWL)) +- Dirkson - Dochi (Acer Chromebook Plus Spin 514) - Domika (Multiple devices - See help text) - Felwinter (ASUS Chromebook Flip CX5(CX5601)) @@ -134,6 +135,9 @@ - Epic - Pujjocento - Butterfly (HP Pavilion Chromebook 14) +- Calypso +- Mensa +- C1nv - Cherry - Dojo (HP Chromebook x360 (13b-ca0002sa)) - Tomato (Acer Chromebook Spin 513 (CP513-2H)) @@ -255,7 +259,6 @@ - Pico (Acer Chromebook Spin 311) - Link (Google Chromebook Pixel (2013)) - Mistral -- Myst - Nyan - Nyan Big (Acer Chromebook 13 (CB5-311)) - Nyan Blaze (HP Chromebook 14 G3) @@ -331,6 +334,8 @@ - Mace - Obiwan - Padme +- R2d2 +- Sheev - Skywalker - Tarkin - Vader @@ -470,6 +475,7 @@ - ThinkPad X230s - ThinkPad X230 eDP Mod (2K/FHD) - ThinkPad X60 / X60s / X60t +- ThinkPad X61 / X61s ## MSI - PRO Z690-A (WIFI) DDR4 diff --git a/Documentation/soc/intel/redundancy.md b/Documentation/soc/intel/redundancy.md index bd3a92aaa53..b40a2faa573 100644 --- a/Documentation/soc/intel/redundancy.md +++ b/Documentation/soc/intel/redundancy.md @@ -28,19 +28,19 @@ implementation for example has been developed basing mainly on ADL-P EDS Vol The implementation assumes four FMAP regions that are CBFS formatted and that use the following names. -The bootblocks live in `BOOTBLOCK` and `TOPSWAP`. Each of these is a relatively +The bootblocks live in `BOOTBLOCK` and `BOOTBLOCK_B`. Each of these is a relatively small CBFS region that contains a bootblock image and any additional files that must reside next to it for early boot on a given platform. These regions must exist in the board's `.fmd` file and must be sized with headroom for growth - keeping in mind the FIT table and Boot Guard ACM's must reside in the same region as the bootblock. -The main firmware CBFS regions are `COREBOOT` and `COREBOOT_TS`. `COREBOOT` is +The main firmware CBFS regions are `COREBOOT` and `COREBOOT_B`. `COREBOOT` is typically the base slot and is often placed under write protection, along with -`BOOTBLOCK`. `COREBOOT_TS` is the alternate slot and is typically left writable -so it can be replaced by an update mechanism, along with `TOPSWAP`. +`BOOTBLOCK`. `COREBOOT_B` is the alternate slot and is typically left writable +so it can be replaced by an update mechanism, along with `BOOTBLOCK_B`. -The `BOOTBLOCK` and `TOPSWAP` regions are expected to be placed in the +The `BOOTBLOCK` and `BOOTBLOCK_B` regions are expected to be placed in the flash area covered by the Top Swap configuration. The sizes of the regions must match and be equal to the corresponding field in the IFD. coreboot can adjust the The Top Swap size (also called Top Swap Block Size in @@ -56,8 +56,8 @@ bootblock. The option `CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS` changes where the bootblocks are stored. When it is disabled, both are stored in the primary CBFS region as on existing platforms. When it is enabled, they are placed in the `BOOTBLOCK` -`TOPSWAP` FMAP regions. It also places copies of the following stages and -required files from the `COREBOOT` region in the `COREBOOT_TS` region. +`BOOTBLOCK_B` FMAP regions. It also places copies of the following stages and +required files from the `COREBOOT` region in the `COREBOOT_B` region. If CBFS verification is enabled, the image build checks verification status for all main CBFS regions that are part of the redundancy configuration, not only @@ -117,7 +117,7 @@ behavior. Intel Top Swap platforms provide a strong definition of `cbfs_fmap_region_hint()` in `src/soc/intel/common/block/rtc/rtc.c`. When `CONFIG_INTEL_TOP_SWAP_OPTION_CONTROL` is enabled and the Top Swap control -bit is set, it returns `COREBOOT_TS`. Otherwise it returns `COREBOOT`. +bit is set, it returns `COREBOOT_B`. Otherwise it returns `COREBOOT`. `cbfs_get_boot_device()` logs the selected region and stops with an error if the region cannot be found in FMAP. @@ -138,7 +138,7 @@ A typical update and rollback sequence is as follows. The platform starts in slot A with Top Swap disabled. The hardware boots from the `BOOTBLOCK` and coreboot continues from the `COREBOOT` CBFS region. -An update writes into the `TOPSWAP` and `COREBOOT_TS` regions, then sets the +An update writes into the `BOOTBLOCK_B` and `COREBOOT_B` regions, then sets the `attempt_slot_b` CMOS option. On the next boot, `sync_rtc_buc_top_swap()` observes that the CMOS request @@ -147,7 +147,7 @@ state, and resets the platform. After the reset, the hardware starts from the bootblock corresponding to the new Top Swap state. When coreboot later initializes its boot device, -`cbfs_fmap_region_hint()` sees the Top Swap state and selects `COREBOOT_TS`, so +`cbfs_fmap_region_hint()` sees the Top Swap state and selects `COREBOOT_B`, so the remainder of the boot uses the updated slot. Clearing CMOS or resetting `attempt_slot_b` triggers the same sequence in the @@ -165,7 +165,7 @@ block implementation providing `cbfs_fmap_region_hint()` is linked into the stage that performs CBFS initialization on your platform. If the build fails to boot after enabling separate regions, confirm that the -`.fmd` file defines `BOOTBLOCK`, `TOPSWAP`, `COREBOOT`, and `COREBOOT_TS` as +`.fmd` file defines `BOOTBLOCK`, `BOOTBLOCK_B`, `COREBOOT`, and `COREBOOT_B` as CBFS regions and that the platform Top Swap configuration matches the reserved bootblock and Top Swap region placement and sizing. diff --git a/MAINTAINERS b/MAINTAINERS index bd26cac7f4b..595f53fa09c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -297,6 +297,13 @@ F: src/mainboard/facebook/monolith/ +FRAMEWORK MAINBOARDS +M: Daniel Schaefer +S: Maintained +F: src/mainboard/framework/ + + + FOXCONN MAINBOARDS S: Orphan F: src/mainboard/foxconn/ @@ -332,6 +339,7 @@ M: Kapil Porwal M: Jakub Czapiga M: Eran Mitrani M: Dinesh Gehlot +M: Matt DeVillier S: Maintained F: src/mainboard/google/rex/ @@ -342,6 +350,7 @@ M: Eric Lai M: Kapil Porwal M: Dinesh Gehlot M: Jayvik Desai +M: Matt DeVillier S: Maintained F: src/mainboard/google/brya/ @@ -357,6 +366,7 @@ F: src/mainboard/google/fatcat/ GOOGLE HATCH MAINBOARDS M: Subrata Banik M: Nick Vaccaro +M: Matt DeVillier S: Maintained F: src/mainboard/google/hatch/ @@ -368,11 +378,12 @@ F: src/mainboard/google/ocelot/ GOOGLE VOLTEER MAINBOARDS M: Nick Vaccaro +M: Matt DeVillier S: Maintained F: src/mainboard/google/volteer/ GOOGLE MAINBOARDS (Intel-based, legacy/inactive) -M: Matt DeVillier +M: Matt DeVillier S: Maintained F: src/mainboard/google/auron/ F: src/mainboard/google/beltino/ @@ -599,7 +610,7 @@ F: src/mainboard/roda/ SAMSUNG CHROMEOS MAINBOARDS -M: Matt DeVillier +M: Matt DeVillier S: Maintained F: src/mainboard/samsung/lumpy/ F: src/mainboard/samsung/stumpy/ @@ -635,7 +646,6 @@ F: src/mainboard/sifive/ STAR LABS MAINBOARDS M: Sean Rhodes -M: Matt DeVillier S: Maintained F: src/mainboard/starlabs/ @@ -877,6 +887,14 @@ M: Felix Held S: Odd Fixes F: src/soc/amd/stoneyridge/ +AMD Strix Halo +M: Anand Vaikar +M: David Milosevic +M: Felix Held +S: Maintained +F: src/soc/amd/strix_halo/ +F: src/vendorcode/amd/fsp/strix_halo/ + INTEL ALDERLAKE SOC M: Subrata Banik M: Nick Vaccaro @@ -970,6 +988,7 @@ MEDIATEK SOCS M: Hung-Te Lin M: Yu-Ping Wu M: Yidi Lin +M: Chen-Tsung Hsieh S: Supported F: src/soc/mediatek/ @@ -1222,7 +1241,7 @@ M: Felix Singer M: Jason Glenesk M: Angel Pons M: Martin Roth -M: Matt DeVillier +M: Matt DeVillier S: Maintained F: Documentation/releases/ F: util/release/ diff --git a/Makefile.mk b/Makefile.mk index b5e988195f7..eabec35530e 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -555,6 +555,7 @@ CFLAGS_common += -ffunction-sections CFLAGS_common += -fdata-sections CFLAGS_common += -fno-pie CFLAGS_common += -Wstring-compare +CFLAGS_common += -Werror ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_common += -Wold-style-declaration CFLAGS_common += -Wcast-function-type @@ -636,9 +637,6 @@ LDFLAGS_common += -static LDFLAGS_common += -z noexecstack LDFLAGS_common += --emit-relocs -ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) -CFLAGS_common += -Werror -endif ifneq ($(GDB_DEBUG),) CFLAGS_common += -Og ADAFLAGS_common += -Og @@ -988,9 +986,13 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) else -CBFS_REGIONS := COREBOOT,COREBOOT_TS +CBFS_REGIONS := COREBOOT,COREBOOT_B endif endif +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) +CBFS_REGIONS := COREBOOT,COREBOOT_B +endif + CBFS_REGION_COUNT := $(words $(subst $(comma),$(spc),$(CBFS_REGIONS))) @@ -1109,38 +1111,13 @@ FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE) ifeq ($(CONFIG_ARCH_X86),y) -DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd -# check if IFD_CHIPSET is set and if yes generate a FMAP template from IFD descriptor -ifneq ($(CONFIG_IFD_CHIPSET),) -ifeq ($(CONFIG_HAVE_IFD_BIN),y) -DEFAULT_FLASHMAP:=$(obj)/fmap-template.fmd -$(DEFAULT_FLASHMAP): $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) $(IFDTOOL) - echo " IFDTOOL -p $(CONFIG_IFD_CHIPSET) -F $@ $<" - $(IFDTOOL) -p $(CONFIG_IFD_CHIPSET) -F $@ $< -endif # ifeq($(CONFIG_HAVE_IFD_BIN),y) -endif # ifneq($(CONFIG_IFD_CHIPSET),) - # entire "BIOS" region (everything directly of concern to the host system) FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE -# -# X86 CONSOLE FMAP region -# -# position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled - FMAP_CURRENT_BASE := 0 -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE) -FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) -FMAP_CONSOLE_ENTRY := CONSOLE@$(call _tohex,$(FMAP_CONSOLE_BASE)) $(call _tohex,$(FMAP_CONSOLE_SIZE)) -FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)) -else -FMAP_CONSOLE_ENTRY := -endif - ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000) FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) @@ -1163,7 +1140,7 @@ ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y) FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE)) FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000) -FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(call _tohex,$(FMAP_SPD_CACHE_BASE)) $(call _tohex,$(FMAP_SPD_CACHE_SIZE)) +FMAP_SPD_CACHE_ENTRY := $(call strip_quotes,$(CONFIG_SPD_CACHE_FMAP_NAME))@$(call _tohex,$(FMAP_SPD_CACHE_BASE)) $(call _tohex,$(FMAP_SPD_CACHE_SIZE)) FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)) else FMAP_SPD_CACHE_ENTRY := @@ -1172,12 +1149,21 @@ endif ifeq ($(CONFIG_VPD),y) FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE) -FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(call _tohex,$(FMAP_VPD_BASE)) $(call _tohex,$(FMAP_VPD_SIZE)) +FMAP_VPD_ENTRY := $(call strip_quotes,$(CONFIG_VPD_FMAP_NAME))@$(call _tohex,$(FMAP_VPD_BASE)) $(call _tohex,$(FMAP_VPD_SIZE)) FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)) else FMAP_VPD_ENTRY := endif +ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +FMAP_CONSOLE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000) +FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) +FMAP_CONSOLE_ENTRY := CONSOLE@$(call _tohex,$(FMAP_CONSOLE_BASE)) $(call _tohex,$(FMAP_CONSOLE_SIZE)) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)) +else +FMAP_CONSOLE_ENTRY := +endif + ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y) FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000) FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE) @@ -1193,18 +1179,17 @@ endif # # position, size FMAP_FMAP_BASE := $(FMAP_CURRENT_BASE) -FMAP_FMAP_SIZE := 0x200 +FMAP_FMAP_SIZE := 0x1000 # # X86 COREBOOT default cbfs FMAP region # -# position and size of CBFS, relative to BIOS_BASE +# position of CBFS, relative to BIOS_BASE +# will extend to the end of the flash/bios region FMAP_CBFS_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)), 0x1000) -FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) -DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd # entire flash # entire "BIOS" region (everything directly of concern to the host system) FMAP_BIOS_BASE := 0 @@ -1246,26 +1231,64 @@ endif # # position and size of CBFS, relative to BIOS_BASE FMAP_CBFS_BASE := $(FMAP_CURRENT_BASE) -FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif # ifeq ($(CONFIG_ARCH_X86),y) + +# x86 BIOS region and children (offsets relative to BIOS base). +define FMAP_EMIT_X86_BIOS + printf '\tBIOS@0x%x 0x%x {\n' $(FMAP_BIOS_BASE) $(FMAP_BIOS_SIZE); \ + $(if $(strip $(FMAP_MRC_CACHE_ENTRY)),printf '\t\t%s\n' '$(FMAP_MRC_CACHE_ENTRY)';) \ + $(if $(strip $(FMAP_SMMSTORE_ENTRY)),printf '\t\t%s\n' '$(FMAP_SMMSTORE_ENTRY)';) \ + $(if $(strip $(FMAP_SPD_CACHE_ENTRY)),printf '\t\t%s\n' '$(FMAP_SPD_CACHE_ENTRY)';) \ + $(if $(strip $(FMAP_VPD_ENTRY)),printf '\t\t%s\n' '$(FMAP_VPD_ENTRY)';) \ + $(if $(strip $(FMAP_CONSOLE_ENTRY)),printf '\t\t%s\n' '$(FMAP_CONSOLE_ENTRY)';) \ + $(if $(strip $(FMAP_HSPHY_FW_ENTRY)),printf '\t\t%s\n' '$(FMAP_HSPHY_FW_ENTRY)';) \ + printf '\t\tFMAP@0x%x 0x%x\n' $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE); \ + printf '\t\tCOREBOOT(CBFS)@0x%x\n' $(FMAP_CBFS_BASE); \ + printf '\t}\n'; +endef + +# Non-x86 BIOS region: BOOTBLOCK, FMAP, optional regions, then CBFS. +define FMAP_EMIT_NON_X86_BIOS + printf '\tBIOS@0x%x 0x%x {\n' $(FMAP_BIOS_BASE) $(FMAP_BIOS_SIZE); \ + printf '\t\tBOOTBLOCK 128K\n'; \ + printf '\t\tFMAP@0x%x 0x%x\n' $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE); \ + $(if $(strip $(FMAP_CONSOLE_ENTRY)),printf '\t\t%s\n' '$(FMAP_CONSOLE_ENTRY)';) \ + $(if $(strip $(FMAP_MRC_CACHE_ENTRY)),printf '\t\t%s\n' '$(FMAP_MRC_CACHE_ENTRY)';) \ + printf '\t\tCOREBOOT(CBFS)@0x%x\n' $(FMAP_CBFS_BASE); \ + printf '\t}\n'; +endef + +ifeq ($(CONFIG_ARCH_X86),y) + +ifneq ($(and $(CONFIG_IFD_CHIPSET),$(CONFIG_HAVE_IFD_BIN)),) + +$(obj)/fmap-ifd.fmd: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) $(IFDTOOL) + echo " IFDTOOL -p $(CONFIG_IFD_CHIPSET) -F $(obj)/fmap-ifd.fmd $<" + $(IFDTOOL) -p $(CONFIG_IFD_CHIPSET) -F $(obj)/fmap-ifd.fmd $< + +$(obj)/fmap.fmd: $(top)/Makefile.mk $(obj)/config.h $(obj)/fmap-ifd.fmd + @{ $(FMAP_EMIT_X86_BIOS) } > $(obj)/fmap-bios.tmp + sed -e '1s/^FLASH .*/FLASH $(call _tohex,$(FMAP_FLASH_SIZE)) {/' \ + -e '/SI_BIOS@/r $(obj)/fmap-bios.tmp' -e '/SI_BIOS@/d' \ + '$(obj)/fmap-ifd.fmd' > $@ + +else # x86 without IFD + +$(obj)/fmap.fmd: $(top)/Makefile.mk $(obj)/config.h + @{ printf 'FLASH 0x%x {\n' $(FMAP_FLASH_SIZE); \ + $(FMAP_EMIT_X86_BIOS) \ + printf '}\n'; } > $@ +endif + +else # ifeq ($(CONFIG_ARCH_X86),y) + +$(obj)/fmap.fmd: $(top)/Makefile.mk $(obj)/config.h + @{ printf 'FLASH 0x%x {\n' $(FMAP_FLASH_SIZE); \ + $(FMAP_EMIT_NON_X86_BIOS) \ + printf '}\n'; } > $@ endif # ifeq ($(CONFIG_ARCH_X86),y) -$(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h - sed -e "s,##FLASH_SIZE##,$(call _tohex,$(FMAP_FLASH_SIZE))," \ - -e "s,##BIOS_BASE##,$(call _tohex,$(FMAP_BIOS_BASE))," \ - -e "s,##BIOS_SIZE##,$(call _tohex,$(FMAP_BIOS_SIZE))," \ - -e "s,##FMAP_BASE##,$(call _tohex,$(FMAP_FMAP_BASE))," \ - -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ - -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ - -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ - -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ - -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ - -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ - -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \ - -e "s,##CBFS_BASE##,$(call _tohex,$(FMAP_CBFS_BASE))," \ - -e "s,##CBFS_SIZE##,$(call _tohex,$(FMAP_CBFS_SIZE))," \ - $(DEFAULT_FLASHMAP) > $@.tmp - mv $@.tmp $@ else # ifeq ($(CONFIG_FMDFILE),) $(obj)/fmap.fmd: $(CONFIG_FMDFILE) $(obj)/config.h $(HOSTCC) $(PREPROCESS_ONLY) -include $(obj)/config.h $< -o $@.pre @@ -1287,7 +1310,7 @@ BB_FIT_REGION = COREBOOT TS_FIT_REGION = COREBOOT else BB_FIT_REGION = BOOTBLOCK -TS_FIT_REGION = TOPSWAP +TS_FIT_REGION = BOOTBLOCK_B bootblock_add_params = -f $(objcbfs)/bootblock.bin \ -n bootblock -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) \ diff --git a/configs/config.asrock_h370m_itx b/configs/config.asrock_h370m_itx new file mode 100644 index 00000000000..46efc2061cf --- /dev/null +++ b/configs/config.asrock_h370m_itx @@ -0,0 +1,6 @@ +CONFIG_VENDOR_ASROCK=y +CONFIG_BOARD_ASROCK_H370M_ITX=y +CONFIG_USE_OPTION_TABLE=y +CONFIG_ON_DEVICE_ROM_LOAD=n +CONFIG_PAYLOAD_SEABIOS=y +CONFIG_SEABIOS_THREAD_OPTIONROMS=y diff --git a/configs/config.qotom_qdnv01 b/configs/config.qotom_qdnv01 index 1042ec6de44..d5bbf853393 100644 --- a/configs/config.qotom_qdnv01 +++ b/configs/config.qotom_qdnv01 @@ -1,4 +1,5 @@ CONFIG_VENDOR_QOTOM=y +CONFIG_BOARD_QOTOM_QDNV01=y CONFIG_MAINBOARD_PART_NUMBER="Qotom QDNV01" CONFIG_ENABLE_HSUART=y CONFIG_USE_DENVERTON_NS_FSP_CAR=y diff --git a/payloads/Kconfig b/payloads/Kconfig index e30b1ec76c5..65cecaf42e1 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -189,8 +189,8 @@ endif # !PAYLOAD_NONE config PAYLOAD_FIT_SUPPORT bool "FIT support" + default y if PAYLOAD_LINUX default n - default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select FLATTENED_DEVICE_TREE help @@ -198,4 +198,7 @@ config PAYLOAD_FIT_SUPPORT Enables FIT parser and devicetree patching. The FIT is non self-extracting and needs to have a compatible compression format. + In case the Payload is added afterwards (e.g. using cbfstool), one + can enable this option in combination with PAYLOAD_NONE=y. + endmenu diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore index c9efcffd032..47b377ea31c 100644 --- a/payloads/external/.gitignore +++ b/payloads/external/.gitignore @@ -1,12 +1,14 @@ +coreDOOM/coredoom/ depthcharge/depthcharge/ +edk2/workspace FILO/filo/ GRUB2/grub2/ +iPXE/ipxe/ LinuxBoot/linuxboot/ +Memtest86Plus/memtest86plus_v*/ SeaBIOS/seabios/ -edk2/workspace +skiboot/build +skiboot/skiboot tint/tint/ +tint/tint_*.tar.xz U-Boot/u-boot/ -Memtest86Plus/memtest86plus/ -iPXE/ipxe/ -skiboot/skiboot -skiboot/build diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 2f4cab5efea..86dc4f85441 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -86,7 +86,7 @@ config EDK2_REPOSITORY config EDK2_TAG_OR_REV string "Insert a commit's SHA-1 or a branch name" - default "origin/uefipayload_2511" if EDK2_REPO_MRCHROMEBOX + default "origin/uefipayload_2603" if EDK2_REPO_MRCHROMEBOX default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD default "origin/master" if EDK2_REPO_OFFICIAL default "" if EDK2_REPO_CUSTOM diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 09c38d8cf86..5b1f85ad919 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -78,6 +78,7 @@ BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency=$(C endif # DISABLE_SERIAL_TERMINAL = FALSE ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) +BUILD_STR += -D SERIAL_DRIVER_ENABLE=FALSE BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE endif # VARIABLE_SUPPORT = EMU @@ -145,10 +146,6 @@ ifeq ($(CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE),y) BUILD_STR += -D CAPSULE_EMBED_FMP_DXE=TRUE endif -CAPSULE_PCD_INC_REL := BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc -CAPSULE_PCD_INC := $(EDK2_PATH)/$(CAPSULE_PCD_INC_REL) -CAPSULE_PCD_NAME := gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr - CAPSULE_GUID := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID)) CAPSULE_REGIONS := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_CAPSULE_REGIONS)) CAPSULE_LOCALVERSION := $(call strip_quotes,$(CONFIG_LOCALVERSION)) @@ -160,6 +157,16 @@ CAPSULE_SIGNER_PRIVATE_CERT_PATH := $(call edk2_abspath,$(CAPSULE_SIGNER_PRIVATE CAPSULE_OTHER_PUBLIC_CERT_PATH := $(call edk2_abspath,$(CAPSULE_OTHER_PUBLIC_CERT)) CAPSULE_TRUSTED_PUBLIC_CERT_PATH := $(call edk2_abspath,$(CAPSULE_TRUSTED_PUBLIC_CERT)) +# Workspace-local PCD include for FmpDxe; path is relative to EDK2 WORKSPACE for DSC (!include). +CAPSULE_FMP_PCD_INC_REL := Conf/CapsuleFmpPkcs7Pcd.inc +CAPSULE_FMP_PCD_INC_PCD_NAME := gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr + +ifeq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),y) +ifneq ($(CAPSULE_TRUSTED_PUBLIC_CERT),) +BUILD_STR += -D FMP_DEVICE_PKCS7_PCD_INC=$(CAPSULE_FMP_PCD_INC_REL) +endif +endif + # AppendRmapManifest.py moved from BaseTools/Scripts to UefiPayloadPkg/Tools in # newer edk2 trees. EDK2_APPEND_RMAP_MANIFEST = $(firstword $(wildcard \ @@ -170,7 +177,23 @@ EDK2_APPEND_RMAP_MANIFEST = $(firstword $(wildcard \ # If FmpDxe is built, edk2 also places it in the top-level X64 output dir. EDK2_FMP_DXE = $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/X64/FmpDxe.efi -CAPSULE_ROOT_CERT_DER := $(WORKSPACE)/capsule_trusted_root.der +define EDK2_ENSURE_FMP_CERT_INC + if [ "$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES)" = "y" ] && [ -n "$(CAPSULE_TRUSTED_PUBLIC_CERT)" ]; then \ + type openssl > /dev/null 2>&1 || { echo "ERROR: Please install openssl."; exit 1; }; \ + test -f "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)"; \ + binto_pcd="$(EDK2_PATH)/BaseTools/Scripts/BinToPcd.py"; \ + if [ ! -f "$$binto_pcd" ]; then \ + echo "ERROR: BinToPcd.py not found (expected EDK2 BaseTools/Scripts/BinToPcd.py)."; \ + exit 1; \ + fi; \ + mkdir -p "$(WORKSPACE)/Conf"; \ + der="$(WORKSPACE)/.capsule_fmp_cert.$$$$.der"; \ + openssl x509 -in "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)" -outform der -out "$$der" || exit 1; \ + python3 "$$binto_pcd" -q -x -i "$$der" \ + -o "$(WORKSPACE)/$(CAPSULE_FMP_PCD_INC_REL)" -p "$(CAPSULE_FMP_PCD_INC_PCD_NAME)" || exit 1; \ + rm -f "$$der"; \ + fi; +endef # # One or more downstream edk2 repositories support the following additional options: @@ -266,10 +289,6 @@ $(EDK2_PATH): $(WORKSPACE) fi cd $(EDK2_PATH); \ git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \ - git checkout "$(CAPSULE_PCD_INC_REL)" > /dev/null 2>&1 || true; \ - if ! git ls-files --error-unmatch "$(CAPSULE_PCD_INC_REL)" >/dev/null 2>&1; then \ - rm -f "$(CAPSULE_PCD_INC_REL)" || true; \ - fi; \ if [ -e UefiPayloadPkg/ShimLayer/UniversalPayload.o ]; then \ rm UefiPayloadPkg/ShimLayer/UniversalPayload.o; \ fi; \ @@ -335,13 +354,7 @@ checktools: ifeq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES)$(CONFIG_DRIVERS_EFI_GENERATE_CAPSULE),yy) capsule_keys: $(EDK2_PATH) - type openssl > /dev/null 2>&1 || ( echo "ERROR: Please install openssl."; exit 1 ) - test -f "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)" - test -f "$(EDK2_PATH)/BaseTools/Scripts/BinToPcd.py" - mkdir -p "$(dir $(CAPSULE_PCD_INC))" - openssl x509 -in "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)" -outform der -out "$(CAPSULE_ROOT_CERT_DER)" - python3 "$(EDK2_PATH)/BaseTools/Scripts/BinToPcd.py" -q -x \ - -i "$(CAPSULE_ROOT_CERT_DER)" -o "$(CAPSULE_PCD_INC)" -p "$(CAPSULE_PCD_NAME)" + $(EDK2_ENSURE_FMP_CERT_INC) prep: capsule_keys endif @@ -371,6 +384,7 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/FV/UEFIPAYLOAD.fd: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ + $(EDK2_ENSURE_FMP_CERT_INC) \ echo -n "EDK2: Building... "; \ build -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR) \ -y $(WORKSPACE)/Build/UefiPayloadPkgX64/UEFIPAYLOAD.txt; \ @@ -384,6 +398,7 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ + $(EDK2_ENSURE_FMP_CERT_INC) \ echo -n "EDK2: Building... "; \ $(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR) if [ ! -f $@ ]; then \ @@ -413,7 +428,7 @@ UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/IA32/U ../../../build/ShimmedUniversalPayload.elf clean: - test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 + test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt Conf/CapsuleFmpPkcs7Pcd.inc) || exit 0 distclean: rm -rf $(WORKSPACE) diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk index f7c2c8bda0e..0f5d1a0e114 100644 --- a/payloads/libpayload/Makefile.mk +++ b/payloads/libpayload/Makefile.mk @@ -111,8 +111,8 @@ includes-handler= \ $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs)) printf " AR $(subst $(CURDIR)/,,$(@))\n" printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M - for func in $$($(NM) $@ | awk '/ (w|W) / { print $$NF }'); do \ - if $(NM) --no-weak --defined-only $@ | grep -Eq " $$func$$"; then \ + for func in $$($(NM) $@ | awk '/ [wW] / { print $$NF }'); do \ + if $(NM) $@ 2>/dev/null | grep -Eq " [TDRCB] $${func}$$"; then \ printf "\nERROR: Function '$$func' appears as both weak and strong symbol in libpayload.\n"; \ printf " Weak symbol overrides don't work reliably from within the same library.\n\n"; \ rm $@; \ diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 0b7d206a589..deabf99a700 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -651,10 +651,11 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) /* framebuffer address has been set already, so just add it as DMA */ if (framebuffer->physical_address) { - if (mmu_add_memrange(mmu_ranges, - framebuffer->physical_address, - fb_size, - TYPE_DMA_MEM) == NULL) + if (mmu_add_memrange(mmu_ranges, framebuffer->physical_address, + fb_size, TYPE_DMA_MEM) == NULL) + mmu_error(); + if (mmu_add_memrange(&usedmem_ranges, framebuffer->physical_address, + fb_size, TYPE_DMA_MEM) == NULL) mmu_error(); return; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 9864c2b5d4d..63dbf44ffe3 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -464,6 +464,10 @@ enum boot_mode_t { CB_BOOT_MODE_LOW_BATTERY_CHARGING, /* Device is booting in due to charger insertion */ CB_BOOT_MODE_OFFMODE_CHARGING, + /* Device is booting in due to RTC alarm */ + CB_BOOT_MODE_RTC_WAKE, + /* Device is booting in "no-battery" */ + CB_BOOT_MODE_NO_BATTERY, }; /* diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index a38e0ac23f4..52d9e2c3554 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -467,6 +467,39 @@ "speedMbps": 9600, "lp5x": true } + }, + { + "name": "SL5D32G32C2A-HC0", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 7500, + "lp5x": true + } + }, + { + "name": "K3KL9L90EM-MGCV", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 9600, + "lp5x": true + } + }, + { + "name": "H58G66EK9BX223", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 9600, + "lp5x": true + } } ] } diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt index ee0aab92cab..d2bfea4026c 100644 --- a/spd/lp5/platforms_manifest.generated.txt +++ b/spd/lp5/platforms_manifest.generated.txt @@ -1,6 +1,7 @@ # Generated by: -# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 +# ./util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 +NVL,set-0 PTL,set-0 MTL,set-0 ADL,set-0 diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index ac104fc0104..1aa14011e73 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -1,5 +1,5 @@ # Generated by: -# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 +# ./util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 MT62F512M32D2DR-031 WT:B,spd-1.hex MT62F1G32D4DR-031 WT:B,spd-2.hex @@ -45,3 +45,6 @@ RS1G32LO5D2FDB-23BT,spd-11.hex BWMYAX32P8A-32G,spd-7.hex MT62F2G32D4DS-020 WT:D,spd-10.hex H58G56DK9BX068,spd-14.hex +SL5D32G32C2A-HC0,spd-7.hex +K3KL9L90EM-MGCV,spd-15.hex +H58G66EK9BX223,spd-15.hex diff --git a/spd/lp5/set-0/spd-15.hex b/spd/lp5/set-0/spd-15.hex new file mode 100644 index 00000000000..4f2ec1ef894 --- /dev/null +++ b/spd/lp5/set-0/spd-15.hex @@ -0,0 +1,32 @@ +23 10 15 0E 16 22 B5 08 00 00 00 00 0A 01 00 00 +00 00 07 00 00 00 00 00 AE 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 A4 00 D6 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt index ac104fc0104..1aa14011e73 100644 --- a/spd/lp5/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -1,5 +1,5 @@ # Generated by: -# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 +# ./util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 MT62F512M32D2DR-031 WT:B,spd-1.hex MT62F1G32D4DR-031 WT:B,spd-2.hex @@ -45,3 +45,6 @@ RS1G32LO5D2FDB-23BT,spd-11.hex BWMYAX32P8A-32G,spd-7.hex MT62F2G32D4DS-020 WT:D,spd-10.hex H58G56DK9BX068,spd-14.hex +SL5D32G32C2A-HC0,spd-7.hex +K3KL9L90EM-MGCV,spd-15.hex +H58G66EK9BX223,spd-15.hex diff --git a/spd/lp5/set-1/spd-15.hex b/spd/lp5/set-1/spd-15.hex new file mode 100644 index 00000000000..f32bc8e5c0e --- /dev/null +++ b/spd/lp5/set-1/spd-15.hex @@ -0,0 +1,32 @@ +23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00 +00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 A4 00 D6 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/Kconfig b/src/Kconfig index 93df67ed3d4..cd4dfde43b8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -818,6 +818,14 @@ config STACK_SIZE default 0x2000 if ARCH_X86 default 0x0 +config THREAD_STACK_SIZE + hex + depends on COOP_MULTITASKING + default 0x2000 + help + The stack size for each cooperative thread. This is separate from + the main CPU stack size (STACK_SIZE). + config MAX_CPUS int default 1 @@ -876,7 +884,7 @@ config TIMER_QUEUE config COOP_MULTITASKING def_bool n select TIMER_QUEUE - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_ARM64 help Cooperative multitasking allows callbacks to be multiplexed on the main thread. With this enabled it allows for multiple execution paths @@ -1463,10 +1471,6 @@ endmenu source "src/lib/Kconfig" -config WARNINGS_ARE_ERRORS - bool - default y - # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are # mutually exclusive. One of these options must be selected in the diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 94b63092613..0288fb2f771 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -261,6 +261,9 @@ static void *get_tpm2_log(u32 *size) static void acpi_create_tpm2(acpi_header_t *header, void *unused) { + u64 control_area; + u32 start_method; + if (tlcl_get_family() != TPM_2) return; @@ -270,37 +273,44 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused) acpi_tpm2_t *tpm2 = (acpi_tpm2_t *)header; u32 tpm2_log_len; - void *lasa; /* * Some payloads like SeaBIOS depend on log area to use TPM2. * Get the memory size and address of TPM2 log area or initialize it. */ - lasa = get_tpm2_log(&tpm2_log_len); + void *lasa = get_tpm2_log(&tpm2_log_len); if (!lasa) tpm2_log_len = 0; - if (acpi_fill_header(header, "TPM2", TPM2, sizeof(acpi_tpm2_t)) != CB_SUCCESS) - return; - - /* Hard to detect for coreboot. Just set it to 0 */ - tpm2->platform_class = 0; - if (CONFIG(AMD_CRB_FTPM) && crb_tpm_is_active()) { - tpm2->control_area = crb_tpm_base_address() + 0x40; - tpm2->start_method = ACPI_TPM2_SM_ACPI_START; + control_area = crb_tpm_base_address() + 0x40; + start_method = ACPI_TPM2_SM_ACPI_START; } else if (CONFIG(CRB_TPM) && crb_tpm_is_active()) { - tpm2->control_area = crb_tpm_base_address() + 0x40; - tpm2->start_method = ACPI_TPM2_SM_CRB; + control_area = crb_tpm_base_address() + 0x40; + start_method = ACPI_TPM2_SM_CRB; } else { - tpm2->control_area = 0; - tpm2->start_method = ACPI_TPM2_SM_MMIO_TIS; + control_area = 0; + start_method = ACPI_TPM2_SM_MMIO_TIS; } - memset(tpm2->msp, 0, sizeof(tpm2->msp)); + acpi_write_tpm2(tpm2, lasa, tpm2_log_len, control_area, start_method); +} - /* Fill the log area size and start address fields. */ +void acpi_write_tpm2(acpi_tpm2_t *tpm2, const void *lasa, const u32 tpm2_log_len, + const u64 control_area, const u32 start_method) +{ + acpi_header_t *header = &tpm2->header; + memset(tpm2, 0, sizeof(acpi_tpm2_t)); + + if (acpi_fill_header(header, "TPM2", TPM2, sizeof(acpi_tpm2_t)) != CB_SUCCESS) + return; + + tpm2->control_area = control_area; + tpm2->start_method = start_method; tpm2->laml = tpm2_log_len; tpm2->lasa = (uintptr_t)lasa; + + tpm2->header.checksum = 0; + tpm2->header.checksum = acpi_checksum((void *)tpm2, tpm2->header.length); } static void acpi_ssdt_write_cbtable(void) diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index 3edf0d03424..86ac361e0e8 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -25,6 +25,16 @@ void acpigen_write_ADR_pci_device(const struct device *dev) acpigen_write_ADR_pci_devfn(dev->path.pci.devfn); } +/* + * Emit one PCI _PRT entry for direct GSI (IO-APIC) routing. + * + * Package (0x04) { + * (pci_dev << 16) | 0xFFFF, // Address: device (high word), all functions (0xFFFF) + * acpi_pin, // Pin: INTA..INTD (0..3) + * 0, // Source: 0 => GSI + * gsi // Source Index: GSI number + * } + */ void acpigen_write_PRT_GSI_entry(unsigned int pci_dev, unsigned int acpi_pin, unsigned int gsi) { acpigen_write_package(4); @@ -40,6 +50,16 @@ void acpigen_write_PRT_GSI_entry(unsigned int pci_dev, unsigned int acpi_pin, un acpigen_pop_len(); /* Package */ } +/* + * Emit one PCI _PRT entry for link-device (PIC-style) routing. + * + * Package (0x04) { + * (pci_dev << 16) | 0xFFFF, // Address: device (high word), all functions (0xFFFF) + * acpi_pin, // Pin: INTA..INTD (0..3) + * source_path, // Source: NameString (e.g. "\\_SB.INTA") + * index // Source Index + * } + */ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, const char *source_path, unsigned int index) { @@ -55,3 +75,58 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, acpigen_pop_len(); /* Package */ } + +/* + * Emit one PCI routing table entry for IO-APIC (GSI) routing: + * + * Package (0x04) + * { + * 0xDDDDFFFF, // PCI address: slot (high word), function (low word) + * 0xPP, // PCI interrupt pin (INTA-INTx) + * 0x00, // Source (0 = GSI) + * 0x000000GG // Global system interrupt + * } + */ +void acpigen_write_PRT_GSI_entry_devfn(unsigned int devfn, unsigned int acpi_pin, + unsigned int gsi) +{ + acpigen_write_package(4); + acpigen_write_dword((PCI_SLOT(devfn) << 16) | PCI_FUNC(devfn)); + acpigen_write_byte(acpi_pin); + + /* Source */ + acpigen_write_byte(0); + + /* Source Index */ + acpigen_write_dword(gsi); + + acpigen_pop_len(); /* Package */ +} + +/* +* Emit one PCI routing table entry for static interrupt link (PIC) routing: +* +* Package (0x04) +* { +* 0xDDDDFFFF, // PCI address: slot, function +* 0xPP, // PCI interrupt pin +* \_SB.INTx, // Interrupt source (e.g. \_SB.INTA) +* 0x000000II // Source index +* } +*/ +void acpigen_write_PRT_source_entry_devfn(unsigned int devfn, unsigned int acpi_pin, + const char *source_path, + unsigned int index) +{ + acpigen_write_package(4); + acpigen_write_dword((PCI_SLOT(devfn) << 16) | PCI_FUNC(devfn)); + acpigen_write_byte(acpi_pin); + + /* Source */ + acpigen_emit_namestring(source_path); + + /* Source Index */ + acpigen_write_dword(index); + + acpigen_pop_len(); /* Package */ +} diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c index ce57b9cc799..699a437ae02 100644 --- a/src/acpi/acpigen_pci_root_resource_producer.c +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -6,6 +6,7 @@ #include #include #include +#include #include static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, @@ -44,6 +45,15 @@ static void write_ssdt_domain_mmio_producer_range(const char *domain_name, MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); } +static void write_ssdt_domain_tpm_mmio_producer_range(const struct device *domain) +{ + if ((CONFIG(MEMORY_MAPPED_TPM) && (CONFIG_TPM_TIS_BASE_ADDRESS == 0xfed40000)) || + (CONFIG(CRB_TPM) && (CONFIG_CRB_TPM_BASE_ADDRESS == 0xfed40000))) { + write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), + 0xfed40000, 0xfed44fff); + } +} + void pci_domain_fill_ssdt(const struct device *domain) { const char *acpi_scope = acpi_device_path(domain); @@ -64,6 +74,7 @@ void pci_domain_fill_ssdt(const struct device *domain) /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); + write_ssdt_domain_tpm_mmio_producer_range(domain); } struct resource *res; diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 38af89bfda8..80c295e03af 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -64,11 +64,6 @@ static const uint32_t action_keymaps[] = { /* Keymap for numeric keypad keys */ static uint32_t numeric_keypad_keymaps[] = { - /* Row-0 */ - KEYMAP(0xc9, KEY_PAGEUP), - KEYMAP(0xd1, KEY_PAGEDOWN), - KEYMAP(0xc7, KEY_HOME), - KEYMAP(0xcf, KEY_END), /* Row-1 */ KEYMAP(0xb5, KEY_KPSLASH), KEYMAP(0x37, KEY_KPASTERISK), @@ -181,6 +176,13 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0xd2, KEY_INSERT), /* Screen Lock */ KEYMAP(0xab, KEY_SCREENLOCK), + /* Navigation keys */ + KEYMAP(0xc9, KEY_PAGEUP), + KEYMAP(0xd1, KEY_PAGEDOWN), + KEYMAP(0xc7, KEY_HOME), + KEYMAP(0xcf, KEY_END), + /* Contextual Insert Key */ + KEYMAP(0xac, KEY_CONTEXTUAL_INSERT), }; static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys, @@ -303,6 +305,39 @@ static void ssdt_generate_keymap(struct acpi_dp *dp, uint8_t num_top_row_keys, acpi_dp_add_array(dp, dp_array); } +static bool ps2_keyboard_dsd_args_valid(const char *caller, const char *scope, + uint8_t num_top_row_keys) +{ + if (!scope || + num_top_row_keys < PS2_MIN_TOP_ROW_KEYS || + num_top_row_keys > PS2_MAX_TOP_ROW_KEYS) { + printk(BIOS_ERR, "PS2K: %s: invalid args\n", caller); + return false; + } + + return true; +} + +void acpigen_ps2_keyboard_physmap_dsd(const char *scope, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[]) +{ + struct acpi_dp *dsd; + + if (!ps2_keyboard_dsd_args_valid(__func__, scope, num_top_row_keys)) + return; + + dsd = acpi_dp_new_table("_DSD"); + if (!dsd) { + printk(BIOS_ERR, "PS2K: couldn't write _DSD\n"); + return; + } + + acpigen_write_scope(scope); + ssdt_generate_physmap(dsd, num_top_row_keys, action_keys); + acpi_dp_write(dsd); + acpigen_pop_len(); /* Scope */ +} + void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, enum ps2_action_key action_keys[], bool can_send_function_keys, @@ -313,12 +348,8 @@ void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, { struct acpi_dp *dsd; - if (!scope || - num_top_row_keys < PS2_MIN_TOP_ROW_KEYS || - num_top_row_keys > PS2_MAX_TOP_ROW_KEYS) { - printk(BIOS_ERR, "PS2K: %s: invalid args\n", __func__); + if (!ps2_keyboard_dsd_args_valid(__func__, scope, num_top_row_keys)) return; - } dsd = acpi_dp_new_table("_DSD"); if (!dsd) { diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index a99d80bbf49..f39ce8bb518 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -7,6 +7,8 @@ #include #endif +External (\_SB.NAPE, MethodObj) + /* Operating system enumeration. */ Name (OSYS, 0) @@ -28,6 +30,10 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ PICM = Arg0 + If (CondRefOf (\_SB.NAPE)) + { + \_SB.NAPE() + } } #if CONFIG(ECAM_MMCONF_SUPPORT) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk index efd628fee7d..7310ce1c1f1 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -82,6 +82,7 @@ romstage-y += transition.c transition_asm.S ifneq ($(CONFIG_ARM64_CURRENT_EL),3) romstage-y += smc.c smc_asm.S endif +romstage-$(CONFIG_COOP_MULTITASKING) += thread.c thread_switch.S rmodules_arm64-y += memset.S rmodules_arm64-y += memcpy.S @@ -115,6 +116,7 @@ ramstage-y += transition.c transition_asm.S ifneq ($(CONFIG_ARM64_CURRENT_EL),3) ramstage-y += smc.c smc_asm.S endif +ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c thread_switch.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += dma.c diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index f53c16d1568..d25ec149140 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -30,4 +30,15 @@ config ARCH_ARMV8_EXTENSION need to be changed unless specific features (e.g. new instructions) are used by the SoC's coreboot code. +config ARCH_ARM64_DEBUG_MMU + bool "Debug MMU table" + default n + help + When enabled, the MMU table walker will dump the translation + table entries and their attributes to the debug console during + initialization or range configuration. + + This is useful for verifying that memory ranges (Normal, Device, + Read-Only, etc.) are being mapped correctly in the page tables. + endif # ARCH_ARM64 diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 65d0f92e5dc..c30fd5789ab 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -76,16 +76,25 @@ static const char *table_level_name(size_t xlat_size) } } +static int init_next_free_table(void *start, void *end) +{ + if ((void *)next_free_table < start || (void *)next_free_table >= end) + next_free_table = start; + while (next_free_table[0] != UNUSED_DESC) { + next_free_table += GRANULE_SIZE / sizeof(*next_free_table); + if ((void *)next_free_table >= end) + return -1; + } + return 0; +} + /* Func : setup_new_table * Desc : Get next free table from TTB and set it up to match old parent entry. */ static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size) { - while (next_free_table[0] != UNUSED_DESC) { - next_free_table += GRANULE_SIZE/sizeof(*next_free_table); - if (_ettb - (u8 *)next_free_table <= 0) - die("Ran out of page table space!"); - } + if (init_next_free_table(_ttb, _ettb)) + die("Ran out of page table space!"); void *frame_base = (void *)(desc & XLAT_ADDR_MASK); const char *level_name = table_level_name(xlat_size); @@ -227,6 +236,171 @@ static void assert_correct_ttb_mapping(void *addr) == BLOCK_INDEX_MEM_NORMAL && !(pte & BLOCK_NS)); } + +/* Decodes and prints the architectural attributes of a PTE. */ +static void print_pte_attributes(uint64_t pte) +{ + /* Invalid/Unused entries */ + if (pte == 0 || (pte & DESC_MASK) == INVALID_DESC) + return; + + printk(BIOS_INFO, " Attributes: "); + printk(BIOS_INFO, (pte & BLOCK_NS) ? "Non-Secure | " : "Secure | "); + printk(BIOS_INFO, (pte & BLOCK_AP_RO) ? "Read-Only | " : "Read-Write | "); + printk(BIOS_INFO, (pte & BLOCK_ACCESS) ? "Accessed | " : "Not Accessed | "); + printk(BIOS_INFO, (pte & BLOCK_XN) ? "Execute-Never | " : "Executable | "); + + uint64_t sh = pte & BLOCK_SH_MASK; + switch (sh) { + case BLOCK_SH_NON_SHAREABLE: + printk(BIOS_INFO, "Non-Shareable | "); + break; + case BLOCK_SH_UNPREDICTABLE: + printk(BIOS_INFO, "Unpredictable Shareability | "); + break; + case BLOCK_SH_OUTER_SHAREABLE: + printk(BIOS_INFO, "Outer-Shareable | "); + break; + case BLOCK_SH_INNER_SHAREABLE: + printk(BIOS_INFO, "Inner-Shareable | "); + break; + default: + printk(BIOS_INFO, "Unknown Shareability (0x%llx) | ", sh); + break; + } + + uint64_t index = (pte >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK; + switch (index) { + case BLOCK_INDEX_MEM_DEV_NGNRNE: + printk(BIOS_INFO, "Device NGNRNE"); + break; + case BLOCK_INDEX_MEM_DEV_NGNRE: + printk(BIOS_INFO, "Device NGNRE"); + break; + case BLOCK_INDEX_MEM_DEV_GRE: + printk(BIOS_INFO, "Device GRE"); + break; + case BLOCK_INDEX_MEM_NORMAL_NC: + printk(BIOS_INFO, "Normal Non-Cacheable"); + break; + case BLOCK_INDEX_MEM_NORMAL: + printk(BIOS_INFO, "Normal Cacheable (WBWAC)"); + break; + default: + printk(BIOS_INFO, "Unknown Memory Type Index (%llu)", index); + break; + } + printk(BIOS_INFO, "\n"); +} + +/* Structure to hold the state of the last printed range */ +struct last_mmu_entry { + uint64_t start; + uint64_t end; + uint64_t pte; + const char *desc_type; + bool valid; +}; + +/* Function to print the accumulated range and reset the state */ +static void print_and_reset_last_range(struct last_mmu_entry *last) +{ + if (last->valid) { + printk(BIOS_INFO, " Mapping [" ADDR_FMT ":" ADDR_FMT ") -> PTE: 0x%016llx (%s)\n", + (uintptr_t)last->start, (uintptr_t)last->end, last->pte, last->desc_type); + print_pte_attributes(last->pte); + last->valid = false; + } +} + +/* + * Prints the MMU entries for a given address range, merging contiguous + * mappings with identical attributes. + */ +static void print_mmu_range(uint64_t base_addr, size_t size) +{ + if (!CONFIG(ARCH_ARM64_DEBUG_MMU)) + return; + + uint64_t current_addr = base_addr; + uint64_t end_addr = base_addr + size; + + printk(BIOS_INFO, "Dumping MMU entries for range [" ADDR_FMT ":" ADDR_FMT ")\n", + (uintptr_t)base_addr, (uintptr_t)end_addr); + + struct last_mmu_entry last = { .valid = false }; + + while (current_addr < end_addr) { + int shift = L0_ADDR_SHIFT; + uint64_t *pte_ptr = (uint64_t *)_ttb; + uint64_t pte = 0; + uint64_t mapped_size = 0; + const char *desc_type = "UNKNOWN"; + + /* Perform a table walk to find the terminal PTE and its size. */ + while (shift >= L3_ADDR_SHIFT) { + int index = (current_addr >> shift) & ((1UL << BITS_RESOLVED_PER_LVL) - 1); + pte = pte_ptr[index]; + + if (pte == 0) { + desc_type = "UNMAPPED"; + mapped_size = 1UL << shift; + break; + } else if ((pte & DESC_MASK) == TABLE_DESC) { + if (shift == L3_ADDR_SHIFT) { + /* At L3, TABLE_DESC (0x3) is actually PAGE_DESC */ + desc_type = "PAGE"; + mapped_size = GRANULE_SIZE; + break; + } else { + /* At L0, L1, L2, it means TABLE_DESC, continue walk */ + pte_ptr = (uint64_t *)(pte & XLAT_ADDR_MASK); + shift -= BITS_RESOLVED_PER_LVL; + } + } else if ((pte & DESC_MASK) == BLOCK_DESC) { + desc_type = "BLOCK"; + mapped_size = 1UL << shift; + break; + } else { + desc_type = "IMPOSSIBLE"; + mapped_size = 1UL << shift; + printk(BIOS_ERR, "Unexpected descriptor (PTE: 0x%016llx) found!\n", pte); + break; + } + } + + /* Align the start address to the beginning of the mapped block/page. */ + uint64_t start_of_mapping = ALIGN_DOWN(current_addr, mapped_size); + uint64_t current_print_end = start_of_mapping + mapped_size; + + if (last.valid && start_of_mapping == last.end && + (pte & ~XLAT_ADDR_MASK) == (last.pte & ~XLAT_ADDR_MASK)) { + /* Extend the last range */ + last.end = current_print_end; + } else { + /* Print the previous range */ + print_and_reset_last_range(&last); + /* Start a new range */ + last.start = start_of_mapping; + last.end = current_print_end; + last.pte = pte; + last.desc_type = desc_type; + last.valid = true; + } + + /* Advance current_addr */ + current_addr = start_of_mapping + mapped_size; + if (current_addr <= start_of_mapping) { + printk(BIOS_ERR, "Address overflow in %s!\n", __func__); + break; + } + } + + /* Print the very last accumulated range */ + print_and_reset_last_range(&last); + printk(BIOS_INFO, "\n"); +} + /* Func : mmu_config_range * Desc : This function repeatedly calls init_xlat_table with the base * address. Based on size returned from init_xlat_table, base_addr is updated @@ -243,6 +417,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) print_tag(BIOS_INFO, tag); sanity_check(base_addr, temp_size); + assert(raw_read_ttbr0() == (uint64_t)_ttb); while (temp_size) temp_size -= init_xlat_table(base_addr + (size - temp_size), @@ -253,6 +428,8 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) tlbiall(); dsb(); isb(); + + print_mmu_range(0, 1UL << BITS_PER_VA); } /* Func : mmu_init @@ -326,3 +503,65 @@ void mmu_enable(void) isb(); } + +/* + * Func : mmu_relocate_ttb + * Desc : Relocates a Translation Table Base (TTB) from _preram_ttb + * to _postram_ttb. This involves copying the table data and updating + * all internal pointers within the translation table entries to reflect + * the new location. + */ +void mmu_relocate_ttb(void) +{ + const uintptr_t old_base = (uintptr_t)_preram_ttb; + const uintptr_t new_base = (uintptr_t)_postram_ttb; + const uintptr_t offset = new_base - old_base; + + ASSERT_MSG(offset, "TTB relocation is not required.\n"); + + /* Ensure that next_free_table pointer is correct. */ + init_next_free_table(_preram_ttb, _epreram_ttb); + + const size_t used_size = (uintptr_t)next_free_table - old_base; + uint64_t *entry; + uint64_t *end = (uint64_t *)(new_base + used_size); + + printk(BIOS_INFO, "Relocating TTB: 0x%lx -> 0x%lx (offset 0x%lx)\n", + old_base, new_base, offset); + + /* Copy the used TTB region to the new location. */ + memcpy((void *)new_base, (void *)old_base, used_size); + + /* + * Update all internal table pointers. Since the entire TTB region is + * moved as a single block, every table pointer inside the descriptors + * needs to be adjusted by the same relative offset. + */ + for (entry = (uint64_t *)new_base; entry < end; entry++) { + /* + * In ARMv8, a descriptor with bits [1:0] == 0b11 can be either a + * Table descriptor or a Page descriptor. To differentiate, we + * check the Access Flag (bit 10). Table descriptors do not use + * this bit, whereas we ensure all Page/Block descriptors have it + * set. This relies on TCR.HAFT[42] remaining 0. + */ + if ((*entry & DESC_MASK) == TABLE_DESC && !(*entry & BLOCK_ACCESS)) + *entry += offset; + } + + /* Mark remaining table slots unused (first PTE == UNUSED_DESC). */ + for (entry = end; (u8 *)entry < _epostram_ttb; entry += GRANULE_SIZE / sizeof(*entry)) + *entry = UNUSED_DESC; + + /* Update TTBR0 to point to the new base address. */ + dsb(); + raw_write_ttbr0((uintptr_t)new_base); + isb(); + + tlb_invalidate_all(); + dsb(); + isb(); + + printk(BIOS_INFO, "TTB relocation is complete.\n"); + print_mmu_range(0, 1UL << BITS_PER_VA); +} diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c index 18f3eff056d..5c2a45d51d6 100644 --- a/src/arch/arm64/bl31.c +++ b/src/arch/arm64/bl31.c @@ -71,6 +71,11 @@ __weak void *soc_get_bl31_plat_params(void) return bl_aux_params; } +__weak void soc_prepare_bl31_handoff(void) +{ + /* Default: do nothing */ +} + void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) { struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); @@ -106,6 +111,12 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) void *bl31_plat_params = soc_get_bl31_plat_params(); + /* + * Perform SoC-specific housekeeping (e.g., clearing reset status, + * configuring security controller, or locking down registers). + */ + soc_prepare_bl31_handoff(); + /* MMU disable will flush cache, so passed params land in memory. */ raw_write_daif(SPSR_EXCEPTION_MASK); mmu_disable(); diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 5c938517be4..2ff2fc61cfe 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -5,6 +5,9 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H +/* ARM64 stacks need 16-byte alignment. */ +#define ARCH_STACK_ALIGN_SIZE 16 + #define TTB(addr, size) \ REGION(ttb, addr, size, 4K) \ _ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!"); @@ -32,9 +35,8 @@ _ = ASSERT(size % 1M == 0, \ "Framebuffer must fit exactly in 1M!"); -/* ARM64 stacks need 16-byte alignment. */ #define STACK(addr, size) \ - REGION(stack, addr, size, 16) \ + REGION(stack, addr, size, ARCH_STACK_ALIGN_SIZE) \ _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk"); \ ALIAS_REGION(stack, preram_stack) \ ALIAS_REGION(stack, postram_stack) diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 0db6d3ff28c..c2c4bad19f6 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -42,6 +42,7 @@ #define BLOCK_XN (1UL << 54) +#define BLOCK_SH_MASK (0x3 << BLOCK_SH_SHIFT) #define BLOCK_SH_SHIFT (8) #define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT) #define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT) @@ -152,5 +153,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag); void mmu_enable(void); /* Disable the MMU (which also disables dcache but not icache). */ void mmu_disable(void); +/* Relocates a Translation Table Base (TTB) from _preram_ttb to _postram_ttb */ +void mmu_relocate_ttb(void); #endif /* __ARCH_ARM64_MMU_H__ */ diff --git a/src/arch/arm64/include/bl31.h b/src/arch/arm64/include/bl31.h index bb99fcde718..613c508b8b9 100644 --- a/src/arch/arm64/include/bl31.h +++ b/src/arch/arm64/include/bl31.h @@ -18,4 +18,10 @@ void *soc_get_bl31_plat_params(void); that use the default soc_get_bl31_plat_params() implementation. */ void register_bl31_aux_param(struct bl_aux_param_header *param); +/* + * Perform SoC-specific housekeeping (e.g., clearing reset status, + * configuring security controller, or locking down registers). + */ +void soc_prepare_bl31_handoff(void); + #endif /* __BL31_H__ */ diff --git a/src/arch/arm64/thread.c b/src/arch/arm64/thread.c new file mode 100644 index 00000000000..65b6ff6757d --- /dev/null +++ b/src/arch/arm64/thread.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* The stack frame looks like the following after switch_to_thread. */ +struct saved_regs { + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; /* frame pointer */ + uint64_t x30; /* link register */ +}; + +extern void thread_entry_wrapper(void); + +void arch_prepare_thread(struct thread *t, + asmlinkage void (*thread_entry)(void *), void *arg) +{ + t->stack_current -= sizeof(struct saved_regs); + /* ABI requirement, should always be true */ + assert(IS_ALIGNED(t->stack_current, ARCH_STACK_ALIGN_SIZE)); + struct saved_regs *regs = (void *)t->stack_current; + regs->x19 = (uintptr_t)arg; + regs->x20 = (uintptr_t)thread_entry; + regs->x30 = (uintptr_t)thread_entry_wrapper; +} diff --git a/src/arch/arm64/thread_switch.S b/src/arch/arm64/thread_switch.S new file mode 100644 index 00000000000..3dff706dd4f --- /dev/null +++ b/src/arch/arm64/thread_switch.S @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * Routine for context switching between threads. + * + * asmlinkage void switch_to_thread(uintptr_t new_stack, + * uintptr_t *saved_stack) + * x0 - new_stack + * x1 - saved_stack + */ +ENTRY(switch_to_thread) + /* Save the callee saved registers, frame pointer and link register */ + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + + /* Save current stack pointer */ + mov x9, sp + str x9, [x1] + + /* Restore new stack pointer */ + mov sp, x0 + + /* Restore the callee saved registers and return to new thread */ + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + ret +ENDPROC(switch_to_thread) + +/* + * This is the entry point for a new thread. + * x19 - thread_arg + * x20 - thread_entry + */ +ENTRY(thread_entry_wrapper) + mov x0, x19 + br x20 +ENDPROC(thread_entry_wrapper) diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index cf393ba7007..bb33b5f694c 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -169,7 +169,7 @@ $(OPENSBI_TARGET): $(obj)/config.h | $(OPENSBI_SOURCE) mkdir -p $(OPENSBI_BUILD) $(MAKE) \ -C "$(OPENSBI_SOURCE)" \ - CC="$(GCC_ramstage) -fno-builtin" \ + CC="$(GCC_ramstage) -fno-builtin -std=gnu11" \ LD="$(LD_ramstage)" \ OBJCOPY="$(OBJCOPY_ramstage)" \ AR="$(AR_ramstage)" \ diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e7328b63750..d644fbf82b5 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -26,6 +26,10 @@ config ARCH_POSTCAR_X86_32 config ARCH_RAMSTAGE_X86_32 bool +config ARCH_SMM_X86_32 + bool + default ARCH_RAMSTAGE_X86_32 && !NO_SMM + config ARCH_ALL_STAGES_X86_32 bool default !ARCH_ALL_STAGES_X86_64 @@ -57,6 +61,10 @@ config ARCH_RAMSTAGE_X86_64 bool select SSE2 +config ARCH_SMM_X86_64 + bool + default ARCH_RAMSTAGE_X86_64 && !NO_SMM + config ARCH_ALL_STAGES_X86_64 bool select ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk index 785d35c0aa6..5b1cc827e94 100644 --- a/src/arch/x86/Makefile.mk +++ b/src/arch/x86/Makefile.mk @@ -4,6 +4,12 @@ ifeq ($(CONFIG_POSTCAR_STAGE),y) $(eval $(call init_standard_toolchain,postcar)) endif +ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_NO_SMM),y) +$(eval $(call init_standard_toolchain,smm)) +endif +endif + ################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -170,9 +176,6 @@ romstage-libs ?= $(eval $(call link_stage,romstage)) -# Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 -romstage-S-ccopts += -g0 - endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index efa1d078498..e2b0777d964 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -133,6 +133,7 @@ static acpi_generic_error_status_t *new_bert_status(void) return NULL; } + memset(status, 0, sizeof(*status)); status->error_severity = ACPI_GENERROR_SEV_NONE; return status; } @@ -191,6 +192,8 @@ static size_t sizeof_error_section(guid_t *guid) return sizeof(cper_ia32x64_proc_error_section_t); else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) return sizeof(cper_fw_err_rec_section_t); + else if (!guidcmp(guid, &CPER_SEC_PLATFORM_MEM_GUID)) + return sizeof(cper_mem_section_t); /* else if ... sizeof(structures not yet defined) */ else if (CONFIG(SOC_BERT_SIZEOF_ERROR_SECTION)) { size_t size = soc_bert_sizeof_error_section(guid); @@ -429,6 +432,31 @@ cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check( return proc_err_info; } +/* Helper to append an ACPI Generic Error Data Entry plus a CPER Memory + * Error Section. As many fields are populated as possible for the + * caller. + */ +acpi_hest_generic_data_v300_t *bert_append_plat_mem(acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + cper_mem_section_t *mem_sec; + + entry = bert_append_error_datasection(status, &CPER_SEC_PLATFORM_MEM_GUID); + if (!entry) + return NULL; + + status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID; + status->error_severity = ACPI_GENERROR_SEV_FATAL; + + memset(entry, 0, sizeof(*entry)); + entry->error_severity = ACPI_GENERROR_SEV_FATAL; + + mem_sec = section_of_acpientry(mem_sec, entry); + memset(mem_sec, 0, sizeof(*mem_sec)); + + return entry; +} + /* Helper to append an ACPI Generic Error Data Entry plus a CPER IA32/X64 * Processor Error Section. As many fields are populated as possible for the * caller. @@ -540,6 +568,8 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid) r = bert_append_ia32x64(status); else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) r = bert_append_fw_err(status); + else if (!guidcmp(guid, &CPER_SEC_PLATFORM_MEM_GUID)) + r = bert_append_plat_mem(status); else r = bert_append_error_datasection(status, guid); diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index f893e3a9f6b..d65a079829d 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define WAKEUP_BASE 0x600 @@ -20,6 +21,9 @@ void __noreturn acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); + if (CONFIG(TCG_OPAL_S3_UNLOCK)) + opal_s3_resume_unlock(); + /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 41c4f1c6e5d..3f8fad2dcae 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -94,7 +94,7 @@ static inline acpi_hest_generic_data_v300_t *acpi_hest_generic_data3( /* Add a context to an existing IA32/X64-type error entry */ cper_ia32x64_context_t *new_cper_ia32x64_ctx( acpi_generic_error_status_t *status, - cper_ia32x64_proc_error_section_t *x86err, int type, int array_size); + cper_ia32x64_proc_error_section_t *x86err, int type, int array_size_bytes); /* Helper to add an MSR context to an existing IA32/X64-type error entry */ cper_ia32x64_context_t *cper_new_ia32x64_context_msr( @@ -132,6 +132,8 @@ acpi_hest_generic_data_v300_t *bert_append_ia32x64( void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size); acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status); +acpi_hest_generic_data_v300_t *bert_append_plat_mem(acpi_generic_error_status_t *status); + /* Add a new event to the BERT region. An event consists of an ACPI Error * Status Block, a Generic Error Data Entry, and an associated CPER Error * Section. diff --git a/src/arch/x86/include/arch/bootblock.h b/src/arch/x86/include/arch/bootblock.h index 0019e5fab2b..a3cb6d69b2a 100644 --- a/src/arch/x86/include/arch/bootblock.h +++ b/src/arch/x86/include/arch/bootblock.h @@ -7,4 +7,8 @@ void bootblock_early_cpu_init(void); void bootblock_early_northbridge_init(void); void bootblock_early_southbridge_init(void); +void bootblock_cpu_init(void); +void bootblock_northbridge_init(void); +void bootblock_southbridge_init(void); + #endif diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index fde2ffadaa8..ba9d985de46 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk index f71fff48921..3af5560c107 100644 --- a/src/commonlib/Makefile.mk +++ b/src/commonlib/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +subdirs-y += gnat + subdirs-y += mipi subdirs-y += storage subdirs-y += bsd/zstd diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index df0e0d0b672..b73b89a5b17 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -4,6 +4,7 @@ #define _CBMEM_ID_H_ #define CBMEM_ID_ACPI 0x41435049 +#define CBMEM_ID_ACPI_BDAT 0x42444154 #define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_CNVS 0x434e5653 #define CBMEM_ID_ACPI_GNVS 0x474e5653 @@ -99,6 +100,7 @@ #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ + { CBMEM_ID_ACPI_BDAT, "ACPI BDAT " }, \ { CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_OPAL_S3_SCRATCH, "OPAL S3 SCR" }, \ diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h index 79e0c812dad..b299a19fdff 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -73,6 +73,10 @@ #define __nonstring #endif +#if defined(__STDC_VERSION__) && __STDC_VERSION__ < 202311L +#define typeof(x) __typeof__(x) +#endif + /* * This evaluates to the type of the first expression, unless that is constant * in which case it evaluates to the type of the second. This is useful when @@ -82,7 +86,7 @@ * literal is assigned to the temporary variable. If the literal doesn't fit in * the chosen type, -Werror=overflow will catch it, so this should be safe. */ -#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) __typeof__( \ +#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) typeof( \ __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) /* This creates a unique local variable name for use in macros. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index 49953055b04..598089ddea2 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -12,11 +12,11 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif -#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL) +#define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a)-1UL) #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x, a) ALIGN((x), (a)) -#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL)) -#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) +#define ALIGN_DOWN(x, a) ((x) & ~((typeof(x))(a)-1UL)) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1UL)) == 0) /* Double-evaluation unsafe min/max, for bitfields and outside of functions */ #define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) @@ -42,13 +42,13 @@ #ifndef ABS #define ABS(a) ({ \ - __typeof__(a) _abs_local_a = (a); \ + typeof(a) _abs_local_a = (a); \ (_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \ }) #endif #define IS_POWER_OF_2(x) ({ \ - __typeof__(x) _power_local_x = (x); \ + typeof(x) _power_local_x = (x); \ (_power_local_x & (_power_local_x - 1)) == 0; \ }) @@ -58,15 +58,15 @@ #define GENMASK(high, low) (((~0ULL) << (low)) & (~0ULL >> (63 - (high)))) #define DIV_ROUND_UP(x, y) ({ \ - __typeof__(x) _div_local_x = (x); \ - __typeof__(y) _div_local_y = (y); \ + typeof(x) _div_local_x = (x); \ + typeof(y) _div_local_y = (y); \ (_div_local_x + _div_local_y - 1) / _div_local_y; \ }) #define SWAP(a, b) do { \ - __typeof__(&(a)) _swap_local_a = &(a); \ - __typeof__(&(b)) _swap_local_b = &(b); \ - __typeof__(a) _swap_local_tmp = *_swap_local_a; \ + typeof(&(a)) _swap_local_a = &(a); \ + typeof(&(b)) _swap_local_b = &(b); \ + typeof(a) _swap_local_tmp = *_swap_local_a; \ *_swap_local_a = *_swap_local_b; \ *_swap_local_b = _swap_local_tmp; \ } while (0) @@ -93,8 +93,8 @@ #define _retry_impl(attempts, condition, expr, ...) \ ({ \ - __typeof__(condition) _retry_ret = \ - (__typeof__(condition))0; \ + typeof(condition) _retry_ret = \ + (typeof(condition))0; \ int _retry_attempts = (attempts); \ do { \ _retry_ret = (condition); \ diff --git a/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h index d5e54b508ed..f73700ec027 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h +++ b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h @@ -8,7 +8,7 @@ /* This structure is embedded somewhere in the (uncompressed) bootblock. */ struct metadata_hash_anchor { - uint8_t magic[8]; + uint8_t __nonstring magic[8]; struct vb2_hash cbfs_hash; /* NOTE: This is just reserving space. sizeof(struct vb2_hash) may change between configurations/versions and cannot be relied upon, so the FMAP hash must be placed diff --git a/src/commonlib/bsd/zstd/Makefile.mk b/src/commonlib/bsd/zstd/Makefile.mk index d04ad31e98f..b7f10bd2ea6 100644 --- a/src/commonlib/bsd/zstd/Makefile.mk +++ b/src/commonlib/bsd/zstd/Makefile.mk @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ zstd_support=n +ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_ZSTD),y) +zstd_support=y +endif ifeq ($(CONFIG_COMPRESS_RAMSTAGE_ZSTD),y) zstd_support=y endif diff --git a/src/commonlib/bsd/zstd/common/zstd_compiler.h b/src/commonlib/bsd/zstd/common/zstd_compiler.h index 80df87162e0..f2e98346415 100644 --- a/src/commonlib/bsd/zstd/common/zstd_compiler.h +++ b/src/commonlib/bsd/zstd/common/zstd_compiler.h @@ -400,7 +400,6 @@ unsigned char* ZSTD_maybeNullPtrAdd(unsigned char* ptr, ptrdiff_t add) /* Not all platforms that support msan provide sanitizers/msan_interface.h. * We therefore declare the functions we need ourselves, rather than trying to * include the header file... */ -#include /* size_t */ #define ZSTD_DEPS_NEED_STDINT #include "zstd_deps.h" /* intptr_t */ @@ -425,7 +424,6 @@ void __msan_print_shadow(const volatile void *x, size_t size); /* Not all platforms that support asan provide sanitizers/asan_interface.h. * We therefore declare the functions we need ourselves, rather than trying to * include the header file... */ -#include /* size_t */ /** * Marks a memory region ([addr, addr+size)) as unaddressable. diff --git a/src/lib/gnat/COPYING.RUNTIME b/src/commonlib/gnat/COPYING.RUNTIME similarity index 100% rename from src/lib/gnat/COPYING.RUNTIME rename to src/commonlib/gnat/COPYING.RUNTIME diff --git a/src/lib/gnat/COPYING3 b/src/commonlib/gnat/COPYING3 similarity index 100% rename from src/lib/gnat/COPYING3 rename to src/commonlib/gnat/COPYING3 diff --git a/src/lib/gnat/Makefile.mk b/src/commonlib/gnat/Makefile.mk similarity index 98% rename from src/lib/gnat/Makefile.mk rename to src/commonlib/gnat/Makefile.mk index 150a715067a..773615c2cc1 100644 --- a/src/lib/gnat/Makefile.mk +++ b/src/commonlib/gnat/Makefile.mk @@ -10,7 +10,7 @@ ADAFLAGS_libgnat-$(1) := \ --RTS=$$(obj)/libgnat-$(1)/ \ -gnatg \ -gnatpg \ - -I$$(src)/lib/gnat/ \ + -I$(dir) \ $$(GCC_ADAFLAGS_$(1)) \ -Werror \ -fno-pie \ diff --git a/src/lib/gnat/a-unccon.ads b/src/commonlib/gnat/a-unccon.ads similarity index 100% rename from src/lib/gnat/a-unccon.ads rename to src/commonlib/gnat/a-unccon.ads diff --git a/src/lib/gnat/ada.ads b/src/commonlib/gnat/ada.ads similarity index 100% rename from src/lib/gnat/ada.ads rename to src/commonlib/gnat/ada.ads diff --git a/src/lib/gnat/g-souinf.ads b/src/commonlib/gnat/g-souinf.ads similarity index 100% rename from src/lib/gnat/g-souinf.ads rename to src/commonlib/gnat/g-souinf.ads diff --git a/src/lib/gnat/gnat.ads b/src/commonlib/gnat/gnat.ads similarity index 100% rename from src/lib/gnat/gnat.ads rename to src/commonlib/gnat/gnat.ads diff --git a/src/lib/gnat/i-c.adb b/src/commonlib/gnat/i-c.adb similarity index 100% rename from src/lib/gnat/i-c.adb rename to src/commonlib/gnat/i-c.adb diff --git a/src/lib/gnat/i-c.ads b/src/commonlib/gnat/i-c.ads similarity index 100% rename from src/lib/gnat/i-c.ads rename to src/commonlib/gnat/i-c.ads diff --git a/src/lib/gnat/interfac.ads b/src/commonlib/gnat/interfac.ads similarity index 100% rename from src/lib/gnat/interfac.ads rename to src/commonlib/gnat/interfac.ads diff --git a/src/lib/gnat/s-atacco.ads b/src/commonlib/gnat/s-atacco.ads similarity index 100% rename from src/lib/gnat/s-atacco.ads rename to src/commonlib/gnat/s-atacco.ads diff --git a/src/lib/gnat/s-imenne.adb b/src/commonlib/gnat/s-imenne.adb similarity index 100% rename from src/lib/gnat/s-imenne.adb rename to src/commonlib/gnat/s-imenne.adb diff --git a/src/lib/gnat/s-imenne.ads b/src/commonlib/gnat/s-imenne.ads similarity index 100% rename from src/lib/gnat/s-imenne.ads rename to src/commonlib/gnat/s-imenne.ads diff --git a/src/lib/gnat/s-maccod.ads b/src/commonlib/gnat/s-maccod.ads similarity index 100% rename from src/lib/gnat/s-maccod.ads rename to src/commonlib/gnat/s-maccod.ads diff --git a/src/lib/gnat/s-parame.ads b/src/commonlib/gnat/s-parame.ads similarity index 100% rename from src/lib/gnat/s-parame.ads rename to src/commonlib/gnat/s-parame.ads diff --git a/src/lib/gnat/s-stoele.adb b/src/commonlib/gnat/s-stoele.adb similarity index 100% rename from src/lib/gnat/s-stoele.adb rename to src/commonlib/gnat/s-stoele.adb diff --git a/src/lib/gnat/s-stoele.ads b/src/commonlib/gnat/s-stoele.ads similarity index 100% rename from src/lib/gnat/s-stoele.ads rename to src/commonlib/gnat/s-stoele.ads diff --git a/src/lib/gnat/s-unstyp.ads b/src/commonlib/gnat/s-unstyp.ads similarity index 100% rename from src/lib/gnat/s-unstyp.ads rename to src/commonlib/gnat/s-unstyp.ads diff --git a/src/lib/gnat/system.ads b/src/commonlib/gnat/system.ads similarity index 100% rename from src/lib/gnat/system.ads rename to src/commonlib/gnat/system.ads diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index cb16e65c5cb..b4c96527c96 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -321,7 +321,7 @@ struct lb_gpio { #define ACTIVE_HIGH 1 uint32_t value; #define GPIO_MAX_NAME_LENGTH 16 - uint8_t name[GPIO_MAX_NAME_LENGTH]; + uint8_t __nonstring name[GPIO_MAX_NAME_LENGTH]; }; struct lb_gpios { @@ -647,6 +647,10 @@ enum boot_mode_t { LB_BOOT_MODE_LOW_BATTERY_CHARGING, /* Device is booting in due to charger insertion */ LB_BOOT_MODE_OFFMODE_CHARGING, + /* Device is booting in due to RTC alarm */ + LB_BOOT_MODE_RTC_WAKE, + /* Device is booting in "no-battery" */ + LB_BOOT_MODE_NO_BATTERY, }; /* diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index c294bee1179..97100a28aa9 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -15,10 +15,10 @@ * for negative dividends if the divisor variable type is unsigned. */ #define DIV_ROUND_CLOSEST(x, divisor)({ \ - __typeof__(x) _div_local_x = (x); \ - __typeof__(divisor) _div_local_d = (divisor); \ - (((__typeof__(x))-1) > 0 || \ - ((__typeof__(divisor))-1) > 0 || (_div_local_x) > 0) ? \ + typeof(x) _div_local_x = (x); \ + typeof(divisor) _div_local_d = (divisor); \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (_div_local_x) > 0) ? \ ((_div_local_x + (_div_local_d / 2)) / _div_local_d) : \ ((_div_local_x - (_div_local_d / 2)) / _div_local_d); \ }) @@ -31,7 +31,7 @@ * */ #define container_of(ptr, type, member) ({ \ - const __typeof__(((type *)0)->member) *__mptr = (ptr); \ + const typeof(((type *)0)->member) *__mptr = (ptr); \ (type *)((char *)__mptr - offsetof(type, member)); }) #ifndef alloca diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h index 33875bc10b5..aabadd919c7 100644 --- a/src/commonlib/include/commonlib/list.h +++ b/src/commonlib/include/commonlib/list.h @@ -22,21 +22,6 @@ struct list_node { /* Initialize a circular list, with `head` being a placeholder head node. */ void _list_init(struct list_node *head); -// Remove list_node node from the doubly linked list it's a part of. -void list_remove(struct list_node *node); -// Insert list_node node after list_node after in a doubly linked list. -void list_insert_after(struct list_node *node, struct list_node *after); -// Insert list_node node before list_node before in a doubly linked list. -// `before` must not be the placeholder head node. -void list_insert_before(struct list_node *node, struct list_node *before); -// Append the node to the end of the list. -static inline void list_append(struct list_node *node, struct list_node *head) -{ - _list_init(head); - /* With a circular list, we just need to insert before the head. */ - list_insert_before(node, head); -} - // Return if the list is empty. static inline bool list_is_empty(const struct list_node *head) { @@ -69,6 +54,31 @@ static inline struct list_node *list_last(const struct list_node *head) return list_prev(head, head); } +// Remove list_node node from the doubly linked list it's a part of. +void list_remove(struct list_node *node); +// Insert list_node node after list_node after in a doubly linked list. +void list_insert_after(struct list_node *node, struct list_node *after); +// Insert list_node node before list_node before in a doubly linked list. +// `before` must not be the placeholder head node. +void list_insert_before(struct list_node *node, struct list_node *before); + +// Append the node to the end of the list. +static inline void list_append(struct list_node *node, struct list_node *head) +{ + _list_init(head); + /* With a circular list, we just need to insert before the head. */ + list_insert_before(node, head); +} + +// Pop the node from the end of the list. +static inline struct list_node *list_pop(struct list_node *head) +{ + struct list_node *last = list_last(head); + if (last) + list_remove(last); + return last; +} + // Get the number of list elements. size_t list_length(const struct list_node *head); diff --git a/src/commonlib/include/commonlib/memory_info.h b/src/commonlib/include/commonlib/memory_info.h index 48b71581852..dc680ad6349 100644 --- a/src/commonlib/include/commonlib/memory_info.h +++ b/src/commonlib/include/commonlib/memory_info.h @@ -146,4 +146,13 @@ struct memory_info { struct dimm_info dimm[DIMM_INFO_TOTAL]; } __packed; +union bus_width_struct { + uint8_t raw_data; + struct { + uint8_t primary_bus_width_per_subchan : 3; // Bits 0-2: Primary bus width per sub-channel + uint8_t bus_width_ext_per_subchannel : 2; // Bits 3-4: Bus width Extension per sub-channel + uint8_t number_of_subchannel_per_dimm : 3; // Bits 5-7: Number of sub-channels per dimm + } bits; +} __packed; + #endif /* _COMMONLIB_MEMORY_INFO_H_ */ diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 3999b35069b..dd08b2178b9 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -157,8 +157,8 @@ enum timestamp_id { /* 990+ reserved for vendorcode extensions (990-997: Intel ME continued) */ TS_ME_ROM_START = 990, - TS_ISSE_DMU_LOAD_END = 991, - TS_ESE_LOAD_AUNIT_END = 992, + TS_DMU_LOAD_END = 991, + TS_AUNIT_LOAD_END = 992, /* 998-999 reserved for ARM Trusted firmware) */ TS_TFA_LOAD_BL32_START = 998, @@ -374,8 +374,8 @@ static const struct timestamp_id_to_name { /* Intel ME continued */ TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), - TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), - TS_NAME_DEF(TS_ESE_LOAD_AUNIT_END, 0, "ESE completed AUnit loading"), + TS_NAME_DEF(TS_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), + TS_NAME_DEF(TS_AUNIT_LOAD_END, 0, "AUnit load completed"), TS_NAME_DEF(TS_TFA_LOAD_BL32_START, 0, "BL32(secure_os) loading start"), TS_NAME_DEF(TS_TFA_LOAD_BL32_END, 0, "BL32(secure_os) loading end"), diff --git a/src/commonlib/region.c b/src/commonlib/region.c index fbc6276e96b..0727349d5ac 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -227,7 +227,7 @@ static void *mdev_mmap(const struct region_device *rd, size_t offset, { const struct mem_region_device *mdev; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); return &mdev->base[offset]; } @@ -243,7 +243,7 @@ static ssize_t mdev_readat(const struct region_device *rd, void *b, { const struct mem_region_device *mdev; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); memcpy(b, &mdev->base[offset], size); @@ -255,7 +255,7 @@ static ssize_t mdev_writeat(const struct region_device *rd, const void *b, { const struct mem_region_device *mdev; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); memcpy(&mdev->base[offset], b, size); @@ -267,7 +267,7 @@ static ssize_t mdev_eraseat(const struct region_device *rd, size_t offset, { const struct mem_region_device *mdev; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); memset(&mdev->base[offset], 0, size); @@ -307,7 +307,7 @@ void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset, struct mmap_helper_region_device *mdev; void *mapping; - mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + mdev = container_of((void *)rd, typeof(*mdev), rdev); mapping = mem_pool_alloc(mdev->pool, size); @@ -326,7 +326,7 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping) { struct mmap_helper_region_device *mdev; - mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + mdev = container_of((void *)rd, typeof(*mdev), rdev); mem_pool_free(mdev->pool, mapping); @@ -358,7 +358,7 @@ static void *xlate_mmap(const struct region_device *rd, size_t offset, }; const struct xlate_window *xlwindow; - xldev = container_of(rd, __typeof__(*xldev), rdev); + xldev = container_of(rd, typeof(*xldev), rdev); xlwindow = xlate_find_window(xldev, &req); if (!xlwindow) @@ -392,7 +392,7 @@ static ssize_t xlate_readat(const struct region_device *rd, void *b, const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; - xldev = container_of(rd, __typeof__(*xldev), rdev); + xldev = container_of(rd, typeof(*xldev), rdev); xlwindow = xlate_find_window(xldev, &req); if (!xlwindow) @@ -413,7 +413,7 @@ static ssize_t xlate_writeat(const struct region_device *rd, const void *b, const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; - xldev = container_of(rd, __typeof__(*xldev), rdev); + xldev = container_of(rd, typeof(*xldev), rdev); xlwindow = xlate_find_window(xldev, &req); if (!xlwindow) @@ -434,7 +434,7 @@ static ssize_t xlate_eraseat(const struct region_device *rd, const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; - xldev = container_of(rd, __typeof__(*xldev), rdev); + xldev = container_of(rd, typeof(*xldev), rdev); xlwindow = xlate_find_window(xldev, &req); if (!xlwindow) diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index c53379b69ff..a4eb3428135 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -18,6 +18,10 @@ void __weak bootblock_early_northbridge_init(void) { } void __weak bootblock_early_southbridge_init(void) { } void __weak bootblock_early_cpu_init(void) { } +void __weak bootblock_northbridge_init(void) { } +void __weak bootblock_southbridge_init(void) { } +void __weak bootblock_cpu_init(void) { } + void bootblock_soc_early_init(void) { bootblock_early_northbridge_init(); @@ -27,6 +31,9 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + bootblock_northbridge_init(); + bootblock_southbridge_init(); + bootblock_cpu_init(); /* Halt if there was a built in self test failure */ report_bist_failure(saved_bist); } diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk index 4a01449e4ea..b45e2a8a110 100644 --- a/src/cpu/intel/fit/Makefile.mk +++ b/src/cpu/intel/fit/Makefile.mk @@ -15,9 +15,9 @@ intel_fit-align := 16 ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y) regions-for-file-intel_fit = BOOTBLOCK -regions-for-file-intel_fit_ts = TOPSWAP +regions-for-file-intel_fit_ts = BOOTBLOCK_B -TS_MCU_REGION = COREBOOT_TS +TS_MCU_REGION = COREBOOT_B else TS_MCU_REGION = COREBOOT endif diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index b66a4aa9ee8..8025aa528df 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,10 @@ config CPU_INTEL_HASWELL select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE + select HAVE_INSMM_STS select CPU_INTEL_COMMON_VOLTAGE + select DRIVERS_INTEL_OC_MAILBOX + select HAS_DIGITAL_IO_POWER_DOMAIN if CPU_INTEL_HASWELL diff --git a/src/cpu/intel/haswell/Makefile.mk b/src/cpu/intel/haswell/Makefile.mk index 65e411df63b..a3765d75d1d 100644 --- a/src/cpu/intel/haswell/Makefile.mk +++ b/src/cpu/intel/haswell/Makefile.mk @@ -17,8 +17,6 @@ ramstage-y += haswell_init.c ramstage-y += pcode_mailbox.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -smm-y += finalize.c - subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/haswell/cfr.h b/src/cpu/intel/haswell/cfr.h new file mode 100644 index 00000000000..2c92c1540a0 --- /dev/null +++ b/src/cpu/intel/haswell/cfr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CPU_INTEL_HASWELL_CFR_H_ +#define _CPU_INTEL_HASWELL_CFR_H_ + +#include + +static const struct sm_object cpu_power_limit_lock = SM_DECLARE_BOOL({ + .opt_name = "cpu_power_limit_lock", + .ui_name = "CPU power limit lock", + .ui_helptext = "Lock CPU package power limits after programming.\n" + "This prevents the power limits from being changed by the OS or runtime tools.\n", + .default_value = false, +}); + +#endif /* _CPU_INTEL_HASWELL_CFR_H_ */ diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c deleted file mode 100644 index 398387644ec..00000000000 --- a/src/cpu/intel/haswell/finalize.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "haswell.h" - -void intel_cpu_haswell_finalize_smm(void) -{ - /* Lock memory configuration to protect SMM */ - msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); -} diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index b8cc98a5703..f2245a6d29a 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,6 +84,7 @@ #define PKG_POWER_LIMIT_CLAMP (1 << 16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f +#define PKG_POWER_LIMIT_LOCK (1U << 31) #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 @@ -159,9 +160,6 @@ enum { NUM_C_STATES, }; -/* Lock MSRs */ -void intel_cpu_haswell_finalize_smm(void); - /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 7d58795db05..49976815918 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -2,6 +2,7 @@ #include #include + #include #include #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -260,6 +262,7 @@ void set_power_limits(u8 power_limit_1_time) msr_t limit; unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time; + unsigned int pl1, pl2; u8 power_limit_1_val; if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) @@ -292,17 +295,30 @@ void set_power_limits(u8 power_limit_1_time) power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - /* Set long term power limit to TDP */ + const unsigned int pl1_override_w = get_uint_option("tdp_pl1_override", 0); + const unsigned int pl2_override_w = get_uint_option("tdp_pl2_override", 0); + + /* Set long term power limit to TDP if not overridden */ limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + pl1 = pl1_override_w ? (pl1_override_w * power_unit) : tdp; + printk(BIOS_DEBUG, "CPU PL1 = %u Watts\n", pl1 / power_unit); + limit.lo |= pl1 & PKG_POWER_LIMIT_MASK; limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; - /* Set short term power limit to 1.25 * TDP */ + /* Set short term power limit to 1.25 * TDP if not overridden */ limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + pl2 = pl2_override_w ? (pl2_override_w * power_unit) : ((tdp * 125) / 100); + if (pl2 < pl1) + pl2 = pl1; + printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", pl2 / power_unit); + limit.hi |= pl2 & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_EN; + if (get_uint_option("cpu_power_limit_lock", 0)) { + limit.hi |= PKG_POWER_LIMIT_LOCK; + printk(BIOS_DEBUG, "Locking package power limits\n"); + } /* Power limit 2 time is only programmable on server SKU */ wrmsr(MSR_PKG_POWER_LIMIT, limit); @@ -587,6 +603,12 @@ void mp_init_cpus(struct bus *cpu_bus) MTRR_TYPE_WRPROT); } +static void haswell_final(struct device *dev) +{ + /* Lock memory configuration to protect SMM */ + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); +} + static struct device_operations cpu_dev_ops = { .init = cpu_core_init, }; @@ -610,6 +632,7 @@ struct device_operations haswell_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, + .final = haswell_final, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f8fb5891599..f87a5d8129e 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -57,10 +57,15 @@ static void set_max_ratio(void) perf_ctl.hi = 0; - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - wrmsr(IA32_PERF_CTL, perf_ctl); + /* Check for configurable TDP option */ + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio (no Turbo mode) */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } printk(BIOS_DEBUG, "model_x065x: frequency set to %d\n", ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); @@ -68,21 +73,10 @@ static void set_max_ratio(void) static void model_2065x_init(struct device *cpu) { - char processor_name[49]; - /* Clear out pending MCEs */ /* This should only be done on a cold boot */ mca_clear_status(); - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - printk(BIOS_INFO, "CPU:lapic=%d, boot_cpu=%d\n", lapicid(), - boot_cpu()); - - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - enable_lapic_tpr(); /* Set virtualization based on Kconfig option */ @@ -96,9 +90,6 @@ static void model_2065x_init(struct device *cpu) /* Thermal throttle activation offset */ configure_thermal_target(cpu); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -151,6 +142,9 @@ static void per_cpu_smm_trigger(void) static void post_mp_init(void) { + /* Set Max Ratio. This has no effect until BIOS_RESET_CPL is set. */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index cf1664044ab..a85e794762b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,6 +3,7 @@ config CPU_INTEL_MODEL_206AX bool select ARCH_X86 + select HAVE_INSMM_STS select HAVE_X86_64_SUPPORT select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 0fdbacbe8d5..bec55049cef 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -384,12 +384,19 @@ static void set_max_ratio(void) perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ + if (get_turbo_state() == TURBO_ENABLED) { + /* + * It takes 1200msec after BIOS_RESET_CPL before the CPU starts using + * the turbo. + */ + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio (no Turbo mode) */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; } else { - /* Platform Info bits 15:8 give max ratio */ + /* Platform Info bits 15:8 give max ratio (no Turbo mode) */ msr = rdmsr(MSR_PLATFORM_INFO); perf_ctl.lo = msr.lo & 0xff00; } @@ -421,17 +428,8 @@ unsigned int smbios_processor_external_clock(void) static void model_206ax_report(void) { static const char *const mode[] = {"NOT ", ""}; - char processor_name[49]; int vt, txt, aes; - uint32_t cpu_id, cpu_feature_flag; - - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* CPUID and features */ - cpu_id = cpu_get_cpuid(); - printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id); + uint32_t cpu_feature_flag; cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; @@ -448,12 +446,6 @@ static void model_206ax_init(struct device *cpu) /* This should only be done on a cold boot */ mca_clear_status(); - /* Print infos */ - model_206ax_report(); - - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - enable_lapic_tpr(); /* Set virtualization based on Kconfig option */ @@ -476,9 +468,6 @@ static void model_206ax_init(struct device *cpu) /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -486,6 +475,9 @@ static void model_206ax_init(struct device *cpu) /* MP initialization support. */ static void pre_mp_init(void) { + /* Print infos */ + model_206ax_report(); + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); @@ -531,6 +523,9 @@ static void per_cpu_smm_trigger(void) static void post_mp_init(void) { + /* Set Max Ratio. This has no effect until BIOS_RESET_CPL is set. */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index e05ba6f6fb5..d660eba84a9 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -6,3 +6,4 @@ config CPU_INTEL_MODEL_F2X select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select SSE2 + select X86_INIT_NEED_2ND_SIPI diff --git a/src/cpu/intel/model_f2x/mp_init.c b/src/cpu/intel/model_f2x/mp_init.c index 010b1770c14..df05332c077 100644 --- a/src/cpu/intel/model_f2x/mp_init.c +++ b/src/cpu/intel/model_f2x/mp_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #include /* Parallel MP initialization support. */ diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 229ddb0b962..dd7fa6c751d 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,4 @@ config CPU_INTEL_MODEL_F3X select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select SSE2 + select X86_INIT_NEED_2ND_SIPI diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index a7332e0a3fa..0574d685871 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_F4X select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select SSE2 + select X86_INIT_NEED_2ND_SIPI diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index fffca39585a..49e32b88f41 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -13,6 +13,7 @@ config CPU_INTEL_SLOT_1 select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE select RESERVE_MTRRS_FOR_OS + select X86_INIT_NEED_2ND_SIPI if CPU_INTEL_SLOT_1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5f6bf7bd18d..10764aee584 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -258,13 +258,13 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config X86_INIT_NEED_1_SIPI +config X86_INIT_NEED_2ND_SIPI bool default n help - This option limits the number of SIPI signals sent during the - common AP setup. Intel documentation specifies an INIT SIPI SIPI - sequence, however this doesn't work on some AMD and Intel platforms. + This option enables a second SIPI signal sent during the common AP setup. + Intel documentation specifies an INIT SIPI SIPI sequence, however this + doesn't work on some AMD and Intel platforms. These newer AMD and Intel platforms don't need the 10ms wait between INIT and SIPI, so skip that too to save some time. diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index ed2005e91ef..a048ee980d4 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -37,6 +37,17 @@ struct mp_callback { static char processor_name[49]; +static void write_back_cached_data(const void *start, size_t size) +{ + if (self_snooping_supported()) + return; + + if (clflush_supported()) + clflush_region((uintptr_t)start, size); + else + wbinvd(); +} + /* * A mp_flight_record details a sequence of calls for the APs to perform * along with the BSP to coordinate sequencing. Each flight record either @@ -366,14 +377,9 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params) ap_count = &sp->ap_count; atomic_set(ap_count, 0); - if (!self_snooping_supported()) { - /* Make sure SIPI data hits RAM so the APs that come up will see the - startup code even if the caches are disabled. */ - if (clflush_supported()) - clflush_region((uintptr_t)mod_loc, module_size); - else - wbinvd(); - } + /* Make sure SIPI data hits RAM so the APs that come up will see the + startup code even if the caches are disabled. */ + write_back_cached_data(mod_loc, module_size); return ap_count; } @@ -481,7 +487,16 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap /* Send INIT IPI to all but self. */ lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT); - if (!CONFIG(X86_INIT_NEED_1_SIPI)) { + if (CONFIG(X86_INIT_NEED_2ND_SIPI)) { + /* + * The Multiprocessor Specification 1.4 (1997) example code suggests + * that there should be a 10ms delay between the BSP asserting INIT + * and de-asserting INIT, when starting a remote processor. + * But that slows boot and resume on modern processors, which include + * many cores and don't require that delay. Keep the delay for older + * processors where removing the delay could not be tested. + */ + printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); @@ -603,6 +618,8 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; atomic_t *ap_count; + void *microcode_pointer_dram = NULL; + enum cb_err ret; g_cpu_bus = cpu_bus; @@ -630,6 +647,32 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) return CB_ERR; } + /* + * On Server platforms with high core count or older platforms with + * slow SPI flash interface loading the microcode from SPI flash MMIO + * area on each AP slows down MPinit. On Server platforms tests showed + * a difference of multiple seconds. Cache the microcode in DRAM once + * before starting the APs. + */ + if (p->microcode_pointer && p->microcode_size) { + microcode_pointer_dram = malloc(p->microcode_size); + if (microcode_pointer_dram) { + memcpy(microcode_pointer_dram, p->microcode_pointer, + p->microcode_size); + /* + * Make sure microcode hits RAM so the APs that come up will + * see the microcode even if the caches are disabled. + */ + write_back_cached_data(microcode_pointer_dram, + p->microcode_size); + p->microcode_pointer = microcode_pointer_dram; + } else { + /* For developers: Increase CONFIG_HEAP_SIZE */ + printk(BIOS_WARNING, "%s: Not enough heap. MPinit will be slower.\n", + __func__); + } + } + /* Copy needed parameters so that APs have a reference to the plan. */ mp_info.num_records = p->num_records; mp_info.records = p->flight_plan; @@ -649,7 +692,11 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) } /* Walk the flight plan for the BSP. */ - return bsp_do_flight_plan(p); + ret = bsp_do_flight_plan(p); + + free(microcode_pointer_dram); + + return ret; } void smm_initiate_relocation_parallel(void) diff --git a/src/cpu/x86/smi_trigger.c b/src/cpu/x86/smi_trigger.c index 52c72472b21..d164f659651 100644 --- a/src/cpu/x86/smi_trigger.c +++ b/src/cpu/x86/smi_trigger.c @@ -22,6 +22,8 @@ static void apmc_log(const char *fn, u8 cmd) break; case APM_CNT_SMMSTORE: break; + case APM_CNT_ROM_ARMOR: + break; case APM_CNT_SMMINFO: break; default: diff --git a/src/cpu/x86/smm/Makefile.mk b/src/cpu/x86/smm/Makefile.mk index a104a87743c..351745d7cd1 100644 --- a/src/cpu/x86/smm/Makefile.mk +++ b/src/cpu/x86/smm/Makefile.mk @@ -5,7 +5,7 @@ ramstage-$(CONFIG_SMM_PCI_RESOURCE_STORE) += pci_resource_store.c smm-$(CONFIG_SMM_PCI_RESOURCE_STORE) += pci_resource_store.c -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_SMM_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) $(eval $(call create_class_compiler,smmstub,x86_32)) else @@ -51,7 +51,7 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual $(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_SMM_X86_32),y) $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o,x86_32)) else $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o,x86_64)) @@ -66,7 +66,7 @@ $(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/sm # C-based SMM handler. -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_SMM_X86_32),y) $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a,x86_32)) else $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a,x86_64)) diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 41ef14a9235..7a123cb7d47 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -66,7 +66,7 @@ int i2c_dev_readb(struct device *const dev) return busdev->ops->ops_smbus_bus->recv_byte(dev); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte\n", dev_path(busdev)); return -1; } @@ -88,7 +88,7 @@ int i2c_dev_writeb(struct device *const dev, uint8_t val) return busdev->ops->ops_smbus_bus->send_byte(dev, val); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte\n", dev_path(busdev)); return -1; } @@ -125,7 +125,7 @@ int i2c_dev_readb_at(struct device *const dev, uint8_t off) return busdev->ops->ops_smbus_bus->read_byte(dev, off); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte\n", dev_path(busdev)); return -1; } @@ -148,7 +148,7 @@ int i2c_dev_writeb_at(struct device *const dev, const uint8_t off, const uint8_t return busdev->ops->ops_smbus_bus->write_byte(dev, off, val); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte\n", dev_path(busdev)); return -1; } @@ -183,7 +183,7 @@ int i2c_dev_read_at16(struct device *const dev, uint8_t *const buf, const size_t else return len; } else { - printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer\n", dev_path(busdev)); return -1; } } @@ -218,7 +218,7 @@ int i2c_dev_read_at(struct device *const dev, uint8_t *const buf, const size_t l else return len; } else { - printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer\n", dev_path(busdev)); return -1; } } @@ -253,7 +253,7 @@ int i2c_dev_write_at(struct device *const dev, uint8_t *const buf, const size_t else return len; } else { - printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer\n", dev_path(busdev)); return -1; } } diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 3c2f06e013a..8885402ac55 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -814,7 +814,7 @@ void pciexp_dev_read_resources(struct device *dev) if (!sriovpos) return; - sriovpos = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_SRIOV_ID, PCIE_EXT_CAP_OFFSET); + sriovpos = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_SRIOV_ID, 0); if (!sriovpos) return; diff --git a/src/device/xhci_resource.c b/src/device/xhci_resource.c index 31f26108232..dbd72510ced 100644 --- a/src/device/xhci_resource.c +++ b/src/device/xhci_resource.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/drivers/amd/ftpm/Kconfig b/src/drivers/amd/ftpm/Kconfig index 9e9c3825728..daf5150f21b 100644 --- a/src/drivers/amd/ftpm/Kconfig +++ b/src/drivers/amd/ftpm/Kconfig @@ -5,9 +5,9 @@ config AMD_CRB_FTPM default n depends on !CRB_TPM depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 - # The fTPM needs to access the SPI flash when ROM Armor - # is not being used, thus select SOC_AMD_COMMON_BLOCK_PSP_SMI. - select SOC_AMD_COMMON_BLOCK_PSP_SMI + # The fTPM needs to access the SPI flash, either directly when + # ROM Armor is used, or via PSP SMI when ROM Armor is not used. + depends on SOC_AMD_COMMON_BLOCK_PSP_SMI || SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 help Mainboard has AMD fTPM with Command Response Buffer support. The fTPM is based on the CRB interface as defined by TCG, diff --git a/src/drivers/amd/ftpm/tis.c b/src/drivers/amd/ftpm/tis.c index 0f0dd5c899c..b6f2324893b 100644 --- a/src/drivers/amd/ftpm/tis.c +++ b/src/drivers/amd/ftpm/tis.c @@ -62,6 +62,17 @@ static void (*tpm_start_callbacks[])(void *) = { tpm_start_func1_cb, }; +static void crb_tpm_init_mailbox(struct device *dev) +{ + /* + * When TPM2 is enabled crb_tis_probe() will call crb_tpm_init() + * and then issue tlcl_startup(). When not selected only initialize the + * mailbox, but don't start the TPM. + */ + if (!CONFIG(TPM2)) + crb_tpm_init(); +} + #define TPM_START_UUID "6bbf6cab-5463-4714-b7cd-f0203c0368d4" static void crb_tpm_fill_ssdt(const struct device *dev) @@ -111,7 +122,7 @@ static const char *crb_tpm_acpi_name(const struct device *dev) return "TPM2"; } -#if CONFIG(GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) static tpm_result_t tpm_get_cap(uint32_t property, uint32_t *value) { TPMS_CAPABILITY_DATA cap_data; @@ -181,14 +192,38 @@ static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned lon } #endif +static unsigned long acpi_create_tpm2(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + /* When TPM2 is enabled table is written by common code */ + if (CONFIG(TPM2)) + return current; + + if (!crb_tpm_is_active()) + return current; + + acpi_tpm2_t *tpm2 = (acpi_tpm2_t *)(uintptr_t)current; + acpi_write_tpm2(tpm2, NULL, 0, crb_tpm_base_address() + 0x40, ACPI_TPM2_SM_ACPI_START); + + current += tpm2->header.length; + current = acpi_align_current(current); + + acpi_add_table(rsdp, tpm2); + + return current; +} + static struct device_operations __maybe_unused amd_crb_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, + .init = crb_tpm_init_mailbox, #if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = acpi_create_tpm2, .acpi_name = crb_tpm_acpi_name, .acpi_fill_ssdt = crb_tpm_fill_ssdt, #endif -#if CONFIG(GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) .get_smbios_data = smbios_write_type43_tpm, #endif }; diff --git a/src/drivers/amd/ftpm/tpm.c b/src/drivers/amd/ftpm/tpm.c index e5ab0dea39a..22b69724bdd 100644 --- a/src/drivers/amd/ftpm/tpm.c +++ b/src/drivers/amd/ftpm/tpm.c @@ -25,8 +25,10 @@ */ #include +#include #include #include +#include #include #include #include @@ -93,12 +95,39 @@ static tpm_result_t crb_wait_for_reg32(const void *addr, } } -static int erase_region(const char *name) +static int synchronize_region(const char *name) +{ + struct region ar; + + if (fmap_locate_area(name, &ar)) { + printk(BIOS_ERR, "FTPM: Unable to find FMAP region %s\n", name); + return -1; + } + + if (backup_boot_device_sync_subregion(&ar, true)) { + printk(BIOS_ERR, "FTPM: Failed to synchronize subregion %s\n", name); + return -1; + } + + return 0; +} + +static int erase_region(const char *name, const enum boot_device boot_device) { struct region_device store; + struct region ar; - if (fmap_locate_area_as_rdev_rw(name, &store)) { - printk(BIOS_ERR, "fTPM: Unable to find FMAP region %s\n", name); + if (fmap_locate_area(name, &ar)) { + printk(BIOS_ERR, "FTPM: Unable to find FMAP region %s\n", name); + return -1; + } + if (boot_device == FLASH_PRIMARY && boot_device_rw_subregion(&ar, &store)) { + printk(BIOS_ERR, "FTPM: Unable to find FMAP region %s\n", name); + return -1; + } + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH) && boot_device == FLASH_BACKUP && + backup_boot_device_rw_subregion(&ar, &store)) { + printk(BIOS_ERR, "FTPM: Unable to find FMAP region %s\n", name); return -1; } @@ -107,7 +136,6 @@ static int erase_region(const char *name) return -1; printk(BIOS_NOTICE, "fTPM: Erased FMAP region %s\n", name); - return 0; } @@ -129,15 +157,23 @@ tpm_result_t crb_tpm_init(void) psp_ftpm_needs_recovery(&psp_rpmc_nvram, &psp_nvram, &psp_dir); if (psp_rpmc_nvram) { - if (erase_region(FMAP_NAME_PSP_RPMC_NVRAM)) - psp_rpmc_nvram = false; /* Skip reset if erase failed */ - } + if (erase_region(FMAP_NAME_PSP_RPMC_NVRAM, FLASH_PRIMARY)) + psp_rpmc_nvram = false; /* Skip reset if erase failed */ - if (psp_nvram) { - if (erase_region(FMAP_NAME_PSP_NVRAM)) - psp_nvram = false; /* Skip reset if erase failed */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH) && + erase_region(FMAP_NAME_PSP_RPMC_NVRAM, FLASH_BACKUP)) + printk(BIOS_ERR, "Failed to erase backup " FMAP_NAME_PSP_RPMC_NVRAM + " FMAP region\n"); } + if (psp_nvram) { + if (erase_region(FMAP_NAME_PSP_NVRAM, FLASH_PRIMARY)) + psp_nvram = false; /* Skip reset if erase failed */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH) && + erase_region(FMAP_NAME_PSP_NVRAM, FLASH_BACKUP)) + printk(BIOS_ERR, "Failed to erase backup " FMAP_NAME_PSP_NVRAM + " FMAP region\n"); + } if (psp_rpmc_nvram || psp_nvram) { printk(BIOS_DEBUG, "fTPM: Reset to recover fTPM...\n"); cold_reset(); @@ -151,6 +187,11 @@ tpm_result_t crb_tpm_init(void) if (!psp_ftpm_is_active()) return CB_ERR_NOT_IMPLEMENTED; + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) { + synchronize_region(FMAP_NAME_PSP_NVRAM); + synchronize_region(FMAP_NAME_PSP_RPMC_NVRAM); + } + if (ENV_HAS_CBMEM) { /* setting up fTPM communication buffers in cbmem */ const struct cbmem_entry *entry; @@ -177,7 +218,6 @@ tpm_result_t crb_tpm_init(void) write64(CRB_REG(CRB_REG_CMD_ADDR), (uintptr_t)buf); write32(CRB_REG(CRB_REG_RESP_SIZE), FTPM_CRB_SIZE); write64(CRB_REG(CRB_REG_RESP_ADDR), (uintptr_t)buf + FTPM_CRB_SIZE); - /* * The OS will read the CRB registers to find the communication * buffers. No need to advertise it in ACPI. diff --git a/src/drivers/amd/ftpm/tpm.h b/src/drivers/amd/ftpm/tpm.h index aaae99eb348..17b6aed8824 100644 --- a/src/drivers/amd/ftpm/tpm.h +++ b/src/drivers/amd/ftpm/tpm.h @@ -21,7 +21,12 @@ /* address of locality 0 (CRB) */ #define CRB_REG(REG) ((void *)(uintptr_t)(psp_ftpm_base_address() + (REG))) +#if ENV_RAMSTAGE tpm_result_t crb_tpm_init(void); +#else +/* fTPM needs SMM to fully function. Indicate failure until ramstage. */ +static inline tpm_result_t crb_tpm_init(void) { return TPM_CB_PROBE_FAILURE; } +#endif size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, void *tpm2_response, size_t max_response); bool crb_tpm_is_active(void); diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index c33d63428ef..12b39eabbdf 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "tpm.h" diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 70d17cb7164..47826f75fec 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/gfx/nvidia/Kconfig b/src/drivers/gfx/nvidia/Kconfig new file mode 100644 index 00000000000..eb2d60dff65 --- /dev/null +++ b/src/drivers/gfx/nvidia/Kconfig @@ -0,0 +1,39 @@ +config DRIVERS_GFX_NVIDIA + bool + default n + depends on HAVE_ACPI_TABLES + help + Support for NVIDIA Optimus graphics + +config DRIVERS_GFX_NVIDIA_BRIDGE + hex "PCI bridge for the GPU device" + default 0x01 + depends on DRIVERS_GFX_NVIDIA + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + depends on DRIVERS_GFX_NVIDIA + bool + default n + help + Support for NVIDIA Dynamic Boost + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + int "Total processor power offset from default TGP in watts" + default 45 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This identifies the available power for the CPU or GPU boost + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN + int "Minimum TGP offset from default TGP in watts" + default 0 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This is used to transfer power from the GPU to the CPU + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + int "Maximum TGP offset from default TGP in watts" + default 0 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This is used to transfer power from the CPU to the GPU diff --git a/src/drivers/gfx/nvidia/Makefile.mk b/src/drivers/gfx/nvidia/Makefile.mk new file mode 100644 index 00000000000..32ddf7e64e5 --- /dev/null +++ b/src/drivers/gfx/nvidia/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c + +ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c diff --git a/src/drivers/gfx/nvidia/acpi/coffeelake.asl b/src/drivers/gfx/nvidia/acpi/coffeelake.asl new file mode 100644 index 00000000000..c515ec1cb29 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/coffeelake.asl @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA GC6 on CFL and CML CPU PCIe ports */ + +// Memory mapped PCI express config space +OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000) + +Field (PCIC, ByteAcc, NoLock, Preserve) { + PVID, 16, + PDID, 16, + + Offset (0x248), + , 7, + L23E, 1, /* L23_Rdy Entry Request */ + L23R, 1, /* L23_Rdy to Detect Transition */ + + Offset (0xC20), + , 4, + P0AP, 2, /* Additional power savings */ + + Offset (0xC38), + , 3, + P0RM, 1, /* Robust squelch mechanism */ +} + +// Enter L23 +Method (DL23, 0, Serialized) { + Printf(" GPU PORT DL23 START") + + L23E = 1 + Sleep (16) + Local0 = 0 + While (L23E) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + + P0RM = 1 + P0AP = 3 + + Printf(" GPU PORT DL23 FINISH") +} + +// Exit L23 +Method (L23D, 0, Serialized) { + Printf(" GPU PORT L23D START") + + L23R = 1 + Sleep (16) + Local0 = 0 + While (L23R) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + + P0RM = 0 + P0AP = 0 + + Printf(" GPU PORT L23D FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PORT PWRR._ON") + + ^^DEV0._ON() + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PORT PWRR._OFF") + + ^^DEV0._OFF() + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) + +#include "common/gpu.asl" diff --git a/src/drivers/gfx/nvidia/acpi/common/dsm.asl b/src/drivers/gfx/nvidia/acpi/common/dsm.asl new file mode 100644 index 00000000000..ad440b58b74 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/dsm.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define NV_ERROR_SUCCESS 0x0 +#define NV_ERROR_UNSPECIFIED 0x80000001 +#define NV_ERROR_UNSUPPORTED 0x80000002 + +#include "gps.asl" +#include "nvjt.asl" + +Method (_DSM, 4, Serialized) { + Printf("GPU _DSM") + If (Arg0 == ToUUID (JT_DSM_GUID)) { + If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) { + Return (NVJT(Arg2, Arg3)) + } Else { + Printf(" Unsupported JT revision: %o", SFST(Arg1)) + Return (NV_ERROR_UNSUPPORTED) + } + } ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) { + If (ToInteger(Arg1) == GPS_REVISION_ID) { + Return (GPS(Arg2, Arg3)) + } Else { + Printf(" Unsupported GPS revision: %o", SFST(Arg1)) + Return (NV_ERROR_UNSUPPORTED) + } + } Else { + Printf(" Unsupported GUID: %o", IDST(Arg0)) + Return (NV_ERROR_UNSPECIFIED) + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/gps.asl b/src/drivers/gfx/nvidia/acpi/common/gps.asl new file mode 100644 index 00000000000..7d69b194066 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/gps.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81" +#define GPS_REVISION_ID 0x00000200 +#define GPS_FUNC_SUPPORT 0x00000000 +#define GPS_FUNC_PSHARESTATUS 0x00000020 +#define GPS_FUNC_PSHAREPARAMS 0x0000002A + +Method(GPS, 2, Serialized) { + Printf(" GPU GPS") + Switch(ToInteger(Arg0)) { + Case(GPS_FUNC_SUPPORT) { + Printf(" Supported Functions") + Return(ITOB( + (1 << GPS_FUNC_SUPPORT) | + (1 << GPS_FUNC_PSHARESTATUS) | + (1 << GPS_FUNC_PSHAREPARAMS) + )) + } + Case(GPS_FUNC_PSHARESTATUS) { + Printf(" Power Share Status") + Return(ITOB(0)) + } + Case(GPS_FUNC_PSHAREPARAMS) { + Printf(" Power Share Parameters") + + CreateField(Arg1, 0, 4, QTYP) // Query type + + Name(GPSP, Buffer(36) { 0x00 }) + CreateDWordField(GPSP, 0, RSTS) // Response status + CreateDWordField(GPSP, 4, VERS) // Version + + // Set query type of response + RSTS = QTYP + // Set version of response + VERS = 0x00010000 + + Switch(ToInteger(QTYP)) { + Case(0) { + Printf(" Request Current Information") + // No required information + Return(GPSP) + } + Case(1) { + Printf(" Request Supported Fields") + // Support GPU temperature field + RSTS |= (1 << 8) + Return(GPSP) + } + Case(2) { + Printf(" Request Current Limits") + // No required limits + Return(GPSP) + } + Default { + Printf(" Unknown Query: %o", SFST(QTYP)) + Return(NV_ERROR_UNSUPPORTED) + } + } + } + Default { + Printf(" Unsupported function: %o", SFST(Arg0)) + Return(NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/gpu.asl b/src/drivers/gfx/nvidia/acpi/common/gpu.asl new file mode 100644 index 00000000000..49e5c47285b --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/gpu.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (DEV0) { + Name(_ADR, 0x00000000) + + #include "utility.asl" + #include "dsm.asl" + #include "power.asl" +} + +#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST) +Scope (\_SB) { + Device(NPCF) { + #include "utility.asl" + #include "nvpcf.asl" + } +} +#endif diff --git a/src/drivers/gfx/nvidia/acpi/common/nvjt.asl b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl new file mode 100644 index 00000000000..31eaed275e8 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34" +#define JT_REVISION_ID_MIN 0x00000100 +#define JT_REVISION_ID_MAX 0x00000200 +#define JT_FUNC_SUPPORT 0x00000000 +#define JT_FUNC_CAPS 0x00000001 +#define JT_FUNC_POWERCONTROL 0x00000003 + +//TODO: SMI traps and EGIN/XCLM +#define JT_GPC_GSS 0 // Get current GPU GCx sleep status +#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh +#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh +#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh +#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update + +#define JT_DFGC_NONE 0 // Handle request immediately +#define JT_DFGC_DEFER 1 // Defer GPC and GPCX +//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests + +// Deferred GC6 enter/exit until D3-cold (saved DFGC) +Name(DFEN, 0) + +// Deferred GC6 enter control (saved GPC) +Name(DFCI, 0) + +// Deferred GC6 exit control (saved GPCX) +Name(DFCO, 0) + +Method (NVJT, 2, Serialized) { + Printf(" GPU NVJT") + Switch (ToInteger(Arg0)) { + Case (JT_FUNC_SUPPORT) { + Printf(" Supported Functions") + Return(ITOB( + (1 << JT_FUNC_SUPPORT) | + (1 << JT_FUNC_CAPS) | + (1 << JT_FUNC_POWERCONTROL) + )) + } + Case (JT_FUNC_CAPS) { + Printf(" Capabilities") + Return(ITOB( + (1 << 0) | // G-SYNC NSVR power-saving features are enabled + (1 << 1) | // NVSR disabled + (2 << 3) | // Panel power and backlight are on the suspend rail + (0 << 5) | // self-refresh controller remains powered while panel is powered + (0 << 6) | // FB is not on the suspend rail but is powered on in GC6 + (0 << 8) | // Combined power rail for all GPUs + (0 << 10) | // External SPI ROM + (1 << 11) | // No SMI handler for kernel panic exit while in GC6 + (0 << 12) | // Supports notify on GC6 state done + (1 << 13) | // Support deferred GC6 + (1 << 14) | // Support fine-grained root port control + (2 << 15) | // GC6 version is GC6-R + (0 << 17) | // GC6 exit ISR is not supported + (0 << 18) | // GC6 self wakeup not supported + (JT_REVISION_ID_MAX << 20) // Highest revision supported + )) + } + Case (JT_FUNC_POWERCONTROL) { + Printf(" Power Control: %o", SFST(Arg1)) + + CreateField (Arg1, 0, 3, GPC) // GPU power control + CreateField (Arg1, 4, 1, PPC) // Panel power control + CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold + CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control + + // Save deferred GC6 request + If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) { + DFEN = DFGC + DFCI = GPC + DFCO = GPCX + } + + // Buffer to cache current state + Name (JTBF, Buffer (4) { 0, 0, 0, 0 }) + CreateField (JTBF, 0, 3, CGCS) // Current GC state + CreateField (JTBF, 3, 1, CGPS) // Current GPU power status + CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on) + + // If doing deferred GC6 request, return now + If (ToInteger(DFGC) != 0) { + CGCS = 1 + CGPS = 1 + Return (JTBF) + } + + // Apply requested state + Switch (ToInteger(GPC)) { + Case (JT_GPC_GSS) { + Printf(" Get current GPU GCx sleep status") + //TODO: include transitions! + If (GTXS(DGPU_RST_N)) { + // GPU powered on + CGCS = 1 + CGPS = 1 + } ElseIf (GTXS(DGPU_PWR_EN)) { + // GPU powered off, GC6 + CGCS = 3 + CGPS = 0 + } Else { + // GPU powered off, D3 cold + CGCS = 2 + CGPS = 0 + } + } + Case (JT_GPC_EGNS) { + Printf(" Enter GC6 without self-refresh") + GC6I() + CPSS = 1 + } + Case (JT_GPC_EGIS) { + Printf(" Enter GC6 with self-refresh") + GC6I() + If (ToInteger(PPC) == 0) { + CPSS = 0 + } + } + Case (JT_GPC_XGXS) { + Printf(" Exit GC6 and stop self-refresh") + GC6O() + + CGCS = 1 + CGPS = 1 + If (ToInteger(PPC) != 0) { + CPSS = 0 + } + } + Case (JT_GPC_XGIS) { + Printf(" Exit GC6 for self-refresh update") + GC6O() + + CGCS = 1 + CGPS = 1 + If (ToInteger(PPC) != 0) { + CPSS = 0 + } + } + Default { + Printf(" Unsupported GPU power control: %o", SFST(GPC)) + } + } + + Return (JTBF) + } + Default { + Printf(" Unsupported function: %o", SFST(Arg0)) + Return (NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl b/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl new file mode 100644 index 00000000000..6ecbd05191b --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66" +#define NVPCF_REVISION_ID 0x200 + +#define NVPCF_ERROR_SUCCESS 0 +#define NVPCF_ERROR_GENERIC 0x80000001 +#define NVPCF_ERROR_UNSUPPORTED 0x80000002 + +#define NVPCF_FUNC_GET_SUPPORTED 0 // Required +#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 1 // Required +#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 2 // Required +#define NVPCF_FUNC_GET_WM2_TBAND_TABLES 3 +#define NVPCF_FUNC_GET_WM2_SL_MAP_TABLES 4 +#define NVPCF_FUNC_GET_WM2_DYNAMIC_PARAMS 5 +#define NVPCF_FUNC_CPU_CONTROL 6 +#define NVPCF_FUNC_GPU_INFO 7 +#define NVPCF_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE 8 +#define NVPCF_FUNC_CPU_TDP_CONTROL 9 +#define NVPCF_FUNC_GET_DC_TPP_LIMIT_PREFERENCE 10 +#define NVPCF_FUNC_GET_THERMAL_ZONE_STATUS 11 + +Name (DBAC, 0) // Disable GPU Boost on AC +Name (DBDC, 0) // Disable GPU Boost on DC (XXX: Proprietary default disables on DC) + +Name (_HID, "NVDA0820") +Name (_UID, "NPCF") + +Method (_STA, 0, NotSerialized) +{ + Return (0x0F) // ACPI_STATUS_DEVICE_ALL_ON +} + +Method (_DSM, 4, Serialized) +{ + If (Arg0 == ToUUID (NVPCF_DSM_GUID)) { + Printf ("NVPCF DSM") + If (ToInteger (Arg1) == NVPCF_REVISION_ID) { + Return (NPCF (Arg2, Arg3)) + } Else { + Printf (" NVPCF: Unsupported revision: %o", Arg1) + } + } + Else { + Printf (" NVPCF: Unsupported GUID: %o", IDST (Arg0)) + } + + Return (NVPCF_ERROR_GENERIC) +} + +Method (NPCF, 2, Serialized) +{ + Switch (ToInteger (Arg0)) { + Case (NVPCF_FUNC_GET_SUPPORTED) { + Printf (" NVPCF[0]: GET_SUPPORTED") + Return (ITOB ( + (1 << NVPCF_FUNC_GET_SUPPORTED) | + (1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) | + (1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) + )) + } + Case (NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) { + Printf (" NVPCF[1]: GET_STATIC_CONFIG_TABLE") + Return (Buffer (14) { + // System Device Table Header (v2.0) + 0x20, 0x03, 0x01, + // System Device Table Entries + // [3:0] CPU Type (0=Intel, 1=AMD) + // [7:4] GPU Type (0=Nvidia) + 0x00, + // System Controller Table Header (v2.3) + 0x23, 0x04, 0x05, 0x01, + // System Controller Table Controller Entry + // Controller Flags + // [3:0] Controller Class Type + // 0=Disabled + // 1=Dynamic Boost Controller + // 2=Configurable TGP-only Controller + // [7:4] Reserved + 0x01, + // Controller Params + // [0:0] DC support (0=Not supported, 1=Supported) + // [31:1] Reserved + 0x01, 0x00, 0x00, 0x00, + // Single byte checksum value + 0xAD + }) + } + Case (NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) { + Printf (" NVPCF[2]: UPDATE_DYNAMIC_PARAMS") + + // Dynamic Params Common Status, Input + // 0=Get Controller Params + // 1=Set Controller Status + CreateField (Arg1, 0x28, 2, ICMD) + + // XXX: All input params unused? + // Controller Entry, Input + //CreateByteField (Arg1, 0x15, IIDX) // Controller index + //CreateField (Arg1, 0xB0, 0x01, PWCS) // Power control capability (0=Disabled, 1=Enabled) + //CreateField (Arg1, 0xB1, 0x01, PWTS) // Power transfer status (0=Disabled, 1=Enabled) + //CreateField (Arg1, 0xB2, 0x01, CGPS) // CTGP status (0=Disabled, 1=Enabled) + + Name (PBD2, Buffer(49) { + // Dynamic Params Table Header + 0x23, // Version 2.3 + 0x05, // Table header size in bytes + 0x10, // Size of Common Status in bytes + 0x1C, // Size of Controller Entry in bytes + 0x01, // Number of Controller Entries + }) + + // Dynamic Params Common Status, Output + // Baseline (configurable) TGP in AC for the intended TPP + // limit, expressed as a signed offset relative to the + // static TGP rates, AC, in 1/8-watt units. + CreateWordField (PBD2, 0x05, TGPA) + + // Controller Entry, Output - Dynamic Boost Controller + CreateByteField (PBD2, 0x15, OIDX) // Controller index + // Disable controller on AC/DC + // [0:0] Disable controller on AC (0=Enable, 1=Disable) + // [1:1] Disable controller on DC (0=Enable, 1=Disable) + CreateByteField (PBD2, 0x16, PC02) + CreateWordField (PBD2, 0x19, TPPA) // TPP target on AC + CreateWordField (PBD2, 0x1D, MAGA) // Max TGP on AC + CreateWordField (PBD2, 0x21, MIGA) // Min TGP on AC + CreateDWordField (PBD2, 0x25, DROP) // DC Rest of system reserved power + CreateDWordField (PBD2, 0x29, LTBC) // Long Timescale Battery Current Limit + CreateDWordField (PBD2, 0x2D, STBC) // Short Timescale Battery Current Limit + + Switch (ToInteger (ICMD)) { + Case (0) { + Printf (" Get Controller Params") + + TGPA = 0 + OIDX = 0 + PC02 = DBAC | (DBDC << 1) + TPPA = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3) + MAGA = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3) + MIGA = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3) + + // TODO: Handle v2.3+ fields + + Printf ("PBD2: %o", SFST(PBD2)) + Return (PBD2) + } + Case (1) { + Printf (" Set Controller Status") + + // XXX: Match proprietary firmware behavior, + // which just explicitly sets fields to zero. + TGPA = 0 + OIDX = 0 + PC02 = 0 + TPPA = 0 + MAGA = 0 + MIGA = 0 + + Printf ("PBD2: %o", SFST(PBD2)) + Return (PBD2) + } + Default { + Printf (" Unknown Input Command: %o", SFST(ICMD)) + Return (NV_ERROR_UNSUPPORTED) + } + } + } + Case (NVPCF_FUNC_GET_WM2_TBAND_TABLES) { + Printf (" NVPCF[3]: GET_WM2_TBAND_TABLES") + } + Case (NVPCF_FUNC_GET_WM2_SL_MAP_TABLES) { + Printf (" NVPCF[4]: GET_WM2_SL_MAP_TABLES") + } + Case (NVPCF_FUNC_GET_WM2_DYNAMIC_PARAMS) { + Printf (" NVPCF[5]: GET_WM2_DYNAMIC_PARAMS") + } + Case (NVPCF_FUNC_CPU_CONTROL) { + Printf (" NVPCF[6]: CPU_CONTROL") + } + Case (NVPCF_FUNC_GPU_INFO) { + Printf (" NVPCF[7]: GPU_INFO") + } + Case (NVPCF_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE) { + Printf (" NVPCF[8]: GET_DC_SYSTEM_POWER_LIMITS_TABLE") + } + Case (NVPCF_FUNC_CPU_TDP_CONTROL) { + Printf (" NVPCF[9]: CPU_TDP_CONTROL") + } + Case (NVPCF_FUNC_GET_DC_TPP_LIMIT_PREFERENCE) { + Printf (" NVPCF[10]: GET_DC_TPP_LIMIT_PREFERENCE") + } + Case (NVPCF_FUNC_GET_THERMAL_ZONE_STATUS) { + Printf (" NVPCF[11]: GET_THERMAL_ZONE_STATUS") + } + Default { + Printf (" NVPCF: Unknown function: %o", Arg0) + } + } + + // XXX: DG says unsupported functions should return a + // buffer, but even the example immediately following + // this statement returns a DWORD, and this is what + // proprietary firmware also does. + Return (NVPCF_ERROR_UNSUPPORTED) +} diff --git a/src/drivers/gfx/nvidia/acpi/common/power.asl b/src/drivers/gfx/nvidia/acpi/common/power.asl new file mode 100644 index 00000000000..1425329e0ea --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/power.asl @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +//TODO: evaluate sleeps + +OperationRegion (PCIC, PCI_Config, 0x00, 0xFF) +Field (PCIC, DwordAcc, NoLock, Preserve) { + NVID, 16, + NDID, 16, + Offset (0x40), + SSID, 32, // Subsystem vendor and product ID +} + +// Enter GC6 +Method(GC6I, 0, Serialized) { + Printf(" GPU GC6I START") + + // Enter L23 + ^^DL23() + Sleep(5) + + // Put GPU into reset + Printf(" Put GPU into reset") + CTXS(DGPU_RST_N) + Sleep(5) + + Printf(" GPU GC6I FINISH") +} + +// Exit GC6 +Method(GC6O, 0, Serialized) { + Printf(" GPU GC6O START") + + // Bring GPU out of reset + Printf(" Bring GPU out of reset") + STXS(DGPU_RST_N) + Sleep(10) + + // Exit L23 + ^^L23D() + + // Wait for GPU to appear on the bus + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) { + If (Local0 == 0) { + Break + } + + Stall (100) + Local0-- + } + + Printf(" GPU GC6O FINISH") +} + +Method (_ON, 0, Serialized) { + Printf(" GPU _ON START") + + If (DFEN == JT_DFGC_DEFER) { + Switch (ToInteger(DFCO)) { + Case (JT_GPC_XGXS) { + Printf(" Exit GC6 and stop self-refresh") + GC6O() + } + Default { + Printf(" Unsupported DFCO: %o", SFST(DFCO)) + } + } + DFEN = JT_DFGC_NONE + } Else { + Printf(" Standard RTD3 power on") + STXS(DGPU_PWR_EN) + + // Wait for rails to stabilize +#if DGPU_PWRGD + Local0 = 500 + While (GRXS(DGPU_PWRGD) != 1) { + If (Local0 == 0) { + Break + } + + Stall(100) + Local0-- + } +#else + Sleep(50) +#endif + + GC6O() + } + + Printf(" GPU _ON FINISH") +} + +Method (_OFF, 0, Serialized) { + Printf(" GPU _OFF START") + + If (DFEN == JT_DFGC_DEFER) { + Switch (ToInteger(DFCI)) { + Case (JT_GPC_EGNS) { + Printf(" Enter GC6 without self-refresh") + GC6I() + } + Case (JT_GPC_EGIS) { + Printf(" Enter GC6 with self-refresh") + GC6I() + } + Default { + Printf(" Unsupported DFCI: %o", SFST(DFCI)) + } + } + DFEN = JT_DFGC_NONE + } Else { + Printf(" Standard RTD3 power off") + GC6I() + CTXS(DGPU_PWR_EN) + Sleep(5) + } + + Printf(" GPU _OFF FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PWRR._ON") + + // Restore SSID + ^^SSID = DGPU_SSID + Printf(" Restore SSID: %o", SFST(^^SSID)) + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PWRR._OFF") + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) diff --git a/src/drivers/gfx/nvidia/acpi/common/utility.asl b/src/drivers/gfx/nvidia/acpi/common/utility.asl new file mode 100644 index 00000000000..edf42bd024b --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/utility.asl @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Convert a byte to a hex string, trimming extra parts +Method (BHEX, 1) { + Local0 = ToHexString(Arg0) + Return (Mid(Local0, SizeOf(Local0) - 2, 2)) +} + +// UUID to string +Method (IDST, 1) { + Local0 = "" + Fprintf( + Local0, + "%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o", + BHEX(DerefOf(Arg0[3])), + BHEX(DerefOf(Arg0[2])), + BHEX(DerefOf(Arg0[1])), + BHEX(DerefOf(Arg0[0])), + BHEX(DerefOf(Arg0[5])), + BHEX(DerefOf(Arg0[4])), + BHEX(DerefOf(Arg0[7])), + BHEX(DerefOf(Arg0[6])), + BHEX(DerefOf(Arg0[8])), + BHEX(DerefOf(Arg0[9])), + BHEX(DerefOf(Arg0[10])), + BHEX(DerefOf(Arg0[11])), + BHEX(DerefOf(Arg0[12])), + BHEX(DerefOf(Arg0[13])), + BHEX(DerefOf(Arg0[14])), + BHEX(DerefOf(Arg0[15])) + ) + Return (Local0) +} + +// Safe hex conversion, checks type first +Method (SFST, 1) { + Local0 = ObjectType(Arg0) + If (Local0 == 1 || Local0 == 2 || Local0 == 3) { + Return (ToHexString(Arg0)) + } Else { + Return (Concatenate("Type: ", Arg0)) + } +} + +// Convert from 4-byte buffer to 32-bit integer +Method (BTOI, 1) { + Return( + DerefOf(Arg0[0]) | + (DerefOf(Arg0[1]) << 8) | + (DerefOf(Arg0[2]) << 16) | + (DerefOf(Arg0[3]) << 24) + ) +} + +// Convert from 32-bit integer to 4-byte buffer +Method (ITOB, 1) { + Local0 = Buffer(4) { 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Return (Local0) +} diff --git a/src/drivers/gfx/nvidia/acpi/tigerlake.asl b/src/drivers/gfx/nvidia/acpi/tigerlake.asl new file mode 100644 index 00000000000..a13e46a04f8 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/tigerlake.asl @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */ + +// Port mapped PCI express config space +OperationRegion (PCIC, PCI_Config, 0x00, 0xFF) + +Field (PCIC, AnyAcc, NoLock, Preserve) { + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + + Offset(0x60), /* RSTS - Root Status Register */ + , 16, + PSPX, 1, /* 16, PME Status */ + + Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + + Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */ + SCB0, 1, /* Scratch bit 0 */ + + Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ +} + +Field (PCIC, AnyAcc, NoLock, WriteAsZeros) { + Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +// Enter L23 +Method (DL23, 0, Serialized) { + Printf(" GPU PORT DL23 START") + + L23E = 1 + Sleep (16) + Local0 = 0 + While (L23E) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + SCB0 = 1 + + Printf(" GPU PORT DL23 FINISH") +} + +// Exit L23 +Method (L23D, 0, Serialized) { + Printf(" GPU PORT L23D START") + + If ((SCB0 == 1)) { + L23R = 1 + Local0 = 0 + While (L23R) { + If ((Local0 > 4)) { + Break + } + Sleep (16) + Local0++ + } + + SCB0 = 0 + Local0 = 0 + While ((LASX == 0)) { + If ((Local0 > 8)) { + Break + } + Sleep (16) + Local0++ + } + } + + Printf(" GPU PORT L23D FINISH") +} + +Method (HPME, 0, Serialized) { + Printf(" GPU PORT HPME START") + + If (PMSX == 1) { + Printf(" Notify GPU driver of PME SCI") + Notify(DEV0, 0x2) + Printf(" Clear PME SCI") + PMSX = 1 + Printf(" Consume PME notification") + PSPX = 1 + } + + Printf(" GPU PORT HPME FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PORT PWRR._ON") + + HPME(); + If (PMEX == 1) { + Printf(" Disable power management SCI") + PMEX = 0 + } + + ^^DEV0._ON() + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PORT PWRR._OFF") + + ^^DEV0._OFF() + + If (PMEX == 0) { + Printf(" Enable power management SCI") + PMEX = 1 + HPME() + } + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) + +#include "common/gpu.asl" diff --git a/src/drivers/gfx/nvidia/chip.h b/src/drivers/gfx/nvidia/chip.h new file mode 100644 index 00000000000..b6d9c908ebc --- /dev/null +++ b/src/drivers/gfx/nvidia/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_ +#define _DRIVERS_GFX_NVIDIA_CHIP_H_ + +struct drivers_gfx_nvidia_config { + /* TODO: Set GPIOs in devicetree? */ +}; + +#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */ diff --git a/src/drivers/gfx/nvidia/gpu.h b/src/drivers/gfx/nvidia/gpu.h new file mode 100644 index 00000000000..f9ec690322d --- /dev/null +++ b/src/drivers/gfx/nvidia/gpu.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_ +#define _DRIVERS_GFX_NVIDIA_GPU_H_ + +#include + +struct nvidia_gpu_config { + /* GPIO for GPU_PWR_EN */ + unsigned int power_gpio; + /* GPIO for GPU_PWRGD */ + unsigned int power_good_gpio; + /* GPIO for GPU_RST# */ + unsigned int reset_gpio; + /* Enable or disable GPU power */ + bool enable; +}; + +void nvidia_set_power(const struct nvidia_gpu_config *config); + +#endif /* _DRIVERS_NVIDIA_GPU_H_ */ diff --git a/src/drivers/gfx/nvidia/nvidia.c b/src/drivers/gfx/nvidia/nvidia.c new file mode 100644 index 00000000000..42d5db07f05 --- /dev/null +++ b/src/drivers/gfx/nvidia/nvidia.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "chip.h" +#include +#include +#include +#include + +#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40 + +static void nvidia_read_resources(struct device *dev) +{ + printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev)); + + pci_dev_read_resources(dev); + + // Find all BARs on GPU, mark them above 4g if prefetchable + for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { + struct resource *res = probe_resource(dev, bar); + + if (res) { + if (res->flags & IORESOURCE_PREFETCH) { + printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar); + res->flags |= IORESOURCE_ABOVE_4G; + } else { + printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar); + } + } else { + printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar); + } + } +} + +static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) +{ + pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations nvidia_device_ops_pci = { + .set_subsystem = nvidia_set_subsystem, +}; + +static struct device_operations nvidia_device_ops = { + .read_resources = nvidia_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pci_rom_ssdt, + .init = pci_dev_init, + .ops_pci = &nvidia_device_ops_pci, +}; + +static void nvidia_enable(struct device *dev) +{ + if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI) + return; + + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA) + return; + + dev->ops = &nvidia_device_ops; +} + +struct chip_operations drivers_gfx_nvidia_ops = { + .name = "NVIDIA Optimus Graphics Device", + .enable_dev = nvidia_enable +}; diff --git a/src/drivers/gfx/nvidia/romstage.c b/src/drivers/gfx/nvidia/romstage.c new file mode 100644 index 00000000000..c9cd42fc902 --- /dev/null +++ b/src/drivers/gfx/nvidia/romstage.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "gpu.h" + +void nvidia_set_power(const struct nvidia_gpu_config *config) +{ + if (!config->power_gpio || !config->reset_gpio) { + printk(BIOS_ERR, "%s: GPU_PWR_EN, GPU_RST# must be set\n", __func__); + return; + } + + printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio); + printk(BIOS_DEBUG, "%s: GPU_PWRGD = %d\n", __func__, config->power_good_gpio); + printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio); + + gpio_set(config->reset_gpio, 0); + mdelay(10); + + if (config->enable) { + gpio_set(config->power_gpio, 1); + if (config->power_good_gpio) { + if (wait_ms(50, gpio_get(config->power_good_gpio) == 1)) { + printk(BIOS_INFO, "dGPU powered on\n"); + gpio_set(config->reset_gpio, 1); + } else { + printk(BIOS_ERR, "dGPU failed to power on, turning off\n"); + gpio_set(config->power_gpio, 0); + } + } else { + mdelay(50); + gpio_set(config->reset_gpio, 1); + } + } else { + gpio_set(config->power_gpio, 0); + } + + mdelay(10); +} diff --git a/src/drivers/i2c/ck505/chip.h b/src/drivers/i2c/ck505/chip.h index 745e76bf71a..8ecd0ec38ef 100644 --- a/src/drivers/i2c/ck505/chip.h +++ b/src/drivers/i2c/ck505/chip.h @@ -3,6 +3,9 @@ #ifndef DRIVERS_CK505_CHIP_H #define DRIVERS_CK505_CHIP_H +void mb_pre_ck505_init(void); +void mb_post_ck505_init(void); + struct drivers_i2c_ck505_config { const int nregs; const u8 regs[32]; diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index db660fe67ff..0a57df82d5a 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -8,6 +8,16 @@ #define SMBUS_BLOCK_SIZE 32 +__weak void mb_pre_ck505_init(void) +{ + // do nothing +} + +__weak void mb_post_ck505_init(void) +{ + // do nothing +} + static void ck505_init(struct device *dev) { struct drivers_i2c_ck505_config *config; @@ -18,6 +28,8 @@ static void ck505_init(struct device *dev) if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C) return; + mb_pre_ck505_init(); + config = dev->chip_info; dev_nregs = smbus_block_read(dev, 0, sizeof(block), block); @@ -41,6 +53,8 @@ static void ck505_init(struct device *dev) if (smbus_block_write(dev, 0, dev_nregs, block) < 0) printk(BIOS_ERR, "Failed writing ck505 configuration!\n"); + + mb_post_ck505_init(); } static struct device_operations ck505_operations = { diff --git a/src/drivers/i2c/rv3028c7/chip.h b/src/drivers/i2c/rv3028c7/chip.h index 0ed86ffeff3..02654b29da4 100644 --- a/src/drivers/i2c/rv3028c7/chip.h +++ b/src/drivers/i2c/rv3028c7/chip.h @@ -40,9 +40,10 @@ struct drivers_i2c_rv3028c7_config { unsigned char user_day; /* User day to set */ unsigned char user_month; /* User month to set */ unsigned char user_year; /* User year to set (2-digit) */ - unsigned char set_user_date; /* Use user date from devicetree */ + bool set_user_date; /* Use user date from devicetree */ enum sw_mode bckup_sw_mode; /* Mode for switching between VDD and VBACKUP */ enum charge_mode cap_charge; /* Mode for capacitor charging */ + bool sync_to_cmos_rtc; /* Sync the RTC date & time to the CMOS RTC */ }; #endif /* __DRIVERS_I2C_RV3028C7_CHIP_H__ */ diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.c b/src/drivers/i2c/rv3028c7/rv3028c7.c index a8ac33b5a2a..e8bcd7e9e40 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.c +++ b/src/drivers/i2c/rv3028c7/rv3028c7.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -63,59 +64,104 @@ static enum cb_err rtc_eep_start_update(struct device *dev) return CB_SUCCESS; } -static void rtc_set_time_date(struct device *dev) +static int rv3028c7_rtc_set(struct device *dev, struct rtc_time *time) { - struct drivers_i2c_rv3028c7_config *config = dev->chip_info; - uint8_t buf[7]; + const uint8_t buf[7] = { + bin2bcd(time->sec), + bin2bcd(time->min), + bin2bcd(time->hour), + bin2bcd(time->wday), + bin2bcd(time->mday), + bin2bcd(time->mon), + bin2bcd(time->year % 100) + }; - /* The buffer contains the seconds through years of the new time and date. - Whenever a new date is set, the time is set to 00:00:00. */ - buf[0] = 0; /* Entry for seconds. */ - buf[1] = 0; /* Entry for minutes. */ - buf[2] = 0; /* Entry for hours. */ - if (config->set_user_date) { - buf[3] = config->user_weekday; - buf[4] = bin2bcd(config->user_day); - buf[5] = bin2bcd(config->user_month); - buf[6] = bin2bcd(config->user_year); - printk(BIOS_DEBUG, "%s: Set to user date\n", dev->chip_ops->name); - } else { - buf[3] = coreboot_build_date.weekday; - buf[4] = coreboot_build_date.day; - buf[5] = coreboot_build_date.month; - buf[6] = coreboot_build_date.year; - printk(BIOS_DEBUG, "%s: Set to coreboot build date\n", dev->chip_ops->name); - } for (size_t i = 0; i < ARRAY_SIZE(buf); i++) { if (i2c_dev_writeb_at(dev, i, buf[i]) < 0) { printk(BIOS_ERR, "%s: Failed to write register 0x%02zx!\n", dev->chip_ops->name, i); - return; + return 1; } } + return 0; } -static void rtc_final(struct device *dev) +static int rv3028c7_rtc_get(struct device *dev, struct rtc_time *time) { - uint8_t buf[7]; - int val; - /* Read back current RTC date and time byte by byte */ - printk(BIOS_DEBUG, "%s: Reading current date and time...\n", dev->chip_ops->name); + int buf[7]; for (size_t i = 0; i < ARRAY_SIZE(buf); i++) { - val = i2c_dev_readb_at(dev, i); - if (val < 0) { + buf[i] = i2c_dev_readb_at(dev, i); + if (buf[i] < 0) { printk(BIOS_ERR, "%s: Failed to read register 0x%02zx!\n", - dev->chip_ops->name, i); - return; + dev->chip_ops->name, i); + return 1; } - buf[i] = (uint8_t)val; + } + /* Convert the BCD register values into decimal date and time values. */ + time->sec = bcd2bin((uint8_t)buf[SECOND_REG]); + time->min = bcd2bin((uint8_t)buf[MINUTE_REG]); + time->hour = bcd2bin((uint8_t)buf[HOUR_REG]); + time->wday = bcd2bin((uint8_t)buf[WDAY_REG]); + time->mday = bcd2bin((uint8_t)buf[MDAY_REG]); + time->mon = bcd2bin((uint8_t)buf[MONTH_REG]); + /* The RV3028-C7 does not store the century but only years 0..99. + Use the coreboot build date to get a meaningful century value. */ + time->year = bcd2bin(buf[YEAR_REG]) + (100 * bcd2bin(coreboot_build_date.century)); + return 0; +} + +static void rtc_set_time_date(struct device *dev) +{ + struct drivers_i2c_rv3028c7_config *config = dev->chip_info; + struct rtc_time time; + + /* Whenever a new date is set, the time is set to 00:00:00. */ + time.sec = 0; + time.min = 0; + time.hour = 0; + if (config->set_user_date) { + time.wday = config->user_weekday; + time.mday = bin2bcd(config->user_day); + time.mon = bin2bcd(config->user_month); + time.year = bin2bcd(config->user_year); + printk(BIOS_DEBUG, "%s: Use user date.\n", dev->chip_ops->name); + } else { + time.wday = coreboot_build_date.weekday; + time.mday = coreboot_build_date.day; + time.mon = coreboot_build_date.month; + time.year = coreboot_build_date.year; + printk(BIOS_DEBUG, "%s: Use coreboot build date.\n", dev->chip_ops->name); + } + if (rv3028c7_rtc_set(dev, &time) != 0) { + printk(BIOS_ERR, "%s: Not able to set date and time!\n", dev->chip_ops->name); + } else { + printk(BIOS_NOTICE, "%s: Date and time set.\n", dev->chip_ops->name); + } +} + +static void rtc_final(struct device *dev) +{ + struct drivers_i2c_rv3028c7_config *config = dev->chip_info; + struct rtc_time time; + + /* Read back current RTC date and time. */ + printk(BIOS_SPEW, "%s: Read current date and time.\n", dev->chip_ops->name); + if (rv3028c7_rtc_get(dev, &time) != 0) { + printk(BIOS_ERR, "%s: Not able to read current date and time!\n", + dev->chip_ops->name); + return; + } + + /* Synchronize the x86 CMOS RTC with the external RTC if enabled. */ + if (config->sync_to_cmos_rtc) { + printk(BIOS_INFO, "%s: Synchronize to CMOS RTC.\n", dev->chip_ops->name); + rtc_set(&time); } - printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n", - dev->chip_ops->name, bcd2bin(buf[5]), bcd2bin(buf[4]), - bcd2bin(buf[6]), bcd2bin(buf[2]), bcd2bin(buf[1]), - bcd2bin(buf[0])); + printk(BIOS_INFO, "%s: Current date is %02u-%02u-%02u %02u:%02u:%02u\n", + dev->chip_ops->name, time.year, time.mon, time.mday, time.hour, + time.min, time.sec); /* Make sure the EEPROM automatic refresh is enabled. */ if (rtc_eep_auto_refresh(dev, EEP_REFRESH_EN) != CB_SUCCESS) { diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.h b/src/drivers/i2c/rv3028c7/rv3028c7.h index b1f9971bbeb..39ea4d65a0f 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.h +++ b/src/drivers/i2c/rv3028c7/rv3028c7.h @@ -11,8 +11,8 @@ #define SECOND_REG 0x00 #define MINUTE_REG 0x01 #define HOUR_REG 0x02 -#define WEEK_REG 0x03 -#define DAY_REG 0x04 +#define WDAY_REG 0x03 +#define MDAY_REG 0x04 #define MONTH_REG 0x05 #define YEAR_REG 0x06 #define STATUS_REG 0x0e diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index 2b184266cd6..99e23e7f56f 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -12,21 +12,21 @@ struct drivers_i2c_rx6110sa_config { unsigned char user_day; /* User day to set */ unsigned char user_month; /* User month to set */ unsigned char user_year; /* User year to set */ - unsigned char set_user_date; /* Use user date from device tree */ + bool set_user_date; /* Use user date from device tree */ unsigned char cof_selection; /* Set up "clock out" frequency */ unsigned char timer_clk; /* Set up timer clock */ unsigned char timer_irq_en; /* Interrupt generation on timer */ unsigned short timer_preset; /* Preset value for the timer */ unsigned char timer_mode; /* Set the timer mode of operation */ - unsigned char timer_en; /* Enable timer operation */ + bool timer_en; /* Enable timer operation */ unsigned char irq_output_pin; /* 0: IRQ2 pin used, 1: IRQ1 pin used */ unsigned char fout_output_pin; /* 0: IRQ2, 1: IRQ1, 2: DO/FOUT */ - unsigned char enable_1hz_out; /* If set enables 1 Hz output on IRQ1 */ + bool enable_1hz_out; /* If set enables 1 Hz output on IRQ1 */ unsigned char pmon_sampling; /* Select power monitor sampling time */ /* The following two bits set the power monitor and backup mode. */ - unsigned char bks_on; - unsigned char bks_off; - unsigned char iocut_en; /* Disable backup of I/O circuit. */ + bool bks_on; + bool bks_off; + bool iocut_en; /* Disable backup of I/O circuit. */ }; #endif /* __DRIVERS_I2C_RX6110SA_CHIP_H__ */ diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index ce5051d755a..9242c1765d0 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -56,9 +56,9 @@ static void rx6110sa_final(struct device *dev) month = rx6110sa_read(dev, MONTH_REG); day = rx6110sa_read(dev, DAY_REG); - printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n", - dev->chip_ops->name, bcd2bin(month), bcd2bin(day), - bcd2bin(year), bcd2bin(hour), bcd2bin(minute), bcd2bin(second)); + printk(BIOS_INFO, "%s: Current date %02u-%02u-%02u %02u:%02u:%02u\n", + dev->chip_ops->name, bcd2bin(year), bcd2bin(month), + bcd2bin(day), bcd2bin(hour), bcd2bin(minute), bcd2bin(second)); } static void rx6110sa_init(struct device *dev) diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c index 59d7847bd2d..f4837a47696 100644 --- a/src/drivers/intel/dtbt/dtbt.c +++ b/src/drivers/intel/dtbt/dtbt.c @@ -221,13 +221,22 @@ static void dtbt_enable(struct device *dev) } } +static void dtbt_scan_bridge(struct device *dev) +{ + if (CONFIG(PCIEXP_HOTPLUG) && dev->upstream && dev->upstream->dev && + dev->upstream->dev->ops == &dtbt_device_ops) + pciexp_hotplug_scan_bridge(dev); + else + pciexp_scan_bridge(dev); +} + static struct device_operations dtbt_device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .acpi_fill_ssdt = dtbt_fill_ssdt, .acpi_name = dtbt_acpi_name, - .scan_bus = pciexp_scan_bridge, + .scan_bus = dtbt_scan_bridge, .reset_bus = pci_bus_reset, .enable = dtbt_enable }; @@ -244,6 +253,8 @@ static const unsigned short pci_device_ids[] = { TR_DD_BRG, MR_2C_BRG, MR_4C_BRG, + BR_80G_BRG, + BR_40G_BRG, 0 }; diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h index 40c1938ceb4..3d2823536d4 100644 --- a/src/drivers/intel/dtbt/dtbt.h +++ b/src/drivers/intel/dtbt/dtbt.h @@ -38,6 +38,14 @@ #define MR_4C_NHI 0x1137 #define MR_4C_USB 0x1138 +/* Barlow Ridge device IDs */ +#define BR_80G_BRG 0x5780 +#define BR_80G_NHI 0x5781 +#define BR_80G_USB 0x5782 +#define BR_40G_BRG 0x5783 +#define BR_40G_NHI 0x5784 +#define BR_40G_USB 0x5785 + /* Security Levels */ #define SEC_LEVEL_NONE 0 #define SEC_LEVEL_USER 1 @@ -52,6 +60,7 @@ #define PCIE2TBT_OS_UP 6 #define PCIE2TBT_SET_SECURITY_LEVEL 8 #define PCIE2TBT_GET_SECURITY_LEVEL 9 +#define PCIE2TBT_MPS 17 #define PCIE2TBT_BOOT_ON 24 #define PCIE2TBT_USB_ON 25 #define PCIE2TBT_GET_ENUMERATION_METHOD 26 @@ -60,6 +69,7 @@ #define PCIE2TBT_SX_START 29 #define PCIE2TBT_ACL_BOOT 30 #define PCIE2TBT_CONNECT_TOPOLOGY 31 +#define PCIE2TBT_GO2SLEEP 36 #define TBT2PCIE 0x548 #define TBT2PCIE_DONE BIT(0) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3309f99907d..0333203eca6 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -260,10 +260,14 @@ config FSP_TEMP_RAM_SIZE config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS bool help - This is selected by SoC or mainboard to supply their own - concept of a version for the memory settings respectively. - This allows deployed systems to bump their version number - with the same FSP which will trigger a retrain of the memory. + Select this when a SoC or mainboard needs to mix its own + memory-settings version into the MRC cache version. + + FSP-M UPDs can affect memory training without changing the FSP + binary version, and some platforms use the MRC version rather than + the FSP-M image revision as the cache key. Mixing in the SoC and + mainboard versions lets deployed systems invalidate stale training + data when those settings change while keeping the same FSP binary. config FSP_COMPRESS_FSP_S_LZMA bool @@ -279,6 +283,10 @@ config FSP_COMPRESS_FSP_M_LZ4 bool depends on !FSP_M_XIP +config FSP_COMPRESS_FSP_M_ZSTD + bool + depends on !FSP_M_XIP + config FSP_ALIGNMENT_FSP_S int help diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk index a7dd80a1ed6..e967a003161 100644 --- a/src/drivers/intel/fsp2_0/Makefile.mk +++ b/src/drivers/intel/fsp2_0/Makefile.mk @@ -83,6 +83,9 @@ $(FSP_M_CBFS_2)-compression := LZMA else ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) $(FSP_M_CBFS)-compression := LZ4 $(FSP_M_CBFS_2)-compression := LZ4 +else ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_ZSTD),y) +$(FSP_M_CBFS)-compression := ZSTD +$(FSP_M_CBFS_2)-compression := ZSTD endif ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),) $(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f3cb529caaf..ad877fd90d9 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -227,18 +227,14 @@ uint8_t fsp_memory_soc_version(void) } /* - * Allow SoC and/or mainboard to bump the revision of the FSP setting - * number. The FSP spec uses the low 8 bits as the build number. Take over - * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way - * a tweak in the settings will bump the version used to track the cached - * setting which triggers retraining when the FSP version hasn't changed, but - * the SoC or mainboard settings have. + * Allow SoC and/or mainboard to bump the revision of the memory setting + * number. Take over bits 3:0 for the SoC setting and bits 7:4 for the + * mainboard. That way a tweak in the settings will bump the version used to + * track the cached setting, which triggers retraining when the FSP or MRC + * version has not changed, but the SoC or mainboard settings have. */ -static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) +static uint32_t fsp_memory_settings_version(uint32_t ver) { - /* Use the full FSP version by default. */ - uint32_t ver = hdr->image_revision; - if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) return ver; @@ -374,7 +370,8 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) if (CONFIG(MRC_CACHE_USING_MRC_VERSION)) version = fsp_mrc_version(hdr); else - version = fsp_memory_settings_version(hdr); + version = hdr->image_revision; + version = fsp_memory_settings_version(version); upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 9e7e2a41469..7a1a1a5c663 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -1,11 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -config INTEL_DDI - bool - default n - help - helper functions for intel DDI operations - config INTEL_EDID bool default n diff --git a/src/drivers/intel/gma/Makefile.mk b/src/drivers/intel/gma/Makefile.mk index 269ef5aeb08..7311ac27b24 100644 --- a/src/drivers/intel/gma/Makefile.mk +++ b/src/drivers/intel/gma/Makefile.mk @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 5c341046f55..2b4f3a8eb84 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -64,21 +64,6 @@ enum plane { PLANE_C, }; -/* debug enums. These are for printks that, due to their place in the - * middle of graphics device IO, might change timing. Use with care - * or not at all. - */ -enum { - vio = 2, /* dump every IO */ - vspin = 4, /* print # of times we spun on a register value */ -}; - -/* The mainboard must provide these functions. */ -unsigned long io_i915_read32(unsigned long addr); -void io_i915_write32(unsigned long val, unsigned long addr); - -void intel_prepare_ddi(void); - int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 3d6cd45276e..0282122c303 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4006,6 +4006,7 @@ #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) #define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_DATA1 0x13812c #define GEN6_GT_CORE_STATUS 0x138060 #define GEN6_CORE_CPD_STATE_MASK (7<<4) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c deleted file mode 100644 index 6c6d13e7186..00000000000 --- a/src/drivers/intel/gma/intel_ddi.c +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: MIT */ - -#include -#include -#include - -/* HDMI/DVI modes ignore everything but the last 2 items. So we share - * them for both DP and FDI transports, allowing those ports to - * automatically adapt to HDMI connections as well. - */ -static u32 hsw_ddi_translations_dp[] = { - 0x00FFFFFF, 0x0006000E, /* DP parameters */ - 0x00D75FFF, 0x0005000A, - 0x00C30FFF, 0x00040006, - 0x80AAAFFF, 0x000B0000, - 0x00FFFFFF, 0x0005000A, - 0x00D75FFF, 0x000C0004, - 0x80C30FFF, 0x000B0000, - 0x00FFFFFF, 0x00040006, - 0x80D75FFF, 0x000B0000, - 0x00FFFFFF, 0x00040006 /* HDMI parameters */ -}; - -static u32 hsw_ddi_translations_fdi[] = { - 0x00FFFFFF, 0x0007000E, /* FDI parameters */ - 0x00D75FFF, 0x000F000A, - 0x00C30FFF, 0x00060006, - 0x00AAAFFF, 0x001E0000, - 0x00FFFFFF, 0x000F000A, - 0x00D75FFF, 0x00160004, - 0x00C30FFF, 0x001E0000, - 0x00FFFFFF, 0x00060006, - 0x00D75FFF, 0x001E0000, - 0x00FFFFFF, 0x00040006 /* HDMI parameters */ -}; - -/* On Haswell, DDI port buffers must be programmed with correct values - * in advance. The buffer values are different for FDI and DP modes, - * but the HDMI/DVI fields are shared among those. So we program the DDI - * in either FDI or DP modes only, as HDMI connections will work with both - * of those. - */ -static void intel_prepare_ddi_buffers(int port, int use_fdi_mode) -{ - u32 reg; - int i; - u32 *ddi_translations = ((use_fdi_mode) ? - hsw_ddi_translations_fdi : - hsw_ddi_translations_dp); - - printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", - port, - use_fdi_mode ? "FDI" : "DP"); - - for (i=0,reg=DDI_BUF_TRANS(port);i < ARRAY_SIZE(hsw_ddi_translations_fdi);i++) { - gtt_write(reg,ddi_translations[i]); - reg += 4; - } -} - -void intel_prepare_ddi(void) -{ - int port; - u32 use_fdi = 1; - - for (port = PORT_A; port < PORT_E; port++) - intel_prepare_ddi_buffers(port, !use_fdi); - - intel_prepare_ddi_buffers(PORT_E, use_fdi); -} diff --git a/src/drivers/intel/oc_mailbox/Kconfig b/src/drivers/intel/oc_mailbox/Kconfig new file mode 100644 index 00000000000..456fb19d8e1 --- /dev/null +++ b/src/drivers/intel/oc_mailbox/Kconfig @@ -0,0 +1,23 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_INTEL_OC_MAILBOX + bool + help + Provides access to the Intel's OC Mailbox MSR (0x150). + Supports 4th-10th generation Intel Core CPUs (Haswell-Cometlake). + +if DRIVERS_INTEL_OC_MAILBOX + +config INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING + bool "Enable undervolting via OC mailbox" + help + Program per-plane voltage offsets via OC Mailbox MSR. + When enabled, coreboot can apply per-domain undervolt settings at boot + (core/GT/cache/SA and I/O planes, depending on CPU generation). Settings + are exposed as runtime options and written using OC_MAILBOX commands. + +config HAS_DIGITAL_IO_POWER_DOMAIN + bool + default n + +endif diff --git a/src/drivers/intel/oc_mailbox/Makefile.mk b/src/drivers/intel/oc_mailbox/Makefile.mk new file mode 100644 index 00000000000..a2719753ed2 --- /dev/null +++ b/src/drivers/intel/oc_mailbox/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_INTEL_OC_MAILBOX) += oc_mailbox.c diff --git a/src/drivers/intel/oc_mailbox/cfr.h b/src/drivers/intel/oc_mailbox/cfr.h new file mode 100644 index 00000000000..6ea5c34f88c --- /dev/null +++ b/src/drivers/intel/oc_mailbox/cfr.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR objects and form for drivers/intel/oc_mailbox + */ + +#ifndef DRIVERS_INTEL_OC_MAILBOX_CFR_H +#define DRIVERS_INTEL_OC_MAILBOX_CFR_H + +#include +#include "oc_mailbox.h" + +static const struct sm_object oc_undervolt_apply = SM_DECLARE_BOOL({ + .opt_name = "oc_undervolt_apply", + .ui_name = "Apply OC mailbox undervolt", + .ui_helptext = "Program MSR OC_MAILBOX offsets at boot.\n" + "Use with caution; may cause instability.\n" + "Turn off to use platform defaults.", + .default_value = false, +}); + +static const struct sm_object oc_undervolt_core = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_core", + .ui_name = "CPU core undervolt (mV)", + .ui_helptext = "MSR plane 0. 0 = no undervolt. Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static const struct sm_object oc_undervolt_gpu = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_gpu", + .ui_name = "Intel GPU undervolt (mV)", + .ui_helptext = "MSR plane 1 (GT). Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static const struct sm_object oc_undervolt_cache = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_cache", + .ui_name = "CPU Cache undervolt (mV)", + .ui_helptext = "MSR plane 2. Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static const struct sm_object oc_undervolt_sa = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_sa", + .ui_name = "System Agent undervolt (mV)", + .ui_helptext = "MSR plane 3. Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static const struct sm_object oc_undervolt_analog_io = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_analog_io", + .ui_name = "Analog I/O undervolt (mV)", + .ui_helptext = "MSR plane 4. Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static const struct sm_object oc_undervolt_digital_io = SM_DECLARE_NUMBER({ + .opt_name = "oc_undervolt_digital_io", + .ui_name = "Digital I/O undervolt (mV)", + .ui_helptext = "MSR plane 5. Range: 0-125 mV.", + .default_value = 0, + .min = 0, + .max = OC_MBOX_MAX_VOLTAGE_OFFSET_MV, + .step = 1, + .display_flags = 0, +}, WITH_DEP_VALUES(&oc_undervolt_apply, true)); + +static struct sm_obj_form cpu_voltage = { + .ui_name = "CPU voltage (OC mailbox)", + .obj_list = (const struct sm_object *[]) { + &oc_undervolt_apply, + &oc_undervolt_core, + &oc_undervolt_gpu, + &oc_undervolt_cache, + &oc_undervolt_sa, + &oc_undervolt_analog_io, +#if CONFIG(HAS_DIGITAL_IO_POWER_DOMAIN) + &oc_undervolt_digital_io, +#endif + NULL + }, +}; + +#endif /* DRIVERS_INTEL_OC_MAILBOX_CFR_H */ diff --git a/src/drivers/intel/oc_mailbox/oc_mailbox.c b/src/drivers/intel/oc_mailbox/oc_mailbox.c new file mode 100644 index 00000000000..f318e49b5d4 --- /dev/null +++ b/src/drivers/intel/oc_mailbox/oc_mailbox.c @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "oc_mailbox.h" + +#define MSR_OC_MAILBOX 0x150 + +#define OC_MBOX_CMD_VOLTAGE_FREQ_OVR_READ 0x10 +#define OC_MBOX_CMD_VOLTAGE_FREQ_OVR_WRITE 0x11 + +union voltage_freq_override_data { + struct __packed { + uint32_t max_ratio_limit : 8; /* Bits 7:0: Max OC ratio limit */ + uint32_t voltage_target : 12; /* Bits 19:8: Voltage target in U12.2.10V format */ + uint32_t target_mode : 1; /* Bit 20: 0=PCU adaptive, 1=override */ + int32_t voltage_offset : 11; /* Bits 31:21: Voltage offset in S11.0.10V format */ + }; + uint32_t raw; +}; + +union oc_mailbox_msr { + struct __packed { + uint32_t data; /* Bits 31:0 */ + union oc_mailbox_interface interface; /* Bits 63:32 */ + }; + uint64_t raw; + msr_t msr; +}; + +enum oc_mailbox_plane { + OC_PLANE_CORE = 0, + OC_PLANE_GPU, + OC_PLANE_CACHE, + OC_PLANE_SA, + OC_PLANE_ANALOG_IO, + OC_PLANE_DIGITAL_IO, + OC_PLANE_MAX, +}; + +static const char *const plane_opt_names[OC_PLANE_MAX] = { + [OC_PLANE_CORE] = "oc_undervolt_core", + [OC_PLANE_GPU] = "oc_undervolt_gpu", + [OC_PLANE_CACHE] = "oc_undervolt_cache", + [OC_PLANE_SA] = "oc_undervolt_sa", + [OC_PLANE_ANALOG_IO] = "oc_undervolt_analog_io", + [OC_PLANE_DIGITAL_IO] = "oc_undervolt_digital_io", +}; + +static const char *const plane_log_names[OC_PLANE_MAX] = { + [OC_PLANE_CORE] = "core", + [OC_PLANE_GPU] = "gpu", + [OC_PLANE_CACHE] = "cache", + [OC_PLANE_SA] = "sa", + [OC_PLANE_ANALOG_IO] = "analog_io", + [OC_PLANE_DIGITAL_IO] = "digital_io", +}; + +int oc_mailbox_ready(void) +{ + int wait_count; + const int delay_step = 10; + + wait_count = 0; + do { + const union oc_mailbox_msr oc_mbox = { .msr = rdmsr(MSR_OC_MAILBOX) }; + if (oc_mbox.interface.run_busy == 0) + return 0; + wait_count += delay_step; + udelay(delay_step); + } while (wait_count < 1000); + + return -1; +} + +u32 oc_mailbox_read(const union oc_mailbox_interface command) +{ + if (oc_mailbox_ready() < 0) { + printk(BIOS_ERR, "OC mailbox: timeout on wait ready\n"); + return 0; + } + + union oc_mailbox_msr wr = { + .interface = command, + .data = 0, + }; + wr.interface.run_busy = 1; + wrmsr(MSR_OC_MAILBOX, wr.msr); + + if (oc_mailbox_ready() < 0) { + printk(BIOS_ERR, "OC mailbox: timeout on completion\n"); + return 0; + } + + const union oc_mailbox_msr rd = { .msr = rdmsr(MSR_OC_MAILBOX) }; + if (rd.interface.cmd_code != 0) { + printk(BIOS_ERR, "OC mailbox: command failed with error 0x%02x\n", + rd.interface.cmd_code); + return 0; + } + return rd.data; +} + +int oc_mailbox_write(const union oc_mailbox_interface command, u32 data) +{ + if (oc_mailbox_ready() < 0) { + printk(BIOS_ERR, "OC mailbox: timeout on wait ready\n"); + return -1; + } + + union oc_mailbox_msr wr = { + .interface = command, + .data = data, + }; + wr.interface.run_busy = 1; + wrmsr(MSR_OC_MAILBOX, wr.msr); + + if (oc_mailbox_ready() < 0) { + printk(BIOS_ERR, "OC mailbox: timeout on completion\n"); + return -1; + } + + const union oc_mailbox_msr rd = { .msr = rdmsr(MSR_OC_MAILBOX) }; + if (rd.interface.cmd_code != 0) { + printk(BIOS_ERR, "OC mailbox: command failed with error 0x%02x\n", + rd.interface.cmd_code); + return -1; + } + + return 0; +} + +/* + * Convert a signed voltage tweak in mV into OC_MAILBOX fixed-point units for + * voltage_offset (S11.0.10V). Negative mV is undervolt, positive is overvolt, + * matching common tools (intel-undervolt / ThrottleStop). + * + * The hardware allows roughly +/-500 mV; we cap the absolute adjustment at + * 125 mV for policy reasons. The return value is round(|in_mv| * 1024 / 1000) + * in those units, with the original sign (after clamping magnitude). + */ +static int encode_voltage(const int in_mv) +{ + const int sign = in_mv < 0 ? -1 : 1; + const int abs_mv = MIN(in_mv * sign, OC_MBOX_MAX_VOLTAGE_OFFSET_MV); + + return DIV_ROUND_CLOSEST(abs_mv * 1024, 1000) * sign; +} + +static bool set_plane_undervolt(enum oc_mailbox_plane plane, unsigned int undervolt_mv) +{ + if (plane >= OC_PLANE_MAX) + return false; + + printk(BIOS_INFO, "OC mailbox: setting plane %s undervolt to %u mV\n", + plane_log_names[plane], undervolt_mv); + + /* Program voltage offset; leave target/ratio fields at 0. */ + const union voltage_freq_override_data data = { + .voltage_offset = encode_voltage(-(int)undervolt_mv), + }; + const union oc_mailbox_interface command_wr = { + .cmd_code = OC_MBOX_CMD_VOLTAGE_FREQ_OVR_WRITE, + .param1 = plane, + }; + + if (oc_mailbox_write(command_wr, data.raw) < 0) + return false; + + const union oc_mailbox_interface command_rd = { + .cmd_code = OC_MBOX_CMD_VOLTAGE_FREQ_OVR_READ, + .param1 = plane, + }; + const uint32_t readback = oc_mailbox_read(command_rd); + + if (readback != data.raw) { + printk(BIOS_WARNING, + "OC mailbox: plane %s verify failed (expected 0x%08x got 0x%08x)\n", + plane_log_names[plane], data.raw, readback); + return false; + } + return true; +} + +/* HSW/BDW expose 6 planes; SKL-CML expose 5 (no digital_io plane). */ +static const enum oc_mailbox_plane last_plane = CONFIG(HAS_DIGITAL_IO_POWER_DOMAIN) ? + OC_PLANE_DIGITAL_IO : OC_PLANE_ANALOG_IO; + +static void oc_mailbox_undervolt(void) +{ + uint32_t status = 0; + + if (!get_uint_option("oc_undervolt_apply", false)) + return; + + printk(BIOS_INFO, "OC mailbox: applying voltage offsets\n"); + + /* + * We program all planes/offsets (including zero) to ensure that the mailbox + * is in a consistent state, and that previous settings are cleared. + */ + for (enum oc_mailbox_plane i = 0; i <= last_plane; i++) { + const unsigned int undervolt_mv = get_uint_option(plane_opt_names[i], 0); + if (set_plane_undervolt(i, undervolt_mv)) + status |= 1 << i; + } + if (status == 0) + printk(BIOS_INFO, "OC mailbox: all planes programmed successfully\n"); + else + printk(BIOS_ERR, "OC mailbox: plane programming failed, status = 0x%x\n", status); +} + +void program_oc_mailbox(void) +{ + if (CONFIG(INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING)) + oc_mailbox_undervolt(); +} diff --git a/src/drivers/intel/oc_mailbox/oc_mailbox.h b/src/drivers/intel/oc_mailbox/oc_mailbox.h new file mode 100644 index 00000000000..dd04aee4962 --- /dev/null +++ b/src/drivers/intel/oc_mailbox/oc_mailbox.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_INTEL_OC_MAILBOX_H_ +#define _DRIVERS_INTEL_OC_MAILBOX_H_ + +#include +#include + +#define OC_MBOX_MAX_VOLTAGE_OFFSET_MV 125 + +union oc_mailbox_interface { + struct __packed { + uint32_t cmd_code : 8; /* Bits 7:0 */ + uint32_t param1 : 8; /* Bits 15:8 */ + uint32_t param2 : 8; /* Bits 23:16 */ + uint32_t unused1 : 7; /* Bits 30:24 */ + uint32_t run_busy : 1; /* Bits 31:31 */ + }; + uint32_t raw; +}; + +int oc_mailbox_ready(void); +u32 oc_mailbox_read(const union oc_mailbox_interface command); +int oc_mailbox_write(const union oc_mailbox_interface command, u32 data); + +void program_oc_mailbox(void); + +#endif diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h index 6e2696ff3fe..d714ea7008c 100644 --- a/src/drivers/intel/touch/chip.h +++ b/src/drivers/intel/touch/chip.h @@ -180,7 +180,7 @@ enum intel_touch_device { TH_SENSOR_WACOM, /* BOM22 for SPI only */ /* * TH_SENSOR_ELAN: the ELAN device for Intel's RVPs (default for ELAN) - * TH_SENSOR_ELAN_REX: the devece used in Google Rex; requires a special cable for Intel's RVP + * TH_SENSOR_ELAN_REX: the device used in Google Rex; requires a special cable for Intel's RVP */ TH_SENSOR_ELAN, /* BOM36 for SPI and BOM37 for I2C */ TH_SENSOR_ELAN_REX, /* ELAN9006 for SPI and ELAN6918 for I2C */ diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h index 2b60d50a251..0de05111605 100644 --- a/src/drivers/intel/usb4/retimer/chip.h +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -7,7 +7,7 @@ #include #include -#define DFP_NUM_MAX 2 +#define DFP_NUM_MAX 4 enum ec_typec_port { UNDEFINED = 0, @@ -18,6 +18,7 @@ enum ec_typec_port { }; struct drivers_intel_usb4_retimer_config { + uint8_t num_dfps; /* Downstream facing port(DFP) */ struct { /* GPIO used to control power of retimer device */ diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 6c220f2b07f..ba06f95bb52 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -382,6 +383,12 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) if (!usb4_retimer_scope || !config) return; + assert(config->num_dfps <= DFP_NUM_MAX); + /* All existing boards have 2 DFPs. If num_dfps is not configfured, then + set it to 2 by default. */ + if (!config->num_dfps) + config->num_dfps = 2; + /* Scope */ acpigen_write_scope(usb4_retimer_scope); @@ -390,7 +397,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) { + for (dfp_port = 0; dfp_port < config->num_dfps; dfp_port++) { if (!config->dfp[dfp_port].power_gpio.pin_count) { printk(BIOS_WARNING, "%s: No DFP%1d power GPIO for %s\n", __func__, dfp_port, dev_path(dev)); diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index b8e5812b714..8e087f7f6d4 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -16,16 +16,6 @@ config REALTEK_8168_MACADDRESS hexadecimal number for it to be valid. Failing to do so will result in the default macaddress being used. -config RT8168_PUT_MAC_TO_ERI - bool - help - After programming MAC address into the regular rt8168 ID registers, - also program it into ERI. On some mainboards our programmed - MAC address will not survive a controller reset without this step. - - Select at mainboard level only if its rt8168 has no EEPROM and - programmed MAC address is lost after booting to OS. - config RT8168_GET_MAC_FROM_VPD bool default n diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 203707c4367..d65eb0cb3a5 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -35,6 +35,9 @@ struct drivers_net_config { /* Allow kernel driver to enable ASPM L1.2. */ bool enable_aspm_l1_2; + /* Enable CLKREQ# via PCI config register 0x81 (RTL8168 specific). */ + bool enable_pcie_clkreq; + /* When set to true, this will add a _DSD which contains a single property, `DmaProperty`, set to 1, under the ACPI Device. */ bool add_acpi_dma_property; diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 8ef2ee8148e..7132f15cc18 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -39,6 +39,16 @@ #define ASPM_L1_2_MASK 0xe059000f #define ERIDR 0x70 #define ERIAR 0x74 +#define TX_CONFIG 0x40 + +/* From Realtek r8168 Linux driver */ +#define TXCFG_CHIP_FAMILY_MASK 0x7c800000 +#define TXCFG_IC_VER_ID_MASK 0x00700000 +#define TXCFG_IC_VER_ID_METHOD_17 0x00100000 +#define TXCFG_FAMILY_8168EVL_METHOD_17 0x2c800000 +#define TXCFG_FAMILY_8168F_UP 0x48000000 + +#define ERIAR_WRITE_MASK 0x8000f000 #define DEVICE_INDEX_BYTE 12 #define MAX_DEVICE_SUPPORT 10 @@ -149,25 +159,24 @@ static void fetch_mac_string_vpd(struct drivers_net_config *config, u8 *macstrbu if (!config) return; + uint8_t index = config->device_index; + /* Current implementation is up to 10 NIC cards */ - if (config->device_index > MAX_DEVICE_SUPPORT) { + if (index > MAX_DEVICE_SUPPORT) { printk(BIOS_ERR, "r8168: the maximum device_index should be less then %d\n." " Using default 00:e0:4c:00:c0:b0\n", MAX_DEVICE_SUPPORT); return; } - if (fetch_mac_vpd_dev_idx(macstrbuf, config->device_index) == CB_SUCCESS) + if (CONFIG(RT8168_SUPPORT_LEGACY_VPD_MAC) && index == 0 && + fetch_mac_vpd_key(macstrbuf, "ethernet_mac") == CB_SUCCESS) return; - if (!CONFIG(RT8168_SUPPORT_LEGACY_VPD_MAC)) { - printk(BIOS_ERR, "r8168: mac address not found in VPD," - " using default 00:e0:4c:00:c0:b0\n"); + if (fetch_mac_vpd_dev_idx(macstrbuf, index) == CB_SUCCESS) return; - } - if (fetch_mac_vpd_key(macstrbuf, "ethernet_mac") != CB_SUCCESS) - printk(BIOS_ERR, "r8168: mac address not found in VPD," - " using default 00:e0:4c:00:c0:b0\n"); + printk(BIOS_ERR, "r8168: mac address not found in VPD," + " using default 00:e0:4c:00:c0:b0\n"); } static enum cb_err fetch_mac_string_cbfs(u8 *macstrbuf) @@ -199,6 +208,41 @@ static void get_mac_address(u8 *macaddr, const u8 *strbuf) } } +static void r8168_eri_write(u16 io_base, u32 reg, u32 data) +{ + outl(data, io_base + ERIDR); + inl(io_base + ERIDR); + outl(ERIAR_WRITE_MASK | reg, io_base + ERIAR); + inl(io_base + ERIAR); +} + +/* + * Program MAC to ERI (Extended Register Interface) + * 8168E-VL (CFG_METHOD_17) uses 0xf0/0xf4; CFG_METHOD_18+ uses 0xe0/0xe4. + * Pre-CFG_METHOD_17 does not support ERI. + */ +static void program_mac_eri(u16 io_base, u32 maclo, u32 machi) +{ + const u32 txconfig = inl(io_base + TX_CONFIG); + const u32 family = txconfig & TXCFG_CHIP_FAMILY_MASK; + const u32 ic_ver = txconfig & TXCFG_IC_VER_ID_MASK; + const bool method_17 = family == TXCFG_FAMILY_8168EVL_METHOD_17 && + ic_ver == TXCFG_IC_VER_ID_METHOD_17; + + if (!method_17 && family < TXCFG_FAMILY_8168F_UP) + return; + + if (method_17) { + r8168_eri_write(io_base, 0xf0, (maclo & 0xffff) << 16); + r8168_eri_write(io_base, 0xf4, (maclo >> 16) | (machi << 16)); + } else { + r8168_eri_write(io_base, 0xe0, maclo); + r8168_eri_write(io_base, 0xe4, machi); + } + + udelay(1000); +} + static void program_mac_address(struct device *dev, u16 io_base) { u8 macstrbuf[MACLEN] = { 0 }; @@ -239,34 +283,16 @@ static void program_mac_address(struct device *dev, u16 io_base) /* Set MAC address: only 4-byte write accesses allowed */ maclo = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24; machi = mac[4] | mac[5] << 8; + + /* Write MAC to ID registers (MAC4/MAC0) */ outl(machi, io_base + 4); inl(io_base + 4); outl(maclo, io_base); inl(io_base); - /* Some boards (e.g. asus/p8z77-v_le_plus) need the MAC address set here too */ - if (CONFIG(RT8168_PUT_MAC_TO_ERI)) { - switch (pci_read_config8(dev, PCI_REVISION_ID)) { - case 6: - outl((maclo & 0xffff) << 16, io_base + ERIDR); - inl(io_base + ERIDR); - outl(0x8000f0f0, io_base + ERIAR); - inl(io_base + ERIAR); - outl((machi << 16 | maclo >> 16), io_base + ERIDR); - inl(io_base + ERIDR); - outl(0x8000f0f4, io_base + ERIAR); - break; - case 9: - outl(maclo, io_base + ERIDR); - inl(io_base + ERIDR); - outl(0x8000f0e0, io_base + ERIAR); - inl(io_base + ERIAR); - outl(machi, io_base + ERIDR); - inl(io_base + ERIDR); - outl(0x800030e4, io_base + ERIAR); - break; - } - udelay(1000); - } + + /* Write MAC to ERI (Extended Register Interface) */ + program_mac_eri(io_base, maclo, machi); + /* Lock config regs */ outb(CFG_9346_LOCK, io_base + CFG_9346); @@ -361,6 +387,7 @@ static void r8168_set_customized_led(struct device *dev, u16 io_base) static void r8168_init(struct device *dev) { + struct drivers_net_config *config = dev->chip_info; /* Get the resource of the NIC mmio */ struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); u16 io_base = (u16)nic_res->base; @@ -374,6 +401,10 @@ static void r8168_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable CLKREQ# if set in devicetree. */ + if (config && config->enable_pcie_clkreq) + pci_write_config8(dev, 0x81, 0x01); + /* Program MAC address based on CBFS "macaddress" containing * a string AA:BB:CC:DD:EE:FF */ program_mac_address(dev, io_base); @@ -382,8 +413,7 @@ static void r8168_init(struct device *dev) if (CONFIG(RT8168_SET_LED_MODE)) r8168_set_customized_led(dev, io_base); - struct drivers_net_config *config = dev->chip_info; - if (CONFIG(PCIEXP_ASPM) && config->enable_aspm_l1_2) + if (CONFIG(PCIEXP_ASPM) && config && config->enable_aspm_l1_2) enable_aspm_l1_2(io_base); } diff --git a/src/drivers/pcie/rtd3/device/chip.c b/src/drivers/pcie/rtd3/device/chip.c index 314aff81504..e642767f280 100644 --- a/src/drivers/pcie/rtd3/device/chip.c +++ b/src/drivers/pcie/rtd3/device/chip.c @@ -8,7 +8,6 @@ #include #include #include -#include #include "chip.h" /* diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index be049173b60..4a73061d6a1 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -173,6 +173,19 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev) } acpigen_pop_len(); /* Device */ + + /* + * Intel PEP may require the GSPI host (e.g. SPI1) at D3 while power is on + * the child device. Empty _PS0/_PS3 on the host scope satisfy LPI without + * duplicating the child's PowerResource sequencing. + */ + if (config->has_power_resource) { + acpigen_write_method_serialized("_PS0", 0); + acpigen_pop_len(); /* Method */ + acpigen_write_method_serialized("_PS3", 0); + acpigen_pop_len(); /* Method */ + } + acpigen_pop_len(); /* Scope */ printk(BIOS_INFO, "%s: %s at %s\n", path, diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index daf8a219dbf..1943cd981b7 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -251,11 +251,41 @@ int spi_flash_cmd_wait_ready(const struct spi_flash *flash, CMD_READ_STATUS, STATUS_WIP); } +/* + * Find a SPI flash block erase command from SFDP that fits the constrains. + * + * @param flash Pointer to struct spi_flash + * @param offset Offset in bytes from start of SPI flash to start of region to erase + * @param end Offset in bytes from start of SPI flash to end of region to erase + * + * @return Pointer to struct sfdp_block_erase_info, NULL if not suitable SFDP block was found + */ +static const struct sfdp_block_erase_info * +spi_flash_sfdp_erase_block(const struct sfdp_jedec_info *sfdp, const u32 offset, const u32 end) +{ + const struct sfdp_block_erase_info *info, *best = NULL; + for (int i = 0; i < ARRAY_SIZE(sfdp->erase_info); i++) { + info = &sfdp->erase_info[i]; + if (!info->block_size_pow2) + break; + const uint32_t bs = (1U << info->block_size_pow2); + if ((offset + bs) > end) + continue; + if (!IS_ALIGNED(offset, bs)) + continue; + if (best && best->block_size_pow2 > info->block_size_pow2) + continue; + best = info; + } + return best; +} + int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret = -1; - u8 cmd[4 + ADDR_MOD]; + u8 cmd[4 + ADDR_MOD], erase_cmd; + struct sfdp_jedec_info info = {0}; erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -267,12 +297,53 @@ int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) return -1; } - cmd[0] = flash->erase_cmd; + /* + * Only parse SFDP when necessary since reading it in is slow. + * Using 33Mhz SPI bus frequency it takes about 150 usec to read it. + * + * The SFDP JEDEC info isn't cached as 'struct spi_flash' is read only here, + * and erasing the flash isn't usually done as part of the boot. + * On MT25QU256ABA using SFDP results in using 64KiB erase block sizes + * over 4KiB blocks and thus reduces boot time by 67msec for each erased block. + * The time to read SFDP, every time this function is called, is thus negligible. + */ + if (CONFIG(SPI_FLASH_SFDP) && (len >= 2 * erase_size)) { + if (spi_flash_get_sfdp_info(flash, &info) == CB_SUCCESS) { + for (int i = 0; i < ARRAY_SIZE(info.erase_info); i++) { + if (!info.erase_info[i].block_size_pow2) + continue; + printk(BIOS_DEBUG, "SF: Erase block size 0x%08x, OP=0x%02x\n", + 1U << info.erase_info[i].block_size_pow2, + info.erase_info[i].opcode); + } + } + } + + erase_cmd = flash->erase_cmd; start = offset; end = start + len; while (offset < end) { spi_flash_addr(offset, cmd); + + /* + * Try to find a better suited erase op code when SFDP is + * available and spi_flash_get_sfdp_info() was successful. + */ + if (CONFIG(SPI_FLASH_SFDP) && + info.erase_info[0].block_size_pow2) { + const struct sfdp_block_erase_info *best = + spi_flash_sfdp_erase_block(&info, offset, end); + if (best) { + erase_size = 1U << best->block_size_pow2; + erase_cmd = best->opcode; + } else { + erase_size = flash->sector_size; + erase_cmd = flash->erase_cmd; + } + } + + cmd[0] = erase_cmd; offset += erase_size; if (CONFIG(DEBUG_SPI_FLASH)) { diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index c20369cdf49..0894119bd0a 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -164,4 +164,15 @@ enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, /* Fill rpmc_caps field in spi_flash struct with RPMC config from SFDP */ void spi_flash_fill_rpmc_caps(struct spi_flash *flash); +/** + * Get JEDEC flash parameters from the SPI flash's SFDP table. + * + * @param flash The SPI flash to read SFDP info from + * @param info The struct to fill with parsed data + * + * @return CB_SUCCESS on Success + */ +enum cb_err spi_flash_get_sfdp_info(const struct spi_flash *flash, + struct sfdp_jedec_info *info); + #endif /* SPI_FLASH_INTERNAL_H */ diff --git a/src/drivers/spi/spi_flash_rpmc.c b/src/drivers/spi/spi_flash_rpmc.c index 27342ab351a..52fdb341fe5 100644 --- a/src/drivers/spi/spi_flash_rpmc.c +++ b/src/drivers/spi/spi_flash_rpmc.c @@ -105,25 +105,26 @@ static bool spi_flash_rpmc_is_extended_status_successful(uint8_t extended_status return extended_status & RPMC_OP2_EXT_STATUS_SUCCESS; } -static void spi_flash_rpmc_print_extended_status_error(uint8_t extended_status) +static void spi_flash_rpmc_print_extended_status_error(const struct spi_flash *flash, + uint8_t extended_status) { if (extended_status & RPMC_OP2_EXT_STATUS_POLL_BUSY) - printk(BIOS_WARNING, "SPI flash RPMC is busy\n"); + printk(BIOS_WARNING, "SPI flash CS %d RPMC is busy\n", flash->spi.cs); if (extended_status & RPMC_OP2_EXT_STATUS_ERR_OTHER) - printk(BIOS_ERR, "SPI flash RPMC other error\n"); + printk(BIOS_ERR, "SPI flash CS %d RPMC other error\n", flash->spi.cs); if (extended_status & RPMC_OP2_EXT_STATUS_ERR_INVALID) - printk(BIOS_ERR, "SPI flash RPMC invalid input\n"); + printk(BIOS_ERR, "SPI flash CS %d RPMC invalid input\n", flash->spi.cs); if (extended_status & RPMC_OP2_EXT_STATUS_ERR_UNINITIALIZED) - printk(BIOS_ERR, "SPI flash RPMC uninitialized\n"); + printk(BIOS_ERR, "SPI flash CS %d RPMC uninitialized\n", flash->spi.cs); if (extended_status & RPMC_OP2_EXT_STATUS_ERR_BAD_COUNTER) - printk(BIOS_ERR, "SPI flash RPMC counter mismatch\n"); + printk(BIOS_ERR, "SPI flash CS %d RPMC counter mismatch\n", flash->spi.cs); if (extended_status & RPMC_OP2_EXT_STATUS_ERR_FATAL) - printk(BIOS_ERR, "SPI flash RPMC fatal error\n"); + printk(BIOS_ERR, "SPI flash CS %d RPMC fatal error\n", flash->spi.cs); } static enum cb_err spi_flash_rpmc_check_extended_status(const struct spi_flash *flash) @@ -136,7 +137,7 @@ static enum cb_err spi_flash_rpmc_check_extended_status(const struct spi_flash * if (spi_flash_rpmc_is_extended_status_successful(extended_status)) return CB_SUCCESS; - spi_flash_rpmc_print_extended_status_error(extended_status); + spi_flash_rpmc_print_extended_status_error(flash, extended_status); return CB_ERR; } @@ -329,7 +330,7 @@ enum cb_err spi_flash_rpmc_request(const struct spi_flash *flash, uint8_t counte return CB_ERR; if (!spi_flash_rpmc_is_extended_status_successful(extended_status)) { - spi_flash_rpmc_print_extended_status_error(extended_status); + spi_flash_rpmc_print_extended_status_error(flash, extended_status); return CB_ERR; } diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c index 94509fdf56c..17fb713d482 100644 --- a/src/drivers/spi/spi_flash_sfdp.c +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "spi_flash_internal.h" @@ -363,3 +364,82 @@ enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, buf[SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_LONG_DELAY]); return CB_SUCCESS; } + +#define SFDP_PARAMETER_ID_JEDEC 0xff00 +#define SFDP_JEDEC_PARAM_TABLE_LENGTH_DWORDS 9 +#define SFDP_JEDEC_PARAM_TABLE_SUPPORTED_MAJOR_REV 1 + +/* RPMC parameter table byte offsets and fields */ +#define SFDP_JEDEC_TABLE_CONFIG 0 +#define SFDP_JEDEC_TABLE_CONFIG_ERASE_MASK 0x3 +#define SFDP_JEDEC_TABLE_CONFIG_ERASE_4K_SUPPORT 0x1 + +#define SFDP_JEDEC_TABLE_CONFIG_4K_ERASE_OPCODE 1 + +#define SFDP_JEDEC_TABLE_NUM_VAR_ERASE_BLOCKS 4 +#define SFDP_JEDEC_TABLE_ERASE_BLOCK_SIZE(x) (0x1c + 2 * (x)) +#define SFDP_JEDEC_TABLE_ERASE_BLOCK_OPCODE(x) (0x1d + 2 * (x)) + +enum cb_err spi_flash_get_sfdp_info(const struct spi_flash *flash, + struct sfdp_jedec_info *info) +{ + uint16_t rev; + uint8_t length_dwords; + uint32_t table_pointer; + uint8_t buf[SFDP_JEDEC_PARAM_TABLE_LENGTH_DWORDS * sizeof(uint32_t)]; + uint8_t op, size; + size_t num_erasers = 0; + + if (!flash || !info) + return CB_ERR_ARG; + + memset(info, 0, sizeof(*info)); + + if (find_sfdp_parameter_header(flash, SFDP_PARAMETER_ID_JEDEC, &rev, &length_dwords, + &table_pointer) != CB_SUCCESS) + return CB_ERR; + + if (length_dwords < SFDP_JEDEC_PARAM_TABLE_LENGTH_DWORDS) + return CB_ERR; + + if (rev >> 8 != SFDP_JEDEC_PARAM_TABLE_SUPPORTED_MAJOR_REV) { + printk(BIOS_ERR, "Unsupported major JEDEC param table revision: expected %#x, but is %#x\n", + SFDP_JEDEC_PARAM_TABLE_SUPPORTED_MAJOR_REV, rev >> 8); + return CB_ERR; + } + + if (read_sfdp_data(flash, table_pointer, sizeof(buf), buf) != CB_SUCCESS) + return CB_ERR; + + /* 4K erase support */ + op = buf[SFDP_JEDEC_TABLE_CONFIG_4K_ERASE_OPCODE]; + size = buf[SFDP_JEDEC_TABLE_CONFIG] & SFDP_JEDEC_TABLE_CONFIG_ERASE_MASK; + + if (size == SFDP_JEDEC_TABLE_CONFIG_ERASE_4K_SUPPORT && op != 0xff) { + info->erase_info[num_erasers].opcode = op; + info->erase_info[num_erasers].block_size_pow2 = 12; + num_erasers++; + } + + /* block erase opcodes. The 4K erase opcode might be in the list as well. */ + for (int n = 0; n < SFDP_JEDEC_TABLE_NUM_VAR_ERASE_BLOCKS; n++) { + size = buf[SFDP_JEDEC_TABLE_ERASE_BLOCK_SIZE(n)]; + op = buf[SFDP_JEDEC_TABLE_ERASE_BLOCK_OPCODE(n)]; + + /* Already in list? */ + for (int j = 0; j < num_erasers; j++) { + if (info->erase_info[j].opcode == op) { + size = 0; /* then skip it */ + break; + } + } + + if (op && size > 0) { + info->erase_info[num_erasers].opcode = op; + info->erase_info[num_erasers].block_size_pow2 = size; + num_erasers++; + } + } + + return CB_SUCCESS; +} diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 2f5a8b02a53..a29ed3911f7 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -50,6 +50,8 @@ #define STM_ID_N25Q128__1E 0xbb18 #define STM_ID_N25Q256__1E 0xbb19 +#define XMC_ID_XM25RU256C 0x4419 + static const struct spi_flash_part_id flash_table_se32k[] = { { /* M25P10 */ @@ -190,6 +192,11 @@ static const struct spi_flash_part_id flash_table_sse[] = { .id[0] = STM_ID_N25Q256__1E, .nr_sectors_shift = 13, }, + { + /* XMC XM25RU256C */ + .id[0] = XMC_ID_XM25RU256C, + .nr_sectors_shift = 13, + }, }; int stmicro_release_deep_sleep_identify(const struct spi_slave *spi, u8 *idcode) diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 815a0cfb05c..2c609a82d95 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -53,8 +53,7 @@ void uart_init(unsigned int idx) * <=> * div = (f_in / f_baud) - 1 */ - unsigned int div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), - uart_input_clock_divider()); + unsigned int div = uart_get_baudrate_divisor(); div -= 1; sifive_uart_init(uart_platform_baseptr(idx), div); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 89ec229dfc9..ba5c723fa6c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -87,9 +87,7 @@ uintptr_t uart_platform_base(unsigned int idx) void uart_init(unsigned int idx) { if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) { - unsigned int div; - div = uart_baudrate_divisor(get_uart_baudrate(), - uart_platform_refclk(), uart_input_clock_divider()); + unsigned int div = uart_get_baudrate_divisor(); uart8250_init(uart_platform_base(idx), div); } } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index fcf031e3782..42509f915eb 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -103,9 +103,7 @@ void uart_init(unsigned int idx) if (!base) return; - unsigned int div; - div = uart_baudrate_divisor(get_uart_baudrate(), - uart_platform_refclk(), uart_input_clock_divider()); + unsigned int div = uart_get_baudrate_divisor(); uart8250_mem_init(base, div); } diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 1ac994e6c8d..2db1a373643 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -5,7 +5,7 @@ #include /* Calculate divisor. Do not floor but round to nearest integer. */ -unsigned int uart_baudrate_divisor(unsigned int baudrate, +unsigned int uart_calc_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample) { return (1 + (2 * refclk) / (baudrate * oversample)) / 2; diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 081f7cb754f..db4ad9e540c 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -17,6 +17,14 @@ config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP not defined, the memmap data is instead accessed on 900h-9ffh via the LPC bus. +config EC_GOOGLE_CHROMEEC_ACPI_HID + string + default "GOOG0004" + help + Allow customizing the ACPI HID name to allow the OSPM to match on + different CrosEC implementations (e.g. Framework Computer's + FRMWC004). + config EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER def_bool n help @@ -267,6 +275,14 @@ config EC_GOOGLE_CHROMEEC_LED_CONTROL Enable manual AP control over ChromeEC LEDs/lightbars to ensure visual continuity with AP-side boot animations. +config EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS + bool "Include vendor tablet mode controls (VBTN/VGBI) in ACPI" + default y if !CHROMEOS && (SYSTEM_TYPE_CONVERTIBLE || SYSTEM_TYPE_DETACHABLE) + help + Include ACPI devices for tablet mode / convertible controls (Intel VBTN, + AMD VGBI). Default is enabled for non-ChromeOS builds when the board + reports SMBIOS enclosure type convertible or detachable. + endif # EC_GOOGLE_CHROMEEC source "src/ec/google/chromeec/*/Kconfig" diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index eb19c3c4225..be96bc7fb4c 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -40,6 +40,10 @@ Method (BTSW, 1) // Arg0 = battery index Method (BSTA, 1, Serialized) { + If (!DFUD &&!(BATT || SBAT)) { + Return (0) + } + If (Acquire (^BATM, 1000)) { Return (0) } diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index f29ca14efcc..90e662c44bf 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -6,7 +6,7 @@ Device (CREC) { - Name (_HID, "GOOG0004") + Name (_HID, CONFIG_EC_GOOGLE_CHROMEEC_ACPI_HID) Name (_UID, 1) Name (_DDN, "EC Command Device") #ifdef EC_ENABLE_WAKE_PIN @@ -62,6 +62,15 @@ CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) Name (_HID, "GOOG0007") Name (_UID, 1) Name (_DDN, "EC MKBP Device") + + Method (_STA, 0) + { + If (DFUD || KEYB) { + Return (0xF) + } + + Return (0) + } } #endif diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 93b04718ec8..e6f1852b65f 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -14,6 +14,9 @@ #define ACPI_NOTIFY_CROS_EC_MKBP 0x80 #define ACPI_NOTIFY_CROS_EC_PANIC 0xB0 +/* Windows CrosEc / crosecbus: ACPI notify on GOOG0004 (CREC) */ +#define ACPI_NOTIFY_CROS_EC_S0IX_ENTER 0x01 +#define ACPI_NOTIFY_CROS_EC_S0IX_EXIT 0x02 // Mainboard specific throttle handler #ifdef DPTF_ENABLE_CHARGER @@ -119,6 +122,42 @@ Device (EC0) #include "emem.asl" } +#ifdef EC_FRAMEWORK_ACPI_SHARED_MEM_IO + /* + * Framework EC custom shared-memory + * byte 0 (EC memmap 0x100): system flags + * byte 1 (EC memmap 0x101): power state + */ + OperationRegion (FRMW, SystemIO, EC_FRAMEWORK_ACPI_SHARED_MEM_IO, 0x02) + Field (FRMW, ByteAcc, NoLock, Preserve) + { + ADRD, 1, // ACPI driver ready (exit EC preOS mode) + Offset (0x01), // power-state byte + , 6, // EC_PS_{ENTER,RESUME}_S3/S4/S5 + ENS0, 1, // EC_PS_ENTER_S0ix (BIT6) + RES0, 1, // EC_PS_RESUME_S0ix (BIT7) + } +#else + /* Dummy vars to avoid guarding in S0ix() */ + Name (ENS0, 0) + Name (RES0, 0) +#endif + /* + * S0ix entry/exit notification invoked by PEP LPS0 _DSM + */ + Method (S0IX, 1, Serialized) + { + If (Arg0 == 1) { + ENS0 = 1 // notify EC: entering S0ix (ENTER_CS) + /* Let EC settle before proceeding, same as vendor firmware */ + Sleep (0xD2) + Notify (^CREC, ACPI_NOTIFY_CROS_EC_S0IX_ENTER) + } Else { + RES0 = 1 // notify EC: resuming from S0ix (RESUME_CS) + Notify (^CREC, ACPI_NOTIFY_CROS_EC_S0IX_EXIT) + } + } + #ifdef EC_ENABLE_LID_SWITCH /* LID Switch */ Device (LID0) @@ -135,6 +174,18 @@ Device (EC0) } #endif /* EC_ENABLE_LID_SWITCH */ +#ifdef EC_ENABLE_POWER_BUTTON + /* Power Button */ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + +#ifdef EC_ENABLE_WAKE_PIN + Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) +#endif + } +#endif /* EC_ENABLE_POWER_BUTTON */ + Method (TINS, 1, Serialized) { Switch (ToInteger (Arg0)) @@ -171,6 +222,15 @@ Device (EC0) Method (_REG, 2, NotSerialized) { +#ifdef EC_FRAMEWORK_ACPI_SHARED_MEM_IO + /* + * When OSPM's ACPI EC driver connects the EmbeddedControl region, + * the OS is up: tell the Framework EC to leave "preOS" mode + */ + If ((Arg0 == 0x03) && (Arg1 == 0x01)) { + ADRD = 1 + } +#endif // Initialize AC power state \PWRS = ACEX /* @@ -203,6 +263,20 @@ Device (EC0) #endif } +#ifdef EC_FRAMEWORK_ACPI_SHARED_MEM_IO + Method (_INI, 0, NotSerialized) + { + /* + * The vendor firmware signals driver-ready from _INI as well as + * from _REG (for ACPI 2.0+ OSes), so the EC reliably leaves + * "preOS" mode even when the EC region is connected late. + */ + If (_REV >= 0x02) { + ADRD = 1 + } + } +#endif + /* Read requested temperature and check against EC error values */ Method (TSRD, 1, Serialized) { @@ -274,6 +348,9 @@ Device (EC0) Method (_Q03, 0, NotSerialized) { Printf ("EC: POWER BUTTON") +#ifdef EC_ENABLE_POWER_BUTTON + Notify (PWRB, 0x80) +#endif } // AC Connected @@ -461,6 +538,18 @@ Device (EC0) #ifdef EC_ENABLE_TBMC_DEVICE Notify (^CREC.TBMC, 0x80) #endif +#if CONFIG(EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS) +#if CONFIG(SOC_INTEL_COMMON) + If (^TBMD == 1) { + Notify (VBTN, 0xCC) + } Else { + Notify (VBTN, 0xCD) + } +#endif +#if CONFIG(SOC_AMD_COMMON) + Notify (VGBI, 0x81) +#endif +#endif #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) If (CondRefOf (\_SB.DPTC)) { \_SB.DPTC() @@ -667,4 +756,13 @@ Device (EC0) #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT #include "keyboard_backlight.asl" #endif + +#if CONFIG(EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS) +#if CONFIG(SOC_INTEL_COMMON) + #include "vbtn.asl" +#endif +#if CONFIG(SOC_AMD_COMMON) + #include "vgbi.asl" +#endif +#endif } diff --git a/src/ec/google/chromeec/acpi/vbtn.asl b/src/ec/google/chromeec/acpi/vbtn.asl new file mode 100644 index 00000000000..3bddc304def --- /dev/null +++ b/src/ec/google/chromeec/acpi/vbtn.asl @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* VGBS reports 0x40 when NOT in tablet mode. */ +/* Sent event 0xCC for tablet mode, 0xCD for laptop */ +/* Linux driver expects SMBIOS_ENCLOSURE_TYPE=SMBIOS_ENCLOSURE_CONVERTIBLE */ + +Device (VBTN) +{ + Name (_HID, "INT33D6") + Name (_DDN, "Tablet Virtual Buttons") + + Method (VBDL, 0) + { + } + + Method (VGBS) + { + If (^^RCTM == 1) { + Return (0x0) + } Else { + Return (0x40) + } + } + Method(_STA, 0) + { + Return (0xF) + } +} + +Device (VBTO) +{ + Name (_HID, "INT33D3") + Name (_CID, "PNP0C60") + Method (_STA, 0) + { + Return (0xF) + } +} diff --git a/src/ec/google/chromeec/acpi/vgbi.asl b/src/ec/google/chromeec/acpi/vgbi.asl new file mode 100644 index 00000000000..be71f11429b --- /dev/null +++ b/src/ec/google/chromeec/acpi/vgbi.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (CIND) +{ + Name (_HID, "AMD33D3") // _HID: Hardware ID + Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID + Method (_STA, 0, Serialized) // _STA: Status + { + Return (0x0F) + } +} + +Device (VGBI) +{ + Name (_HID, "AMD33D6") // _HID: Hardware ID + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (AMWF, 0, Serialized) + { + If (^^RCTM == 1) { + Return (0) + } Else { + Return (1) + } + } +} diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5b89dac265d..2dacf656bdc 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -816,8 +816,16 @@ int google_chromeec_reboot(enum ec_reboot_cmd type, uint8_t flags) void google_chromeec_ap_poweroff(void) { - if (ec_cmd_ap_shutdown(PLAT_EC)) - printk(BIOS_ERR, "Failed to power off the AP.\n"); + if (ec_cmd_ap_shutdown(PLAT_EC)) { + printk(BIOS_ERR, "Standard shutdown failed. Trying forced AP Off...\n"); + /* + * Fallback (2nd attempt): If the standard shutdown command fails, + * force a cold reboot with the 'AP OFF' flag. This is a more + * aggressive hardware-level trigger to ensure the system doesn't + * remain powered on in an undefined state. + */ + google_chromeec_reboot(EC_REBOOT_COLD_AP_OFF, 0); + } halt(); } @@ -1186,6 +1194,14 @@ bool google_chromeec_is_charger_present(void) EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)); } +/* This API checks if RTC event. */ +bool google_chromeec_is_rtc_event(void) +{ + /* Check if the Chrome EC has an active RTC event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)); +} + /* * Using below scenarios to conclude if device has a barrel charger attached. * +-----------+-----------------+------------------+---------------------------------+ @@ -1863,6 +1879,22 @@ bool google_chromeec_is_battery_present(void) return false; } +bool google_chromeec_is_battery_data_valid(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, ¶ms, &resp) == 0) { + /* Check if battery data is valid */ + if (resp.flags & EC_BATT_FLAG_INVALID_DATA) + return false; + } + + return true; +} + /* * Performs early power off. * @@ -1922,7 +1954,13 @@ static int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state) if (resp.full_capacity <= 0) return -1; - uint32_t soc = (uint32_t)resp.remaining_capacity * 100 / (uint32_t)resp.full_capacity; + /* + * Integer Ceiling Math Formula: (X + Y - 1) / Y + * This forces any fractional remainder to push up to the next integer. + */ + uint64_t numerator = ((uint64_t)resp.remaining_capacity * 100) + + (uint64_t)resp.full_capacity - 1; + uint32_t soc = (uint32_t)(numerator / (uint64_t)resp.full_capacity); /* Clamp the value to 100% (some fuel gauges report slight overflows) */ if (soc > 100) @@ -1955,6 +1993,73 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state) return ret; } +/* + * Reads remaining battery capacity. + * capacity: Pointer to store the remaining capacity in mAh. + * + * Return: 0 on success, -1 on failure. + */ +int google_chromeec_read_batt_remaining_capacity(uint32_t *capacity) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + /* Send command to Chrome EC to query dynamic battery parameters */ + if (ec_cmd_battery_get_dynamic(PLAT_EC, ¶ms, &resp) != 0) + return -1; + + /* Sanity check: Ensure remaining capacity is non-negative and valid */ + if (resp.remaining_capacity < 0) + return -1; + + *capacity = (uint32_t)resp.remaining_capacity; + + return 0; +} + +/* + * Query the EC for the Battery MISC Information. + * + * Sends a host command to the ChromeOS Embedded Controller to retrieve the status + * of the battery's charging field-effect transistor (CFET) at index 0 and battery + * status. + * + * Return: 0 on success, or -1 if the command fails or is + * unsupported by the current EC firmware version. + */ +int google_chromeec_get_battery_misc_info(struct ec_response_battery_get_misc_info *resp) +{ + const struct ec_params_battery_get_misc_info params = { + .index = 0 + }; + + struct chromeec_command cmd = { + .cmd_code = EC_CMD_BATTERY_GET_MISC_INFO, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(struct ec_response_battery_get_misc_info), + .cmd_data_out = resp, + .cmd_dev_index = 0, + }; + + int rv; + + rv = google_chromeec_command(&cmd); + + if (rv != 0 && (cmd.cmd_code == EC_RES_INVALID_COMMAND || + cmd.cmd_code == EC_RES_INVALID_PARAM)) { + printk(BIOS_INFO, "BATTERY_GET_CFET_STATUS not supported by EC.\n"); + return -1; + } else if (rv != 0) { + return -1; + } + + return 0; +} + /* * Set the RGB color of a specific LED on the Lightbar. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aadd51ff22f..9788f25b010 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -158,6 +158,14 @@ bool google_chromeec_is_usb_pd_attached(void); */ bool google_chromeec_is_charger_present(void); +/** + * Check if the Chrome EC has an active RTC event. + * + * @return true: if the RTC event is present + * false: if the RTC event is not present + */ +bool google_chromeec_is_rtc_event(void); + /** * Check if barrel charger is present. * @@ -480,6 +488,14 @@ bool google_chromeec_is_below_critical_threshold(void); */ bool google_chromeec_is_battery_present(void); +/** + * Check if battery data is valid. + * + * @return true: if the battery data is valid + * false: if the battery data is invalid + */ +bool google_chromeec_is_battery_data_valid(void); + /** * Determine if the UCSI stack is currently active. * @@ -548,6 +564,22 @@ void chipset_ioport_range(uint16_t *base, size_t *size); */ int google_chromeec_read_batt_state_of_charge(uint32_t *state); +/* + * Reads remaining battery capacity. + * capacity: Pointer to store the remaining capacity in mAh. + * + * Return: 0 on success, -1 on failure. + */ +int google_chromeec_read_batt_remaining_capacity(uint32_t *capacity); + +/* + * Query the EC for the Battery MISC Information. + * + * Return: 0 on success, or -1 if the command fails or is + * unsupported by the current EC firmware version. + */ +int google_chromeec_get_battery_misc_info(struct ec_response_battery_get_misc_info *resp); + /* * Set the RGB color of a specific LED on the Lightbar. * diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 8e0e9fee34e..372e63dc3ad 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -274,6 +274,11 @@ static void fill_ssdt_ps2_keyboard(const struct device *dev) !!(keybd.capabilities & KEYBD_CAP_SCRNLOCK_KEY), !!(keybd.capabilities & KEYBD_CAP_ASSISTANT_KEY), true); + + /* Windows drivers expect function-row-physmap under CKSC (no keymap). */ + if (!CONFIG(CHROMEOS)) + acpigen_ps2_keyboard_physmap_dsd("_SB.PCI0.LPCB.EC0.CREC.CKSC", + keybd.num_top_row_keys, ps2_action_keys); } static const char *ec_acpi_name(const struct device *dev) diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h index 89c2d11f4c3..a88e3045940 100644 --- a/src/ec/google/chromeec/ec_cmd_api.h +++ b/src/ec/google/chromeec/ec_cmd_api.h @@ -115,6 +115,14 @@ static inline int ec_cmd_fp_frame(CROS_EC_COMMAND_INFO *h, p->size); } +static inline int ec_cmd_fp_frame_v1(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_frame_v1 *p, + uint8_t *r) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_FRAME, 1, p, sizeof(*p), r, + p->size); +} + static inline int ec_cmd_fp_template(CROS_EC_COMMAND_INFO *h, const struct ec_params_fp_template *p, int size) @@ -122,6 +130,13 @@ static inline int ec_cmd_fp_template(CROS_EC_COMMAND_INFO *h, return CROS_EC_COMMAND(h, EC_CMD_FP_TEMPLATE, 0, p, size, NULL, 0); } +static inline int +ec_cmd_fp_template_v1(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_template_v1 *p, int size) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_TEMPLATE, 1, p, size, NULL, 0); +} + static inline int ec_cmd_fp_info_v2(CROS_EC_COMMAND_INFO *h, struct ec_response_fp_info_v2 *r, size_t resp_size) @@ -129,6 +144,13 @@ static inline int ec_cmd_fp_info_v2(CROS_EC_COMMAND_INFO *h, return CROS_EC_COMMAND(h, EC_CMD_FP_INFO, 2, NULL, 0, r, resp_size); } +static inline int ec_cmd_fp_info_v3(CROS_EC_COMMAND_INFO *h, + struct ec_response_fp_info_v3 *r, + size_t resp_size) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_INFO, 3, NULL, 0, r, resp_size); +} + /* * Section 2: EC interface functions that can be generated with the help * of template macros. @@ -273,6 +295,8 @@ _CROS_EC_CV_F_P(EC_CMD_BATTERY_CUT_OFF, 1, battery_cut_off_v1, battery_cutoff); _CROS_EC_C0_F(EC_CMD_BATTERY_CUT_OFF, battery_cut_off); _CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_DYNAMIC, 0, battery_get_dynamic, battery_dynamic_info, battery_dynamic_info); +_CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_DYNAMIC, 1, battery_get_dynamic_v1, + battery_dynamic_info, battery_dynamic_info_v1); _CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_STATIC, 0, battery_get_static, battery_static_info, battery_static_info); _CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_STATIC, 1, battery_get_static_v1, @@ -361,6 +385,8 @@ _CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, host_event_set_wake_mask, host_event_mask); _CROS_EC_C0_F_PF(EC_CMD_HOST_SLEEP_EVENT, host_sleep_event); _CROS_EC_C1_F_PF_RF(EC_CMD_HOST_SLEEP_EVENT, host_sleep_event); +_CROS_EC_C0_F_RF(EC_CMD_HOST_SLEEP_SIGNAL_TRANSITIONS, + host_sleep_signal_transitions); _CROS_EC_C0_F_PF_RF(EC_CMD_I2C_CONTROL, i2c_control); _CROS_EC_C0_F_PF_RF(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_passthru_protect); _CROS_EC_C0_F_RF(EC_CMD_KEYBOARD_FACTORY_TEST, keyboard_factory_test); @@ -418,6 +444,7 @@ _CROS_EC_C0_F_PF_RF(EC_CMD_REGULATOR_IS_ENABLED, regulator_is_enabled); _CROS_EC_C0_F_PF(EC_CMD_REGULATOR_SET_VOLTAGE, regulator_set_voltage); _CROS_EC_C0_F_PF_RF(EC_CMD_RGBKBD, rgbkbd); _CROS_EC_C0_F_RF(EC_CMD_ROLLBACK_INFO, rollback_info); +_CROS_EC_C1_F_RF(EC_CMD_ROLLBACK_INFO, rollback_info); _CROS_EC_CV_F_R(EC_CMD_RTC_GET_ALARM, 0, rtc_get_alarm, rtc); _CROS_EC_CV_F_R(EC_CMD_RTC_GET_VALUE, 0, rtc_get_value, rtc); _CROS_EC_CV_F_P(EC_CMD_RTC_SET_ALARM, 0, rtc_set_alarm, rtc); @@ -461,6 +488,10 @@ _CROS_EC_C0_F_PF_RF(EC_CMD_VSTORE_READ, vstore_read); _CROS_EC_C0_F_PF(EC_CMD_VSTORE_WRITE, vstore_write); _CROS_EC_C0_F_PF(EC_CMD_UCSI_PPM_SET, ucsi_ppm_set); _CROS_EC_C0_F_PF(EC_CMD_UCSI_PPM_GET, ucsi_ppm_get); +_CROS_EC_C0_F_PF(EC_CMD_FP_VENDOR, fp_vendor); +_CROS_EC_C0_F_RF(EC_CMD_FP_ASCP_CLAIM, fp_ascp_claim); +_CROS_EC_C0_F_PF(EC_CMD_FP_ASCP_ESTABLISH, fp_ascp_establish); +_CROS_EC_C0_F_PF(EC_CMD_ENTER_BOOTLOADER, enter_bootloader); #ifdef __cplusplus } diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 1dbb7115f61..a853b33c808 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -763,10 +763,12 @@ enum ec_status { } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); #ifdef CONFIG_EC_HOST_CMD +#ifdef CONFIG_ZEPHYR /* * Make sure Zephyre uses the same status codes. */ #include +#endif BUILD_ASSERT((uint16_t)EC_RES_SUCCESS == (uint16_t)EC_HOST_CMD_SUCCESS); BUILD_ASSERT((uint16_t)EC_RES_INVALID_COMMAND == @@ -934,6 +936,9 @@ enum host_event_code { /* Body detect (lap/desk) change event */ EC_HOST_EVENT_BODY_DETECT_CHANGE = 33, + /* New console logs since last snapshot */ + EC_HOST_EVENT_CONSOLE_LOGS = 34, + /* * Only 64 host events are supported. This enum uses 1-based counting so * it can skip 0 (NONE), so the last legal host event number is 64. @@ -981,6 +986,7 @@ enum host_event_code { [EC_HOST_EVENT_WOV] = "WOV", \ [EC_HOST_EVENT_INVALID] = "INVALID", \ [EC_HOST_EVENT_BODY_DETECT_CHANGE] = "BODY_DETECT_CHANGE", \ + [EC_HOST_EVENT_CONSOLE_LOGS] = "CONSOLE_LOGS", \ } /* clang-format on */ @@ -1780,6 +1786,10 @@ enum ec_feature_code { * The EC supports a hybrid boost charger */ EC_FEATURE_CHARGER_HYBRID_POWER_BOOST = 57, + /* + * Support signaling new console logs via host event + */ + EC_FEATURE_CONSOLE_LOG_EVENT = 58, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2533,6 +2543,14 @@ struct lightbar_params_v2_colors { struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; +struct lightbar_params_v3 { + /* + * Number of LEDs reported by the EC. + * May be less than the actual number of LEDs in the lightbar. + */ + uint8_t reported_led_num; +} __ec_todo_packed; + /* Lightbar program. */ #define EC_LB_PROG_LEN 192 struct lightbar_program { @@ -2540,6 +2558,17 @@ struct lightbar_program { uint8_t data[EC_LB_PROG_LEN]; } __ec_todo_unpacked; +/* + * Lightbar program for large sequences. Sequences are sent in pieces, with + * increasing offset. The sequences are still limited by the amount reserved in + * EC RAM. + */ +struct lightbar_program_ex { + uint8_t size; + uint16_t offset; + uint8_t data[0]; +} __ec_todo_packed; + struct ec_params_lightbar { uint8_t cmd; /* Command (see enum lightbar_command) */ union { @@ -2586,6 +2615,7 @@ struct ec_params_lightbar { struct lightbar_params_v2_colors set_v2par_colors; struct lightbar_program set_program; + struct lightbar_program_ex set_program_ex; }; } __ec_todo_packed; @@ -2613,6 +2643,8 @@ struct ec_response_lightbar { struct lightbar_params_v2_thresholds get_params_v2_thlds; struct lightbar_params_v2_colors get_params_v2_colors; + struct lightbar_params_v3 get_params_v3; + struct __ec_todo_unpacked { uint32_t num; uint32_t flags; @@ -2670,6 +2702,8 @@ enum lightbar_command { LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, + LIGHTBAR_CMD_GET_PARAMS_V3 = 34, + LIGHTBAR_CMD_SET_PROGRAM_EX = 35, LIGHTBAR_NUM_CMDS, }; @@ -2714,6 +2748,7 @@ enum ec_led_colors { EC_LED_COLOR_YELLOW, EC_LED_COLOR_WHITE, EC_LED_COLOR_AMBER, + EC_LED_COLOR_MAGENTA, EC_LED_COLOR_COUNT, }; @@ -2999,6 +3034,7 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_BMI220 = 29, MOTIONSENSE_CHIP_CM32183 = 30, MOTIONSENSE_CHIP_VEML3328 = 31, + MOTIONSENSE_CHIP_CM36781 = 32, MOTIONSENSE_CHIP_MAX, }; @@ -5313,6 +5349,17 @@ struct ec_response_s0ix_cnt { uint32_t s0ix_counter; } __ec_align4; +/*****************************************************************************/ +/* Ask the EC for sleep_signal_transitions without needing to send a + * HOST_SLEEP_EVENT command, which this command is related to. + * Note: EC_CMD_CONSOLE_PRINT has value 0x00AC, so skip over it. + */ +#define EC_CMD_HOST_SLEEP_SIGNAL_TRANSITIONS 0x00AD + +struct ec_response_host_sleep_signal_transitions { + uint32_t sleep_signal_transitions; +} __ec_align4; + /*****************************************************************************/ /* Smart battery pass-through */ @@ -5849,6 +5896,16 @@ struct ec_params_get_panic_info_v1 { uint8_t preserve_old_hostcmd_flag; } __ec_align1; +struct ec_params_get_panic_info_v2 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; + + /* Read panic_data struct from this offset. + * Signal end of data with empty success. + */ + uint16_t read_offset; +} __ec_align1; + /*****************************************************************************/ /* * Special commands @@ -5987,6 +6044,109 @@ struct ec_params_enter_bootloader { uint8_t mode; } __ec_align1; +#define EC_CMD_HOSTCMD_WATCHDOG_INFO 0x00E3 + +struct ec_params_hostcmd_watchdog_info { + uint8_t reset_stats; +} __ec_align1; + +struct ec_response_hostcmd_watchdog_info { + /* Static watchdog info */ + int32_t watchdog_period_ms; + int32_t watchdog_warning_period_ms; + int32_t watchdog_reload_period_nominal_ms; + /* Dynamic watchdog stats */ + int32_t watchdog_reload_period_max_ms; + int64_t watchdog_reload_period_max_ts_ms; + uint32_t watchdog_reload_count; + int64_t watchdog_stats_elapsed_ms; +} __ec_align4; + +#define EC_THREAD_INFO_MAX_COUNT 32 +#define EC_THREAD_INFO_NAME_SIZE 16 + +#define EC_CMD_THREAD_INFO_LIST 0x00E4 + +struct ec_response_thread_info_list { + /* Total number of threads found, or EC_THREAD_INFO_MAX_COUNT if it + * exceeds the limit. + */ + uint32_t thread_count; + uint32_t thread_ids[EC_THREAD_INFO_MAX_COUNT]; +} __ec_align4; + +#define EC_CMD_THREAD_INFO_DETAIL 0x00E5 + +#define EC_THREAD_INFO_DETAIL_STACK_VALID \ + BIT(0) /* CONFIG_THREAD_STACK_INFO \ + */ +#define EC_THREAD_INFO_DETAIL_RUNTIME_USAGE_VALID \ + BIT(1) /* CONFIG_SCHED_THREAD_USAGE */ +#define EC_THREAD_INFO_DETAIL_USAGE_ANALYSIS_VALID \ + BIT(2) /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ +#define EC_THREAD_INFO_DETAIL_NAME_VALID BIT(3) /* CONFIG_THREAD_NAME */ +#define EC_THREAD_INFO_DETAIL_PC_VALID BIT(4) +#define EC_THREAD_INFO_DETAIL_LR_VALID BIT(5) +#define EC_THREAD_INFO_DETAIL_SP_VALID BIT(6) + +struct ec_params_thread_info_detail { + uint32_t thread_id; +} __ec_align4; + +/* + * These commands are ONLY applicable to Zephyr threads. + */ +struct ec_response_thread_info_detail { + /* Metadata */ + uint64_t timestamp_us; /* System uptime when stats were collected */ + uint32_t valid_flags; /* See EC_THREAD_INFO_DETAIL_*_VALID flags */ + + /* Name (Only valid if EC_THREAD_INFO_DETAIL_NAME_VALID is set). + * Guaranteed to be null-terminated. + */ + char name[EC_THREAD_INFO_NAME_SIZE]; + + /* Basic information */ + uint32_t entry_point; /* Thread entry point function address */ + uint32_t timeout_us; + /* + * Remaining timeout in us, 0xffffffff if forever, + * 0 if none + */ + + uint16_t user_options; /* From k_thread->base.user_options */ + int8_t prio; /* From k_thread->base.prio */ + uint8_t thread_state; /* From k_thread->base.thread_state */ + uint8_t is_idle; /* 1 if per-CPU idle thread, 0 otherwise */ + uint8_t is_current; /* 1 if thread is current, 0 otherwise */ + uint8_t reserved[2]; /* Padding for alignment */ + + /* Stack usage (Only valid if EC_THREAD_INFO_DETAIL_STACK_VALID is set) + */ + uint32_t stack_cur; + uint32_t stack_max; + uint32_t stack_size; + + /* Timing (Only valid if EC_THREAD_INFO_DETAIL_RUNTIME_USAGE_VALID is + * set) + */ + uint32_t execution_time_us; + + /* Analysis (Only valid if EC_THREAD_INFO_DETAIL_USAGE_ANALYSIS_VALID is + * set) + */ + uint32_t window_peak_us; + uint32_t window_avg_us; + + /* CPU scheduling */ + uint32_t pending_on; /* Address of object thread is blocked on */ + + /* CPU registers (Valid flags: EC_THREAD_INFO_DETAIL_PC_VALID, etc.) */ + uint32_t pc; + uint32_t lr; + uint32_t sp; +} __ec_align4; + /*****************************************************************************/ /* * PD commands @@ -6940,6 +7100,14 @@ struct ec_response_rollback_info { int32_t rw_rollback_version; } __ec_align4; +struct ec_response_rollback_info_v1 { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; + uint8_t is_secret_inited; + uint8_t reserved[3]; +} __ec_align4; + /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -8369,6 +8537,12 @@ struct ec_params_fp_passthru { #define FP_MODE_RESET_SENSOR BIT(7) /* Sensor maintenance for dead pixels. */ #define FP_MODE_SENSOR_MAINTENANCE BIT(8) +/* Encrypt template. */ +#define FP_MODE_ENCRYPT_TEMPLATE BIT(9) +/* Decrypt template. */ +#define FP_MODE_DECRYPT_TEMPLATE BIT(10) +/* Disable template update. */ +#define FP_MODE_MATCH_NO_TEMPLATE_UPDATE BIT(11) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE BIT(31) @@ -8376,9 +8550,16 @@ struct ec_params_fp_passthru { (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \ FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \ - FP_MODE_DONT_CHANGE) + FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE | \ + FP_MODE_MATCH_NO_TEMPLATE_UPDATE | FP_MODE_DONT_CHANGE) #define FP_MODES_WITH_AUTHENTICATION (FP_MODE_ENROLL_SESSION | FP_MODE_MATCH) +#define FP_MODES_CRYPTO_IN_PROGRESS \ + (FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE) +#define FP_MODES_TEMPLATE_OPERATION \ + (FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | FP_MODE_ENCRYPT_TEMPLATE | \ + FP_MODE_DECRYPT_TEMPLATE) /* Capture types defined in bits [30..26] */ #define FP_MODE_CAPTURE_TYPE_SHIFT 26 @@ -8386,6 +8567,7 @@ struct ec_params_fp_passthru { /** * enum fp_capture_type - Specifies the "mode" when capturing images. * + * @FP_CAPTURE_TYPE_INVALID: an invalid capture type * @FP_CAPTURE_VENDOR_FORMAT: Capture 1-3 images and choose the best quality * image (produces 'frame_size' bytes) * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x @@ -8402,7 +8584,9 @@ struct ec_params_fp_passthru { * @note This enum must remain ordered, if you add new values you must ensure * that FP_CAPTURE_TYPE_MAX is still the last one. */ +/* LINT.IfChange */ enum fp_capture_type { + FP_CAPTURE_TYPE_INVALID = -1, FP_CAPTURE_VENDOR_FORMAT = 0, FP_CAPTURE_DEFECT_PXL_TEST = 1, FP_CAPTURE_ABNORMAL_TEST = 2, @@ -8414,6 +8598,9 @@ enum fp_capture_type { FP_CAPTURE_RESET_TEST = 20, FP_CAPTURE_TYPE_MAX, }; +/* LINT.ThenChange(/test/fpsensor_utils.cc, + * /zephyr/test/fingerprint/task/src/fpsensor_debug.cc) + */ /* The maximum number of capture types in enum fp_capture_type */ #define FP_MAX_CAPTURE_TYPES 9 @@ -8539,6 +8726,31 @@ struct ec_response_fp_info_v2 { } __ec_align4; BUILD_ASSERT(sizeof(struct ec_response_fp_info_v2) == 36); +struct fp_image_frame_params_v2 { + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t image_data_offset_bytes; /**< Byte offset of image buffer */ + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + /** Type of image capture from enum fp_capture_type. */ + uint8_t fp_capture_type; + uint8_t reserved; /**< padding for alignment */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_image_frame_params_v2) == 20); + +struct ec_response_fp_info_v3 { + /* Sensor identification */ + struct fp_sensor_info sensor_info; + /* Template/finger current information */ + struct fp_template_info template_info; + /* fingerprint image frame parameters */ + struct fp_image_frame_params_v2 + image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; +BUILD_ASSERT(sizeof(struct ec_response_fp_info_v3) == 36); + /* Get the last captured finger frame or a template content */ #define EC_CMD_FP_FRAME 0x0404 @@ -8591,6 +8803,33 @@ struct ec_params_fp_frame { uint32_t size; } __ec_align4; +/* + * FP_FRAME commands: + * + * - FP_FRAME_GET_RAW_IMAGE command can be used to get raw image from sensor. + * This command works only when the system is not locked. The template index + * is ignored. + * - FP_FRAME_ENCRYPT_TEMPLATE command is used to request encryption of the + * template with provided template index. Offset and size are ignored. + * The encryption process is considered as started only after EC_SUCCESS + * was returned. + * - FP_FRAME_GET_ENCRYPTED_TEMPLATE command is used to obtain the encrypted + * template. + */ +enum fp_frame_cmd { + FP_FRAME_GET_RAW_IMAGE = 0, + FP_FRAME_ENCRYPT_TEMPLATE = 1, + FP_FRAME_GET_ENCRYPTED_TEMPLATE = 2, +}; + +struct ec_params_fp_frame_v1 { + uint8_t cmd; + uint8_t reserved; + uint16_t index; + uint32_t offset; + uint32_t size; +} __ec_align4; + /* Load a template into the MCU */ #define EC_CMD_FP_TEMPLATE 0x0405 @@ -8603,6 +8842,27 @@ struct ec_params_fp_template { uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; } __ec_align4; +/* + * FP_TEMPLATE commands: + * + * - FP_TEMPLATE_LOAD command is used to copy part of the template to FPMCU + * buffer. + * - FP_TEMPLATE_DECRYPT command starts template decryption. + * - FP_TEMPLATE_GET_RESULT command is used to check decryption result. + */ +enum fp_template_cmd { + FP_TEMPLATE_LOAD = 0, + FP_TEMPLATE_DECRYPT = 1, + FP_TEMPLATE_GET_RESULT = 2, +}; + +struct ec_params_fp_template_v1 { + uint32_t offset; + uint32_t size; + uint8_t cmd; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + /* Clear the current fingerprint user context and set a new one */ #define EC_CMD_FP_CONTEXT 0x0406 @@ -8663,6 +8923,8 @@ struct ec_params_fp_seed { #define FP_CONTEXT_USER_ID_SET BIT(3) /* The operation authentication challenge was generated */ #define FP_AUTH_CHALLENGE_SET BIT(4) +/* Encrypted template is available */ +#define FP_ENCRYPTED_TEMPLATE_READY BIT(5) struct ec_response_fp_encryption_status { /* Used bits in encryption engine status */ @@ -8794,6 +9056,50 @@ struct ec_response_fp_sign_match { uint8_t signature[FP_MAC_LENGTH]; } __ec_align4; +/* + * Fingerprint ASCP claim command. + * + */ +#define EC_CMD_FP_ASCP_CLAIM 0x0420 + +/* + * ECC public key with no point compression as defined in + * ANSI X9.62 section 4.3.6 (0x04||x||y), P256v1 curve. + */ +#define FP_ASCP_KEY_SIZE 65 +/* ECC signature, P256v1 curve, P1363 encoding (r||s) */ +#define FP_ASCP_SIGNATURE_SIZE 64 +/* SHA256 */ +#define FP_ASCP_HASH_SIZE 32 + +struct ec_response_fp_ascp_claim { + /* Model public key. */ + uint8_t pk_m[FP_ASCP_KEY_SIZE]; + /* Model public key signature. */ + uint8_t s_goog[FP_ASCP_SIGNATURE_SIZE]; + /* Device public key. */ + uint8_t pk_d[FP_ASCP_KEY_SIZE]; + /* Device public key signature (signed using model key). */ + uint8_t s_m[FP_ASCP_SIGNATURE_SIZE]; + /* Ephemeral public key used in ECDH procedure. */ + uint8_t pk_f[FP_ASCP_KEY_SIZE]; + /* SHA256 hash of the firmware. */ + uint8_t h_f[FP_ASCP_HASH_SIZE]; + /* Signature of the SHA256( 0xC001 || h_f || pk_f) using device key. */ + uint8_t s_d[FP_ASCP_SIGNATURE_SIZE]; +} __ec_align4; + +/* + * Fingerprint ASCP establish command. + * + */ +#define EC_CMD_FP_ASCP_ESTABLISH 0x0421 + +struct ec_params_fp_ascp_establish { + /* TA's ephemeral public key. */ + uint8_t pk_g[FP_ASCP_KEY_SIZE]; +} __ec_align4; + /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ @@ -8908,6 +9214,38 @@ struct ec_response_battery_static_info_v2 { char chemistry[SBS_MAX_STR_OBJ_SIZE]; } __ec_align4; +/** + * struct ec_response_battery_static_info_v3 - hostcmd v3 battery static info + * + * Extends struct ec_response_battery_static_info_v2 with + * manuf_info. + * + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer: battery manufacturer string + * @device_name: battery model string + * @serial: battery serial number string + * @chemistry: battery type string + * @manuf_info: battery manufacture info string (vendor specific) + * @manuf_year: battery manufacture year + * @manuf_month: battery manufacture month + * @manuf_day: battery manufacture day + */ +struct ec_response_battery_static_info_v3 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; + char manuf_info[SBS_MAX_STR_OBJ_SIZE]; + uint16_t manuf_year; + uint8_t manuf_month; + uint8_t manuf_day; +} __ec_align4; + /* * Get battery dynamic information, i.e. information that is likely to change * every time it is read. @@ -8942,6 +9280,29 @@ struct ec_response_battery_dynamic_info { int16_t desired_current; } __ec_align2; +/** + * struct ec_response_battery_dynamic_info_v1 - Battery dynamic info response + * (v1) + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + * @temperature: Battery temperature (dK) + */ +struct ec_response_battery_dynamic_info_v1 { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; + uint16_t temperature; +} __ec_align2; + /* * Control charger chip. Used to control charger chip on the peripheral. */ @@ -8999,6 +9360,29 @@ struct ec_response_get_boot_time { */ #define EC_CMD_ENABLE_OFFMODE_HEARTBEAT 0x0606 +/* Get battery misc info */ +#define EC_CMD_BATTERY_GET_MISC_INFO 0x0607 + +/** + * struct ec_params_battery_get_misc_info - Battery misc info parameters + * @index: Battery index. + */ +struct ec_params_battery_get_misc_info { + uint8_t index; +} __ec_align1; + +/** + * struct ec_response_battery_get_misc_info - Battery misc info response + * @cfet_status: status of C-FET. 1: disabled, 0: enabled, -1: error. + * @battery_status: Battery status register. + * @dfet_status: status of D-FET. 0: disconnected, 1: not disconnected, -1: + * error. + */ +struct ec_response_battery_get_misc_info { + int32_t cfet_status; + uint32_t battery_status; + int32_t dfet_status; +} __ec_align4; /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 439ede5a207..63769489882 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -41,6 +41,10 @@ config H8_FN_CTRL_SWAP The main use-case for this Kconfig option is to enable Fn-Ctrl swap without using any runtime configurable option backends (e.g. CMOS). +config H8_HAS_BAT_CHARGE_BEHAVIOUR + bool + default n + config H8_HAS_BAT_THRESHOLDS_IMPL bool default n @@ -61,6 +65,10 @@ config H8_HAS_LEDLOGO bool default n +config H8_HAS_FNLOCK_LED + bool + default n + config THINKPADEC_HKEY_EISAID string default "IBM0068" diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 392a8ed441b..882068db83c 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -32,8 +32,7 @@ Field (ERAM, ByteAcc, NoLock, Preserve) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset(0xa0), - , 15, - BAMA, 1, + BAMA, 16, /* 16-bit read required; 8-bit access at 0xa1 returns garbage! */ } /* PAGE == 0x02 */ @@ -95,8 +94,9 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) Local0 = 0 - ^BPAG(Arg0 | 1) + ^BPAG(Arg0 | 1) /* Battery static information */ Local1 = BAMA + Local1 >>= 0x0f ^BPAG(Arg0) /* Battery dynamic information */ /* @@ -133,6 +133,10 @@ Method(BSTA, 4, NotSerialized) Arg1 [0] = Local0 + /* + * Values are in mAh but we want mWh. + * This is required to match PowerUnit! + */ if (Local1) { Arg1 [2] = BARC * 10 Local2 *= BAVO @@ -149,9 +153,9 @@ Method(BSTA, 4, NotSerialized) Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) - ^BPAG(1 | Arg1) /* Battery 0 static information */ - Arg0 [0] = BAMA ^ 1 + ^BPAG(1 | Arg1) /* Battery static information */ Local0 = BAMA + Local0 >>= 0x0f ^BPAG(Arg1) Local2 = BAFC ^BPAG(Arg1 | 2) @@ -163,6 +167,7 @@ Method(BINF, 2, Serialized) Local2 *= 10 } + Arg0 [0] = Local0 ^ 1 // PowerUnit (mWh/mAh) Arg0 [1] = Local1 // Design Capacity Arg0 [2] = Local2 // Last full charge capacity Arg0 [4] = BADV // Design Voltage diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index fe39c197618..b47699f5ffc 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -17,6 +17,9 @@ Device(EC) HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x0d), + , 6, + KBBL, 2, /* Keyboard Backlight */ Offset (0x0F), , 7, TBSW, 1, /* Tablet mode switch */ @@ -42,7 +45,7 @@ Device(EC) WWEB, 1, Offset (0x3B), , 1, - KBLT, 1, /* Keyboard Light */ + KBLT, 1, /* Keyboard Light (ThinkLight) */ , 2, USPW, 1, /* USB Power enable */ Offset (0x48), @@ -156,6 +159,11 @@ Device(EC) /* AC status change: not present */ Method(_Q27, 0, NotSerialized) { + #if CONFIG(H8_HAS_BAT_CHARGE_BEHAVIOUR) + /* Reset battery charge behaviour on AC detach */ + \_SB.PCI0.LPCB.EC.HKEY.RBCB(0) + #endif + Notify (AC, 0x80) EVNT = 0x50 \PNOT() diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 1268e22b945..4991c6d1399 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -5,6 +5,7 @@ Device (HKEY) /* Generated by ssdt.c */ External (\HBDC, IntObj) External (\HWAN, IntObj) + External (\HKLT, IntObj) External (\HKBL, IntObj) External (\HUWB, IntObj) @@ -26,6 +27,9 @@ Device (HKEY) /* Device enabled. */ Name (EN, 0) + /* Hotkey control state, read by thinkpad_acpi hotkey_status_get(). */ + Name (DHKC, 0) + Method (_STA, 0, NotSerialized) { Return (0x0F) @@ -69,6 +73,7 @@ Device (HKEY) /* Enable/disable all events. */ Method (MHKC, 1, NotSerialized) { + DHKC = Arg0 If (Arg0) { EMSK = DHKN ETAB = Ones @@ -235,30 +240,34 @@ Device (HKEY) /* * Argument is unused. * Returns the current state: - * Bit 9: Backlight HW present - * Bit 0-1: Brightness level + * Bit 9: Keyboard backlight HW present + * Bit 4: ThinkLight state + * Bit 0-1: Keyboard backlight brightness level */ Method (MLCG, 1) { + Local0 = 0x0 + If (HKBL) { - Local0 = 0x200 - /* FIXME: Support 2bit brightness control */ - Local0 |= \_SB.PCI0.LPCB.EC.KBLT - Return (Local0) - } Else { - Return (0) + Local0 |= 0x200 + Local0 |= \_SB.PCI0.LPCB.EC.KBBL & 0x3 } + + If (HKLT) { + Local0 |= (\_SB.PCI0.LPCB.EC.KBLT & 0x1) << 4 + } + + Return (Local0) } /* * Set the current state: - * Bit 0-1: Brightness level + * Bit 0-1: Keyboard backlight brightness level */ Method (MLCS, 1) { If (HKBL) { - /* FIXME: Support 2bit brightness control */ - \_SB.PCI0.LPCB.EC.WWEB = Arg0 & 1 + \_SB.PCI0.LPCB.EC.KBBL = Arg0 & 0x3 } } @@ -304,6 +313,10 @@ Device (HKEY) } } + #if CONFIG(H8_HAS_BAT_CHARGE_BEHAVIOUR) + #include "thinkpad_bat_charge_behaviour.asl" + #endif + #if CONFIG(H8_HAS_BAT_THRESHOLDS_IMPL) #include "thinkpad_bat_thresholds.asl" #endif diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_charge_behaviour.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_charge_behaviour.asl new file mode 100644 index 00000000000..57ffa2d0544 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_charge_behaviour.asl @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Charge behaviour control */ +#define DISABLE_INHIBITCHARGE 0x1 +#define ENABLE_INHIBITCHARGE 0x2 +#define DISABLE_FORCEDISCHARGE 0x3 +#define ENABLE_FORCEDISCHARGE 0x4 + +/* Return values for BDSG method */ +#define FORCEDISCHARGE_SUPPORTED 0x100 +#define FORCEDISCHARGE_ACTIVE 0x001 + +/* Return values for BICG method */ +#define INHIBITCHARGE_SUPPORTED 0x20 +#define INHIBITCHARGE_ACTIVE 0x01 + +/* EC Registers */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x0f), + B0IC, 1, /* BAT0 inhibit-charge active */ + B1IC, 1, /* BAT1 inhibit-charge active */ + B0FD, 1, /* BAT0 force-discharge active */ + B1FD, 1, /* BAT1 force-discharge active */ + Offset (0x21), + BAET, 16, /* Effective time (for inhibit-charge) */ + Offset (0xb4), + B0CB, 8, /* BAT0 charge behaviour control */ + Offset (0xb5), + B1CB, 8, /* BAT1 charge behaviour control */ +} + +/* + * Set state for force-discharge: + * Bit 8-9: Battery ID (0x1=BAT0; 0x2=BAT1) + * Bit 1: Break on AC attach + * Bit 0: Enable or disable + */ +Method (BDSS, 1, NotSerialized) +{ + Local0 = Arg0 & 0x1 // New state + Local1 = (Arg0 >> 8) & 0x3 // Battery ID + Local2 = (Arg0 >> 1) & 0x1 // Break on AC attach + Local3 = 0x0 // EC RAM value + + If (Local0) + { + /* + * Silently ignore it if AC is not attached. + * This should match stock BIOS behaviour. + */ + If (!HPAC) + { + Return (0x0) + } + + Local3 = ENABLE_FORCEDISCHARGE + } + Else + { + Local3 = DISABLE_FORCEDISCHARGE + } + + /* + * "Break on AC attach" is not supported by modern ECs. + * It's not used by thinkpad_acpi, return error if requested. + * Intentionally unsupported to match stock BIOS behaviour. + */ + If (!Local2) + { + /* BAT0 */ + If (Local1 == 1) + { + B0CB = Local3 + Return (0x0) + } + + /* BAT1 */ + If (Local1 == 2) + { + B1CB = Local3 + Return (0x0) + } + } + + Return (1 << 31) +} + +/* + * Argument: 0x1 for BAT0; 0x2 for BAT1 + * Returns the current state for force-discharge: + * Bit 8: Feature supported + * Bit 0: Currently active + */ +Method (BDSG, 1, NotSerialized) +{ + Local0 = 0x0 + Local1 = 0x0 + Local2 = 0x0 + + /* BAT0 */ + If (Arg0 == 1) + { + Local0 = B0PR + Local1 = B0FD + } + /* BAT1 */ + ElseIf (Arg0 == 2) + { + Local0 = B1PR + Local1 = B1FD + } + Else + { + Return (1 << 31) + } + + If (Local0) + { + Local2 |= FORCEDISCHARGE_SUPPORTED + + If (Local1) + { + Local2 |= FORCEDISCHARGE_ACTIVE + } + } + + Return (Local2) +} + +/* + * Set state for inhibit-charge: + * Bit 8-23: Effective time in minutes (0xffff indicates forever) + * Bit 4-5: Battery ID (0x1=BAT0; 0x2=BAT1) + * Bit 0: Enable or disable + */ +Method (BICS, 1, NotSerialized) +{ + Local0 = Arg0 & 0x1 // New state + Local1 = (Arg0 >> 4) & 0x3 // Battery ID + Local2 = (Arg0 >> 8) & 0xffff // Effective time + Local3 = 0x0 // EC RAM value + Local4 = 0x0 + + If (Local2 != 0xffff) + { + Local4 = Local2 >> 8 + } + + /* Only allow effective time <256 minutes (1-byte) or 0xffff. */ + If (Local4 == 0x0) + { + If (Local0) + { + Local3 = ENABLE_INHIBITCHARGE + } + Else + { + Local3 = DISABLE_INHIBITCHARGE + } + + /* BAT0 */ + If (Local1 == 1) + { + BAET = Local2 + B0CB = Local3 + Return (0x0) + } + + /* BAT1 */ + If (Local1 == 2) + { + BAET = Local2 + B1CB = Local3 + Return (0x0) + } + } + + Return (1 << 31) +} + +/* + * Argument: 0x1 for BAT0; 0x2 for BAT1 + * Returns the current state for inhibit-charge: + * Bit 5: Feature supported + * Bit 0: Currently active + */ +Method (BICG, 1, NotSerialized) +{ + Local0 = 0x0 + Local1 = 0x0 + Local2 = 0x0 + + /* BAT0 */ + If (Arg0 == 1) + { + Local0 = B0PR + Local1 = B0IC + } + /* BAT1 */ + ElseIf (Arg0 == 2) + { + Local0 = B1PR + Local1 = B1IC + } + Else + { + Return (1 << 31) + } + + If (Local0) + { + Local2 |= INHIBITCHARGE_SUPPORTED + + If (Local1) + { + Local2 |= INHIBITCHARGE_ACTIVE + } + } + + Return (Local2) +} + +/* + * RBCB - ResetBatteryChargeBehaviour, implemented for _Q27 method in ec.asl. + * Argument reserved for future extension: AC attached (1) or detached (0) + */ +Method (RBCB, 1, NotSerialized) +{ + /* AC detach */ + If (!Arg0) + { + /* BAT0: Disable force-discharge */ + BDSS(0x100) + + /* BAT1: Disable force-discharge */ + BDSS(0x200) + } +} diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 0e4b11e7532..4c872c73ea4 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -29,9 +29,10 @@ struct ec_lenovo_h8_config { u8 evente_enable; u8 eventf_enable; - u8 has_keyboard_backlight; - u8 has_power_management_beeps; - u8 has_uwb; + bool has_thinklight; + bool has_keyboard_backlight; + bool has_power_management_beeps; + bool has_uwb; u8 bdc_gpio_num; u8 bdc_gpio_lvl; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 1ea3ccfa405..2148ba4f495 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -67,18 +67,30 @@ static void h8_charge_priority(enum battery battery) static void h8_sticky_fn(int on) { - if (on) + if (on) { ec_set_bit(0x0, 3); - else + if (CONFIG(H8_HAS_FNLOCK_LED)) + ec_set_bit(0x3, 4); + } else { ec_clr_bit(0x0, 3); + if (CONFIG(H8_HAS_FNLOCK_LED)) + ec_clr_bit(0x3, 4); + } } -static void f1_to_f12_as_primary(int on) +/* + * Stock BIOS uses bits 2-3 in 0x09 for this option. + * Bit 3 in 0x3b is only used by physical Fn+Esc toggle! + */ +static void h8_f1_to_f12_as_primary(int on) { - if (on) - ec_set_bit(0x3b, 3); - else - ec_clr_bit(0x3b, 3); + if (on) { + ec_set_bit(0x09, 2); + ec_clr_bit(0x09, 3); + } else { + ec_set_bit(0x09, 3); + ec_clr_bit(0x09, 2); + } } static u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) @@ -241,6 +253,7 @@ static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val; + u8 backlight; u8 beepmask0, beepmask1, reg8; dev->ops = &h8_dev_ops; @@ -254,11 +267,20 @@ static void h8_enable(struct device *dev) reg8 |= H8_CONFIG0_TC_ENABLE; ec_write(H8_CONFIG0, reg8); + /* Default to both keyboard illumination devices */ + backlight = get_uint_option("backlight", 0) & 0x3; + + /* + * Disable keyboard backlight if: + * - Non-backlit hardware is physically installed -or- + * - "Thinklight only" or "None" is selected as keyboard illumination + */ + if (conf->has_keyboard_backlight) + conf->has_keyboard_backlight = (ec_read(0x34) & 0x40) && !(backlight & 0x2); + reg8 = conf->config1; - if (conf->has_keyboard_backlight) { - /* Default to both backlights */ - reg8 = (reg8 & 0xf3) | ((get_uint_option("backlight", 0) & 0x3) << 2); - } + if (conf->has_thinklight || conf->has_keyboard_backlight) + reg8 = (reg8 & 0xf3) | (backlight << 2); ec_write(H8_CONFIG1, reg8); ec_write(H8_CONFIG2, conf->config2); ec_write(H8_CONFIG3, conf->config3); @@ -268,6 +290,8 @@ static void h8_enable(struct device *dev) * (Without this warm reboot leaves LEDs off) */ ec_write(H8_LED_CONTROL, H8_LED_CONTROL_ON | H8_LED_CONTROL_POWER_LED); + if (CONFIG(H8_HAS_LEDLOGO)) + ec_write(H8_LED_CONTROL, H8_LED_CONTROL_ON | H8_LED_CONTROL_LOGO_LED); beepmask0 = conf->beepmask0; beepmask1 = conf->beepmask1; @@ -338,7 +362,7 @@ static void h8_enable(struct device *dev) h8_sticky_fn(get_uint_option("sticky_fn", 0)); if (CONFIG(H8_HAS_PRIMARY_FN_KEYS)) - f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1)); + h8_f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1)); h8_charge_priority(get_uint_option("first_battery", PRIMARY_BATTERY)); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 88d7b07136f..9b71f2994af 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -43,6 +43,7 @@ void h8_mb_init(void); #define H8_CONFIG0 0x00 #define H8_CONFIG0_EVENTS_ENABLE 0x02 #define H8_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8_CONFIG0_STICKY_FN 0x08 #define H8_CONFIG0_SMM_H8_ENABLE 0x20 #define H8_CONFIG0_TC_ENABLE 0x80 @@ -56,6 +57,7 @@ void h8_mb_init(void); #define H8_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 #define H8_CONFIG3 0x03 +#define H8_CONFIG3_STICKY_FNLOCK_LED 0x10 #define H8_SOUND_ENABLE0 0x04 #define H8_SOUND_ENABLE1 0x05 @@ -70,16 +72,18 @@ void h8_mb_init(void); #define H8_LED_CONTROL 0x0c #define H8_LED_CONTROL_OFF 0x00 #define H8_LED_CONTROL_ON 0x80 -#define H8_LED_CONTROL_PULSE 0xa0 /* Some models, power LED only*/ +#define H8_LED_CONTROL_PULSE 0xa0 /* Some models, power LED and logo LED only*/ #define H8_LED_CONTROL_BLINK 0xc0 #define H8_LED_CONTROL_POWER_LED 0x00 #define H8_LED_CONTROL_BAT0_LED 0x01 #define H8_LED_CONTROL_BAT1_LED 0x02 #define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_FNLOCK_LED 0x06 /* early models: Fn key (green led); later models: Esc key (white led) */ #define H8_LED_CONTROL_SUSPEND_LED 0x07 #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 +#define H8_LED_CONTROL_LOGO_LED 0x0a /* red i-dot LED in ThinkPad logo (display lid) */ #define H8_LED_CONTROL_ACDC_LED 0x0c #define H8_LED_CONTROL_MUTE_LED 0x0e diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c index 1bd8d1b1624..5e4824628c3 100644 --- a/src/ec/lenovo/h8/panic.c +++ b/src/ec/lenovo/h8/panic.c @@ -12,9 +12,15 @@ static void h8_panic(void) H8_LED_CONTROL_BAT0_LED, H8_LED_CONTROL_BAT1_LED, H8_LED_CONTROL_UBAY_LED, +#if CONFIG(H8_HAS_FNLOCK_LED) + H8_LED_CONTROL_FNLOCK_LED, +#endif H8_LED_CONTROL_SUSPEND_LED, H8_LED_CONTROL_DOCK_LED1, H8_LED_CONTROL_DOCK_LED2, +#if CONFIG(H8_HAS_LEDLOGO) + H8_LED_CONTROL_LOGO_LED, +#endif H8_LED_CONTROL_ACDC_LED, H8_LED_CONTROL_MUTE_LED }; diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index 7d7bfac66c4..c4158e3a774 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -37,6 +37,8 @@ void h8_ssdt_generator(const struct device *dev) /* Used by thinkpad_acpi */ acpigen_write_name_byte("HBDC", h8_has_bdc(dev) ? ONE_OP : ZERO_OP); acpigen_write_name_byte("HWAN", h8_has_wwan(dev) ? ONE_OP : ZERO_OP); + acpigen_write_name_byte("HKLT", (conf && conf->has_thinklight) ? + ONE_OP : ZERO_OP); acpigen_write_name_byte("HKBL", (conf && conf->has_keyboard_backlight) ? ONE_OP : ZERO_OP); acpigen_write_name_byte("HUWB", (conf && conf->has_uwb) ? diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl index 5f00c883995..86784f2ba72 100644 --- a/src/ec/starlabs/merlin/acpi/battery.asl +++ b/src/ec/starlabs/merlin/acpi/battery.asl @@ -42,21 +42,29 @@ Device (BAT0) CONFIG_EC_STARLABS_BATTERY_OEM // 12: OEM Information }) + Method (BFCX, 0, NotSerialized) + { + Local0 = ECRD(RefOf(B1FC)) + If (Local0) { + If (Local0 != 0xffff) { + Return (Local0) + } + } + Return (ECRD(RefOf(B1DC))) + } + Method (_BIF, 0, NotSerialized) { Local0 = ECRD(RefOf(B1DC)) If (Local0) { + Local1 = BFCX() SBIF [1] = Local0 - If (B1FC != 0xffff) { - SBIF [2] = ECRD(RefOf(B1FC)) - } Else { - SBIF [2] = Local0 - } + SBIF [2] = Local1 SBIF [4] = ECRD(RefOf(B1DV)) - SBIF [5] = Local0 / 5 // 20% - SBIF [6] = Local0 / 20 // 5% - SBIF [7] = Local0 / 500 // 0.2% - SBIF [8] = Local0 / 500 // 0.2% + SBIF [5] = (Local1 + 2) / 5 // 20% + SBIF [6] = (Local1 + 5) / 10 // 10% + SBIF [7] = Local1 / 500 // 0.2% + SBIF [8] = Local1 / 500 // 0.2% } Return (SBIF) } @@ -94,20 +102,17 @@ Device (BAT0) { Local0 = ECRD(RefOf(B1DC)) If (Local0) { + Local1 = BFCX() XBIF [2] = Local0 - If (B1FC != 0xffff) { - XBIF [3] = ECRD(RefOf(B1FC)) - } Else { - XBIF [3] = Local0 - } + XBIF [3] = Local1 XBIF [5] = ECRD(RefOf(B1DV)) - XBIF [6] = Local0 / 5 // 20% - XBIF [7] = Local0 / 20 // 5% + XBIF [6] = (Local1 + 2) / 5 // 20% + XBIF [7] = (Local1 + 5) / 10 // 10% If (B1CC != 0xffff) { XBIF [8] = ECRD(RefOf(B1CC)) } - XBIF [14] = Local0 / 500 // 0.2% - XBIF [15] = Local0 / 500 // 0.2% + XBIF [14] = Local1 / 500 // 0.2% + XBIF [15] = Local1 / 500 // 0.2% } Return (XBIF) } @@ -124,11 +129,22 @@ Device (BAT0) PKG1[0] = (ECRD(RefOf(B1ST)) & 0x07) PKG1[1] = ECRD(RefOf(B1PR)) - Local0 = ECRD(RefOf(B1RC)) - If (Local0 != 0xffff) { - PKG1[2] = Local0 - } Else { - PKG1[2] = (ECRD(RefOf(B1RP)) * ECRD(RefOf(B1DC))) / 100 + PKG1[2] = 0xffffffff + Local2 = 0 + + Local0 = ECRD(RefOf(B1RP)) + If (Local0 <= 100) { + Local1 = BFCX() + If (Local1) { + PKG1[2] = ((Local0 * Local1) + 50) / 100 + Local2 = 1 + } + } + If (Local2 == 0) { + Local0 = ECRD(RefOf(B1RC)) + If (Local0 != 0xffff) { + PKG1[2] = Local0 + } } PKG1[3] = ECRD(RefOf(B1PV)) Return (PKG1) diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl index 84113c343da..5156f34dce4 100644 --- a/src/ec/starlabs/merlin/acpi/ec.asl +++ b/src/ec/starlabs/merlin/acpi/ec.asl @@ -108,6 +108,9 @@ Scope (\_SB.PCI0.LPCB) } #include "ac.asl" +#if CONFIG(EC_STARLABS_MERLIN) + #include "shutdown.asl" +#endif #if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE) #include "battery.asl" #include "lid.asl" diff --git a/src/ec/starlabs/merlin/acpi/shutdown.asl b/src/ec/starlabs/merlin/acpi/shutdown.asl new file mode 100644 index 00000000000..93f150a3aa7 --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/shutdown.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q3F, 0, NotSerialized) // Event: Graceful Shutdown Request +{ + Notify (\_SB, 0x81) +} diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index 39c805cb48e..753383fb32a 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -7,6 +7,8 @@ #ifndef _EC_STARLABS_EC_H #define _EC_STARLABS_EC_H +#include + /* * Define the expected value of the PNP base address that is fixed through * the BADRSEL register controlled within the EC domain by the EC Firmware. diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index a3369700c3b..84c619cebbf 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include -#include - #include "ecdefs.h" #include "ec.h" @@ -36,24 +35,11 @@ static uint16_t ec_get_chip_id(unsigned int port) return (pnp_read_index(port, ITE_CHIPID1) << 8) | pnp_read_index(port, ITE_CHIPID2); } -static void merlin_init(struct device *dev) +static void merlin_restore_options(void *unused) { - if (!dev->enabled) - return; - - /* - * The address/data IO port pair for the ite EC are configurable - * through the EC domain and are fixed by the EC's firmware blob. If - * the value(s) passed through the "dev" structure don't match the - * expected values then output severe warnings. - */ - if (dev->path.pnp.port != ITE_FIXED_ADDR) { - printk(BIOS_ERR, "ITE: Incorrect ports defined in devicetree.cb.\n"); - printk(BIOS_ERR, "ITE: Serious operational issues will arise.\n"); - return; - } + (void)unused; - const uint16_t chip_id = ec_get_chip_id(dev->path.pnp.port); + const uint16_t chip_id = ec_get_chip_id(ITE_FIXED_ADDR); if (chip_id != ITE_IT5570 && chip_id != ITE_IT8987) { printk(BIOS_ERR, "ITE: Unsupported chip ID 0x%04x.\n", chip_id); @@ -266,9 +252,9 @@ static void merlin_init(struct device *dev) get_ec_value_from_option("charge_led", LED_NORMAL, led_brightness, ARRAY_SIZE(led_brightness))); } +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, merlin_restore_options, NULL); static struct device_operations ops = { - .init = merlin_init, .read_resources = noop_read_resources, .set_resources = noop_set_resources, }; diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c index 398b12619bd..a435c2a49be 100644 --- a/src/ec/starlabs/merlin/nuvoton.c +++ b/src/ec/starlabs/merlin/nuvoton.c @@ -5,8 +5,6 @@ #include #include #include -#include - #include "ecdefs.h" #include "ec.h" diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig index f0702a76d17..14899dbce73 100644 --- a/src/ec/system76/ec/Kconfig +++ b/src/ec/system76/ec/Kconfig @@ -21,6 +21,11 @@ config EC_SYSTEM76_EC_DGPU select EC_SYSTEM76_EC_FAN2 depends on EC_SYSTEM76_EC +config EC_SYSTEM76_EC_LOCKDOWN + bool + default n + depends on EC_SYSTEM76_EC + config EC_SYSTEM76_EC_OLED bool default n diff --git a/src/ec/system76/ec/Makefile.mk b/src/ec/system76/ec/Makefile.mk index 9808e297d66..02fcda537ce 100644 --- a/src/ec/system76/ec/Makefile.mk +++ b/src/ec/system76/ec/Makefile.mk @@ -4,6 +4,7 @@ ifeq ($(CONFIG_EC_SYSTEM76_EC),y) all-y += system76_ec.c ramstage-y += smbios.c +ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c smm-$(CONFIG_DEBUG_SMI) += system76_ec.c diff --git a/src/ec/system76/ec/lockdown.c b/src/ec/system76/ec/lockdown.c new file mode 100644 index 00000000000..e0274c95e16 --- /dev/null +++ b/src/ec/system76/ec/lockdown.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "system76_ec.h" +#include +#include +#include +#include + +static int protect_region_by_name(const char *name) +{ + int res; + struct region region; + + res = fmap_locate_area(name, ®ion); + if (res < 0) { + printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res); + return res; + } + + res = spi_flash_ctrlr_protect_region(boot_device_spi_flash(), ®ion, WRITE_PROTECT); + if (res < 0) { + printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res); + return res; + } + + printk(BIOS_INFO, "protected '%s'\n", name); + return 0; +} + +static void lock(void *unused) +{ + uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK; + if (!system76_ec_security_get(&state)) { + printk(BIOS_INFO, "failed to get security state, assuming unlocked\n"); + state = SYSTEM76_EC_SECURITY_STATE_UNLOCK; + } + + printk(BIOS_INFO, "security state: %d\n", state); + if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) { + // Protect WP_RO region, which should contain FMAP and COREBOOT + protect_region_by_name("WP_RO"); + // Protect RW_MRC_CACHE region, this must be done after it is written + protect_region_by_name("RW_MRC_CACHE"); + //TODO: protect entire flash except when in SMM? + } +} + +/* + * Keep in sync with mrc_cache.c + */ +#if CONFIG(MRC_WRITE_NV_LATE) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL); +#else +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL); +#endif diff --git a/src/ec/system76/ec/system76_ec.c b/src/ec/system76/ec/system76_ec.c index 828376d0e5c..ee41b1e8d72 100644 --- a/src/ec/system76/ec/system76_ec.c +++ b/src/ec/system76/ec/system76_ec.c @@ -26,6 +26,9 @@ #define CMD_PRINT_REG_LEN 3 #define CMD_PRINT_REG_DATA 4 +// Get security state command +#define CMD_SECURITY_GET 20 + static inline uint8_t system76_ec_read(uint8_t addr) { return inb(SYSTEM76_EC_BASE + (uint16_t)addr); @@ -110,3 +113,9 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data, return ret; } + +bool system76_ec_security_get(uint8_t *state) +{ + *state = SYSTEM76_EC_SECURITY_STATE_LOCK; + return system76_ec_cmd(CMD_SECURITY_GET, NULL, 0, state, sizeof(*state)); +} diff --git a/src/ec/system76/ec/system76_ec.h b/src/ec/system76/ec/system76_ec.h index 9675bd0cafc..6c91bb6aec6 100644 --- a/src/ec/system76/ec/system76_ec.h +++ b/src/ec/system76/ec/system76_ec.h @@ -6,6 +6,15 @@ #include #include +// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET +#define SYSTEM76_EC_SECURITY_STATE_LOCK 0 +// Flashing is allowed, cannot be set with CMD_SECURITY_SET +#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1 +// Flashing will be prevented on the next reboot +#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2 +// Flashing will be allowed on the next reboot +#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3 + /* * Send a command to the EC. request_data/request_size are the request payload, * request_data can be NULL if request_size is 0. reply_data/reply_size are @@ -14,4 +23,6 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data, uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); +bool system76_ec_security_get(uint8_t *state); + #endif diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index ac00050031b..8c2f8308018 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1626,6 +1626,9 @@ void acpi_create_crat(struct acpi_crat_header *crat, unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); +void acpi_write_tpm2(acpi_tpm2_t *tpm2, const void *lasa, const u32 tpm2_log_len, + const u64 control_area, const u32 start_method); + /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(const struct device *device); diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 69216ec4fa4..4daafc885db 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -4,7 +4,6 @@ #define ACPIGEN_PCI_H #include -#include #include void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); @@ -14,6 +13,10 @@ void acpigen_write_PRT_GSI_entry(unsigned int pci_dev, unsigned int acpi_pin, un void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, const char *source_path, unsigned int index); +void acpigen_write_PRT_GSI_entry_devfn(unsigned int devfn, unsigned int acpi_pin, unsigned int gsi); +void acpigen_write_PRT_source_entry_devfn(unsigned int devfn, unsigned int acpi_pin, + const char *source_path, unsigned int index); + void pci_domain_fill_ssdt(const struct device *domain); #endif /* ACPIGEN_PCI_H */ diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h index b564e648172..6097782bcf2 100644 --- a/src/include/acpi/acpigen_ps2_keybd.h +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -43,4 +43,8 @@ void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, bool has_assistant_key, bool has_alpha_num_punct_keys); +/* _DSD with function-row-physmap only (no keymap) */ +void acpigen_ps2_keyboard_physmap_dsd(const char *scope, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[]); + #endif /* __ACPI_ACPIGEN_PS2_KEYBD_H__ */ diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 67b3a405a11..dc06ca69450 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -202,6 +202,12 @@ static inline bool platform_is_low_battery_shutdown_needed(void) { return false; static inline void platform_handle_emergency_low_battery(void) { /* nop */ } #endif +#if CONFIG(PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO) +bool platform_use_secondary_logo(void); +#else +static inline bool platform_use_secondary_logo(void) { return false; } +#endif + /* * Platform specific callbacks for off-mode bootsplash handling. * diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 3f9e5b01da0..5051e5648c3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -32,17 +32,24 @@ static inline unsigned int get_uart_for_console(void) } #endif +/* Returns the oversample divisor multiplied by any other divisors that act + * on the input clock + */ +unsigned int uart_input_clock_divider(void); + /* Returns the divisor value for a given baudrate. * The formula to satisfy is: * refclk / divisor = baudrate * oversample */ -unsigned int uart_baudrate_divisor(unsigned int baudrate, +unsigned int uart_calc_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); -/* Returns the oversample divisor multiplied by any other divisors that act - * on the input clock - */ -unsigned int uart_input_clock_divider(void); +/* Same as above but with the most commonly used parameters */ +static inline unsigned int uart_get_baudrate_divisor(void) +{ + return uart_calc_baudrate_divisor(get_uart_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); +} /* Bitbang out one byte on an 8n1 UART through the output function set_tx(). */ void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state)); diff --git a/src/include/cper.h b/src/include/cper.h index 1bddaa78efb..3197d9bb091 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -415,37 +415,63 @@ typedef struct cper_ia32x64_ctx_x64state { u16 tr; } __packed cper_ia32x64_ctx_x64state_t; +/* Memory Error Section Valid bit fields (Table 275) */ +#define CPER_MEM_VALID_ERROR_STATUS BIT(0) +#define CPER_MEM_VALID_PA BIT(1) +#define CPER_MEM_VALID_PA_MASK BIT(2) +#define CPER_MEM_VALID_NODE BIT(3) +#define CPER_MEM_VALID_CARD BIT(4) +#define CPER_MEM_VALID_MODULE BIT(5) +#define CPER_MEM_VALID_BANK BIT(6) +#define CPER_MEM_VALID_DEVICE BIT(7) +#define CPER_MEM_VALID_ROW BIT(8) +#define CPER_MEM_VALID_COLUMN BIT(9) +#define CPER_MEM_VALID_BIT_POSITION BIT(10) +#define CPER_MEM_VALID_REQUESTOR_ID BIT(11) +#define CPER_MEM_VALID_RESPONDER_ID BIT(12) +#define CPER_MEM_VALID_TARGET_ID BIT(13) +#define CPER_MEM_VALID_ERROR_TYPE BIT(14) +#define CPER_MEM_VALID_RANK BIT(15) +#define CPER_MEM_VALID_CARD_HANDLE BIT(16) +#define CPER_MEM_VALID_MODULE_HANDLE BIT(17) +#define CPER_MEM_VALID_EXTENDED BIT(18) +#define CPER_MEM_VALID_BANK_GROUP BIT(19) +#define CPER_MEM_VALID_BANK_ADDRESS BIT(20) +#define CPER_MEM_VALID_CHIP_ID BIT(21) + /* UEFI Spec 2.10, Appendix N.2.5 Memory Error Types (Table N.31) */ -#define CPER_UNDEFINED 0 +#define CPER_MEM_UNKNOWN 0 +#define CPER_MEM_UNDEFINED 0 #define CPER_ERR_SINGLE_BIT_ECC 2 #define CPER_ERR_MULTI_BIT_ECC 3 +#define CPER_ERR_TARGET_ABORT 7 #define CPER_ERR_MEM_PARITY_ERR 8 #define CPER_ERR_MEM_SCRUB_CE_ERR 13 #define CPER_ERR_MEM_SCRUB_UCE_ERR 14 -/* UEFI Spec 2.10, Appendix N.2.5 Memory Error Section (Table N.31) */ -struct __packed cper_memory_section { - u64 valid_bits; - u64 err_sts; - u64 phys_addr; - u64 phys_addr_mask; - u16 node; - u16 card; - u16 module; - u16 bank; - u16 device; - u16 row; - u16 column; - u16 bit_position; - u64 requestor_id; - u64 responder_id; - u64 target_id; - u8 mem_err_type; - u8 extended; - u16 rank_number; - u16 card_handle; - u16 module_handle; -}; +/// UEFI 2.6 Appendix N Table 275 Spec. +typedef struct cper_mem_section { + u64 validation_bits; // see CPER_MEM_VALID_ macros above + u64 error_status; // Error Status + u64 physical_addr; // Physical memory address of detected error + u64 physical_addr_mask; // Physical Error Address mask + u16 node; // Node Number + u16 card; // Card Number + u16 module; // Module Number + u16 bank; // Bank Number + u16 device; // Device Number + u16 row; // Row Number + u16 column; // Column Number + u16 bit_position; // Bit Position + u64 requestor_id; // Requestor ID + u64 responder_id; // Responder ID + u64 target_id; // Target ID + u8 error_type; // Memory Error Type + u8 extended; // Extended + u16 rank; // Rank Number + u16 card_handle; // Card Number + u16 module_handle; // Module Number +} __packed cper_mem_section_t; #define FW_ERR_RECORD_ID_CRASHLOG_GUID \ GUID_INIT(0x8f87f311, 0xc998, 0x4d9e, \ diff --git a/src/include/cpu/amd/cpuid.h b/src/include/cpu/amd/cpuid.h index 81d008de77b..538ff0a1fe2 100644 --- a/src/include/cpu/amd/cpuid.h +++ b/src/include/cpu/amd/cpuid.h @@ -121,6 +121,10 @@ #define CPUID_EBX_THREADS_SHIFT 8 #define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) +#define CPUID_ECX_NODE_ID 0x8000001E +#define CPUID_ECX_NODE_ID_SHIFT 0 +#define CPUID_ECX_NODE_ID_MASK (0xff << CPUID_ECX_NODE_ID_SHIFT) + #define CPUID_EBX_MEM_ENCRYPT 0x8000001f #define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT 6 #define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK (0x3f << CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT) diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 69425c5cca4..225f71e014a 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -66,6 +66,7 @@ #define IC_CFG_MSR 0xC0011021 #define DC_CFG_MSR 0xC0011022 #define BU_CFG_MSR 0xC0011023 +#define COMBINE_CR0_CD (1ull << 49) // Core::X86::Msr::TW_CFG::CombineCr0Cd #define FP_CFG_MSR 0xC0011028 #define DE_CFG_MSR 0xC0011029 #define BU_CFG2_MSR 0xC001102A diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 2b25c757054..f3fc4d29e8d 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -28,7 +28,7 @@ struct smm_relocation_params { extern struct smm_relocation_params smm_reloc_params; struct ied_header { - char signature[10]; + char __nonstring signature[10]; u32 size; u8 reserved[34]; } __packed; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 834874095f8..6b0e78153af 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -25,6 +25,7 @@ #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_ROM_ARMOR 0xea #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 972b89a606c..b0dca470df4 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -37,7 +37,7 @@ uint32_t crc32_byte(uint32_t prev_crc, uint8_t data); #define CRC(buf, size, crc_func) ({ \ const uint8_t *_crc_local_buf = (const uint8_t *)(buf); \ size_t _crc_local_size = size; \ - __typeof__(crc_func(0, 0)) _crc_local_result = 0; \ + typeof(crc_func(0, 0)) _crc_local_result = 0; \ while (_crc_local_size--) { \ _crc_local_result = crc_func(_crc_local_result, *_crc_local_buf++); \ } \ diff --git a/src/include/device/azalia_codec/realtek.h b/src/include/device/azalia_codec/realtek.h index c7b622a332a..b7e5ce4b048 100644 --- a/src/include/device/azalia_codec/realtek.h +++ b/src/include/device/azalia_codec/realtek.h @@ -29,6 +29,19 @@ enum alc269_pin_widget { ALC269_VB_HP_OUT = 0x21, // Port-I, ALC269-VBx only }; +enum alc662_pin_widget { + ALC662_FRONT = 0x14, // Port-D + ALC662_SURROUND = 0x15, // Port-A + ALC662_CENTER_LFE = 0x16, // Port-G + ALC662_MIC1 = 0x18, // Port-B + ALC662_MIC2 = 0x19, // Port-F + ALC662_LINE1 = 0x1a, // Port-C + ALC662_LINE2 = 0x1b, // Port-E + ALC662_CD = 0x1c, + ALC662_PC_BEEP = 0x1d, + ALC662_SPDIF_OUT1 = 0x1e, +}; + enum alc887_pin_widget { ALC887_SPDIF_OUT2 = 0x11, ALC887_DMIC_LR = 0x12, @@ -46,4 +59,47 @@ enum alc887_pin_widget { ALC887_SPDIF_IN = 0x1f, }; +enum alc892_pin_widget { + ALC892_SPDIF_OUT2 = 0x11, + ALC892_DMIC_LR = 0x12, + ALC892_FRONT = 0x14, // Port-D + ALC892_SURROUND = 0x15, // Port-A + ALC892_CENTER_LFE = 0x16, // Port-G + ALC892_SIDE_SURROUND = 0x17, // Port-H + ALC892_MIC1 = 0x18, // Port-B + ALC892_MIC2 = 0x19, // Port-F + ALC892_LINE1 = 0x1a, // Port-C + ALC892_LINE2 = 0x1b, // Port-E + ALC892_CD = 0x1c, + ALC892_PC_BEEP = 0x1d, + ALC892_SPDIF_OUT1 = 0x1e, + ALC892_SPDIF_IN = 0x1f, +}; + +enum alc1150_pin_widget { + ALC1150_SPDIF_OUT2 = 0x11, + ALC1150_FRONT = 0x14, // Port-D + ALC1150_SURROUND = 0x15, // Port-A + ALC1150_CENTER_LFE = 0x16, // Port-G + ALC1150_SIDE_SURROUND = 0x17, // Port-H + ALC1150_MIC1 = 0x18, // Port-B + ALC1150_MIC2 = 0x19, // Port-F + ALC1150_LINE1 = 0x1a, // Port-C + ALC1150_LINE2 = 0x1b, // Port-E + ALC1150_SPDIF_OUT1 = 0x1e, +}; + +enum alc1200_pin_widget { + ALC1200_SPDIF_OUT2 = 0x11, + ALC1200_FRONT = 0x14, // Port-D + ALC1200_SURROUND = 0x15, // Port-A + ALC1200_CENTER_LFE = 0x16, // Port-G + ALC1200_SIDE_SURROUND = 0x17, // Port-H + ALC1200_MIC1 = 0x18, // Port-B + ALC1200_MIC2 = 0x19, // Port-F + ALC1200_LINE1 = 0x1a, // Port-C + ALC1200_LINE2 = 0x1b, // Port-E + ALC1200_SPDIF_OUT1 = 0x1e, +}; + #endif /* DEVICE_AZALIA_CODEC_REALTEK_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d990b86a022..ebdcd608ab9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3406,6 +3406,12 @@ #define PCI_DID_INTEL_LPT_LP_PCIE_RP4 0x9c16 #define PCI_DID_INTEL_LPT_LP_PCIE_RP5 0x9c18 #define PCI_DID_INTEL_LPT_LP_PCIE_RP6 0x9c1a +#define PCI_DID_INTEL_WPT_LP_PCIE_RP1 0x9c90 +#define PCI_DID_INTEL_WPT_LP_PCIE_RP2 0x9c92 +#define PCI_DID_INTEL_WPT_LP_PCIE_RP3 0x9c94 +#define PCI_DID_INTEL_WPT_LP_PCIE_RP4 0x9c96 +#define PCI_DID_INTEL_WPT_LP_PCIE_RP5 0x9c98 +#define PCI_DID_INTEL_WPT_LP_PCIE_RP6 0x9c9a #define PCI_DID_INTEL_SPT_LP_PCIE_RP1 0x9d10 #define PCI_DID_INTEL_SPT_LP_PCIE_RP2 0x9d11 @@ -4553,6 +4559,9 @@ #define PCI_DID_INTEL_PTL_H_GT2_2 0xb0a0 #define PCI_DID_INTEL_PTL_H_GT2_3 0xb0b0 #define PCI_DID_INTEL_PTL_H_GT2_4 0xb08f +#define PCI_DID_INTEL_PTL_H_GT2_5 0xb081 +#define PCI_DID_INTEL_PTL_H_GT2_6 0xb082 +#define PCI_DID_INTEL_PTL_H_GT2_7 0xb083 #define PCI_DID_INTEL_WCL_GT2_1 0xfd80 #define PCI_DID_INTEL_WCL_GT2_2 0xfd81 #define PCI_DID_INTEL_NVL_GT2_1 0xd741 @@ -4665,7 +4674,6 @@ #define PCI_DID_INTEL_ADL_P_ID_6 0x4609 #define PCI_DID_INTEL_ADL_P_ID_7 0x4601 #define PCI_DID_INTEL_ADL_P_ID_8 0x4661 -#define PCI_DID_INTEL_ADL_P_ID_9 0x467f #define PCI_DID_INTEL_ADL_P_ID_10 0x4619 #define PCI_DID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DID_INTEL_ADL_M_ID_2 0x460a @@ -4702,6 +4710,7 @@ #define PCI_DID_INTEL_RPL_S_ID_3 0xa703 #define PCI_DID_INTEL_RPL_S_ID_4 0xa704 #define PCI_DID_INTEL_RPL_S_ID_5 0xa705 +#define PCI_DID_INTEL_RPL_S_ID_6 0xa740 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 @@ -4887,6 +4896,7 @@ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 #define PCI_DID_INTEL_LPT_H_AUDIO_9 0x8ca0 #define PCI_DID_INTEL_LPT_LP_AUDIO 0x9c20 +#define PCI_DID_INTEL_WPT_LP_AUDIO 0x9ca0 #define PCI_DID_INTEL_APL_AUDIO 0x5a98 #define PCI_DID_INTEL_GLK_AUDIO 0x3198 #define PCI_DID_INTEL_CNL_AUDIO 0x9dc8 @@ -4991,6 +5001,7 @@ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba #define PCI_DID_INTEL_LPT_LP_MEI 0x9c3a +#define PCI_DID_INTEL_WPT_LP_MEI 0x9cba #define PCI_DID_INTEL_APL_CSE0 0x5a9a #define PCI_DID_INTEL_GLK_CSE0 0x319a #define PCI_DID_INTEL_CNL_CSE0 0x9de0 diff --git a/src/include/edid.h b/src/include/edid.h index b2d6aa2cab7..cd8df7e3edb 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -82,8 +82,8 @@ struct edid { u32 bytes_per_line; int hdmi_monitor_detected; - char ascii_string[EDID_ASCII_STRING_LENGTH + 1]; - char manufacturer_name[3 + 1]; + char __nonstring ascii_string[EDID_ASCII_STRING_LENGTH + 1]; + char __nonstring manufacturer_name[3 + 1]; }; enum edid_status { diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 266490bc7e4..b8d370abce4 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -58,18 +58,11 @@ static inline bool fw_config_is_provisioned(void) return fw_config_get() != UNDEFINED_FW_CONFIG; } - -#if CONFIG(FW_CONFIG) - /** - * fw_config_get_field() - Provide firmware configuration field value. - * @field: Structure containing field name and mask - * - * Return 64bit firmware configuration value determined for the system. - * Will return UNDEFINED_FW_CONFIG if unprovisioned, caller should treat - * as error value for the case. + * fw_config_get_mainboard_override() - Allow mainboard to override fw_config. + * @fw_config: Pointer to the current fw_config value to modify. */ -uint64_t fw_config_get_field(const struct fw_config_field *field); +void fw_config_get_mainboard_override(uint64_t *fw_config); /** * fw_config_probe_mainboard_override() - Mainboard hook to override specific probes @@ -85,6 +78,28 @@ uint64_t fw_config_get_field(const struct fw_config_field *field); */ bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result); +#if CONFIG(FW_CONFIG) + +/** + * fw_config_get_field() - Provide firmware configuration field value. + * @field: Structure containing field name and mask + * + * Return 64bit firmware configuration value determined for the system. + * Will return UNDEFINED_FW_CONFIG if unprovisioned, caller should treat + * as error value for the case. + */ +uint64_t fw_config_get_field(const struct fw_config_field *field); + +/** + * fw_config_value_set_field() - Update a field within a raw fw_config value. + * @fw_config: Pointer to the raw fw_config value to modify. + * @field: The field to set. + * @value: The new value for the field. + */ +void fw_config_value_set_field(uint64_t *fw_config, + const struct fw_config_field *field, + uint64_t value); + /** * fw_config_probe() - Check if field and option matches. * @match: Structure containing field and option to probe. @@ -120,6 +135,12 @@ bool fw_config_probe_dev(const struct device *dev, const struct fw_config **matc #else +static inline void fw_config_value_set_field(uint64_t *fw_config, + const struct fw_config_field *field, + uint64_t value) +{ +} + static inline bool fw_config_probe(const struct fw_config *match) { /* Always return true when probing with disabled fw_config. */ diff --git a/src/include/input-event-codes.h b/src/include/input-event-codes.h index 968f3a352db..8549cfc9c6f 100644 --- a/src/include/input-event-codes.h +++ b/src/include/input-event-codes.h @@ -2,8 +2,8 @@ * This file is copied as-is from include/uapi/linux/input-event-codes.h * from HID maintainer's tree: * git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git - * from `for-next` branch - * at SHA: c412e40267dd4ac020c5f8dc8c1cccc04e796ff4 + * from `master` branch + * at SHA: 7f87a5ea75f011d2c9bc8ac0167e5e2d1adb1594 */ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ @@ -35,6 +35,7 @@ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ +#define INPUT_PROP_PRESSUREPAD 0x07 /* pressure triggers clicks */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) @@ -527,6 +528,7 @@ #define KEY_NOTIFICATION_CENTER 0x1bc /* Show/hide the notification center */ #define KEY_PICKUP_PHONE 0x1bd /* Answer incoming call */ #define KEY_HANGUP_PHONE 0x1be /* Decline incoming call */ +#define KEY_LINK_PHONE 0x1bf /* AL Phone Syncing */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 @@ -608,6 +610,11 @@ #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 +#define BTN_GRIPL 0x224 +#define BTN_GRIPR 0x225 +#define BTN_GRIPL2 0x226 +#define BTN_GRIPR2 0x227 + #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ #define KEY_REFRESH_RATE_TOGGLE 0x232 /* Display refresh rate toggle */ @@ -632,6 +639,22 @@ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ +/* + * Keycodes for hotkeys toggling the electronic privacy screen found on some + * laptops on/off. Note when the embedded-controller turns on/off the eprivacy + * screen itself then the state should be reported through drm connecter props: + * https://www.kernel.org/doc/html/latest/gpu/drm-kms.html#standard-connector-properties + * Except when implementing the drm connecter properties API is not possible + * because e.g. the firmware does not allow querying the presence and/or status + * of the eprivacy screen at boot. + */ +#define KEY_EPRIVACY_SCREEN_ON 0x252 +#define KEY_EPRIVACY_SCREEN_OFF 0x253 + +#define KEY_ACTION_ON_SELECTION 0x254 /* AL Action on Selection (HUTRR119) */ +#define KEY_CONTEXTUAL_INSERT 0x255 /* AL Contextual Insertion (HUTRR119) */ +#define KEY_CONTEXTUAL_QUERY 0x256 /* AL Contextual Query (HUTRR119) */ + #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 @@ -772,6 +795,9 @@ #define KEY_KBD_LCD_MENU4 0x2bb #define KEY_KBD_LCD_MENU5 0x2bc +/* Performance Boost key (Alienware)/G-Mode key (Dell) */ +#define KEY_PERFORMANCE 0x2bd + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -877,6 +903,7 @@ #define ABS_VOLUME 0x20 #define ABS_PROFILE 0x21 +#define ABS_SND_PROFILE 0x22 #define ABS_MISC 0x28 @@ -932,7 +959,8 @@ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MACHINE_COVER 0x10 /* set = cover closed */ -#define SW_MAX 0x10 +#define SW_USB_INSERT 0x11 /* set = USB audio device connected */ +#define SW_MAX 0x11 #define SW_CNT (SW_MAX+1) /* @@ -985,4 +1013,12 @@ #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) +/* + * ABS_SND_PROFILE values + */ + +#define SND_PROFILE_SILENT 0x00 +#define SND_PROFILE_VIBRATE 0x01 +#define SND_PROFILE_RING 0x02 + #endif diff --git a/src/include/lib.h b/src/include/lib.h index 863888e16ba..05e33865986 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -21,6 +21,7 @@ void quick_ram_check_or_die(uintptr_t dst); int primitive_memtest(uintptr_t base, uintptr_t size); /* Defined in src/lib/stack.c */ +int _checkstack(void *top_of_stack, size_t stack_size, int core); int checkstack(void *top_of_stack, int core); /* diff --git a/src/include/limits.h b/src/include/limits.h index 938eeed6f3d..5e34998ee40 100644 --- a/src/include/limits.h +++ b/src/include/limits.h @@ -3,6 +3,8 @@ #ifndef LIMITS_H #define LIMITS_H +#define CHAR_BIT 8 + #define USHRT_MAX ((unsigned short)~0U) #define SHRT_MAX ((short)(USHRT_MAX >> 1)) #define SHRT_MIN ((short)(-SHRT_MAX - 1)) diff --git a/src/include/rules.h b/src/include/rules.h index 053cd6bc09c..d9e7fecdcb9 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -347,7 +347,7 @@ /* When set is included for the spinlock implementation. */ #define ENV_SUPPORTS_SMP (CONFIG(SMP) && ENV_HAS_SPINLOCKS) -#if ENV_X86 && CONFIG(COOP_MULTITASKING) && (ENV_RAMSTAGE || ENV_CREATES_CBMEM) +#if CONFIG(COOP_MULTITASKING) && (ENV_RAMSTAGE || ENV_CREATES_CBMEM) /* TODO: Enable in all x86 stages */ #define ENV_SUPPORTS_COOP 1 #else diff --git a/src/include/security/tcg/opal_s3_resume.h b/src/include/security/tcg/opal_s3_resume.h new file mode 100644 index 00000000000..f14ee90b490 --- /dev/null +++ b/src/include/security/tcg/opal_s3_resume.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_TCG_OPAL_S3_RESUME_H +#define SECURITY_TCG_OPAL_S3_RESUME_H + +/* + * Trigger an SMM-assisted OPAL unlock during S3 resume. + * + * The unlock implementation lives in SMM; this is a small ramstage helper + * that issues the APMC trigger. It is called automatically from the x86 + * resume path when enabled. + */ +void opal_s3_resume_unlock(void); + +#endif diff --git a/src/include/security/tcg/opal_s3_smm.h b/src/include/security/tcg/opal_s3_smm.h new file mode 100644 index 00000000000..798ed0ae0a4 --- /dev/null +++ b/src/include/security/tcg/opal_s3_smm.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_TCG_OPAL_S3_SMM_H +#define SECURITY_TCG_OPAL_S3_SMM_H + +#include + +/* + * OPAL S3 SMM helpers. + * + * These helpers are called from SMI handlers. When the feature is disabled, + * these APIs compile to no-ops so callers do not need preprocessor guards. + */ +#if CONFIG(TCG_OPAL_S3_UNLOCK) +int opal_s3_smi_apmc(u8 apmc); +void opal_s3_smi_sleep(u8 slp_typ); +void opal_s3_smi_sleep_finalize(u8 slp_typ); +#else +static inline int opal_s3_smi_apmc(u8 apmc) +{ + (void)apmc; + return 0; +} + +static inline void opal_s3_smi_sleep(u8 slp_typ) +{ + (void)slp_typ; +} + +static inline void opal_s3_smi_sleep_finalize(u8 slp_typ) +{ + (void)slp_typ; +} +#endif + +#endif diff --git a/src/include/smbios.h b/src/include/smbios.h index 103e85b9afd..b42140cb5aa 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -104,6 +104,7 @@ unsigned int smbios_processor_family(struct cpuid_result res); unsigned int smbios_cache_error_correction_type(u8 level); unsigned int smbios_cache_sram_type(void); unsigned int smbios_cache_conf_operation_mode(u8 level); +u8 smbios_cache_speed(u8 level); /* Used by mainboard to add port information of type 8 */ struct port_information; diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 9ba5d1f53ef..f8fec968c4c 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -107,6 +107,22 @@ struct spi_flash_rpmc_cap { uint8_t op2_read_cmd; }; +struct sfdp_block_erase_info { + uint8_t opcode; /* 0 if not available */ + uint8_t block_size_pow2; /* Block size in bytes power of two. + * 0 if unused or uninitialized. */ +}; + +/** + * For now SFDP defines up to 5 different erase block sizes, + * not counting full chip erase. + */ +#define SFDP_NUM_ERASE_BLOCKS 5 + +struct sfdp_jedec_info { + struct sfdp_block_erase_info erase_info[SFDP_NUM_ERASE_BLOCKS]; +}; + struct spi_flash { struct spi_slave spi; u8 vendor; diff --git a/src/include/stddef.h b/src/include/stddef.h index 352a54f5636..d68a210bcb5 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -21,6 +21,7 @@ typedef __WINT_TYPE__ wint_t; #if __STDC_VERSION__ >= 202300L #define NULL nullptr +typedef typeof(nullptr) nullptr_t; #else #define nullptr ((void *)0) #define NULL ((void *)0) diff --git a/src/include/thread.h b/src/include/thread.h index 059ba52a2c3..6beeb176709 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -4,6 +4,7 @@ #include #include +#include #include struct thread_mutex { @@ -43,7 +44,7 @@ struct thread { int id; uintptr_t stack_current; uintptr_t stack_orig; - struct thread *next; + struct list_node list_node; enum cb_err (*entry)(void *); void *entry_arg; int can_yield; @@ -95,5 +96,7 @@ static inline void thread_mutex_lock(struct thread_mutex *mutex) {} static inline void thread_mutex_unlock(struct thread_mutex *mutex) {} #endif +/* Check all thread stacks for overruns. */ +int thread_check_stacks(void); #endif /* THREAD_H_ */ diff --git a/src/include/types.h b/src/include/types.h index df5e7ae06d2..56994ddab77 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -30,6 +30,7 @@ #define BIT_FLAG_32(x) (1u << (x)) #endif -#define BITS_PER_BYTE 8 +#define BITS_PER_BYTE CHAR_BIT +_Static_assert(CHAR_BIT == 8, "coreboot expects 8-bit bytes"); #endif /* __TYPES_H */ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 38cc4590867..3f2cb31e977 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -239,6 +239,13 @@ config PLATFORM_POST_RENDER_DELAY_SEC teardown/synchronization after user notification before passing control to the OS. +config PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO + bool "Enable alternative (Secondary) resolution for boot indicator" + default n + help + Select this if your board uses multiple panels with different + resolutions and needs a second set of indicator logos in CBFS. + if PLATFORM_HAS_LOW_BATTERY_INDICATOR config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR @@ -253,7 +260,15 @@ config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH string "Path to low battery logo file" default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery.bmp" -endif + +if PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO + +config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_SECONDARY_PATH + string "Path to secondary low battery logo" + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery_alt.bmp" + +endif # PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO +endif # PLATFORM_HAS_LOW_BATTERY_INDICATOR config SPLASH_SCREEN_FOOTER bool "Enable custom footer on firmware splash screen" @@ -283,10 +298,21 @@ config PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR This feature requires a functional display and depends on the BMP_LOGO infrastructure to render the charging assets. +if PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR + config PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH string "Path to off-mode charging logo file" default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/off_mode_charging.bmp" +if PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO + +config PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_SECONDARY_PATH + string "Path to secondary off-mode charging logo" + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/off_mode_charging_alt.bmp" + +endif # PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO +endif # PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR + config FRAMEBUFFER_SPLASH_TEXT bool "Enable splash screen text" default n diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index 756956aca53..012792fe6c1 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -subdirs-y += gnat - ifeq ($(CONFIG_UBSAN),y) ramstage-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined @@ -476,7 +474,18 @@ endif $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR, \ low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH)) + +ifeq ($(CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR),y) +$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO, \ + low_battery_alt.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_SECONDARY_PATH)) +endif + $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_SPLASH_SCREEN_FOOTER, \ footer_logo.bmp,CONFIG_SPLASH_SCREEN_FOOTER_LOGO_PATH)) $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR, \ off_mode_charging.bmp,CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH)) + +ifeq ($(CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR),y) +$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO, \ + off_mode_charging_alt.bmp,CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_SECONDARY_PATH)) +endif diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 7b0de547209..a778c5c0717 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -17,6 +17,14 @@ static const char *bootsplash_list[BOOTSPLASH_MAX_NUM] = { [BOOTSPLASH_OFF_MODE_CHARGING] = "off_mode_charging.bmp" }; +/* Mapping of different bootsplash logo name (including secondary) based on bootsplash type */ +static const char *alt_bootsplash_list[BOOTSPLASH_MAX_NUM] = { + [BOOTSPLASH_LOW_BATTERY] = "low_battery_alt.bmp", + [BOOTSPLASH_CENTER] = "logo.bmp", + [BOOTSPLASH_FOOTER] = "footer_logo.bmp", + [BOOTSPLASH_OFF_MODE_CHARGING] = "off_mode_charging_alt.bmp" +}; + /* * Return the appropriate logo filename based on the bootsplash type. * This will be the default filename from 'bootsplash_list' or the @@ -28,7 +36,7 @@ static const char *bmp_get_logo_filename(enum bootsplash_type type) if ((type == BOOTSPLASH_CENTER) && CONFIG(HAVE_CUSTOM_BMP_LOGO)) return bmp_logo_filename(); - return bootsplash_list[type]; + return platform_use_secondary_logo() ? alt_bootsplash_list[type] : bootsplash_list[type]; } void *bmp_load_logo_by_type(enum bootsplash_type type, size_t *logo_size) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 07bd3f4a28e..2cdb3cf5904 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -160,6 +160,8 @@ static inline bool cbfs_lzma_enabled(void) static inline bool cbfs_zstd_enabled(void) { + if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_ZSTD)) + return true; if (ENV_PAYLOAD_LOADER && CONFIG(COMPRESSED_PAYLOAD_ZSTD)) return true; if (ENV_RAMSTAGE_LOADER && CONFIG(COMPRESS_RAMSTAGE_ZSTD)) @@ -176,12 +178,7 @@ static bool cbfs_file_hash_mismatch(const void *buffer, size_t size, const struct vb2_hash *hash = NULL; - /* - * Skipping this block in SMM because vboot library isn't linked to SMM stage. This is - * an issue only if using a CMOS options backend, then SMM refers to an option and tries - * to verify cmos.layout here. - */ - if (CONFIG(CBFS_VERIFICATION) && !ENV_SMM && !skip_verification) { + if (CONFIG(CBFS_VERIFICATION) && !skip_verification) { hash = cbfs_file_hash(mdata); if (!hash) { ERROR("'%s' does not have a file hash!\n", mdata->h.filename); @@ -515,6 +512,24 @@ static void *do_alloc(union cbfs_mdata *mdata, struct region_device *rdev, return loc; } +static enum cb_err check_or_query_type(const union cbfs_mdata *mdata, enum cbfs_type *type) +{ + if (type == NULL) + return CB_SUCCESS; + + const enum cbfs_type real_type = be32toh(mdata->h.type); + if (*type == CBFS_TYPE_QUERY) { + *type = real_type; + return CB_SUCCESS; + } + + if (*type == real_type) + return CB_SUCCESS; + + ERROR("'%s' type mismatch (is %u, expected %u)\n", mdata->h.filename, real_type, *type); + return CB_ERR; +} + void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out, bool force_ro, enum cbfs_type *type) { @@ -528,16 +543,8 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, if (_cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return NULL; - if (type) { - const enum cbfs_type real_type = be32toh(mdata.h.type); - if (*type == CBFS_TYPE_QUERY) - *type = real_type; - else if (*type != real_type) { - ERROR("'%s' type mismatch (is %u, expected %u)\n", - mdata.h.filename, real_type, *type); - return NULL; - } - } + if (check_or_query_type(&mdata, type) != CB_SUCCESS) + return NULL; /* Update the rdev with the preload content */ if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) @@ -571,16 +578,8 @@ void *_cbfs_unverified_area_alloc(const char *area, const char *name, return NULL; } - if (type) { - const enum cbfs_type real_type = be32toh(mdata.h.type); - if (*type == CBFS_TYPE_QUERY) - *type = real_type; - else if (*type != real_type) { - ERROR("'%s' type mismatch (is %u, expected %u)\n", - mdata.h.filename, real_type, *type); - return NULL; - } - } + if (check_or_query_type(&mdata, type) != CB_SUCCESS) + return NULL; if (rdev_chain(&file_rdev, &area_rdev, data_offset, be32toh(mdata.h.len))) return NULL; diff --git a/src/lib/delay.c b/src/lib/delay.c index 25f93acdcb5..7b971593172 100644 --- a/src/lib/delay.c +++ b/src/lib/delay.c @@ -1,15 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include + void mdelay(unsigned int msecs) { - unsigned int i; - for (i = 0; i < msecs; i++) - udelay(1000); + assert(msecs <= UINT_MAX / USECS_PER_MSEC); + return udelay(msecs * USECS_PER_MSEC); } + void delay(unsigned int secs) { - unsigned int i; - for (i = 0; i < secs; i++) - mdelay(1000); + assert(secs <= UINT_MAX / MSECS_PER_SEC); + return mdelay(secs * MSECS_PER_SEC); } diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index b2c1cd491da..64803a490c4 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -54,9 +54,15 @@ uint64_t fw_config_get(void) __func__); } + fw_config_get_mainboard_override(&fw_config_value); + return fw_config_value; } +void __weak fw_config_get_mainboard_override(uint64_t *fw_config) +{ +} + uint64_t fw_config_get_field(const struct fw_config_field *field) { /* If fw_config is not provisioned, then there is nothing to get. */ @@ -72,6 +78,15 @@ uint64_t fw_config_get_field(const struct fw_config_field *field) return value; } +void fw_config_value_set_field(uint64_t *fw_config, + const struct fw_config_field *field, + uint64_t value) +{ + const int shift = __ffs64(field->mask); + *fw_config &= ~field->mask; + *fw_config |= (value << shift) & field->mask; +} + bool __weak fw_config_probe_mainboard_override(const struct fw_config *match, bool *result) { return false; diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index f68cab61c4f..607315d5bb3 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -402,11 +402,10 @@ int LzmaDecode(CLzmaDecoderState *vs, do { RC_NORMALIZE Range >>= 1; - rep0 <<= 1; - if (Code >= Range) { - Code -= Range; - rep0 |= 1; - } + Code -= Range; + UInt32 t = (0 - ((UInt32)Code >> 31)); + rep0 = (rep0 << 1) + (t + 1); + Code += Range & t; } while (--numDirectBits != 0); prob = p + Align; rep0 <<= kNumAlignBits; diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 35b4d7765f3..039b0f4182f 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -257,8 +257,19 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, t->size = 0x7fff; t->extended_size = dimm->dimm_size & 0x7fffffff; } +// If DDR5 memory is used, the definition of the bus_width field in the SPD spec is different from that of DDR4 +#if (CONFIG(DRAM_SUPPORT_DDR5)) + union bus_width_struct bus_width_info; + bus_width_info.raw_data = dimm->bus_width; + uint8_t number_of_subchannel_per_dimm = 1 << bus_width_info.bits.number_of_subchannel_per_dimm; + uint8_t bus_width_ext_per_subchannel = 4 * bus_width_info.bits.bus_width_ext_per_subchannel; + uint8_t primary_bus_width_per_subchan = 8 * 1 << bus_width_info.bits.primary_bus_width_per_subchan; + t->data_width = number_of_subchannel_per_dimm * primary_bus_width_per_subchan; + t->total_width = t->data_width + number_of_subchannel_per_dimm * bus_width_ext_per_subchannel; +#else t->data_width = 8 * (1 << (dimm->bus_width & 0x7)); t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3); +#endif t->form_factor = info.form_factor; smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t); @@ -445,6 +456,11 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level) return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */ } +u8 __weak smbios_cache_speed(u8 level) +{ + return 0; /* Unknown */ +} + /* Returns the processor voltage in 100mV units */ unsigned int __weak smbios_cpu_get_voltage(void) { @@ -583,7 +599,7 @@ int smbios_write_type7(unsigned long *current, t->associativity = associativity; t->supported_sram_type = sram_type; t->current_sram_type = sram_type; - t->cache_speed = 0; /* Unknown */ + t->cache_speed = smbios_cache_speed(level); t->error_correction_type = smbios_cache_error_correction_type(level); t->system_cache_type = type; diff --git a/src/lib/stack.c b/src/lib/stack.c index 6e563db7b7a..ffc0564ff1d 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -26,12 +26,10 @@ it with the version available from LANL. #include #include #include +#include -int checkstack(void *top_of_stack, int core) +int _checkstack(void *top_of_stack, size_t stack_size, int core) { - /* Not all archs use CONFIG_STACK_SIZE, those who don't set it to 0. */ - size_t stack_size = CONFIG_STACK_SIZE ? - CONFIG_STACK_SIZE : REGION_SIZE(stack); int i; u32 *stack = (u32 *) (top_of_stack - stack_size); @@ -58,3 +56,19 @@ int checkstack(void *top_of_stack, int core) return 0; } + +int checkstack(void *top_of_stack, int core) +{ + int ret; + /* Not all archs use CONFIG_STACK_SIZE, those who don't set it to 0. */ + size_t stack_size = CONFIG_STACK_SIZE ? + CONFIG_STACK_SIZE : REGION_SIZE(stack); + + printk(BIOS_SPEW, "Check main stack:\n"); + ret = _checkstack(top_of_stack, stack_size, core); + + if (CONFIG(COOP_MULTITASKING) && ENV_SUPPORTS_COOP) + ret |= thread_check_stacks(); + + return ret; +} diff --git a/src/lib/thread.c b/src/lib/thread.c index 8b58ca0f3ea..ed4f3c958d1 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -3,12 +3,18 @@ #include #include #include +#include +#include #include #include #include #include -static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(sizeof(uint64_t)); +_Static_assert(CONFIG_THREAD_STACK_SIZE > 0, "THREAD_STACK_SIZE is not set"); +_Static_assert(IS_ALIGNED(CONFIG_THREAD_STACK_SIZE, ARCH_STACK_ALIGN_SIZE), + "THREAD_STACK_SIZE is not aligned to ARCH_STACK_ALIGN_SIZE"); + +static u8 thread_stacks[CONFIG_THREAD_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(ARCH_STACK_ALIGN_SIZE); static bool initialized; static void idle_thread_init(void); @@ -21,8 +27,8 @@ static struct thread all_threads[TOTAL_NUM_THREADS]; /* All runnable (but not running) and free threads are kept on their * respective lists. */ -static struct thread *runnable_threads; -static struct thread *free_threads; +static struct list_node runnable_threads; +static struct list_node free_threads; static struct thread *active_thread; @@ -45,25 +51,20 @@ static inline struct thread *current_thread(void) return active_thread; } -static inline int thread_list_empty(struct thread **list) +static inline struct thread *pop_thread(struct list_node *head) { - return *list == NULL; -} + struct list_node *node; -static inline struct thread *pop_thread(struct thread **list) -{ - struct thread *t; + node = list_pop(head); + if (node == NULL) + return NULL; - t = *list; - *list = t->next; - t->next = NULL; - return t; + return container_of(node, struct thread, list_node); } -static inline void push_thread(struct thread **list, struct thread *t) +static inline void push_thread(struct list_node *head, struct thread *t) { - t->next = *list; - *list = t; + list_append(&t->list_node, head); } static inline void push_runnable(struct thread *t) @@ -80,10 +81,9 @@ static inline struct thread *get_free_thread(void) { struct thread *t; - if (thread_list_empty(&free_threads)) - return NULL; - t = pop_thread(&free_threads); + if (t == NULL) + return NULL; /* Reset the current stack value to the original. */ if (!t->stack_orig) @@ -116,9 +116,9 @@ static void schedule(struct thread *t) /* If t is NULL need to find new runnable thread. */ if (t == NULL) { - if (thread_list_empty(&runnable_threads)) - die("Runnable thread list is empty!\n"); t = pop_runnable(); + if (t == NULL) + die("Runnable thread list is empty!\n"); } else { /* current is still runnable. */ push_runnable(current); @@ -232,8 +232,8 @@ thread_yield_timed_callback(struct timeout_callback *tocb, static void *thread_alloc_space(struct thread *t, size_t bytes) { /* Allocate the amount of space on the stack keeping the stack - * aligned to the pointer size. */ - t->stack_current -= ALIGN_UP(bytes, sizeof(uintptr_t)); + * aligned to the architecture requirement. */ + t->stack_current -= ALIGN_UP(bytes, ARCH_STACK_ALIGN_SIZE); return (void *)t->stack_current; } @@ -255,12 +255,15 @@ static void threads_initialize(void) t->id = 0; t->can_yield = 1; - stack_top = &thread_stacks[CONFIG_STACK_SIZE]; + for (i = 0; i < sizeof(thread_stacks) / sizeof(u32); i++) + ((u32 *)thread_stacks)[i] = 0xDEADBEEF; + + stack_top = &thread_stacks[CONFIG_THREAD_STACK_SIZE]; for (i = 1; i < TOTAL_NUM_THREADS; i++) { t = &all_threads[i]; t->stack_orig = (uintptr_t)stack_top; t->id = i; - stack_top += CONFIG_STACK_SIZE; + stack_top += CONFIG_THREAD_STACK_SIZE; free_thread(t); } @@ -355,6 +358,23 @@ int thread_yield_microseconds(unsigned int microsecs) return 0; } +int thread_check_stacks(void) +{ + int i; + int ret = 0; + + if (!initialized) + return 0; + + for (i = 1; i < TOTAL_NUM_THREADS; i++) { + struct thread *t = &all_threads[i]; + printk(BIOS_SPEW, "Check thread %d stack:\n", i); + ret |= _checkstack((void *)t->stack_orig, CONFIG_THREAD_STACK_SIZE, 0); + } + + return ret; +} + void thread_coop_enable(void) { struct thread *current; diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index e25aaec4127..d91e168ad8f 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -18,6 +18,7 @@ static struct timestamp_table *glob_ts_table; static void timestamp_cache_init(struct timestamp_table *ts_cache, uint64_t base) { + ts_cache->tick_freq_mhz = 0; ts_cache->num_entries = 0; ts_cache->base_time = base; ts_cache->max_entries = (REGION_SIZE(timestamp) - diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 9d112db9ea7..7be7136349a 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -6,9 +6,8 @@ chip soc/amd/picasso # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "has_usb2_phy_tune_params" = "1" + register "has_usb2_phy_tune_params" = "true" # Controller0 Port0 Default register "usb_2_port_tune_params[0]" = "{ diff --git a/src/mainboard/amd/bilby/romstage.c b/src/mainboard/amd/bilby/romstage.c index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/amd/bilby/romstage.c +++ b/src/mainboard/amd/bilby/romstage.c @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index f690e5e67a5..89538307eec 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -6,7 +6,7 @@ config BOARD_AMD_BIRMAN_COMMON select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE - select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_CHROMEOS if SOC_AMD_PHOENIX_FSP || SOC_AMD_PHOENIX_OPENSIL select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 21b8607b480..6e57959c9bb 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -2,17 +2,18 @@ config BOARD_AMD_BIRMANPLUS_COMMON def_bool n + select AMD_CRB_FTPM + select MAINBOARD_HAS_TPM2 select BOARD_ROMSIZE_KB_65536 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE select DRIVERS_I2C_GENERIC - select MAINBOARD_HAS_CHROMEOS select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED + select SOC_AMD_COMMON_BLOCK_PSP_SMI select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE - config BOARD_AMD_BIRMANPLUS_PHOENIX select BOARD_AMD_BIRMANPLUS_COMMON select SOC_AMD_PHOENIX_FSP @@ -24,8 +25,6 @@ config BOARD_AMD_BIRMANPLUS_GLINDA if BOARD_AMD_BIRMANPLUS_COMMON config FMDFILE - default "src/mainboard/amd/birman_plus/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMANPLUS_PHOENIX - default "src/mainboard/amd/birman_plus/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMANPLUS_GLINDA default "src/mainboard/amd/birman_plus/board_phoenix.fmd" if BOARD_AMD_BIRMANPLUS_PHOENIX default "src/mainboard/amd/birman_plus/board_glinda.fmd" if BOARD_AMD_BIRMANPLUS_GLINDA @@ -54,28 +53,6 @@ config BIRMANPLUS_MCHP_FW_FILE help The EC firmware blob is at the EC_BODY FMAP region of the firmware image. -config VBOOT - select VBOOT_NO_BOARD_SUPPORT - select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_IN_BOOTBLOCK - -config VBOOT_VBNV_OFFSET - hex - default 0x2A - -config RO_REGION_ONLY - string - depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A - # Add the EFS and EC to the RO region only - # This is a birmanplus specific override of soc/amd/(phoenix | glinda)/Kconfig - default "apu/amdfw apu/ecfw" - -config CHROMEOS - # Use default libpayload config - select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE - # We don't have recovery buttons, so we can't manually enable devmode. - select GBB_FLAG_FORCE_DEV_SWITCH_ON - config ENABLE_EVAL_CARD bool "Enable Eval Card" help @@ -127,7 +104,7 @@ endchoice if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE - default 3 # Quad IO (1-1-4) + default 5 # Quad IO (1-4-4) config EFS_SPI_SPEED default 0 # 66MHz diff --git a/src/mainboard/amd/birman_plus/Makefile.mk b/src/mainboard/amd/birman_plus/Makefile.mk index c025591115a..939b64b2afb 100644 --- a/src/mainboard/amd/birman_plus/Makefile.mk +++ b/src/mainboard/amd/birman_plus/Makefile.mk @@ -7,7 +7,6 @@ bootblock-y += ec.c romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_GLINDA) += port_descriptors_glinda.c -ramstage-y += chromeos.c ramstage-y += gpio.c ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors_phoenix.c ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_GLINDA) += port_descriptors_glinda.c diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd index 96e1e8d8f08..93db689b522 100644 --- a/src/mainboard/amd/birman_plus/board_glinda.fmd +++ b/src/mainboard/amd/birman_plus/board_glinda.fmd @@ -4,6 +4,8 @@ FLASH 64M { FMAP 4K COREBOOT(CBFS) SMMSTORE(PRESERVE) 256K + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K EC_BODY@15872K 256K RW_MRC_CACHE 256K } diff --git a/src/mainboard/amd/birman_plus/board_phoenix.fmd b/src/mainboard/amd/birman_plus/board_phoenix.fmd index 13354094184..df2d485b0ae 100644 --- a/src/mainboard/amd/birman_plus/board_phoenix.fmd +++ b/src/mainboard/amd/birman_plus/board_phoenix.fmd @@ -3,6 +3,8 @@ FLASH 64M { EC_SIG 4K FMAP 4K COREBOOT(CBFS) + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K EC_BODY@15872K 256K RW_MRC_CACHE 256K } diff --git a/src/mainboard/amd/birman_plus/chromeos.c b/src/mainboard/amd/birman_plus/chromeos.c deleted file mode 100644 index 515da94df16..00000000000 --- a/src/mainboard/amd/birman_plus/chromeos.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = {}; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_write_protect_state(void) -{ - /* Birman doesn't have a write protect pin */ - return 0; -} - -DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd deleted file mode 100644 index de5bcc788fb..00000000000 --- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd +++ /dev/null @@ -1,35 +0,0 @@ -FLASH 64M { - SI_BIOS 16M { - WP_RO 8M { - EC_SIG 4K - RO_VPD(PRESERVE) 16K - RO_SECTION { - FMAP 2K - RO_FRID 64 - COREBOOT(CBFS) - GBB 448K - } - } - RW_SECTION_A 3M { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 256 - } - RW_SECTION_B 3M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 256 - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 256K - RW_LEGACY(CBFS) - EC_BODY@15872K 256K - RW_MRC_CACHE(PRESERVE) 256K - } -} diff --git a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd deleted file mode 100644 index de5bcc788fb..00000000000 --- a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd +++ /dev/null @@ -1,35 +0,0 @@ -FLASH 64M { - SI_BIOS 16M { - WP_RO 8M { - EC_SIG 4K - RO_VPD(PRESERVE) 16K - RO_SECTION { - FMAP 2K - RO_FRID 64 - COREBOOT(CBFS) - GBB 448K - } - } - RW_SECTION_A 3M { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 256 - } - RW_SECTION_B 3M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 256 - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 256K - RW_LEGACY(CBFS) - EC_BODY@15872K 256K - RW_MRC_CACHE(PRESERVE) 256K - } -} diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 2027d5b6c06..481d7295389 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -207,9 +207,15 @@ chip soc/amd/glinda chip drivers/usb/acpi device ref xhci_1_root_hub on chip drivers/usb/acpi + register "desc" = ""USB-3.2-A-Port1 Vertical"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(7, 0)" device ref usb3_port7 on end end chip drivers/usb/acpi + register "desc" = ""USB-3.2-A-Port1 Vertical"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(7, 0)" device ref usb2_port7 on end end end @@ -222,24 +228,45 @@ chip soc/amd/glinda chip drivers/usb/acpi device ref xhci_0_root_hub on chip drivers/usb/acpi + register "desc" = ""USBC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 0)" device ref usb3_port2 on end end chip drivers/usb/acpi + register "desc" = ""USB-3.2-A-Port0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 0)" device ref usb3_port3 on end end chip drivers/usb/acpi + register "desc" = ""USBC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 0)" device ref usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""USB-3.2-A-Port0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 0)" device ref usb2_port3 on end end chip drivers/usb/acpi + register "desc" = ""USB-A 2.0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 0)" device ref usb2_port4 on end end chip drivers/usb/acpi + register "desc" = ""GbE/FingerPrint"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(5, 0)" device ref usb2_port5 on end end chip drivers/usb/acpi + register "desc" = ""BT/Touch"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(6, 0)" device ref usb2_port6 on end end end @@ -250,9 +277,15 @@ chip soc/amd/glinda chip drivers/usb/acpi device ref usb4_xhci_0_root_hub on chip drivers/usb/acpi + register "desc" = ""USBC0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb3_port0 on end end chip drivers/usb/acpi + register "desc" = ""USBC0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb2_port0 on end end end @@ -263,9 +296,15 @@ chip soc/amd/glinda register "type" = "UPC_TYPE_HUB" device ref usb4_xhci_1_root_hub on chip drivers/usb/acpi + register "desc" = ""USBC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 0)" device ref usb3_port1 on end end chip drivers/usb/acpi + register "desc" = ""USBC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 0)" device ref usb2_port1 on end end end diff --git a/src/mainboard/amd/crater/APCB_RN_D4_DefaultRecovery_32GB_DRAM_512MB_VRAM.apcb b/src/mainboard/amd/crater/APCB_RN_D4_DefaultRecovery_32GB_DRAM_512MB_VRAM.apcb new file mode 100644 index 00000000000..34bebc0e8b7 Binary files /dev/null and b/src/mainboard/amd/crater/APCB_RN_D4_DefaultRecovery_32GB_DRAM_512MB_VRAM.apcb differ diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig index 0861a216f73..ce37a3960e3 100644 --- a/src/mainboard/amd/crater/Kconfig +++ b/src/mainboard/amd/crater/Kconfig @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -config BOARD_AMD_CRATER_COMMON - def_bool n +if BOARD_AMD_CRATER + +config BOARD_SPECIFIC_OPTIONS + def_bool y select BOARD_ROMSIZE_KB_16384 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD @@ -9,53 +11,43 @@ config BOARD_AMD_CRATER_COMMON select DRIVERS_I2C_HID select MAINBOARD_HAS_CHROMEOS select HAVE_ACPI_RESUME - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE + select SOC_AMD_ACP_KEEP_RUNNING_IN_S3 select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE select SOC_AMD_COMMON_BLOCK_PSP_RPMC select SOC_AMD_COMMON_BLOCK_PSP_SMI - select KEEP_ACP_RUNNING_IN_S3 - -config BOARD_AMD_CRATER_RENOIR - select BOARD_AMD_CRATER_COMMON - select SOC_AMD_RENOIR - -if BOARD_AMD_CRATER_RENOIR + select SOC_AMD_V2000A + select PSP_INIT_ESPI config FMDFILE - default "src/mainboard/amd/crater/chromeos_renoir.fmd" if CHROMEOS - default "src/mainboard/amd/crater/board_renoir.fmd" + default "src/mainboard/amd/crater/chromeos_v2000a.fmd" if CHROMEOS + default "src/mainboard/amd/crater/board_v2000a_ab.fmd" if PSP_AB_RECOVERY + default "src/mainboard/amd/crater/board_v2000a.fmd" config MAINBOARD_DIR default "amd/crater" config MAINBOARD_PART_NUMBER - default "Crater_RENOIR" + default "Crater_V2000A" config DEVICETREE - default "devicetree_renoir.cb" + default "devicetree_v2000a.cb" + +config AMD_SOC_CONSOLE_UART + default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD config CRATER_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n -config AMD_SOC_CONSOLE_UART - default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD - config CRATER_MCHP_FW_FILE string "Microchip EC firmware file" depends on CRATER_HAVE_MCHP_FW - default "3rdparty/blobs/mainboard/amd/crater/EcSig_Crater.bin" + default "3rdparty/blobs/mainboard/amd/crater/CeladonEC.bin" help The EC firmware blob is at the EC_BODY FMAP region of the firmware image. -config PSP_RECOVERY_AB - default y - config VBOOT select VBOOT_NO_BOARD_SUPPORT select VBOOT_SEPARATE_VERSTAGE @@ -200,4 +192,4 @@ config TPM_SPI_SPEED endif # !EM100 -endif # BOARD_AMD_CRATER_COMMON +endif # BOARD_AMD_CRATER diff --git a/src/mainboard/amd/crater/Kconfig.name b/src/mainboard/amd/crater/Kconfig.name index e49afa5de65..5e129086935 100644 --- a/src/mainboard/amd/crater/Kconfig.name +++ b/src/mainboard/amd/crater/Kconfig.name @@ -1,4 +1,4 @@ comment "Crater" -config BOARD_AMD_CRATER_RENOIR - bool "-> Crater for Renoir SoC" +config BOARD_AMD_CRATER + bool "-> Crater for V2000A SoC" diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk index 8380fc6fef6..a6b09a09749 100644 --- a/src/mainboard/amd/crater/Makefile.mk +++ b/src/mainboard/amd/crater/Makefile.mk @@ -5,19 +5,15 @@ bootblock-y += early_gpio.c bootblock-y += ec.c romstage-y += ec.c -romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c +romstage-y += port_descriptors_v2000a.c ramstage-y += chromeos.c ramstage-y += gpio.c ramstage-y += ec.c -ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c +ramstage-y += port_descriptors_v2000a.c -ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),) -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin -APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_DefaultRecovery.bin -else -show_notices:: warn_no_apcb -endif +# APCB_SOURCES is empty, since we don't need to update APCB settings from the running system +APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/APCB_RN_D4_DefaultRecovery_32GB_DRAM_512MB_VRAM.apcb ifeq ($(CONFIG_CRATER_HAVE_MCHP_FW),y) subdirs-y += ../../../../util/mec152x diff --git a/src/mainboard/amd/crater/board_renoir.fmd b/src/mainboard/amd/crater/board_v2000a.fmd similarity index 86% rename from src/mainboard/amd/crater/board_renoir.fmd rename to src/mainboard/amd/crater/board_v2000a.fmd index f3606246d26..94617800bb7 100644 --- a/src/mainboard/amd/crater/board_renoir.fmd +++ b/src/mainboard/amd/crater/board_v2000a.fmd @@ -3,6 +3,7 @@ FLASH 16M { EC_SIG 4K FMAP 4K COREBOOT(CBFS) + SMMSTORE(PRESERVE) 256K PSP_NVRAM(PRESERVE) 128K PSP_RPMC_NVRAM(PRESERVE) 256K EC_BODY@15872K 256K diff --git a/src/mainboard/amd/crater/board_v2000a_ab.fmd b/src/mainboard/amd/crater/board_v2000a_ab.fmd new file mode 100644 index 00000000000..f752d2fb564 --- /dev/null +++ b/src/mainboard/amd/crater/board_v2000a_ab.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + BIOS { + EC_SIG 4K + FMAP 4K + PSP_AB_NVRAM(PRESERVE) 4K + EFS@128K 128K + RECOVERY_A 7M { + BOOTBLOCK(CBFS) 2M + COREBOOT(CBFS) + } + RECOVERY_B 7M { + BOOTBLOCK_B(CBFS) 2M + COREBOOT_B(CBFS) + } + SMMSTORE(PRESERVE) 256K + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + EC_BODY@16000K 256K + RW_MRC_CACHE 120K + } +} diff --git a/src/mainboard/amd/crater/chromeos_renoir.fmd b/src/mainboard/amd/crater/chromeos_v2000a.fmd similarity index 100% rename from src/mainboard/amd/crater/chromeos_renoir.fmd rename to src/mainboard/amd/crater/chromeos_v2000a.fmd diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_v2000a.cb similarity index 91% rename from src/mainboard/amd/crater/devicetree_renoir.cb rename to src/mainboard/amd/crater/devicetree_v2000a.cb index 33f25e9c295..782781d3db0 100644 --- a/src/mainboard/amd/crater/devicetree_renoir.cb +++ b/src/mainboard/amd/crater/devicetree_v2000a.cb @@ -19,7 +19,6 @@ chip soc/amd/cezanne # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec # ACP Configuration register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_I2S_TDM" @@ -58,14 +57,16 @@ chip soc/amd/cezanne device domain 0 on device ref iommu on end - device ref gpp_gfx_bridge_0 on end #GFX - device ref gpp_gfx_bridge_1 on end + device ref gpp_gfx_bridge_0 on end # MXM + device ref gpp_gfx_bridge_1 on end # DT if CONFIG(PCIE_DT_SLOT) + device ref gpp_gfx_bridge_2 on end # WWAN if CONFIG(XGBE_WWAN_WLAN) device ref gpp_bridge_0 off end - device ref gpp_bridge_1 off end - device ref gpp_bridge_2 on end + device ref gpp_bridge_1 on end # WLAN if CONFIG(XGBE_WWAN_WLAN) + device ref gpp_bridge_2 on end # TB if CONFIG(XGBE_WWAN_WLAN) device ref gpp_bridge_3 on end # NVME device ref gpp_bridge_4 off end device ref gpp_bridge_5 off end + device ref gpp_bridge_6 off end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # gfx_hda @@ -73,12 +74,6 @@ chip soc/amd/cezanne device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on - chip drivers/usb/acpi - device ref usb3_port0 on end - end - chip drivers/usb/acpi - device ref usb3_port1 on end - end chip drivers/usb/acpi device ref usb2_port0 on end end @@ -91,18 +86,18 @@ chip soc/amd/cezanne chip drivers/usb/acpi device ref usb2_port3 on end end + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb3_port1 on end + end end end end device ref xhci_1 on # USB 3.1 (USB1) chip drivers/usb/acpi device ref xhci_1_root_hub on - chip drivers/usb/acpi - device ref usb3_port4 on end - end - chip drivers/usb/acpi - device ref usb3_port5 on end - end chip drivers/usb/acpi device ref usb2_port4 on end end @@ -115,6 +110,12 @@ chip soc/amd/cezanne chip drivers/usb/acpi device ref usb2_port7 on end end + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end end end end diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c index 442782e1d49..4370f9a83ab 100644 --- a/src/mainboard/amd/crater/ec.c +++ b/src/mainboard/amd/crater/ec.c @@ -214,7 +214,7 @@ void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_ ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); for (index = 0; index < MACID_LEN; index++) { value = ec_read(offset + index); - printk(BIOS_SPEW, "READ MACID REG 0x%2x Value 0x%02x\n", offset - index, value); + printk(BIOS_SPEW, "READ MACID REG 0x%2x Value 0x%02x\n", offset + index, value); if (index < 6) { port0_mac = (port0_mac << 8) | value; diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_v2000a.c similarity index 100% rename from src/mainboard/amd/crater/port_descriptors_renoir.c rename to src/mainboard/amd/crater/port_descriptors_v2000a.c diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/jaguar/APCB_FP8_LPDDR5_DefaultRecovery.apcb b/src/mainboard/amd/jaguar/APCB_FP8_LPDDR5_DefaultRecovery.apcb new file mode 100644 index 00000000000..394d6cabb33 Binary files /dev/null and b/src/mainboard/amd/jaguar/APCB_FP8_LPDDR5_DefaultRecovery.apcb differ diff --git a/src/mainboard/amd/jaguar/Kconfig b/src/mainboard/amd/jaguar/Kconfig new file mode 100644 index 00000000000..18d8c0a4dbd --- /dev/null +++ b/src/mainboard/amd/jaguar/Kconfig @@ -0,0 +1,457 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AMD_JAGUAR + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_FAEGAN + select BOARD_ROMSIZE_KB_32768 + select EC_ACPI + select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE + select MB_COMPRESS_RAMSTAGE_ZSTD + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + select SOC_AMD_COMMON_BLOCK_PSP_RPMC + select AMD_CRB_FTPM + select SOC_AMD_COMMON_BLOCK_PSP_SMI + select SMBIOS_TYPE4_SOCKETED_CPU + select SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH + select SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX + +config FMDFILE + default "src/mainboard/amd/jaguar/board_faegan_ab.fmd" if PSP_AB_RECOVERY + default "src/mainboard/amd/jaguar/board_faegan.fmd" + +config BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT + default 2 + +config PSP_LOAD_MP2_FW + prompt "Load MP2 Firmware" + default n + +config MAINBOARD_DIR + default "amd/jaguar" + +config MAINBOARD_PART_NUMBER + default "Jaguar_Faegan" + +config DEVICETREE + default "devicetree_faegan.cb" + +config JAGUAR_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config AMD_SOC_CONSOLE_UART + default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + +config JAGUAR_MCHP_FW_FILE + string "Microchip EC firmware file" + depends on JAGUAR_HAVE_MCHP_FW + help + The EC firmware blob is at the EC_BODY FMAP region of the firmware image. + +config ENABLE_EVAL_CARD + bool "Enable Eval Card" + help + Enable the Eval Card PCIe slot. + +choice + prompt "Force Power on GPP0" + default DISABLE_FORCE_POWER_GPP0 + depends on ENABLE_EVAL_CARD + help + Turn it off/on to disable/enable the force power for bifurcation. + +config DISABLE_FORCE_POWER_GPP0 + bool "Disable Force Power on PCIe Slot-0 (GPP0)" + +config ENABLE_FORCE_POWER_GPP0 + bool "Enable Force Power on PCIe Slot-0 (GPP0)" +endchoice + +choice + prompt "GPP0 Slot as x8/x4 Lanes" + default PCIE_SLOT0_1X8 + depends on ENABLE_EVAL_CARD + help + Either PCIe Slot-0 As 1(x8), PCIe Slot-0 As 2(x4). + +config PCIE_SLOT0_1X8 + bool "Enable PCIe Slot-0 as 1(x8), Turn off force power" + +config PCIE_SLOT0_2X4 + bool "Enable PCIe Slot-0 as 2(x4), Turn on force power" +endchoice + +choice + prompt "WLAN/M.2 SSD0 ENABLE" + default ENABLE_NVME_4LANES + help + Either M.2 SSD0, WLAN X2 or PCIe Slot 1 can be used, as they are sharing PCIe lanes. + +config ENABLE_NVME_4LANES + bool "Enable M.2 NVMe SSD0 x4 Lanes" + +config ENABLE_PCIE_4LANES + bool "Enable PCIe slot 1 with x4 Lanes" + +config ENABLE_NVME_PCIE_2LANES + bool "Enable both x2 NVMe and x2 PCIe slot 1" + +config ENABLE_NVME_WLAN_2LANES + bool "Enable both X2 NVMe and x2 WLAN" +endchoice + +config ENABLE_S0I3_SUPPORT + bool "S0i3 support" + default y + help + Apply quirks to allow board to enter S0i3. + +choice + prompt "Slot2 xGBE/PCIe" + default XGBE_EN + help + Must match board configuration. The mainboard can be reworked to support either + xGBE or GPP2 on PCIe lanes 4+5, but not both. +config XGBE_EN + bool "XGBE Enablement" + depends on !ENABLE_S0I3_SUPPORT + help + The mainboard has been reworked to support xGBE on PCIe lanes 4+5. + +config GPP2_EN + bool "GPP2 Enablement" + help + The mainboard uses PCIe lanes 4+5 for GPP2 (PCIe Slot2) instead of xGBE. +endchoice + +choice + prompt "XGBE_PORT_CONNECTIONTYPE" + depends on XGBE_EN + default XGBE_BACKPLANE_CONNECTION + help + Select to XGBE Port Connector type eith BACKPLANE Connection or SFP Plus Connection. + +config XGBE_BACKPLANE_CONNECTION + bool "XGBE BACKPLANE Enablement" + help + Set select xgbe BACKPLANE. + +config XGBE_SFP_PLUS_CONNECTION + bool "XGBE SFP PLUS Connection Enablement" + help + XGBE SFP PLUS Connection Enablement. Needs board rework as MDIO is by default + not routed to SFP+ connectors. +endchoice + +choice + prompt "XGBE PORT PLATFORM CONFIG" + default XGBE_10G_1G_BACKPLANE + depends on XGBE_BACKPLANE_CONNECTION + help + Select to Use 10G/1G Backplane an on modes. + +config XGBE_10G_1G_BACKPLANE + bool "XGBE XGBE_10G_1G_BACKPLANE" + help + Select to Use 10G/1G Backplane an on modes. + +config XGBE_2_5G_BACKPLANE + bool "XGBE XGBE_2_5G_BACKPLANE" + help + Select to Use 2.5 G Backplane an of modes. + +config XGBE_PORT_SGMII_BACKPLANE + bool "XGBE XGBE_PORT_SGMII_BACKPLANE" + help + Select to Use all speeed with Backplane an of modes. + +config XGBE_SFP_PLUS_CONNECTOR + bool "XGBE XGBE_SFP_PLUS_CONNECTOR" + help + Select to Use 10M/100M/1000M with SGMI modes 10G with SFI mode. +endchoice + +choice + prompt "Xgbe port speed" + depends on XGBE_BACKPLANE_CONNECTION || XGBE_SFP_PLUS_CONNECTION + default XGBE_PORT_SPEED_10G + +config XGBE_PORT_SPEED_10G + bool "10G Port Speed" + help + Set Xgbe port speed to support 10GBps. + +config XGBE_PORT_SPEED_10_100_1000M + bool "10/100/1000MB" + help + Set Xgbe port speed to support 10/100/1000MB. + +config XGBE_PORT_SPEED_10M + bool "10MB Port Speed" + help + Set Xgbe port speed to support 10MBps. + +config XGBE_PORT_SPEED_100M + bool "100 MBps port speed" + help + Set Xgbe port speed to support 1000MBps. + +config XGBE_PORT_SPEED_1G + bool "1G Port Speed" + help + Set Xgbe port speed to support 1GBps. + +config XGBE_PORT_SPEED_2500M + bool "2500M Port Speed" + help + Set Xgbe port speed to support 2.5GBps. +endchoice + +menu "XGBE LED Options" + +choice + prompt "XGBE LED Enable" + default XGBE_LED_TURN_ON + depends on XGBE_EN + help + Turn XGBE LED on or off. + +config XGBE_LED_TURN_OFF + bool "Turn Off XGBE Led" + help + Turn Off XGBE LEDs. UART2 and UART4 are usable. + +config XGBE_LED_TURN_ON + bool "Turn On XGBE Led" + help + Turn On XGBE LEDs. Disables UART2 and UART4. +endchoice + +choice + prompt "XGBE PORT-0 Link Status LED" + depends on XGBE_LED_TURN_ON + default TURN_ON_PORT_0_LINK_STATUS_LED + help + Enable or Disable Link Status LED. + +config TURN_ON_PORT_0_LINK_STATUS_LED + bool "Enable" + help + Turn On link status LED. + +config TURN_OFF_PORT_0_LINK_STATUS_LED + bool "Disable" + help + Turn Off link status LED. +endchoice + +choice + prompt "XGBE PORT-0 Link Speed LED" + depends on XGBE_LED_TURN_ON + default TURN_ON_PORT_0_LINK_SPEED_LED + help + Enable Disable Link Status LED. + +config TURN_ON_PORT_0_LINK_SPEED_LED + bool "Enable" + help + Turn On link speed LED. + +config TURN_OFF_PORT_0_LINK_SPEED_LED + bool "Disable" + help + Turn Off link speed LED. +endchoice + +choice + prompt "XGBE PORT-0 TX/RX LED blink rate" + depends on XGBE_LED_TURN_ON + default PORT_0_TX_RX_LED_BLINK_RATE_170 + help + choose TX RX LED blink rate. + +config PORT_0_TX_RX_LED_BLINK_RATE_42 + bool "42ms" + help + blink at 42ms on and 42ms off. + +config PORT_0_TX_RX_LED_BLINK_RATE_84 + bool "84ms" + help + blink at 84ms on and 84ms off. + +config PORT_0_TX_RX_LED_BLINK_RATE_170 + bool "170ms" + help + blink at 170ms on and 170ms Off. + +config PORT_0_TX_RX_LED_BLINK_RATE_340 + bool "340ms" + help + blink at 340ms on and 340ms off. +endchoice + +choice + prompt "XGBE PORT-1 Link Status LED" + depends on XGBE_LED_TURN_ON + default TURN_ON_PORT_1_LINK_STATUS_LED + help + Enable or Disable Link Status LED. + +config TURN_ON_PORT_1_LINK_STATUS_LED + bool "Enable" + help + Turn On link status LED. + +config TURN_OFF_PORT_1_LINK_STATUS_LED + bool "Disable" + help + Turn Off link status LED. +endchoice + +choice + prompt "XGBE PORT-1 Link Speed LED" + depends on XGBE_LED_TURN_ON + default TURN_ON_PORT_1_LINK_SPEED_LED + help + Enable or Disable Link Status LED. + +config TURN_ON_PORT_1_LINK_SPEED_LED + bool "Enable" + help + Turn On link speed LED. + +config TURN_OFF_PORT_1_LINK_SPEED_LED + bool "Disable" + help + Turn Off link speed LED. +endchoice + +choice + prompt "XGBE PORT-1 TX/RX LED blink rate" + depends on XGBE_LED_TURN_ON + default PORT_1_TX_RX_LED_BLINK_RATE_170 + help + choose TX RX LED blink rate. + +config PORT_1_TX_RX_LED_BLINK_RATE_42 + bool "42ms" + help + blink at 42ms on and 42ms off. + +config PORT_1_TX_RX_LED_BLINK_RATE_84 + bool "84ms" + help + blink at 84ms on and 84ms off. + +config PORT_1_TX_RX_LED_BLINK_RATE_170 + bool "170ms" + help + blink at 170ms on and 170ms Off. + +config PORT_1_TX_RX_LED_BLINK_RATE_340 + bool "340ms" + help + blink at 340ms on and 340ms off. +endchoice + +endmenu + +config PORT_1_TX_RX_LED_BLINK_RATE + int + default 0 if PORT_1_TX_RX_LED_BLINK_RATE_42 + default 1 if PORT_1_TX_RX_LED_BLINK_RATE_84 + default 2 if PORT_1_TX_RX_LED_BLINK_RATE_170 + default 3 if PORT_1_TX_RX_LED_BLINK_RATE_340 + help + Map the Port 1 Tx/Rx Blink rate to an integer. + +config PORT_0_TX_RX_LED_BLINK_RATE + int + default 0 if PORT_0_TX_RX_LED_BLINK_RATE_42 + default 1 if PORT_0_TX_RX_LED_BLINK_RATE_84 + default 2 if PORT_0_TX_RX_LED_BLINK_RATE_170 + default 3 if PORT_0_TX_RX_LED_BLINK_RATE_340 + help + Map the Port 0 Tx/Rx Blink rate to an integer. + +choice + prompt "Uart Mode" + default UART_0_1_2_3_TWO_WIRE + help + Select Uart Mode. + Note: Enabling XGBE LED affects the Uart 2 and Uart 4. + So please turn off to collect logs from UART2 & 4. + +config UART_0_2_4_FOUR_WIRE + bool "3x4 Wire" + help + Uart 0,2,4 in Four wire Mode + +config UART_0_1_2_3_TWO_WIRE + bool "4x2 Wire and 1x4 wire" + help + Uart 0,1,2,3 in Two wire Mode and Uart 4 in Four wire Mode. +endchoice + +choice + prompt "I3C/I2C Configuration" + default I2C_ENABLE + help + Select either I2C or I3C. + +config I2C_ENABLE + bool "I2C" + help + Enable I2C. + +config I3C_ENABLE + depends on !ENABLE_S0I3_SUPPORT + bool "I3C" + help + Enable I3C. +endchoice + +choice + prompt "Select DP4 as TypeC / HDMI display" + default DISPLAY_PORT_TYPEC + help + Enable USBC3/DP4 as TypeC display or HDMI display. + Note that enabling the DISPLAY_PORT_HDMI option is not going to be enough to use it. + Hardware rework also needs to be done as per schematic. + +config DISPLAY_PORT_TYPEC + bool "Enable TYPEC" + +config DISPLAY_PORT_HDMI + bool "Enable HDMI" +endchoice + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig + +config EFS_SPI_READ_MODE + default 5 # Quad IO (1-4-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_JAGUAR diff --git a/src/mainboard/amd/jaguar/Kconfig.name b/src/mainboard/amd/jaguar/Kconfig.name new file mode 100644 index 00000000000..6853d3d713d --- /dev/null +++ b/src/mainboard/amd/jaguar/Kconfig.name @@ -0,0 +1,4 @@ +comment "Jaguar" + +config BOARD_AMD_JAGUAR + bool "-> Jaguar for Faegan SoC" diff --git a/src/mainboard/amd/jaguar/Makefile.mk b/src/mainboard/amd/jaguar/Makefile.mk new file mode 100644 index 00000000000..23578083761 --- /dev/null +++ b/src/mainboard/amd/jaguar/Makefile.mk @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +bootblock-y += ec.c + +romstage-y += port_descriptors.c + +ramstage-y += gpio.c +ramstage-y += port_descriptors.c + +APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/APCB_FP8_LPDDR5_DefaultRecovery.apcb + +ifeq ($(CONFIG_JAGUAR_HAVE_MCHP_FW),y) +subdirs-y += ../../../../util/mec152x + +$(call add_intermediate, add_mchp_fw, $(objutil)/mec152x/mec152xtool) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_JAGUAR_MCHP_FW_FILE) --fill-upward + $(objutil)/mec152x/mec152xtool $(obj)/coreboot.pre GEN_ECFW_PTR -f EC_BODY +else +files_added:: warn_no_mchp +endif # CONFIG_JAGUAR_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the EC FW.\n" + printf "Do not flash this image. Your Jaguar's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/jaguar/acpi/ec.asl b/src/mainboard/amd/jaguar/acpi/ec.asl new file mode 100644 index 00000000000..e257017ee70 --- /dev/null +++ b/src/mainboard/amd/jaguar/acpi/ec.asl @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "ec.h" + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) // ACPI Embedded Controller + Name (_UID, 0) + Name (_GPE, 10) + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, JAGUAR_EC_DATA, JAGUAR_EC_DATA, 1, 1) + IO (Decode16, JAGUAR_EC_CMD, JAGUAR_EC_CMD, 1, 1) + }) + + // Access once OKEC returns 1 + OperationRegion (RAM, EmbeddedControl, 0, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + Offset(EC_M2_POWER), + MPWR, 1, + , 3, + MRST, 1, + Offset(EC_PAGE_SELECT), + PAGE, 8, + } + + // OKEC returns 1 once the EmbeddedControl OS driver has been loaded + Name(OKEC, Zero) + + // OS runs _REG control on change in the availability of OpRegion + Method (_REG, 2) + { + If (Arg0 == 3) // EmbeddedControl + { + OKEC = Arg1 // 1: Loaded, 0: Unloaded + } + } +} + +Scope (\_SB.PCI0.GP11) +{ + // Hint OS about dependency to EC + Name (_DEP, Package (0x01) + { + \_SB.PCI0.LPCB.EC0 + }) + + Name (_PR0, Package (0x01) + { + PR00 + }) + Name (_PR3, Package (0x01) + { + PR00 + }) + PowerResource (PR00, 0, 0) + { + Method (_STA, 0, NotSerialized) + { + // Opt out when EC not ready yet + If (\_SB.PCI0.LPCB.EC0.OKEC == 0) + { + Debug = "_STA returns 0" + Return (Zero) + } + + \_SB.PCI0.LPCB.EC0.PAGE = EC_GPIO_PAGE + Local0 = \_SB.PCI0.LPCB.EC0.MPWR + Local1 = \_SB.PCI0.LPCB.EC0.MRST + Local0 &= Local1 + If (Local0) + { + Debug = "_STA returns 1" + } Else { + Debug = "_STA returns 0" + } + Return (Local0) + } + + Method (_ON, 0, NotSerialized) + { + // Opt out when EC not ready yet + If (\_SB.PCI0.LPCB.EC0.OKEC == 0) + { + Return () + } + If (_STA () == One) + { + Return () + } + + \_SB.PCI0.LPCB.EC0.PAGE = EC_GPIO_PAGE + + \_SB.PCI0.LPCB.EC0.MPWR = One + Sleep (10) + \_SB.PCI0.LPCB.EC0.MRST = One + Sleep (100) + Debug = "_ON method called" + } + + Method (_OFF, 0, NotSerialized) + { + // Opt out when EC not ready yet + If (\_SB.PCI0.LPCB.EC0.OKEC == 0) + { + Return () + } + If (_STA () == Zero) + { + Return () + } + + \_SB.PCI0.LPCB.EC0.PAGE = EC_GPIO_PAGE + + \_SB.PCI0.LPCB.EC0.MRST = Zero + \_SB.PCI0.LPCB.EC0.MPWR = Zero + Sleep (10) + Debug = "_OFF method called" + } + } +} diff --git a/src/mainboard/amd/jaguar/board_faegan.fmd b/src/mainboard/amd/jaguar/board_faegan.fmd new file mode 100644 index 00000000000..11a34be2f4d --- /dev/null +++ b/src/mainboard/amd/jaguar/board_faegan.fmd @@ -0,0 +1,12 @@ +FLASH@0 32M { + BIOS 16M { + EC_SIG 4K + FMAP 4K + COREBOOT(CBFS) + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + SMMSTORE(PRESERVE) 256K + EC_BODY 256K + RW_MRC_CACHE 256K + } +} diff --git a/src/mainboard/amd/jaguar/board_faegan_ab.fmd b/src/mainboard/amd/jaguar/board_faegan_ab.fmd new file mode 100644 index 00000000000..0fc3539b683 --- /dev/null +++ b/src/mainboard/amd/jaguar/board_faegan_ab.fmd @@ -0,0 +1,20 @@ +FLASH@0 32M { + BIOS 16M { + EC_SIG 4K + FMAP 4K + EFS @128K 128K + RECOVERY_A 6656K { + BOOTBLOCK(CBFS) 4224K + COREBOOT(CBFS) + } + RECOVERY_B 6656K { + BOOTBLOCK_B(CBFS) 4224K + COREBOOT_B(CBFS) + } + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + SMMSTORE(PRESERVE) 256K + EC_BODY 256K + RW_MRC_CACHE 256K + } +} diff --git a/src/mainboard/amd/jaguar/board_info.txt b/src/mainboard/amd/jaguar/board_info.txt new file mode 100644 index 00000000000..b351b8e696f --- /dev/null +++ b/src/mainboard/amd/jaguar/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/jaguar/bootblock.c b/src/mainboard/amd/jaguar/bootblock.c new file mode 100644 index 00000000000..9c5586277b4 --- /dev/null +++ b/src/mainboard/amd/jaguar/bootblock.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ec.h" +#include "gpio.h" + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + espi_switch_to_spi1_pads(); +} + +void bootblock_mainboard_init(void) +{ + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD)) + jaguar_ec_init(); +} diff --git a/src/mainboard/amd/jaguar/devicetree_faegan.cb b/src/mainboard/amd/jaguar/devicetree_faegan.cb new file mode 100644 index 00000000000..1a5d955d012 --- /dev/null +++ b/src/mainboard/amd/jaguar/devicetree_faegan.cb @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/glinda + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "system_configuration" = "5" + + register "slow_ppt_limit_mW" = "45000" + register "fast_ppt_limit_mW" = "45000" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "i2c[0].early_init" = "1" + register "i2c[1].early_init" = "1" + register "i2c[2].early_init" = "1" + register "i2c[3].early_init" = "1" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + # Sleep button is advertised in ACPI + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" + + # ACP Configuration + register "common_config.acp_config.acp_pin_cfg" = "ACP_PINS_I2S" + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + + register "usb_phy_custom" = "1" + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[1] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[2] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[3] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[4] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[5] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x6, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x6, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb3PhyPort[0] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_DPM, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_DPM, + .ComboPhyStaticConfig[2] = CONFIG(DISPLAY_PORT_TYPEC) ? USB_COMBO_PHY_MODE_USB_C : + USB_COMBO_PHY_MODE_USB_DPM, + }" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # M.2 SSD + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # Slot 1 + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # Slot 2 + register "gpp_clk_config[4]" = "GPP_CLK_ON" # MXM/Slot 0 (#TODO test bifurcation with GPP_CLK_REQ) + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_2_1 on # NVMe SSD0 + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end + device ref gpp_bridge_2_2 on end # PCIe Slot 1 + device ref gpp_bridge_2_3 on end # WLAN + device ref gpp_bridge_2_4 on end # PCIe Slot 2 + device ref gpp_bridge_3_1 on end # MXM/PCIe Slot 0 (DISABLE_FORCE_POWER_GPP0 && PCIE_SLOT0_1X8) + device ref gpp_bridge_3_2 on end # Bifurcation Slot 0 (ENABLE_FORCE_POWER_GPP0, PCIE_SLOT0_2X4) + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port7 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + end + # + # if gpp_bridge_b secondary bus is not configured , + # edk2 payload skipping enumerating gpp_bridge_c and no XHCI devices detected + # + device ref gpp_bridge_b on + device ref xgbe_0 on end # XGBE0 + device ref xgbe_1 on end # XGBE1 + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + # I2C and I3C are conflicting. Fixed in mainboard code at runtime. + device ref i3c_0 on end + device ref i3c_1 on end + device ref i3c_2 on end + device ref i3c_3 on end + device ref uart_0 on end # UART0 + device ref uart_1 on end + device ref uart_2 on end + device ref uart_3 on end + device ref uart_4 on end + + chip drivers/amd/ftpm + device mmio 0xfd2108d0 on end + end +end diff --git a/src/mainboard/amd/jaguar/dsdt.asl b/src/mainboard/amd/jaguar/dsdt.asl new file mode 100644 index 00000000000..2463796f184 --- /dev/null +++ b/src/mainboard/amd/jaguar/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include + + #include + + Scope(\_SB.PCI0.LPCB) + { + #include "acpi/ec.asl" + } +} diff --git a/src/mainboard/amd/jaguar/early_gpio.c b/src/mainboard/amd/jaguar/early_gpio.c new file mode 100644 index 00000000000..cabf102bdb8 --- /dev/null +++ b/src/mainboard/amd/jaguar/early_gpio.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_UP), + /* TPM IRQ */ + PAD_INT(GPIO_130, PULL_UP, EDGE_LOW, STATUS_DELIVERY), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_UP), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* EC SCI */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + + /* FANIN0 */ + PAD_NF(GPIO_84, FANIN0, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC BEEP - DNI */ + PAD_NFO(GPIO_91, SPKR, LOW), + + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), +#if CONFIG(UART_0_1_2_3_TWO_WIRE) + /* UART3_TXD */ + PAD_NF(GPIO_135, UART3_TXD, PULL_NONE), + /* UART3_RXD */ + PAD_NF(GPIO_137, UART3_RXD, PULL_NONE), + /* UART1_TXD */ + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + /* UART1_RXD */ + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), +#else + /* UART2_CTS_L */ + PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + /* UART2_RTS_L */ + PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), + /* UART0_CTS_L */ + PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* UART0_RTS_L */ + PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), +#endif + + /* CPLD_TDO_SOC_1V8 / MDIO2_SCL */ + PAD_GPO(GPIO_9, LOW), + /* CPLD_TMS_SOC / USB_OSC3_L */ + PAD_GPO(GPIO_24, LOW), + /* LPC_RST_L (CPLD RST)*/ + PAD_NF(GPIO_32, LPC_RST_L, PULL_DOWN), + /* CPLD_TCK_SOC */ + PAD_NF(GPIO_74,GPIOxx, PULL_DOWN), + /* CPLD_TDI_SOC */ + PAD_NF(GPIO_79, GPIOxx, PULL_DOWN), + /* USB2_HDR_P0/1_SMI */ + PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), +}; + +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/jaguar/ec.c b/src/mainboard/amd/jaguar/ec.c new file mode 100644 index 00000000000..d263f136c8b --- /dev/null +++ b/src/mainboard/amd/jaguar/ec.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ec.h" + +#include +#include +#include + +/* Controls power and reset lines connected to EC */ +static void configure_ec_gpio(void) +{ + uint8_t tmp; + uint8_t olddata = ec_read(EC_PAGE_SELECT); + + /* select page c2 */ + ec_write(EC_PAGE_SELECT, EC_GPIO_PAGE); + + /* SLOT-0 Force power */ + if (CONFIG(ENABLE_EVAL_CARD) && + CONFIG(ENABLE_FORCE_POWER_GPP0) && + CONFIG(PCIE_SLOT0_2X4)) { + tmp = EC_FORCE_PWR_SLOT0; + } else { + tmp = 0; + } + + ec_write(EC_FORCE_PWR, tmp); + printk(BIOS_SPEW, "EC: 0x%02x = %02x\n", EC_FORCE_PWR, tmp); + + /* Power on WLAN */ + tmp = 0; + if (CONFIG(ENABLE_NVME_WLAN_2LANES)) + tmp |= EC_WLAN_POWER_PWR_EN | EC_WLAN_POWER_PERST_N | EC_WLAN_POWER_SDIO_RST_N; + ec_write(EC_WLAN_POWER, tmp); + printk(BIOS_SPEW, "EC: 0x%02x = %02x\n", EC_WLAN_POWER, tmp); + + /* Configure PCIe mux */ + if (CONFIG(ENABLE_NVME_PCIE_2LANES)) { + tmp = EC_PCIE_MUX_M2_SLOT_2X2X; + } else if (CONFIG(ENABLE_PCIE_4LANES)) { + tmp = EC_PCIE_MUX_SLOT1X4; + } else if (CONFIG(ENABLE_NVME_WLAN_2LANES)) { + tmp = EC_PCIE_MUX_M2_WLAN_2X2X; + } else { + tmp = EC_PCIE_MUX_NVMEX4; + } + ec_write(EC_PCIE_MUX, tmp); + printk(BIOS_SPEW, "EC: 0x%02x = %02x\n", EC_PCIE_MUX, tmp); + + tmp = 0; + if (CONFIG(XGBE_LED_TURN_ON)) + tmp |= EC_XGBE_LED_ENABLE; + + /* Only SFP+ needs MDIO. xGBE in backplane mode doesn't use MDIO. */ + if (CONFIG(XGBE_SFP_PLUS_CONNECTION)) + tmp |= EC_XGBE_MDIO0_1_XGBE | EC_XGBE_SFPP_MUX_ENABLE; + + ec_write(EC_XGBE_CTRL, tmp); + printk(BIOS_SPEW, "EC: 0x%02x = %02x\n", EC_XGBE_CTRL, tmp); + + /* Enable M.2 SSD0 power */ + if (CONFIG(ENABLE_NVME_4LANES) || + CONFIG(ENABLE_NVME_PCIE_2LANES) || + CONFIG(ENABLE_NVME_WLAN_2LANES)) + tmp = EC_M2_POWER_PWR_EN | EC_M2_POWER_PERST_N; + else + tmp = 0; + ec_write(EC_M2_POWER, tmp); + printk(BIOS_SPEW, "EC: 0x%02x = %02x\n", EC_M2_POWER, tmp); + + /* restore page */ + ec_write(EC_PAGE_SELECT, olddata); +} + +void jaguar_ec_init(void) +{ + ec_set_ports(JAGUAR_EC_CMD, JAGUAR_EC_DATA); + configure_ec_gpio(); +} diff --git a/src/mainboard/amd/jaguar/ec.h b/src/mainboard/amd/jaguar/ec.h new file mode 100644 index 00000000000..8cde537f7f9 --- /dev/null +++ b/src/mainboard/amd/jaguar/ec.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef JAGUAR_EC_H +#define JAGUAR_EC_H + +#ifndef __ACPI__ +void jaguar_ec_init(void); +#endif + +#define JAGUAR_EC_CMD 0x666 +#define JAGUAR_EC_DATA 0x662 + +#define EC_PAGE_SELECT 0x31 +#define EC_MODERN_STANDBY 0xB7 +#define EC_MODERN_STANDBY_SSD0_D3_EN BIT(4) +#define EC_MODERN_STANDBY_SSD1_D3_EN BIT(5) +#define EC_MODERN_STANDBY_S0ix BIT(7) + +#define EC_GPIO_PAGE 0xc2 + +/* Registers [0h-30h] on page 0xc2 */ +#define EC_FORCE_PWR 0x11 +#define EC_FORCE_PWR_SLOT0 BIT(0) +#define EC_FORCE_PWR_SLOT1 BIT(1) +#define EC_FORCE_PWR_SLOT2 BIT(2) + +#define EC_PCIE_MUX 0x13 +#define EC_PCIE_MUX_NVMEX4 0 +#define EC_PCIE_MUX_SLOT1X4 1 +#define EC_PCIE_MUX_M2_SLOT_2X2X 2 +#define EC_PCIE_MUX_M2_WLAN_2X2X 3 +#define EC_PCIE_MUX_M2_WLAN_SLOT_2X1X1X 4 + +#define EC_M2_POWER 0x15 +#define EC_M2_POWER_PWR_EN BIT(0) +#define EC_M2_POWER_PERST_N BIT(4) + +#define EC_WLAN_POWER 0x20 +#define EC_WLAN_POWER_PWR_EN BIT(0) +#define EC_WLAN_POWER_PERST_N BIT(1) +#define EC_WLAN_POWER_SDIO_RST_N BIT(2) + +#define EC_XGBE_CTRL 0x22 +#define EC_XGBE_MDIO0_1_XGBE BIT(0) +#define EC_XGBE_MDIO2_3_XGBE BIT(1) +#define EC_XGBE_LED_ENABLE BIT(2) +#define EC_XGBE_SFPP_MUX_ENABLE BIT(3) + +#endif /* JAGUAR_EC_H */ diff --git a/src/mainboard/amd/jaguar/gpio.c b/src/mainboard/amd/jaguar/gpio.c new file mode 100644 index 00000000000..73328cfa071 --- /dev/null +++ b/src/mainboard/amd/jaguar/gpio.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L*/ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* INT_CLKREQ#_S5_R */ + PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), + /* UART_WAKE_L_M2_APU */ + PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), + /* MPM_EVENT_L, input or OD output */ + PAD_GPI(GPIO_5, PULL_UP), + /* EC SCI */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* VDD_MEM_LP# */ + PAD_GPO(GPIO_7, HIGH), + /* TPAD_INT_L */ + PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), + /* CPLD_TDO_SOC_1V8 / MDIO2_SCL */ + PAD_GPO(GPIO_9, LOW), + /* GPIO_10: VDD_MEM_VID0 - Controlled by firmware outside of coreboot (ABL) */ + /* HP_MIC_DET_L */ + PAD_GPI(GPIO_11, PULL_UP), + /* ALIGN_FLAG_MU_L */ + PAD_GPO(GPIO_12, HIGH), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* USB_OC1_L */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), + /* PCIE_WLAN_WAKE_L */ + PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* CPLD_TMS_SOC / USB_OSC3_L */ + PAD_GPO(GPIO_24, LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* GPIO_28: Not available */ + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_UP), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_UP), + /* SPI_CS3_L */ + PAD_NF(GPIO_31, SPI_CS3_L, PULL_UP), + /* LPC_RST_L */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_DOWN), + /* GPIO_33 - GPIO_37: Not available */ + /* CLK_REQ5_L */ + PAD_NF(GPIO_38, CLK_REQ5_L, PULL_UP), + /* CLK_REQ6_L */ + PAD_NF(GPIO_39, CLK_REQ6_L, PULL_UP), + /* USB2_HDR_P0/1_SMI */ + PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), + /* GPIO_41: Not available */ + /* GPIO_42: VDD_MEM_VID1 - Controlled by firmware outside of coreboot (ABL) */ + /* GPIO_43 - GPIO_66: Not available */ + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* SPI2_CLK */ + PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* CPLD_TCK_SOC */ + PAD_NF(GPIO_74, GPIOxx, PULL_DOWN), + /* SPI2_CS1_L */ + PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + /* CPLD_TDI_SOC */ + PAD_NF(GPIO_79, GPIOxx, PULL_DOWN), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* GPIO_82 - GPIO_83: Not available */ + /* FANIN0 */ + PAD_NF(GPIO_84, FANIN0, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* GPIO_86 - GPIO_88: Not available */ + /* DP_HPD_DIG# */ + PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), + /* ALERT_L_M2_SSD0 */ + PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), + /* PC BEEP - DNI */ + PAD_NFO(GPIO_91, SPKR, LOW), + /* CLK_REQ0_L */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), + /* GPIO_93 - GPIO_103: Not available */ + /* SPI2_DAT0 */ + PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), + /* SPI2_DAT1 */ + PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), + /* SPI2_DAT2 */ + PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), + /* SPI2_DAT3 */ + PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), + /* GPIO_108 - GPIO_112: Not available */ + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* CLK_REQ2_L */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), + /* GPIO_117 - GPIO_129: Not available */ + /* TPM IRQ */ + PAD_INT(GPIO_130, PULL_UP, EDGE_LOW, STATUS_DELIVERY), + /* CLK_REQ3_L */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_UP), + /* CLK_REQ4_L */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), + /* GPIO_133 - GPIO_134: Not available */ +#if CONFIG(UART_0_1_2_3_TWO_WIRE) + /* UART3_TXD */ + PAD_NF(GPIO_135, UART3_TXD, PULL_NONE), + /* UART3_RXD */ + PAD_NF(GPIO_137, UART3_RXD, PULL_NONE), + /* UART1_TXD */ + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + /* UART1_RXD */ + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), +#else + /* UART2_CTS_L */ + PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + /* UART2_RTS_L */ + PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), + /* UART0_CTS_L */ + PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* UART0_RTS_L */ + PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), +#endif + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* I2S_CODEC_INT */ + PAD_SCI(GPIO_139, PULL_UP, EDGE_LOW), + /* SFP_IOEXP_INT0_L */ + PAD_GPI(GPIO_144, PULL_UP), + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* GPIO_149 - GPIO_152: Not available */ + /* UART4_CTS_L */ + PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE), + /* UART4_RTS_L */ + PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE), + /* UART4_RXD */ + PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), + /* UART4_TXD */ + PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), + /* UART4_INTR - DNI */ + PAD_GPI(GPIO_157, PULL_NONE), +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/jaguar/gpio.h b/src/mainboard/amd/jaguar/gpio.h new file mode 100644 index 00000000000..04c98c50df9 --- /dev/null +++ b/src/mainboard/amd/jaguar/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/jaguar/mainboard.c b/src/mainboard/amd/jaguar/mainboard.c new file mode 100644 index 00000000000..72a497ba2b3 --- /dev/null +++ b/src/mainboard/amd/jaguar/mainboard.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include "gpio.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ec.h" + +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 0xA, 0xA }, + { PIRQ_I2C1, 0xB, 0xB }, + { PIRQ_I2C2, 0x4, 0x4 }, + { PIRQ_I2C3, 0x6, 0x6 }, + { PIRQ_UART0, 0x3, 0x3 }, +#if CONFIG(UART_0_1_2_3_TWO_WIRE) + { PIRQ_UART1, 0xE, 0xE }, + { PIRQ_UART3, 0xF, 0xF }, +#endif + { PIRQ_UART2, 0x5, 0x5 }, + { PIRQ_UART4, 0x10, 0x10 }, + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void mainboard_configure_uarts(void) +{ + if (CONFIG(XGBE_LED_TURN_ON)) { + DEV_PTR(uart_2)->enabled = 0; + DEV_PTR(uart_4)->enabled = 0; + } + if (CONFIG(UART_0_2_4_FOUR_WIRE)) { + DEV_PTR(uart_1)->enabled = 0; + DEV_PTR(uart_3)->enabled = 0; + } +} + +static void mainboard_configure_i2c(void) +{ + if (!CONFIG(I2C_ENABLE)) { + DEV_PTR(i2c_0)->enabled = 0; + DEV_PTR(i2c_1)->enabled = 0; + DEV_PTR(i2c_2)->enabled = 0; + DEV_PTR(i2c_3)->enabled = 0; + } +} + +static void mainboard_configure_i3c(void) +{ + struct soc_amd_glinda_config *cfg = config_of_soc(); + + if (CONFIG(I2C_ENABLE)) { + /* I2C mode - disable I3C devices, use devicetree defaults (I2C_PAD_RX_1_8V) */ + DEV_PTR(i3c_0)->enabled = 0; + DEV_PTR(i3c_1)->enabled = 0; + DEV_PTR(i3c_2)->enabled = 0; + DEV_PTR(i3c_3)->enabled = 0; + } else { + /* I3C mode - configure i2c_pad for I3C voltage levels */ + cfg->i2c_pad[0].rx_level = I3C_PAD_RX_1_8V; + cfg->i2c_pad[1].rx_level = I3C_PAD_RX_1_8V; + cfg->i2c_pad[2].rx_level = I3C_PAD_RX_1_8V; + cfg->i2c_pad[3].rx_level = I3C_PAD_RX_1_8V; + } +} + +static void mainboard_configure_ec(void) +{ + ec_set_ports(JAGUAR_EC_CMD, JAGUAR_EC_DATA); + + /* Modern Standby enable, D3 cold enable */ + const u8 mask = EC_MODERN_STANDBY_SSD0_D3_EN | + EC_MODERN_STANDBY_SSD1_D3_EN | + EC_MODERN_STANDBY_S0ix; + + u8 tmp = ec_read(EC_MODERN_STANDBY); + if ((tmp & mask) != mask) + ec_write(EC_MODERN_STANDBY, tmp | mask); +} + +static void mainboard_init(void *chip_info) +{ + mainboard_program_gpios(); + mainboard_configure_uarts(); + mainboard_configure_i2c(); + mainboard_configure_i3c(); + mainboard_configure_ec(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/amd/jaguar/port_descriptors.c b/src/mainboard/amd/jaguar/port_descriptors.c new file mode 100644 index 00000000000..3d08c664922 --- /dev/null +++ b/src/mainboard/amd/jaguar/port_descriptors.c @@ -0,0 +1,382 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include + +bool devtree_xgbe_dev_enabled(uint8_t port_num); + +#define ECRAM_MACID_OFFSET 0x50 +#define MACID_LEN 12 +#define JAGUAR_EC_CMD 0x666 +#define JAGUAR_EC_DATA 0x662 +#define XGBE_PORT_0 0 +#define XGBE_PORT_1 1 +#define ETHERNET_PORT_COUNT 2 + +/* Eval slot / PCIe SLOT-0 (CLK_REQ4) */ +#define jaguar_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 19, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* 2(x4) Eval slot / PCIe SLOT-0 (CLK_REQ4) */ +#define jaguar_mxm_v0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 15, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* 4x - 8x Eval slot / PCIe SLOT-0 (CLK_REQ4) */ +#define jaguar_mxm_v1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 3, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* 4x or 2x PCIe M.2 SSD0, muxed with GPP1/Wifi (CLKREQ0) */ +#define jaguar_nvme0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = CONFIG(ENABLE_NVME_4LANES) ? 0 : 2, \ + .end_logical_lane = 3, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* 4x or 2x PCIe GPP1, muxed with NVMe0 (CLKREQ1) */ +#define jaguar_gpp1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = CONFIG(ENABLE_PCIE_4LANES) ? 3 : 1, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .clk_req = CLK_REQ1, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* PCIe SLOT-2 muxed with xGBE (CLK_REQ3) */ +#define jaguar_gpp2_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 4, \ + .end_logical_lane = 5, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .clk_req = CLK_REQ3, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* + * 2x PCIe WLAN (CLK_REQ2) + * only if CONFIG(ENABLE_NVME_WLAN_2LANES) + */ +#define jaguar_wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 1, \ + .device_number = 2, \ + .function_number = 3, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +/* + * XGBE ETHERNET PORTS Entry Port 0 + * XGBE SGMII interface: Physical lane 4, Logical lane 0 + * NOTE: Ancillary data not yet captured here due to FSP + * limitations + */ +#define jaguar_xgbe0_dxio_descriptor { \ + .port_present = true, \ + .engine_type = ETHERNET_ENGINE, \ + .start_logical_lane = 4, \ + .end_logical_lane = 4, \ +} + +/* + * XGBE ETHERNET PORTS Entry Port 1 + * XGBE SGMII interface: Physical lane 5, Logical lane 1 + * NOTE: Ancillary data not yet captured here due to FSP + * limitations + */ +#define jaguar_xgbe1_dxio_descriptor { \ + .port_present = true, \ + .engine_type = ETHERNET_ENGINE, \ + .start_logical_lane = 5, \ + .end_logical_lane = 5, \ +} + +static fsp_ddi_descriptor jaguar_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - TYPEC */ + .connector_type = CONFIG(DISPLAY_PORT_TYPEC) ? DDI_DP_W_TYPEC : DDI_HDMI, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + static const fsp_dxio_descriptor jaguar_dxio_descriptors[] = { + +#if CONFIG(DISABLE_FORCE_POWER_GPP0) && CONFIG(PCIE_SLOT0_1X8) + jaguar_mxm_dxio_descriptor, +#endif +#if CONFIG(ENABLE_EVAL_CARD) && CONFIG(ENABLE_FORCE_POWER_GPP0) && CONFIG(PCIE_SLOT0_2X4) + jaguar_mxm_v0_dxio_descriptor, + jaguar_mxm_v1_dxio_descriptor, +#endif +#if CONFIG(ENABLE_NVME_PCIE_2LANES) || CONFIG(ENABLE_NVME_WLAN_2LANES) || CONFIG(ENABLE_NVME_4LANES) + jaguar_nvme0_dxio_descriptor, +#endif +#if CONFIG(ENABLE_NVME_PCIE_2LANES) || CONFIG(ENABLE_PCIE_4LANES) + jaguar_gpp1_dxio_descriptor, +#endif +#if CONFIG(ENABLE_NVME_WLAN_2LANES) + jaguar_wlan_dxio_descriptor, +#endif + +#if CONFIG(XGBE_EN) + jaguar_xgbe0_dxio_descriptor, + jaguar_xgbe1_dxio_descriptor, +#else + jaguar_gpp2_dxio_descriptor, +#endif + }; + + *dxio_descs = jaguar_dxio_descriptors; + *dxio_num = ARRAY_SIZE(jaguar_dxio_descriptors); + *ddi_descs = jaguar_ddi_descriptors; + *ddi_num = ARRAY_SIZE(jaguar_ddi_descriptors); +} + +static void xgbe_init(FSP_M_CONFIG *mcfg) +{ + uint8_t mac_buffer[12]; + + ec_set_ports(JAGUAR_EC_CMD, JAGUAR_EC_DATA); + uint16_t offset = ECRAM_MACID_OFFSET; + + uint16_t index = 0; + for (index = 0; index < MACID_LEN ; index++) { + uint8_t reg_value = ec_read(offset); + printk(BIOS_SPEW, "READ MACID REG 0x%2x value 0x%02x\n", offset, reg_value); + offset++; + mac_buffer[index] = reg_value; + } + + uint64_t value = 0x0; + for (index = 0; index < 6; index++) { + value += mac_buffer[index]; + value = value * 0x100; + } + uint64_t mac_addr_port0 = value / 0x100; + printk(BIOS_SPEW, "value : mac_addr_port0 0x%02llx\n", mac_addr_port0); + value = 0x0; + for (index = 6; index < 12; index++) { + value += mac_buffer[index]; + value = value * 0x100; + } + uint64_t mac_addr_port1 = value / 0x100; + printk(BIOS_SPEW, "value : mac_addr_port1 0x%02llx\n", mac_addr_port1); + + for (index = 0; index < MACID_LEN; index++) { + printk(BIOS_SPEW, " mac_buffer[0x%02x] 0x%02x\n", index, mac_buffer[index]); + } + /* MAC can be updated here to pass the same to FSP */ + mcfg->xgbe_port0_mac = mac_addr_port0; + mcfg->xgbe_port1_mac = mac_addr_port1; + + if (CONFIG(XGBE_EN)) { + mcfg->xgbe_port0_config_en = is_dev_enabled(DEV_PTR(xgbe_0)); + mcfg->xgbe_port1_config_en = is_dev_enabled(DEV_PTR(xgbe_1)); + mcfg->XgbeDisable = 0; + } else { + mcfg->xgbe_port0_config_en = 0; + mcfg->xgbe_port1_config_en = 0; + mcfg->XgbeDisable = 1; + } + + if (CONFIG(XGBE_LED_TURN_ON)) { + mcfg->xgbe_led_en = CONFIG(XGBE_LED_TURN_ON); + mcfg->xgbe_led_link_status0 = CONFIG(TURN_ON_PORT_0_LINK_STATUS_LED); + mcfg->xgbe_led_link_status1 = CONFIG(TURN_ON_PORT_1_LINK_STATUS_LED); + mcfg->xgbe_led_link_speed0 = CONFIG(TURN_ON_PORT_0_LINK_SPEED_LED); + mcfg->xgbe_led_link_speed1 = CONFIG(TURN_ON_PORT_1_LINK_SPEED_LED); + mcfg->xgbe_led_tx_rx_blink_rate0 = CONFIG_PORT_0_TX_RX_LED_BLINK_RATE; + mcfg->xgbe_led_tx_rx_blink_rate1 = CONFIG_PORT_1_TX_RX_LED_BLINK_RATE; + } + + static struct xgbe_port_table xgbe_port[2]; + for (int port_idx = 0; port_idx < ETHERNET_PORT_COUNT; port_idx++) { + if ((mcfg->xgbe_port0_config_en == true) || (mcfg->xgbe_port1_config_en == true)) { + xgbe_port[port_idx].XgbePortConfig = XGBE_PORT_ENABLE; + if (CONFIG(XGBE_BACKPLANE_CONNECTION)) { + xgbe_port[port_idx].XgbePortConnectedType = XGBE_BACKPLANE_CONNECTION; + if (CONFIG(XGBE_PORT_SGMII_BACKPLANE)) { + xgbe_port[port_idx].XgbePortPlatformConfig = XGBE_PORT_SGMII_BACKPLANE; + } else if (CONFIG(XGBE_10G_1G_BACKPLANE)) { + xgbe_port[port_idx].XgbePortPlatformConfig = XGBE_10G_1G_BACKPLANE; + } else if (CONFIG(XGBE_2_5G_BACKPLANE)) { + xgbe_port[port_idx].XgbePortPlatformConfig = XGBE_2_5G_BACKPLANE; + } + } else if (CONFIG(XGBE_SFP_PLUS_CONNECTION)) { + xgbe_port[port_idx].XgbePortConnectedType = XGBE_SFP_PLUS_CONNECTION; + xgbe_port[port_idx].XgbePortPlatformConfig = XGBE_SFP_PLUS_CONNECTOR; + } + xgbe_port[port_idx].XgbePortMdioResetType = 0x00; + xgbe_port[port_idx].XgbePortResetGpioNum = 0x00; + xgbe_port[port_idx].XgbePortMdioResetI2cAddress = 0x00; + xgbe_port[port_idx].XgbePortSfpI2cAddress = 0x01; + xgbe_port[port_idx].XgbePortSfpGpioMask = 0x02; + xgbe_port[port_idx].XgbePortSfpRsGpio = 0x00; + xgbe_port[port_idx].XgbaPortRedriverModel = 0x00; + xgbe_port[port_idx].XgbaPortRedriverInterface = 0x01; + xgbe_port[port_idx].XgbaPortRedriverAddress = 0x00; + xgbe_port[port_idx].XgbaPortRedriverLane = 0x00; + xgbe_port[port_idx].XgbePortSfpTwiAddress = 0x1C; + xgbe_port[port_idx].XgbaPortPadGpio = 0x00; + xgbe_port[port_idx].XgbaPortPadI2C = 0x00; + xgbe_port[port_idx].Reserve1 = 0x00; + xgbe_port[port_idx].XgbePortSfpTwiBus = 0x0E; + xgbe_port[port_idx].XgbePortSfpModAbsGpio = 0x0C; + xgbe_port[port_idx].XgbePortSfpRxLosGpio = 0x0D; + xgbe_port[port_idx].XgbePortSfpTwiBus = 0x01; + if (CONFIG(XGBE_PORT_SPEED_10_100_1000M)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_10_100_1000M; + } else if (CONFIG(XGBE_PORT_SPEED_10G)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_10G; + } else if (CONFIG(XGBE_PORT_SPEED_2500M)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_2500M; + } else if (CONFIG(XGBE_PORT_SPEED_1G)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_1G; + } else if (CONFIG(XGBE_PORT_SPEED_100M)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_100M; + } else if (CONFIG(XGBE_PORT_SPEED_10M)) { + xgbe_port[port_idx].XgbePortSupportedSpeed = XGBE_PORT_SPEED_10M; + } + if (port_idx == 1) { + xgbe_port[port_idx].XgbePortSfpTwiBus = 0xA; + xgbe_port[port_idx].XgbePortSfpModAbsGpio = 0x8; + xgbe_port[port_idx].XgbePortSfpRxLosGpio = 0x9; + xgbe_port[port_idx].XgbePortSfpTwiBus = 0x2; + } + } else { + /* Disable the Xgbe port */ + xgbe_port[port_idx].XgbePortConfig = XGBE_PORT_DISABLE; + } + /* Assign pointer of xgbe_port_table, Will be consumed by FSP */ + if (port_idx == 0) { + mcfg->xgbe_port0_table_ptr = (uint32_t)(uintptr_t)&xgbe_port[0]; + } else { + mcfg->xgbe_port1_table_ptr = (uint32_t)(uintptr_t)&xgbe_port[1]; + } + } +} + +void mb_pre_fspm(FSP_M_CONFIG *mcfg) +{ + /* fch_rt_device_enable_map is already set by SoC code. Update as needed. */ + if (CONFIG(XGBE_LED_TURN_ON)) + mcfg->fch_rt_device_enable_map &= ~(BIT(FCH_AOAC_DEV_UART2) | BIT(FCH_AOAC_DEV_UART4)); + if (CONFIG(UART_0_2_4_FOUR_WIRE)) + mcfg->fch_rt_device_enable_map &= ~(BIT(FCH_AOAC_DEV_UART1) | BIT(FCH_AOAC_DEV_UART3)); + + if (CONFIG(I2C_ENABLE)) { + /* Disable I3C */ + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I3C0); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I3C1); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I3C2); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I3C3); + } else { + /* Disable I2C */ + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I2C0); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I2C1); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I2C2); + mcfg->fch_rt_device_enable_map &= ~BIT(FCH_AOAC_DEV_I2C3); + } + + xgbe_init(mcfg); +} diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 9758e9cf2d1..a1c53c81ff7 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -38,12 +38,6 @@ chip soc/amd/cezanne device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on - chip drivers/usb/acpi - device ref usb3_port0 on end - end - chip drivers/usb/acpi - device ref usb3_port1 on end - end chip drivers/usb/acpi device ref usb2_port0 on end end @@ -56,18 +50,18 @@ chip soc/amd/cezanne chip drivers/usb/acpi device ref usb2_port3 on end end + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb3_port1 on end + end end end end device ref xhci_1 on # USB 3.1 (USB1) chip drivers/usb/acpi device ref xhci_1_root_hub on - chip drivers/usb/acpi - device ref usb3_port4 on end - end - chip drivers/usb/acpi - device ref usb3_port5 on end - end chip drivers/usb/acpi device ref usb2_port4 on end end @@ -80,6 +74,12 @@ chip soc/amd/cezanne chip drivers/usb/acpi device ref usb2_port7 on end end + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end end end end diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/amd/mandolin/romstage.c +++ b/src/mainboard/amd/mandolin/romstage.c @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 20595e8d77f..8f75a120aa3 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -6,9 +6,8 @@ chip soc/amd/picasso # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "has_usb2_phy_tune_params" = "1" + register "has_usb2_phy_tune_params" = "true" # Controller0 Port0 Default register "usb_2_port_tune_params[0]" = "{ diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 9628992857a..48d98ea115b 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -6,9 +6,8 @@ chip soc/amd/picasso # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "has_usb2_phy_tune_params" = "1" + register "has_usb2_phy_tune_params" = "true" # Controller0 Port0 Default register "usb_2_port_tune_params[0]" = "{ diff --git a/src/mainboard/amd/maple/APCB/APCB_FP11_LPDDR5_DefaultRecovery.apcb b/src/mainboard/amd/maple/APCB/APCB_FP11_LPDDR5_DefaultRecovery.apcb new file mode 100644 index 00000000000..7dcb3d354b5 Binary files /dev/null and b/src/mainboard/amd/maple/APCB/APCB_FP11_LPDDR5_DefaultRecovery.apcb differ diff --git a/src/mainboard/amd/maple/Kconfig b/src/mainboard/amd/maple/Kconfig new file mode 100644 index 00000000000..2043def4a17 --- /dev/null +++ b/src/mainboard/amd/maple/Kconfig @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only +# TODO: update for Maple + +config BOARD_AMD_MAPLE_COMMON + def_bool n + select BOARD_ROMSIZE_KB_65536 + select EC_ACPI + select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE + select DRIVERS_I2C_GENERIC + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + +config BOARD_AMD_MAPLE_STRIX_HALO + select BOARD_AMD_MAPLE_COMMON + select SOC_AMD_STRIX_HALO + +if BOARD_AMD_MAPLE_COMMON + +config FMDFILE + default "src/mainboard/amd/maple/board.fmd" + +config MAINBOARD_DIR + default "amd/maple" + +config MAINBOARD_PART_NUMBER + default "Maple_StrixHalo" + +config DEVICETREE + default "devicetree.cb" + +config MAPLE_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config AMD_SOC_CONSOLE_UART + default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + +config MAPLE_MCHP_FW_FILE + string "Microchip EC firmware file" + depends on MAPLE_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/maple/StxhComboEC.bin" + help + The EC firmware blob is at the EC_BODY FMAP region of the firmware image. + +config ENABLE_SSD1_MAPLE + bool "Enable M.2 SSD1 Slot" + help + Enable M.2 SSD1 Slot. For Strix Halo SoC this will downgrade + PCIe x8 slot to x4. + +choice + prompt "WLAN / WWAN Lane Selection" + default ENABLE_WLANx1_WWANx1_MAPLE + help + Enable 2 Lanes WLAN or 2 Lanes WWAN or 1 Lane WLAN and 1 Lane WWAN. + +config ENABLE_WLANx1_WWANx1_MAPLE + bool "Enable 1 Lane WLAN and 1 Lane WWAN" + +config ENABLE_WLANx2_WWANx0_MAPLE + bool "Enable 2 Lanes WLAN (no WWAN)" + +config ENABLE_WLANx0_WWANx2_MAPLE + bool "Enable 2 Lanes WWAN (no WLAN)" +endchoice + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 3 # Quad IO (1-1-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_MAPLE_COMMON diff --git a/src/mainboard/amd/maple/Kconfig.name b/src/mainboard/amd/maple/Kconfig.name new file mode 100644 index 00000000000..e21533681af --- /dev/null +++ b/src/mainboard/amd/maple/Kconfig.name @@ -0,0 +1,4 @@ +comment "Maple" + +config BOARD_AMD_MAPLE_STRIX_HALO + bool "-> Maple for Strix Halo SoC" diff --git a/src/mainboard/amd/maple/Makefile.mk b/src/mainboard/amd/maple/Makefile.mk new file mode 100644 index 00000000000..c2489a406d6 --- /dev/null +++ b/src/mainboard/amd/maple/Makefile.mk @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: update for maple + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +bootblock-y += ec.c + +romstage-y += port_descriptors.c + +ramstage-y += gpio.c +ramstage-y += port_descriptors.c + +APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/APCB/APCB_FP11_LPDDR5_DefaultRecovery.apcb + +ifeq ($(CONFIG_MAPLE_HAVE_MCHP_FW),y) +subdirs-y += ../../../../util/mec152x + +$(call add_intermediate, add_mchp_fw, $(objutil)/mec152x/mec152xtool) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_MAPLE_MCHP_FW_FILE) --fill-upward + $(objutil)/mec152x/mec152xtool $(obj)/coreboot.pre GEN_ECFW_PTR -f EC_BODY +else +show_notices:: warn_no_mchp +endif # CONFIG_MAPLE_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the EC FW.\n" + printf "Do not flash this image. Your Maple's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/maple/acpi/acp.asl b/src/mainboard/amd/maple/acpi/acp.asl new file mode 100644 index 00000000000..1ffc3b5a5a0 --- /dev/null +++ b/src/mainboard/amd/maple/acpi/acp.asl @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* TODO: Update for Maple */ + +/* ACP Audio Configuration */ +Scope (\_SB.PCI0.GP41.ACPD) { + + /* Global Configuration - _DSD properties for ACP device */ + Name (_DSD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) {"acp-audio-zsc-enable", 0x01}, + Package (0x02) {"acp-audio-config-flag", 0x10} + } + }) +} +Scope (\_SB.PCI0.GP41.ACPD.HDA0) { + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) {"acp-audio-device-interface-version",0x01}, + Package (2) {"acp-audio-device-type",0x01} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02) {"acp-audio-device-eps", + Package () { "PE00","PE01"} + } + } + }) + Name (PE00, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02) {"acp-audio-ep-type", 0x0 }, + Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1}, + Package (0x02) {"acp-audio-ep-category", 0x1} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02){"acp-audio-ep-format", "FMTS"}, + Package (0x02){"acp-audio-ep-apo-fx-type-ex", "EFXS"} + } + }) + Name (PE01, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-type", 0x0}, + Package (0x02){"acp-audio-ep-dsp-offload-supported", 0x1}, + Package (0x02){"acp-audio-ep-category", 0x2} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02){"acp-audio-ep-format", "FMTH"}, + Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFXH"} + } + }) + Name (FMTS, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-format-max-channels", 0x02}, + Package (0x02){"acp-audio-ep-format-sampling-frequency", + Package (){ 48000,96000} + }, + Package (0x02){"acp-audio-ep-format-bits-per-sample", + Package (){16,24} + } + } + }) + Name (FMTH, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-format-max-channels", 0x02}, + Package (0x02){"acp-audio-ep-format-sampling-frequency", + Package (){ 48000,96000} + }, + Package (0x02){"acp-audio-ep-format-bits-per-sample", + Package (){16,24} + } + } + }) + Name (EFXS, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"{05714B44-A61C-40F0-9F72-3A2EFF40D74C}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"} + } + }) + Name (EFXH, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"} + } + }) +} +Scope (\_SB.PCI0.GP41.ACPD.BTSC) { + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) {"acp-audio-device-interface-version",0x01}, + Package (2) {"acp-audio-device-type",0x04} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02) {"acp-audio-device-eps", + Package () { "PE00","CE00"} + } + } + }) + Name (PE00, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02) {"acp-audio-ep-type", 0x0 }, + Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1}, + Package (0x02) {"acp-audio-ep-category", 0x1}, + Package (0x02) {"acp-audio-ep-port", 0x3}, + Package (0x02) {"acp-audio-ep-node", 0x2}, + Package (0x02) {"acp-audio-ep-capabilities", + Package (){ 0x1, 0x2, 0x4, 0x8}} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02){"acp-audio-ep-format", "FMT0"}, + Package (0x02){"acp-audio-ep-apo-fx-type", "EFX0"}, + Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFX1"} + } + }) + Name (FMT0, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-format-max-channels", 0x02}, + Package (0x02){"acp-audio-ep-format-sampling-frequency", + Package (){ 8000,16000, 48000}}, + Package (0x02){"acp-audio-ep-format-bits-per-sample", + Package (){16}} + } + }) + Name (EFX0, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-apo-efx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-mfx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-sfx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-efx-encoder-type", 0x100} + } + }) + Name (EFX1, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{09DF37AE-0217-4601-A842-DEC90EEBC68F}", "{66E5A40D-4559-4019-B0F1-5F842C7E461A}"}, + } + }) + Name (CE00, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02) {"acp-audio-ep-type", 0x1 }, + Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1}, + Package (0x02) {"acp-audio-ep-ai-noise-reduction-supported", 0x0}, + Package (0x02) {"acp-audio-ep-port", 0x3}, + Package (0x02) {"acp-audio-ep-node", 0x2} + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () + { + Package (0x02){"acp-audio-ep-format", "FMT1"}, + Package (0x02){"acp-audio-ep-apo-fx-type", "EFX2"}, + Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFX3"} + } + }) + Name (FMT1, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-format-max-channels", 0x02}, + Package (0x02){"acp-audio-ep-format-sampling-frequency", + Package (){ 8000,16000}}, + Package (0x02){"acp-audio-ep-format-bits-per-sample", + Package (){16}} + } + }) + Name (EFX2, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"acp-audio-ep-apo-efx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-mfx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-sfx-type", 0x0}, + Package (0x02){"acp-audio-ep-apo-efx-encoder-type", 0x100} + } + }) + Name (EFX3, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02){"{65E94A28-DE71-4154-AD49-F67C7831EA4D}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{E5B78E46-DAA2-4827-8D84-F6C0C0306541}", "{00000000-0000-0000-0000-000000000000}"}, + Package (0x02){"{09DF37AE-0217-4601-A842-DEC90EEBC68F}", "{66E5A40D-4559-4019-B0F1-5F842C7E461A}"} + } + }) +} diff --git a/src/mainboard/amd/maple/board.fmd b/src/mainboard/amd/maple/board.fmd new file mode 100644 index 00000000000..6bd258da4f5 --- /dev/null +++ b/src/mainboard/amd/maple/board.fmd @@ -0,0 +1,12 @@ +/* TODO: Update for Maple */ + +FLASH 64M { + BIOS 16M { + EC_SIG 4K + FMAP 4K + COREBOOT(CBFS) + SMMSTORE(PRESERVE) 256K + EC_BODY@15296K 512K + RW_MRC_CACHE 576K + } +} diff --git a/src/mainboard/amd/maple/board_info.txt b/src/mainboard/amd/maple/board_info.txt new file mode 100644 index 00000000000..b351b8e696f --- /dev/null +++ b/src/mainboard/amd/maple/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/maple/bootblock.c b/src/mainboard/amd/maple/bootblock.c new file mode 100644 index 00000000000..1a09dcf18d6 --- /dev/null +++ b/src/mainboard/amd/maple/bootblock.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// TODO: update for maple + +#include +#include +#include "ec.h" +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + espi_switch_to_spi1_pads(); +} + +void bootblock_mainboard_init(void) +{ + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD)) + maple_ec_init(); +} diff --git a/src/mainboard/amd/maple/devicetree.cb b/src/mainboard/amd/maple/devicetree.cb new file mode 100644 index 00000000000..6a8ac2e675d --- /dev/null +++ b/src/mainboard/amd/maple/devicetree.cb @@ -0,0 +1,293 @@ +# SPDX-License-Identifier: GPL-2.0-only +# TODO: update for maple + +chip soc/amd/strix_halo + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "system_configuration" = "2" + + register "slow_ppt_limit_mW" = "45000" + register "fast_ppt_limit_mW" = "45000" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + register "i2c[2].early_init" = "1" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + + register "usb_phy_custom" = "true" + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[1] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[2] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[3] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[4] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[5] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb3PhyPort[0] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, + }" + + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # NVME SSD1 + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # DT MPCIE + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0 + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN + register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_2_1 on # GBE + device pci 0.0 on end # RTL8111 + end + device ref gpp_bridge_2_2 on # SD Express + device pci 0.0 on end # RTS5264 + end + device ref gpp_bridge_2_3 on end # WLAN + device ref gpp_bridge_2_4 on end # WWAN + device ref gpp_bridge_2_5 on end # NVME SSD0 + device ref gpp_bridge_3_1 on end # NVME SSD1 + device ref gpp_bridge_3_2 on end # DT MPCIE + + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port7 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + end + end + end + + device ref usb4_xhci_0 on + chip drivers/usb/acpi + device ref usb4_xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + end + end + end + device ref usb4_xhci_1 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref usb4_xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "desc" = ""TMP420 3 channel temperature sensor"" + register "uid" = "1" + register "compat_string" = ""ti,tmp432"" + device i2c 4d on end + end + end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + device ref uart_2 on end # UART2 + device ref uart_4 on end # UART4 +end diff --git a/src/mainboard/amd/maple/dsdt.asl b/src/mainboard/amd/maple/dsdt.asl new file mode 100644 index 00000000000..751b9fb9cae --- /dev/null +++ b/src/mainboard/amd/maple/dsdt.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include + + #include + #include "acpi/acp.asl" +} diff --git a/src/mainboard/amd/maple/early_gpio.c b/src/mainboard/amd/maple/early_gpio.c new file mode 100644 index 00000000000..c92efc79381 --- /dev/null +++ b/src/mainboard/amd/maple/early_gpio.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* TODO: update for Maple */ + +#include +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* TPM IRQ */ + PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + /* M2_SSD1_RST_L */ + PAD_GPO(GPIO_79, HIGH), + + /* Enable UART 2 */ + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/maple/ec.c b/src/mainboard/amd/maple/ec.c new file mode 100644 index 00000000000..a34704b7e61 --- /dev/null +++ b/src/mainboard/amd/maple/ec.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// TODO: update for maple + +#include +#include +#include +#include "ec.h" + +#define MAPLE_EC_CMD 0x666 +#define MAPLE_EC_DATA 0x662 + +#define EC_GPIO_3_ADDR 0xA3 +#define EC3_WLAN_RST_AUX BIT(5) +#define EC3_WWAN_RST_AUX BIT(4) +#define EC3_SD_RST_AUX BIT(3) +#define EC3_DT_RST_AUX BIT(2) +#define EC3_LOM_RST_AUX BIT(1) + +#define EC_GPIO_6_ADDR 0xA6 +#define EC6_TPNL_BUF_EN BIT(1) +#define EC6_TPAD_BUF_EN BIT(0) + +#define EC_GPIO_7_ADDR 0xA7 +#define EC7_WWAN_PWR_OFF_N BIT(7) +#define EC7_BT_RADIO_DIS BIT(2) +#define EC7_WL_RADIO_EN BIT(0) + +#define EC_GPIO_8_ADDR 0xA8 +#define EC8_ADAPTER_OFF BIT(5) +#define EC8_MP2_SEL BIT(2) + +#define EC_GPIO_9_ADDR 0xA9 +#define EC9_WWAN_RST_N BIT(5) +#define EC9_SSD1_PWREN BIT(2) +#define EC9_TPM_PWR_EN BIT(1) +#define EC9_TPM_S0I3_N BIT(0) + +#define EC_GPIO_A_ADDR 0xAA +#define ECA_MUX2_S0 BIT(7) +#define ECA_MUX2_S1 BIT(6) +#define ECA_MUX1_S0 BIT(5) +#define ECA_MUX1_S1 BIT(4) +#define ECA_MUX0_S0 BIT(3) +#define ECA_MUX0_S1 BIT(2) +#define ECA_SMBUS1_EN BIT(1) +#define ECA_SMBUS0_EN BIT(0) + +#define EC_GPIO_D_ADDR 0xAD +#define ECD_TPNL_PWR_EN BIT(7) +#define ECD_TPNL_EN BIT(6) +#define ECD_FPR_PWR_EN BIT(3) +#define ECD_FPR_OFF_N BIT(2) +#define ECD_FPR_LOCK_N BIT(1) +#define ECD_TPAD_DISABLE_N BIT(0) + +#define EC_GPIO_E_ADDR 0xAE +#define ECE_LOM_PWR_EN BIT(7) +#define ECE_SSD0_PWR_EN BIT(6) +#define ECE_SD_PWR_EN BIT(5) +#define ECE_WLAN_PWR_EN BIT(4) +#define ECE_WWAN_PWR_EN BIT(3) +#define ECE_CAM_PWR_EN BIT(2) +#define ECE_GBE_N_FPR_SEL BIT(1) // USB6_MUX_GBE#_FPR_SEL for Maple +#define ECE_TPNL_N_BT_SEL BIT(0) // USB5_MUX_TPNL#_BT_SEL for Maple + +#define EC_GPIO_F_ADDR 0xAF +#define ECF_SD_MAIN_PWR_EN BIT(6) +#define ECF_WLAN_LANE0_WWAN_LANE1_SW BIT(1) +#define ECF_WWAN_LANE0_WLAN_LANE1_SW BIT(0) + +#define EC_GPIO_G_ADDR 0xB0 +#define ECG_U0_WLAN_HDR_SEL BIT(6) +#define ECG_NFC_BUF_EN BIT(5) +#define ECG_WLAN_WWAN_MUX_OFF BIT(4) + +static void configure_ec_gpio(void) +{ + uint8_t tmp; + + tmp = ec_read(EC_GPIO_3_ADDR); + tmp |= EC3_WLAN_RST_AUX | EC3_WWAN_RST_AUX | EC3_SD_RST_AUX; + tmp |= EC3_DT_RST_AUX | EC3_LOM_RST_AUX; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp); + ec_write(EC_GPIO_3_ADDR, tmp); + + tmp = ec_read(EC_GPIO_6_ADDR); + tmp |= EC6_TPNL_BUF_EN | EC6_TPAD_BUF_EN; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_6_ADDR, tmp); + ec_write(EC_GPIO_6_ADDR, tmp); + + tmp = ec_read(EC_GPIO_7_ADDR); + tmp |= EC7_WWAN_PWR_OFF_N; + tmp &= ~(EC7_BT_RADIO_DIS | EC7_BT_RADIO_DIS); // todo: typo? + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); + ec_write(EC_GPIO_7_ADDR, tmp); + + tmp = ec_read(EC_GPIO_8_ADDR); + tmp |= EC8_MP2_SEL; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); + ec_write(EC_GPIO_8_ADDR, tmp); + + tmp = ec_read(EC_GPIO_9_ADDR); + tmp |= EC9_TPM_PWR_EN; + + if (CONFIG(ENABLE_WLANx2_WWANx0_MAPLE)) { + tmp &= ~EC9_WWAN_RST_N; + } else { + tmp |= EC9_WWAN_RST_N; + } + + if (CONFIG(ENABLE_SSD1_MAPLE)) { + tmp |= EC9_SSD1_PWREN; + } else { + tmp &= ~EC9_SSD1_PWREN; + } + + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp); + ec_write(EC_GPIO_9_ADDR, tmp); + + tmp = ec_read(EC_GPIO_A_ADDR); + tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN; + // Touch Panel under I2C0 bus (default) + tmp &= ~(ECA_MUX0_S1 | ECA_MUX0_S0); + // Touch Pad Under I2C1 bus (default) + tmp |= ECA_MUX1_S0; + tmp &= ~ECA_MUX1_S1; + // NFC under I2C0 bus (default) + tmp &= ~(ECA_MUX2_S0 | ECA_MUX2_S1); + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_A_ADDR, tmp); + ec_write(EC_GPIO_A_ADDR, tmp); + + tmp = ec_read(EC_GPIO_D_ADDR); + tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N; + tmp &= ~ECD_FPR_PWR_EN; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp); + ec_write(EC_GPIO_D_ADDR, tmp); + + tmp = ec_read(EC_GPIO_E_ADDR); + tmp |= ECE_SSD0_PWR_EN | ECE_CAM_PWR_EN | ECE_GBE_N_FPR_SEL; + tmp &= ~ECE_TPNL_N_BT_SEL; + + tmp |= ECE_SD_PWR_EN; + tmp |= ECE_LOM_PWR_EN; + + if (CONFIG(ENABLE_WLANx2_WWANx0_MAPLE)) { + tmp &= ~ECE_WWAN_PWR_EN; + } else { + tmp |= ECE_WWAN_PWR_EN; + } + + if (CONFIG(ENABLE_WLANx0_WWANx2_MAPLE)) { + tmp &= ~ECE_WLAN_PWR_EN; + } else { + tmp |= ECE_WLAN_PWR_EN; + } + + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_E_ADDR, tmp); + ec_write(EC_GPIO_E_ADDR, tmp); + + tmp = ec_read(EC_GPIO_F_ADDR); + tmp |= ECF_SD_MAIN_PWR_EN; + + if (CONFIG(ENABLE_WLANx1_WWANx1_MAPLE)) { + tmp &= ~ECF_WWAN_LANE0_WLAN_LANE1_SW; + tmp &= ~ECF_WLAN_LANE0_WWAN_LANE1_SW; + } + + if (CONFIG(ENABLE_WLANx2_WWANx0_MAPLE)) { + tmp |= ECF_WWAN_LANE0_WLAN_LANE1_SW; + tmp &= ~ECF_WLAN_LANE0_WWAN_LANE1_SW; + } + + if (CONFIG(ENABLE_WLANx0_WWANx2_MAPLE)) { + tmp &= ~ECF_WWAN_LANE0_WLAN_LANE1_SW; + tmp |= ECF_WLAN_LANE0_WWAN_LANE1_SW; + } + + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_F_ADDR, tmp); + ec_write(EC_GPIO_F_ADDR, tmp); + + tmp = ec_read(EC_GPIO_G_ADDR); + tmp &= ~ECG_WLAN_WWAN_MUX_OFF; // Keep low to avoid GPP13, GPP14 not work. + tmp |= ECG_U0_WLAN_HDR_SEL | ECG_NFC_BUF_EN; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_G_ADDR, tmp); + ec_write(EC_GPIO_G_ADDR, tmp); +} + +void maple_ec_init(void) +{ + ec_set_ports(MAPLE_EC_CMD, MAPLE_EC_DATA); + configure_ec_gpio(); +} diff --git a/src/mainboard/amd/maple/ec.h b/src/mainboard/amd/maple/ec.h new file mode 100644 index 00000000000..d9212e1eee2 --- /dev/null +++ b/src/mainboard/amd/maple/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAPLE_EC_H +#define MAPLE_EC_H + +void maple_ec_init(void); + +#endif /* MAPLE_EC_H */ diff --git a/src/mainboard/amd/maple/gpio.c b/src/mainboard/amd/maple/gpio.c new file mode 100644 index 00000000000..b5acacf4790 --- /dev/null +++ b/src/mainboard/amd/maple/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* PCIE_SD_WAKE_L */ + PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), + /* UART_WAKE_L_M2_APU */ + PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), + /* MPM_EVENT_L, input or OD output */ + PAD_GPI(GPIO_5, PULL_UP), + /* EC_SCI_L */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* APU_VDDCR_SR_LP_L */ + PAD_GPO(GPIO_7, HIGH), + /* TPAD_INT_L */ + PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), + /* SD_CARD_PRSNT_L */ + PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ + /* GPIO_10: VDD_MEM_VID0 - Controlled by firmware outside of coreboot (ABL) */ + /* HP_MIC_DET_L */ + PAD_GPI(GPIO_11, PULL_UP), + /* ALIGN_FLAG_MU_L */ + PAD_GPO(GPIO_12, HIGH), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* WAKE_ON_WAN_L */ + PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), + /* PCIE_WLAN_WAKE_L */ + PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_NONE), + /* PCIE_LOM_WAKE_L */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* GPIO_28: Not available */ + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* INT_CLKREQ_L */ + PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* LPC_RST_L */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), + /* GPIO_33 - GPIO_37: Not available */ + /* CLK_REQ5_L */ + PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE), + /* CLK_REQ6_L */ + PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE), + /* USB2_HDR_P0/1_SMI_L / DASH_SMI_L */ + PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), + /* GPIO_41: Not available */ + /* GPIO_42: VDD_MEM_VID1 - Controlled by firmware outside of coreboot (ABL) */ + /* GPIO_43 - GPIO_66: Not available */ + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* SPI2_CLK */ + PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* APU_NFC_DWL_REQ_1V8 */ + PAD_GPO(GPIO_74, LOW), + /* SPI2_CS1_L */ + PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + /* M2_SSD1_RST_L */ + PAD_GPO(GPIO_79, HIGH), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* GPIO_82 - GPIO_83: Not available */ + /* FANIN0 */ + PAD_NF(GPIO_84, FANIN0, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* GPIO_86 - GPIO_88: Not available */ + /* APU_MIPI_S0_GPIO89 */ + PAD_GPO(GPIO_89, HIGH), + /* ALERT_L_M2_SSD0 */ + PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), + /* NFC_IRQ_L_1V8 */ + PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW), + /* CLK_REQ0_L */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* SPI2_DAT0 */ + PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), + /* SPI2_DAT1 */ + PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), + /* SPI2_DAT2 */ + PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), + /* SPI2_DAT3 */ + PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), + /* GPIO_108 - GPIO_112: Not available */ + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_129: Not available */ + /* TPM_PIRQ_L */ + PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* CLK_REQ3_L */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), + /* CLK_REQ4_L */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ + /* UART2_CTS_L */ + PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_RTS_L */ + PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* UART2_INTR / I2S_CODEC_INT_1V8 */ + PAD_GPI(GPIO_139, PULL_UP), + /* UART0_CTS_L */ + PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_RTS_L */ + PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* NFC_RST_L / WAKE_1V8 */ + PAD_GPO(GPIO_144, LOW), + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* GPIO_149 - GPIO_152: Not available */ + /* GPIO_153 - GPIO_154: Controlled by firmware outside of coreboot */ + /* UART4_RXD */ + PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), + /* UART4_TXD */ + PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), + /* UART4_INTR / ALERT_L_M2_WWAN / ALERT_L_M2_SSD1 */ + PAD_GPI(GPIO_157, PULL_UP), +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/maple/gpio.h b/src/mainboard/amd/maple/gpio.h new file mode 100644 index 00000000000..04c98c50df9 --- /dev/null +++ b/src/mainboard/amd/maple/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/amd/maple/mainboard.c similarity index 58% rename from src/mainboard/google/myst/mainboard.c rename to src/mainboard/amd/maple/mainboard.c index 57bfcd4768b..8e233cdd314 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/amd/maple/mainboard.c @@ -1,14 +1,13 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include -#include -#include -#include +#include #include -#include -#include +#include +#include "gpio.h" + +/* TODO: Update for maple */ /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is accessed via I/O ports 0xc00/0xc01. */ @@ -23,7 +22,6 @@ * 8: rtc0 <- soc/amd/common/acpi/lpc.asl * 9: acpi <- soc/amd/common/acpi/lpc.asl */ - static const struct fch_irq_routing fch_irq_map[] = { { PIRQ_A, 12, PIRQ_NC }, { PIRQ_B, 14, PIRQ_NC }, @@ -57,37 +55,11 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) return fch_irq_map; } -static void mainboard_configure_gpios(void) -{ - size_t base_num_gpios, override_num_gpios; - const struct soc_amd_gpio *base_gpios, *override_gpios; - - baseboard_gpio_table(&base_gpios, &base_num_gpios); - variant_override_gpio_table(&override_gpios, &override_num_gpios); - - gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); -} - static void mainboard_init(void *chip_info) { - mainboard_configure_gpios(); - mainboard_ec_init(); -} - -static void mainboard_enable(struct device *dev) -{ - /* TODO: b/184678786 - Move into espi_config */ - /* Unmask eSPI IRQ 1 (Keyboard) */ - pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); -} - -void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size) -{ - soc_xhci_store_resources(slots, size); + mainboard_program_gpios(); } struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/maple/port_descriptors.c b/src/mainboard/amd/maple/port_descriptors.c new file mode 100644 index 00000000000..a0d9a1e9191 --- /dev/null +++ b/src/mainboard/amd/maple/port_descriptors.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define strix_halo_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 3, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define strix_halo_dt_mpcie_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 4, \ + .end_logical_lane = 7, \ + .device_number = 3, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ1, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define strix_halo_ssd0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 15, \ + .device_number = 2, \ + .function_number = 5, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define strix_halo_wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 10, \ + .end_logical_lane = CONFIG(ENABLE_WLANx2_WWANx0_MAPLE) ? 11 : 10, \ + .device_number = 2, \ + .function_number = 3, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ3, \ +} + +#define strix_halo_wwan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 11, \ + .end_logical_lane = CONFIG(ENABLE_WLANx0_WWANx2_MAPLE) ? 10 : 11, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define strix_halo_gbe_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 8, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define strix_halo_sd_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 9, \ + .end_logical_lane = 9, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .link_hotplug = HOTPLUG_BASIC, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +static fsp_ddi_descriptor maple_strix_halo_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI/DP */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + } +}; + +static uint8_t get_ddi1_type(void) +{ + const uint8_t eeprom_i2c_bus = 2; + const uint8_t eeprom_i2c_address = 0x55; + const uint16_t eeprom_connector_type_offset = 2; + uint16_t connector_type = 0; + + if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, + eeprom_connector_type_offset, (void *)&connector_type, + sizeof(connector_type))) { + printk(BIOS_NOTICE, + "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + /* On some NOVA cards it's LE, on some it's BE... */ + switch (connector_type) { + case 0x0c00: + case 0x000c: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + case 0x1300: + case 0x0013: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + case 0x1400: + case 0x0014: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + case 0x1700: + case 0x0017: + printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); + return DDI_DP_W_TYPEC; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", + connector_type); + return DDI_UNUSED_TYPE; + } +} + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + maple_strix_halo_ddi_descriptors[1].connector_type = get_ddi1_type(); + + static const fsp_dxio_descriptor maple_strix_halo_dxio_descriptors[] = { + strix_halo_ssd1_dxio_descriptor, + strix_halo_dt_mpcie_dxio_descriptor, + strix_halo_ssd0_dxio_descriptor, +#if !CONFIG(ENABLE_WLANx0_WWANx2_MAPLE) + strix_halo_wlan_dxio_descriptor, +#endif +#if !CONFIG(ENABLE_WLANx2_WWANx0_MAPLE) + strix_halo_wwan_dxio_descriptor, +#endif + strix_halo_gbe_dxio_descriptor, + strix_halo_sd_dxio_descriptor, + }; + + *dxio_descs = maple_strix_halo_dxio_descriptors; + *dxio_num = ARRAY_SIZE(maple_strix_halo_dxio_descriptors); + *ddi_descs = maple_strix_halo_ddi_descriptors; + *ddi_num = ARRAY_SIZE(maple_strix_halo_ddi_descriptors); +} diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index 18109c8c87e..b1e59507321 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -202,7 +202,7 @@ chip soc/intel/alderlake end device ref ish on end device ref hda on - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/i945_macs/Kconfig similarity index 52% rename from src/mainboard/apple/macbook21/Kconfig rename to src/mainboard/apple/i945_macs/Kconfig index 330d8efae2b..438ca6801b7 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/i945_macs/Kconfig @@ -1,14 +1,13 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_APPLE_I945_MACS_COMMON + bool select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX + select NO_UART_ON_SUPERIO select EC_ACPI select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -17,22 +16,44 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + +config BOARD_APPLE_MACBOOK11 + bool + select BOARD_APPLE_I945_MACS_COMMON select I945_LVDS +config BOARD_APPLE_MACBOOK21 + bool + select BOARD_APPLE_I945_MACS_COMMON + select I945_LVDS + +config BOARD_APPLE_IMAC52 + bool + select BOARD_APPLE_I945_MACS_COMMON + select I945_LVDS + +if BOARD_APPLE_I945_MACS_COMMON + config MAINBOARD_DIR - default "apple/macbook21" + default "apple/i945_macs" config MAINBOARD_PART_NUMBER default "Macbook1,1" if BOARD_APPLE_MACBOOK11 default "MacBook2,1" if BOARD_APPLE_MACBOOK21 default "iMac5,2" if BOARD_APPLE_IMAC52 +config VARIANT_DIR + default "macbook1_1" if BOARD_APPLE_MACBOOK11 + default "macbook2_1" if BOARD_APPLE_MACBOOK21 + default "imac5_2" if BOARD_APPLE_IMAC52 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAX_CPUS - int default 2 config MAINBOARD_SMBIOS_MANUFACTURER - string default "Apple Inc." endif diff --git a/src/mainboard/apple/macbook21/Kconfig.name b/src/mainboard/apple/i945_macs/Kconfig.name similarity index 100% rename from src/mainboard/apple/macbook21/Kconfig.name rename to src/mainboard/apple/i945_macs/Kconfig.name index 5d708007767..4a8c9392b10 100644 --- a/src/mainboard/apple/macbook21/Kconfig.name +++ b/src/mainboard/apple/i945_macs/Kconfig.name @@ -1,10 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_APPLE_MACBOOK21 - bool "Macbook2,1" - config BOARD_APPLE_MACBOOK11 bool "Macbook1,1" +config BOARD_APPLE_MACBOOK21 + bool "Macbook2,1" + config BOARD_APPLE_IMAC52 bool "iMac5,2" diff --git a/src/mainboard/apple/macbook21/Makefile.mk b/src/mainboard/apple/i945_macs/Makefile.mk similarity index 74% rename from src/mainboard/apple/macbook21/Makefile.mk rename to src/mainboard/apple/i945_macs/Makefile.mk index 115d7e9cbd9..d994847e50a 100644 --- a/src/mainboard/apple/macbook21/Makefile.mk +++ b/src/mainboard/apple/i945_macs/Makefile.mk @@ -5,3 +5,4 @@ bootblock-y += early_init.c romstage-y += early_init.c ramstage-y += cstates.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/i945_macs/acpi/ec.asl similarity index 100% rename from src/mainboard/apple/macbook21/acpi/ec.asl rename to src/mainboard/apple/i945_macs/acpi/ec.asl diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/i945_macs/acpi/ich7_pci_irqs.asl similarity index 100% rename from src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl rename to src/mainboard/apple/i945_macs/acpi/ich7_pci_irqs.asl diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/i945_macs/acpi/platform.asl similarity index 100% rename from src/mainboard/apple/macbook21/acpi/platform.asl rename to src/mainboard/apple/i945_macs/acpi/platform.asl diff --git a/src/mainboard/apple/macbook21/acpi/superio.asl b/src/mainboard/apple/i945_macs/acpi/superio.asl similarity index 100% rename from src/mainboard/apple/macbook21/acpi/superio.asl rename to src/mainboard/apple/i945_macs/acpi/superio.asl diff --git a/src/mainboard/apple/i945_macs/board_info.txt b/src/mainboard/apple/i945_macs/board_info.txt new file mode 100644 index 00000000000..aff34496b1a --- /dev/null +++ b/src/mainboard/apple/i945_macs/board_info.txt @@ -0,0 +1,4 @@ +Category: misc +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/i945_macs/cmos.default similarity index 100% rename from src/mainboard/apple/macbook21/cmos.default rename to src/mainboard/apple/i945_macs/cmos.default diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/i945_macs/cmos.layout similarity index 100% rename from src/mainboard/apple/macbook21/cmos.layout rename to src/mainboard/apple/i945_macs/cmos.layout diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/i945_macs/cstates.c similarity index 100% rename from src/mainboard/apple/macbook21/cstates.c rename to src/mainboard/apple/i945_macs/cstates.c diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb similarity index 85% rename from src/mainboard/apple/macbook21/devicetree.cb rename to src/mainboard/apple/i945_macs/devicetree.cb index fd86e939b9b..b17f8ae5296 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/i945_macs/devicetree.cb @@ -1,17 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "true" - register "pwm_freq" = "180" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/i945_macs/dsdt.asl similarity index 100% rename from src/mainboard/apple/macbook21/dsdt.asl rename to src/mainboard/apple/i945_macs/dsdt.asl diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/i945_macs/early_init.c similarity index 100% rename from src/mainboard/apple/macbook21/early_init.c rename to src/mainboard/apple/i945_macs/early_init.c diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/i945_macs/gpio.c similarity index 100% rename from src/mainboard/apple/macbook21/gpio.c rename to src/mainboard/apple/i945_macs/gpio.c diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/i945_macs/mainboard.c similarity index 100% rename from src/mainboard/apple/macbook21/mainboard.c rename to src/mainboard/apple/i945_macs/mainboard.c diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/i945_macs/mptable.c similarity index 100% rename from src/mainboard/apple/macbook21/mptable.c rename to src/mainboard/apple/i945_macs/mptable.c diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/i945_macs/smihandler.c similarity index 100% rename from src/mainboard/apple/macbook21/smihandler.c rename to src/mainboard/apple/i945_macs/smihandler.c diff --git a/src/mainboard/apple/i945_macs/variants/imac5_2/board_info.txt b/src/mainboard/apple/i945_macs/variants/imac5_2/board_info.txt new file mode 100644 index 00000000000..e24591746b8 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/imac5_2/board_info.txt @@ -0,0 +1,7 @@ +Board name: iMac5,2 +Category: aio +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2007 diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/i945_macs/variants/imac5_2/hda_verb.c similarity index 60% rename from src/mainboard/apple/macbook21/hda_verb.c rename to src/mainboard/apple/i945_macs/variants/imac5_2/hda_verb.c index d06fc0170fa..c6eccaa0418 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/i945_macs/variants/imac5_2/hda_verb.c @@ -2,23 +2,6 @@ #include -#if CONFIG(BOARD_APPLE_MACBOOK11) || CONFIG(BOARD_APPLE_MACBOOK21) -static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b2200; - -static const u32 sigmatel_stac9221_a1_verbs[] = { - AZALIA_SUBVENDOR(0, 0x106b2200), - AZALIA_PIN_CFG(0, 0x0a, 0x0321e21f), - AZALIA_PIN_CFG(0, 0x0b, 0x03a1e02e), - AZALIA_PIN_CFG(0, 0x0c, 0x9017e110), - AZALIA_PIN_CFG(0, 0x0d, 0x9017e11f), - AZALIA_PIN_CFG(0, 0x0e, 0x400000fe), - AZALIA_PIN_CFG(0, 0x0f, 0x0381e020), - AZALIA_PIN_CFG(0, 0x10, 0x1345e230), - AZALIA_PIN_CFG(0, 0x11, 0x13c5e240), - AZALIA_PIN_CFG(0, 0x15, 0x400000fc), - AZALIA_PIN_CFG(0, 0x1b, 0x400000fb), -}; -#else /* CONFIG_BOARD_APPLE_IMAC52 */ static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b0f00; static const u32 sigmatel_stac9221_a1_verbs[] = { @@ -34,7 +17,6 @@ static const u32 sigmatel_stac9221_a1_verbs[] = { AZALIA_PIN_CFG(0, 0x15, 0x4080e10f), AZALIA_PIN_CFG(0, 0x1b, 0x4080e10f), }; -#endif const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/apple/i945_macs/variants/imac5_2/overridetree.cb b/src/mainboard/apple/i945_macs/variants/imac5_2/overridetree.cb new file mode 100644 index 00000000000..ff3c4db1220 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/imac5_2/overridetree.cb @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/i945 + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "true" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" + + device domain 0 on + end +end diff --git a/src/mainboard/apple/i945_macs/variants/macbook1_1/board_info.txt b/src/mainboard/apple/i945_macs/variants/macbook1_1/board_info.txt new file mode 100644 index 00000000000..dd8866cd9c8 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/macbook1_1/board_info.txt @@ -0,0 +1,7 @@ +Board name: Macbook1,1 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/apple/i945_macs/variants/macbook1_1/hda_verb.c b/src/mainboard/apple/i945_macs/variants/macbook1_1/hda_verb.c new file mode 100644 index 00000000000..14c080963a2 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/macbook1_1/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b2200; + +static const u32 sigmatel_stac9221_a1_verbs[] = { + AZALIA_SUBVENDOR(0, 0x106b2200), + AZALIA_PIN_CFG(0, 0x0a, 0x0321e21f), + AZALIA_PIN_CFG(0, 0x0b, 0x03a1e02e), + AZALIA_PIN_CFG(0, 0x0c, 0x9017e110), + AZALIA_PIN_CFG(0, 0x0d, 0x9017e11f), + AZALIA_PIN_CFG(0, 0x0e, 0x400000fe), + AZALIA_PIN_CFG(0, 0x0f, 0x0381e020), + AZALIA_PIN_CFG(0, 0x10, 0x1345e230), + AZALIA_PIN_CFG(0, 0x11, 0x13c5e240), + AZALIA_PIN_CFG(0, 0x15, 0x400000fc), + AZALIA_PIN_CFG(0, 0x1b, 0x400000fb), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Sigmatel STAC9221 A1", + .vendor_id = 0x83847680, + .subsystem_id = sigmatel_stac9221_a1_subsystem_id, + .address = 0, + .verbs = sigmatel_stac9221_a1_verbs, + .verb_count = ARRAY_SIZE(sigmatel_stac9221_a1_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/i945_macs/variants/macbook1_1/overridetree.cb b/src/mainboard/apple/i945_macs/variants/macbook1_1/overridetree.cb new file mode 100644 index 00000000000..ff3c4db1220 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/macbook1_1/overridetree.cb @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/i945 + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "true" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" + + device domain 0 on + end +end diff --git a/src/mainboard/apple/macbook21/board_info.txt b/src/mainboard/apple/i945_macs/variants/macbook2_1/board_info.txt similarity index 100% rename from src/mainboard/apple/macbook21/board_info.txt rename to src/mainboard/apple/i945_macs/variants/macbook2_1/board_info.txt diff --git a/src/mainboard/apple/i945_macs/variants/macbook2_1/hda_verb.c b/src/mainboard/apple/i945_macs/variants/macbook2_1/hda_verb.c new file mode 100644 index 00000000000..14c080963a2 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/macbook2_1/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b2200; + +static const u32 sigmatel_stac9221_a1_verbs[] = { + AZALIA_SUBVENDOR(0, 0x106b2200), + AZALIA_PIN_CFG(0, 0x0a, 0x0321e21f), + AZALIA_PIN_CFG(0, 0x0b, 0x03a1e02e), + AZALIA_PIN_CFG(0, 0x0c, 0x9017e110), + AZALIA_PIN_CFG(0, 0x0d, 0x9017e11f), + AZALIA_PIN_CFG(0, 0x0e, 0x400000fe), + AZALIA_PIN_CFG(0, 0x0f, 0x0381e020), + AZALIA_PIN_CFG(0, 0x10, 0x1345e230), + AZALIA_PIN_CFG(0, 0x11, 0x13c5e240), + AZALIA_PIN_CFG(0, 0x15, 0x400000fc), + AZALIA_PIN_CFG(0, 0x1b, 0x400000fb), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Sigmatel STAC9221 A1", + .vendor_id = 0x83847680, + .subsystem_id = sigmatel_stac9221_a1_subsystem_id, + .address = 0, + .verbs = sigmatel_stac9221_a1_verbs, + .verb_count = ARRAY_SIZE(sigmatel_stac9221_a1_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/i945_macs/variants/macbook2_1/overridetree.cb b/src/mainboard/apple/i945_macs/variants/macbook2_1/overridetree.cb new file mode 100644 index 00000000000..ff3c4db1220 --- /dev/null +++ b/src/mainboard/apple/i945_macs/variants/macbook2_1/overridetree.cb @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/i945 + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "true" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" + + device domain 0 on + end +end diff --git a/src/mainboard/asrock/h370m-itx_ac/Kconfig b/src/mainboard/asrock/h370m-itx_ac/Kconfig new file mode 100644 index 00000000000..cdafb525993 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/Kconfig @@ -0,0 +1,41 @@ +if BOARD_ASROCK_H370M_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CRB_TPM + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_INTEL_PTT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + +config MAINBOARD_DIR + default "asrock/h370m-itx_ac" + +config MAINBOARD_PART_NUMBER + default "H370M-ITX/ac" + +config DIMM_SPD_SIZE + default 512 #DDR4 + +config DIMM_MAX + default 2 + +config TPM_PIRQ + hex + default 0x10 # GPP_A7/PIRQA# + +config CBFS_SIZE + default 0xa00000 # 12mb available + +endif diff --git a/src/mainboard/asrock/h370m-itx_ac/Kconfig.name b/src/mainboard/asrock/h370m-itx_ac/Kconfig.name new file mode 100644 index 00000000000..50bf492e3ed --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H370M_ITX + bool "H370M-ITX/ac" diff --git a/src/mainboard/asrock/h370m-itx_ac/Makefile.mk b/src/mainboard/asrock/h370m-itx_ac/Makefile.mk new file mode 100644 index 00000000000..93ced0a1c8a --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h370m-itx_ac/board_info.txt b/src/mainboard/asrock/h370m-itx_ac/board_info.txt new file mode 100644 index 00000000000..ffec43e6818 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/board_info.txt @@ -0,0 +1,8 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H370M-ITXac/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: n +ROM URL: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf +Flashrom support: y +Release year: 2020 diff --git a/src/mainboard/asrock/h370m-itx_ac/bootblock.c b/src/mainboard/asrock/h370m-itx_ac/bootblock.c new file mode 100644 index 00000000000..318e80426cf --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/bootblock.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT5539D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT5539D_ACPI) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + u8 cr26 = pnp_read_config(GLOBAL_DEV, 0x26); + pnp_write_config(GLOBAL_DEV, 0x26, cr26 | (1 << 4)); + pnp_write_config(GLOBAL_DEV, 0x13, 0xff); // Device IRQ Polarity for Channel<15:8> + pnp_write_config(GLOBAL_DEV, 0x14, 0xff); // Device IRQ Polarity for Channel<7:0> + pnp_write_config(GLOBAL_DEV, 0x26, cr26); // restore + + pnp_write_config(GLOBAL_DEV, 0x1a, 0x38); // Pin39, Pin23 + pnp_write_config(GLOBAL_DEV, 0x1b, 0x76); // Pin41, Pin46, Pin22 + pnp_write_config(GLOBAL_DEV, 0x1c, 0x90); // AUXFANIN2 + pnp_write_config(GLOBAL_DEV, 0x24, 0xff); // *FANOUT* + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); // Pin13,...Pin20 + pnp_write_config(GLOBAL_DEV, 0x2c, 0x40); // Pin34, Pin58, Pin60 + pnp_write_config(GLOBAL_DEV, 0x2d, 0x80); // Pin42 + + if (!acpi_is_wakeup_s3()) { + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe1, 0x07); // KBC Wake-Up Index Register + pnp_write_config(ACPI_DEV, 0xe2, 0x02); // KBC Wake-Up Index Register + pnp_write_config(ACPI_DEV, 0xe4, 0x38); // Power-loss control, always turn on + pnp_write_config(ACPI_DEV, 0xe6, 0xa1); // 300ms delay + pnp_write_config(ACPI_DEV, 0xe7, 0x01); // Hardware Monitor RESET, LRESET# + pnp_write_config(ACPI_DEV, 0xec, 0x04); // ACPI Control and Status Register + pnp_write_config(ACPI_DEV, 0xf0, 0x30); // DEEP_S5_1, 3VSBSW + pnp_write_config(ACPI_DEV, 0xf7, 0xc0); // PSIN_BLK_EN, RSTOUT1# Push-Pull + } + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/h370m-itx_ac/cmos.default b/src/mainboard/asrock/h370m-itx_ac/cmos.default new file mode 100644 index 00000000000..73af4f73235 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Info +power_on_after_fail=Disable +me_state=Enable +fast_boot=Enable +hyper_threading=Enable diff --git a/src/mainboard/asrock/h370m-itx_ac/cmos.layout b/src/mainboard/asrock/h370m-itx_ac/cmos.layout new file mode 100644 index 00000000000..eb796c15eb0 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/cmos.layout @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +430 1 e 10 fast_boot + +# coreboot config options: cpu +440 1 e 10 hyper_threading + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +7 0 Disable +7 1 Enable +7 2 Keep + +10 1 Enable +10 0 Disable + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/asrock/h370m-itx_ac/data.vbt b/src/mainboard/asrock/h370m-itx_ac/data.vbt new file mode 100644 index 00000000000..7a95d71c43b Binary files /dev/null and b/src/mainboard/asrock/h370m-itx_ac/data.vbt differ diff --git a/src/mainboard/asrock/h370m-itx_ac/devicetree.cb b/src/mainboard/asrock/h370m-itx_ac/devicetree.cb new file mode 100644 index 00000000000..91517d7a498 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/devicetree.cb @@ -0,0 +1,189 @@ +chip soc/intel/cannonlake + + register "eist_enable" = "true" + register "enable_c6dram" = "true" + + register "AcousticNoiseMitigation" = "1" + # needed for working WoL + register "WolEnableOverride" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_K" + register "gpe0_dw2" = "GPP_E" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PchPmSlpS3MinAssert" = "0x03" + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PchPmSlpS4MinAssert" = "0x04" + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PchPmSlpSusMinAssert" = "0x03" + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PchPmSlpAMinAssert" = "0x03" + + device domain 0 on + device ref peg0 on + register "PcieClkSrcUsage[0]" = "0x41" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE16X" "SlotDataBusWidth16X" + end + device ref igpu on end + device ref thermal on + subsystemid 0x1849 0xa379 + end + device ref xhci on + subsystemid 0x1849 0xa36d + + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB31_0 rear */ + [1] = USB2_PORT_MID(OC_SKIP), /* USB31_1 rear */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB31_2 rear */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB31_3 rear */ + [4] = USB2_PORT_MID(OC_SKIP), /* USB30_4 rear */ + [5] = USB2_PORT_MID(OC_SKIP), /* USB30_5 rear */ + [6] = USB2_PORT_MID(OC_SKIP), /* USB3_6 internal header */ + [7] = USB2_PORT_MID(OC_SKIP), /* USB3_7 internal header */ + [8] = USB2_PORT_MID(OC_SKIP), /* USB2_1 rear */ + [9] = USB2_PORT_MID(OC_SKIP), /* USB2_2 rear */ + [10] = USB2_PORT_MID(OC_SKIP), /* USB2_3 internal header */ + [11] = USB2_PORT_MID(OC_SKIP), /* USB2_4 internal header */ + [12] = USB2_PORT_SHORT(OC_SKIP), /* ? */ + [13] = USB2_PORT_SHORT(OC_SKIP), /* M2_WIFI1 bluetooth usb */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB31_3 rear */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB31_2 rear */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB31_1 rear */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB31_0 rear */ + [4] = USB3_PORT_DEFAULT(OC_SKIP), /* USB30_4 rear */ + [5] = USB3_PORT_DEFAULT(OC_SKIP), /* USB30_5 rear */ + [6] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_6 internal header */ + [7] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_7 internal header */ + }" + end + device ref heci1 on end + device ref sata on + register "satapwroptimize" = "1" + register "SataSalpSupport" = "0" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + }" + register "SataPortsHotPlug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + }" + end + device ref pcie_rp6 on + register "PcieRpSlotImplemented[5]" = "0" + register "PcieRpLtrEnable[5]" = "true" + register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" + register "PcieClkSrcUsage[9]" = "5" + register "PcieClkSrcClkReq[9]" = "9" + device pci 00.0 on end # Intel Corporation I211 Gigabit Network Connection + end + device ref pcie_rp7 on + register "PcieRpSlotImplemented[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" + register "PcieRpMaxPayload[6]" = "RpMaxPayload_256" + register "PcieClkSrcUsage[15]" = "6" + register "PcieClkSrcClkReq[15]" = "15" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" + end + device ref pcie_rp9 on + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" + register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" + register "PcieClkSrcUsage[14]" = "8" + register "PcieClkSrcClkReq[14]" = "14" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X" + end + device ref lpc_espi on + subsystemid 0x1849 0xa304 + + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct5539d # SuperIO chip found at port 0x2e + device pnp 2e.2 on end # UART A + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 # Keyboard + irq 0x72 = 0x0c # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0xff + irq 0xe1 = 0x06 + end + device pnp 2e.207 off end + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on end # GPIO4 + device pnp 2e.309 on + irq 0xf4 = 0xdf + end # GPIO5 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # Hardware Monitor, Front Panel LED + io 0x60 = 0x0290 + io 0x62 = 0x02a0 + irq 0x70 = 0x00 + end + device pnp 2e.d on end # WDT2 + device pnp 2e.e off end # CIR Wake-Up + device pnp 2e.f on end # GPIO Push-Pull or Open-Drain selection + device pnp 2e.11 on end # GPIO, RI PSOUT Wake-Up Status + device pnp 2e.12 on end # SW Error Control + device pnp 2e.15 on end # Fading LED + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + end + + end # device pnp 2e.0 + end # chip superio/common + + chip drivers/pc80/tpm # external TPM + device pnp 0c31.0 on end + end + end + device ref hda on + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on + register "PcieClkSrcUsage[10]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[10]" = "10" + end + chip drivers/crb + device mmio 0xfed40000 on end + end + end +end diff --git a/src/mainboard/asrock/h370m-itx_ac/dsdt.asl b/src/mainboard/asrock/h370m-itx_ac/dsdt.asl new file mode 100644 index 00000000000..6f50a142fc7 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + #include +} diff --git a/src/mainboard/asrock/h370m-itx_ac/gma-mainboard.ads b/src/mainboard/asrock/h370m-itx_ac/gma-mainboard.ads new file mode 100644 index 00000000000..7ffdd938f59 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h370m-itx_ac/gpio.c b/src/mainboard/asrock/h370m-itx_ac/gpio.c new file mode 100644 index 00000000000..8eb917ee82c --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/gpio.c @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "include/gpio.h" + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, PLTRST, GPIO), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + /* GPP_A7 - PIRQA# */ + PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF(GPP_A8, DN_5K, PLTRST, NF1), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF(GPP_A10, DN_5K, PLTRST, NF1), + /* GPP_A11 - PME# */ + PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_A12, 0, PLTRST), + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* GPP_A15 - SUSACK# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* GPP_A16 - CLKOUT_48 */ + PAD_CFG_NF(GPP_A16, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + PAD_CFG_GPO(GPP_A18, 1, PLTRST), + PAD_CFG_NF(GPP_A19, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_A20, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_A21, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_A22, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_A23, NONE, PLTRST, GPIO), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 1, PLTRST), + PAD_CFG_GPO(GPP_B1, 1, PLTRST), + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + PAD_CFG_NF(GPP_B3, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + // PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B6, 1, PLTRST), + PAD_CFG_NF(GPP_B7, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_B8, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_B9, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_B10, 1, PLTRST), + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPO(GPP_B15, 1, PLTRST), + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + PAD_CFG_GPO(GPP_B19, 1, PLTRST), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B22, 0, PLTRST), + PAD_CFG_GPO(GPP_B23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C5, 0, PLTRST), + PAD_CFG_GPO(GPP_C6, 1, PLTRST), + PAD_CFG_GPO(GPP_C7, 1, PLTRST), + PAD_CFG_GPO(GPP_C8, 1, PLTRST), + PAD_CFG_GPO(GPP_C9, 1, PLTRST), + PAD_CFG_GPO(GPP_C10, 1, PLTRST), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C16, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C17, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C18, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C19, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + PAD_CFG_GPO(GPP_C23, 1, PLTRST), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D3, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D5, 1, PLTRST), + PAD_CFG_GPO(GPP_D6, 1, PLTRST), + PAD_CFG_GPO(GPP_D7, 1, PLTRST), + PAD_CFG_GPO(GPP_D8, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D11, 1, PLTRST), + PAD_CFG_GPO(GPP_D12, 1, PLTRST), + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* GPP_D17 - DMIC_CLK1 */ + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + /* GPP_D18 - DMIC_DATA1 */ + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + /* GPP_D19 - DMIC_CLK0 */ + PAD_CFG_NF(GPP_D19, NONE, PLTRST, NF1), + /* GPP_D20 - DMIC_DATA0 */ + PAD_CFG_NF(GPP_D20, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D21, 1, PLTRST), + PAD_CFG_GPO(GPP_D22, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 1, PLTRST), + PAD_CFG_GPO(GPP_G1, 1, PLTRST), + PAD_CFG_GPO(GPP_G2, 1, PLTRST), + PAD_CFG_GPO(GPP_G3, 1, PLTRST), + PAD_CFG_GPO(GPP_G4, 1, PLTRST), + PAD_CFG_GPO(GPP_G5, 1, PLTRST), + PAD_CFG_GPO(GPP_G6, 1, PLTRST), + PAD_CFG_GPO(GPP_G7, 1, PLTRST), + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPD1, NONE, PLTRST, GPIO), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + PAD_CFG_GPO(GPD7, 1, PLTRST), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + /* GPD11 - LANPHYPC */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_NF(GPP_K0, NONE, RSMRST, GPIO), + PAD_CFG_NF(GPP_K1, NONE, RSMRST, GPIO), + PAD_CFG_GPO(GPP_K2, 1, PLTRST), + PAD_CFG_GPO(GPP_K3, 1, PLTRST), + PAD_CFG_GPO(GPP_K4, 1, PLTRST), + PAD_CFG_GPO(GPP_K5, 0, RSMRST), + PAD_CFG_GPO(GPP_K6, 0, RSMRST), + PAD_CFG_GPO(GPP_K7, 0, RSMRST), + PAD_CFG_GPO(GPP_K8, 1, PLTRST), + PAD_CFG_GPO(GPP_K9, 1, PLTRST), + PAD_CFG_GPO(GPP_K10, 1, PLTRST), + PAD_CFG_GPO(GPP_K11, 1, PLTRST), + PAD_CFG_GPO(GPP_K12, 1, PLTRST), + PAD_CFG_NF(GPP_K13, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_K14, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_K15, 1, PLTRST), + PAD_CFG_GPO(GPP_K16, 1, PLTRST), + PAD_CFG_GPO(GPP_K17, 1, PLTRST), + PAD_CFG_GPO(GPP_K18, 1, PLTRST), + PAD_CFG_GPO(GPP_K19, 1, PLTRST), + PAD_CFG_GPO(GPP_K20, 1, PLTRST), + PAD_CFG_GPO(GPP_K21, 1, PLTRST), + PAD_CFG_GPO(GPP_K22, 1, PLTRST), + PAD_CFG_GPO(GPP_K23, 1, PLTRST), + + /* ------- GPIO Group GPP_H ------- */ + /* SRCCLKREQ6 */ + PAD_CFG_NF(GPP_H0, NONE, PLTRST, GPIO), + /* SRCCLKREQ7 */ + PAD_CFG_NF(GPP_H1, NONE, PLTRST, GPIO), + /* SRCCLKREQ8 */ + PAD_CFG_NF(GPP_H2, NONE, PLTRST, GPIO), + /* SRCCLKREQ9 */ + PAD_CFG_NF(GPP_H3, NONE, PLTRST, NF1), + /* SRCCLKREQ10 */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* SRCCLKREQ11 */ + PAD_CFG_NF(GPP_H5, NONE, PLTRST, GPIO), + /* SRCCLKREQ12 */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, GPIO), + /* SRCCLKREQ13 */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, GPIO), + /* SRCCLKREQ14 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, GPIO), + /* SRCCLKREQ15 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* PCIE_SMB_CLK */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), + /* PCIE_SMB_DATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_H19, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_NF(GPP_H23, NONE, RSMRST, GPIO), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - SATAXPCIE0 */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), + /* GPP_E1 - SATAXPCIE1 - M.2 SATA/PCIe detect */ + PAD_CFG_GPI(GPP_E1, NONE, PLTRST), + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_GPO(GPP_E2, 1, PLTRST), + /* GPP_E3 - CPU_GP0 */ + PAD_CFG_NF(GPP_E3, NONE, PLTRST, GPIO), + PAD_CFG_NF(GPP_E4, NONE, RSMRST, NF1), + /* GPP_E5 - SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), + PAD_CFG_GPO(GPP_E7, 1, PLTRST), + /* GPP_E8 - SATA_LED# */ + PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1), + /* GPP_E9 - USB2_OC0# */ + PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + PAD_CFG_GPO(GPP_E11, 1, PLTRST), + PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - SATAXPCIE3 */ + PAD_CFG_NF(GPP_F0, UP_5K, PLTRST, NF1), + /* GPP_F1 - SATAXPCIE4 */ + PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_F3, 1, PLTRST), + PAD_CFG_GPO(GPP_F4, 1, PLTRST), + PAD_CFG_NF(GPP_F5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_F7, NONE, RSMRST, NF1), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* Wi-Fi Unblock (Set to Input, let card pull high) */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* Bluetooth Unblock (Output High) */ + PAD_CFG_GPO(GPP_F11, 1, PLTRST), + PAD_CFG_GPO(GPP_F12, 0, RSMRST), + PAD_CFG_GPO(GPP_F13, 0, RSMRST), + /* GPP_F14 - PS_ON# */ + PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF2), + PAD_CFG_GPO(GPP_F15, 1, PLTRST), + PAD_CFG_GPO(GPP_F16, 1, PLTRST), + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + PAD_CFG_GPO(GPP_F19, 1, PLTRST), + PAD_CFG_GPO(GPP_F20, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - DDPB_HPD0 */ + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + /* GPP_I1 - DDPB_HPD1 */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + /* GPP_I2 - DDPB_HPD2 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_I3, 1, PLTRST), + /* GPP_I4 - EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + /* GPP_I5 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + /* GPP_I6 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + /* GPP_I7 - DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + /* GPP_I8 - DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + /* GPP_I9 - DDPD_CTRLCLK */ + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + /* GPP_I10 - DDPD_CTRLDATA */ + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_I11, 1, PLTRST), + PAD_CFG_GPO(GPP_I12, 1, PLTRST), + PAD_CFG_GPO(GPP_I13, 1, PLTRST), + PAD_CFG_GPO(GPP_I14, 1, PLTRST), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPO(GPP_J0, 1, PLTRST), + /* GPP_J1 - CPU_C10_GATE# */ + PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF2), + PAD_CFG_GPO(GPP_J2, 1, PLTRST), + PAD_CFG_GPO(GPP_J3, 1, PLTRST), + PAD_CFG_NF(GPP_J4, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_J5, 1, PLTRST), + PAD_CFG_NF(GPP_J6, NONE, PLTRST, GPIO), + PAD_CFG_GPO(GPP_J7, 1, PLTRST), + PAD_CFG_GPO(GPP_J8, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_J10, 1, PLTRST), + PAD_CFG_GPO(GPP_J11, 1, PLTRST), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asrock/h370m-itx_ac/include/gpio.h b/src/mainboard/asrock/h370m-itx_ac/include/gpio.h new file mode 100644 index 00000000000..ef2a21c4188 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/include/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/asrock/h370m-itx_ac/ramstage.c b/src/mainboard/asrock/h370m-itx_ac/ramstage.c new file mode 100644 index 00000000000..a4bc1d8e2fd --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/ramstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* + * Enable Intel PTT (fTPM) via HECI FW_FEATURE_SHIPMENT_OVERRIDE. + * This must happen before FSP Silicon Init / End-of-Post, while + * HECI is still available. If PTT state changes, cse_enable_ptt() + * triggers a global reset; on the subsequent boot PTT is active + * and the CRB TPM at 0xfed40000 is usable. If PTT is already + * enabled this is a no-op. + */ + cse_enable_ptt(true); +} + +static void init_mainboard(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/asrock/h370m-itx_ac/romstage.c b/src/mainboard/asrock/h370m-itx_ac/romstage.c new file mode 100644 index 00000000000..9d4833a5c86 --- /dev/null +++ b/src/mainboard/asrock/h370m-itx_ac/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static const struct cnl_mb_cfg baseboard_mem_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa0}}, + .spd[1] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa2}}, + .spd[2] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa4}}, + .spd[3] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa6}}, + + .rcomp_resistor = {121, 75, 100}, + .rcomp_targets = {60, 26, 20, 20, 26}, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memupd->FspmConfig.UserBd = BOARD_TYPE_DESKTOP; + + memupd->FspmConfig.MrcFastBoot = get_uint_option("fast_boot", true); + + cannonlake_memcfg_init(&memupd->FspmConfig, &baseboard_mem_cfg); +} diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 48633d5f695..ef1cc017b92 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb index c26baeaa0fb..e297547f44d 100644 --- a/src/mainboard/asrock/imb-1222/devicetree.cb +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc diff --git a/src/mainboard/asrock/z87_extreme3/hda_verb.c b/src/mainboard/asrock/z87_extreme3/hda_verb.c index 550c58923d6..4ebff3a1604 100644 --- a/src/mainboard/asrock/z87_extreme3/hda_verb.c +++ b/src/mainboard/asrock/z87_extreme3/hda_verb.c @@ -4,20 +4,84 @@ static const u32 realtek_alc892_verbs[] = { AZALIA_SUBVENDOR(0, 0x1849c892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19840), - AZALIA_PIN_CFG(0, 0x19, 0x02a19850), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), - AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT | 0x8, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT | 0x8, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_GREY, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/z87_extreme4/hda_verb.c b/src/mainboard/asrock/z87_extreme4/hda_verb.c index 1399a3f3fbf..9305373c742 100644 --- a/src/mainboard/asrock/z87_extreme4/hda_verb.c +++ b/src/mainboard/asrock/z87_extreme4/hda_verb.c @@ -4,16 +4,80 @@ static const u32 realtek_alc1150_verbs[] = { AZALIA_SUBVENDOR(0, 0x18491151), - AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x01a19040), - AZALIA_PIN_CFG(0, 0x19, 0x02a19050), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/z87_extreme6/Kconfig b/src/mainboard/asrock/z87_extreme6/Kconfig new file mode 100644 index 00000000000..c43339f3ef6 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASM1061 + select GFX_GMA_ANALOG_I2C_HDMI_B + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme6" + +config USBDEBUG_HCD_INDEX + default 2 # Header1: USB2_3 + # Header2: USB3_6_7 +endif diff --git a/src/mainboard/asrock/z87_extreme6/Kconfig.name b/src/mainboard/asrock/z87_extreme6/Kconfig.name new file mode 100644 index 00000000000..13ffd65dc7a --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME6 + bool "Z87 Extreme6" diff --git a/src/mainboard/intel/dcp847ske/Makefile.mk b/src/mainboard/asrock/z87_extreme6/Makefile.mk similarity index 68% rename from src/mainboard/intel/dcp847ske/Makefile.mk rename to src/mainboard/asrock/z87_extreme6/Makefile.mk index f8c155e4c3f..c3cf55d3979 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.mk +++ b/src/mainboard/asrock/z87_extreme6/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += early_southbridge.c -romstage-y += early_southbridge.c +bootblock-y += bootblock.c bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme6/acpi/ec.asl b/src/mainboard/asrock/z87_extreme6/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme6/acpi/platform.asl b/src/mainboard/asrock/z87_extreme6/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme6/acpi/superio.asl b/src/mainboard/asrock/z87_extreme6/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme6/board_info.txt b/src/mainboard/asrock/z87_extreme6/board_info.txt new file mode 100644 index 00000000000..ee5d4abba8c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme6/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme6/bootblock.c b/src/mainboard/asrock/z87_extreme6/bootblock.c new file mode 100644 index 00000000000..20250226f6c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/bootblock.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x4e); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme6/data.vbt b/src/mainboard/asrock/z87_extreme6/data.vbt new file mode 100644 index 00000000000..4bb86662ce3 Binary files /dev/null and b/src/mainboard/asrock/z87_extreme6/data.vbt differ diff --git a/src/mainboard/asrock/z87_extreme6/devicetree.cb b/src/mainboard/asrock/z87_extreme6/devicetree.cb new file mode 100644 index 00000000000..18dec8bd3bd --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/devicetree.cb @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIE2 + subsystemid 0x1849 0x0c01 + end + device pci 01.1 on # PCIE3 + subsystemid 0x1849 0x0c05 + end + device pci 01.2 on # PCIE4 + subsystemid 0x1849 0x0c09 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 off end # RP #1: (lane used for USB3) + device pci 1c.1 on # RP #2: MINI_PCIE1 + subsystemid 0x1849 0x8c12 + end + device pci 1c.2 on # RP #3: ASMedia ASM1061 SATA Controller (SATA3_A1_A2) + subsystemid 0x1849 0x8c14 + end + device pci 1c.3 on # RP #4: Intel I211 GbE NIC + subsystemid 0x1849 0x8c16 + device pci 00.0 on end + end + device pci 1c.4 on # RP #5: ASMedia ASM1061 SATA Controller (SATA3_A3_A4) + subsystemid 0x1849 0x8c18 + end + device pci 1c.5 on # RP #6: PCIE1 + subsystemid 0x1849 0x8c1a + end + device pci 1c.6 on # RP #7: ASMedia ASM1083 PCIe-to-PCI-bridge + subsystemid 0x1849 0x8c1c + end + device pci 1c.7 off end # RP #8: (lane used for PCH GbE) + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # UART B, IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + irq 0xf1 = 0x5c + end + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 on end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87_extreme6/dsdt.asl b/src/mainboard/asrock/z87_extreme6/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme6/gma-mainboard.ads new file mode 100644 index 00000000000..da296b38b83 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DDI C + HDMI1, -- DVI-I + HDMI2, -- DP (dual-mode) + HDMI3, -- HDMI + Analog,-- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme6/gpio.c b/src/mainboard/asrock/z87_extreme6/gpio.c new file mode 100644 index 00000000000..4213ac14cb1 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme6/hda_verb.c b/src/mainboard/asrock/z87_extreme6/hda_verb.c new file mode 100644 index 00000000000..9305373c742 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/hda_verb.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x18491151, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme6/mainboard.c b/src/mainboard/asrock/z87_extreme6/mainboard.c new file mode 100644 index 00000000000..8e30e3c61cc --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/mainboard.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include +#include +#include +#include +#include +#include +#include + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/z87_extreme6/romstage.c b/src/mainboard/asrock/z87_extreme6/romstage.c new file mode 100644 index 00000000000..52e7f0072c8 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/z87_extreme6/smihandler.c b/src/mainboard/asrock/z87_extreme6/smihandler.c new file mode 100644 index 00000000000..5ecf42409c6 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme6/smihandler.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +} diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c index ff58f699895..0454b5f823b 100644 --- a/src/mainboard/asrock/z87e-itx/hda_verb.c +++ b/src/mainboard/asrock/z87e-itx/hda_verb.c @@ -4,16 +4,80 @@ static const u32 realtek_alc1150_verbs[] = { AZALIA_SUBVENDOR(0, 0x18491150), - AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x01a19040), - AZALIA_PIN_CFG(0, 0x19, 0x02a19050), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/z87m_extreme4/hda_verb.c b/src/mainboard/asrock/z87m_extreme4/hda_verb.c index b9d9e9d8895..9305373c742 100644 --- a/src/mainboard/asrock/z87m_extreme4/hda_verb.c +++ b/src/mainboard/asrock/z87m_extreme4/hda_verb.c @@ -4,16 +4,80 @@ static const u32 realtek_alc1150_verbs[] = { AZALIA_SUBVENDOR(0, 0x18491151), - AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19040), - AZALIA_PIN_CFG(0, 0x19, 0x02a19050), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c index 1399a3f3fbf..9305373c742 100644 --- a/src/mainboard/asrock/z97_extreme6/hda_verb.c +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -4,16 +4,80 @@ static const u32 realtek_alc1150_verbs[] = { AZALIA_SUBVENDOR(0, 0x18491151), - AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x01a19040), - AZALIA_PIN_CFG(0, 0x19, 0x02a19050), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/z97e-itx_ac/hda_verb.c b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c index ff58f699895..0454b5f823b 100644 --- a/src/mainboard/asrock/z97e-itx_ac/hda_verb.c +++ b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c @@ -4,16 +4,80 @@ static const u32 realtek_alc1150_verbs[] = { AZALIA_SUBVENDOR(0, 0x18491150), - AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x01a19040), - AZALIA_PIN_CFG(0, 0x19, 0x02a19050), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index d09ed1e244a..f2796e6a0ba 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -30,6 +30,15 @@ config BOARD_ASUS_H61M_CS select NO_UART_ON_SUPERIO select SUPERIO_NUVOTON_NCT6779D +config BOARD_ASUS_P8H61_I_R2_0 + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_8192 + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select NO_UART_ON_SUPERIO + select REALTEK_8168_RESET + select SUPERIO_ITE_IT8772F + config BOARD_ASUS_P8H61_M_LX select BOARD_ASUS_H61_SERIES select BOARD_ROMSIZE_KB_4096 @@ -40,6 +49,14 @@ config BOARD_ASUS_P8H61_M_LX select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 +config BOARD_ASUS_P8H61_M_LX2 + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_4096 + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6776 + config BOARD_ASUS_P8H61_M_LX3_R2_0 select BOARD_ASUS_H61_SERIES select BOARD_ROMSIZE_KB_8192 @@ -87,19 +104,23 @@ config MAINBOARD_DIR config VARIANT_DIR default "h61m-a_usb3" if BOARD_ASUS_H61M_A_USB3 default "h61m-cs" if BOARD_ASUS_H61M_CS + default "p8h61-i_r2_0" if BOARD_ASUS_P8H61_I_R2_0 default "p8h61-m_lx" if BOARD_ASUS_P8H61_M_LX + default "p8h61-m_lx2" if BOARD_ASUS_P8H61_M_LX2 default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 default "p8h67-i_deluxe" if BOARD_ASUS_P8H67_I_DELUXE config MAINBOARD_PART_NUMBER - default "H61M-CS" if BOARD_ASUS_H61M_CS - default "P8H61-M LX" if BOARD_ASUS_P8H61_M_LX - default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 - default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO + default "H61M-CS" if BOARD_ASUS_H61M_CS + default "P8H61-I R2.0" if BOARD_ASUS_P8H61_I_R2_0 + default "P8H61-M LX" if BOARD_ASUS_P8H61_M_LX + default "P8H61-M LX2" if BOARD_ASUS_P8H61_M_LX2 + default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO default "P8H61-M PRO CM6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 - default "P8H67-I DELUXE" if BOARD_ASUS_P8H67_I_DELUXE + default "P8H67-I DELUXE" if BOARD_ASUS_P8H67_I_DELUXE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -121,6 +142,6 @@ config CBFS_SIZE config ME_CLEANER_ARGS string depends on USE_ME_CLEANER - default "-S --whitelist EFFS,FCRS" if BOARD_ASUS_P8H61_M_LX + default "-S --whitelist EFFS,FCRS" if BOARD_ASUS_P8H61_M_LX || BOARD_ASUS_P8H61_I_R2_0 endif diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name index e1e2317f093..acfa6ea2121 100644 --- a/src/mainboard/asus/h61-series/Kconfig.name +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -6,9 +6,15 @@ config BOARD_ASUS_H61M_A_USB3 config BOARD_ASUS_H61M_CS bool "H61M-CS" +config BOARD_ASUS_P8H61_I_R2_0 + bool "P8H61-I R2.0" + config BOARD_ASUS_P8H61_M_LX bool "P8H61-M LX" +config BOARD_ASUS_P8H61_M_LX2 + bool "P8H61-M LX2" + config BOARD_ASUS_P8H61_M_LX3_R2_0 bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/h61-series/Makefile.mk b/src/mainboard/asus/h61-series/Makefile.mk index e3392856201..361a1cc17ac 100644 --- a/src/mainboard/asus/h61-series/Makefile.mk +++ b/src/mainboard/asus/h61-series/Makefile.mk @@ -6,3 +6,4 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads +smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/smihandler.c) diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c index df1fb43b95d..be11186a1f9 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c @@ -21,20 +21,7 @@ static const u32 realtek_alc887_verbs[] = { AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)), }; -static const u32 intel_display_audio_1_verbs[] = { - AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x04, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560010), - AZALIA_PIN_CFG(2, 0x08, 0x18560010), - AZALIA_PIN_CFG(2, 0x0a, 0x18560010), - AZALIA_PIN_CFG(2, 0x0b, 0x18560010), - AZALIA_PIN_CFG(2, 0x0c, 0x18560010), - AZALIA_PIN_CFG(2, 0x0d, 0x18560010), - AZALIA_PIN_CFG(2, 0x0e, 0x18560010), - AZALIA_PIN_CFG(2, 0x0f, 0x18560010), -}; - -static const u32 intel_display_audio_2_verbs[] = { +static const u32 intel_display_audio_verbs[] = { AZALIA_SUBVENDOR(3, 0x80860101), AZALIA_PIN_CFG(3, 0x05, 0x58560010), AZALIA_PIN_CFG(3, 0x06, 0x58560020), @@ -53,29 +40,12 @@ struct azalia_codec mainboard_azalia_codecs[] = { .verb_count = ARRAY_SIZE(realtek_alc887_verbs), }, { - /* - * TODO: This seems out of place, the vendor ID suggests this - * codec is an Alder Lake P Intel Display Audio[1], and - * the user manual[2] does not mention this codec. Could someone - * with this board confirm what this is? - * - * [1] Linux kernel: sound/hda/codecs/hdmi/intelhdmi.c:789 - * [2] H61M-A/USB3 User's Manual (English), Version E8184 - */ - .name = "Intel Display Audio #1 (HDMI/DP)", - .vendor_id = 0x8086281c, - .subsystem_id = 0x80860101, - .address = 2, - .verbs = intel_display_audio_1_verbs, - .verb_count = ARRAY_SIZE(intel_display_audio_1_verbs), - }, - { - .name = "Intel Display Audio #2 (HDMI/DP)", + .name = "Intel Display Audio (HDMI/DP)", .vendor_id = 0x80862805, .subsystem_id = 0x80860101, .address = 3, - .verbs = intel_display_audio_2_verbs, - .verb_count = ARRAY_SIZE(intel_display_audio_2_verbs), + .verbs = intel_display_audio_verbs, + .verb_count = ARRAY_SIZE(intel_display_audio_verbs), }, { /* terminator */ } }; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/board_info.txt new file mode 100644 index 00000000000..131a7bd444c --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/board_info.txt @@ -0,0 +1,8 @@ +Category: desktop +Board URL: https://www.asus.com/us/supportonly/p8h61-i%20r2-0/helpdesk_manual/ +ROM IC: W25Q64FV +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.default b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.default new file mode 100644 index 00000000000..1220d7298c4 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.default @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M +#hyper_threading=Enable diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.layout new file mode 100644 index 00000000000..a670118dd66 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/cmos.layout @@ -0,0 +1,68 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 2 e 9 sata_mode + +# coreboot config options: cpu +#427 1 e 1 hyper_threading + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible +9 2 Legacy +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/data.vbt new file mode 100644 index 00000000000..1e05be6bdd7 Binary files /dev/null and b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/data.vbt differ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/early_init.c new file mode 100644 index 00000000000..07e237642d1 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/early_init.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define IT8772F_BASE 0x2e +#define EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) +#define GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, 0x3c0f); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + + ite_disable_pme_out(EC_DEV); + ite_ac_resume_southbridge(EC_DEV); + ite_disable_3vsbsw(GPIO_DEV); + ite_kill_watchdog(GPIO_DEV); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gma-mainboard.ads new file mode 100644 index 00000000000..08fbd1d33f3 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, -- mainboard HDMI port + HDMI1, -- mainboard DVI-D port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gpio.c new file mode 100644 index 00000000000..5eb3f561c77 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/gpio.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio27 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/hda_verb.c new file mode 100644 index 00000000000..e9fe35443dc --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/hda_verb.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 via_vt1708s_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x185600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +static const u32 intel_display_audio_verbs[] = { + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "VIA VT1708S", + .vendor_id = 0x11060397, + .subsystem_id = 0x10438415, + .address = 0, + .verbs = via_vt1708s_verbs, + .verb_count = ARRAY_SIZE(via_vt1708s_verbs), + }, + { + .name = "Intel CougarPoint HDMI", + .vendor_id = 0x80862805, + .subsystem_id = 0x80860101, + .address = 3, + .verbs = intel_display_audio_verbs, + .verb_count = ARRAY_SIZE(intel_display_audio_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/overridetree.cb new file mode 100644 index 00000000000..6e9c8b49b1d --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/overridetree.cb @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device domain 0x0 on + subsystemid 0x1043 0x844d inherit + device ref peg10 on + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "PCIEX16" "SlotDataBusWidth16X" + end + device ref igd on + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + end + chip southbridge/intel/bd82x6x # Intel 6 Series Cougar Point PCH + register "usb_port_config" = "{ + {1, 0xf5f, 0}, + {1, 0xf5f, 0}, + {1, 0xf5f, 1}, + {1, 0xf5f, 1}, + {1, 0x95f, 2}, + {1, 0xf5f, 2}, + {1, 0xb57, 3}, + {1, 0xb57, 3}, + {1, 0x353, 4}, + {1, 0x353, 4}, + {1, 0xb5f, 6}, + {1, 0xb5f, 5}, + {1, 0xb57, 5}, + {1, 0xb57, 6}, + }" + device ref hda on + subsystemid 0x1043 0x8415 + end + device ref pcie_rp5 on # RTL8111F Gigabit Ethernet Controller + device pci 00.0 on end + end + device ref pcie_rp6 on end # ASM1042A USB 3.0 Host Controller + device ref lpc on + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00fc0a01" + + chip superio/ite/it8772f + device pnp 2e.0 off end # FDC + device pnp 2e.1 off # COM + io 0x60 = 0x03f8 + irq 0x70 = 0x04 + irq 0xf1 = 0x50 + end + device pnp 2e.4 on # EC / HWM + io 0x60 = 0x0290 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + irq 0x70 = 1 + io 0x62 = 0x0064 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + end + end + end +end diff --git a/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/smihandler.c b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/smihandler.c new file mode 100644 index 00000000000..f94fef6a276 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-i_r2_0/smihandler.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) + +void mainboard_smi_sleep(u8 slp_typ) +{ + switch (slp_typ) { + case ACPI_S3: + ite_enable_3vsbsw(GPIO_DEV); + ite_delay_pwrgd3(GPIO_DEV); + break; + default: + break; + } +} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/board_info.txt new file mode 100644 index 00000000000..517a65921c1 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/p8h61-m_lx2/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/data.vbt new file mode 100644 index 00000000000..33ffe7eab09 Binary files /dev/null and b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/data.vbt differ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/early_init.c new file mode 100644 index 00000000000..cb521ae7e64 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x06); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x34); + pnp_write_config(GLOBAL_DEV, 0x27, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gma-mainboard.ads new file mode 100644 index 00000000000..1f292460336 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gpio.c new file mode 100644 index 00000000000..93b1c73d86a --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/gpio.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio44 = GPIO_RESET_RSMRST, + .gpio45 = GPIO_RESET_RSMRST, + .gpio46 = GPIO_RESET_RSMRST, + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/hda_verb.c new file mode 100644 index 00000000000..bc2e2d3fee1 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 via_vt1708s_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x185600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "VIA VT1708S", + .vendor_id = 0x11060397, + .subsystem_id = 0x10438415, + .address = 0, + .verbs = via_vt1708s_verbs, + .verb_count = ARRAY_SIZE(via_vt1708s_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/overridetree.cb new file mode 100644 index 00000000000..dcb126b2367 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx2/overridetree.cb @@ -0,0 +1,98 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + device domain 0 on + subsystemid 0x1043 0x844d inherit + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + {1, 0xf5f, 0}, + {1, 0xf5f, 0}, + {1, 5, 1}, + {1, 0x25f, 1}, + {1, 0x4f2, 2}, + {1, 0x757, 2}, + {1, 0xb57, 3}, + {1, 0xb57, 3}, + {1, 0x353, 4}, + {1, 0x353, 4}, + {1, 0xb5f, 5}, + {1, 0xb5f, 5}, + {1, 0xb57, 6}, + {1, 0xb57, 6}, + }" + register "gen1_dec" = "0x000c0291" + device ref hda on + subsystemid 0x1043 0x8415 + end + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1_1) + device ref pcie_rp2 on end # PCIe x1 Port (PCIEX1_2) + device ref pcie_rp3 on # ASMedia ASM1083 PCIe-to-PCI bridge + device pci 00.0 on + subsystemid 0x1043 0x8489 + end + end + device ref pcie_rp4 on # Realtek RTL8111E Ethernet Controller + chip drivers/net + register "customized_leds" = "0x00f6" + register "wake" = "9" + device pci 00.0 on + subsystemid 0x1043 0x8432 + end + end + end + device ref pcie_rp5 off end # USB 3.0 controller, unpopulated + device ref pcie_rp6 off end # SATA controller, unpopulated + + device ref lpc on + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe5 = 0x02 + irq 0xe6 = 0x5c + irq 0xe7 = 0x01 + irq 0xf0 = 0x00 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0000 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on # GPIO Push-Pull or Open-drain + irq 0xf0 = 0x9d + end + device pnp 2e.14 off end # SVID + device pnp 2e.16 on # Deep Sleep + io 0x30 = 0x20 + end + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe5 = 0xff + end + end + end + end + end +end diff --git a/src/mainboard/asus/h610i-plus-d4/Kconfig b/src/mainboard/asus/h610i-plus-d4/Kconfig index e4f75980665..e51b50edc40 100644 --- a/src/mainboard/asus/h610i-plus-d4/Kconfig +++ b/src/mainboard/asus/h610i-plus-d4/Kconfig @@ -8,6 +8,7 @@ config BOARD_ASUS_H610I_PLUS_D4 select INTEL_GMA_HAVE_VBT select SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_NUVOTON_COMMON_HWM select SUPERIO_NUVOTON_NCT6791D select USE_LEGACY_8254_TIMER diff --git a/src/mainboard/asus/h610i-plus-d4/devicetree.cb b/src/mainboard/asus/h610i-plus-d4/devicetree.cb index 8a7fd7390ec..54289db803d 100644 --- a/src/mainboard/asus/h610i-plus-d4/devicetree.cb +++ b/src/mainboard/asus/h610i-plus-d4/devicetree.cb @@ -4,7 +4,7 @@ chip soc/intel/alderlake # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" @@ -180,7 +180,7 @@ chip soc/intel/alderlake device ref hda on register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_sdi_enable[0]" = "1" - register "pch_hda_dsp_enable" = "0" + register "pch_hda_dsp_enable" = "false" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/asus/h610i-plus-d4/mainboard.c b/src/mainboard/asus/h610i-plus-d4/mainboard.c index ff24624972a..bb85e1cdb53 100644 --- a/src/mainboard/asus/h610i-plus-d4/mainboard.c +++ b/src/mainboard/asus/h610i-plus-d4/mainboard.c @@ -10,84 +10,49 @@ #include #include -// This is the base address of the HWM registers (set in the device tree) +/* HWM base address, set in devicetree.cb. */ #define HWM_IOBASE 0x290 -// The registers below are in a separate bank for each fan -// On the H610I-PLUS and H610M-K only SYSFAN and CPUFAN are wired up +/* Alder Lake desktop Tjmax in degrees Celsius. */ +#define CPU_TJMAX 100 + +/* Per-fan register banks. Only SYSFAN and CPUFAN are wired up. */ #define BANK_SYSFAN 1 #define BANK_CPUFAN 2 -#define FAN_SOURCE 0x00 // Fan control temperature source -# define FAN_SOURCE_PECI0 0x10 // PECI Agent 0 -# define FAN_SOURCE_PECI0_CAL 0x1c // PECI Agent 0 Calibration - -#define FAN_MODE_TEMP_TOLERANCE 0x02 // [7:4] = mode [2:0] temperature tolerance -# define FAN_MODE_SFIV 4 // SmartFan IV -#define FAN_STEP_UP_TIME 0x03 // In 0.1 sec -#define FAN_STEP_DOWN_TIME 0x04 // In 0.1 sec -#define FAN_DUTY_PER_STEP 0x66 // [7:4] step up val [3:0] step down val - -#define FAN_TEMP(i) (0x21 + (i)) // Temperature points on the curve (4 points) -#define FAN_DUTY(i) (0x27 + (i)) // Corresponding duty for each temperature point - -#define FAN_CRIT_TEMP 0x35 // Critical temperature -#define FAN_CRIT_DUTY_EN 0x36 // Use critical duty (or default to 255) -#define FAN_CRIT_DUTY 0x37 // Critical duty -#define FAN_CRIT_TEMP_TOLERANCE 0x38 // Critical temperature tolerance - -struct nct_fan { - const char *name; - uint8_t bank; - - // Temperature source - uint8_t source; - - // Temperature x duty cycle curve points - uint8_t temp[4]; - uint8_t duty[4]; - - // Temperature tolerance - uint8_t temp_tolerance; - - // Step up and down smoothing - uint8_t step_up_time; - uint8_t step_down_time; - uint8_t duty_per_step_up; - uint8_t duty_per_step_down; - - // Critical mode - uint8_t crit_temp; - uint8_t crit_duty_en; - uint8_t crit_duty; - uint8_t crit_temp_tolerance; -}; - -#define PERCENT_TO_DUTY(perc) ((perc) * 255 / 100) - -// These fan curves have been adjusted from Mate Kukri's original values (for his i3-12100), and work well with my i7-12700 -static const struct nct_fan NCT_FANS[] = { +/* Fan profiles tuned for an i7-12700. */ +static const struct nuvoton_fan_curve fans[] = { { - .name = "SYSFAN", - .bank = BANK_SYSFAN, - .source = FAN_SOURCE_PECI0, - .temp = {40, 60, 75, 90}, - .duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)}, - .crit_temp = 100, - .crit_duty_en = 1, - .crit_duty = 255, - .crit_temp_tolerance = 2, + .name = "SYSFAN", + .bank = BANK_SYSFAN, + .source = NUVOTON_FAN_SOURCE_PECI0, + .temp = { 40, 60, 75, 90 }, + .duty = { + NUVOTON_PERCENT_TO_DUTY(20), + NUVOTON_PERCENT_TO_DUTY(40), + NUVOTON_PERCENT_TO_DUTY(70), + NUVOTON_PERCENT_TO_DUTY(100), + }, + .crit_temp = 100, + .crit_duty_en = 1, + .crit_duty = 255, + .crit_temp_tolerance = 2, }, { - .name = "CPUFAN", - .bank = BANK_CPUFAN, - .source = FAN_SOURCE_PECI0, - .temp = {40, 60, 75, 90}, - .duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)}, - .crit_temp = 100, - .crit_duty_en = 1, - .crit_duty = 255, - .crit_temp_tolerance = 2, + .name = "CPUFAN", + .bank = BANK_CPUFAN, + .source = NUVOTON_FAN_SOURCE_PECI0, + .temp = { 40, 60, 75, 90 }, + .duty = { + NUVOTON_PERCENT_TO_DUTY(20), + NUVOTON_PERCENT_TO_DUTY(40), + NUVOTON_PERCENT_TO_DUTY(70), + NUVOTON_PERCENT_TO_DUTY(100), + }, + .crit_temp = 100, + .crit_duty_en = 1, + .crit_duty = 255, + .crit_temp_tolerance = 2, }, }; @@ -187,54 +152,14 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; -static void nct6798d_hwm_init(void *arg) +static void hwm_init(void *arg) { - printk(BIOS_DEBUG, "NCT6798D HWM configuration\n"); - - // Setup PECI - // Devicetree must set pin 121 to PECI mode first - nuvoton_hwm_select_bank(HWM_IOBASE, 7); - pnp_write_hwm5_index(HWM_IOBASE, 1, 0x85); - pnp_write_hwm5_index(HWM_IOBASE, 2, 0x02); - pnp_write_hwm5_index(HWM_IOBASE, 3, 0x10); - pnp_write_hwm5_index(HWM_IOBASE, 4, 0x00); - pnp_write_hwm5_index(HWM_IOBASE, 9, 0x64); - - // Enable PECI temp reading - nuvoton_hwm_select_bank(HWM_IOBASE, 0); - pnp_write_hwm5_index(HWM_IOBASE, 0xae, 1); - - // Program PECI Agent 0 Calibration - nuvoton_hwm_select_bank(HWM_IOBASE, 4); - pnp_write_hwm5_index(HWM_IOBASE, 0xf8, 0x50); - pnp_write_hwm5_index(HWM_IOBASE, 0xfa, 0x51); - + /* Devicetree must set superio pin 121 to PECI mode first. */ + nuvoton_hwm_enable_peci(HWM_IOBASE, CPU_TJMAX); + nuvoton_hwm_enable_peci_calibration(HWM_IOBASE); - // Program fan control profiles - for (const struct nct_fan *fan = NCT_FANS; fan < NCT_FANS + ARRAY_SIZE(NCT_FANS); ++fan) { - printk(BIOS_DEBUG, "Configuring NCT6798D fan %s\n", fan->name); - - nuvoton_hwm_select_bank(HWM_IOBASE, fan->bank); - - pnp_write_hwm5_index(HWM_IOBASE, FAN_SOURCE, fan->source); - - for (size_t i = 0; i < 4; ++i) - pnp_write_hwm5_index(HWM_IOBASE, FAN_TEMP(i), fan->temp[i]); - for (size_t i = 0; i < 4; ++i) - pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY(i), fan->duty[i]); - - pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP, fan->crit_temp); - pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY_EN, fan->crit_duty_en); - pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY, fan->crit_duty); - pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP_TOLERANCE, fan->crit_temp_tolerance); - - pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_UP_TIME, fan->step_up_time); - pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_DOWN_TIME, fan->step_down_time); - pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY_PER_STEP, fan->duty_per_step_up << 4 | fan->duty_per_step_down); - - // There are other modes supported by hardware, but always use SmartFan IV mode here - pnp_write_hwm5_index(HWM_IOBASE, FAN_MODE_TEMP_TOLERANCE, (FAN_MODE_SFIV << 4) | fan->temp_tolerance); - } + for (size_t i = 0; i < ARRAY_SIZE(fans); i++) + nuvoton_hwm_configure_fan(HWM_IOBASE, &fans[i]); } -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, nct6798d_hwm_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, hwm_init, NULL); diff --git a/src/mainboard/asus/h610m-k/Kconfig b/src/mainboard/asus/h610m-k/Kconfig new file mode 100644 index 00000000000..085fb4a0535 --- /dev/null +++ b/src/mainboard/asus/h610m-k/Kconfig @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_H610M_K + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_COMMON_HWM + select SUPERIO_NUVOTON_NCT6791D + select USE_LEGACY_8254_TIMER + +if BOARD_ASUS_H610M_K + +config MAINBOARD_DIR + default "asus/h610m-k" + +config MAINBOARD_PART_NUMBER + default "ASUS PRIME H610M-K D4" + +config UART_FOR_CONSOLE + int + default 0 + +config USE_PM_ACPI_TIMER + bool + default n + +config CBFS_SIZE + hex + default 0xb00000 + +endif diff --git a/src/mainboard/asus/h610m-k/Kconfig.name b/src/mainboard/asus/h610m-k/Kconfig.name new file mode 100644 index 00000000000..908f379dbab --- /dev/null +++ b/src/mainboard/asus/h610m-k/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_H610M_K + bool "PRIME H610M-K D4" diff --git a/src/mainboard/asus/h610m-k/Makefile.mk b/src/mainboard/asus/h610m-k/Makefile.mk new file mode 100644 index 00000000000..bf162bb01ed --- /dev/null +++ b/src/mainboard/asus/h610m-k/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c diff --git a/src/mainboard/asus/h610m-k/board_info.txt b/src/mainboard/asus/h610m-k/board_info.txt new file mode 100644 index 00000000000..65d312b4c98 --- /dev/null +++ b/src/mainboard/asus/h610m-k/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/motherboards-components/motherboards/prime/prime-h610m-k-d4/ +ROM IC: W25Q128JSQ +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes +Release year: 2021 diff --git a/src/mainboard/asus/h610m-k/bootblock.c b/src/mainboard/asus/h610m-k/bootblock.c new file mode 100644 index 00000000000..9a4ea80ff2a --- /dev/null +++ b/src/mainboard/asus/h610m-k/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 0x02) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/h610m-k/data.vbt b/src/mainboard/asus/h610m-k/data.vbt new file mode 100644 index 00000000000..ed9d9c63473 Binary files /dev/null and b/src/mainboard/asus/h610m-k/data.vbt differ diff --git a/src/mainboard/asus/h610m-k/devicetree.cb b/src/mainboard/asus/h610m-k/devicetree.cb new file mode 100644 index 00000000000..7f401b95bfe --- /dev/null +++ b/src/mainboard/asus/h610m-k/devicetree.cb @@ -0,0 +1,116 @@ +chip soc/intel/alderlake + register "eist_enable" = "true" + + device domain 0 on + # PCIe x16 slot + device ref pcie5_0 on + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref igpu on end + + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // USB3 front header + [1] = USB2_PORT_MID(OC0), // USB3 front header + [2] = USB2_PORT_MID(OC1), // USB3 back + [3] = USB2_PORT_MID(OC1), // USB3 back + [4] = USB2_PORT_MID(OC2), // USB2 back + [5] = USB2_PORT_MID(OC2), // USB2 back + [6] = USB2_PORT_MID(OC3), // USB2 back + [7] = USB2_PORT_MID(OC3), // USB2 back + [8] = USB2_PORT_MID(OC4), // USB2 front header + [13] = USB2_PORT_MID(OC4), // USB2 front header + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // USB3 front header + [1] = USB3_PORT_DEFAULT(OC0), // USB3 front header + [2] = USB3_PORT_DEFAULT(OC1), // USB3 back + [3] = USB3_PORT_DEFAULT(OC1), // USB3 back + }" + end + + device ref sata on + register "sata_ports_enable" = "{ + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end + + # PCIe x1 slot + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + # LAN controller + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, + }" + + device pci 00.0 on end + end + + # M.2 slot + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 11, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pch_espi on + # HWM I/O decode range + register "gen1_dec" = "0x007c0281" + + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel port (this line needed for super i/o init to work) + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + + # Pin 121 is PECI + irq 0x2c = 0 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 + end + device pnp 2e.b on # HWM + io 0x60 = 0x0290 + io 0x62 = 0x0b00 + io 0x64 = 0x0a00 + irq 0xf0 = 0xfe + end + end + end + + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "false" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + + device ref smbus on end + end +end diff --git a/src/mainboard/asus/h610m-k/dsdt.asl b/src/mainboard/asus/h610m-k/dsdt.asl new file mode 100644 index 00000000000..e612ec09dea --- /dev/null +++ b/src/mainboard/asus/h610m-k/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/asus/h610m-k/gpio.h b/src/mainboard/asus/h610m-k/gpio.h new file mode 100644 index 00000000000..77a9880c805 --- /dev/null +++ b/src/mainboard/asus/h610m-k/gpio.h @@ -0,0 +1,445 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDSP_HPD1 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDSP_HPD2 */ + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDSP_HPD3 */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* DDSP_HPD4 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* USB_OC4# */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* USB_OC5# */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* USB_OC6# */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* USB_OC7# */ + PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_R12, NONE, PLTRST, NF2), /* DDP3_CTRLCLK */ + PAD_CFG_NF(GPP_R13, NONE, PLTRST, NF2), /* DDP3_CTRLDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_R16, NONE, PLTRST, NF1), /* DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_R17, NONE, PLTRST, NF1), /* DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_R18, NONE, PLTRST, NF1), /* DDP2_CTRLCLK */ + PAD_CFG_NF(GPP_R19, NONE, PLTRST, NF1), /* DDP2_CTRLDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1), /* CPU_C10_GATE# */ + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_J7, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group vGPIO ------- */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_0, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(VGPIO_4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_NF(VGPIO_6, NONE, DEEP, NF1), /* VGPIO_6 */ + PAD_CFG_NF(VGPIO_7, NONE, DEEP, NF1), /* VGPIO_7 */ + PAD_CFG_NF(VGPIO_8, NONE, DEEP, NF1), /* VGPIO_8 */ + PAD_CFG_NF(VGPIO_9, NONE, DEEP, NF1), /* VGPIO_9 */ + PAD_CFG_NF(VGPIO_10, NONE, DEEP, NF1), /* VGPIO_10 */ + PAD_CFG_NF(VGPIO_11, NONE, DEEP, NF1), /* VGPIO_11 */ + PAD_CFG_NF(VGPIO_12, NONE, DEEP, NF1), /* VGPIO_12 */ + PAD_CFG_NF(VGPIO_13, NONE, DEEP, NF1), /* VGPIO_13 */ + PAD_CFG_NF(VGPIO_18, NONE, DEEP, NF1), /* VGPIO_18 */ + PAD_CFG_NF(VGPIO_19, NONE, DEEP, NF1), /* VGPIO_19 */ + PAD_CFG_NF(VGPIO_20, NONE, DEEP, NF1), /* VGPIO_20 */ + PAD_CFG_NF(VGPIO_21, NONE, DEEP, NF1), /* VGPIO_21 */ + PAD_CFG_NF(VGPIO_22, NONE, DEEP, NF1), /* VGPIO_22 */ + PAD_CFG_NF(VGPIO_23, NONE, DEEP, NF1), /* VGPIO_23 */ + PAD_CFG_NF(VGPIO_24, NONE, DEEP, NF1), /* VGPIO_24 */ + PAD_CFG_NF(VGPIO_25, NONE, DEEP, NF1), /* VGPIO_25 */ + PAD_CFG_NF(VGPIO_30, NONE, DEEP, NF1), /* VGPIO_30 */ + PAD_CFG_NF(VGPIO_31, NONE, DEEP, NF1), /* VGPIO_31 */ + PAD_CFG_NF(VGPIO_32, NONE, DEEP, NF1), /* VGPIO_32 */ + PAD_CFG_NF(VGPIO_33, NONE, DEEP, NF1), /* VGPIO_33 */ + PAD_CFG_NF(VGPIO_34, NONE, DEEP, NF1), /* VGPIO_34 */ + PAD_CFG_NF(VGPIO_35, NONE, DEEP, NF1), /* VGPIO_35 */ + PAD_CFG_NF(VGPIO_36, NONE, DEEP, NF1), /* VGPIO_36 */ + PAD_CFG_NF(VGPIO_37, NONE, DEEP, NF1), /* VGPIO_37 */ + + /* ------- GPIO Group vGPIO_0 ------- */ + PAD_CFG_NF(VGPIO_USB_0, NONE, DEEP, NF1), /* VGPIO_USB_0 */ + PAD_CFG_NF(VGPIO_USB_1, NONE, DEEP, NF1), /* VGPIO_USB_1 */ + PAD_CFG_NF(VGPIO_USB_2, NONE, DEEP, NF1), /* VGPIO_USB_2 */ + PAD_CFG_NF(VGPIO_USB_3, NONE, DEEP, NF1), /* VGPIO_USB_3 */ + PAD_CFG_NF(VGPIO_USB_8, NONE, DEEP, NF1), /* VGPIO_USB_8 */ + PAD_CFG_NF(VGPIO_USB_9, NONE, DEEP, NF1), /* VGPIO_USB_9 */ + PAD_CFG_NF(VGPIO_USB_10, NONE, DEEP, NF1), /* VGPIO_USB_10 */ + PAD_CFG_NF(VGPIO_USB_11, NONE, DEEP, NF1), /* VGPIO_USB_11 */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), /* SPKR */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_B18, UP_20K, PLTRST, NF1), /* PMCALERT# */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_G1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_G3, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_SCI(GPP_G7, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* SRCCLKREQ11# */ + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PWROK, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PWROK, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, PWROK, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, PWROK, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPD10, 0, PWROK), /* GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD12, NONE, PWROK, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), /* I2C2_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), /* I2C2_SCL */ + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* SML0ALERT# */ + PAD_CFG_GPI_TRIG_OWN(GPP_C6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group vGPIO_3 ------- */ + PAD_CFG_NF(VGPIO_PCIE_0, NONE, PLTRST, NF1), /* VGPIO_PCIE_0 */ + PAD_CFG_NF(VGPIO_PCIE_1, NONE, PLTRST, NF1), /* VGPIO_PCIE_1 */ + PAD_CFG_NF(VGPIO_PCIE_2, NONE, PLTRST, NF1), /* VGPIO_PCIE_2 */ + PAD_CFG_NF(VGPIO_PCIE_3, NONE, PLTRST, NF1), /* VGPIO_PCIE_3 */ + PAD_CFG_NF(VGPIO_PCIE_4, NONE, PLTRST, NF1), /* VGPIO_PCIE_4 */ + PAD_CFG_NF(VGPIO_PCIE_5, NONE, PLTRST, NF1), /* VGPIO_PCIE_5 */ + PAD_CFG_NF(VGPIO_PCIE_6, NONE, PLTRST, NF1), /* VGPIO_PCIE_6 */ + PAD_CFG_NF(VGPIO_PCIE_7, NONE, PLTRST, NF1), /* VGPIO_PCIE_7 */ + PAD_CFG_NF(VGPIO_PCIE_8, NONE, PLTRST, NF1), /* VGPIO_PCIE_8 */ + PAD_CFG_NF(VGPIO_PCIE_9, NONE, PLTRST, NF1), /* VGPIO_PCIE_9 */ + PAD_CFG_NF(VGPIO_PCIE_10, NONE, PLTRST, NF1), /* VGPIO_PCIE_10 */ + PAD_CFG_NF(VGPIO_PCIE_11, NONE, PLTRST, NF1), /* VGPIO_PCIE_11 */ + PAD_CFG_NF(VGPIO_PCIE_12, NONE, PLTRST, NF1), /* VGPIO_PCIE_12 */ + PAD_CFG_NF(VGPIO_PCIE_13, NONE, PLTRST, NF1), /* VGPIO_PCIE_13 */ + PAD_CFG_NF(VGPIO_PCIE_14, NONE, PLTRST, NF1), /* VGPIO_PCIE_14 */ + PAD_CFG_NF(VGPIO_PCIE_15, NONE, PLTRST, NF1), /* VGPIO_PCIE_15 */ + PAD_CFG_NF(VGPIO_PCIE_16, NONE, PLTRST, NF1), /* VGPIO_PCIE_16 */ + PAD_CFG_NF(VGPIO_PCIE_17, NONE, PLTRST, NF1), /* VGPIO_PCIE_17 */ + PAD_CFG_NF(VGPIO_PCIE_18, NONE, PLTRST, NF1), /* VGPIO_PCIE_18 */ + PAD_CFG_NF(VGPIO_PCIE_19, NONE, PLTRST, NF1), /* VGPIO_PCIE_19 */ + PAD_CFG_NF(VGPIO_PCIE_20, NONE, PLTRST, NF1), /* VGPIO_PCIE_20 */ + PAD_CFG_NF(VGPIO_PCIE_21, NONE, PLTRST, NF1), /* VGPIO_PCIE_21 */ + PAD_CFG_NF(VGPIO_PCIE_22, NONE, PLTRST, NF1), /* VGPIO_PCIE_22 */ + PAD_CFG_NF(VGPIO_PCIE_23, NONE, PLTRST, NF1), /* VGPIO_PCIE_23 */ + PAD_CFG_NF(VGPIO_PCIE_24, NONE, PLTRST, NF1), /* VGPIO_PCIE_24 */ + PAD_CFG_NF(VGPIO_PCIE_25, NONE, PLTRST, NF1), /* VGPIO_PCIE_25 */ + PAD_CFG_NF(VGPIO_PCIE_26, NONE, PLTRST, NF1), /* VGPIO_PCIE_26 */ + PAD_CFG_NF(VGPIO_PCIE_27, NONE, PLTRST, NF1), /* VGPIO_PCIE_27 */ + PAD_CFG_NF(VGPIO_PCIE_28, NONE, PLTRST, NF1), /* VGPIO_PCIE_28 */ + PAD_CFG_NF(VGPIO_PCIE_29, NONE, PLTRST, NF1), /* VGPIO_PCIE_29 */ + PAD_CFG_NF(VGPIO_PCIE_30, NONE, PLTRST, NF1), /* VGPIO_PCIE_30 */ + PAD_CFG_NF(VGPIO_PCIE_31, NONE, PLTRST, NF1), /* VGPIO_PCIE_31 */ + PAD_CFG_NF(VGPIO_PCIE_32, NONE, PLTRST, NF1), /* VGPIO_PCIE_32 */ + PAD_CFG_NF(VGPIO_PCIE_33, NONE, PLTRST, NF1), /* VGPIO_PCIE_33 */ + PAD_CFG_NF(VGPIO_PCIE_34, NONE, PLTRST, NF1), /* VGPIO_PCIE_34 */ + PAD_CFG_NF(VGPIO_PCIE_35, NONE, PLTRST, NF1), /* VGPIO_PCIE_35 */ + PAD_CFG_NF(VGPIO_PCIE_36, NONE, PLTRST, NF1), /* VGPIO_PCIE_36 */ + PAD_CFG_NF(VGPIO_PCIE_37, NONE, PLTRST, NF1), /* VGPIO_PCIE_37 */ + PAD_CFG_NF(VGPIO_PCIE_38, NONE, PLTRST, NF1), /* VGPIO_PCIE_38 */ + PAD_CFG_NF(VGPIO_PCIE_39, NONE, PLTRST, NF1), /* VGPIO_PCIE_39 */ + PAD_CFG_NF(VGPIO_PCIE_40, NONE, PLTRST, NF1), /* VGPIO_PCIE_40 */ + PAD_CFG_NF(VGPIO_PCIE_41, NONE, PLTRST, NF1), /* VGPIO_PCIE_41 */ + PAD_CFG_NF(VGPIO_PCIE_42, NONE, PLTRST, NF1), /* VGPIO_PCIE_42 */ + PAD_CFG_NF(VGPIO_PCIE_43, NONE, PLTRST, NF1), /* VGPIO_PCIE_43 */ + PAD_CFG_NF(VGPIO_PCIE_44, NONE, PLTRST, NF1), /* VGPIO_PCIE_44 */ + PAD_CFG_NF(VGPIO_PCIE_45, NONE, PLTRST, NF1), /* VGPIO_PCIE_45 */ + PAD_CFG_NF(VGPIO_PCIE_46, NONE, PLTRST, NF1), /* VGPIO_PCIE_46 */ + PAD_CFG_NF(VGPIO_PCIE_47, NONE, PLTRST, NF1), /* VGPIO_PCIE_47 */ + PAD_CFG_NF(VGPIO_PCIE_48, NONE, PLTRST, NF1), /* VGPIO_PCIE_48 */ + PAD_CFG_NF(VGPIO_PCIE_49, NONE, PLTRST, NF1), /* VGPIO_PCIE_49 */ + PAD_CFG_NF(VGPIO_PCIE_50, NONE, PLTRST, NF1), /* VGPIO_PCIE_50 */ + PAD_CFG_NF(VGPIO_PCIE_51, NONE, PLTRST, NF1), /* VGPIO_PCIE_51 */ + PAD_CFG_NF(VGPIO_PCIE_52, NONE, PLTRST, NF1), /* VGPIO_PCIE_52 */ + PAD_CFG_NF(VGPIO_PCIE_53, NONE, PLTRST, NF1), /* VGPIO_PCIE_53 */ + PAD_CFG_NF(VGPIO_PCIE_54, NONE, PLTRST, NF1), /* VGPIO_PCIE_54 */ + PAD_CFG_NF(VGPIO_PCIE_55, NONE, PLTRST, NF1), /* VGPIO_PCIE_55 */ + PAD_CFG_NF(VGPIO_PCIE_56, NONE, PLTRST, NF1), /* VGPIO_PCIE_56 */ + PAD_CFG_NF(VGPIO_PCIE_57, NONE, PLTRST, NF1), /* VGPIO_PCIE_57 */ + PAD_CFG_NF(VGPIO_PCIE_58, NONE, PLTRST, NF1), /* VGPIO_PCIE_58 */ + PAD_CFG_NF(VGPIO_PCIE_59, NONE, PLTRST, NF1), /* VGPIO_PCIE_59 */ + PAD_CFG_NF(VGPIO_PCIE_60, NONE, PLTRST, NF1), /* VGPIO_PCIE_60 */ + PAD_CFG_NF(VGPIO_PCIE_61, NONE, PLTRST, NF1), /* VGPIO_PCIE_61 */ + PAD_CFG_NF(VGPIO_PCIE_62, NONE, PLTRST, NF1), /* VGPIO_PCIE_62 */ + PAD_CFG_NF(VGPIO_PCIE_63, NONE, PLTRST, NF1), /* VGPIO_PCIE_63 */ + PAD_CFG_NF(VGPIO_PCIE_64, NONE, PLTRST, NF1), /* VGPIO_PCIE_64 */ + PAD_CFG_NF(VGPIO_PCIE_65, NONE, PLTRST, NF1), /* VGPIO_PCIE_65 */ + PAD_CFG_NF(VGPIO_PCIE_66, NONE, PLTRST, NF1), /* VGPIO_PCIE_66 */ + PAD_CFG_NF(VGPIO_PCIE_67, NONE, PLTRST, NF1), /* VGPIO_PCIE_67 */ + PAD_CFG_NF(VGPIO_PCIE_68, NONE, PLTRST, NF1), /* VGPIO_PCIE_68 */ + PAD_CFG_NF(VGPIO_PCIE_69, NONE, PLTRST, NF1), /* VGPIO_PCIE_69 */ + PAD_CFG_NF(VGPIO_PCIE_70, NONE, PLTRST, NF1), /* VGPIO_PCIE_70 */ + PAD_CFG_NF(VGPIO_PCIE_71, NONE, PLTRST, NF1), /* VGPIO_PCIE_71 */ + PAD_CFG_NF(VGPIO_PCIE_72, NONE, PLTRST, NF1), /* VGPIO_PCIE_72 */ + PAD_CFG_NF(VGPIO_PCIE_73, NONE, PLTRST, NF1), /* VGPIO_PCIE_73 */ + PAD_CFG_NF(VGPIO_PCIE_74, NONE, PLTRST, NF1), /* VGPIO_PCIE_74 */ + PAD_CFG_NF(VGPIO_PCIE_75, NONE, PLTRST, NF1), /* VGPIO_PCIE_75 */ + PAD_CFG_NF(VGPIO_PCIE_76, NONE, PLTRST, NF1), /* VGPIO_PCIE_76 */ + PAD_CFG_NF(VGPIO_PCIE_77, NONE, PLTRST, NF1), /* VGPIO_PCIE_77 */ + PAD_CFG_NF(VGPIO_PCIE_78, NONE, PLTRST, NF1), /* VGPIO_PCIE_78 */ + PAD_CFG_NF(VGPIO_PCIE_79, NONE, PLTRST, NF1), /* VGPIO_PCIE_79 */ + PAD_CFG_NF(VGPIO_PCIE_80, NONE, DEEP, NF1), /* VGPIO_PCIE_80 */ + PAD_CFG_NF(VGPIO_PCIE_81, NONE, DEEP, NF1), /* VGPIO_PCIE_81 */ + PAD_CFG_NF(VGPIO_PCIE_82, NONE, DEEP, NF1), /* VGPIO_PCIE_82 */ + PAD_CFG_NF(VGPIO_PCIE_83, NONE, DEEP, NF1), /* VGPIO_PCIE_83 */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_E3, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* SATA_DEVSLP2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* SATALED# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_OC3# */ + PAD_CFG_GPI_APIC(GPP_E13, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPI_APIC(GPP_K0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2), /* n/a */ + PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2), /* n/a */ + PAD_CFG_GPO(GPP_K8, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2), /* n/a */ + PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF2), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3), /* MODEM_CLKREQ */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* SML1DATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Group CPU ------- */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/asus/h610m-k/hda_verb.c b/src/mainboard/asus/h610m-k/hda_verb.c new file mode 100644 index 00000000000..13819bbb779 --- /dev/null +++ b/src/mainboard/asus/h610m-k/hda_verb.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc897_verbs[] = { + AZALIA_SUBVENDOR(0, 0x104387fb), + + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPDIF_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x12, 0x4037c000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 3, 15 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4044c601), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), +}; + +static const u32 intel_display_audio_verbs[] = { + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x04, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x08, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0c, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0d, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0f, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC897", + .vendor_id = 0x10ec0897, + .subsystem_id = 0x104387fb, + .address = 0, + .verbs = realtek_alc897_verbs, + .verb_count = ARRAY_SIZE(realtek_alc897_verbs), + }, + { + .name = "Intel Display Audio (HDMI/DP)", + .vendor_id = 0x80862815, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_display_audio_verbs, + .verb_count = ARRAY_SIZE(intel_display_audio_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h610m-k/ramstage.c b/src/mainboard/asus/h610m-k/ramstage.c new file mode 100644 index 00000000000..43e06641a9b --- /dev/null +++ b/src/mainboard/asus/h610m-k/ramstage.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ +} + +/* HWM base address, set in devicetree.cb. */ +#define HWM_IOBASE 0x290 + +/* Alder Lake desktop Tjmax in degrees Celsius. */ +#define CPU_TJMAX 100 + +/* Per-fan register banks. Only SYSFAN and CPUFAN are wired up. */ +#define BANK_SYSFAN 1 +#define BANK_CPUFAN 2 + +/* Fan profiles. The curves below were picked empirically on an i3-12100. */ +static const struct nuvoton_fan_curve fans[] = { + { + .name = "SYSFAN", + .bank = BANK_SYSFAN, + .source = NUVOTON_FAN_SOURCE_PECI0_CAL, + .temp = { 40, 60, 80, 100 }, + .duty = { + NUVOTON_PERCENT_TO_DUTY(20), + NUVOTON_PERCENT_TO_DUTY(40), + NUVOTON_PERCENT_TO_DUTY(60), + NUVOTON_PERCENT_TO_DUTY(80), + }, + .crit_temp = 125, + .crit_duty_en = 1, + .crit_duty = NUVOTON_PERCENT_TO_DUTY(100), + .crit_temp_tolerance = 2, + }, + { + .name = "CPUFAN", + .bank = BANK_CPUFAN, + .source = NUVOTON_FAN_SOURCE_PECI0_CAL, + .temp = { 40, 60, 80, 100 }, + .duty = { + NUVOTON_PERCENT_TO_DUTY(20), + NUVOTON_PERCENT_TO_DUTY(40), + NUVOTON_PERCENT_TO_DUTY(60), + NUVOTON_PERCENT_TO_DUTY(80), + }, + .crit_temp = 125, + .crit_duty_en = 1, + .crit_duty = NUVOTON_PERCENT_TO_DUTY(100), + .crit_temp_tolerance = 2, + }, +}; + +static void hwm_init(void *arg) +{ + /* + * The board wires a real thermistor to CPUTIN (not a diode), which + * PECI calibration uses as its reference. Chip default is diode + + * current mode; reading that without configuring CPUTIN correctly + * leaves the calibrated source garbage. + */ + nuvoton_hwm_set_sensor_type(HWM_IOBASE, NUVOTON_TEMP_SRC_CPUTIN, + NUVOTON_TEMP_SENSOR_THERMISTOR); + + /* Devicetree must set superio pin 121 to PECI mode first. */ + nuvoton_hwm_enable_peci(HWM_IOBASE, CPU_TJMAX); + nuvoton_hwm_enable_peci_calibration(HWM_IOBASE); + + for (size_t i = 0; i < ARRAY_SIZE(fans); i++) + nuvoton_hwm_configure_fan(HWM_IOBASE, &fans[i]); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, hwm_init, NULL); diff --git a/src/mainboard/asus/h610m-k/romstage.c b/src/mainboard/asus/h610m-k/romstage.c new file mode 100644 index 00000000000..2b946c6bde7 --- /dev/null +++ b/src/mainboard/asus/h610m-k/romstage.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "gpio.h" + +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + .UserBd = BOARD_TYPE_DESKTOP_1DPC, + .ddr_config = { + .dq_pins_interleaved = true, + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memcfg_init(memupd, &mem_config, &dimm_module_spd_info, false); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/h81m_k/Kconfig b/src/mainboard/asus/h81m_k/Kconfig new file mode 100644 index 00000000000..cb562c0735c --- /dev/null +++ b/src/mainboard/asus/h81m_k/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_H81M_K + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + +config MAINBOARD_DIR + default "asus/h81m_k" + +config MAINBOARD_PART_NUMBER + default "H81M-K" + +config CBFS_SIZE + default 0x600000 +endif diff --git a/src/mainboard/asus/h81m_k/Kconfig.name b/src/mainboard/asus/h81m_k/Kconfig.name new file mode 100644 index 00000000000..dbc11fcebc6 --- /dev/null +++ b/src/mainboard/asus/h81m_k/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_H81M_K + bool "H81M-K" diff --git a/src/mainboard/asus/h81m_k/Makefile.mk b/src/mainboard/asus/h81m_k/Makefile.mk new file mode 100644 index 00000000000..5daae272406 --- /dev/null +++ b/src/mainboard/asus/h81m_k/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h81m_k/acpi/ec.asl b/src/mainboard/asus/h81m_k/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/h81m_k/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/h81m_k/acpi/platform.asl b/src/mainboard/asus/h81m_k/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/h81m_k/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/h81m_k/acpi/superio.asl b/src/mainboard/asus/h81m_k/acpi/superio.asl new file mode 100644 index 00000000000..55b1db5b113 --- /dev/null +++ b/src/mainboard/asus/h81m_k/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/asus/h81m_k/board_info.txt b/src/mainboard/asus/h81m_k/board_info.txt new file mode 100644 index 00000000000..e423b0bcc92 --- /dev/null +++ b/src/mainboard/asus/h81m_k/board_info.txt @@ -0,0 +1,8 @@ +Category: desktop +Board URL: https://www.asus.com/motherboards-components/motherboards/business/h81mk +ROM package: DIP-8 +ROM protocol: SPI +ROM IC: GD25B64C +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/h81m_k/bootblock.c b/src/mainboard/asus/h81m_k/bootblock.c new file mode 100644 index 00000000000..582c1ee8a4c --- /dev/null +++ b/src/mainboard/asus/h81m_k/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/h81m_k/data.vbt b/src/mainboard/asus/h81m_k/data.vbt new file mode 100644 index 00000000000..c5b2e6a05af Binary files /dev/null and b/src/mainboard/asus/h81m_k/data.vbt differ diff --git a/src/mainboard/asus/h81m_k/devicetree.cb b/src/mainboard/asus/h81m_k/devicetree.cb new file mode 100644 index 00000000000..db2ad60f60a --- /dev/null +++ b/src/mainboard/asus/h81m_k/devicetree.cb @@ -0,0 +1,96 @@ +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIEX16 + device pci 02.0 on end # Internal graphics + device pci 03.0 on end # Mini-HD audio + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gpe0_en_1" = "0x46" + register "sata_port_map" = "0x33" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8576 + end + device pci 1c.0 on end # PCIEX1_1 + device pci 1c.1 on end # PCIEX1_2 + device pci 1c.2 on # PCIe Port #3 Realtek RTL8111G GbE NIC + device pci 00.0 on end + end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct5539d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x12 + irq 0xed = 0x01 + irq 0xf0 = 0x30 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/h81m_k/dsdt.asl b/src/mainboard/asus/h81m_k/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/h81m_k/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/h81m_k/gma-mainboard.ads b/src/mainboard/asus/h81m_k/gma-mainboard.ads new file mode 100644 index 00000000000..c9e43269241 --- /dev/null +++ b/src/mainboard/asus/h81m_k/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h81m_k/gpio.c b/src/mainboard/asus/h81m_k/gpio.c new file mode 100644 index 00000000000..063e8f38e59 --- /dev/null +++ b/src/mainboard/asus/h81m_k/gpio.c @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio27 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h81m_k/hda_verb.c b/src/mainboard/asus/h81m_k/hda_verb.c new file mode 100644 index 00000000000..7018c22ece0 --- /dev/null +++ b/src/mainboard/asus/h81m_k/hda_verb.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc887_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438444), + AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430140), + AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010), + AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x01011012), + AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, 0x01016011), + AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, 0x01012014), + AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19850), + AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c60), + AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181305f), + AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20), + AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005e601), + AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01456130), + AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)), +}; + +static const u32 intel_display_audio_verbs[] = { + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC887", + .vendor_id = 0x10ec0887, + .subsystem_id = 0x10438444, + .address = 0, + .verbs = realtek_alc887_verbs, + .verb_count = ARRAY_SIZE(realtek_alc887_verbs), + }, + { + .name = "Intel Display Audio (HDMI/DP)", + .vendor_id = 0x80862805, + .subsystem_id = 0x80860101, + .address = 3, + .verbs = intel_display_audio_verbs, + .verb_count = ARRAY_SIZE(intel_display_audio_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h81m_k/romstage.c b/src/mainboard/asus/h81m_k/romstage.c new file mode 100644 index 00000000000..45d8d6e731d --- /dev/null +++ b/src/mainboard/asus/h81m_k/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vi_extreme/Kconfig b/src/mainboard/asus/maximus_vi_extreme/Kconfig new file mode 100644 index 00000000000..2c20386a166 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_EXTREME + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASM1061 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/maximus_vi_extreme" + +config MAINBOARD_PART_NUMBER + default "Maximus VI EXTREME" + +config USBDEBUG_HCD_INDEX + default 2 # Header: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vi_extreme/Kconfig.name b/src/mainboard/asus/maximus_vi_extreme/Kconfig.name new file mode 100644 index 00000000000..33da357f189 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_EXTREME + bool "Maximus VI EXTREME" diff --git a/src/mainboard/asus/maximus_vi_extreme/Makefile.mk b/src/mainboard/asus/maximus_vi_extreme/Makefile.mk new file mode 100644 index 00000000000..ab3a37006f3 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c diff --git a/src/mainboard/asus/maximus_vi_extreme/acpi/ec.asl b/src/mainboard/asus/maximus_vi_extreme/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_extreme/acpi/platform.asl b/src/mainboard/asus/maximus_vi_extreme/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_extreme/acpi/superio.asl b/src/mainboard/asus/maximus_vi_extreme/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_extreme/board_info.txt b/src/mainboard/asus/maximus_vi_extreme/board_info.txt new file mode 100644 index 00000000000..fc6f139aeeb --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/MAXIMUS_VI_EXTREME/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (x2) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_extreme/bootblock.c b/src/mainboard/asus/maximus_vi_extreme/bootblock.c new file mode 100644 index 00000000000..f9e90cf9627 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x0a); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x36); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x26, 0x00); + pnp_write_config(GLOBAL_DEV, 0x28, 0x10); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/asus/maximus_vi_extreme/data.vbt b/src/mainboard/asus/maximus_vi_extreme/data.vbt new file mode 100644 index 00000000000..b7f15bca636 Binary files /dev/null and b/src/mainboard/asus/maximus_vi_extreme/data.vbt differ diff --git a/src/mainboard/asus/maximus_vi_extreme/devicetree.cb b/src/mainboard/asus/maximus_vi_extreme/devicetree.cb new file mode 100644 index 00000000000..6b04249a30f --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/devicetree.cb @@ -0,0 +1,131 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG: PCIE_X16/X8_1 + device pci 01.1 on end # PEG: PCIE_X16_A2/PCIE_X8_B2/PCIE_X8_3/PCIE_X8_4 + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8580 + end + device pci 1c.0 on end # RP #1: M.2 (muxed with SATA4) + device pci 1c.1 on end # RP #2: WiFi + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: PEX8605 PCIe switch + device pci 1c.4 on end # RP #5: PCIEX4_1 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + irq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xfe + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x10 + irq 0xe7 = 0x70 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0xcf + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xfa + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x81 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf2 = 0x5d + irq 0xfc = 0x80 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0x01 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + irq 0xe0 = 0xff + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_extreme/dsdt.asl b/src/mainboard/asus/maximus_vi_extreme/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vi_extreme/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_extreme/gma-mainboard.ads new file mode 100644 index 00000000000..464aef82c5a --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, -- DP++ + HDMI3, -- HDMI, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_extreme/gpio.c b/src/mainboard/asus/maximus_vi_extreme/gpio.c new file mode 100644 index 00000000000..45aeba952bf --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/gpio.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_extreme/hda_verb.c b/src/mainboard/asus/maximus_vi_extreme/hda_verb.c new file mode 100644 index 00000000000..85959aec617 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/hda_verb.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438580), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREY, + AZALIA_JACK_PRESENCE_DETECT, + 1, 4 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 6, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x10438580, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_extreme/romstage.c b/src/mainboard/asus/maximus_vi_extreme/romstage.c new file mode 100644 index 00000000000..22e79b8cb5c --- /dev/null +++ b/src/mainboard/asus/maximus_vi_extreme/romstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vi_formula/Kconfig b/src/mainboard/asus/maximus_vi_formula/Kconfig new file mode 100644 index 00000000000..e57c48605ad --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/Kconfig @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_FORMULA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASM1061 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/maximus_vi_formula" + +config MAINBOARD_PART_NUMBER + default "Maximus VI FORMULA" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB7~10: Top + # Header: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vi_formula/Kconfig.name b/src/mainboard/asus/maximus_vi_formula/Kconfig.name new file mode 100644 index 00000000000..948d5384ae0 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_FORMULA + bool "Maximus VI FORMULA" diff --git a/src/mainboard/asus/maximus_vi_formula/Makefile.mk b/src/mainboard/asus/maximus_vi_formula/Makefile.mk new file mode 100644 index 00000000000..ab3a37006f3 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c diff --git a/src/mainboard/asus/maximus_vi_formula/acpi/ec.asl b/src/mainboard/asus/maximus_vi_formula/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_formula/acpi/platform.asl b/src/mainboard/asus/maximus_vi_formula/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_formula/acpi/superio.asl b/src/mainboard/asus/maximus_vi_formula/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_formula/board_info.txt b/src/mainboard/asus/maximus_vi_formula/board_info.txt new file mode 100644 index 00000000000..f5a9f1ffd05 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/MAXIMUS_VI_FORMULA/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_formula/bootblock.c b/src/mainboard/asus/maximus_vi_formula/bootblock.c new file mode 100644 index 00000000000..4933e38ef00 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x0a); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x76); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x26, 0x00); + pnp_write_config(GLOBAL_DEV, 0x28, 0x10); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/asus/maximus_vi_formula/data.vbt b/src/mainboard/asus/maximus_vi_formula/data.vbt new file mode 100644 index 00000000000..28ac159e546 Binary files /dev/null and b/src/mainboard/asus/maximus_vi_formula/data.vbt differ diff --git a/src/mainboard/asus/maximus_vi_formula/devicetree.cb b/src/mainboard/asus/maximus_vi_formula/devicetree.cb new file mode 100644 index 00000000000..d257aa993d3 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/devicetree.cb @@ -0,0 +1,136 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG: PCIE_X16/X8_1 + device pci 01.1 on end # PEG: PCIE_X8/X4_2 + device pci 01.2 on end # PEG: PCIE_X4_3 + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x857e + end + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2: WiFi + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4: PCIEX1_1 + device pci 1c.4 on end # RP #5: PCIEX1_2 + device pci 1c.5 on end # RP #6: PCIEX1_3 + device pci 1c.6 on end # RP #7: ASRock ASM1061/ASM1062 SATA Controller + device pci 1c.7 on end # RP #8: ASRock ASM1061/ASM1062 SATA Controller + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + irq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xfe + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x10 + irq 0xe7 = 0x70 + end + device pnp 2e.209 on # GPIO4 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xfa + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf2 = 0x5d + irq 0xfc = 0x80 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0x01 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_formula/dsdt.asl b/src/mainboard/asus/maximus_vi_formula/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vi_formula/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_formula/gma-mainboard.ads new file mode 100644 index 00000000000..7275f849d3b --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI2, + HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_formula/gpio.c b/src/mainboard/asus/maximus_vi_formula/gpio.c new file mode 100644 index 00000000000..7f305deabd7 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/gpio.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_formula/hda_verb.c b/src/mainboard/asus/maximus_vi_formula/hda_verb.c new file mode 100644 index 00000000000..8eabb46a65c --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/hda_verb.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x1043857e), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREY, + AZALIA_JACK_PRESENCE_DETECT, + 1, 4 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 6, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x1043857e, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_formula/romstage.c b/src/mainboard/asus/maximus_vi_formula/romstage.c new file mode 100644 index 00000000000..e26cb98c7e1 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_formula/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vi_hero/Kconfig b/src/mainboard/asus/maximus_vi_hero/Kconfig new file mode 100644 index 00000000000..e77f34a34e0 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Kconfig @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_HERO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASM1061 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/maximus_vi_hero" + +config MAINBOARD_PART_NUMBER + default "Maximus VI HERO" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB910 (Bottom) + # Header: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vi_hero/Kconfig.name b/src/mainboard/asus/maximus_vi_hero/Kconfig.name new file mode 100644 index 00000000000..c6cd0e64312 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_HERO + bool "Maximus VI HERO" diff --git a/src/mainboard/asus/maximus_vi_hero/Makefile.mk b/src/mainboard/asus/maximus_vi_hero/Makefile.mk new file mode 100644 index 00000000000..c3cf55d3979 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl b/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl b/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl b/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_hero/board_info.txt b/src/mainboard/asus/maximus_vi_hero/board_info.txt new file mode 100644 index 00000000000..2da82eafa8c --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_VI_HERO/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_hero/bootblock.c b/src/mainboard/asus/maximus_vi_hero/bootblock.c new file mode 100644 index 00000000000..904aab86b33 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/bootblock.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x13, 0xff); + pnp_write_config(GLOBAL_DEV, 0x14, 0xff); + pnp_write_config(GLOBAL_DEV, 0x1a, 0x0a); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x76); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x26, 0x00); + pnp_write_config(GLOBAL_DEV, 0x28, 0x10); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/asus/maximus_vi_hero/data.vbt b/src/mainboard/asus/maximus_vi_hero/data.vbt new file mode 100644 index 00000000000..748d5f5ca82 Binary files /dev/null and b/src/mainboard/asus/maximus_vi_hero/data.vbt differ diff --git a/src/mainboard/asus/maximus_vi_hero/devicetree.cb b/src/mainboard/asus/maximus_vi_hero/devicetree.cb new file mode 100644 index 00000000000..103b22e092f --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/devicetree.cb @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG: PCIE_X16/X8_1 + device pci 01.1 on end # PEG: PCIE_X8_2 + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x859d + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4: ASM1061 Serial ATA Controller + device pci 1c.4 on end # RP #5: PCIEX4_3 + device pci 1c.5 on end # RP #6: PCIEX1_1 + device pci 1c.6 on end # RP #7: PCIEX1_2 + device pci 1c.7 on end # RP #8: PCIEX1_3 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe1 = 0x88 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf1 = 0xa3 + irq 0xf3 = 0xa7 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xc0 + irq 0xe3 = 0xe0 + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x10 + end + device pnp 2e.209 on # GPIO4 + irq 0xe8 = 0x4e + irq 0xf0 = 0xfd + irq 0xf1 = 0x04 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xfa + irq 0xf5 = 0x68 + irq 0xf7 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf0 = 0x10 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + irq 0xe0 = 0xff + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_hero/dsdt.asl b/src/mainboard/asus/maximus_vi_hero/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads new file mode 100644 index 00000000000..fe5bbb376fa --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_hero/gpio.c b/src/mainboard/asus/maximus_vi_hero/gpio.c new file mode 100644 index 00000000000..59829160c01 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/gpio.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_hero/hda_verb.c b/src/mainboard/asus/maximus_vi_hero/hda_verb.c new file mode 100644 index 00000000000..4b72507e09e --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/hda_verb.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x1043859d), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREY, + AZALIA_JACK_PRESENCE_DETECT, + 1, 4 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT | 0x8, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT | 0xc, + 6, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT | 0xc, + 2, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x1043859d, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_hero/romstage.c b/src/mainboard/asus/maximus_vi_hero/romstage.c new file mode 100644 index 00000000000..3e6a38bca1c --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vi_impact/Kconfig b/src/mainboard/asus/maximus_vi_impact/Kconfig new file mode 100644 index 00000000000..4bf32b6f7c0 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_IMPACT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/maximus_vi_impact" + +config MAINBOARD_PART_NUMBER + default "Maximus VI IMPACT" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB7~10 (Top) + # Header: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vi_impact/Kconfig.name b/src/mainboard/asus/maximus_vi_impact/Kconfig.name new file mode 100644 index 00000000000..688b58dceff --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_IMPACT + bool "Maximus VI IMPACT" diff --git a/src/mainboard/asus/maximus_vi_impact/Makefile.mk b/src/mainboard/asus/maximus_vi_impact/Makefile.mk new file mode 100644 index 00000000000..c3cf55d3979 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vi_impact/acpi/ec.asl b/src/mainboard/asus/maximus_vi_impact/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_impact/acpi/platform.asl b/src/mainboard/asus/maximus_vi_impact/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_impact/acpi/superio.asl b/src/mainboard/asus/maximus_vi_impact/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_impact/board_info.txt b/src/mainboard/asus/maximus_vi_impact/board_info.txt new file mode 100644 index 00000000000..3fc4ed6edea --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://rog.asus.com/motherboards/rog-maximus/rog-maximus-vi-impact-model/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_impact/bootblock.c b/src/mainboard/asus/maximus_vi_impact/bootblock.c new file mode 100644 index 00000000000..08a1e2178a3 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x13, 0x00); + pnp_write_config(GLOBAL_DEV, 0x14, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1a, 0x30); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0x04); + pnp_write_config(GLOBAL_DEV, 0x26, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x01); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/asus/maximus_vi_impact/data.vbt b/src/mainboard/asus/maximus_vi_impact/data.vbt new file mode 100644 index 00000000000..174f6d69b93 Binary files /dev/null and b/src/mainboard/asus/maximus_vi_impact/data.vbt differ diff --git a/src/mainboard/asus/maximus_vi_impact/devicetree.cb b/src/mainboard/asus/maximus_vi_impact/devicetree.cb new file mode 100644 index 00000000000..de897019ca0 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/devicetree.cb @@ -0,0 +1,130 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + register "usb_xhci_on_resume" = "false" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8581 + end + device pci 1c.0 on end # RP #1: M.2 (NGFF) + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: mPCIe (WiFi) + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf1 = 0xa7 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x10 + end + device pnp 2e.209 on # GPIO4 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xea + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf0 = 0x10 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_impact/dsdt.asl b/src/mainboard/asus/maximus_vi_impact/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vi_impact/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_impact/gma-mainboard.ads new file mode 100644 index 00000000000..4cadc08f4d2 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_impact/gpio.c b/src/mainboard/asus/maximus_vi_impact/gpio.c new file mode 100644 index 00000000000..4493c63c265 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/gpio.c @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_impact/hda_verb.c b/src/mainboard/asus/maximus_vi_impact/hda_verb.c new file mode 100644 index 00000000000..817f0e32f7e --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/hda_verb.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438581), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, 0x4037c040), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 4, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 4, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x10438581, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_impact/romstage.c b/src/mainboard/asus/maximus_vi_impact/romstage.c new file mode 100644 index 00000000000..a810644a391 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_impact/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig b/src/mainboard/asus/maximus_vii_impact/Kconfig new file mode 100644 index 00000000000..0feae506c4c --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VII_IMPACT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asus/maximus_vii_impact" + +config MAINBOARD_PART_NUMBER + default "Maximus VII IMPACT" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: KBMS_USB910 (bottom) + # Header: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig.name b/src/mainboard/asus/maximus_vii_impact/Kconfig.name new file mode 100644 index 00000000000..d5a59d8f4c4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VII_IMPACT + bool "Maximus VII IMPACT" diff --git a/src/mainboard/asus/maximus_vii_impact/Makefile.mk b/src/mainboard/asus/maximus_vii_impact/Makefile.mk new file mode 100644 index 00000000000..c9500cfe9b4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_impact/board_info.txt b/src/mainboard/asus/maximus_vii_impact/board_info.txt new file mode 100644 index 00000000000..2913218dfe7 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://rog.asus.com/motherboards/rog-maximus/rog-maximus-vi-impact-model/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2014 diff --git a/src/mainboard/asus/maximus_vii_impact/data.vbt b/src/mainboard/asus/maximus_vii_impact/data.vbt new file mode 100644 index 00000000000..04c363ae3fd Binary files /dev/null and b/src/mainboard/asus/maximus_vii_impact/data.vbt differ diff --git a/src/mainboard/asus/maximus_vii_impact/devicetree.cb b/src/mainboard/asus/maximus_vii_impact/devicetree.cb new file mode 100644 index 00000000000..0e8b1333112 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/devicetree.cb @@ -0,0 +1,134 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + register "usb_xhci_on_resume" = "false" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x003c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002246" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x85c4 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8603 + end + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: mPCIe WiFi + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf1 = 0xb3 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xd0 + end + device pnp 2e.109 on # GPIO3 + irq 0xe5 = 0x10 + irq 0xe7 = 0x70 + end + device pnp 2e.209 on # GPIO4 + irq 0xf1 = 0x36 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xef + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0x01 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vii_impact/dsdt.asl b/src/mainboard/asus/maximus_vii_impact/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads new file mode 100644 index 00000000000..938687fac9f --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vii_impact/gpio.c b/src/mainboard/asus/maximus_vii_impact/gpio.c new file mode 100644 index 00000000000..7b4720c0122 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vii_impact/hda_verb.c b/src/mainboard/asus/maximus_vii_impact/hda_verb.c new file mode 100644 index 00000000000..8cb8204b474 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/hda_verb.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438603), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, 0x4007c000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 6, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x10438603, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vii_impact/romstage.c b/src/mainboard/asus/maximus_vii_impact/romstage.c new file mode 100644 index 00000000000..cb0a045d15e --- /dev/null +++ b/src/mainboard/asus/maximus_vii_impact/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/maximus_vii_ranger/Kconfig b/src/mainboard/asus/maximus_vii_ranger/Kconfig new file mode 100644 index 00000000000..06b4ae6aaa6 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VII_RANGER + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asus/maximus_vii_ranger" + +config MAINBOARD_PART_NUMBER + default "Maximus VII RANGER" + +config USBDEBUG_HCD_INDEX + default 2 # Header1: USB910 + # Header2: USB3_12 +endif diff --git a/src/mainboard/asus/maximus_vii_ranger/Kconfig.name b/src/mainboard/asus/maximus_vii_ranger/Kconfig.name new file mode 100644 index 00000000000..e1f4a0cd31e --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VII_RANGER + bool "Maximus VII RANGER" diff --git a/src/mainboard/asus/maximus_vii_ranger/Makefile.mk b/src/mainboard/asus/maximus_vii_ranger/Makefile.mk new file mode 100644 index 00000000000..c9500cfe9b4 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vii_ranger/acpi/ec.asl b/src/mainboard/asus/maximus_vii_ranger/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_ranger/acpi/platform.asl b/src/mainboard/asus/maximus_vii_ranger/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vii_ranger/acpi/superio.asl b/src/mainboard/asus/maximus_vii_ranger/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vii_ranger/board_info.txt b/src/mainboard/asus/maximus_vii_ranger/board_info.txt new file mode 100644 index 00000000000..e9e3d80eb99 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://rog.asus.com/motherboards/rog-maximus/rog-maximus-vii-ranger-model/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2014 diff --git a/src/mainboard/asus/maximus_vii_ranger/data.vbt b/src/mainboard/asus/maximus_vii_ranger/data.vbt new file mode 100644 index 00000000000..7cf807a2d0a Binary files /dev/null and b/src/mainboard/asus/maximus_vii_ranger/data.vbt differ diff --git a/src/mainboard/asus/maximus_vii_ranger/devicetree.cb b/src/mainboard/asus/maximus_vii_ranger/devicetree.cb new file mode 100644 index 00000000000..4f30a8e49a0 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/devicetree.cb @@ -0,0 +1,136 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG: PCIE_X16/X8_1 + device pci 01.1 on end # PEG: PCIE_X8_2 + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x003c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40042246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x85c4 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8602 + end + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4: PCIEX1_1 + device pci 1c.4 on end # RP #5: PCIEX4_3 + device pci 1c.5 on end # RP #6 + device pci 1c.6 on end # RP #7: PCIEX1_2/M.2(SOCKET 3) + device pci 1c.7 on end # RP #8: PCIEX1_3 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe1 = 0x88 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xbf + irq 0xf1 = 0xb3 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xd0 + end + device pnp 2e.109 on # GPIO3 + irq 0xe5 = 0x10 + end + device pnp 2e.209 on # GPIO4 + irq 0xf1 = 0x36 + end + device pnp 2e.309 on # GPIO5 + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xee = 0x10 + irq 0xf2 = 0x5d + irq 0xfc = 0x80 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0x01 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + irq 0xe0 = 0xff + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vii_ranger/dsdt.asl b/src/mainboard/asus/maximus_vii_ranger/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/maximus_vii_ranger/gma-mainboard.ads b/src/mainboard/asus/maximus_vii_ranger/gma-mainboard.ads new file mode 100644 index 00000000000..6ec7398d20c --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vii_ranger/gpio.c b/src/mainboard/asus/maximus_vii_ranger/gpio.c new file mode 100644 index 00000000000..7217ff5cdfc --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/gpio.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vii_ranger/hda_verb.c b/src/mainboard/asus/maximus_vii_ranger/hda_verb.c new file mode 100644 index 00000000000..e72fa0cfbbb --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/hda_verb.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const u32 realtek_alc1150_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438602), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC1150_FRONT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 2 + )), + AZALIA_PIN_CFG(0, ALC1150_CENTER_LFE, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 1 + )), + AZALIA_PIN_CFG(0, ALC1150_SIDE_SURROUND, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREY, + AZALIA_JACK_PRESENCE_DETECT, + 1, 4 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_MIC2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 6, 0 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_LINE2, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 15 + )), + AZALIA_PIN_CFG(0, ALC1150_SPDIF_OUT1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0 + )), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1150", + .vendor_id = 0x10ec0900, + .subsystem_id = 0x10438602, + .address = 0, + .verbs = realtek_alc1150_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1150_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vii_ranger/romstage.c b/src/mainboard/asus/maximus_vii_ranger/romstage.c new file mode 100644 index 00000000000..5df3348d77d --- /dev/null +++ b/src/mainboard/asus/maximus_vii_ranger/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0140, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 68b8d924867..11e79d9879d 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -41,7 +41,7 @@ config BOARD_ASUS_P8Z77_V_LX2 select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select REALTEK_8168_RESET - select SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_NCT5535D select USE_NATIVE_RAMINIT select POWER_LED_USES_GPIO8 @@ -67,7 +67,6 @@ config BOARD_ASUS_P8Z77_V_LE_PLUS select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select RT8168_SET_LED_MODE - select RT8168_PUT_MAC_TO_ERI select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT select POWER_LED_USES_GPIO8 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 69a2f4544c5..f17151c9e40 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -3,11 +3,11 @@ #include #include #include -#include +#include #define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0) -#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1) -#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT5535D_SP1) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT5535D_ACPI) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 926d9d1c15e..e79ad869150 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -28,44 +28,22 @@ chip northbridge/intel/sandybridge device ref pcie_rp8 on end # PCIEX1_2 device ref lpc on - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel + chip superio/nuvoton/nct5535d device pnp 2e.2 on # UART A io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # UART B, IR device pnp 2e.5 on # Keyboard io 0x60 = 0x0060 io 0x62 = 0x0064 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6-8 - device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 off end # GPIO0 - device pnp 2e.9 off end # GPIO8 - device pnp 2e.109 off end # GPIO1 - device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff - end - device pnp 2e.309 off end # GPIO3 - device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 off end # GPIO5 - device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 - device pnp 2e.a on end # ACPI device pnp 2e.b on # H/W Monitor, FP LED io 0x60 = 0x0290 io 0x62 = 0 irq 0x70 = 0 end - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR Wake-up - device pnp 2e.f off end # Push-pull/Open-drain - device pnp 2e.14 off end # Port 80 UART - device pnp 2e.16 off end # Deep Sleep end end end diff --git a/src/mainboard/asus/z87-k/Kconfig b/src/mainboard/asus/z87-k/Kconfig new file mode 100644 index 00000000000..11918fe0177 --- /dev/null +++ b/src/mainboard/asus/z87-k/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_Z87_K + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/z87-k" + +config MAINBOARD_PART_NUMBER + default "Z87-K" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB910 (Bottom) + # Header: USB3_12 +endif diff --git a/src/mainboard/asus/z87-k/Kconfig.name b/src/mainboard/asus/z87-k/Kconfig.name new file mode 100644 index 00000000000..4c9f6636372 --- /dev/null +++ b/src/mainboard/asus/z87-k/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_Z87_K + bool "Z87-K" diff --git a/src/mainboard/asus/z87-k/Makefile.mk b/src/mainboard/asus/z87-k/Makefile.mk new file mode 100644 index 00000000000..c9500cfe9b4 --- /dev/null +++ b/src/mainboard/asus/z87-k/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/z87-k/acpi/ec.asl b/src/mainboard/asus/z87-k/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/z87-k/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/z87-k/acpi/platform.asl b/src/mainboard/asus/z87-k/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asus/z87-k/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/z87-k/acpi/superio.asl b/src/mainboard/asus/z87-k/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asus/z87-k/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/z87-k/board_info.txt b/src/mainboard/asus/z87-k/board_info.txt new file mode 100644 index 00000000000..18e165090ad --- /dev/null +++ b/src/mainboard/asus/z87-k/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/us/supportonly/z87-k/helpdesk_knowledge/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/z87-k/data.vbt b/src/mainboard/asus/z87-k/data.vbt new file mode 100644 index 00000000000..781da09c28d Binary files /dev/null and b/src/mainboard/asus/z87-k/data.vbt differ diff --git a/src/mainboard/asus/z87-k/devicetree.cb b/src/mainboard/asus/z87-k/devicetree.cb new file mode 100644 index 00000000000..30d2fe1e131 --- /dev/null +++ b/src/mainboard/asus/z87-k/devicetree.cb @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1043 0x8534 inherit + + device pci 00.0 on end # Desktop Host bridge + device pci 01.0 on end # PEG: PCIEX16_1 + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gpe0_en_1" = "0x2046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI 1 + device pci 16.1 off end # MEI 2 + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x8576 + end + device pci 1c.0 on end # RP #1: PCIEX1_1 + device pci 1c.1 on end # RP #2: PCIEX1_2 + device pci 1c.2 on # RP #3 + device pci 00.0 on end # Realtek RTL8111 Gigabit Ethernet + end + device pci 1c.3 on # RP #4 + device pci 00.0 on end # ASMedia ASM1083 PCIe to PCI bridge + end + device pci 1c.4 on end # RP #5: PCIEX16_2 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d # Actual chip is NCT5538D + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + end + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xbe + irq 0xf1 = 0x01 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xd0 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x02 + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xed = 0x01 + irq 0xf0 = 0x10 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/z87-k/dsdt.asl b/src/mainboard/asus/z87-k/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asus/z87-k/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/z87-k/gma-mainboard.ads b/src/mainboard/asus/z87-k/gma-mainboard.ads new file mode 100644 index 00000000000..b0c2c29b44b --- /dev/null +++ b/src/mainboard/asus/z87-k/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/z87-k/gpio.c b/src/mainboard/asus/z87-k/gpio.c new file mode 100644 index 00000000000..aa3059b05aa --- /dev/null +++ b/src/mainboard/asus/z87-k/gpio.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, /* Front panel LED, used to make it blink in S3? */ + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio26 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio70 = GPIO_LEVEL_HIGH, /* Enable pin of 1.2V LDO for ASM108x PCI bridge */ +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/z87-k/hda_verb.c b/src/mainboard/asus/z87-k/hda_verb.c new file mode 100644 index 00000000000..0f9180766f6 --- /dev/null +++ b/src/mainboard/asus/z87-k/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc887_verbs[] = { + AZALIA_SUBVENDOR(0, 0x10438576), + AZALIA_PIN_CFG(0, 0x11, 0x90460130), + AZALIA_PIN_CFG(0, 0x12, 0x40330000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4044c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC887", + .vendor_id = 0x10ec0887, + .subsystem_id = 0x10438576, + .address = 0, + .verbs = realtek_alc887_verbs, + .verb_count = ARRAY_SIZE(realtek_alc887_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/z87-k/romstage.c b/src/mainboard/asus/z87-k/romstage.c new file mode 100644 index 00000000000..d35ae2ec3d9 --- /dev/null +++ b/src/mainboard/asus/z87-k/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb index f115303944f..9b588e5bb11 100644 --- a/src/mainboard/bostentech/gbyt4/devicetree.cb +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -3,14 +3,14 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" # SATA port enable mask (2 ports) register "sata_port_map" = "0x3" - register "sata_ahci" = "0x1" + register "sata_ahci" = "true" # Do not route USB ports to XHCI - register "usb_route_to_xhci" = "0" + register "usb_route_to_xhci" = "false" # USB Port Disable Mask register "usb2_port_disable_mask" = "0x0" @@ -27,7 +27,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" + register "disable_slp_x_stretch_sus_fail" = "true" device cpu_cluster 0 on end device domain 0 on diff --git a/src/mainboard/bytedance/bd_egs/bootblock.c b/src/mainboard/bytedance/bd_egs/bootblock.c index 0ae8b1d8005..eee0c406196 100644 --- a/src/mainboard/bytedance/bd_egs/bootblock.c +++ b/src/mainboard/bytedance/bd_egs/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index fa9344e1b69..5099b9f7407 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + #register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/dell/sklkbl_desktops/Kconfig b/src/mainboard/dell/sklkbl_desktops/Kconfig index 6d57c1ed108..098d43dc225 100644 --- a/src/mainboard/dell/sklkbl_desktops/Kconfig +++ b/src/mainboard/dell/sklkbl_desktops/Kconfig @@ -45,4 +45,9 @@ config CBFS_SIZE config DIMM_SPD_SIZE default 512 if BOARD_DELL_OPTIPLEX_3050 # DDR4 +# Won't boot if MFS partition is missing, deguard requires it +config ME_CLEANER_ARGS + string + default "-S --whitelist MFS" + endif diff --git a/src/mainboard/dell/sklkbl_desktops/devicetree.cb b/src/mainboard/dell/sklkbl_desktops/devicetree.cb index f66091f6793..0dbc298fd4c 100644 --- a/src/mainboard/dell/sklkbl_desktops/devicetree.cb +++ b/src/mainboard/dell/sklkbl_desktops/devicetree.cb @@ -4,7 +4,7 @@ chip soc/intel/skylake register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" device domain 0 on diff --git a/src/mainboard/emulation/qemu-i440fx/rom_media.c b/src/mainboard/emulation/qemu-i440fx/rom_media.c index f4fd3c37751..5c9626b7aad 100644 --- a/src/mainboard/emulation/qemu-i440fx/rom_media.c +++ b/src/mainboard/emulation/qemu-i440fx/rom_media.c @@ -43,7 +43,7 @@ static ssize_t qemu_writeat(const struct region_device *rd, const void *b, volatile char *ptr; const char *buf = b; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); ptr = &mdev->base[offset]; for (i = 0; i < size; i++) { @@ -67,7 +67,7 @@ static ssize_t qemu_eraseat(const struct region_device *rd, size_t offset, size_t i; volatile char *ptr; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); ptr = &mdev->base[offset]; if (!IS_ALIGNED(offset, QEMU_FLASH_BLOCK_SIZE)) { diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index 9de1b75f50c..8df5c9843bc 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -2,4 +2,9 @@ chip mainboard/emulation/qemu-riscv device cpu_cluster 0 on end + + device domain 0 on + ops qemu_riscv_pci_domain_ops + device pci 00.0 on end + end end diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index eb0e9f34401..f36491c50cb 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -1,9 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #define QEMU_VIRT_CLINT 0x02000000 +#define QEMU_VIRT_PCIE_PIO 0x03000000 #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 #define QEMU_VIRT_FW_CFG 0x10100000 #define QEMU_VIRT_FLASH 0x20000000 +#define QEMU_VIRT_PCIE_ECAM 0x30000000 +#define QEMU_VIRT_PCIE_ECAM_SIZE 0x10000000 +#define QEMU_VIRT_PCIE_MMIO_BASE 0x40000000 +#define QEMU_VIRT_PCIE_MMIO_LIMIT 0x7fffffff #define QEMU_VIRT_DRAM 0x80000000 +#define QEMU_VIRT_PCIE_MMIO_HIGH_BASE 0x300000000ULL +#define QEMU_VIRT_PCIE_MMIO_HIGH_LIMIT 0x3ffffffffULL diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 61e8f989258..e801d14ba7f 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -2,16 +2,52 @@ #include #include +#include #include #include +#include + +static void qemu_riscv_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* PCI I/O port window */ + res = new_resource(dev, index++); + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* 32-bit PCI MMIO window */ + res = new_resource(dev, index++); + res->base = QEMU_VIRT_PCIE_MMIO_BASE; + res->limit = QEMU_VIRT_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + /* + * NOTE: 64-bit MMIO window (0x300000000-0x3ffffffff) is omitted + * because OpenSBI 1.1 (bundled with coreboot) does not add PMP + * entries for it, causing S-mode load access faults. All BARs + * will be assigned in the 32-bit window which is plenty for the + * QEMU virt machine's typical device set. + */ + + /* ECAM config space (fixed MMIO) */ + mmio_range(dev, index++, QEMU_VIRT_PCIE_ECAM, QEMU_VIRT_PCIE_ECAM_SIZE); + + /* DRAM */ + ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top()); +} + +struct device_operations qemu_riscv_pci_domain_ops = { + .read_resources = qemu_riscv_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; static void mainboard_enable(struct device *dev) { - if (!dev) { + if (!dev) die("No dev0; die\n"); - } - - ram_from_to(dev, 0, (uintptr_t)_dram, cbmem_top()); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/emulation/qemu-riscv/mmio.c b/src/mainboard/emulation/qemu-riscv/mmio.c index 86fc626d14f..9c38a747413 100644 --- a/src/mainboard/emulation/qemu-riscv/mmio.c +++ b/src/mainboard/emulation/qemu-riscv/mmio.c @@ -3,4 +3,4 @@ #include #include -uintptr_t io_port_mmio_base = QEMU_VIRT_FW_CFG; +uintptr_t io_port_mmio_base = QEMU_VIRT_PCIE_PIO; diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb index 7bf15668236..92435ca2152 100644 --- a/src/mainboard/erying/tgl/devicetree.cb +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/tigerlake .vnn_sx_voltage_mv = 1050, }" - device cpu_cluster 0 on end device domain 0 on device ref igpu on register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" # DP diff --git a/src/mainboard/framework/Kconfig b/src/mainboard/framework/Kconfig index 980aa6d34fc..3feeae7bc32 100644 --- a/src/mainboard/framework/Kconfig +++ b/src/mainboard/framework/Kconfig @@ -14,4 +14,7 @@ source "src/mainboard/framework/*/Kconfig" config MAINBOARD_VENDOR default "Framework" +config EC_GOOGLE_CHROMEEC_ACPI_HID + default "FRMWC004" + endif # VENDOR_FRAMEWORK diff --git a/src/mainboard/framework/azalea/romstage.c b/src/mainboard/framework/azalea/romstage.c index 73fa78ef14e..16990d45f42 100644 --- a/src/mainboard/framework/azalea/romstage.c +++ b/src/mainboard/framework/azalea/romstage.c @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/framework/azalea/smihandler.c b/src/mainboard/framework/azalea/smihandler.c index 73fa78ef14e..16990d45f42 100644 --- a/src/mainboard/framework/azalea/smihandler.c +++ b/src/mainboard/framework/azalea/smihandler.c @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/framework/marigold/Kconfig b/src/mainboard/framework/marigold/Kconfig new file mode 100644 index 00000000000..3f5c1478fbc --- /dev/null +++ b/src/mainboard/framework/marigold/Kconfig @@ -0,0 +1,78 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_FRAMEWORK_MARIGOLD_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CRB_TPM + select DRIVERS_I2C_HID + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_INTEL_WIFI + select DRIVERS_GFX_GENERIC + select DRIVERS_INTEL_PMC + select HAVE_ACPI_TABLES + select HAVE_INTEL_PTT + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MEMORY_MAPPED_TPM + select PMC_IPC_ACPI_INTERFACE + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_SUPPORT_RESIZABLE_BARS + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SKIP_SEND_CONNECT_TOPOLOGY_CMD + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_MEASURED_BOOT + +config BOARD_FRAMEWORK_MARIGOLD + select BOARD_FRAMEWORK_MARIGOLD_COMMON + select FSP_TYPE_IOT + select SOC_INTEL_METEORLAKE_U_H + +if BOARD_FRAMEWORK_MARIGOLD_COMMON + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAINBOARD_DIR + default "framework/marigold" + +config MAINBOARD_PART_NUMBER + default "Framework Laptop 13 (Intel Core Ultra Series 1)" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Laptop 13 (Intel Core Ultra Series 1)" + +config MAINBOARD_FAMILY + default "Laptop" + +config CONSOLE_POST + default y + +config D3COLD_SUPPORT + default y + +config DIMM_SPD_SIZE + default 1024 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 36 + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/framework/marigold/Kconfig.name b/src/mainboard/framework/marigold/Kconfig.name new file mode 100644 index 00000000000..51a7eca3b6d --- /dev/null +++ b/src/mainboard/framework/marigold/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_FRAMEWORK_MARIGOLD + bool "Laptop 13 (Intel Core Ultra Series 1)" diff --git a/src/mainboard/framework/marigold/Makefile.mk b/src/mainboard/framework/marigold/Makefile.mk new file mode 100644 index 00000000000..96aba855660 --- /dev/null +++ b/src/mainboard/framework/marigold/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ec.c +ramstage-y += fadt.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/framework/marigold/board.fmd b/src/mainboard/framework/marigold/board.fmd new file mode 100644 index 00000000000..ee3600520b8 --- /dev/null +++ b/src/mainboard/framework/marigold/board.fmd @@ -0,0 +1,13 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 10128K + SI_DEVICEEXP2 6240K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/framework/marigold/board_info.txt b/src/mainboard/framework/marigold/board_info.txt new file mode 100644 index 00000000000..e535b1c4475 --- /dev/null +++ b/src/mainboard/framework/marigold/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://frame.work/laptop13 +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2024 diff --git a/src/mainboard/framework/marigold/bootblock.c b/src/mainboard/framework/marigold/bootblock.c new file mode 100644 index 00000000000..7e915cba5a1 --- /dev/null +++ b/src/mainboard/framework/marigold/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/framework/marigold/data.vbt b/src/mainboard/framework/marigold/data.vbt new file mode 100644 index 00000000000..9f21e445fe5 Binary files /dev/null and b/src/mainboard/framework/marigold/data.vbt differ diff --git a/src/mainboard/framework/marigold/devicetree.cb b/src/mainboard/framework/marigold/devicetree.cb new file mode 100644 index 00000000000..bbd360c468f --- /dev/null +++ b/src/mainboard/framework/marigold/devicetree.cb @@ -0,0 +1,376 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/meteorlake + register "common_soc_config.i2c[5]" = "{ + /* Touchpad I2C bus */ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "true" + + # Thermal + register "tcc_offset" = "8" + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + # S0ix enable for modern standby + register "s0ix_enable" = "true" + + # DPTF enable + register "dptf_enable" = "true" + + # Platform max power (100W USB-C PD, no EPR) + register "psys_pmax_watts" = "100" + + # SAGV + power management + register "sagv" = "SAGV_ENABLED" + register "pch_pm_energy_report_enable" = "1" + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + + # SOC Aux orientation override for Type-C retimers: + # All 4 ports have Hayden Bridge retimers, aux lines not swapped. + # Even bits (0,2,4,6): 0 = retimer present; Odd bits (1,3,5,7): 0 = aux not swapped. + register "tcss_aux_ori" = "0x00" + + device domain 0 on + subsystemid 0xf111 0x0003 inherit + + device ref igpu on + # DDIA is eDP + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + chip drivers/gfx/generic + register "device_count" = "5" + # [DDIA] eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # [TCP0] JUSBC3 - left side, front + register "device[1].name" = ""DD01"" + register "device[1].use_pld" = "true" + register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 0))" + # [TCP1] JUSBC4 - left side, back + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # [TCP2] JUSBC1 - right side, back + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 0))" + # [TCP3] JUSBC2 - right side, front + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + + device ref vpu on end + device ref dtt on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + + device ref tcss_xhci on + # TCP0 = JUSBC3, TCP1 = JUSBC4, TCP2 = JUSBC1, TCP3 = JUSBC2 + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC3)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 0))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC4)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 0))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC2)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + use tcss_usb3_port3 as dfp[1].typec_port + device generic 0 on end + end + end + + device ref xhci on + # USB2: [0]=DCI [1]=JUSBC1 [2]=JUSBC2 [3]=JUSBC3 [4]=JUSBC4 + # [6]=Camera [8]=Fingerprint [9]=WLAN-BT + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), + [1] = USB2_PORT_TYPE_C(OC_SKIP), + [2] = USB2_PORT_TYPE_C(OC_SKIP), + [3] = USB2_PORT_TYPE_C(OC_SKIP), + [4] = USB2_PORT_TYPE_C(OC_SKIP), + [6] = USB2_PORT_MID(OC_SKIP), + [8] = USB2_PORT_MID(OC_SKIP), + [9] = USB2_PORT_MID(OC_SKIP), + }" + # Type-C SuperSpeed is routed through TCSS (tcss_usb3_portN), + # not the PCH xHCI, so no PCH usb3_ports are populated. + chip drivers/usb/acpi + device ref xhci_root_hub on + # USB2 lines of the Type-C connectors. Locations match + # the gfx/TCSS entries (same panel + PLD group) so the OS + # correlates the USB2, SS and DP lanes of one connector. + # NB: usb2_portN is 1-based; usb2_ports[N-1] is the array. + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 0))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC2)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC3)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 0))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC4)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + # Internal devices (not user-visible) + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + + device ref ioe_shared_sram on end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 on end # JUSBC3 = TCP0 + end + chip drivers/intel/pmc_mux/conn + use usb2_port4 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 on end # JUSBC4 = TCP1 + end + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 2 on end # JUSBC1 = TCP2 + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 3 on end # JUSBC2 = TCP3 + end + end + end + end + device ref pmc_shared_sram on end + + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FRMW0004"" + register "generic.desc" = ""EC Mediakeys"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B05)" + register "hid_desc_reg_offset" = "0x55" + device i2c 50 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FRMW0005"" + register "generic.desc" = ""EC ALS"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D06_IRQ)" + register "hid_desc_reg_offset" = "0x55" + device i2c 51 on end + end + end + + device ref i2c3 on + # Touch Screen + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + + device ref i2c4 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + + device ref i2c5 on + # Touchpad on I2C5 alternate pins (GPP_B20/B21) + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""PIXA3854"" + register "generic.desc" = ""Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + + device ref pcie_rp1 on + # SSD M.2 NVMe: PCIe x4, Gen4 + register "pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 15, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B06)" + register "srcclk_pin" = "0" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + + device ref pcie_rp6 on + # WLAN M.2 Key-E: PCIe x1 + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + + # BIOS/OS console + device ref uart0 on + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoSkipInit" + end + + device ref soc_espi on + # EC host command ranges: 0x200-0x20f + register "gen1_dec" = "0x000c0201" + # EC memory range: 0xE00-0xEFF + register "gen2_dec" = "0x00fc0e01" + # EC extended range: 0xF00-0xFFF + register "gen3_dec" = "0x00fc0f01" + # EC NPCX shared memory: 0x800-0x8FF + register "gen4_dec" = "0x00fc0801" + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + + chip drivers/crb + device mmio 0xfed40000 on end + end + + device ref hda on + # Enable HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/framework/marigold/dsdt.asl b/src/mainboard/framework/marigold/dsdt.asl new file mode 100644 index 00000000000..a62b4d1080c --- /dev/null +++ b/src/mainboard/framework/marigold/dsdt.asl @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + #include + } + + #include + + /* Framework EC over eSPI */ + Scope (\_SB.PCI0.LPCB) + { + /* PS/2 keyboard + mouse, and EC host-command/memmap I/O reservations */ + #include + /* EC0: lid switch, AC adapter, battery, cros_ec command device */ + #include + } + + /* + * Clear ACPI driver ready before entering suspend, same as the vendor + * firmware, so the EC returns to preOS mode across the power transition. + */ + Method (\_SB.MPTS, 1, Serialized) + { + If (Arg0) { + \_SB.PCI0.LPCB.EC0.ADRD = 0 + } + } + + /* + * Signal ACPI driver ready to EC again, after resume from suspend, + * same as on boot, to make sure function keys, etc. are working. + */ + Method (\_SB.MWAK, 1, Serialized) + { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + \_SB.PCI0.LPCB.EC0.ADRD = 1 + } + } +} diff --git a/src/mainboard/framework/marigold/ec.c b/src/mainboard/framework/marigold/ec.c new file mode 100644 index 00000000000..4d06e824de1 --- /dev/null +++ b/src/mainboard/framework/marigold/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/framework/marigold/fadt.c b/src/mainboard/framework/marigold/fadt.c new file mode 100644 index 00000000000..f8841168f0d --- /dev/null +++ b/src/mainboard/framework/marigold/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->flags |= ACPI_FADT_POWER_BUTTON; +} diff --git a/src/mainboard/framework/marigold/gpio.c b/src/mainboard/framework/marigold/gpio.c new file mode 100644 index 00000000000..5974d066073 --- /dev/null +++ b/src/mainboard/framework/marigold/gpio.c @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * GPIO configuration from vendor firmware dump (inteltool -G) + * and schematic review. + */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPP_V - Power Management ------- */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1), /* BATLOW# / PCH_BATLOW# */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */ + PAD_NC(GPP_V02, NONE), /* SOC_WAK# / LAN_WAKE# (unused) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# / PBTN_OUT# (from EC) */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK (Suspend Clock) */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# / PM_SLP_WLAN# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */ + PAD_NC(GPP_V11, NONE), /* LANPHYPC (not connected) */ + PAD_NC(GPP_V12, NONE), /* SLP_LAN# (only testpoint TP3) */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# / SOC_WL_WAKE# */ + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), + + /* ------- GPP_C - SMBus, SML, CLKREQs, TBT ------- */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* SMBCLK / SOC_SMBCLK (DDR) */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* SMBDATA /SOC_SMBDATA (DDR) */ + PAD_CFG_GPI(GPP_C02, NONE, DEEP), /* GPP_C2_STRAP (TLS strap, has 4.7k pullup to 1.8V_PRIM) */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* SML0CLK (TBT, has 2.2k pullup to 1.8V_PRIM) */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), /* SML0DATA (TBT, has 2.2k pullup to 1.8V_PRIM) */ + PAD_CFG_GPI(GPP_C05, NONE, DEEP), /* GPP_C5_STRAP (eSPI strap) */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), /* SML1CLK (PD 1/2) */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), /* SML1DATA (PD 1/2) */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), /* SML1ALERT# */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), /* SRCCLKREQ0# (SSD) */ + PAD_NC(GPP_C10, NONE), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* SRCCLKREQ2# (WLAN) */ + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C15, NONE), /* GPP_C15_STRAP (Reserved) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* TBT_LSX2_TXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TBT_LSX2_RXD */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* TBT_LSX3_TXD */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* TBT_LSX3_RXD */ + + /* ------- GPP_A - eSPI ------- */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), /* RTD3_WLAN_PLT_RST# (10k to 1.8VS) */ + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1), /* PMCALERT# / SOC_PD_INT# */ + + /* ------- GPP_E ------- */ + PAD_NC(GPP_E00, NONE), + PAD_NC(GPP_E01, NONE), /* SOC_WL_OFF# */ + PAD_NC(GPP_E02, NONE), + PAD_CFG_GPI(GPP_E03, NONE, DEEP), /* TPM_PIRQ# */ + PAD_NC(GPP_E04, NONE), + PAD_NC(GPP_E05, NONE), /* TS_INT# (Unused) */ + PAD_NC(GPP_E06, NONE), /* GPP_E6_STRAP (JTAG ODT Enable) */ + PAD_NC(GPP_E07, NONE), + PAD_NC(GPP_E08, NONE), + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), /* USB_OC0# / CCG6_PD2_OC3# */ + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* EDP_HPD / SOC_EDP_HPD# */ + PAD_NC(GPP_E15, NONE), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# connected to H_PROCHOT# */ + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), /* DNX_FORCE_RELOAD (NP resistor RC1 to 1.8V+PRIM) */ + + /* ------- GPP_H - UART, I2C1 ------- */ + /* TODO: Maybe explicitly drive these low instead of relying in "weak internal PD 20K" */ + PAD_NC(GPP_H00, NONE), /* GPP_H00_STRAP (eSPI flash sharing mode, no external pull) */ + PAD_NC(GPP_H01, NONE), /* GPP_H01_STRAP (Flash descriptor recovery, no external pull) */ + PAD_NC(GPP_H02, NONE), /* GPP_H02_STRAP (Reserved, no external pull) */ + PAD_NC(GPP_H04, NONE), + PAD_NC(GPP_H05, NONE), + PAD_NC(GPP_H06, NONE), /* I2C_3_SDA (Touchscreen, unused) */ + PAD_NC(GPP_H07, NONE), /* I2C_3_SCL (Touchscreen, unused) */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD (BIOS, OS UART) */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD (BIOS, OS UART) */ + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* CPU_C10_GATE# (unused) */ + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* I2C1_SDA (EC HID) */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* I2C1_SCL (EC HID) */ + + /* ------- GPP_F - CNVi ------- */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F01, NONE, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F03, NONE, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ / CLKREQ_CNV_1P8 */ + PAD_NC(GPP_F06, NONE), + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), + PAD_NC(GPP_F09, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), /* TS_EN (Touchscreen, unused) */ + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), /* GPP_F19_STRAP (Reserved) */ + PAD_NC(GPP_F20, NONE), /* GPP_F20_STRAP# (SVID VR) */ + PAD_NC(GPP_F21, NONE), /* GPP_F21_STRAP (Low: BSSB-LS CCD, High: Baltic Peak I3C CCD) */ + PAD_NC(GPP_F22, NONE), /* Testpoint TP4 */ + PAD_NC(GPP_F23, NONE), /* Testpoint TP5 */ + + /* ------- GPP_S - DMIC ------- */ + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), /* DMIC_CLK_A0 - TODO: I don't think this is connected to the PCH but instead the Codec */ + PAD_NC(GPP_S03, NONE), /* DMIC_DATA0 - TODO: I don't think this is connected to the PCH but instead the Codec */ + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + + /* ------- GPP_B - Platform, I2C5 ------- */ + PAD_CFG_GPI_INT(GPP_B00, NONE, DEEP, LEVEL), /* SOC_TP_INT# (Touchpad) */ + PAD_NC(GPP_B01, NONE), + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_NC(GPP_B04, NONE), /* GPP_B04_STRAP# (No Reboot) */ + PAD_CFG_GPI_INT(GPP_B05, NONE, DEEP, LEVEL), /* SOC_EC_INT# */ + PAD_CFG_GPO(GPP_B06, 1, DEEP), /* RTD3_SSD_PLT_RST# */ + PAD_NC(GPP_B07, NONE), /* TS_RESET (Touchscreen, unused) */ + PAD_NC(GPP_B08, NONE), + PAD_NC(GPP_B09, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# (Default is F1, so reset type doesn't matter) */ + PAD_NC(GPP_B14, NONE), /* TOP_SWAP_EN_STRAP */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* USB_OC3# / CCG6_PD1_OC0# */ + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), /* RT_GPIO6_CTRL_CPU (To turn off the retimer) */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), /* SOC_BT_ON */ + PAD_CFG_GPO(GPP_B19, 0, DEEP), /* SOC_DG_BB_FORCE_PWR (Force Retimer Power for firmware update) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF2), /* I2C5A_SDA (Touchpad) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF2), /* I2C5A_SCL (Touchpad) */ + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + /* ------- GPP_D - HDA ------- */ + PAD_NC(GPP_D00, NONE), + PAD_NC(GPP_D01, NONE), + PAD_NC(GPP_D02, NONE), + PAD_NC(GPP_D03, NONE), + PAD_NC(GPP_D04, NONE), + PAD_NC(GPP_D05, NONE), + PAD_CFG_GPI_APIC(GPP_D06, NONE, DEEP, LEVEL, INVERT), /* SOC_EC_INT2# */ + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), /* SML0B_ALERT# (TODO: This may need to be NF. It just has a pullup to +1.8V_PRIM) */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + /* TODO: Check if these are required */ + PAD_NC(GPP_D14, NONE), /* WLAN_PCM_CLK */ + PAD_NC(GPP_D15, NONE), /* WLAN_PCM_FRM */ + PAD_NC(GPP_D16, NONE), /* WLAN_PCM_IN */ + PAD_NC(GPP_D17, NONE), /* WLAN_PCM_OUT */ + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- VGPIO3 - USB Type-C mux control ------- */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/framework/marigold/gpio_early.c b/src/mainboard/framework/marigold/gpio_early.c new file mode 100644 index 00000000000..cdb5257f0e8 --- /dev/null +++ b/src/mainboard/framework/marigold/gpio_early.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* UART0 for console */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + + /* SMBus for DDR5 SPD */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* SMBDATA */ +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/framework/marigold/hda_verb.c b/src/mainboard/framework/marigold/hda_verb.c new file mode 100644 index 00000000000..acd23815dee --- /dev/null +++ b/src/mainboard/framework/marigold/hda_verb.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const u32 realtek_alc285_verbs[] = { + AZALIA_SUBVENDOR(0, 0xf1110009), + AZALIA_RESET(1), + + /* Pin widget configurations */ + /* DMIC - Internal Mic */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), /* DMIC - NC */ + /* Front (Port-D) - Internal Speaker */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), /* NPC */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* I2S OUT */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* I2S IN */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* NPC */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* LINE2 (Port-E) */ + AZALIA_PIN_CFG(0, 0x1d, 0x40651b05), /* BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* S/PDIF-OUT */ + /* HP1-OUT (Port-I) - Headphone Jack */ + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + + /* Reset power state to D0 */ + 0x00170500, 0x00170500, 0x00170500, 0x00170500, + + /* Reset all registers back to default */ + 0x0205001a, 0x02048003, 0x0205001a, 0x0204c003, + + /* ClassD reset */ + 0x0205003c, 0x0204f2d4, 0x0205003c, 0x0204f214, + + /* JD1 - 2port JD mode */ + 0x02050009, 0x0204e003, 0x0205000a, 0x02047770, + + /* Set TRS type-1 */ + 0x02050045, 0x0204c689, 0x02050049, 0x02040049, + + /* Set TRS type-2 (Turn off MIC2_Vrefo_R_L) + Set UAJ Line2 vref */ + 0x0205004a, 0x0204a830, 0x02050063, 0x02040f00, + + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + Set sine tone gain(0x34) */ + 0x02050038, 0x02047909, 0x05c50000, 0x05c43482, + + /* HP-JD Enable + For Nokia type (+power down JD2) */ + 0x0205004a, 0x02042010, 0x02050008, 0x02046a2c, + + /* EAPD set to verb-control (I2C unuse & DVDD= +3.3V) */ + 0x02050010, 0x02040020, 0x02050034, 0x0204a2b1, + + /* Class D silent detection enable -84dB threshold */ + 0x02050030, 0x02049000, 0x02050037, 0x0204fe15, + + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, 0x020477d7, 0x0143b000, 0x01470740, + + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470c02, 0x01470c02, 0x01470c02, 0x01470c02, + + /* ALC285 EQ Verb table - disable EQ first */ + 0x05350000, 0x053423da, 0x05350000, 0x053423da, + + /* Left Channel EQ */ + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341f61, 0x05350004, 0x05342299, + 0x0535001f, 0x0534039e, 0x05350020, 0x05341fc0, + 0x05350021, 0x05341e56, 0x05350022, 0x053454ec, + 0x05350023, 0x053401f3, 0x05350024, 0x053464aa, + 0x05350025, 0x05341c4a, 0x05350026, 0x05347f28, + 0x05350027, 0x053401c1, 0x05350028, 0x053456c6, + 0x05350012, 0x0534c391, 0x05350013, 0x05341c7b, + 0x05350014, 0x0534f8ff, 0x05350015, 0x0534c16f, + 0x05350016, 0x05341eb3, 0x05350017, 0x0534fa18, + 0x05350018, 0x0534c17f, 0x05350019, 0x05341ec4, + 0x0535001a, 0x0534069a, + + /* Right Channel EQ */ + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441f61, + 0x05450004, 0x05442299, 0x0545001f, 0x0544039e, + 0x05450020, 0x05441fc0, 0x05450021, 0x05441e56, + 0x05450022, 0x054454ec, 0x05450023, 0x054401f3, + 0x05450024, 0x054464aa, 0x05450025, 0x05441c4a, + 0x05450026, 0x05447f28, 0x05450027, 0x054401c1, + 0x05450028, 0x054456c6, 0x05450012, 0x0544c391, + 0x05450013, 0x05441c7b, 0x05450014, 0x0544f8ff, + 0x05450015, 0x0544c16f, 0x05450016, 0x05441eb3, + 0x05450017, 0x0544fa18, 0x05450018, 0x0544c17f, + 0x05450019, 0x05441ec4, 0x0545001a, 0x0544069a, + + /* EQ enable + additional DSP settings */ + 0x05350000, 0x0534e3da, 0x02050038, 0x02044909, + 0x05350002, 0x05348000, 0x05d50006, 0x05d44c50, + 0x05d50002, 0x05d441c4, 0x05d50003, 0x05d45f5f, + 0x05d50001, 0x05d4d78c, 0x05d50009, 0x05d451ff, + 0x05d50006, 0x05d44e50, +}; + +static const u32 intel_mtl_hdmi_verbs[] = { + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x08, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0c, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0d, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x0f, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC285", + .vendor_id = 0x10ec0285, + .subsystem_id = 0xf1110009, + .address = 0, + .verbs = realtek_alc285_verbs, + .verb_count = ARRAY_SIZE(realtek_alc285_verbs), + }, + { + .name = "Intel Meteor Lake HDMI", + .vendor_id = 0x8086281d, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_mtl_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_mtl_hdmi_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/framework/marigold/include/mainboard/bootblock.h b/src/mainboard/framework/marigold/include/mainboard/bootblock.h new file mode 100644 index 00000000000..f7a9a294f8d --- /dev/null +++ b/src/mainboard/framework/marigold/include/mainboard/bootblock.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_BOOTBLOCK_H +#define MAINBOARD_BOOTBLOCK_H + +void mainboard_configure_early_gpios(void); + +#endif /* MAINBOARD_BOOTBLOCK_H */ diff --git a/src/mainboard/framework/marigold/include/mainboard/ec.h b/src/mainboard/framework/marigold/include/mainboard/ec.h new file mode 100644 index 00000000000..b3c4845e32b --- /dev/null +++ b/src/mainboard/framework/marigold/include/mainboard/ec.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include +#include + +/* + * EC events that the Framework CrosEC fork raises as SCIs + * Does NOT include Chromebook events like MKBP, PD_MCU, ... + */ +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)) +#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with power button only */ +#define MAINBOARD_EC_S5_WAKE_EVENTS EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) +/* EC can additionally wake from S3/S0ix on AC change and critical battery */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS MAINBOARD_EC_S3_WAKE_EVENTS +/* Log EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* ACPI feature toggles to enable EC eSPI, lid and wake */ +#define EC_SCI_GPI GPE0_ESPI +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_POWER_BUTTON +#define EC_ENABLE_WAKE_PIN GPE0_ESPI + +/* + * Enable standard PS2 keyboard (not e.g. Chrome Vivaldi) + * Also when the OS has no I2C HID driver (e.g. Windows installer), the EC + * presents an emulated PS2 mouse interface to allow using the touchpad. + */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_ENABLE_PS2M /* Enable PS/2 Mouse */ + +/* + * Framework ACPI shared memory with the EC + * + * Contains a couple of flags and up-to-date system information. + */ +#define EC_FRAMEWORK_ACPI_SHARED_MEM_IO 0xF00 + +#endif /* MAINBOARD_EC_H */ diff --git a/src/mainboard/framework/marigold/include/mainboard/ramstage.h b/src/mainboard/framework/marigold/include/mainboard/ramstage.h new file mode 100644 index 00000000000..a8d3d9956e5 --- /dev/null +++ b/src/mainboard/framework/marigold/include/mainboard/ramstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_RAMSTAGE_H +#define MAINBOARD_RAMSTAGE_H + +void mainboard_configure_gpios(void); + +#endif /* MAINBOARD_RAMSTAGE_H */ diff --git a/src/mainboard/framework/marigold/ramstage.c b/src/mainboard/framework/marigold/ramstage.c new file mode 100644 index 00000000000..252f8dfbb5b --- /dev/null +++ b/src/mainboard/framework/marigold/ramstage.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* + * Disable C10 reporting over eSPI to prevent LED flicker + * during S0ix entry/exit on MTL laptops. + */ + params->PchEspiHostC10ReportEnable = 0; + + /* Auto-notify iGPU of display changes on USB-C (for hotplug) */ + params->TcNotifyIgd = 2; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); + mainboard_ec_init(); +} + +struct chip_operations mainboard_ops = {.init = mainboard_init}; diff --git a/src/mainboard/framework/marigold/romstage.c b/src/mainboard/framework/marigold/romstage.c new file mode 100644 index 00000000000..8d34655de3d --- /dev/null +++ b/src/mainboard/framework/marigold/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .UserBd = BOARD_TYPE_ULT_ULX, + .ddr_config = { + .dq_pins_interleaved = false, + }, + }; + + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + + const bool half_populated = false; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/framework/marigold/smihandler.c b/src/mainboard/framework/marigold/smihandler.c new file mode 100644 index 00000000000..25d07735fa1 --- /dev/null +++ b/src/mainboard/framework/marigold/smihandler.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} diff --git a/src/mainboard/framework/sakura/Kconfig b/src/mainboard/framework/sakura/Kconfig new file mode 100644 index 00000000000..9b48dd8aa92 --- /dev/null +++ b/src/mainboard/framework/sakura/Kconfig @@ -0,0 +1,85 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_FRAMEWORK_SAKURA_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CRB_TPM + select DRIVERS_I2C_HID + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_INTEL_WIFI + select DRIVERS_GFX_GENERIC + select DRIVERS_INTEL_PMC + select HAVE_ACPI_TABLES + select HAVE_INTEL_PTT + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MEMORY_MAPPED_TPM + select PMC_IPC_ACPI_INTERFACE + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_SUPPORT_RESIZABLE_BARS + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_MEASURED_BOOT + +config BOARD_FRAMEWORK_SAKURA + select BOARD_FRAMEWORK_SAKURA_COMMON + select FSP_TYPE_IOT + select SOC_INTEL_PANTHERLAKE_U_H + +if BOARD_FRAMEWORK_SAKURA_COMMON + +config MAINBOARD_DIR + default "framework/sakura" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +# The PTL SoC default (0xd0000) is sized only for FSP-S preloading. Our UEFI +# payload is ~1.44 MB, so cbfs_preload() of the payload fails to allocate and +# trips an assert in commonlib/list.c. Enlarge the cache to fit dsdt.aml + the +# payload. +config RAMSTAGE_CBFS_CACHE_SIZE + default 0x200000 + +config MAINBOARD_PART_NUMBER + default "Framework Laptop 13 Pro (Intel Core Ultra Series 3)" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Laptop 13 Pro (Intel Core Ultra Series 3)" + +config MAINBOARD_FAMILY + default "Laptop" + +config CONSOLE_POST + default y + +config D3COLD_SUPPORT + default y + +config DIMM_SPD_SIZE + default 1024 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 36 + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/framework/sakura/Kconfig.name b/src/mainboard/framework/sakura/Kconfig.name new file mode 100644 index 00000000000..8d9cf2a403f --- /dev/null +++ b/src/mainboard/framework/sakura/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_FRAMEWORK_SAKURA + bool "Laptop 13 Pro (Intel Core Ultra Series 3)" diff --git a/src/mainboard/framework/sakura/Makefile.mk b/src/mainboard/framework/sakura/Makefile.mk new file mode 100644 index 00000000000..96aba855660 --- /dev/null +++ b/src/mainboard/framework/sakura/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ec.c +ramstage-y += fadt.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/framework/sakura/alc1320_smartamp.inc b/src/mainboard/framework/sakura/alc1320_smartamp.inc new file mode 100644 index 00000000000..0c0b318faac --- /dev/null +++ b/src/mainboard/framework/sakura/alc1320_smartamp.inc @@ -0,0 +1,15706 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * ALC1320 Class-D smart-amp firmware/register/EQ initialization sequence. + * For Framework Laptop 13 Pro chassis speakers. + */ + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c570, 0x02050028, 0x02040000, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c560, + 0x02050028, 0x02040000, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c000, 0x02050028, 0x02040003, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c003, + 0x02050028, 0x020400e0, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204e80a, 0x02050028, 0x02040000, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c01b, + 0x02050028, 0x020400fd, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c5c3, 0x02050028, 0x020400f3, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c5c2, + 0x02050028, 0x02040050, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c5c6, 0x02050028, 0x02040010, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c5c4, + 0x02050028, 0x02040012, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c5c8, 0x02050028, 0x02040005, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c5d8, + 0x02050028, 0x0204000a, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c5d0, 0x02050028, 0x020400cf, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204dc20, + 0x02050028, 0x02040030, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c582, 0x02050028, 0x02040001, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c60b, + 0x02050028, 0x020400b1, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c5d3, 0x02050028, 0x0204000f, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c58d, + 0x02050028, 0x02040011, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c58c, 0x02050028, 0x02040098, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c057, + 0x02050028, 0x02040051, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c054, 0x02050028, 0x02040035, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c053, + 0x02050028, 0x02040055, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c052, 0x02050028, 0x02040055, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c051, + 0x02050028, 0x02040013, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c050, 0x02050028, 0x02040015, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c060, + 0x02050028, 0x02040099, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c061, 0x02050028, 0x02040055, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c063, + 0x02050028, 0x02040055, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c065, 0x02050028, 0x020400a5, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c06b, + 0x02050028, 0x0204000a, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204ca05, 0x02050028, 0x020400d6, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204ca07, + 0x02050028, 0x02040007, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204ca25, 0x02050028, 0x020400d6, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204ca27, + 0x02050028, 0x02040007, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204cd00, 0x02050028, 0x02040005, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204cf02, + 0x02050028, 0x0204000f, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c604, 0x02050028, 0x02040040, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c609, + 0x02050028, 0x02040040, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c600, 0x02050028, 0x02040005, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c601, + 0x02050028, 0x02040080, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c046, 0x02050028, 0x020400fc, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c045, + 0x02050028, 0x020400ff, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c044, 0x02050028, 0x020400ff, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c043, + 0x02050028, 0x020400ff, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c042, 0x02050028, 0x020400ff, + 0x02050029, 0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02040000, 0x02050026, 0x0204c041, + 0x02050028, 0x0204007f, 0x02050029, 0x0204b023, + 0x02050024, 0x02040010, 0x02050025, 0x02040000, + 0x02050026, 0x0204c040, 0x02050028, 0x020400ff, + 0x02050029, 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0x0204b023, 0x02050024, 0x02040010, + 0x02050025, 0x02041000, 0x02050026, 0x0204d0c5, + 0x02050028, 0x02040000, 0x02050029, 0x0204b023, diff --git a/src/mainboard/framework/sakura/board.fmd b/src/mainboard/framework/sakura/board.fmd new file mode 100644 index 00000000000..ee3600520b8 --- /dev/null +++ b/src/mainboard/framework/sakura/board.fmd @@ -0,0 +1,13 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 10128K + SI_DEVICEEXP2 6240K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/framework/sakura/board_info.txt b/src/mainboard/framework/sakura/board_info.txt new file mode 100644 index 00000000000..107dfee0f65 --- /dev/null +++ b/src/mainboard/framework/sakura/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://frame.work/laptop13pro +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2026 diff --git a/src/mainboard/framework/sakura/bootblock.c b/src/mainboard/framework/sakura/bootblock.c new file mode 100644 index 00000000000..7e915cba5a1 --- /dev/null +++ b/src/mainboard/framework/sakura/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/framework/sakura/data.vbt b/src/mainboard/framework/sakura/data.vbt new file mode 100644 index 00000000000..5a0666af983 Binary files /dev/null and b/src/mainboard/framework/sakura/data.vbt differ diff --git a/src/mainboard/framework/sakura/devicetree.cb b/src/mainboard/framework/sakura/devicetree.cb new file mode 100644 index 00000000000..a4bfc5990cf --- /dev/null +++ b/src/mainboard/framework/sakura/devicetree.cb @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/pantherlake + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "true" + + # Thermal + register "tcc_offset" = "8" + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # S0ix enable for modern standby + register "s0ix_enable" = "true" + + # DPTF enable + register "dptf_enable" = "true" + + # Platform max power (100W USB-C PD, no EPR) + register "psys_pmax_watts" = "100" + + # SAGV + power management + register "sagv" = "SAGV_ENABLED" + register "pch_pm_energy_report_enable" = "1" + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + + # SOC Aux orientation override for Type-C retimers: + # All 4 ports have Hayden Bridge retimers, aux lines not swapped. + register "tcss_aux_ori" = "0x00" + + # Enable all four TCSS Type-C ports with full functionality + # USB3 + DP-alt + Thunderbolt/USB4 + PCIe tunneling + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + device domain 0 on + subsystemid 0xf111 0x000f inherit + + device ref igpu on + # DDIA is eDP + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + chip drivers/gfx/generic + register "device_count" = "5" + # [DDIA] eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # [TCP0] JUSBC3 - left side, front + register "device[1].name" = ""DD01"" + register "device[1].use_pld" = "true" + register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 0))" + # [TCP1] JUSBC4 - left side, back + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # [TCP2] JUSBC1 - right side, front + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 0))" + # [TCP3] JUSBC2 - right side, back + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + + device ref npu on end + device ref iaa off end + device ref dtt on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + + device ref tcss_xhci on + # TCP0 = JUSBC3, TCP1 = JUSBC4, TCP2 = JUSBC1, TCP3 = JUSBC2 + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC3)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 0))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC4)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 0))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC2)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port3 as dfp[1].typec_port + device generic 0 on end + end + end + + device ref xhci on + # USB2 port mapping from schematic (0-indexed): + # [0]=DCI [1]=JUSBC1 [2]=JUSBC2 [3]=JUSBC3 [4]=JUSBC4 + # [5]=Camera [6]=Fingerprint [7]=BT + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), + [1] = USB2_PORT_TYPE_C(OC_SKIP), + [2] = USB2_PORT_TYPE_C(OC_SKIP), + [3] = USB2_PORT_TYPE_C(OC_SKIP), + [4] = USB2_PORT_TYPE_C(OC_SKIP), + [5] = USB2_PORT_MID(OC_SKIP), + [6] = USB2_PORT_MID(OC_SKIP), + /* [7] BT is the discrete WLAN module's USB Bluetooth. + This board uses CNVi (BT on cnvi_bluetooth, PCI 14.7), + so leave it off; uncomment for a discrete module. */ + /* [7] = USB2_PORT_MID(OC_SKIP), */ + }" + # USB3: Type-C SS is via TCSS; PCH USB3 for DCI debug + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref xhci_root_hub on + # USB2 lines of the Type-C connectors + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 0))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC2)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC3)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 0))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C (JUSBC4)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + # Internal devices (not user-visible) + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + # Discrete-module Bluetooth (USB). Off because this board + # uses CNVi (BT is on cnvi_bluetooth, PCI 14.7). Enable + # only when fitting a discrete WLAN module (e.g. AX210). + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 off end + end + end + end + end + + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end + device ref cnvi_bluetooth on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + + end + + device ref pmc_shared_sram on end + + # Configuring Touchpad, Touchscreen as I2C instead of THC + device ref thc0 off end + device ref thc1 off end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FRMW0004"" + register "generic.desc" = ""EC Mediakeys"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B05)" + register "hid_desc_reg_offset" = "0x55" + device i2c 50 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FRMW0005"" + register "generic.desc" = ""EC ALS"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D06_IRQ)" + register "hid_desc_reg_offset" = "0x55" + device i2c 51 on end + end + end + + device ref i2c3 on + # Power monitor (PAC1954T) - not populated on mass production + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + + device ref i2c4 on + # Touchscreen (shares pins with THC0) + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""CSW1322"" + register "generic.desc" = ""Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_E18)" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on end + end + end + + device ref i2c5 on + # Touchpad (shares pins with THC1) + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""PIXA3854"" + register "generic.desc" = ""Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F18)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + + # WLAN M.2 Key-E (J_WLAN1). This board ships an Intel CNVi module + # (BE211): WiFi is on cnvi_wifi (CNVio) and BT on cnvi_bluetooth + # (PCI 14.7), so the discrete PCIe path and the discrete USB2 BT + # port are both disabled. To support a discrete module (e.g. AX210) + # instead, enable pcie_rp4 + usb2_port8 and disable cnvi_*. + device ref pcie_rp4 off + register "pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + + device ref pcie_rp9 on + # SSD M.2 NVMe: PCIe x4, Gen5 + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 15, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "1" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + + # BIOS/OS console + device ref uart0 on + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoSkipInit" + end + + device ref soc_espi on + # EC host command ranges: 0x200-0x20f + register "gen1_dec" = "0x000c0201" + # EC memory range: 0xE00-0xEFF + register "gen2_dec" = "0x00fc0e01" + # EC extended range: 0xF00-0xFFF + register "gen3_dec" = "0x00fc0f01" + # EC NPCX shared memory: 0x800-0x8FF + register "gen4_dec" = "0x00fc0801" + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + + chip drivers/crb + device mmio 0xfed40000 on end + end + + device ref hda on + # Enable HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + + device ref smbus on end + end +end diff --git a/src/mainboard/framework/sakura/dsdt.asl b/src/mainboard/framework/sakura/dsdt.asl new file mode 100644 index 00000000000..201b818e8c9 --- /dev/null +++ b/src/mainboard/framework/sakura/dsdt.asl @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +// HACK: MISCCFG_GPIO_PM_CONFIG_BITS are missing +#include +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20240917 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + #include + #include + } + + #include + + /* Framework EC over eSPI */ + Scope (\_SB.PCI0.LPCB) + { + /* PS/2 keyboard + mouse, and EC host-command/memmap I/O reservations */ + #include + /* EC0: lid switch, AC adapter, battery, cros_ec command device */ + #include + } + + /* + * Clear ACPI driver ready before entering suspend, same as the vendor + * firmware, so the EC returns to preOS mode across the power transition. + */ + Method (\_SB.MPTS, 1, Serialized) + { + If (Arg0) { + \_SB.PCI0.LPCB.EC0.ADRD = 0 + } + } + + /* + * Signal ACPI driver ready to EC again, after resume from suspend, + * same as on boot, to make sure function keys, etc. are working. + */ + Method (\_SB.MWAK, 1, Serialized) + { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + \_SB.PCI0.LPCB.EC0.ADRD = 1 + } + } +} diff --git a/src/mainboard/framework/sakura/ec.c b/src/mainboard/framework/sakura/ec.c new file mode 100644 index 00000000000..4d06e824de1 --- /dev/null +++ b/src/mainboard/framework/sakura/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/framework/sakura/fadt.c b/src/mainboard/framework/sakura/fadt.c new file mode 100644 index 00000000000..0621f4396ef --- /dev/null +++ b/src/mainboard/framework/sakura/fadt.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->flags |= ACPI_FADT_POWER_BUTTON; +} diff --git a/src/mainboard/framework/sakura/gpio.c b/src/mainboard/framework/sakura/gpio.c new file mode 100644 index 00000000000..0062740a998 --- /dev/null +++ b/src/mainboard/framework/sakura/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * GPIO configuration from vendor firmware dump (inteltool -G). + * + * Manually double-checked every pad name based on 3/16 schematic (Daniel Schaefer) + */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPP_V - Power Management ------- */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), /* BATLOW#, 10k pull high to 1.8V_PRIM (unused?) */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), /* AC_PRESENT, 10k pull high to 1.8V_PRIM, input from EC */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), /* SOC_WAKE# / LAN_WAKE#, 10k pull high to 1.8V_PRIM (unused?) */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# / PBTN_OUT#, 1k pull high to 1.8_PRIM, input from EC GPIO50 */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), /* SUSCLK (suspend clock, out) */ + PAD_NC(GPP_V08, NONE), + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_S5# */ + PAD_NC(GPP_V10, NONE), + PAD_NC(GPP_V11, NONE), /* SLP_LAN# NC, just TP18 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V12, NONE, DEEP, NF1), /* WAKE# / SOC_WL_WAKE# (1.8V level) */ + PAD_NC(GPP_V13, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_V14, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_V15, NONE), /* Does not exist on schematic */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), /* VCCST_EN (VCC sustain) */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), /* RT_GPIO6_CTRL_CPU (pulled high to 1.8VS via 10k and GND via 100k, to Retimer) */ + + /* ------- GPP_C - SMBus, CLKREQs, TBT ------- */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C00, NONE, DEEP, NF1), /* SMBCLK (LPCAMM2) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C01, NONE, DEEP, NF1), /* SMBDATA (LPCAMM2) */ + PAD_CFG_GPI(GPP_C02, NONE, DEEP), /* TLS strap (active high, ext pull-up) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C03, NONE, DEEP, NF1), /* SML0CLK (TBT) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C04, NONE, DEEP, NF1), /* SML0DATA (TBT) */ + PAD_CFG_GPI(GPP_C05, NONE, DEEP), /* eSPI strap (enable low, ext pull-down) */ + PAD_NC(GPP_C06, NONE), + PAD_NC(GPP_C07, NONE), + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), /* SML1_ALERT# (10k to 1.8V_PRIM) */ + PAD_NC(GPP_C09, NONE), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* SRCCLKREQ1# (SSD) */ + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* SRCCLKREQ4# (WLAN) */ + PAD_NC(GPP_C14, NONE), + PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* strap (must not drive, ext pull-down) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* TBT_LSX2_TXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TBT_LSX2_RXD */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* TBT_LSX3_TXD */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* TBT_LSX3_RXD */ + + /* ------- GPP_F - CNVi ------- */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), /* CLKREQ_CNV */ + PAD_NC(GPP_F06, NONE), + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), /* RSVD_GPP_F08 (TP41) */ + PAD_NC(GPP_F09, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* SOC_TP_I2C_1_SCL (Touchpad) */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* SOC_TP_I2C_1_SDA (Touchpad) */ + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPI_INT(GPP_F18, NONE, DEEP, LEVEL), /* SOC_TP_I2C_1_INT# (Touchpad, GpioInt) */ + PAD_NC(GPP_F19, NONE), /* GPP_F19_STRAP (1.8V_PRIM) */ + PAD_NC(GPP_F20, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPP_E ------- */ + PAD_NC(GPP_E00, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_E01, NONE), + PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2), /* VRALERT# / H_PROCHOT# (2.2k to 1.8V_PRIM) */ + PAD_CFG_GPO(GPP_E03, 1, DEEP), /* RTD3_SSD_PLT_RST# */ + PAD_NC(GPP_E04, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_E05, NONE), + PAD_NC(GPP_E06, NONE), /* GPP_E06_STRAP (floating) */ + PAD_NC(GPP_E07, NONE), + PAD_NC(GPP_E08, NONE), + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), /* USB_OC0# (input from PD) */ + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* SOC_TS_I2C_0_CLK (THC0 I2C CLK Touchscreen) */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* SOC_TS_I2C_0_SDA (THC0 I2C SDA Touchscreen) */ + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* SOC_TS_0_RST (TS_RST# Touch screen reset, active low, 10k to 1.8VS) */ + PAD_NC(GPP_E17, NONE), + PAD_CFG_GPI_INT(GPP_E18, NONE, DEEP, LEVEL), /* SOC_TS_I2C_0_INT# (touchscreen HID interrupt, GpioInt) */ + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* SOC_PD_INT#_R / PMCALERT# */ + PAD_NC(GPP_E22, NONE), + + /* ------- GPP_H - UART, I2C ------- */ + /* MAFS = Host attached Flash Sharing, SAFS = Device Attached Flash Sharing (SAFS) */ + PAD_NC(GPP_H00, NONE), /* GPP_H00_STRAP (internal pulldown, low = MAFS, high = SAFS) */ + PAD_NC(GPP_H01, NONE), /* GPP_H01_STRAP (internal pulldown, high = flash descriptor recovery) */ + PAD_NC(GPP_H02, NONE), /* GPP_H02_STRAP (reserved)*/ + PAD_NC(GPP_H03, NONE), + PAD_NC(GPP_H04, NONE), + PAD_NC(GPP_H05, NONE), + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* I2C3_SDA (PAC1954 Power Monitor, NP in MP, 4.7k to 1.8VS) */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* I2C3_SCL (PAC1954 Power Monitor, NP in MP, 4.7k to 1.8VS) */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD (CPU/PCH UART console) */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD (CPU/PCH UART console) */ + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), /* Does not exist on schematic */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* CPU_C10_GATE# (10k to 1.8V_PRIM) */ + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* SOC_I2C_1_SDA (I2C1_SDA EC HID) */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* SOC_I2C_1_SCL (I2C1_SCL EC HID) */ + + /* ------- GPP_A - eSPI ------- */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A07, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_A08, NONE), + PAD_NC(GPP_A09, NONE), + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPO(GPP_A11, 1, DEEP), /* RTD3_WLAN_PLT_RST# (10k to 1.8VS) */ + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), /* Does not exist on schematic */ + PAD_NC(GPP_A15, NONE), /* EPD_ON_GCD_OUT (Connected to EPD_ON_GCD_IN) */ + PAD_CFG_GPO(GPP_A16, 1, DEEP), /* SOC_BT_ON (10k to 1.8V_PRIM) */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), /* SOC_WL_OFF# (10k to 1.8V_PRIM) */ + + /* ------- GPP_S - SoundWire / DMIC ------- */ + /* TODO: Need to check if this is needed, I think didn't stuff these and DMIC is connected to HDA codec only */ + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), /* PCH_DMIC_CLK_R (BT Offload) */ + PAD_NC(GPP_S03, NONE), /* PCH_DMIC_DATA_R (BT Offload) */ + PAD_NC(GPP_S04, NONE), /* WLAN_PCM_CLK_R (BT Offload) */ + PAD_NC(GPP_S05, NONE), /* WLAN_PCM_FRM (BT Offload) */ + PAD_NC(GPP_S06, NONE), /* WLAN_PCM_OUT_R (BT Offload) */ + PAD_NC(GPP_S07, NONE), /* WLAN_PCM_IN_R (BT Offload) */ + + /* ------- GPP_B - Platform ------- */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), /* SOC_USBC_SMLCLK (2.2k to 1.8V_PRIM, PD 1/2) */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), /* SOC_USBC_SMLDATA (2.2k to 1.8V_PRIM, PD 1/2) */ + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_NC(GPP_B04, NONE), /* ME_EN (high = override flash descriptor security, input from EC) */ + PAD_CFG_GPI_INT(GPP_B05, NONE, DEEP, LEVEL), /* SOC_EC_INT1# (EC keyboard interrupt, GpioInt) */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), /* LPCAMM_ERROR (LED) TODO: This should be triggered if memory training failed. */ + PAD_NC(GPP_B07, NONE), + PAD_NC(GPP_B08, NONE), + PAD_NC(GPP_B09, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# / SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SOC_PLTRST# / PLTRST# */ + PAD_NC(GPP_B14, NONE), /* TOP_SW AP_EN_STRAP (Inverts an address on access to SPI, so the alternate boot block is fetched instead of the original boot-block) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PD2_OC3# / USB_OC3# */ + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 1, DEEP), /* SOC_TS_0_EN (touch screen enable) */ + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_CFG_GPO(GPP_B21, 0, DEEP), /* SOC_RT_FORCE_PW (retimer power) TODO: Triggered for retimer firmware update */ + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), /* GPP_B23_STRAP (Reserved, 1.8V_PRIM) */ + PAD_NC(GPP_B24, NONE), + PAD_NC(GPP_B25, NONE), + + /* ------- GPP_D - HDA, EC sensors ------- */ + PAD_NC(GPP_D00, NONE), + PAD_NC(GPP_D01, NONE), + PAD_NC(GPP_D02, NONE), + PAD_NC(GPP_D03, NONE), + PAD_NC(GPP_D04, NONE), + PAD_CFG_GPO(GPP_D05, 1, DEEP), /* SOC_SSD_PWR_EN (active high, 100k pull-down) */ + PAD_CFG_GPI_APIC(GPP_D06, NONE, DEEP, LEVEL, INVERT), /* SOC_EC_INT2# (EC ALS sensor interrupt) */ + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), + PAD_NC(GPP_D09, NONE), + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO / HDA_SDOUT / GPP_D12_STRAP (1 = no reboot, processor disabled TCO timer system reboot) */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 / HDA_SDIN0 */ + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + PAD_NC(GPP_D24, NONE), + PAD_NC(GPP_D25, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/framework/sakura/gpio_early.c b/src/mainboard/framework/sakura/gpio_early.c new file mode 100644 index 00000000000..cdb5257f0e8 --- /dev/null +++ b/src/mainboard/framework/sakura/gpio_early.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* UART0 for console */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + + /* SMBus for DDR5 SPD */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* SMBDATA */ +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/framework/sakura/hda_verb.c b/src/mainboard/framework/sakura/hda_verb.c new file mode 100644 index 00000000000..09b46c6d9bf --- /dev/null +++ b/src/mainboard/framework/sakura/hda_verb.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const u32 realtek_alc285_verbs[] = { + /* + * Verb table reproduced 1:1 from the vendor reference table. + * The internal speaker is driven via NID 0x17 (I2S OUT) into an + * external ALC1320 Class-D amplifier + */ + AZALIA_SUBVENDOR(0, 0xf111000f), + AZALIA_RESET(1), + + /* Pin widget configuration (matches vendor reference table) */ + /* DMIC - Internal Mic */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), /* DMIC - NC */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), /* Front (Port-D) - NC */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), /* NPC */ + /* I2S OUT - Internal Speaker (ALC1320) */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* I2S IN */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* NPC */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* LINE2 (Port-E) */ + AZALIA_PIN_CFG(0, 0x1d, 0x40651b05), /* BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* S/PDIF-OUT */ + /* HP1-OUT (Port-I) - Headphone Jack */ + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + + /* Reset power state to D0 */ + 0x00170500, 0x00170500, 0x00170500, 0x00170500, + + /* Reset all registers back to default */ + 0x0205001a, 0x02048003, 0x0205001a, 0x0204c003, + + /* ClassD reset */ + 0x0205003c, 0x0204f2d4, 0x0205003c, 0x0204f214, + + /* JD1 - 2port JD mode */ + 0x02050009, 0x0204e003, 0x0205000a, 0x02047770, + + /* Set TRS type-1 */ + 0x02050045, 0x0204c689, 0x02050049, 0x02040049, + + /* Set TRS type-2 (Turn off MIC2_Vrefo_R_L) + Set UAJ Line2 vref (ALC285 only) */ + 0x0205004a, 0x0204a830, 0x02050063, 0x02040f00, + + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + Set sine tone gain(0x34) */ + 0x02050038, 0x02047909, 0x05c50000, 0x05c43482, + + /* HP-JD Enable+ For Nokia type (+power down JD2) ( item 23) */ + 0x0205004a, 0x02042010, 0x02050008, 0x02046a2c, + + /* EAPD set to verb-control */ + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + + /* Class D silent detection enable -84dB threshold */ + 0x02050030, 0x02049000, 0x02050037, 0x0204fe15, + + /* > Reserve EAPD and Set GPIO2 as GPIO */ + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + + /* ALC3254 pin1 I2S/OE pull down to Enable NID17 */ + 0x02050035, 0x02048d6a, 0x02050035, 0x02048d6a, + + /* I2S output buffer enable */ + 0x00170500, 0x01770500, 0x01770740, 0x01770740, + + /* ALC1320 Class-D smart-amp firmware blob */ +#include "alc1320_smartamp.inc" +}; + +static const u32 intel_ptl_hdmi_verbs[] = { + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC285", + .vendor_id = 0x10ec0285, + .subsystem_id = 0xf111000f, + .address = 0, + .verbs = realtek_alc285_verbs, + .verb_count = ARRAY_SIZE(realtek_alc285_verbs), + }, + { + .name = "Intel Panther Lake HDMI", + .vendor_id = 0x80862822, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_ptl_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_ptl_hdmi_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/framework/sakura/include/mainboard/bootblock.h b/src/mainboard/framework/sakura/include/mainboard/bootblock.h new file mode 100644 index 00000000000..f7a9a294f8d --- /dev/null +++ b/src/mainboard/framework/sakura/include/mainboard/bootblock.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_BOOTBLOCK_H +#define MAINBOARD_BOOTBLOCK_H + +void mainboard_configure_early_gpios(void); + +#endif /* MAINBOARD_BOOTBLOCK_H */ diff --git a/src/mainboard/framework/sakura/include/mainboard/ec.h b/src/mainboard/framework/sakura/include/mainboard/ec.h new file mode 100644 index 00000000000..b3c4845e32b --- /dev/null +++ b/src/mainboard/framework/sakura/include/mainboard/ec.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include +#include + +/* + * EC events that the Framework CrosEC fork raises as SCIs + * Does NOT include Chromebook events like MKBP, PD_MCU, ... + */ +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)) +#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with power button only */ +#define MAINBOARD_EC_S5_WAKE_EVENTS EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) +/* EC can additionally wake from S3/S0ix on AC change and critical battery */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS MAINBOARD_EC_S3_WAKE_EVENTS +/* Log EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* ACPI feature toggles to enable EC eSPI, lid and wake */ +#define EC_SCI_GPI GPE0_ESPI +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_POWER_BUTTON +#define EC_ENABLE_WAKE_PIN GPE0_ESPI + +/* + * Enable standard PS2 keyboard (not e.g. Chrome Vivaldi) + * Also when the OS has no I2C HID driver (e.g. Windows installer), the EC + * presents an emulated PS2 mouse interface to allow using the touchpad. + */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_ENABLE_PS2M /* Enable PS/2 Mouse */ + +/* + * Framework ACPI shared memory with the EC + * + * Contains a couple of flags and up-to-date system information. + */ +#define EC_FRAMEWORK_ACPI_SHARED_MEM_IO 0xF00 + +#endif /* MAINBOARD_EC_H */ diff --git a/src/mainboard/framework/sakura/include/mainboard/ramstage.h b/src/mainboard/framework/sakura/include/mainboard/ramstage.h new file mode 100644 index 00000000000..a8d3d9956e5 --- /dev/null +++ b/src/mainboard/framework/sakura/include/mainboard/ramstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_RAMSTAGE_H +#define MAINBOARD_RAMSTAGE_H + +void mainboard_configure_gpios(void); + +#endif /* MAINBOARD_RAMSTAGE_H */ diff --git a/src/mainboard/framework/sakura/ramstage.c b/src/mainboard/framework/sakura/ramstage.c new file mode 100644 index 00000000000..cbb97c8a2d2 --- /dev/null +++ b/src/mainboard/framework/sakura/ramstage.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* + * Disable C10 reporting over eSPI to prevent LED flicker + * during S0ix entry/exit on laptops. + */ + params->PchEspiHostC10ReportEnable = 0; + + /* Auto-notify iGPU of display changes on USB-C (for hotplug) */ + params->TcNotifyIgd = 2; + + /* + * CNVi RF_RESET# and CLKREQ routed to GPP_F04/GPP_F05, not the FSP + * default of GPP_A8/GPP_A9, see FspsUpd.h for defaults and values. + */ + params->CnviRfResetPinMux = 0x194CE404; /* GPP_F04 */ + params->CnviClkreqPinMux = 0x394CE605; /* GPP_F05 */ +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); + mainboard_ec_init(); +} + +struct chip_operations mainboard_ops = {.init = mainboard_init}; diff --git a/src/mainboard/framework/sakura/romstage.c b/src/mainboard/framework/sakura/romstage.c new file mode 100644 index 00000000000..5cd65ea06f2 --- /dev/null +++ b/src/mainboard/framework/sakura/romstage.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* + * LPDDR5x LPCAMM2 module, use same config as camm_t3_mem_config on ptl_rvp + */ +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 3, 1, 2, 6, 7, 4, 5 }, + .dq1 = { 13, 12, 15, 14, 8, 10, 11, 9 }, + }, + .ddr1 = { + .dq0 = { 8, 10, 11, 9, 13, 15, 14, 12 }, + .dq1 = { 5, 7, 6, 4, 3, 2, 1, 0 }, + }, + .ddr2 = { + .dq0 = { 1, 3, 0, 2, 6, 7, 5, 4 }, + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, + }, + .ddr3 = { + .dq0 = { 14, 15, 12, 13, 10, 8, 11, 9 }, + .dq1 = { 4, 6, 7, 5, 1, 3, 0, 2 }, + }, + .ddr4 = { + .dq0 = { 3, 0, 2, 1, 6, 7, 4, 5 }, + .dq1 = { 13, 12, 15, 14, 8, 10, 11, 9 }, + }, + .ddr5 = { + .dq0 = { 10, 8, 11, 9, 13, 15, 12, 14 }, + .dq1 = { 2, 1, 3, 0, 7, 6, 5, 4 }, + }, + .ddr6 = { + .dq0 = { 3, 1, 2, 0, 5, 7, 4, 6 }, + .dq1 = { 12, 14, 15, 13, 9, 10, 11, 8 }, + }, + .ddr7 = { + .dq0 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + .dq1 = { 5, 6, 7, 4, 2, 1, 3, 0 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0x55, + }, + }; + + const struct mem_spd spd_info = { + .topo = MEM_TOPO_LP5_CAMM, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x50, }, + [2] = { .addr_dimm[0] = 0x50, }, + [3] = { .addr_dimm[0] = 0x50, }, + [4] = { .addr_dimm[0] = 0x50, }, + [5] = { .addr_dimm[0] = 0x50, }, + [6] = { .addr_dimm[0] = 0x50, }, + [7] = { .addr_dimm[0] = 0x50, }, + }, + }; + + const bool half_populated = false; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/framework/sakura/smihandler.c b/src/mainboard/framework/sakura/smihandler.c new file mode 100644 index 00000000000..25d07735fa1 --- /dev/null +++ b/src/mainboard/framework/sakura/smihandler.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 75f736a6b8d..0e928ef83c2 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 4b0ea16aa90..b8b992251d0 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include diff --git a/src/mainboard/google/asurada/Makefile.mk b/src/mainboard/google/asurada/Makefile.mk index 63073bcbf7c..56b2102590c 100644 --- a/src/mainboard/google/asurada/Makefile.mk +++ b/src/mainboard/google/asurada/Makefile.mk @@ -24,3 +24,5 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += regulator.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 647555a3391..2414bfd9445 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index d8787f63a22..c6e83ba1cb0 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/asurada/gpio.h rename to src/mainboard/google/asurada/include/baseboard/gpio.h diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 6a0d433ca45..058b1d59f99 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -21,8 +22,6 @@ #include #include -#include "gpio.h" - #define MSDC0_BASE 0x11f60000 #define MSDC0_TOP_BASE 0x11f50000 @@ -113,7 +112,7 @@ static bool configure_display(void) MIPI_DSI_MODE_LINE_END | MIPI_DSI_MODE_EOT_PACKET); - if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) { + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL, NULL) < 0) { printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); return false; } diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c index 91ee7c074de..7622a7f32c2 100644 --- a/src/mainboard/google/asurada/reset.c +++ b/src/mainboard/google/asurada/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_RESET, 1); diff --git a/src/mainboard/google/atria/Kconfig b/src/mainboard/google/atria/Kconfig new file mode 100644 index 00000000000..e9c575233ca --- /dev/null +++ b/src/mainboard/google/atria/Kconfig @@ -0,0 +1,113 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GOOGLE_ATRIA_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_OTHER + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX + select DUMP_SMBIOS_TYPE17 + select EC_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC + select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + select GENERATE_SMBIOS_TABLES + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select I2C_TPM + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_DISABLE_STAGE_CACHE + select MB_COMPRESS_RAMSTAGE_LZ4 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_NOVALAKE_H_P + select TPM_GOOGLE_TI50 + +config BOARD_GOOGLE_BASEBOARD_ATRIA + def_bool n + select BOARD_GOOGLE_ATRIA_COMMON + select MAINBOARD_HAS_CHROMEOS + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_ATRIA + select BOARD_GOOGLE_BASEBOARD_ATRIA + select EC_GOOGLE_CHROMEEC_RTK + select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE + +config BOARD_GOOGLE_PENGHU + select BOARD_GOOGLE_BASEBOARD_ATRIA + +if BOARD_GOOGLE_ATRIA_COMMON + +config BASEBOARD_DIR + string + default "atria" + +config CBFS_SIZE + default 0x1000000 + +config CHROMEOS + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config DRIVER_TPM_I2C_BUS + hex + default 0x02 + +config MAINBOARD_DIR + default "google/atria" + +config MAINBOARD_FAMILY + string + default "Google_Atria" + +config MAINBOARD_PART_NUMBER + default "Atria" if BOARD_GOOGLE_ATRIA + +config VARIANT_DIR + string + default "atria" if BOARD_GOOGLE_ATRIA + default "penghu" if BOARD_GOOGLE_PENGHU + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config TPM_TIS_ACPI_INTERRUPT + int + default 48 # GPE0_DW1_16 (GPP_F16) + +config UART_FOR_CONSOLE + int + default 0 + +config VBOOT + select VBOOT_LID_SWITCH + +config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE + hex + default 0xfe400000 + +endif # BOARD_GOOGLE_ATRIA_COMMON diff --git a/src/mainboard/google/atria/Kconfig.name b/src/mainboard/google/atria/Kconfig.name new file mode 100644 index 00000000000..d837ec9c7c6 --- /dev/null +++ b/src/mainboard/google/atria/Kconfig.name @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "Atria (Intel NovaLake)" + +config BOARD_GOOGLE_ATRIA + bool "-> Atria" + +config BOARD_GOOGLE_PENGHU + bool "-> Penghu" diff --git a/src/mainboard/google/atria/Makefile.mk b/src/mainboard/google/atria/Makefile.mk new file mode 100644 index 00000000000..c69ad6bf2b2 --- /dev/null +++ b/src/mainboard/google/atria/Makefile.mk @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage.c + +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += variants/$(VARIANT_DIR)/memory +LIB_SPD_DEPS = $(SPD_SOURCES) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/myst/board_info.txt b/src/mainboard/google/atria/board_info.txt similarity index 83% rename from src/mainboard/google/myst/board_info.txt rename to src/mainboard/google/atria/board_info.txt index 2969e6ece86..a6b8b1d0005 100644 --- a/src/mainboard/google/myst/board_info.txt +++ b/src/mainboard/google/atria/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Myst +Board name: Atria Category: laptop ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/atria/bootblock.c b/src/mainboard/google/atria/bootblock.c new file mode 100644 index 00000000000..4f44b2ccd85 --- /dev/null +++ b/src/mainboard/google/atria/bootblock.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +void bootblock_mainboard_init(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)) + lpc_open_mmio_window(CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE, + CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE); + +} diff --git a/src/mainboard/google/atria/chromeos.c b/src/mainboard/google/atria/chromeos.c new file mode 100644 index 00000000000..e6ef99fe5fe --- /dev/null +++ b/src/mainboard/google/atria/chromeos.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} + +int get_ec_is_trusted(void) +{ + /* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */ + return 0; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/atria/chromeos.fmd b/src/mainboard/google/atria/chromeos.fmd new file mode 100644 index 00000000000..c5313cb7b33 --- /dev/null +++ b/src/mainboard/google/atria/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 8M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + # This section starts at the 16M boundary in SPI flash. + # NVL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 160K { + RECOVERY_MRC_CACHE 80K + RW_MRC_CACHE 80K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/atria/dsdt.asl b/src/mainboard/google/atria/dsdt.asl new file mode 100644 index 00000000000..8f82f785f59 --- /dev/null +++ b/src/mainboard/google/atria/dsdt.asl @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20240917 +) +{ + #include + #include + + /* global NVS and variables */ + #include + + #include + + Device (\_SB.PCI0) { + #include + #include + } + + /* ChromeOS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } + + #include +} diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/atria/ec.c similarity index 51% rename from src/mainboard/google/myst/ec.c rename to src/mainboard/google/atria/ec.c index 060119dc3c9..f828bc55477 100644 --- a/src/mainboard/google/myst/ec.c +++ b/src/mainboard/google/atria/ec.c @@ -1,24 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include +#include +#include #include -#include -#include #include -static const struct sci_source espi_sci_sources[] = { - { - .scimap = SMITYPE_ESPI_SCI_B, - .gpe = EC_SCI_GPI, - .direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */ - .level = SMI_SCI_EDG, /* enum smi_sci_dir */ - } -}; - void mainboard_ec_init(void) { - const struct google_chromeec_event_info info = { + static const struct google_chromeec_event_info info = { .log_events = MAINBOARD_EC_LOG_EVENTS, .sci_events = MAINBOARD_EC_SCI_EVENTS, .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, @@ -26,8 +16,7 @@ void mainboard_ec_init(void) .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, }; - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + printk(BIOS_DEBUG, "mainboard: EC init\n"); - /* Configure eSPI SCI events */ - gpe_configure_sci(espi_sci_sources, ARRAY_SIZE(espi_sci_sources)); + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); } diff --git a/src/mainboard/google/atria/mainboard.c b/src/mainboard/google/atria/mainboard.c new file mode 100644 index 00000000000..89a828d9a86 --- /dev/null +++ b/src/mainboard/google/atria/mainboard.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + /* default implementation does nothing */ +} + +static void mainboard_init(void *chip_info) +{ + mainboard_ec_init(); +} + +static void mainboard_early(void *unused) +{ + struct pad_config *padbased_table; + const struct pad_config *base_pads; + size_t base_num; + + padbased_table = new_padbased_table(); + base_pads = variant_gpio_table(&base_num); + gpio_padbased_override(padbased_table, base_pads, base_num); + fw_config_gpio_padbased_override(padbased_table); + gpio_configure_pads_with_padbased(padbased_table); + free(padbased_table); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL); + +static void mainboard_fill_ssdt(const struct device *dev) +{ + /* TODO: Add mainboard specific SSDT */ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/atria/romstage.c b/src/mainboard/google/atria/romstage.c new file mode 100644 index 00000000000..93c91f03c8a --- /dev/null +++ b/src/mainboard/google/atria/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* + * Placeholder to configure GPIO early from romstage relying on the FW_CONFIG. + * + * If any platform would like to override early GPIOs, they should override from + * the variant directory. + */ +__weak void fw_config_configure_pre_mem_gpio(void) +{ + /* Nothing to do */ +} + +__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + /* Nothing to do */ +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t pads_num; + const struct mb_cfg *mem_config = variant_memory_params(); + bool half_populated = variant_is_half_populated(); + struct mem_spd spd_info; + + pads = variant_romstage_gpio_table(&pads_num); + if (pads_num) + gpio_configure_pads(pads, pads_num); + fw_config_configure_pre_mem_gpio(); + + memset(&spd_info, 0, sizeof(spd_info)); + variant_get_spd_info(&spd_info); + + memcfg_init(memupd, mem_config, &spd_info, half_populated); + + /* Override FSP-M UPD per board if required. */ + variant_update_soc_memory_init_params(memupd); +} diff --git a/src/mainboard/google/atria/variants/atria/Makefile.mk b/src/mainboard/google/atria/variants/atria/Makefile.mk new file mode 100644 index 00000000000..f4b5d45f774 --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/atria/variants/atria/fw_config.c b/src/mainboard/google/atria/variants/atria/fw_config.c new file mode 100644 index 00000000000..2303f77d07e --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/fw_config.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* t: base table; o: override table */ +#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o)) +/* t: table */ +#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) + +static const struct pad_config pre_mem_gen4_ssd_pads[] = { + /* GPP_B10: SOC_M2_GEN4_SSD3_PWREN */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), +}; + +static const struct pad_config pre_mem_gen5_ssd_pads[] = { + /* GPP_E04: SOC_M2_GEN5_SSD2_PWREN */ + PAD_CFG_GPO(GPP_E04, 1, DEEP), +}; + +static const struct pad_config gen4_ssd_pads[] = { + /* GPP_B10: SOC_M2_GEN4_SSD3_PWREN */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), + /* GPP_A11: SOC_M2_GEN4_SSD3_RESET_N */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), +}; + +static const struct pad_config gen5_ssd_pads[] = { + /* GPP_E04: SOC_M2_GEN5_SSD2_PWREN */ + PAD_CFG_GPO(GPP_E04, 1, DEEP), + /* GPP_E03: SOC_M2_GEN5_SSD2_RESET_N */ + PAD_CFG_GPO(GPP_E03, 1, DEEP), +}; + +static const struct pad_config ufs_enable_pads[] = { + /* GPP_B25: UFS_RST_N */ + PAD_CFG_GPO(GPP_B25, 1, DEEP), + /* GPP_D21: GPP_D21_UFS_REFCLK */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +}; + +void fw_config_configure_pre_mem_gpio(void) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned\n"); + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pads); + return; + } + + if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME_GEN4))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME_GEN5))) { + GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pads); + } +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); + return; + } + + if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME_GEN4))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME_GEN5))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_UFS))) { + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); + } +} diff --git a/src/mainboard/google/atria/variants/atria/gpio.c b/src/mainboard/google/atria/variants/atria/gpio.c new file mode 100644 index 00000000000..6ac6cb11edc --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/gpio.c @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + + /* GPP_A */ + /* GPP_A00: ESPI_IO0_AIC */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + /* GPP_A01: ESPI_IO1_AIC */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + /* GPP_A02: ESPI_IO2_AIC */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + /* GPP_A03: ESPI_IO3_AIC */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + /* GPP_A04: ESPI_CS0_AIC_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + /* GPP_A05: ESPI_CLK_AIC */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + /* GPP_A06: ESPI_RST_AIC_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + /* GPP_A07: SECURE_CAM_SW_R */ + PAD_CFG_GPI_TRIG_OWN(GPP_A07, NONE, PLTRST, LEVEL, ACPI), + /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 1, DEEP), + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), + /* GPP_A10: WLAN_RST_N */ + PAD_CFG_GPO(GPP_A10, 1, PLTRST), + /* GPP_A11: SOC_M2_GEN4_SSD3_RESET_N */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A13: PM_SLP_S0_N_GPP_CNTRL */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* GPP_A14: ESPI_ALERT3_AIC_N */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + /* GPP_A16: Not used */ + PAD_NC(GPP_A16, NONE), + /* GPP_A17: ESPI_CS3_AIC_N */ + PAD_NC(GPP_A17, NONE), + + /* GPP_B */ + /* GPP_B00: MOD_TCSS0_PD_PMC_SCL */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: MOD_TCSS0_PD_PMC_SDA */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: ISH_I3C0_SDA_SNSR_HDR_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF1), + /* GPP_B03: ISH_I3C0_SCL_SNSR_HDR_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF1), + /* GPP_B04: ISH_GP_0_SNSR_HDR */ + PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4), + /* GPP_B05: ISH_GP_1_SNSR_HDR */ + PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), + /* GPP_B06: ISH_GP_2_SNSR_HDR */ + PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4), + /* GPP_B07: ISH_GP_3_SNSR_HDR */ + PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), + /* GPP_B08: ISH_GP_4_SNSR_HDR */ + PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), + /* GPP_B09: FPS_RST_N; not used */ + PAD_NC(GPP_B09, NONE), + /* GPP_B10: SOC_M2_GEN4_SSD3_PWREN */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + /* GPP_B11: SOC_PDB_CTRL */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + /* GPP_B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: DDSP_HDMI_HPD4 */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* GPP_B15: MOD_TCSS_USB_TYP_A_OC3_N */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* GPP_B17: MOD_TCSS0_EDP_VDD_EN */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: M.2_WWAN_RST_N */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), + /* GPP_B24: ESPI_ALERT0_AIC_N */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25: UFS_RST_N */ + PAD_CFG_GPO(GPP_B25, 0, DEEP), + + /* GPP_C */ + /* GPP_C03: TCP_LAN_SML0_SCL_R */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04: TCP_LAN_SML0_SDA_R */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05: CRD1_PWREN */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_C06: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_C06, NONE, DEEP, LEVEL), + /* GPP_C07: X1_SLOT_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_C07, NONE, DEEP, LEVEL), + /* GPP_C08: CRD2_PWREN */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + /* GPP_C09: SOC_CLKREQ0_GEN5_SSD2_N */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C10: CLKREQ1_X1_GEN4_DT_CEM_SLOT_N */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + /* GPP_C11: CLKREQ2_X1_GEN4_M2_WLAN_N */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: CLKREQ3_X1_GEN4_M2_WWAN_N */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13: CLKREQ4_X4_GEN4_M2_SSD3_N */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* GPP_C15: SOC_PCIE_LNK_DOWN */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF3), + /* GPP_C16: MOD_TCSS0_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: MOD_TCSS0_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: MOD_TCSS1_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19: MOD_TCSS1_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20: MOD_TCSS2_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: MOD_TCSS2_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22: GPP_C22_DDP4_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: GPP_C23_DDP4_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + + /* GPP_D */ + /* GPP_D00: IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), + /* GPP_D01: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02: SOC_WP_OD */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), + /* GPP_D03: GPP_D3_PCH_IOE_MODE_EN */ + PAD_NC(GPP_D03, NONE), + /* GPP_D04: IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), + /* GPP_D05: ISH_SPI_CS_N_SNSR_HDR */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF1), + /* GPP_D06: ISH_SPI_CLK_SNSR_HDR */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF1), + /* GPP_D07: ISH_SPI_MISO_SNSR_HDR */ + PAD_CFG_NF(GPP_D07, NONE, DEEP, NF1), + /* GPP_D08: ISH_SPI_MOSI_SNSR_HDR */ + PAD_CFG_NF(GPP_D08, NONE, DEEP, NF1), + /* GPP_D09: PEG_SLOT_RST_N */ + PAD_CFG_GPO(GPP_D09, 1, PLTRST), + /* GPP_D10: HDA_BCLK_I2S0_SCLK_HDR */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11: HDA_SYNC_I2S0_SFRM_HDR */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* GPP_D12: HDA_SDO_I2S0_TXD_HDR */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: HDA_SDI0_I2S0_RXD_HDR */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D16: HDA_RST_N_HDR */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + /* GPP_D17: HDA_SDI1_HDR */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D18: CLKREQ6_X8_GEN5_DT_CEM_SLOT_N */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D20: CLKREQ7_X4_GEN5_M2_SSD_N */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21: GPP_D21_UFS_REFCLK */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), + /* GPP_D22: M.2_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D22, 1, PLTRST), + /* GPP_D23: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_D23, 1, DEEP), + + /* GPP_E */ + /* GPP_E01: VDDQ_DVFSQ_SEL_N */ + PAD_CFG_NF(GPP_E01, NONE, DEEP, NF1), + /* GPP_E02: PEG_SLOT_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), + /* GPP_E03: SOC_M2_GEN5_SSD2_RESET_N */ + PAD_CFG_GPO(GPP_E03, 0, DEEP), + /* GPP_E04: SOC_M2_GEN5_SSD2_PWREN */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + /* GPP_E05: M.2_WWAN_PERST_GPIO_N */ + PAD_CFG_GPO(GPP_E05, 1, PLTRST), + /* GPP_E06: GPP_E6 */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07: SOC_M2_GEN5_SSD1_PWREN */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_E08: M2_GEN5_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + /* GPP_E09: USB32_TYPEA_CONN1_OC0_N */ + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), + /* GPP_E10: CRD1_RST_N */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* GPP_E11: THC0_SPI_CLK_GSPI_CLK_R */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC0_I2C_SCL_TCH_PNL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* GPP_E13: THC0_I2C_SDA_TCH_PNL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* GPP_E14: THC0_SPI_IO_2_TCH_PNL_R */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI_IO_3_TCH_PNL_R */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI_RST_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF3), + /* GPP_E17: THC0_SPI_CS0_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), + /* GPP_E18: THC0_SPI_INT_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_E19: CODEC_GPIO_EN */ + PAD_CFG_GPO(GPP_E19, 1, PLTRST), + /* GPP_E20: FPMCU_FW_UPDATE */ + PAD_CFG_GPI(GPP_E20, NONE, PLTRST), + /* GPP_E21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + + /* GPP_F */ + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F07: IMGCLKOUT_2 */ + PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), + /* GPP_F08: ISH_GP_7A_SNSR_HDR_R */ + PAD_CFG_NF(GPP_F08, NONE, DEEP, NF8), + /* GPP_F09: ISH_INT_GP11_CVS */ + PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4), + /* GPP_F11: CRD2_RST_N */ + PAD_CFG_GPO(GPP_F11, 1, PLTRST), + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F14: EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_F15: WWAN_WAKE_GPIO_N */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, DEEP, LEVEL), + /* GPP_F16: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC_LOCK(GPP_F16, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_F17: CODEC_INT_N */ + PAD_CFG_GPI_SCI_LOW(GPP_F17, NONE, DEEP, LEVEL), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ + PAD_CFG_GPO(GPP_F19, 0, PLTRST), + /* GPP_F22: X1_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + /* GPP_F23: SMC_LID_LS */ + PAD_CFG_GPI(GPP_F23, NONE, DEEP), + + /* GPP_H */ + /* GPP_H00: GPP_PRIVACY_LED_CAM1 */ + PAD_CFG_GPO(GPP_H00, 0, PLTRST), + /* GPP_H01: CRD_CAM_STROBE */ + PAD_CFG_GPO(GPP_H01, 0, PLTRST), + /* GPP_H02: DEBUG_TRACE_PNP */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* GPP_H03: Not used */ + PAD_NC(GPP_H03, NONE), + /* GPP_H04: I2C2_SCL_I3C2_SDA_TTK */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: I2C2_SCL_I3C2_SCL_TTK */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: BUF_RTS_N */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* GPP_H11: BUF_CTS_N */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* GPP_H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14: ISH_I2C1_ISH_I3C1_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF3), + /* GPP_H15: ISH_I2C1_ISH_I3C1_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF3), + /* GPP_H16: MIC_MUTE_R */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17: MIC_MUTE_LED_R */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H19: I2C0_I3C0_SDA_CAM2_FLSH_CVS */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20: I2C0_I3C0_SCL_CAM2_FLSH_CVS */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21: I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S */ + /* GPP_S00: SNDW3_CLK_CODEC */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW3_DATA0_CODEC */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SNDW3_DATA1_CODEC */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SNDW3_DATA2_CODEC */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: GPP_S4_SNDW2_CLK_DMIC_CLK_A_0_R */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC0_DATA_SNDW2_DATA0_R */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: DMIC1_CLK_SNDW1_CLK_SNDW2_DATA1_R */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* GPP_S07: DMIC1_DATA_SNDW1_DATA0_SNDW2_DATA2_R */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), + + /* GPP_V */ + /* GPP_V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: BC_ACOK_MCP */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: GPP_V2_SOC_WAKE_N */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PWRBTN_MCP_N */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: PM_SLP_S3_N */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: PM_SLP_S4_N */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: NC */ + PAD_NC(GPP_V07, NONE), + /* GPP_V08: UFS_RDV_RESET_N */ + PAD_CFG_GPO(GPP_V08, 1, PLTRST), + /* GPP_V09: PM_SLP_S5_N */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: CSE_EARLY_SW */ + PAD_NC(GPP_V16, NONE), + /* GPP_V17: Not used */ + PAD_NC(GPP_V17, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_H04: SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + /* GPP_H08: UART0_BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART0_BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_F16: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC(GPP_F16, NONE, PLTRST, LEVEL, INVERT), + + /* Put all storage media in reset and then disable power. */ + /* GPP_A11: SOC_M2_GEN4_SSD3_RESET_N */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_E03: SOC_M2_GEN5_SSD2_RESET_N */ + PAD_CFG_GPO(GPP_E03, 0, DEEP), + /* GPP_E08: M2_GEN5_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + /* GPP_B25: UFS_RST_N */ + PAD_CFG_GPO(GPP_B25, 0, DEEP), + /* GPP_B10: SOC_M2_GEN4_SSD3_PWREN */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + /* GPP_E04: SOC_M2_GEN5_SSD2_PWREN */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + /* GPP_E07: SOC_M2_GEN5_SSD1_PWREN */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + /* GPP_C00: GPP_C0_SMBCLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: GPP_C1_SMBDATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/atria/variants/atria/include/variant/ec.h b/src/mainboard/google/atria/variants/atria/include/variant/ec.h new file mode 100644 index 00000000000..4fc0622f15a --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/atria/variants/atria/include/variant/gpio.h b/src/mainboard/google/atria/variants/atria/include/variant/gpio.h new file mode 100644 index 00000000000..8d634881f6d --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#define GPIO_PCH_WP GPP_D02 +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +#define EC_SYNC_IRQ GPP_F14_IRQ + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/atria/variants/atria/memory.c b/src/mainboard/google/atria/variants/atria/memory.c new file mode 100644 index 00000000000..ac22790378c --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/memory.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 2, 1, 3, 5, 4, 7, 6, }, + .dq1 = { 12, 14, 15, 13, 9, 11, 10, 8, }, + }, + .ddr1 = { + .dq0 = { 11, 9, 8, 10, 12, 13, 14, 15, }, + .dq1 = { 6, 5, 7, 4, 0, 3, 1, 2, }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 5, 7, 4, 6, }, + .dq1 = { 13, 14, 15, 12, 9, 11, 10, 8, }, + }, + .ddr3 = { + .dq0 = { 10, 8, 9, 11, 15, 12, 13, 14, }, + .dq1 = { 7, 5, 6, 4, 1, 3, 0, 2, }, + }, + .ddr4 = { + .dq0 = { 4, 6, 5, 7, 3, 1, 2, 0, }, + .dq1 = { 10, 8, 9, 11, 15, 13, 12, 14, }, + }, + .ddr5 = { + .dq0 = { 15, 13, 12, 14, 11, 9, 10, 8, }, + .dq1 = { 1, 2, 3, 0, 5, 4, 7, 6, }, + }, + .ddr6 = { + .dq0 = { 4, 6, 5, 7, 1, 3, 0, 2, }, + .dq1 = { 11, 8, 9, 10, 12, 14, 15, 13, }, + }, + .ddr7 = { + .dq0 = { 12, 13, 15, 14, 9, 11, 8, 10, }, + .dq1 = { 2, 3, 0, 1, 5, 4, 7, 6, }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0, } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0x55, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = 0; +} diff --git a/src/mainboard/google/atria/variants/atria/memory/Makefile.mk b/src/mainboard/google/atria/variants/atria/memory/Makefile.mk new file mode 100644 index 00000000000..e38566565d9 --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/memory/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /tmp/go-build2398032822/b001/exe/part_id_gen NVL lp5 src/mainboard/google/atria/variants/atria/memory src/mainboard/google/atria/variants/atria/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = H58G56BK8BX068 diff --git a/src/mainboard/google/atria/variants/atria/memory/dram_id.generated.txt b/src/mainboard/google/atria/variants/atria/memory/dram_id.generated.txt new file mode 100644 index 00000000000..d859f99b839 --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /tmp/go-build2398032822/b001/exe/part_id_gen NVL lp5 src/mainboard/google/atria/variants/atria/memory src/mainboard/google/atria/variants/atria/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H58G56BK8BX068 0 (0000) diff --git a/src/mainboard/google/atria/variants/atria/memory/mem_parts_used.txt b/src/mainboard/google/atria/variants/atria/memory/mem_parts_used.txt new file mode 100644 index 00000000000..ae8eff2d961 --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H58G56BK8BX068 diff --git a/src/mainboard/google/atria/variants/atria/overridetree.cb b/src/mainboard/google/atria/variants/atria/overridetree.cb new file mode 100644 index 00000000000..416d2a482dc --- /dev/null +++ b/src/mainboard/google/atria/variants/atria/overridetree.cb @@ -0,0 +1,360 @@ +# CBI UFSC fields +fw_config + field AUDIO_CODEC 0 2 + option AUDIO_CODEC_ABSENT 0 + option AUDIO_CODEC_CS42L45 1 + option AUDIO_CODEC_ALC721 2 + end + field AUDIO_AMPLIFIER 3 5 + option AUDIO_AMPLIFIER_ABSENT 0 + option AUDIO_AMPLIFIER_CS35L63 1 + end + field CAMERA_UFC_NAME 6 8 + option CAMERA_UFC_NAME_ABSENT 0 + end + field STORAGE_TYPE 12 14 + option STORAGE_TYPE_NVME_GEN4 1 + option STORAGE_TYPE_NVME_GEN5 2 + option STORAGE_TYPE_UFS 3 + end + field SD_CARD_CONTROLLER 15 16 + option SD_CONTROLLER_ABSENT 0 + option SD_CONTROLLER_PRESENT 1 + end + field TOUCHSCREEN 17 18 + option TOUCHSCREEN_ABSENT 0 + option TOUCHSCREEN_PRESENT 1 + end + field SENSOR_HUB 23 23 + option ISH_ABSENT 0 + option ISH_PRESENT 1 + end + field FINGERPRINT_INTERFACE 24 25 + option FINGERPRINT_INTERFACE_ABSENT 0 + option FINGERPRINT_INTERFACE_USB 1 + end + field WIFI_INTERFACE 26 27 + option WIFI_INTERFACE_ABSENT 0 + option WIFI_INTERFACE_CNVI 1 + option WIFI_INTERFACE_PCIE 2 + end + field FORM_FACTOR 30 31 + option FORM_FACTOR_CLAMSHELL 1 + end + field TRACKPAD 32 34 + option TRACKPAD_ABSENT 0 + option TRACKPAD_PRESENT 1 + end + field KEYBOARD_LAYOUT 45 47 + option KEYBOARD_ABSENT 0 + option KEYBOARD_PRESENT 1 + end + field AP_OEM_3BIT_FIELD0 56 58 + option WIFI_SAR_ID0 0 + option WIFI_SAR_ID1 1 + end +end + +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/intel/novalake + # GPE configuration + register "pmc_gpe0_dw2" = "GPP_C" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable eDP in Port A & HDMI in Port 4 + register "ddi_port_A_config" = "1" + register "ddi_port_B_config" = "0" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Unused | + #| I2C1 | Unused | + #| I2C2 | TPM(ti50) | + #| I2C3 | Audio, SAR | + #| I2C4 | Touchscreen | + #| I2C5 | Touchpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[2] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Enable CNVi Wi-Fi and Bluetooth + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "5" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDI4 for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDI4 + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device generic 0 on end + end + end + + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" + register "disable_clkstop_sm_support" = "true" + # SoundWire Link 3 ID 0 + device generic 3.0 on + probe AUDIO_CODEC AUDIO_CODEC_ALC721 + end + end + end + end + end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end # CNVi + + device ref cnvi_bluetooth on + chip soc/intel/common/block/cnvi + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref pcie_rp3 on + probe WIFI_INTERFACE WIFI_INTERFACE_PCIE + register "pcie_rp[PCIE_RP(3)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + register "srcclk_pin" = "2" + device generic 0 on end + end + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_06" + register "add_acpi_dma_property" = "true" + use usb2_port4 as bluetooth_companion + device pci 00.0 on end + end + end # PCIe WLAN + + device ref pcie_rp5 on + probe STORAGE_TYPE STORAGE_TYPE_NVME_GEN4 + probe unprovisioned + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "4" + device generic 0 on end + end + end # Gen4 M.2 SSD + + device ref pcie_rp9 on + probe STORAGE_TYPE STORAGE_TYPE_NVME_GEN5 + probe unprovisioned + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E04)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end # Gen5 M.2 SSD + + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on end + + device ref i2c2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_F16_IRQ)" + device i2c 50 on end + end + end # I2C2 + + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "num_dfps" = "3" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port1 as dfp[1].typec_port + register "dfp[2].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[2].typec_port + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)" + device ref usb2_port4 on + probe WIFI_INTERFACE WIFI_INTERFACE_PCIE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on end + end + end + end + end + + device ref ufs on + probe STORAGE_TYPE STORAGE_TYPE_UFS + probe unprovisioned + end + + end # domain +end # chip soc/intel/novalake diff --git a/src/mainboard/google/atria/variants/baseboard/Makefile.mk b/src/mainboard/google/atria/variants/baseboard/Makefile.mk new file mode 100644 index 00000000000..9064208bff4 --- /dev/null +++ b/src/mainboard/google/atria/variants/baseboard/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/atria/variants/baseboard/devicetree.cb b/src/mainboard/google/atria/variants/baseboard/devicetree.cb new file mode 100644 index 00000000000..ec54db2518c --- /dev/null +++ b/src/mainboard/google/atria/variants/baseboard/devicetree.cb @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/intel/novalake + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_E" + register "pmc_gpe0_dw1" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "pch_hda_dsp_enable" = "true" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_interface" = "IDISP_LINK_HDA" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref npu on end + device ref xhci on end + device ref pmc_shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref soc_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + end # domain +end # chip soc/intel/novalake diff --git a/src/mainboard/google/atria/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/atria/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 00000000000..b9b46890f19 --- /dev/null +++ b/src/mainboard/google/atria/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. AC Connect/Disconnect + * 3. Power button + * 4. Key press + * 5. Mode change + * 6. Low battery + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + MAINBOARD_EC_S5_WAKE_EVENTS) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) | \ + MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN)) +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ +#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ + +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/atria/variants/baseboard/include/baseboard/gpio.h similarity index 65% rename from src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h rename to src/mainboard/google/atria/variants/baseboard/include/baseboard/gpio.h index a6683fd286c..b94afac4bf8 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/atria/variants/baseboard/include/baseboard/gpio.h @@ -3,9 +3,4 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ -#include - -/* SPI Write protect */ -#define CROS_WP_GPIO GPIO_139 - #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/atria/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/atria/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 00000000000..11e5ef172dd --- /dev/null +++ b/src/mainboard/google/atria/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include + +/** + * @brief Get the variant GPIO table + * + * @param[out] num Number of entries in the table + * + * @return Pointer to the variant GPIO table + */ +const struct pad_config *variant_gpio_table(size_t *num); + +/** + * @brief Get the variant early GPIO table + * + * @param[out] num Number of entries in the table + * + * @return Pointer to the variant early GPIO table + */ +const struct pad_config *variant_early_gpio_table(size_t *num); + +/** + * @brief Get the variant romstage GPIO table + * + * @param[out] num Number of entries in the table + * + * @return Pointer to the variant romstage GPIO table + */ +const struct pad_config *variant_romstage_gpio_table(size_t *num); + +/** + * @brief Get the variant memory parameters + * + * @return Pointer to the variant memory parameters + */ +const struct mb_cfg *variant_memory_params(void); + +/** + * @brief Get the variant SPD info + * + * @param[out] spd_info Pointer to the SPD info structure + */ +void variant_get_spd_info(struct mem_spd *spd_info); + +/** + * @brief Get the variant memory SKU + * + * @return Memory SKU + */ +int variant_memory_sku(void); + +/** + * @brief Check if the variant is half populated + * + * @return True if the variant is half populated, false otherwise + */ +bool variant_is_half_populated(void); + +/** + * @brief Update the variant SOC memory init parameters + * + * @param[in,out] memupd Pointer to the FSPM_UPD structure + */ +void variant_update_soc_memory_init_params(FSPM_UPD *memupd); + +void fw_config_configure_pre_mem_gpio(void); + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/atria/variants/baseboard/memory.c b/src/mainboard/google/atria/variants/baseboard/memory.c new file mode 100644 index 00000000000..740d7fb2ef0 --- /dev/null +++ b/src/mainboard/google/atria/variants/baseboard/memory.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 1, 0, 3, 2, 7, 4, 5, 6, }, + .dq1 = { 13, 12, 14, 15, 11, 10, 8, 9, }, + }, + .ddr1 = { + .dq0 = { 11, 8, 10, 9, 15, 12, 13, 14, }, + .dq1 = { 6, 7, 5, 4, 0, 1, 3, 2, }, + }, + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 4, 7, 5, 6, }, + .dq1 = { 13, 12, 14, 15, 10, 11, 8, 9, }, + }, + .ddr3 = { + .dq0 = { 8, 10, 9, 11, 12, 13, 14, 15, }, + .dq1 = { 6, 5, 4, 7, 3, 2, 1, 0, }, + }, + .ddr4 = { + .dq0 = { 5, 6, 4, 7, 3, 2, 1, 0, }, + .dq1 = { 8, 9, 10, 11, 14, 15, 13, 12, }, + }, + .ddr5 = { + .dq0 = { 12, 15, 13, 14, 9, 11, 10, 8, }, + .dq1 = { 3, 2, 1, 0, 4, 7, 6, 5, }, + }, + .ddr6 = { + .dq0 = { 7, 3, 2, 0, 6, 1, 4, 5, }, + .dq1 = { 10, 14, 15, 11, 13, 12, 9, 8, }, + }, + .ddr7 = { + .dq0 = { 8, 12, 11, 9, 10, 15, 14, 13, }, + .dq1 = { 5, 4, 0, 1, 6, 3, 2, 7, }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0, } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + return 0; +} + +bool __weak variant_is_half_populated(void) +{ + return 0; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/atria/variants/penghu/Makefile.mk b/src/mainboard/google/atria/variants/penghu/Makefile.mk new file mode 100644 index 00000000000..2cddd114add --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/atria/variants/penghu/gpio.c b/src/mainboard/google/atria/variants/penghu/gpio.c new file mode 100644 index 00000000000..d6784be3909 --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/gpio.c @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPP_A02: ESPI_SOC_IO2_R */ + /* GPP_A02 => ESPI_SOC_IO2_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_SOC_IO3_R */ + /* GPP_A03 => ESPI_SOC_IO3_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_SOC_CS_R_L */ + /* GPP_A04 => ESPI_SOC_CS_R_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_SOC_CLK_R */ + /* GPP_A05 => ESPI_SOC_CLK_R configured on reset, do not touch */ + + /* GPP_A06: ESPI_SOC_RST_L */ + /* GPP_A06 => ESPI_SOC_RST_L configured on reset, do not touch */ + + /* GPP_A07: SPI_SOC_CLK_FP_R */ + /* GPP_A07 => SPI_SOC_CLK_FP_R configured on reset, do not touch */ + + /* GPP_A08: WWAN_EN */ + PAD_CFG_GPO(GPP_A08, 1, DEEP), + /* GPP_A09: EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), + /* GPP_A10: WLAN_PERST_L */ + PAD_CFG_GPO(GPP_A10, 1, PLTRST), + /* GPP_A11: SSD_GEN4_PERST_L */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A13: SLP_S0_GATE_R */ + /* GPP_A13 => SLP_S0_GATE_R configured on reset, do not touch */ + + /* GPP_A14: SPI_SOC_CS_FP_R_L */ + /* GPP_A14 => SPI_SOC_CS_FP_R_L configured on reset, do not touch */ + + /* GPP_A15: BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), + /* GPP_A16: SPI_SOC_DI_FP_DO */ + /* GPP_A16 => SPI_SOC_DI_FP_DO configured on reset, do not touch */ + + /* GPP_A17: SPI_SOC_DO_FP_DI_R */ + /* GPP_A17 => SPI_SOC_DO_FP_DI_R configured on reset, do not touch */ + + /* GPP_B00: PMC_I2C_PD_SCL */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: PMC_I2C_PD_SDA */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_B02, NONE, DEEP), + /* GPP_B03: MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_B03, NONE, DEEP), + /* GPP_B04: MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_B04, NONE, DEEP), + /* GPP_B05: MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B06: EC_ISH_INT_ODL */ + PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4), + /* GPP_B07: ISH_ACCEL_MB_INT_L */ + PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), + /* GPP_B08: ISH_ACCEL_DB_INT_L */ + PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), + /* GPP_B09: SOC_FP_RST_L */ + PAD_CFG_GPO(GPP_B09, 1, PLTRST), + /* GPP_B10: SOC_GPP_B10 */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11: EN_SPK_PA */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* GPP_B13: PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: HDMI_HPD_L_STRAP */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* GPP_B15: SOC_GPP_B15 */ + PAD_NC(GPP_B15, NONE), + /* GPP_B17: SD_PE_PRSNT_L */ + PAD_CFG_GPI(GPP_B17, NONE, DEEP), + /* GPP_B18: ISH_EC_I2C_SENSOR_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_EC_I2C_SENSOR_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: WWAN_RST_L */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), + /* GPP_B21: USB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* GPP_B22: SOC_GPP_B22 */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23: SOC_GPP_B23_STRAP */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24: NC */ + /* GPP_B24 => NC configured on reset, do not touch */ + + /* GPP_B25: SOC_UFS_RST_L */ + /* GPP_B25 => SOC_UFS_RST_L configured on reset, do not touch */ + + /* GPP_C03: NC */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04: NC */ + PAD_NC(GPP_C04, NONE), + /* GPP_C05: EN_UCAM_PWR_STRAP */ + PAD_CFG_GPO(GPP_C05, 1, DEEP), + /* GPP_C06: EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_C06, 1, DEEP), + /* GPP_C07: MEM_CH_SEL */ + PAD_CFG_GPI(GPP_C07, NONE, DEEP), + /* GPP_C08: EN_WCAM_PWR_STRAP */ + PAD_CFG_GPO(GPP_C08, 1, DEEP), + /* GPP_C09: SSD_GEN5_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C10: SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + /* GPP_C11: WLAN_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: WWAN_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13: SSD_GEN4_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: SOC_GPP_C14 */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15: SOC_GPP_C15_STRAP */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16: USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19: USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20: USB_C2_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: USB_C2_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22: DDI4_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: DDI4_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + /* GPP_D00: WCAM_MCLK_R */ + PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), + /* GPP_D01: EN_PWR_FP */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02: SOC_WP_OD */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), + /* GPP_D03: SOC_GPP_D03_STRAP */ + PAD_NC(GPP_D03, NONE), + /* GPP_D04: UCAM_MCLK_R */ + PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), + /* GPP_D05: UART_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), + /* GPP_D06: UART_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), + /* GPP_D07: EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D07, 1, PLTRST), + /* GPP_D08: SOC_GPP_D08 */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09: I2S0_MCLK_R */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10: I2S0_SCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11: I2S0_SFRM */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12: I2S0_TXD_STRAP */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: I2S0_RDX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D16: SOC_GPP_D16 */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17: SOC_GPP_D17 */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18: SOC_GPP_D18 */ + PAD_NC(GPP_D18, NONE), + /* GPP_D20: SOC_GPP_D20 */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21: SOC_UFS_REFCLK */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* GPP_D22: WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_D22, 1, PLTRST), + /* GPP_D23: WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_D23, 1, DEEP), + /* GPP_E01: SOC_GPP_E01 */ + PAD_NC(GPP_E01, NONE), + /* GPP_E02: FP_SOC_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E02, NONE, PWROK, LEVEL, INVERT), + /* GPP_E03: SSD_GEN5_PERST_L */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E04: EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E04, 1, DEEP), + /* GPP_E05: WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E05, 1, PLTRST), + /* GPP_E06: SOC_GPP_E06_STRAP */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07: WCAM_RST_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_E08: SOC_TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_E08, 1, PLTRST), + /* GPP_E09: USBA_OC_ODL_STRAP */ + PAD_NC(GPP_E09, NONE), + /* GPP_E11: SPI_TCHSCR_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: SPI_I2C_TCHSCR_MOSI_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: SPI_I2C_TCHSCR_MISO_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: SOC_GPP_E14 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: SOC_GPP_E15 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: TCHSCR_RST_ODL */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF3), + /* GPP_E17: SPI_TCHSCR_CS_L */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), + /* GPP_E18: TCHSCR_INT_ODL */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_E19: SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* GPP_E20: SOC_FP_FW_UP */ + PAD_CFG_GPO(GPP_E20, 0, PLTRST), + /* GPP_E22: EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_E22, 1, PLTRST), + /* GPP_F00: CNV_BRI_DT_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: CNV_BRI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: CNV_RGI_DT_STRAP_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: CNV_RGI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RST_L */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CNV_CLKREQ */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F07: FCAM_MCLK */ + PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), + /* GPP_F08: NC */ + PAD_NC(GPP_F08, NONE), + /* GPP_F09: SOC_PEN_DETECT */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, LEVEL, ACPI), + /* GPP_F11: UCAM_RST_L */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* GPP_F12: I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13: I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F14: EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_F15: WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, DEEP, LEVEL), + /* GPP_F16: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_F16, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_F17: HP_INT_ODL */ + // TODO: Check pin GPP_F17 interrupt route, polarity, trigger + PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), + /* GPP_F18: TCHPAD_INT_ODL */ + PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F19: SOC_GPP_F19_STRAP */ + PAD_NC(GPP_F19, NONE), + /* GPP_F22: WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F22, NONE, DEEP, LEVEL), + /* GPP_F23: SD_PERST_L */ + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + /* GPP_H00: SOC_GPP_H00_STRAP */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01: SOC_GPP_H01_STRAP */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: SOC_GPP_H02_STRAP */ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: SOC_GPP_H03 */ + PAD_NC(GPP_H03, NONE), + /* GPP_H04: SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + /* GPP_H06: SOC_I2C_AUDIO_SAR_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: SOC_I2C_AUDIO_SAR_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: SOC_GPP_H10 */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11: SOC_GPP_H11 */ + PAD_NC(GPP_H11, NONE), + /* GPP_H14: UART_SOC_RX_FP_TX */ + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF2), + /* GPP_H15: UART_SOC_TX_FP_RX */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF2), + /* GPP_H16: SOC_GPP_H16 */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17: SOC_GPP_H17 */ + PAD_NC(GPP_H17, NONE), + /* GPP_H19: SOC_I2C_UFC_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20: SOC_I2C_UFC_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21: I2C_WFC_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: I2C_WFC_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_S00: SDW3_CLK_I2S1_TXD */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SDW3_DAT0 */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SDW3_DAT1_I2S1_SCLK */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SDW3_DAT2_I2S1_SFRM */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: DMIC_CLK0_EDP */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC_DATA0_EDP */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: DMIC_SOC_CLK1 */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* GPP_S07: DMIC_SOC_DATA1 */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), + /* GPP_V00: BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: SLP_A_L */ + PAD_NC(GPP_V06, NONE), + /* GPP_V07: SOC_SUSCLK */ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), + /* GPP_V08: SOC_GPP_V08 */ + PAD_NC(GPP_V08, NONE), + /* GPP_V09: SLP_S5_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: NC */ + PAD_NC(GPP_V10, NONE), + /* GPP_V11: SLP_LAN_L */ + PAD_NC(GPP_V11, NONE), + /* GPP_V12: SOC_WAKE_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V16: EC_SOC_REC_SWITCH_ODL */ + PAD_CFG_GPI(GPP_V16, NONE, DEEP), + /* GPP_V17: SOC_GPP_V17_STRAP */ + PAD_NC(GPP_V17, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_F16: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_F16, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_H04: SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + + /* GPP_H08: UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/atria/variants/penghu/include/variant/ec.h b/src/mainboard/google/atria/variants/penghu/include/variant/ec.h new file mode 100644 index 00000000000..4fc0622f15a --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/atria/variants/penghu/include/variant/gpio.h b/src/mainboard/google/atria/variants/penghu/include/variant/gpio.h new file mode 100644 index 00000000000..8d634881f6d --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#define GPIO_PCH_WP GPP_D02 +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +#define EC_SYNC_IRQ GPP_F14_IRQ + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/atria/variants/penghu/memory.c b/src/mainboard/google/atria/variants/penghu/memory.c new file mode 100644 index 00000000000..41a9c8b9104 --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/memory.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 2, 1, 3, 5, 4, 7, 6, }, + .dq1 = { 12, 14, 15, 13, 9, 11, 10, 8, }, + }, + .ddr1 = { + .dq0 = { 11, 9, 8, 10, 12, 13, 14, 15, }, + .dq1 = { 6, 5, 7, 4, 0, 3, 1, 2, }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 5, 7, 4, 6, }, + .dq1 = { 13, 14, 15, 12, 9, 11, 10, 8, }, + }, + .ddr3 = { + .dq0 = { 10, 8, 9, 11, 15, 12, 13, 14, }, + .dq1 = { 7, 5, 6, 4, 1, 3, 0, 2, }, + }, + .ddr4 = { + .dq0 = { 4, 6, 5, 7, 3, 1, 2, 0, }, + .dq1 = { 10, 8, 9, 11, 15, 13, 12, 14, }, + }, + .ddr5 = { + .dq0 = { 15, 13, 12, 14, 11, 9, 10, 8, }, + .dq1 = { 1, 2, 3, 0, 5, 4, 7, 6, }, + }, + .ddr6 = { + .dq0 = { 4, 6, 5, 7, 1, 3, 0, 2, }, + .dq1 = { 11, 8, 9, 10, 12, 14, 15, 13, }, + }, + .ddr7 = { + .dq0 = { 12, 13, 15, 14, 9, 11, 8, 10, }, + .dq1 = { 2, 3, 0, 1, 5, 4, 7, 6, }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0, }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1, }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0, } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0x55, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_B02 + * GPIO_MEM_CONFIG_1 GPP_B03 + * GPIO_MEM_CONFIG_2 GPP_B04 + * GPIO_MEM_CONFIG_3 GPP_B05 + */ + gpio_t spd_gpios[] = { + GPP_B02, + GPP_B03, + GPP_B04, + GPP_B05, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_C07 */ + return gpio_get(GPP_C07); +} diff --git a/src/mainboard/google/atria/variants/penghu/memory/Makefile.mk b/src/mainboard/google/atria/variants/penghu/memory/Makefile.mk new file mode 100644 index 00000000000..8b010d03d36 --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/memory/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen NVL lp5 src/mainboard/google/atria/variants/penghu/memory src/mainboard/google/atria/variants/penghu/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C, H58G66CK8BX147 diff --git a/src/mainboard/google/atria/variants/penghu/memory/dram_id.generated.txt b/src/mainboard/google/atria/variants/penghu/memory/dram_id.generated.txt new file mode 100644 index 00000000000..9671d08eaaf --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen NVL lp5 src/mainboard/google/atria/variants/penghu/memory src/mainboard/google/atria/variants/penghu/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +MT62F1G32D2DS-023 WT:C 1 (0001) +MT62F2G32D4DS-020 WT:F 2 (0010) +H58G56CK8BX146 1 (0001) +MT62F2G32D4DS-023 WT:C 2 (0010) +H58G66CK8BX147 2 (0010) diff --git a/src/mainboard/google/atria/variants/penghu/memory/mem_parts_used.txt b/src/mainboard/google/atria/variants/penghu/memory/mem_parts_used.txt new file mode 100644 index 00000000000..a78826b02ca --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/memory/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H58G56BK7BX068 +MT62F1G32D2DS-023 WT:C +MT62F2G32D4DS-020 WT:F +H58G56CK8BX146 +MT62F2G32D4DS-023 WT:C +H58G66CK8BX147 diff --git a/src/mainboard/google/atria/variants/penghu/overridetree.cb b/src/mainboard/google/atria/variants/penghu/overridetree.cb new file mode 100644 index 00000000000..58bb7d0fd7a --- /dev/null +++ b/src/mainboard/google/atria/variants/penghu/overridetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/intel/novalake + device domain 0 on + end # domain +end # chip soc/intel/novalake diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 10d9a35191c..1a22e530c2d 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -31,6 +31,9 @@ config BOARD_GOOGLE_AURON_YUNA config BOARD_GOOGLE_BUDDY select BOARD_GOOGLE_BASEBOARD_AURON + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select RT8168_SUPPORT_LEGACY_VPD_MAC select SYSTEM_TYPE_ALL_IN_ONE config BOARD_GOOGLE_GANDOF diff --git a/src/mainboard/google/auron/cfr.c b/src/mainboard/google/auron/cfr.c index dea0e812be9..521b62ea585 100644 --- a/src/mainboard/google/auron/cfr.c +++ b/src/mainboard/google/auron/cfr.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include static const struct sm_object touchscreen = SM_DECLARE_BOOL({ .opt_name = "touchscreen", diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 14c8f676429..962cc7625f0 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -7,14 +7,9 @@ #include "ec.h" #include "variant.h" -__weak void lan_init(void) -{ -} - static void mainboard_init(struct device *dev) { mainboard_ec_init(); - lan_init(); } static void mainboard_fill_ssdt(const struct device *dev) diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index d471576bc4a..187f3587278 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -9,7 +9,6 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); -void lan_init(void); unsigned int variant_get_spd_index(void); bool variant_is_dual_channel(const unsigned int spd_index); diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 866ea3a56c0..d373de4a8d0 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: LTE */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P1: POrt A, CN10 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL); + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* P2: CCD */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P3: BT */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port B, CN6 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL); + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, /* P5: EMPTY */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P6: SD Card */ - pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Port A, CN6 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: EMPTY */ - pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P4: EMPTY */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 866ea3a56c0..d373de4a8d0 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: LTE */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P1: POrt A, CN10 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL); + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* P2: CCD */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P3: BT */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port B, CN6 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL); + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, /* P5: EMPTY */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P6: SD Card */ - pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Port A, CN6 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: EMPTY */ - pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P4: EMPTY */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h index 337250a8e04..0ce4f1e5515 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h @@ -3,13 +3,6 @@ #ifndef ONBOARD_H #define ONBOARD_H -/* defines for programming the MAC address */ -#define BUDDY_NIC_VENDOR_ID 0x10EC -#define BUDDY_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define BUDDY_NIC_LED_MODE 0x00 - #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */ #define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */ diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 81fecac9c76..997d24d67c6 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -40,7 +40,14 @@ chip northbridge/intel/broadwell device pci 13.0 on end # Smart Sound Audio DSP device pci 1b.0 off end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.2 on # PCIe Port #3 - LAN (becomes RP1) + chip drivers/net + register "customized_leds" = "0x0087" + register "device_index" = "0" + register "enable_pcie_clkreq" = "true" + device pci 00.0 on end + end + end device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index e185d7ea79d..c2481555234 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: Side USB3.0 port, USB3S1 */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_INTERNAL); + { 0x0150, 1, 0, USB_PORT_INTERNAL }, /* P1: Rear USB3.0 port, USB3R1 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL); + { 0x0040, 1, 0, USB_PORT_INTERNAL }, /* P2: Rear USB3.0 port, USB3R2 */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1, USB_PORT_INTERNAL); + { 0x0080, 1, 1, USB_PORT_INTERNAL }, /* P3: Card Reader, CRS1 */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P4: Rear USB2.0 port, USB2R1 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P5: 2D Camera */ - pei_data_usb2_port(pei_data, 5, 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P6: VP8 */ - pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P7: WLAN & BT */ - pei_data_usb2_port(pei_data, 7, 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Side USB3.0 port, USB3S1 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: Rear USB3.0 port, USB3R1 */ - pei_data_usb3_port(pei_data, 1, 1, 0, 0); + { 1, 0, 0 }, /* P3: Rear USB3.0 port, USB3R2 */ - pei_data_usb3_port(pei_data, 2, 1, 1, 0); + { 1, 1, 0 }, /* P4: Card Reader, CRS1 */ - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} + { 1, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 5af2502e659..0a128dd54a7 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include -#include -#include -#include #include #include -#include #include #include @@ -28,166 +21,3 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) return len; } - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_ERR, "Invalid Hex digit found: %c - 0x%02x\n", *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (CONFIG(VPD)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_map("vpd.bin", &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(BUDDY_NIC_VENDOR_ID, - BUDDY_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN PCI config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((BUDDY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index 866ea3a56c0..d373de4a8d0 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: LTE */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P1: POrt A, CN10 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL); + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* P2: CCD */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P3: BT */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port B, CN6 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL); + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, /* P5: EMPTY */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P6: SD Card */ - pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX); + { 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Port A, CN6 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: EMPTY */ - pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P4: EMPTY */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index 10862e86656..9e58004a0d1 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: Port B, CN01 (IOBoard) */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL); + { 0x0150, 1, 0, USB_PORT_BACK_PANEL }, /* P1: Port A, CN01 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2, USB_PORT_BACK_PANEL); + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, /* P2: CCD */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P3: BT */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Empty */ - pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P5: EMPTY */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P6: SD Card */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P0: PORTB*/ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P1: PORTA */ - pei_data_usb3_port(pei_data, 1, 1, 2, 0); + { 1, 2, 0 }, /* P2: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 705ec25cd88..ef6191c8b25 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: HOST PORT */ - pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, USB_PORT_BACK_PANEL); + { 0x0080, 1, 0, USB_PORT_BACK_PANEL }, /* P1: HOST PORT */ - pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL); + { 0x0080, 1, 1, USB_PORT_BACK_PANEL }, /* P2: RAIDEN */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P4: RAIDEN */ - pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P5: WWAN (Disabled) */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P6: CAMERA */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P7: BT */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: HOST PORT */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: HOST PORT */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); + { 1, 1, 0 }, /* P3: RAIDEN */ - pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P4: RAIDEN */ - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} + { 1, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 0b5be0d5351..94787d19bad 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -15,6 +15,8 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select NORTHBRIDGE_INTEL_HASWELL + select RT8168_GET_MAC_FROM_VPD + select RT8168_SUPPORT_LEGACY_VPD_MAC select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_ITE_IT8772F select SYSTEM_TYPE_MINIPC if !SYSTEM_TYPE_ALL_IN_ONE @@ -83,4 +85,7 @@ config EDK2_BOOT_TIMEOUT int default 5 +config INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING + default y + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/Makefile.mk b/src/mainboard/google/beltino/Makefile.mk index 00255b834e8..9e1841ced27 100644 --- a/src/mainboard/google/beltino/Makefile.mk +++ b/src/mainboard/google/beltino/Makefile.mk @@ -9,7 +9,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -ramstage-y += lan.c verstage-y += chromeos.c diff --git a/src/mainboard/google/beltino/cfr.c b/src/mainboard/google/beltino/cfr.c index 0ff1433e576..029750d35d1 100644 --- a/src/mainboard/google/beltino/cfr.c +++ b/src/mainboard/google/beltino/cfr.c @@ -1,9 +1,36 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include +static const struct sm_object tdp_pl1_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl1_override", + .ui_name = "CPU PL1 power limit (W)", + .ui_helptext = "Long-duration CPU package power limit.\n" + "Default: 15 W. Range: 15-25 W.", + .default_value = 15, + .min = 15, + .max = 25, + .step = 1, + .display_flags = 0, +}); + +static const struct sm_object tdp_pl2_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl2_override", + .ui_name = "CPU PL2 power limit (W)", + .ui_helptext = "Short-duration CPU package power limit.\n" + "Default: 18 W. Range: 15-30 W.\n" + "Must be >= PL1 (enforced at boot).", + .default_value = 18, + .min = 15, + .max = 30, + .step = 1, + .display_flags = 0, +}); + static struct sm_obj_form system = { .ui_name = "System", .obj_list = (const struct sm_object *[]) { @@ -17,6 +44,9 @@ static struct sm_obj_form power = { .ui_name = "Power", .obj_list = (const struct sm_object *[]) { &power_on_after_fail, + &tdp_pl1_override, + &tdp_pl2_override, + &cpu_power_limit_lock, NULL }, }; @@ -24,6 +54,9 @@ static struct sm_obj_form power = { static struct sm_obj_form *sm_root[] = { &system, &power, +#if CONFIG(INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING) + &cpu_voltage, +#endif NULL }; diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 95b04ed14ab..6e99169978c 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -68,7 +68,13 @@ chip northbridge/intel/haswell device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 + device pci 1c.2 on # PCIe Port #3 + chip drivers/net + register "device_index" = "0" + register "enable_pcie_clkreq" = "true" + device pci 00.0 on end + end + end device pci 1c.3 on end # PCIe Port #4 device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c deleted file mode 100644 index baadf15d487..00000000000 --- a/src/mainboard/google/beltino/lan.c +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_ERR, "Invalid Hex digit found: %c - 0x%02x\n", *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (CONFIG(VPD)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_map("vpd.bin", &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(NIC_VENDOR_ID, - NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7d3da78d467..daf2c100002 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -2,27 +2,9 @@ #include #include -#include -#include - -#include "onboard.h" void mainboard_suspend_resume(void) { /* Call SMM finalize() handlers before resume */ apm_control(APM_CNT_FINALIZE); } - -static void mainboard_init(struct device *dev) -{ - lan_init(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 36295ece686..ee7e46d0ed4 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -3,13 +3,6 @@ #ifndef __MAINBOARD_ONBOARD_H #define __MAINBOARD_ONBOARD_H -/* defines for programming the MAC address */ -#define NIC_VENDOR_ID 0x10EC -#define NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define NIC_LED_MODE 0x00 - /* NIC wake is GPIO 8 */ #define NIC_WAKE_GPIO 8 @@ -29,8 +22,6 @@ #define IT8772F_EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) #ifndef __ACPI__ -void lan_init(void); - void set_power_led(int state); enum { diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig index 47c81e6e74f..7838a695f05 100644 --- a/src/mainboard/google/bluey/Kconfig +++ b/src/mainboard/google/bluey/Kconfig @@ -6,9 +6,11 @@ config BOARD_GOOGLE_BLUEY_COMMON # FIXME: keep ADB for development phase select GBB_FLAG_ENABLE_ADB if VBOOT select MAINBOARD_HAS_CHROMEOS + select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT select SPI_FLASH select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE select SPI_FLASH_INCLUDE_ALL_DRIVERS + select QC_SKIP_SOC_DEBUG_FEATURES_IN_RECOVERY config BOARD_GOOGLE_BASEBOARD_BLUEY def_bool n @@ -18,8 +20,10 @@ config BOARD_GOOGLE_MODEL_BLUEY def_bool n select BOARD_GOOGLE_BASEBOARD_BLUEY select BOARD_ROMSIZE_KB_65536 + select FW_CONFIG select MAINBOARD_HAS_FINGERPRINT_VIA_USB select MISSING_BOARD_RESET + select SOC_QUALCOMM_CDT config BOARD_GOOGLE_BLUEY select BOARD_GOOGLE_MODEL_BLUEY @@ -33,11 +37,14 @@ config BOARD_GOOGLE_MODEL_QUENBI def_bool n select BOARD_GOOGLE_BASEBOARD_BLUEY select BOARD_ROMSIZE_KB_32768 + select DAP_USE_SMB2 select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC + select HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK select MAINBOARD_HAS_CAMERA_VIA_USB select MAINBOARD_HAS_CHROME_EC select MAINBOARD_HAS_FINGERPRINT_VIA_SPI select MAINBOARD_HAS_GOOGLE_TPM + select SPI_FREQ_75MHZ config BOARD_GOOGLE_MODEL_QUARTZ def_bool n @@ -47,8 +54,9 @@ config BOARD_GOOGLE_MODEL_QUARTZ select EC_GOOGLE_CHROMEEC_LED_CONTROL select MAINBOARD_HAS_CAMERA_VIA_USB select MAINBOARD_HAS_CHROME_EC - select MAINBOARD_HAS_FINGERPRINT_VIA_SPI + select MAINBOARD_HAS_FINGERPRINT_VIA_USB select MAINBOARD_HAS_GOOGLE_TPM + select SPI_FREQ_75MHZ config BOARD_GOOGLE_QUENBI select BOARD_GOOGLE_MODEL_QUENBI @@ -60,6 +68,8 @@ config BOARD_GOOGLE_QUENBIH config BOARD_GOOGLE_QUARTZ select BOARD_GOOGLE_MODEL_QUARTZ + select DAM_SINK_SENSOR_Z1_OPTIMIZATION + select DAP_USE_SMB1 select HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK select SOC_QUALCOMM_HAMOA select MAINBOARD_HAS_PS8820_RETIMER @@ -72,13 +82,17 @@ config BOARD_GOOGLE_MODEL_MICA select BOARD_ROMSIZE_KB_32768 select EC_GOOGLE_CHROMEEC_LED_CONTROL select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC + select MAINBOARD_HAS_BACKLIGHT_PWM select MAINBOARD_HAS_CAMERA_VIA_USB select MAINBOARD_HAS_CHROME_EC select MAINBOARD_HAS_FINGERPRINT_VIA_USB select MAINBOARD_HAS_GOOGLE_TPM + select SPI_FREQ_75MHZ config BOARD_GOOGLE_MICA select BOARD_GOOGLE_MODEL_MICA + select DAP_USE_SMB1 + select HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK select MAINBOARD_HAS_PS8820_RETIMER select MAINBOARD_NO_USB_A_PORT select SOC_QUALCOMM_HAMOA @@ -139,6 +153,35 @@ config HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK help Enable this option to allow source and sink modes on the debug access port. +config DAP_SMB_SLAVE_ID + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + hex + default 0x07 if DAP_USE_SMB1 + default 0x0a if DAP_USE_SMB2 + help + The Slave ID for the Debug Access Port communication. + +config DAP_USE_SMB1 + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + help + Select this to use SMB1 for DAP. + +config DAP_USE_SMB2 + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + help + Select this to use SMB2 for DAP. + +config DAM_SINK_SENSOR_Z1_OPTIMIZATION + bool + default n + help + Enable this option to write the PMIC PSI workaround flag (address 0x7297) + after QCLib loading. This is required for boards that have + the TPD6s3000 protection IC to prevent high power consumption in the + Z1 (off) state. + config MAINBOARD_HAS_GOOGLE_TPM bool default n @@ -159,6 +202,13 @@ config MAINBOARD_HAS_CHROME_EC help Enable this option if your mainboard is equipped with Chrome EC. +config MAINBOARD_HAS_BACKLIGHT_PWM + bool + default n + help + Enable this option if your mainboard has PWM control for display + backlight. + config MAINBOARD_HAS_CAMERA_VIA_USB bool default n @@ -226,8 +276,20 @@ config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT used for the interrupt line from the Google Security Chip (GSC) to the Application Processor (AP). +config MAINBOARD_GPIO_PIN_FOR_TOUCHSCREEN_POWER + int + default 88 if BOARD_GOOGLE_MODEL_MICA + default 0 + help + The GPIO pin number used to enable/disable power to the + touchscreen controller. This varies by board revision. + Set to 0x0 if power is hardwired. + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nogsc.fmd" if BOARD_GOOGLE_MODEL_BLUEY default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" +config RW_REGION_ONLY + default "%/apdp %/apdp_meta %/ramdump %/ramdump_meta" if QC_SKIP_SOC_DEBUG_FEATURES_IN_RECOVERY + endif # BOARD_GOOGLE_BLUEY_COMMON diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk index 87d58149afc..1e081de1a56 100644 --- a/src/mainboard/google/bluey/Makefile.mk +++ b/src/mainboard/google/bluey/Makefile.mk @@ -15,3 +15,5 @@ romstage-y += charging.c ramstage-y += charging.c ramstage-y += mainboard.c + +ramstage-y += display.c diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h index 04ef0ca3c15..94a46517e15 100644 --- a/src/mainboard/google/bluey/board.h +++ b/src/mainboard/google/bluey/board.h @@ -4,6 +4,7 @@ #define MAINBOARD_GOOGLE_BLUEY_BOARD_H #include +#include #include #define GPIO_AP_EC_INT GPIO(67) @@ -16,14 +17,13 @@ /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */ #if CONFIG(MAINBOARD_HAS_FINGERPRINT) #define GPIO_FP_RST_L GPIO(25) +#define GPIO_EN_FP_RAILS GPIO(22) #if CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI) #define GPIO_FPMCU_BOOT0 GPIO(24) #define GPIO_FPMCU_INT GPIO(23) -#define GPIO_EN_FP_RAILS GPIO(22) #else #define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t) #define GPIO_FPMCU_INT dead_code_t(gpio_t) -#define GPIO_EN_FP_RAILS dead_code_t(gpio_t) #endif #endif @@ -39,9 +39,15 @@ #define GPIO_PANEL_POWER_ON GPIO(70) #define GPIO_PANEL_HPD GPIO(119) +/* Touchscreen specific GPIOs */ +#define TS_POWER_GPIO(x) GPIO(x) +#define GPIO_TS_POWER_EN TS_POWER_GPIO(CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHSCREEN_POWER) + /* Charging GPIOs */ #define GPIO_PARALLEL_CHARGING_CFG GPIO(71) +#define GPIO_LID_OPEN_S3 GPIO(92) + /* SD card specific GPIOs. Only for SD-enabled devices. */ #if CONFIG(MAINBOARD_HAS_SD_CONTROLLER) #define GPIO_SD_CD_L GPIO(71) @@ -57,6 +63,19 @@ #define GPIO_USB_C1_EN_PP0900 GPIO(188) #define GPIO_USB_C1_RETIMER_RESET_L GPIO(176) +#define GPIO_USB_C0_EN_L GPIO(108) +#define GPIO_USB_C1_EN_L GPIO(180) + +/* GPIO for controlling the panel backlight */ +#define BACKLIGHT_CONTROL_PMIC_GPIO 4 +#define BACKLIGHT_CONTROL_PMIC_ID PMIC_D_SLAVE_ID + +/* GPIO for controlling the panel backlight PWM */ +#define BACKLIGHT_PWM_PMIC_GPIO 5 +#define BACKLIGHT_PWM_PMIC_ID PMIC_A_SLAVE_ID + +#define DEAD_BATT_CHG_THRESHOLD_MAH 100 + void setup_chromeos_gpios(void); bool is_off_mode(void); void configure_parallel_charging(void); @@ -65,5 +84,9 @@ void configure_debug_access_port(void); void enable_slow_battery_charging(void); void disable_slow_battery_charging(void); void launch_charger_applet(void); +bool platform_get_battery_soc_information(uint32_t *batt_pct); +void enable_fast_battery_charging(void); +void init_sdam_config(void); +void configure_dead_battery_boot(void); #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */ diff --git a/src/mainboard/google/bluey/boardid.c b/src/mainboard/google/bluey/boardid.c index c893fdbea5d..4d4048a84c3 100644 --- a/src/mainboard/google/bluey/boardid.c +++ b/src/mainboard/google/bluey/boardid.c @@ -3,6 +3,7 @@ #include #include #include +#include uint32_t board_id(void) { @@ -17,6 +18,15 @@ uint32_t board_id(void) [0] = GPIO(135) }; + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + return id; + } else if (CONFIG(SOC_QUALCOMM_CDT)) { + id = cdt_get_hw_version(); + return id; + } + id = gpio_base3_value(pins, ARRAY_SIZE(pins)); return id; diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c index 2e0fcb2bafb..7532fa1d58b 100644 --- a/src/mainboard/google/bluey/charging.c +++ b/src/mainboard/google/bluey/charging.c @@ -5,11 +5,19 @@ #include #include #include +#include +#include +#include #include +#include #include +#include #include #include +#define PMIC_F_GPIO_07 7 +#define PMIC_F_GPIO_09 9 + #define SMB1_SLAVE_ID 0x07 #define SMB2_SLAVE_ID 0x0A #define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666 @@ -19,34 +27,47 @@ #define SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG 0x2B4A #define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD) #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD) -#define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG \ -((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG) +#define SMBx_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG(x) \ +(((x) << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG) #define SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG 0x2B4C -#define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG \ -((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG) +#define SMBx_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG(x) \ +(((x) << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG) +#define SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS 0x2B90 +#define SMBx_SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS(x) \ +(((x) << 16) | SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS) + #define SCHG_CHGR_CHARGING_FCC 0x260A #define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC) #define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC) -#define FCC_1A_STEP_50MA 0x14 +#define FCC_3A_STEP_50MA 0x3C #define FCC_DISABLE 0x8c #define EN_DEBUG_ACCESS_SNK 0x1B #define EN_DEBUG_ACCESS_SRC 0x01 +#define EN_SWITCHER_DAM_500 0x05 + +#define PMIC_PD_NEGOTIATION_FLAG 0x7E7C +#define SKIP_PORT_RESET 0x08 -#define PMC8380F_SLAVE_ID 0x05 -#define GPIO07_MODE_CTL 0x8E40 -#define GPIO07_DIG_OUT_SOURCE_CTL 0x8E44 -#define GPIO07_EN_CTL 0x8E46 -#define GPIO09_MODE_CTL 0x9040 -#define GPIO09_DIG_OUT_SOURCE_CTL 0x9044 -#define GPIO09_EN_CTL 0x9046 +#define PMIC0_SLAVE_ID 0 +#define SDAM16_MEM_030 0x7F5E +#define PMIC0_SDAM16_MEM_030 ((PMIC0_SLAVE_ID << 16) | SDAM16_MEM_030) +#define SDAM16_OS_TYPE_MASK 0x01 /* Bit 0: OSType */ +#define SDAM16_BOOT_REASON_MASK 0x30 /* Bits 5:4: ADSP boot reason */ +#define SDAM16_INIT_MASK (SDAM16_BOOT_REASON_MASK | SDAM16_OS_TYPE_MASK) +#define OS_TYPE_BOOTLOADER 0x00 +#define BOOT_REASON_FRESHBOOT 0x00 -#define MODE_OUTPUT 0x01 -#define OUTPUT_INVERT 0x80 -#define PERPH_EN 0x80 +/* + * SDAM15_MEM_061 (SPMI address 0x7E7D) - SetMaxPwrReq_BattSts register + * Bit 6 - DEAD_BATT_STS + */ +#define SDAM15_MEM_061_ADDR 0x7E7D +#define DEAD_BATT_STS BIT(6) #define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */ -#define CHARGING_RAIL_STABILIZATION_DELAY_MS 3000 /* 3sec */ +#define CHARGING_RAIL_STABILIZATION_DELAY_MS 5000 /* 5sec */ +#define LOW_BATTERY_CHARGING_LOOP_EXIT_MS (3 * 60 * 1000) /* 3min */ #define DELAY_CHARGING_ACTIVE_LB_MS 4000 /* 4sec */ enum charging_status { @@ -54,14 +75,46 @@ enum charging_status { CHRG_ENABLE, }; +static struct sdam_config { +uint32_t addr; +uint8_t mask; +uint8_t value; +} default_sdam_config[] = { + {PMIC_PD_NEGOTIATION_FLAG, SKIP_PORT_RESET, 0}, + {SDAM15_MEM_061_ADDR, DEAD_BATT_STS, 0}, + {PMIC0_SDAM16_MEM_030, SDAM16_INIT_MASK, (BOOT_REASON_FRESHBOOT << 4) | OS_TYPE_BOOTLOADER}, +#if CONFIG(DAM_SINK_SENSOR_Z1_OPTIMIZATION) + {PMIC_SDAM3_PSI_VARIANT_MAJOR, 0xFF, PMIC_PSI_WORKAROUND_ENABLE}, +#endif +}; + +/* + * Initialize SDAM to default values at boot + */ +void init_sdam_config(void) +{ + printk(BIOS_INFO, "Initializing SDAM config at boot\n"); + size_t count = ARRAY_SIZE(default_sdam_config); + for (size_t i = 0; i < count; i++) + spmi_rmw8(default_sdam_config[i].addr, default_sdam_config[i].mask, + default_sdam_config[i].value); +} + static int get_battery_icurr_ma(void) { /* Read battery i-current value */ - int icurr = spmi_read8(SMB1_CHGR_CHARGING_FCC); - if (icurr <= 0) - icurr = spmi_read8(SMB2_CHGR_CHARGING_FCC); - if (icurr < 0) + mdelay(5); + int icurr = spmi_read8_safe(SMB1_CHGR_CHARGING_FCC); + if (icurr <= 0) { + mdelay(5); + icurr = spmi_read8_safe(SMB2_CHGR_CHARGING_FCC); + } + + /* Final safety: if both failed (still negative), treat as 0 */ + if (icurr < 0) { + printk(BIOS_ERR, "Critical: Both SMB registers failed to read.\n"); icurr = 0; + } icurr *= 50; return icurr; @@ -130,6 +183,8 @@ void launch_charger_applet(void) static const long charging_enable_timeout_ms = CHARGING_RAIL_STABILIZATION_DELAY_MS; struct stopwatch sw; + bool has_crossed_threshold = false; + bool has_entered_dead_battery_mode = false; printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__); @@ -158,10 +213,35 @@ void launch_charger_applet(void) } printk(BIOS_INFO, "Charging ready after %lld ms\n", stopwatch_duration_msecs(&sw)); + static const long low_battery_charging_timeout_ms = LOW_BATTERY_CHARGING_LOOP_EXIT_MS; + uint32_t capacity; + if (google_chromeec_read_batt_remaining_capacity(&capacity) < 0) { + printk(BIOS_WARNING, "Failed to get battery capacity\n"); + return; + } + /* + * If the remaining battery is less than + * DEAD_BATT_CHG_THRESHOLD_MAH threshold, enter low-battery + * charging mode and start a timeout timer to come out from dead battery charging + * mode. + */ + if (capacity <= DEAD_BATT_CHG_THRESHOLD_MAH) { + has_entered_dead_battery_mode = true; + stopwatch_init_msecs_expire(&sw, low_battery_charging_timeout_ms); + } + do { /* Add static delay before reading the charging applet pre-requisites */ mdelay(DELAY_CHARGING_APPLET_MS); + if (has_entered_dead_battery_mode) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Issuing power-off to come out from" + " dead battery charging mode.\n"); + google_chromeec_ap_poweroff(); + } + } + /* * Issue a shutdown if not charging. */ @@ -187,7 +267,13 @@ void launch_charger_applet(void) do_board_reset(); } - /* TODO: add Tsense support and issue a shutdown in the event of temperature trip */ + /* Issue a shutdown in the event of temperature trip */ + qcom_tsens_monitor_all(&has_crossed_threshold); + if (has_crossed_threshold) { + printk(BIOS_INFO, "Issuing power-off due to temperature trip.\n"); + google_chromeec_offmode_heartbeat(); + google_chromeec_ap_poweroff(); + } } while (true); } @@ -200,12 +286,8 @@ void configure_parallel_charging(void) return; printk(BIOS_INFO, "Configure parallel charging support\n"); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_EN_CTL), PERPH_EN); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_MODE_CTL), MODE_OUTPUT); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_EN_CTL), PERPH_EN); - spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_MODE_CTL), MODE_OUTPUT); + pmic_gpio_output(PMIC_F_SLAVE_ID, PMIC_F_GPIO_07, true); + pmic_gpio_output(PMIC_F_SLAVE_ID, PMIC_F_GPIO_09, true); } /* @@ -217,8 +299,12 @@ void configure_debug_access_port(void) return; printk(BIOS_INFO, "Enable support of source and sink modes for debug access port\n"); - spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG, EN_DEBUG_ACCESS_SRC); - spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK); + spmi_write8(SMBx_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG(CONFIG_DAP_SMB_SLAVE_ID), + EN_DEBUG_ACCESS_SRC); + spmi_write8(SMBx_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG(CONFIG_DAP_SMB_SLAVE_ID), + EN_DEBUG_ACCESS_SNK); + spmi_write8(SMBx_SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS(CONFIG_DAP_SMB_SLAVE_ID), + EN_SWITCHER_DAM_500); } /* @@ -239,8 +325,8 @@ void enable_slow_battery_charging(void) { /* Configure FCC and enable charging */ printk(BIOS_INFO, "Use slow charging without fast charge support\n"); - spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA); - spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA); + spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_3A_STEP_50MA); + spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_3A_STEP_50MA); spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE); spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE); } @@ -256,3 +342,47 @@ void disable_slow_battery_charging(void) spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_DISABLE); spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_DISABLE); } + +/* + * Instruct ADSP to skip type-c port resets + */ +static void adsp_skip_port_reset(void) +{ + uint8_t flags = (uint8_t)spmi_read8(PMIC_PD_NEGOTIATION_FLAG); + spmi_write8(PMIC_PD_NEGOTIATION_FLAG, flags | SKIP_PORT_RESET); + printk(BIOS_INFO, "Configured ADSP to avoid port resets\n"); +} + +/* + * Enable fast battery charging with ADSP support. + * + * This function loads ADSP firmware and configures fast charging. + */ +void enable_fast_battery_charging(void) +{ + adsp_skip_port_reset(); + + /* Load ADSP firmware first */ + adsp_fw_load(); + + /* Bring up LPASS/QDSP6 (ADSP) for ADSP-dependent charging support */ + if (lpass_bring_up() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS bring-up failed; skipping fast charging.\n"); + } +} + +bool platform_get_battery_soc_information(uint32_t *batt_pct) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return false; + + if (google_chromeec_read_batt_state_of_charge(batt_pct)) + return false; + + return true; +} + +void configure_dead_battery_boot(void) +{ + spmi_rmw8(SDAM15_MEM_061_ADDR, DEAD_BATT_STS, DEAD_BATT_STS); +} diff --git a/src/mainboard/google/bluey/chromeos-nogsc.fmd b/src/mainboard/google/bluey/chromeos-nogsc.fmd index cd3caa84f20..0cd7b162ecf 100644 --- a/src/mainboard/google/bluey/chromeos-nogsc.fmd +++ b/src/mainboard/google/bluey/chromeos-nogsc.fmd @@ -39,7 +39,11 @@ FLASH@0x0 CONFIG_ROM_SIZE { RW_LEGACY(CBFS) +#if CONFIG_QC_QDUTT_ENABLE + RW_UNUSED 2308K + RW_QDUTT 1536K +#else RW_UNUSED 3840K - - RW_CDT 256K + RW_CDT 4K +#endif } diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c index e8609d4c06c..4751c8b3869 100644 --- a/src/mainboard/google/bluey/chromeos.c +++ b/src/mainboard/google/bluey/chromeos.c @@ -15,9 +15,9 @@ void setup_chromeos_gpios(void) if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) { gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) { gpio_output(GPIO_FPMCU_BOOT0, 0); - gpio_output(GPIO_EN_FP_RAILS, 0); gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP); } } @@ -30,6 +30,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) #if CONFIG(EC_GOOGLE_CHROMEEC) {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), "EC interrupt"}, +#endif + {GPIO_PANEL_POWER_ON.addr, ACTIVE_HIGH, gpio_get(GPIO_PANEL_POWER_ON), + "Panel VDD en"}, +#if CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHSCREEN_POWER + {GPIO_TS_POWER_EN.addr, ACTIVE_HIGH, gpio_get(GPIO_TS_POWER_EN), + "Panel VTSP en"}, #endif #if CONFIG(TPM_GOOGLE_TI50) {GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT), diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd index b70b49811df..68ae38a12f7 100644 --- a/src/mainboard/google/bluey/chromeos.fmd +++ b/src/mainboard/google/bluey/chromeos.fmd @@ -38,7 +38,12 @@ FLASH@0x0 CONFIG_ROM_SIZE { RW_FWID_B 256 } - RW_UNUSED 4M - RW_LEGACY(CBFS) + +#if CONFIG_QC_QDUTT_ENABLE + RW_UNUSED 2560K + RW_QDUTT 1536K +#else + RW_UNUSED 4M +#endif } diff --git a/src/mainboard/google/bluey/display.c b/src/mainboard/google/bluey/display.c new file mode 100644 index 00000000000..287f252bdd0 --- /dev/null +++ b/src/mainboard/google/bluey/display.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" +#include "display.h" + +#define BATTERY_CHARGING_SPLASH_TIMEOUT_MS 5000 +static struct stopwatch splash_sw; + +/* Threshold for selecting lower-resolution assets */ +#define FHD_WIDTH_THRESHOLD 1920 + +static struct { + uint32_t x_res; +} cached_display_params; + +/* + * Helper to determine if the current panel is low-resolution (<= FHD). + */ +static bool is_low_res_panel(void) +{ + return cached_display_params.x_res <= FHD_WIDTH_THRESHOLD; +} + +/* + * Mainboard-specific override for logo filenames. + */ +const char *mainboard_bmp_logo_filename(void) +{ + if (is_low_res_panel()) + return "cb_plus_logo.bmp"; + + return "cb_logo.bmp"; +} + +#if CONFIG(PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO) +bool platform_use_secondary_logo(void) +{ + return is_low_res_panel(); +} +#endif + +static void edp_enable_backlight(void) +{ + /* Enable backlight PWM */ + if (CONFIG(MAINBOARD_HAS_BACKLIGHT_PWM)) + pmic_gpio_output(BACKLIGHT_PWM_PMIC_ID, BACKLIGHT_PWM_PMIC_GPIO, true); + + /* Enable backlight */ + pmic_gpio_output(BACKLIGHT_CONTROL_PMIC_ID, BACKLIGHT_CONTROL_PMIC_GPIO, true); +} + +static void qcom_mdss_edp_init(struct edid *edid, uintptr_t fb_addr) +{ + if (edp_ctrl_init(edid) != CB_SUCCESS) + return; + + configure_vbif_qos(); + mdss_layer_mixer_setup(edid); + mdss_source_pipe_config(edid, fb_addr); + + intf_tg_setup(edid); + intf_fetch_start_config(edid); + + merge_3d_active(edid); +} + +static void qcom_mdp_start(uintptr_t fb_addr) +{ + stopwatch_init_msecs_expire(&splash_sw, BATTERY_CHARGING_SPLASH_TIMEOUT_MS); + + write32(&mdp_intf->timing_eng_enable, 1); +} + +void display_stop(void) +{ + if (!get_lb_framebuffer()) + return; + + while (!stopwatch_expired(&splash_sw)) + mdelay(100); + + write32(&mdp_intf->timing_eng_enable, 0); + mdelay(20); + write32(&edp_ahbclk->sw_reset, 1); + mdelay(20); + write32(&edp_ahbclk->sw_reset, 0); + + /* Disable backlight */ + pmic_gpio_output(BACKLIGHT_CONTROL_PMIC_ID, BACKLIGHT_CONTROL_PMIC_GPIO, false); + + /* Disable backlight PWM */ + if (CONFIG(MAINBOARD_HAS_BACKLIGHT_PWM)) + pmic_gpio_output(BACKLIGHT_PWM_PMIC_ID, BACKLIGHT_PWM_PMIC_GPIO, false); + + /* Panel power off */ + gpio_output(GPIO_PANEL_POWER_ON, 0); + + /* Disable power for Touchscreen if available */ + if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHSCREEN_POWER) + gpio_output(GPIO_TS_POWER_EN, 0); +} + +static void display_logo(enum lb_fb_orientation orientation, uintptr_t fb_addr, + const struct edid *edid) +{ + if (!CONFIG(BMP_LOGO) || !fb_addr) + return; + + memset((void *)fb_addr, 0, edid->bytes_per_line * edid->y_resolution); + + struct logo_config config = { + .panel_orientation = orientation, + .halignment = FW_SPLASH_HALIGNMENT_CENTER, + .valignment = FW_SPLASH_VALIGNMENT_CENTER, + .logo_bottom_margin = is_low_res_panel() ? 100 : 200, + }; + render_logo_to_framebuffer(&config); + + qcom_mdp_start(fb_addr); + + edp_enable_backlight(); + + timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED); + + printk(BIOS_DEBUG, "Firmware Splash Screen : Enabled\n"); + + elog_add_event_byte(ELOG_TYPE_FW_SPLASH_SCREEN, 1); +} + +void display_startup(void) +{ + if (!display_init_required() || (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch())) { + printk(BIOS_INFO, "Skipping display init.\n"); + return; + } + + struct edid edid = {}; + struct fb_info *fb; + uintptr_t fb_addr = (REGION_SIZE(framebuffer)) ? (uintptr_t)_framebuffer : 0; + enum lb_fb_orientation orientation = LB_FB_ORIENTATION_NORMAL; + + /* Initialize RPMh subsystem and display power rails */ + if (display_rpmh_init() != CB_SUCCESS) + return; + + enable_mdss_clk(); + qcom_mdss_edp_init(&edid, fb_addr); + if (edid.mode.ha == 0) + return; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + fb = fb_new_framebuffer_info_from_edid(&edid, fb_addr); + fb_set_orientation(fb, orientation); + + cached_display_params.x_res = edid.x_resolution; + display_logo(orientation, fb_addr, &edid); +} diff --git a/src/mainboard/google/bluey/display.h b/src/mainboard/google/bluey/display.h new file mode 100644 index 00000000000..b90ceb1a1ca --- /dev/null +++ b/src/mainboard/google/bluey/display.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_BLUEY_DISPLAY_H__ +#define _MAINBOARD_BLUEY_DISPLAY_H__ + +void display_startup(void); +void display_stop(void); + +#endif // _MAINBOARD_BLUEY_DISPLAY_H__ diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c index 891967f3e39..57e58621320 100644 --- a/src/mainboard/google/bluey/mainboard.c +++ b/src/mainboard/google/bluey/mainboard.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -12,16 +11,23 @@ #include #include #include +#include +#include #include #include +#include #include #include +#include #include #include #include -#include "board.h" -#include +#include #include +#include + +#include "board.h" +#include "display.h" #define C0_RETIMER_I2C_BUS 0x03 #define C1_RETIMER_I2C_BUS 0x07 @@ -70,7 +76,8 @@ static bool is_low_power_boot_with_charger(void) bool ret = false; enum boot_mode_t boot_mode = get_boot_mode(); if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) || - (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING)) + (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING) || + (boot_mode == LB_BOOT_MODE_RTC_WAKE)) ret = true; return ret; @@ -78,8 +85,12 @@ static bool is_low_power_boot_with_charger(void) static void enable_usb_camera(void) { - gpio_output(GPIO_USB_CAM_RESET_L, 1); - gpio_output(GPIO_USB_CAM_ENABLE, 1); + if (CONFIG(MAINBOARD_HAS_CAMERA_VIA_USB)) { + gpio_output(GPIO_USB_CAM_RESET_L, 1); + gpio_output(GPIO_USB_CAM_ENABLE, 1); + } else { + gpio_output(GPIO_USB_CAM_ENABLE, 0); + } } static void setup_usb_typec(void) @@ -95,12 +106,8 @@ static void setup_usb_typec(void) static void setup_audio_gpios(void) { - gpio_configure_no_egpio(GPIO_SNDW_AMP_0_ENABLE, GPIO_FUNC_GPIO, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); - gpio_set(GPIO_SNDW_AMP_0_ENABLE, 0); - gpio_configure_no_egpio(GPIO_SNDW_AMP_1_ENABLE, GPIO_FUNC_GPIO, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); - gpio_set(GPIO_SNDW_AMP_1_ENABLE, 0); + gpio_output(GPIO_SNDW_AMP_0_ENABLE, 0); + gpio_output(GPIO_SNDW_AMP_1_ENABLE, 0); gpio_configure_no_egpio(GPIO_SNDW_0_SCL, GPIO_FUN_SNDW_0_SCL, GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); gpio_configure_no_egpio(GPIO_SNDW_0_SDA, GPIO_FUN_SNDW_0_SDA, @@ -115,12 +122,10 @@ static void setup_audio(void) static void setup_usb(void) { setup_usb_typec(); - - if (CONFIG(MAINBOARD_HAS_CAMERA_VIA_USB)) - enable_usb_camera(); + enable_usb_camera(); } -static void setup_usb_late(void *unused) +static void setup_usb_late(void) { /* Skip USB initialization if boot mode is "low-battery" or "off-mode charging"*/ if (is_low_power_boot_with_charger()) @@ -129,8 +134,6 @@ static void setup_usb_late(void *unused) setup_usb_host0(); } -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, setup_usb_late, NULL); - void lb_add_boot_mode(struct lb_header *header) { if (!CONFIG(EC_GOOGLE_CHROMEEC)) @@ -153,19 +156,12 @@ bool mainboard_needs_pcie_init(void) return true; } -static void display_startup(void) +#if CONFIG(PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR) +bool platform_is_off_mode_charging_active(void) { - if (!display_init_required() || (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch())) { - printk(BIOS_INFO, "Skipping display init.\n"); - return; - } - - /* Initialize RPMh subsystem and display power rails */ - if (display_rpmh_init() != CB_SUCCESS) - return; - - enable_mdss_clk(); + return (get_boot_mode() == LB_BOOT_MODE_OFFMODE_CHARGING); } +#endif static void trigger_critical_battery_shutdown(void) { @@ -179,6 +175,25 @@ static void trigger_critical_battery_shutdown(void) google_chromeec_ap_poweroff(); } +static bool board_support_dead_battery_charging(void) +{ + uint32_t capacity; + + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return false; + + if (google_chromeec_read_batt_remaining_capacity(&capacity) < 0) { + printk(BIOS_WARNING, "Failed to get battery capacity; defaulting to slow charging\n"); + return true; + } + + /* + * If the remaining battery capacity is less than or equal to the + * threshold, set dead battery charging mode. + */ + return capacity <= DEAD_BATT_CHG_THRESHOLD_MAH; +} + /* * Handle charging and UI states for low-power or off-mode boot scenarios. * This function handles the transitions needed when the device is powered @@ -186,8 +201,13 @@ static void trigger_critical_battery_shutdown(void) */ static void handle_low_power_charging_boot(void) { - /* TODO: enable fast charging */ - enable_slow_battery_charging(); + if (!pll_init_and_set(apss_ncc0, L_VAL_710P4MHz)) + printk(BIOS_DEBUG, "CPU Frequency set to 710MHz\n"); + + if (board_support_dead_battery_charging()) + configure_dead_battery_boot(); + + enable_fast_battery_charging(); /* * Disable the lightbar for Low-Battery or Off-Mode charging sequences. @@ -197,30 +217,49 @@ static void handle_low_power_charging_boot(void) if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) google_chromeec_lightbar_off(); + display_stop(); + /* Boot to charging applet; if this fails, the applet should trigger a reset */ launch_charger_applet(); } -static void mainboard_init(struct device *dev) +static void load_qc_se_firmware_early(void) +{ + /* ADSP I2C (Charger/Fuel gauge) */ + qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED); + + gpi_firmware_load(QUP_0_GSI_BASE); + gpi_firmware_load(QUP_1_GSI_BASE); + gpi_firmware_load(QUP_2_GSI_BASE); +} + +static void mainboard_init(void *chip_info) { configure_parallel_charging(); configure_debug_access_port(); - display_startup(); + enum boot_mode_t boot_mode = get_boot_mode(); + + /* Do early display init for low/off-mode charging */ + if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY) || + (boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) || + (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING)) { + /* + * Manual delay for panel readiness; required because standard SOC IP + * initialization is bypassed to prioritize fast-charging boot speeds. + */ + mdelay(250); + display_startup(); + } /* * Low-battery boot indicator is done. Therefore, power off if battery * is critical and not charging */ - if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY) + if (boot_mode == LB_BOOT_MODE_LOW_BATTERY) trigger_critical_battery_shutdown(); - /* ADSP I2C (Charger/Fuel gauge) */ - qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED); - - gpi_firmware_load(QUP_0_GSI_BASE); - gpi_firmware_load(QUP_1_GSI_BASE); - gpi_firmware_load(QUP_2_GSI_BASE); + load_qc_se_firmware_early(); configure_parallel_charging_late(); @@ -229,7 +268,10 @@ static void mainboard_init(struct device *dev) handle_low_power_charging_boot(); halt(); } +} +static void load_qc_se_firmware_late(void) +{ /* * Load console UART QUP firmware. * This is required even if coreboot's serial output is disabled. @@ -251,33 +293,76 @@ static void mainboard_init(struct device *dev) if (!CONFIG(MAINBOARD_NO_USB_A_PORT)) qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */ + qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */ +} + +static void mainboard_late_init(struct device *dev) +{ + load_qc_se_firmware_late(); +} + +void mainboard_soc_init(void) +{ + /* Setup USB related initial config */ + setup_usb(); + + enum boot_mode_t boot_mode = get_boot_mode(); + + if (boot_mode == LB_BOOT_MODE_NORMAL || boot_mode == LB_BOOT_MODE_NO_BATTERY) + display_startup(); /* Enable touchpad power */ if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER) gpio_output(GPIO_TP_POWER_EN, 1); - /* - * Deassert FPMCU reset. Power applied in romstage - * has now stabilized. - */ + /* Deassert FPMCU reset. Power applied in romstage has now stabilized. */ if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) gpio_output(GPIO_FP_RST_L, 1); - /* Setup USB related initial config */ - setup_usb(); - /* Setup audio related initial config */ setup_audio(); + + /* Setup USB related late config */ + setup_usb_late(); } static void mainboard_enable(struct device *dev) { - dev->ops->init = &mainboard_init; + dev->ops->init = &mainboard_late_init; } struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .init = mainboard_init, }; + +void fw_config_get_mainboard_override(uint64_t *fw_config) +{ + if (!CONFIG(SOC_QUALCOMM_CDT)) + return; + + uint16_t soc_id; + switch (platform_get_soc_id()) { + case SOC_ID_HAMOA: + soc_id = HAMOA_ID_SCP; + break; + case SOC_ID_X1P42100: + soc_id = X1P42100_ID_SCP; + break; + default: + printk(BIOS_WARNING, "CDT: Unknown SoC ID, skipping fw_config override\n"); + return; + } + + uint8_t platform_type = cdt_get_platform_id(); + uint32_t soc_platform_id = ((uint32_t)soc_id << 16) | platform_type; + + printk(BIOS_INFO, "CDT: soc_platform_id=0x%08x (soc_id=0x%04x, platform_type=0x%02x)\n", + soc_platform_id, soc_id, platform_type); + + *fw_config = soc_platform_id; +} diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c index 891809f0453..206c8c37b88 100644 --- a/src/mainboard/google/bluey/romstage.c +++ b/src/mainboard/google/bluey/romstage.c @@ -1,21 +1,37 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include "board.h" #include #include #include #include +#include #include #include +#include #include #include +#include #include +#include #include #include +#include #include +#define DELAY_FOR_SHIP_MODE 11000 /* 11sec */ +#define IMEM_COOKIE_TYPE_OFFSET 108 + static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL; +static bool battery_present = true; +static bool battery_below_threshold = false; +static int32_t battery_cfet_status = 1; /* Active C-FET */ +static int32_t battery_dfet_status = 1; /* Active D-FET */ +static bool battery_needs_recovery = false; +static bool battery_is_cutoff = false; +static bool chipset_dload_mode_active = false; /* Mode for crashlog */ /* * is_off_mode - Check if the system is booting due to an off-mode power event. @@ -40,9 +56,13 @@ static enum boot_mode_t set_boot_mode(void) enum boot_mode_t boot_mode_new; - if (is_off_mode() && google_chromeec_is_battery_present()) { + if (!battery_present) { + boot_mode_new = LB_BOOT_MODE_NO_BATTERY; + } else if (google_chromeec_is_rtc_event()) { + boot_mode_new = LB_BOOT_MODE_RTC_WAKE; + } else if (is_off_mode()) { boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING; - } else if (google_chromeec_is_below_critical_threshold()) { + } else if (battery_below_threshold) { if (google_chromeec_is_charger_present()) boot_mode_new = LB_BOOT_MODE_LOW_BATTERY_CHARGING; else @@ -68,8 +88,8 @@ static bool is_pd_sync_required(void) if (!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED))) return false; - if (!(ec_events & manual_pwron_event_mask) || - google_chromeec_is_below_critical_threshold() || !google_chromeec_is_battery_present()) + if (!(ec_events & manual_pwron_event_mask) || battery_below_threshold || + !battery_present || !battery_cfet_status) return true; return false; @@ -99,16 +119,8 @@ int qclib_mainboard_override(struct qclib_cb_if_table *table) table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION; else table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION; - return 0; -} -static void platform_dump_battery_soc_information(void) -{ - uint32_t batt_pct; - if (google_chromeec_read_batt_state_of_charge(&batt_pct)) - printk(BIOS_WARNING, "Failed to get battery level\n"); - else - printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct); + return 0; } static void early_setup_usb_typec(void) @@ -135,50 +147,197 @@ static void platform_init_lightbar(void) * in a previous boot without a subsequent EC reset. */ google_chromeec_lightbar_on(); +} + +static void edp_configure_gpios(void) +{ + /* Ensure enabling power for Touchscreen if available */ + if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHSCREEN_POWER) + gpio_output(GPIO_TS_POWER_EN, 1); + + /* Panel power on GPIO enable */ + gpio_output(GPIO_PANEL_POWER_ON, 1); + + /* Panel HPD GPIO enable */ + gpio_input(GPIO_PANEL_HPD); +} + +/** + * Update and cache battery status from the EC. + * This should be called once, early in the boot process, + * after the EC is reachable. + */ +static void update_battery_status(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + /* + * Force a board reset if the EC reports invalid battery data and crashlog mode + * is not set to prevent downstream configuration issues with bad telemetry. + */ + if (!google_chromeec_is_battery_data_valid() && !chipset_dload_mode_active) { + printk(BIOS_INFO, "Battery data invalid! doing board reset.\n"); + do_board_reset(); + } + + struct ec_response_battery_get_misc_info misc_info; + bool misc_info_valid = false; + + battery_present = google_chromeec_is_battery_present(); + battery_below_threshold = google_chromeec_is_below_critical_threshold(); + + if (battery_present && (google_chromeec_get_battery_misc_info(&misc_info) == 0)) { + battery_cfet_status = misc_info.cfet_status; + battery_dfet_status = misc_info.dfet_status; + misc_info_valid = true; + } else { + printk(BIOS_WARNING, "Failed to get battery FET status from EC\n"); + battery_cfet_status = -1; + battery_dfet_status = -1; + } /* - * Only alert the user (set LED to red in color) if the lid is closed and the battery - * is critically low without AC power. + * SHIP MODE RECOVERY HANDLER: + * Triggered ONLY when the battery info was successfully read, + * and BOTH FETs are explicitly 0 (indicating a locked BMS). */ - if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() && - google_chromeec_is_critically_low_on_battery()) - google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00); + battery_needs_recovery = misc_info_valid && (battery_cfet_status == 0) + && (battery_dfet_status == 0); + + /* + * BATTERY CUTOFF / DISCONNECT DETECTION: + * Triggered when the hardware reports no battery present AND + * the EC FET status read failed (returning -1). + */ + battery_is_cutoff = (battery_cfet_status == -1) && (battery_dfet_status == -1); } -void platform_romstage_main(void) +/* Perform romstage early hardware initialization */ +static void mainboard_setup_peripherals_early(void) { platform_init_lightbar(); + update_battery_status(); + + /* + * Power on NVMe early so that the DDR init and other operations + * that follow provide an organic >50ms delay before PCIe PERST + * de-assertion in platform_romstage_postram(), satisfying the + * NVMe spec requirement without a static mdelay(). + */ + gcom_pcie_power_on_ep(); + + edp_configure_gpios(); + + /* This GPIO has external pullup hence disable default PD */ + gpio_input(GPIO_LID_OPEN_S3); + /* Setup early USB related config */ early_setup_usb(); /* Watchdog must be checked first to avoid erasing watchdog info later. */ check_wdog(); +} - if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL)) - platform_dump_battery_soc_information(); +/* + * Perform romstage late hardware initialization based on boot mode. + * Handles PCIe host setup and fingerprint sensor power rails. + */ +static void mainboard_setup_peripherals_late(int mode) +{ + if (!chipset_dload_mode_active) { + /* Perform PCIe setup early in async mode if supported to save 100ms */ + if (mode == LB_BOOT_MODE_NORMAL || mode == LB_BOOT_MODE_NO_BATTERY) + qcom_setup_pcie_host(NULL); + else + gcom_pcie_power_off_ep(); + } + + /* + * Enable fingerprint power rail early for stability prior to + * its reset being deasserted in ramstage. + * Requires >=200ms delay after its pin was driven low in bootblock. + */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) { + if (mode == LB_BOOT_MODE_NORMAL || mode == LB_BOOT_MODE_NO_BATTERY) + gpio_output(GPIO_EN_FP_RAILS, 1); + } +} + +static void handle_battery_shipping_recovery(bool board_reset) +{ + printk(BIOS_INFO, "==================================================\n"); + printk(BIOS_INFO, "Device has entered into shipping recovery mode.\n"); + printk(BIOS_INFO, "Please wait ...\n"); + printk(BIOS_INFO, "==================================================\n"); - if (!qclib_check_dload_mode()) + enable_slow_battery_charging(); + mdelay(DELAY_FOR_SHIP_MODE); + + if (board_reset) { + printk(BIOS_INFO, "Issuing board reset\n"); + do_board_reset(); + } + + /* Disable charging where `board_reset` is not allowed */ + disable_slow_battery_charging(); +} + +static bool check_ramdump_mode_is_set(void) +{ + if (!CONFIG(QC_RAMDUMP_ENABLE)) + return false; + + uint32_t rawdump_val = read32(_shared_imem + IMEM_COOKIE_TYPE_OFFSET); + + if (rawdump_val == 0x1) { + printk(BIOS_DEBUG, "Ramdump mode detected: 0x%x\n", rawdump_val); + return true; + } + + printk(BIOS_DEBUG, "Ramdump mode not enabled (value: 0x%x)\n", rawdump_val); + + return false; +} + +void platform_romstage_main(void) +{ + static bool ramdump_mode = false; + + if (check_ramdump_mode_is_set()) + ramdump_mode = true; + + chipset_dload_mode_active = qclib_check_dload_mode(); + + mainboard_setup_peripherals_early(); + + if (!chipset_dload_mode_active) shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); + /* Recovery from battery shipping mode */ + if (battery_needs_recovery || battery_is_cutoff) + handle_battery_shipping_recovery(battery_needs_recovery); + + init_sdam_config(); + /* Underlying PMIC registers are accessible only at this point */ set_boot_mode(); - aop_fw_load_reset(); + if (!chipset_dload_mode_active) + aop_fw_load_reset(); + + mainboard_setup_peripherals_late(boot_mode); qclib_rerun(); - /* - * Enable this power rail now for FPMCU stability prior to - * its reset being deasserted in ramstage. This applies - * when MAINBOARD_HAS_FINGERPRINT_VIA_SPI Kconfig is enabled. - * Requires >=200ms delay after its pin was driven low in bootblock. - */ - if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) - gpio_output(GPIO_EN_FP_RAILS, 1); + if (ramdump_mode) { + printk(BIOS_INFO, "Issuing board reset to come out of Ramdump mode\n"); + do_board_reset(); + } } void platform_romstage_postram(void) diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 8847f33e72e..2af87486b1b 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -81,6 +81,7 @@ config BOARD_GOOGLE_BROX_EC_ISH config BOARD_GOOGLE_LOTSO select BOARD_GOOGLE_BASEBOARD_BROX select CHROMEOS_WIFI_SAR if CHROMEOS + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS @@ -94,6 +95,7 @@ config BOARD_GOOGLE_JUBILANT select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_ALC1015 select DRIVERS_I2C_SX9324 + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS diff --git a/src/mainboard/google/brox/cfr.c b/src/mainboard/google/brox/cfr.c index 2025ad32ee3..e5843e501e0 100644 --- a/src/mainboard/google/brox/cfr.c +++ b/src/mainboard/google/brox/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 89045163de1..276903e0a55 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -77,7 +77,7 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_sdi_enable[0]" = "true" register "pch_hda_sdi_enable[1]" = "true" register "pch_hda_audio_link_hda_enable" = "1" diff --git a/src/mainboard/google/brox/variants/jubilant/data.vbt b/src/mainboard/google/brox/variants/jubilant/data.vbt index 716d09f557d..49e36bd1db0 100644 Binary files a/src/mainboard/google/brox/variants/jubilant/data.vbt and b/src/mainboard/google/brox/variants/jubilant/data.vbt differ diff --git a/src/mainboard/google/brox/variants/lotso/data.vbt b/src/mainboard/google/brox/variants/lotso/data.vbt new file mode 100644 index 00000000000..54cb7a714b6 Binary files /dev/null and b/src/mainboard/google/brox/variants/lotso/data.vbt differ diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk index e38115911fd..d5332d9e0bc 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt index c27f7926ca8..e667d7e19d7 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt @@ -13,3 +13,4 @@ H58G56CK8BX146 2 (0010) K3KL8L80EM-MGCU 2 (0010) H58G56BK7BX068 3 (0011) K3KL8L80CM-MGCT 3 (0011) +MT62F1G32D2DS-031RF WT:C 4 (0100) diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt index 7df5ad3b41b..2ff8b79738f 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt @@ -10,7 +10,6 @@ # Part Name K3KL6L60GM-MGCT -K3KL8L80CM-MGCT H9JCNNNBK3MLYR-N6E K3KL8L80DM-MGCU MT62F1G32D2DS-023 WT:C @@ -18,3 +17,5 @@ H58G56BK8BX068 H58G56CK8BX146 K3KL8L80EM-MGCU H58G56BK7BX068 +K3KL8L80CM-MGCT +MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c7fad434f4d..c15ec34eb43 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -38,12 +38,12 @@ config BOARD_GOOGLE_BRYA_COMMON select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 select SOC_INTEL_STORE_ISH_FW_VERSION if DRIVERS_INTEL_ISH config BOARD_GOOGLE_BASEBOARD_BRYA @@ -55,7 +55,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_BRASK @@ -101,11 +101,11 @@ config BOARD_GOOGLE_BASEBOARD_NISSA select MAINBOARD_HAS_EARLY_LIBGFXINIT select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_MMC_OVERRIDE select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC && !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_TI50 - select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_BASEBOARD_TRULO def_bool n @@ -124,7 +124,7 @@ config BOARD_GOOGLE_BASEBOARD_TRULO select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE select SOC_INTEL_TWINLAKE - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_TI50 config BOARD_GOOGLE_AGAH @@ -139,8 +139,8 @@ config BOARD_GOOGLE_AGAH config BOARD_GOOGLE_ANAHERA select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT @@ -148,21 +148,21 @@ config BOARD_GOOGLE_ANAHERA config BOARD_GOOGLE_ANAHERA4ES select BOARD_GOOGLE_BASEBOARD_BRYA select DEFAULT_ADL_NEM - select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_ANRAGGAR select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT - select CHROMEOS_WIFI_SAR if CHROMEOS - select ENFORCE_MEM_CHANNEL_DISABLE config BOARD_GOOGLE_AURASH select BOARD_GOOGLE_BASEBOARD_BRASK @@ -204,13 +204,16 @@ config BOARD_GOOGLE_CRAASK select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CRAASKOV select BOARD_GOOGLE_BASEBOARD_NISSA - select INTEL_GMA_HAVE_VBT select CHROMEOS_WIFI_SAR if CHROMEOS + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CONSTITUTION select BOARD_GOOGLE_BASEBOARD_BRASK @@ -227,9 +230,20 @@ config BOARD_GOOGLE_CROTA select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_DIRKS select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_MINIPC + +config BOARD_GOOGLE_DIRKSON + select BOARD_GOOGLE_BASEBOARD_NISSA + select ENFORCE_MEM_CHANNEL_DISABLE select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE @@ -240,7 +254,9 @@ config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE + select SYSTEM_TYPE_CONVERTIBLE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_DOMIKA @@ -249,7 +265,9 @@ config BOARD_GOOGLE_DOMIKA select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT select SOC_INTEL_TWINLAKE config BOARD_GOOGLE_FELWINTER @@ -258,6 +276,7 @@ config BOARD_GOOGLE_FELWINTER select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9755 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GAELIN select BOARD_GOOGLE_BASEBOARD_BRASK @@ -270,6 +289,7 @@ config BOARD_GOOGLE_GIMBLE select GOOGLE_DSM_CALIB if VPD select GOOGLE_DSM_PARAM_FILE_NAME if VPD select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GIMBLE4ES select BOARD_GOOGLE_BASEBOARD_BRYA @@ -278,12 +298,13 @@ config BOARD_GOOGLE_GIMBLE4ES select DRIVERS_I2C_MAX98390 select GOOGLE_DSM_CALIB if VPD select GOOGLE_DSM_PARAM_FILE_NAME if VPD + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GLADIOS select BOARD_GOOGLE_BASEBOARD_BRASK select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE @@ -295,17 +316,20 @@ config BOARD_GOOGLE_GLASSWAY select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_GOTHRAX select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select HAVE_WWAN_POWER_SEQUENCE - select CHROMEOS_WIFI_SAR if CHROMEOS + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GUREN select BOARD_GOOGLE_BASEBOARD_NISSA @@ -334,6 +358,7 @@ config BOARD_GOOGLE_KALADIN select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_CONVERTIBLE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_KANO @@ -346,6 +371,7 @@ config BOARD_GOOGLE_KANO select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_KINOX select BOARD_GOOGLE_BASEBOARD_BRASK @@ -371,6 +397,7 @@ config BOARD_GOOGLE_JOXER select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENESYSLOGIC_GL9750 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_LISBON select BOARD_GOOGLE_BASEBOARD_BRASK @@ -402,6 +429,7 @@ config BOARD_GOOGLE_MITHRAX select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9755 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_MOLI select BOARD_GOOGLE_BASEBOARD_BRASK @@ -445,8 +473,8 @@ config BOARD_GOOGLE_NOKRIS config BOARD_GOOGLE_NOVA select BOARD_GOOGLE_BASEBOARD_BRASK - select SOC_INTEL_RAPTORLAKE select MEMORY_SOLDERDOWN + select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_OMNIGUL select BOARD_GOOGLE_BASEBOARD_BRYA @@ -474,8 +502,8 @@ config BOARD_GOOGLE_OSIRIS config BOARD_GOOGLE_PIRRHA select BOARD_GOOGLE_BASEBOARD_NISSA - select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_DA7219 + select DRIVERS_INTEL_MIPI_CAMERA config BOARD_GOOGLE_PRIMUS select BOARD_GOOGLE_BASEBOARD_BRYA @@ -496,60 +524,67 @@ config BOARD_GOOGLE_PUJJO select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_SUNDANCE select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA - select DRIVERS_GENERIC_GPIO_KEYS select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PUJJOGATWIN select BOARD_GOOGLE_BASEBOARD_NISSA - select DRIVERS_GENERIC_GPIO_KEYS select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PUJJOLO select BOARD_GOOGLE_BASEBOARD_TRULO select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_GPIO_KEYS - select DRIVERS_INTEL_MIPI_CAMERA - select DRIVERS_I2C_SX9324 select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select DRIVERS_INTEL_MIPI_CAMERA select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PUJJONIRU select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_16384 select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_AUDIO_SOF select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS - select DRIVERS_AUDIO_SOF select ENFORCE_MEM_CHANNEL_DISABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PUJJOCENTO select BOARD_GOOGLE_BASEBOARD_TRULO @@ -566,18 +601,20 @@ config BOARD_GOOGLE_PUJJOCENTO config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_SX9324 + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_QUANDISO2 select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_SX9324 + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT select SOC_INTEL_TWINLAKE @@ -592,6 +629,7 @@ config BOARD_GOOGLE_REDRIX select GOOGLE_DSM_PARAM_FILE_NAME if VPD select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_REDRIX4ES select BOARD_GOOGLE_BASEBOARD_BRYA @@ -602,7 +640,9 @@ config BOARD_GOOGLE_REDRIX4ES select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select GOOGLE_DSM_CALIB if VPD select GOOGLE_DSM_PARAM_FILE_NAME if VPD + select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_RIVEN select BOARD_GOOGLE_BASEBOARD_NISSA @@ -614,6 +654,7 @@ config BOARD_GOOGLE_RIVEN select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_CONVERTIBLE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_RULL @@ -623,6 +664,7 @@ config BOARD_GOOGLE_RULL select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS select ENFORCE_MEM_CHANNEL_DISABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE @@ -630,9 +672,9 @@ config BOARD_GOOGLE_SKOLAS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_NAU8315 select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select DRIVERS_INTEL_MIPI_CAMERA select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE @@ -641,9 +683,9 @@ config BOARD_GOOGLE_SKOLAS4ES select BOARD_GOOGLE_BASEBOARD_BRYA select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select DRIVERS_INTEL_MIPI_CAMERA select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE @@ -657,6 +699,7 @@ config BOARD_GOOGLE_TAEKO select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX if DRIVERS_GENESYSLOGIC_GL9763E select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_TAEKO4ES select BOARD_GOOGLE_BASEBOARD_BRYA @@ -665,6 +708,7 @@ config BOARD_GOOGLE_TAEKO4ES select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_TANIKS select BOARD_GOOGLE_BASEBOARD_BRYA @@ -682,9 +726,11 @@ config BOARD_GOOGLE_TELIKS select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT select SOC_INTEL_TWINLAKE - select ENFORCE_MEM_CHANNEL_DISABLE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_TELITH select BOARD_GOOGLE_BASEBOARD_NISSA @@ -693,9 +739,10 @@ config BOARD_GOOGLE_TELITH select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA + select ENFORCE_MEM_CHANNEL_DISABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE - select ENFORCE_MEM_CHANNEL_DISABLE config BOARD_GOOGLE_TEREID select BOARD_GOOGLE_BASEBOARD_NISSA @@ -721,9 +768,9 @@ config BOARD_GOOGLE_TIVVIKS config BOARD_GOOGLE_TRULO select BOARD_GOOGLE_BASEBOARD_TRULO select SKIP_RAM_ID_STRAPS - select SOC_INTEL_TWINLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select SOC_INTEL_TWINLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_ULDREN @@ -749,8 +796,8 @@ config BOARD_GOOGLE_ULDRENITE config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_CS35L53 + select DRIVERS_INTEL_MIPI_CAMERA select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK_IPU @@ -759,9 +806,9 @@ config BOARD_GOOGLE_VELL config BOARD_GOOGLE_VOLMAR select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS - select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_NAU8825 + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_XIVU @@ -770,12 +817,14 @@ config BOARD_GOOGLE_XIVU select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_XOL select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_DA7219 select DRIVERS_INTEL_ISH + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS @@ -783,8 +832,8 @@ config BOARD_GOOGLE_XOL config BOARD_GOOGLE_YAVIKS select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_MTK_WIFI select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG @@ -798,6 +847,7 @@ config BOARD_GOOGLE_YAVILLA select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT @@ -865,6 +915,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_CRAASKOV default 0x1 if BOARD_GOOGLE_CROTA default 0x0 if BOARD_GOOGLE_DIRKS + default 0x0 if BOARD_GOOGLE_DIRKSON default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_DOMIKA default 0x1 if BOARD_GOOGLE_FELWINTER @@ -955,6 +1006,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_CRAASKOV default 13 if BOARD_GOOGLE_CROTA default 13 if BOARD_GOOGLE_DIRKS + default 13 if BOARD_GOOGLE_DIRKSON default 13 if BOARD_GOOGLE_DOCHI default 13 if BOARD_GOOGLE_DOMIKA default 13 if BOARD_GOOGLE_FELWINTER @@ -1049,6 +1101,7 @@ config MAINBOARD_PART_NUMBER default "Craaskov" if BOARD_GOOGLE_CRAASKOV default "Crota" if BOARD_GOOGLE_CROTA default "Dirks" if BOARD_GOOGLE_DIRKS + default "Dirkson" if BOARD_GOOGLE_DIRKSON default "Dochi" if BOARD_GOOGLE_DOCHI default "Domika" if BOARD_GOOGLE_DOMIKA default "Felwinter" if BOARD_GOOGLE_FELWINTER @@ -1132,6 +1185,7 @@ config VARIANT_DIR default "craaskov" if BOARD_GOOGLE_CRAASKOV default "crota" if BOARD_GOOGLE_CROTA default "dirks" if BOARD_GOOGLE_DIRKS + default "dirkson" if BOARD_GOOGLE_DIRKSON default "dochi" if BOARD_GOOGLE_DOCHI default "yavilla" if BOARD_GOOGLE_DOMIKA default "felwinter" if BOARD_GOOGLE_FELWINTER diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bce6d1c83f1..de17056ae20 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -45,6 +45,9 @@ config BOARD_GOOGLE_CROTA config BOARD_GOOGLE_DIRKS bool "-> Dirks (Acer Chromebox Mini CXM2 (TWL))" +config BOARD_GOOGLE_DIRKSON + bool "-> Dirkson" + config BOARD_GOOGLE_DOCHI bool "-> Dochi (Acer Chromebook Plus Spin 514)" diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c index 31b32749335..27b48c1b349 100644 --- a/src/mainboard/google/brya/cfr.c +++ b/src/mainboard/google/brya/cfr.c @@ -7,12 +7,21 @@ #include #if CONFIG(BOARD_GOOGLE_TANIKS) || CONFIG(BOARD_GOOGLE_TAEKO) +#include enum storage_device { STORAGE_NVME = 0, STORAGE_EMMC = 1, }; +/* Update storage device default value based on fw_config */ +static void update_storage_device(struct sm_object *new) +{ + new->sm_enum.default_value = + (fw_config_get() & FW_CONFIG_FIELD_BOOT_EMMC_MASK_MASK) ? + STORAGE_EMMC : STORAGE_NVME; +} + static const struct sm_object storage_device_opt = SM_DECLARE_ENUM({ .opt_name = "storage_device", .ui_name = "Storage Device", @@ -22,7 +31,8 @@ static const struct sm_object storage_device_opt = SM_DECLARE_ENUM({ { "NVMe SSD", STORAGE_NVME }, { "eMMC", STORAGE_EMMC }, SM_ENUM_VALUE_END }, -}); +}, WITH_CALLBACK(update_storage_device)); + static struct sm_obj_form devices = { .ui_name = "Devices", .obj_list = (const struct sm_object *[]) { @@ -41,6 +51,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index 0d2cd9974bf..f522d86cb81 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -123,6 +123,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME probe STORAGE STORAGE_UNKNOWN end # SSD diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index a444f12c278..90620916291 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -223,6 +223,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tbt_pcie_rp3 on end device ref cnvi_wifi on diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index d54c68d866e..3293061982c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 71dfb54b46c..85f622d47b3 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -68,7 +68,7 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 54046b904b9..c4b1d0124dd 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -50,7 +50,7 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 840c4e778f9..dd608d15213 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -85,7 +85,7 @@ chip soc/intel/alderlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 2fccc243970..0e2c2a7c8e4 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -88,6 +88,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c index ee96c18d458..082dbff8bc5 100644 --- a/src/mainboard/google/brya/variants/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk index da2ad15bbc7..d5dfd9c8a54 100644 --- a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk @@ -5,5 +5,5 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL, H54G56CYRBX247 +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL, H54G56CYRBX247, K4UBE3D4AA-MGCR SPD_SOURCES += spd/lp4x/set-0/spd-10.hex # ID = 2(0b0010) Parts = B3221XM3BDGVI diff --git a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt index f7b781c8cb2..8670771de3d 100644 --- a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ MT53E1G32D2NP-046 WT:B 1 (0001) K4UBE3D4AB-MGCL 1 (0001) H54G56CYRBX247 1 (0001) B3221XM3BDGVI 2 (0010) +K4UBE3D4AA-MGCR 1 (0001) diff --git a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt index 2fc4149f79e..60a70eb48f1 100644 --- a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt @@ -3,3 +3,4 @@ MT53E1G32D2NP-046 WT:B K4UBE3D4AB-MGCL H54G56CYRBX247 B3221XM3BDGVI +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/craask/Makefile.mk b/src/mainboard/google/brya/variants/craask/Makefile.mk index b90c74cd7fa..150df138a5a 100644 --- a/src/mainboard/google/brya/variants/craask/Makefile.mk +++ b/src/mainboard/google/brya/variants/craask/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index b68e406421e..eda5a1157a2 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -17,6 +17,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D11 : EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), + /* E5 : NC ==> GPP_E5_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E5, DN_20K, LOCK_CONFIG), /* E17 : SSD_PLN_L */ PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), /* F12 : WWAN_RST_L */ @@ -73,6 +75,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D11, 1, DEEP), /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* E5 : NC ==> GPP_E5_STRAP */ + PAD_CFG_GPI(GPP_E5, DN_20K, DEEP), }; static const struct pad_config romstage_gpio_table[] = { diff --git a/src/mainboard/google/brya/variants/craask/include/variant/ec.h b/src/mainboard/google/brya/variants/craask/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/craask/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/craask/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/craask/memory.c b/src/mainboard/google/brya/variants/craask/memory.c new file mode 100644 index 00000000000..f5de481ed03 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/memory.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E5 High -> One RAM Chip + * GPP_E5 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E5)) { + /* Disable all other channels except first two on each controller */ + printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory" + "channels except first two on each memory controller.\n"); + return (BIT(2) | BIT(3)); + } + + return 0; +} diff --git a/src/mainboard/google/brya/variants/craask/memory/Makefile.mk b/src/mainboard/google/brya/variants/craask/memory/Makefile.mk index 34d01a6f5fe..84d3ef1b977 100644 --- a/src/mainboard/google/brya/variants/craask/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/craask/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 4(0b0100) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt index e17b510c58e..ab1193c5942 100644 --- a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H9JCNNNBK3MLYR-N6E 1 (0001) K3LKLKL0EM-MGCN 2 (0010) K3LKBKB0BM-MGCP 3 (0011) H9JCNNNCP3MLYR-N6E 0 (0000) +H58G56CK8BX146 4 (0100) diff --git a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt index b08faac3e74..f78ce4598a9 100644 --- a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt @@ -15,3 +15,4 @@ H9JCNNNBK3MLYR-N6E K3LKLKL0EM-MGCN K3LKBKB0BM-MGCP H9JCNNNCP3MLYR-N6E +H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h b/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/crota/include/variant/ec.h b/src/mainboard/google/brya/variants/crota/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/crota/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/crota/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index a7994127c14..af949596644 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -237,6 +237,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref i2c0 on chip drivers/i2c/cs42l42 diff --git a/src/mainboard/google/brya/variants/dirks/data.vbt b/src/mainboard/google/brya/variants/dirks/data.vbt new file mode 100644 index 00000000000..8151c565437 Binary files /dev/null and b/src/mainboard/google/brya/variants/dirks/data.vbt differ diff --git a/src/mainboard/google/brya/variants/dirks/ramstage.c b/src/mainboard/google/brya/variants/dirks/ramstage.c index 04f9c6df83f..e42eef5fcf8 100644 --- a/src/mainboard/google/brya/variants/dirks/ramstage.c +++ b/src/mainboard/google/brya/variants/dirks/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/dirkson/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/Makefile.mk new file mode 100644 index 00000000000..64d3d152f0e --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += memory.c +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/dirkson/gpio.c b/src/mainboard/google/brya/variants/dirkson/gpio.c new file mode 100644 index 00000000000..ec6d2c5b262 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/gpio.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage for dirkson */ +static const struct pad_config override_gpio_table[] = { + /* A11 : EN_SPK_PA ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A14 : USB_OC1# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A3_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : NC ==> HDMI1_HPD_SUB_ODL*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B4 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* B16 : I2C5_SDA ==> NC */ + PAD_NC(GPP_B16, NONE), + /* B17 : I2C5_SCL ==> NC */ + PAD_NC(GPP_B17, NONE), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + + /* E5 : [] ==> USB_A4_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E9 : USB_OC0# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F13 : GSXSLOAD ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, DEEP, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + + /* H6 : I2C1_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C1_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R4 : DMIC_CLK_A_0A ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : DMIC_DATA_0A ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : DMIC_DATA_1A ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : I2S1_TXD ==> NC */ + PAD_NC(GPP_S2, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + /* GPP_B4 : [] ==> LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config early_graphics_gpio_table[] = { + /* A18 : NC ==> HDMI2_HPD*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* E14 : DDSP_HPDA ==> HDMI1_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_graphics_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_graphics_gpio_table); + return early_graphics_gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h new file mode 100644 index 00000000000..469e75c8340 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h new file mode 100644 index 00000000000..c4fe342621e --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/dirkson/memory.c b/src/mainboard/google/brya/variants/dirkson/memory.c new file mode 100644 index 00000000000..8693a719f98 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory" + "channels except first two on each memory controller.\n"); + return (BIT(2) | BIT(3)); + } + + return 0; +} diff --git a/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk new file mode 100644 index 00000000000..7991e5f735c --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = H58G56BK8BX068, H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 6(0b0110) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 7(0b0111) Parts = H58G66BK8BX067 diff --git a/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt new file mode 100644 index 00000000000..2a8769551c4 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKLKL0EM-MGCN 2 (0010) +K3LKBKB0BM-MGCP 3 (0011) +H9JCNNNCP3MLYR-N6E 0 (0000) +K3KL8L80CM-MGCT 4 (0100) +H58G56BK8BX068 5 (0101) +K3KL9L90CM-MGCT 6 (0110) +H58G66BK8BX067 7 (0111) +H58G56CK8BX146 5 (0101) diff --git a/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt new file mode 100644 index 00000000000..f2459f39faf --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt @@ -0,0 +1,22 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3LKLKL0EM-MGCN +K3LKBKB0BM-MGCP +H9JCNNNCP3MLYR-N6E +K3KL8L80CM-MGCT +H58G56BK8BX068 +K3KL9L90CM-MGCT +H58G66BK8BX067 +H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/dirkson/overridetree.cb b/src/mainboard/google/brya/variants/dirkson/overridetree.cb new file mode 100644 index 00000000000..6a5d444f127 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/overridetree.cb @@ -0,0 +1,406 @@ +fw_config + field WIFI_SAR_ID 0 0 + option ID_0 0 + option ID_1 1 + end + field WIFI_TYPE 1 2 + option WIFI_ALL 0 + option WIFI_CNVI 1 + option WIFI_PCIE 2 + end +end + +chip soc/intel/alderlake + + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x1" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + # This port is repurposed from Type-C to type-A port. + # Still declare it as Type-C port in order to set PortResetMessageEnable UPD. + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_A0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A4 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Disable eDP on DDI portA + register "ddi_portA_config" = "0" + + # Enable HPD and DDC for DDI port A + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 5500, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref hda on + chip drivers/sof + register "jack_tplg" = "rt5682" + device generic 0 on end + end + end + device ref pcie_rp7 on + # Enable PCIE 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW2_14" # GPP_F14 + register "device_index" = "0" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device ref pcie_rp11 on + # Enable wlan PCIe 11 using clk 2 + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + use usb2_port8 as bluetooth_companion + device pci 00.0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + end + device ref emmc on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + chip drivers/usb/acpi + register "desc" = ""CNVI Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A4"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/dirkson/ramstage.c b/src/mainboard/google/brya/variants/dirkson/ramstage.c new file mode 100644 index 00000000000..2f1599e8b15 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/ramstage.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /*Enable Type C port1 convert to Type A*/ + params->EnableTcssCovTypeA[1] = 1; + /* PCH xchi port number for Type C port1 port mapping */ + params->MappingPchXhciUsbA[1] = 2; + +} + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 63 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 63 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 63 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in dirkson, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x PR222/(PR222 + R3193) + * PR222/(PR222 + R3193) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); +} diff --git a/src/mainboard/google/brya/variants/dochi/data.vbt b/src/mainboard/google/brya/variants/dochi/data.vbt new file mode 100644 index 00000000000..c687957df97 Binary files /dev/null and b/src/mainboard/google/brya/variants/dochi/data.vbt differ diff --git a/src/mainboard/google/brya/variants/dochi/include/variant/ec.h b/src/mainboard/google/brya/variants/dochi/include/variant/ec.h index 6f104d5da4e..74b96179aa5 100644 --- a/src/mainboard/google/brya/variants/dochi/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/dochi/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index 8a10a7e88d4..6a6c67996d3 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -216,6 +216,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_UNKNOWN probe STORAGE STORAGE_NVME end diff --git a/src/mainboard/google/brya/variants/domika/data.vbt b/src/mainboard/google/brya/variants/domika/data.vbt new file mode 100644 index 00000000000..c85d06dc807 Binary files /dev/null and b/src/mainboard/google/brya/variants/domika/data.vbt differ diff --git a/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/gimble/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/gimble/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/gimble/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/glassway/Makefile.mk b/src/mainboard/google/brya/variants/glassway/Makefile.mk index b4698058ab6..49ba2429513 100644 --- a/src/mainboard/google/brya/variants/glassway/Makefile.mk +++ b/src/mainboard/google/brya/variants/glassway/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c index c2b8f70e700..b69e791e633 100644 --- a/src/mainboard/google/brya/variants/glassway/gpio.c +++ b/src/mainboard/google/brya/variants/glassway/gpio.c @@ -24,6 +24,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E5 : SDD_STRAP2 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), /* F12 : WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H19 : SOC_I2C_SUB_INT_ODL */ @@ -70,6 +72,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D6, 1, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ diff --git a/src/mainboard/google/brya/variants/glassway/memory.c b/src/mainboard/google/brya/variants/glassway/memory.c new file mode 100644 index 00000000000..51a7ff504cb --- /dev/null +++ b/src/mainboard/google/brya/variants/glassway/memory.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + return (BIT(2) | BIT(3)); + } + + return 0; +} diff --git a/src/mainboard/google/brya/variants/gothrax/data.vbt b/src/mainboard/google/brya/variants/gothrax/data.vbt new file mode 100644 index 00000000000..09cdf4a8657 Binary files /dev/null and b/src/mainboard/google/brya/variants/gothrax/data.vbt differ diff --git a/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk index 44065b51d07..8d7708ad74d 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk @@ -8,5 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M3 SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9JCNNNCP3MLYR-N6E -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = RS1G32LO5D2FDB-23BT diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt index 9848a35a359..e50328aefb5 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt @@ -11,3 +11,4 @@ H9JCNNNBK3MLYR-N6E 0 (0000) H9JCNNNCP3MLYR-N6E 3 (0011) K3KL8L80CM-MGCT 4 (0100) RS1G32LO5D2FDB-23BT 5 (0101) +MT62F1G32D2DS-026 WT:B 4 (0100) diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt index baf0ab19af4..1e2d37e9d1c 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt @@ -17,3 +17,4 @@ H9JCNNNBK3MLYR-N6E, H9JCNNNCP3MLYR-N6E, K3KL8L80CM-MGCT, RS1G32LO5D2FDB-23BT, +MT62F1G32D2DS-026 WT:B, diff --git a/src/mainboard/google/brya/variants/joxer/include/variant/ec.h b/src/mainboard/google/brya/variants/joxer/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/joxer/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/joxer/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h index 6f104d5da4e..74b96179aa5 100644 --- a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk index 39725c41d27..5a6304a9582 100644 --- a/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3 SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 2(0b0010) Parts = K3KL8L80CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 3(0b0011) Parts = H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt index 3a81c28ba4c..fb609275bce 100644 --- a/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt @@ -8,3 +8,4 @@ H9JCNNNBK3MLYR-N6E 0 (0000) K3KL6L60GM-MGCT 1 (0001) K3KL8L80CM-MGCT 2 (0010) H58G56CK8BX146 3 (0011) +MT62F1G32D2DS-031RF WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt index 0cefe2ecafc..c3ca0b8ea25 100644 --- a/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt @@ -13,3 +13,4 @@ H9JCNNNBK3MLYR-N6E K3KL6L60GM-MGCT K3KL8L80CM-MGCT H58G56CK8BX146 +MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb index 226b4f41bc5..9c191dba937 100644 --- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb +++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb @@ -166,7 +166,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "0" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/kano/include/variant/ec.h b/src/mainboard/google/brya/variants/kano/include/variant/ec.h index 6f104d5da4e..74b96179aa5 100644 --- a/src/mainboard/google/brya/variants/kano/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/kano/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 89cb3317997..4375c7d72d0 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -246,6 +246,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 5b708f08f7c..279d1a9a176 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -285,12 +285,19 @@ chip soc/intel/alderlake device ref pcie_rp9 off end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 0 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref cnvi_wifi on diff --git a/src/mainboard/google/brya/variants/kinox/ramstage.c b/src/mainboard/google/brya/variants/kinox/ramstage.c index c343c0424ea..14b8f55c313 100644 --- a/src/mainboard/google/brya/variants/kinox/ramstage.c +++ b/src/mainboard/google/brya/variants/kinox/ramstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 19a20a14ecc..9733305b691 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -148,6 +148,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tbt_pcie_rp0 on probe MB_USBC TC_USB4 diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c index 2062383e32e..2c359433d3a 100644 --- a/src/mainboard/google/brya/variants/kuldax/ramstage.c +++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/kulnex/ramstage.c b/src/mainboard/google/brya/variants/kulnex/ramstage.c index a3cd9f3fc61..f82c7e62d3a 100644 --- a/src/mainboard/google/brya/variants/kulnex/ramstage.c +++ b/src/mainboard/google/brya/variants/kulnex/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 741d54d7488..57b0791f60e 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -124,6 +124,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME probe STORAGE STORAGE_UNKNOWN end # SSD diff --git a/src/mainboard/google/brya/variants/moxie/ramstage.c b/src/mainboard/google/brya/variants/moxie/ramstage.c index f4f80bebe00..01063ad9d39 100644 --- a/src/mainboard/google/brya/variants/moxie/ramstage.c +++ b/src/mainboard/google/brya/variants/moxie/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/moxoe/ramstage.c b/src/mainboard/google/brya/variants/moxoe/ramstage.c index de5254337a7..ce29207f8dc 100644 --- a/src/mainboard/google/brya/variants/moxoe/ramstage.c +++ b/src/mainboard/google/brya/variants/moxoe/ramstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index eb5515d7399..2a48a016bbd 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -95,7 +95,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "0" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 5a87ecc70bc..c3b0d847ce5 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -204,6 +204,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref cnvi_wifi on chip drivers/wifi/generic diff --git a/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index 469a880cd6f..122b0a5c5a0 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -70,7 +70,7 @@ chip soc/intel/alderlake # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/pujjocento/ramstage.c b/src/mainboard/google/brya/variants/pujjocento/ramstage.c index 49441a20d88..7fe3d7af519 100644 --- a/src/mainboard/google/brya/variants/pujjocento/ramstage.c +++ b/src/mainboard/google/brya/variants/pujjocento/ramstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/pujjolo/fw_config.c b/src/mainboard/google/brya/variants/pujjolo/fw_config.c index 02e159d14d1..3c69a76c623 100644 --- a/src/mainboard/google/brya/variants/pujjolo/fw_config.c +++ b/src/mainboard/google/brya/variants/pujjolo/fw_config.c @@ -16,6 +16,27 @@ static const struct pad_config ish_disable_pads[] = { PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), }; +static const struct pad_config wwan_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* B8 : WWAN_SAR_DETECT_2_ODL */ + PAD_NC(GPP_B8, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* E16 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_E16, NONE), + /* E17 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (fw_config_probe(FW_CONFIG(TABLET_MODE, TABLET_MODE_DISABLE))) { @@ -23,4 +44,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) gpio_padbased_override(padbased_table, ish_disable_pads, ARRAY_SIZE(ish_disable_pads)); } + + if (fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT))) { + printk(BIOS_INFO, "Disable WWAN-related GPIO pins.\n"); + gpio_padbased_override(padbased_table, wwan_disable_pads, + ARRAY_SIZE(wwan_disable_pads)); + } } diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb index 57fbfaf7f9b..e205a9b8313 100644 --- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb @@ -85,7 +85,7 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/pujjoniru/data.vbt b/src/mainboard/google/brya/variants/pujjoniru/data.vbt new file mode 100644 index 00000000000..aa0ccac1131 Binary files /dev/null and b/src/mainboard/google/brya/variants/pujjoniru/data.vbt differ diff --git a/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk index 1cc183961b0..f2ee3892991 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146 SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt index 160fd2dd47b..b28f9c9f08d 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ H9JCNNNBK3MLYR-N6E 1 (0001) H58G56CK8BX146 2 (0010) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) +MT62F1G32D2DS-031RF WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt index 21e9cecfbc4..028cb888066 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt @@ -14,3 +14,4 @@ H9JCNNNBK3MLYR-N6E H58G56CK8BX146 MT62F1G32D2DS-026 WT:B K3KL8L80CM-MGCT +MT62F1G32D2DS-031RF WT:C diff --git a/src/mainboard/google/brya/variants/quandiso/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/Makefile.mk index 86ba20d3c31..4578e25f248 100644 --- a/src/mainboard/google/brya/variants/quandiso/Makefile.mk +++ b/src/mainboard/google/brya/variants/quandiso/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/quandiso/gpio.c b/src/mainboard/google/brya/variants/quandiso/gpio.c index 55b2905e319..c576475c290 100644 --- a/src/mainboard/google/brya/variants/quandiso/gpio.c +++ b/src/mainboard/google/brya/variants/quandiso/gpio.c @@ -30,6 +30,9 @@ static const struct pad_config override_gpio_table[] = { /* D17 : NC ==> SD_WAKE_N */ PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F12 : WWAN_RST_ODL */ @@ -61,6 +64,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ diff --git a/src/mainboard/google/brya/variants/quandiso/memory.c b/src/mainboard/google/brya/variants/quandiso/memory.c new file mode 100644 index 00000000000..10bc9a95b93 --- /dev/null +++ b/src/mainboard/google/brya/variants/quandiso/memory.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + printk(BIOS_INFO, "Disable all other memory channels" + "except first two on each memory controller.\n"); + return (BIT(2) | BIT(3)); + } + + return 0; +} diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk index 6c970ad89ee..084dea1af0d 100644 --- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk @@ -7,7 +7,7 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, BWMYAX32P8A-32G +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, BWMYAX32P8A-32G, SL5D32G32C2A-HC0 SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070 SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 6(0b0110) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt index 275125f0d28..25bb8227e80 100644 --- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt @@ -22,3 +22,4 @@ H58G56CK8BX146 7 (0111) K3KL8L80EM-MGCU 7 (0111) MT62F512M32D1DS-023 WT:E 7 (0111) BWMYAX32P8A-32G 3 (0011) +SL5D32G32C2A-HC0 3 (0011) diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt index 1570fe89627..5cdb4a05fa2 100644 --- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt @@ -27,3 +27,4 @@ H58G56CK8BX146 K3KL8L80EM-MGCU MT62F512M32D1DS-023 WT:E BWMYAX32P8A-32G +SL5D32G32C2A-HC0 diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h index ea8fb54830b..18716e4f50b 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h @@ -23,4 +23,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/redrix4es/data.vbt b/src/mainboard/google/brya/variants/redrix4es/data.vbt new file mode 100644 index 00000000000..716d09f557d Binary files /dev/null and b/src/mainboard/google/brya/variants/redrix4es/data.vbt differ diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h index d3907460366..3034eef15ae 100644 --- a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h @@ -44,4 +44,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/riven/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/rull/data.vbt b/src/mainboard/google/brya/variants/rull/data.vbt new file mode 100644 index 00000000000..46728a52c84 Binary files /dev/null and b/src/mainboard/google/brya/variants/rull/data.vbt differ diff --git a/src/mainboard/google/brya/variants/sundance/data.vbt b/src/mainboard/google/brya/variants/sundance/data.vbt new file mode 100644 index 00000000000..fa24155cb60 Binary files /dev/null and b/src/mainboard/google/brya/variants/sundance/data.vbt differ diff --git a/src/mainboard/google/brya/variants/taeko/fw_config.c b/src/mainboard/google/brya/variants/taeko/fw_config.c index fbf214db54a..1f8005cccd9 100644 --- a/src/mainboard/google/brya/variants/taeko/fw_config.c +++ b/src/mainboard/google/brya/variants/taeko/fw_config.c @@ -13,13 +13,20 @@ enum storage_device { STORAGE_EMMC = 1, }; +static enum storage_device storage_default_from_fw_config(void) +{ + return (fw_config_get() & FW_CONFIG_FIELD_BOOT_EMMC_MASK_MASK) ? + STORAGE_EMMC : STORAGE_NVME; +} + /* Override fw_config_probe_mainboard_override to check CFR for storage selection */ bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result) { /* Check if this is a storage-related probe */ if (match->field_name) { - /* Read CFR option directly - default to NVMe if not available */ - uint8_t storage_selection = get_uint_option("storage_device", STORAGE_NVME); + /* Read CFR option; if unset, use fw_config setting */ + uint8_t storage_selection = + get_uint_option("storage_device", storage_default_from_fw_config()); if (strcmp(match->field_name, "BOOT_NVME_MASK") == 0) { /* NVMe is enabled if storage selection is NVMe */ *result = (storage_selection == STORAGE_NVME); diff --git a/src/mainboard/google/brya/variants/taeko/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/taeko/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/taeko/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index dfd88a6c16b..8bb7c9ad553 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -400,6 +400,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref tbt_pcie_rp0 off end diff --git a/src/mainboard/google/brya/variants/taeko4es/fw_config.c b/src/mainboard/google/brya/variants/taeko4es/fw_config.c index 5068f84581f..0b1f2d8f3f1 100644 --- a/src/mainboard/google/brya/variants/taeko4es/fw_config.c +++ b/src/mainboard/google/brya/variants/taeko4es/fw_config.c @@ -4,6 +4,50 @@ #include #include #include +#include +#include +#include + +enum storage_device { + STORAGE_NVME = 0, + STORAGE_EMMC = 1, +}; + +static enum storage_device storage_default_from_fw_config(void) +{ + return (fw_config_get() & FW_CONFIG_FIELD_BOOT_EMMC_MASK_MASK) ? + STORAGE_EMMC : STORAGE_NVME; +} + +/* Override fw_config_probe_mainboard_override to check CFR for storage selection */ +bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result) +{ + /* Check if this is a storage-related probe */ + if (match->field_name) { + /* Read CFR option; if unset, use fw_config setting */ + uint8_t storage_selection = + get_uint_option("storage_device", storage_default_from_fw_config()); + if (strcmp(match->field_name, "BOOT_NVME_MASK") == 0) { + /* NVMe is enabled if storage selection is NVMe */ + *result = (storage_selection == STORAGE_NVME); + if (*result) { + printk(BIOS_INFO, "fw_config: NVMe enabled by CFR\n"); + } + return true; + } + if (strcmp(match->field_name, "BOOT_EMMC_MASK") == 0) { + /* eMMC is enabled if storage selection is eMMC */ + *result = (storage_selection == STORAGE_EMMC); + if (*result) { + printk(BIOS_INFO, "fw_config: eMMC enabled by CFR\n"); + } + return true; + } + } + + /* Not handled - use standard fw_config logic */ + return false; +} static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 3e978f1e00e..e0d180d1b80 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -263,6 +263,14 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end + probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end diff --git a/src/mainboard/google/brya/variants/taniks/fw_config.c b/src/mainboard/google/brya/variants/taniks/fw_config.c index b29ea56d98f..00f3a45a9b8 100644 --- a/src/mainboard/google/brya/variants/taniks/fw_config.c +++ b/src/mainboard/google/brya/variants/taniks/fw_config.c @@ -13,13 +13,20 @@ enum storage_device { STORAGE_EMMC = 1, }; +static enum storage_device storage_default_from_fw_config(void) +{ + return (fw_config_get() & FW_CONFIG_FIELD_BOOT_EMMC_MASK_MASK) ? + STORAGE_EMMC : STORAGE_NVME; +} + /* Override fw_config_probe_mainboard_override to check CFR for storage selection */ bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result) { /* Check if this is a storage-related probe */ if (match->field_name) { - /* Read CFR option directly - default to NVMe if not available */ - uint8_t storage_selection = get_uint_option("storage_device", STORAGE_NVME); + /* Read CFR option; if unset, use fw_config setting */ + uint8_t storage_selection = + get_uint_option("storage_device", storage_default_from_fw_config()); if (strcmp(match->field_name, "BOOT_NVME_MASK") == 0) { /* NVMe is enabled if storage selection is NVMe */ *result = (storage_selection == STORAGE_NVME); diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 09654293dcf..c2e6af08bd4 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -246,6 +246,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref tbt_pcie_rp0 off end diff --git a/src/mainboard/google/brya/variants/teliks/data.vbt b/src/mainboard/google/brya/variants/teliks/data.vbt new file mode 100644 index 00000000000..aa0ccac1131 Binary files /dev/null and b/src/mainboard/google/brya/variants/teliks/data.vbt differ diff --git a/src/mainboard/google/brya/variants/teliks/include/variant/ec.h b/src/mainboard/google/brya/variants/teliks/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/teliks/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/teliks/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/telith/data.vbt b/src/mainboard/google/brya/variants/telith/data.vbt new file mode 100644 index 00000000000..0cbbe26cf79 Binary files /dev/null and b/src/mainboard/google/brya/variants/telith/data.vbt differ diff --git a/src/mainboard/google/brya/variants/telith/ramstage.c b/src/mainboard/google/brya/variants/telith/ramstage.c index 9156385ed88..65f1cc28fd5 100644 --- a/src/mainboard/google/brya/variants/telith/ramstage.c +++ b/src/mainboard/google/brya/variants/telith/ramstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 3f0801e8bbc..09fbe321570 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -95,7 +95,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "0" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 157e0fcc298..dca4258d14d 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -112,7 +112,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "0" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index 2145204245c..042446c6ff1 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -217,6 +217,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref cnvi_wifi on diff --git a/src/mainboard/google/brya/variants/xivu/include/variant/ec.h b/src/mainboard/google/brya/variants/xivu/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/brya/variants/xivu/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/xivu/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/brya/variants/xol/data.vbt b/src/mainboard/google/brya/variants/xol/data.vbt new file mode 100644 index 00000000000..9a7897482d9 Binary files /dev/null and b/src/mainboard/google/brya/variants/xol/data.vbt differ diff --git a/src/mainboard/google/brya/variants/xol/ramstage.c b/src/mainboard/google/brya/variants/xol/ramstage.c index 02829ccc71d..d3c29acb04b 100644 --- a/src/mainboard/google/brya/variants/xol/ramstage.c +++ b/src/mainboard/google/brya/variants/xol/ramstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/brya/variants/yavilla/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/Makefile.mk index 86ba20d3c31..4578e25f248 100644 --- a/src/mainboard/google/brya/variants/yavilla/Makefile.mk +++ b/src/mainboard/google/brya/variants/yavilla/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/yavilla/gpio.c b/src/mainboard/google/brya/variants/yavilla/gpio.c index fb7577f06cc..f5f450f13c3 100644 --- a/src/mainboard/google/brya/variants/yavilla/gpio.c +++ b/src/mainboard/google/brya/variants/yavilla/gpio.c @@ -21,6 +21,9 @@ static const struct pad_config override_gpio_table[] = { /* D8 : SD_CLKREQ_ODL ==> NC */ PAD_NC(GPP_D8, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F12 : WWAN_RST_ODL */ @@ -57,6 +60,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ diff --git a/src/mainboard/google/brya/variants/yavilla/memory.c b/src/mainboard/google/brya/variants/yavilla/memory.c new file mode 100644 index 00000000000..10bc9a95b93 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavilla/memory.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + printk(BIOS_INFO, "Disable all other memory channels" + "except first two on each memory controller.\n"); + return (BIT(2) | BIT(3)); + } + + return 0; +} diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk index 99061e1d121..41dce82b342 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk @@ -11,4 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7B SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070, MT62F2G32D4DS-031RF WT:C SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 6(0b0110) Parts = K3KL6L60GM-MGCT -SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 7(0b0111) Parts = H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 7(0b0111) Parts = H58G56CK8BX146, H58G56BK8BX068 diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt index 6b938ba8dd9..407538532ac 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt @@ -20,3 +20,4 @@ K3KL6L60GM-MGCT 6 (0110) H58G56CK8BX146 7 (0111) MT62F1G32D2DS-031RF WT:C 2 (0010) MT62F2G32D4DS-031RF WT:C 5 (0101) +H58G56BK8BX068 7 (0111) diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt index d0add1f65a9..4fe824fdd88 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt @@ -25,3 +25,4 @@ K3KL6L60GM-MGCT H58G56CK8BX146 MT62F1G32D2DS-031RF WT:C MT62F2G32D4DS-031RF WT:C +H58G56BK8BX068 diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb index f87f9f3f16e..dcedfdb6e6e 100644 --- a/src/mainboard/google/brya/variants/zydron/overridetree.cb +++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb @@ -218,6 +218,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/calypso/Kconfig b/src/mainboard/google/calypso/Kconfig new file mode 100644 index 00000000000..7183f5051d0 --- /dev/null +++ b/src/mainboard/google/calypso/Kconfig @@ -0,0 +1,176 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GOOGLE_CALYPSO_COMMON + def_bool n + select COMMON_CBFS_SPI_WRAPPER + # FIXME: keep ADB for development phase + select GBB_FLAG_ENABLE_ADB if VBOOT + select MAINBOARD_HAS_CHROMEOS + select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT + select SPI_FLASH + select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE + select SPI_FLASH_INCLUDE_ALL_DRIVERS + +config BOARD_GOOGLE_BASEBOARD_CALYPSO + def_bool n + select BOARD_GOOGLE_CALYPSO_COMMON + +config BOARD_GOOGLE_MODEL_MENSA + def_bool n + select BOARD_GOOGLE_BASEBOARD_CALYPSO + select BOARD_ROMSIZE_KB_32768 + select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC + select EC_GOOGLE_CHROMEEC_LED_CONTROL + select MAINBOARD_HAS_CHROME_EC + select MAINBOARD_HAS_GOOGLE_TPM + +config BOARD_GOOGLE_MENSA + select BOARD_GOOGLE_MODEL_MENSA + select DAP_USE_SMB1 + select HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + select MAINBOARD_HAS_FINGERPRINT_VIA_USB + select SOC_QUALCOMM_CALYPSO + +config BOARD_GOOGLE_C1NV + select BOARD_GOOGLE_MODEL_MENSA + select MAINBOARD_HAS_FINGERPRINT_VIA_USB + select SOC_QUALCOMM_CALYPSO + +config BOARD_GOOGLE_MODEL_CALYPSO + def_bool n + select BOARD_GOOGLE_BASEBOARD_CALYPSO + select BOARD_ROMSIZE_KB_65536 + select MISSING_BOARD_RESET + select SOC_QUALCOMM_CDT + +config BOARD_GOOGLE_CALYPSO + select BOARD_GOOGLE_MODEL_CALYPSO + select MAINBOARD_HAS_FINGERPRINT_VIA_USB + select SOC_QUALCOMM_CALYPSO + +if BOARD_GOOGLE_CALYPSO_COMMON + +config MAINBOARD_DIR + default "google/calypso" + +config MAINBOARD_HAS_FINGERPRINT_VIA_SPI + bool + default n + help + Enable this option if your mainboard's fingerprint reader + is connected via the SPI interface. + +config MAINBOARD_HAS_FINGERPRINT_VIA_USB + bool + default n + help + Enable this option if your mainboard's fingerprint reader + is connected via the USB interface. + +config MAINBOARD_HAS_FINGERPRINT + bool + default y if MAINBOARD_HAS_FINGERPRINT_VIA_SPI || MAINBOARD_HAS_FINGERPRINT_VIA_USB + help + Enable this option if your mainboard is equipped with an onboard + fingerprint reader. This could be connected via SPI or USB. + +config HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + default n + help + Enable this option to allow source and sink modes on the debug access port. + +config DAP_SMB_SLAVE_ID + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + hex + default 0x09 if DAP_USE_SMB1 + default 0x0a if DAP_USE_SMB2 + default 0x0b if DAP_USE_SMB3 + help + The Slave ID for the Debug Access Port communication. + +config DAP_USE_SMB1 + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + help + Select this to use SMB1 for DAP. + +config DAP_USE_SMB2 + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + help + Select this to use SMB2 for DAP. + +config DAP_USE_SMB3 + depends on HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK + bool + help + Select this to use SMB3 for DAP. + +config MAINBOARD_HAS_GOOGLE_TPM + bool + default n + select I2C_TPM + select MAINBOARD_HAS_TPM2 + select TPM_GOOGLE_TI50 + help + Enable this option if your mainboard is equipped with Google TPM aka GSC. + +config MAINBOARD_HAS_CHROME_EC + bool + default n + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT + select RTC + help + Enable this option if your mainboard is equipped with Chrome EC. + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_LID_SWITCH if MAINBOARD_HAS_CHROME_EC + select VBOOT_NO_BOARD_SUPPORT if !MAINBOARD_HAS_CHROME_EC + select VBOOT_VBNV_FLASH + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + default "Calypso" if BOARD_GOOGLE_CALYPSO + default "Mensa" if BOARD_GOOGLE_MENSA + default "C1nv" if BOARD_GOOGLE_C1NV + +config DRIVER_TPM_I2C_BUS + depends on I2C_TPM + hex + default 0x01 # QUP0_SE1 + +config DRIVER_TPM_I2C_ADDR + depends on I2C_TPM + default 0x50 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + depends on EC_GOOGLE_CHROMEEC + hex + default 0x16 # QUP2_SE6 + +config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT + depends on TPM_GOOGLE_TI50 + int + default 23 + help + This option specifies the GPIO pin number on the mainboard that is + used for the interrupt line from the Google Security Chip (GSC) to the + Application Processor (AP). + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if MAINBOARD_HAS_GOOGLE_TPM + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nogsc.fmd" + +endif # BOARD_GOOGLE_CALYPSO_COMMON diff --git a/src/mainboard/google/calypso/Kconfig.name b/src/mainboard/google/calypso/Kconfig.name new file mode 100644 index 00000000000..50976e83f98 --- /dev/null +++ b/src/mainboard/google/calypso/Kconfig.name @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "Calypso (Qualcomm Calypso)" + +config BOARD_GOOGLE_CALYPSO + bool "-> Calypso" + +config BOARD_GOOGLE_MENSA + bool "-> Mensa" + +config BOARD_GOOGLE_C1NV + bool "-> C1nv" diff --git a/src/mainboard/google/calypso/Makefile.mk b/src/mainboard/google/calypso/Makefile.mk new file mode 100644 index 00000000000..87d58149afc --- /dev/null +++ b/src/mainboard/google/calypso/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += boardid.c +all-y += chromeos.c +ifneq ($(CONFIG_MISSING_BOARD_RESET),y) +all-y += reset.c +endif + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +romstage-y += charging.c + +ramstage-y += charging.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/calypso/board.h b/src/mainboard/google/calypso/board.h new file mode 100644 index 00000000000..4e8af3f9070 --- /dev/null +++ b/src/mainboard/google/calypso/board.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GOOGLE_MENSA_BOARD_H +#define MAINBOARD_GOOGLE_MENSA_BOARD_H + +#include +#include + +/* TODO: update as per datasheet */ +#define GPIO_AP_EC_INT GPIO(67) +#define GSC_AP_INT(x) GPIO(x) +#define GPIO_GSC_AP_INT GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT) + +/* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */ +#if CONFIG(MAINBOARD_HAS_FINGERPRINT) +#define GPIO_FP_RST_L GPIO(25) +#define GPIO_EN_FP_RAILS GPIO(22) +#if CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI) +#define GPIO_FPMCU_BOOT0 GPIO(24) +#define GPIO_FPMCU_INT GPIO(23) +#else +#define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t) +#define GPIO_FPMCU_INT dead_code_t(gpio_t) +#endif +#endif + +#define DEAD_BATT_CHG_THRESHOLD_MAH 100 + +void setup_chromeos_gpios(void); +void configure_debug_access_port(void); +void enable_slow_battery_charging(void); +void disable_slow_battery_charging(void); +void launch_charger_applet(void); +bool platform_get_battery_soc_information(uint32_t *batt_pct); +void enable_fast_battery_charging(void); +void configure_dead_battery_boot(void); + +#endif /* MAINBOARD_GOOGLE_MENSA_BOARD_H */ diff --git a/src/mainboard/google/calypso/board_info.txt b/src/mainboard/google/calypso/board_info.txt new file mode 100644 index 00000000000..3ad18f128ef --- /dev/null +++ b/src/mainboard/google/calypso/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Calypso reference board with Qualcomm Calypso SoC +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/calypso/boardid.c b/src/mainboard/google/calypso/boardid.c new file mode 100644 index 00000000000..c7eaf9cf41d --- /dev/null +++ b/src/mainboard/google/calypso/boardid.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + /* Placeholder */ + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + if (id != UNDEFINED_STRAPPING_ID) + return id; + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = google_chromeec_get_board_sku(); + + return id; +} diff --git a/src/mainboard/google/calypso/bootblock.c b/src/mainboard/google/calypso/bootblock.c new file mode 100644 index 00000000000..cb641d85109 --- /dev/null +++ b/src/mainboard/google/calypso/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); + + if (CONFIG(I2C_TPM)) + i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ +} diff --git a/src/mainboard/google/calypso/charging.c b/src/mainboard/google/calypso/charging.c new file mode 100644 index 00000000000..517a33c0972 --- /dev/null +++ b/src/mainboard/google/calypso/charging.c @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "board.h" + +#include +#include +#include +#include +#include +#include +#include + +#define SMB1_SLAVE_ID 0x09 +#define SMB2_SLAVE_ID 0x0A +#define SMB3_SLAVE_ID 0x0B + +#define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666 +#define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG) +#define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG) +#define SMB3_CHGR_MAX_FCC_CFG ((SMB3_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG) + +#define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642 +#define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD) +#define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD) +#define SMB3_CHGR_CHRG_EN_CMD ((SMB3_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD) + +#define SCHG_CHGR_CHARGING_FCC 0x260A +#define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC) +#define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC) +#define SMB3_CHGR_CHARGING_FCC ((SMB3_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC) + +#define FCC_3A_STEP_50MA 0x3C +#define FCC_DISABLE 0x8c + +/* + * SDAM15_MEM_061 (SPMI address 0x7E7D) - SetMaxPwrReq_BattSts register + * Bit 6 - DEAD_BATT_STS + */ +#define SDAM15_MEM_061_ADDR 0x7E7D +#define DEAD_BATT_STS BIT(6) + +#define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */ +#define CHARGING_RAIL_STABILIZATION_DELAY_MS 5000 /* 5sec */ +#define DEAD_BATTERY_CHARGING_LOOP_EXIT_MS (10 * 60 * 1000) /* 10min */ +#define DELAY_CHARGING_ACTIVE_LB_MS 4000 /* 4sec */ +#define SMB_FCC_MULTIPLIER_MA 50 +#define SMB_READ_DELAY_MS 5 + +enum charging_status { + CHRG_DISABLE, + CHRG_ENABLE, +}; + +static int get_battery_icurr_ma(void) +{ + const uint32_t smb_regs[] = { + SMB1_CHGR_CHARGING_FCC, + SMB2_CHGR_CHARGING_FCC, + SMB3_CHGR_CHARGING_FCC, + }; + + int icurr = 0; + for (size_t i = 0; i < ARRAY_SIZE(smb_regs); i++) { + mdelay(SMB_READ_DELAY_MS); + icurr = spmi_read8_safe(smb_regs[i]); + + if (icurr > 0) + return icurr * SMB_FCC_MULTIPLIER_MA; + } + + printk(BIOS_ERR, "Critical: All SMB registers failed to read.\n"); + return 0; +} + +static void clear_ec_manual_poweron_event(void) +{ + const uint64_t manual_pwron_event_mask = + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)); + google_chromeec_clear_events_b(manual_pwron_event_mask); +} + +static int detect_ec_manual_poweron_event(void) +{ + const uint64_t manual_pwron_event_mask = + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)); + uint64_t events = google_chromeec_get_events_b(); + + if (!!(events & manual_pwron_event_mask)) + return 1; + + return 0; +} + +static void clear_ac_unplug_event(void) +{ + const uint64_t ac_unplug_event = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED); + google_chromeec_clear_events_b(ac_unplug_event); +} + +static int detect_ac_unplug_event(void) +{ + const uint64_t ac_unplug_event_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED); + uint64_t events = google_chromeec_get_events_b(); + + if (!!(events & ac_unplug_event_mask)) + return 1; + + return 0; +} + +/* + * Provides visual feedback via the LEDs and clears the AC unplug + * event to acknowledge the transition into a charging state. + */ +static void indicate_charging_status(void) +{ + /* Turn on LEDs to alert user of power state change */ + if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) { + google_chromeec_lightbar_on(); + mdelay(DELAY_CHARGING_ACTIVE_LB_MS); + } + + /* Clear the event to prevent re-triggering in the next iteration */ + clear_ac_unplug_event(); +} + +void launch_charger_applet(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + static const long charging_enable_timeout_ms = CHARGING_RAIL_STABILIZATION_DELAY_MS; + struct stopwatch sw; + bool has_entered_dead_battery_mode = false; + + printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__); + + /* Reset AC-unplug detection state and lightbar status before entering loop */ + clear_ac_unplug_event(); + /* clear any pending power button press and lid open event */ + clear_ec_manual_poweron_event(); + + stopwatch_init_msecs_expire(&sw, charging_enable_timeout_ms); + while (!get_battery_icurr_ma()) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "Charging not enabled %ld ms. Abort.\n", + charging_enable_timeout_ms); + /* + * If firmware-based charging fails to enable within the timeout, + * do not simply return, as this leaves IPs uninitialized and + * causes a boot hang. Instead, issue a shutdown if not charging. + */ + printk(BIOS_INFO, "Issuing power-off.\n"); + if (detect_ac_unplug_event()) + indicate_charging_status(); + google_chromeec_offmode_heartbeat(); + google_chromeec_ap_poweroff(); + } + mdelay(200); + } + printk(BIOS_INFO, "Charging ready after %lld ms\n", stopwatch_duration_msecs(&sw)); + + static const long dead_battery_charging_timeout_ms = DEAD_BATTERY_CHARGING_LOOP_EXIT_MS; + uint32_t capacity; + if (google_chromeec_read_batt_remaining_capacity(&capacity) < 0) { + printk(BIOS_WARNING, "Failed to get battery capacity\n"); + return; + } + /* + * If the remaining battery is less than + * DEAD_BATT_CHG_THRESHOLD_MAH threshold, enter low-battery + * charging mode and start a timeout timer to come out from dead battery charging + * mode. + */ + if (capacity <= DEAD_BATT_CHG_THRESHOLD_MAH) { + has_entered_dead_battery_mode = true; + stopwatch_init_msecs_expire(&sw, dead_battery_charging_timeout_ms); + } + + do { + /* Add static delay before reading the charging applet pre-requisites */ + mdelay(DELAY_CHARGING_APPLET_MS); + + if (has_entered_dead_battery_mode) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Issuing power-off to come out from" + " dead battery charging mode.\n"); + google_chromeec_ap_poweroff(); + } + } + + /* + * Issue a shutdown if not charging. + */ + if (!get_battery_icurr_ma()) { + printk(BIOS_INFO, "Issuing power-off due to change in charging state.\n"); + if (detect_ac_unplug_event()) + indicate_charging_status(); + google_chromeec_offmode_heartbeat(); + google_chromeec_ap_poweroff(); + } + + /* + * Exit the charging loop in the event of lid open or power + * button press. + * + * Reset the device to ensure a fresh boot to OS. + * This is required to avoid any kind of tear-down due to ADSP-lite + * being loaded and need some clean up before loading ADSP firmware by + * linux kernel. + */ + if (detect_ec_manual_poweron_event()) { + printk(BIOS_INFO, "Exiting charging applet to boot to OS\n"); + do_board_reset(); + } + } while (true); +} + +/* + * Enable charging w/ 1A Icurrent supply at max. + */ +void enable_slow_battery_charging(void) +{ + /* Configure FCC and enable charging */ + printk(BIOS_INFO, "Use slow charging without fast charge support\n"); + spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_3A_STEP_50MA); + spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_3A_STEP_50MA); + spmi_write8(SMB3_CHGR_MAX_FCC_CFG, FCC_3A_STEP_50MA); + spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE); + spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE); + spmi_write8(SMB3_CHGR_CHRG_EN_CMD, CHRG_ENABLE); +} + +/* + * Disable charging. + */ +void disable_slow_battery_charging(void) +{ + printk(BIOS_INFO, "Disable slow charge support\n"); + spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE); + spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE); + spmi_write8(SMB3_CHGR_CHRG_EN_CMD, CHRG_DISABLE); + spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_DISABLE); + spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_DISABLE); + spmi_write8(SMB3_CHGR_MAX_FCC_CFG, FCC_DISABLE); +} + +/* + * Enable fast battery charging with ADSP support. + * + * This function loads SoCCP firmware and configures fast charging. + */ +void enable_fast_battery_charging(void) +{ + /* TODO */ +} + +bool platform_get_battery_soc_information(uint32_t *batt_pct) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return false; + + if (google_chromeec_read_batt_state_of_charge(batt_pct)) + return false; + + return true; +} + +void configure_dead_battery_boot(void) +{ + spmi_rmw8(SDAM15_MEM_061_ADDR, DEAD_BATT_STS, DEAD_BATT_STS); +} diff --git a/src/mainboard/google/calypso/chromeos-nogsc.fmd b/src/mainboard/google/calypso/chromeos-nogsc.fmd new file mode 100644 index 00000000000..6d3c49842fe --- /dev/null +++ b/src/mainboard/google/calypso/chromeos-nogsc.fmd @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +FLASH@0x0 CONFIG_ROM_SIZE { + WP_RO 8M { + RO_SECTION { + BOOTBLOCK 512K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 16K + } + + RW_MISC 184K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + } + + RW_SECTION_A 8704K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + RW_SECTION_B 8704K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) + +#if CONFIG_QC_QDUTT_ENABLE + RW_UNUSED 2304K + RW_QDUTT 1536K +#else + RW_UNUSED 3840K + RW_CDT 4K +#endif +} diff --git a/src/mainboard/google/calypso/chromeos.c b/src/mainboard/google/calypso/chromeos.c new file mode 100644 index 00000000000..dc20da1213b --- /dev/null +++ b/src/mainboard/google/calypso/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "board.h" + +void setup_chromeos_gpios(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + gpio_input(GPIO_AP_EC_INT); + + if (CONFIG(TPM_GOOGLE_TI50)) + gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_NO_PULL); + + if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) { + gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) { + gpio_output(GPIO_FPMCU_BOOT0, 0); + gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP); + } + } +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + /* TODO: Add required GPIO after referring to the schematics */ + const struct lb_gpio chromeos_gpios[] = { +#if CONFIG(EC_GOOGLE_CHROMEEC) + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, +#endif +#if CONFIG(TPM_GOOGLE_TI50) + {GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT), + "TPM interrupt"}, +#endif + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int cr50_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_GSC_AP_INT); +} diff --git a/src/mainboard/google/calypso/chromeos.fmd b/src/mainboard/google/calypso/chromeos.fmd new file mode 100644 index 00000000000..68ae38a12f7 --- /dev/null +++ b/src/mainboard/google/calypso/chromeos.fmd @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +FLASH@0x0 CONFIG_ROM_SIZE { + WP_RO 8M { + RO_SECTION { + BOOTBLOCK 512K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_GSCVD 8K + RO_VPD(PRESERVE) 16K + } + + RW_MISC 184K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + } + + RW_SECTION_A 8704K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + RW_SECTION_B 8704K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) + +#if CONFIG_QC_QDUTT_ENABLE + RW_UNUSED 2560K + RW_QDUTT 1536K +#else + RW_UNUSED 4M +#endif +} diff --git a/src/mainboard/google/calypso/devicetree.cb b/src/mainboard/google/calypso/devicetree.cb new file mode 100644 index 00000000000..a15a72d9077 --- /dev/null +++ b/src/mainboard/google/calypso/devicetree.cb @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/calypso + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # Root Bridge + end +end diff --git a/src/mainboard/google/calypso/mainboard.c b/src/mainboard/google/calypso/mainboard.c new file mode 100644 index 00000000000..c3d61cde0d8 --- /dev/null +++ b/src/mainboard/google/calypso/mainboard.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "board.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +bool mainboard_needs_pcie_init(void) +{ + return true; +} + +/* + * This function calls the underlying PMIC/EC function only once during the + * first execution and caches the result for all subsequent calls. + */ +static enum boot_mode_t get_boot_mode(void) +{ + static bool initialized = false; + static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL; + if (!initialized) { + enum boot_mode_t *boot_mode_ptr = cbmem_find(CBMEM_ID_BOOT_MODE); + if (boot_mode_ptr) + boot_mode = *boot_mode_ptr; + printk(BIOS_INFO, "Boot mode is %d\n", boot_mode); + initialized = true; + } + return boot_mode; +} + +static void trigger_critical_battery_shutdown(void) +{ + printk(BIOS_WARNING, "Critical battery level detected without charger! Shutting down.\n"); + + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + platform_handle_emergency_low_battery(); + + google_chromeec_ap_poweroff(); +} + +static void load_qc_se_firmware_early(void) +{ + /* ADSP I2C (Charger/Fuel gauge) */ + qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED); + + gpi_firmware_load(QUP_0_GSI_BASE); + gpi_firmware_load(QUP_1_GSI_BASE); + gpi_firmware_load(QUP_2_GSI_BASE); + gpi_firmware_load(QUP_3_GSI_BASE); +} + +static bool is_low_power_boot_with_charger(void) +{ + bool ret = false; + enum boot_mode_t boot_mode = get_boot_mode(); + if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) || + (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING) || + (boot_mode == LB_BOOT_MODE_RTC_WAKE)) + ret = true; + + return ret; +} + +#if CONFIG(PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR) +bool platform_is_off_mode_charging_active(void) +{ + return (get_boot_mode() == LB_BOOT_MODE_OFFMODE_CHARGING); +} +#endif + +static bool board_support_dead_battery_charging(void) +{ + uint32_t capacity; + + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return false; + + if (google_chromeec_read_batt_remaining_capacity(&capacity) < 0) { + printk(BIOS_WARNING, "Failed to get battery capacity; defaulting to slow charging\n"); + return true; + } + + /* + * If the remaining battery capacity is less than or equal to the + * threshold, set dead battery charging mode. + */ + return capacity <= DEAD_BATT_CHG_THRESHOLD_MAH; +} + +/* + * Handle charging and UI states for low-power or off-mode boot scenarios. + * This function handles the transitions needed when the device is powered + * solely to show a charging status rather than a full OS boot. + */ +static void handle_low_power_charging_boot(void) +{ + if (!pll_init_and_set(apss_ncc0, L_VAL_710P4MHz)) + printk(BIOS_DEBUG, "CPU Frequency set to 710MHz\n"); + + if (board_support_dead_battery_charging()) + configure_dead_battery_boot(); + + /* FIXME: Add fast charging support */ + enable_slow_battery_charging(); + + /* + * Disable the lightbar for Low-Battery or Off-Mode charging sequences. + * This maintains visual consistency between the built-in display + * indicators and the external lightbar. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) + google_chromeec_lightbar_off(); + + /* Placeholder for display stop before launching charging applet */ + + /* Boot to charging applet; if this fails, the applet should trigger a reset */ + launch_charger_applet(); +} + +static void mainboard_init(void *chip_info) +{ + enum boot_mode_t boot_mode = get_boot_mode(); + + /* Do early display init for low/off-mode charging */ + if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY) || + (boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) || + (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING)) { + /* + * Manual delay for panel readiness; required because standard SOC IP + * initialization is bypassed to prioritize fast-charging boot speeds. + */ + mdelay(250); + /* Placeholder for display init */ + } + + /* + * Low-battery boot indicator is done. Therefore, power off if battery + * is critical and not charging + */ + if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY) + trigger_critical_battery_shutdown(); + + load_qc_se_firmware_early(); + + /* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */ + if (is_low_power_boot_with_charger()) { + handle_low_power_charging_boot(); + halt(); + } +} + +static void setup_audio(void) +{ + /* Placeholder for audio init */ +} + +static void setup_usb(void) +{ + /* Skip USB initialization if boot mode is "low-battery" or "off-mode charging"*/ + if (is_low_power_boot_with_charger()) + return; + + /* Placeholder for late USB init */ +} + +static void setup_usb_late(void) +{ + /* Skip USB initialization if boot mode is "low-battery" or "off-mode charging"*/ + if (is_low_power_boot_with_charger()) + return; + + /* Placeholder for late USB init */ +} + +void mainboard_soc_init(void) +{ + /* Setup USB related initial config */ + setup_usb(); + + /* Placeholder for display init in LB_BOOT_MODE_NORMAL */ + + /* Setup audio related initial config */ + setup_audio(); + + /* Setup USB related late config */ + setup_usb_late(); +} + +static void load_qc_se_firmware_late(void) +{ + /* + * Load console UART QUP firmware. + * This is required even if coreboot's serial output is disabled. + */ + if (!CONFIG(CONSOLE_SERIAL)) + qupv3_se_fw_load_and_init(QUPV3_2_SE5, SE_PROTOCOL_UART, FIFO); + + qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */ + qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */ + qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */ + + qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_I2C, MIXED); /* USB-C0 Re-Timer I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_I2C, MIXED); /* USB-C1 Re-Timer I2C */ + qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* USB-C2 Re-Timer I2C */ + + qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */ +} + +static void mainboard_late_init(struct device *dev) +{ + load_qc_se_firmware_late(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_late_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; diff --git a/src/mainboard/google/calypso/reset.c b/src/mainboard/google/calypso/reset.c new file mode 100644 index 00000000000..deb0ba8096a --- /dev/null +++ b/src/mainboard/google/calypso/reset.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE); +} diff --git a/src/mainboard/google/calypso/romstage.c b/src/mainboard/google/calypso/romstage.c new file mode 100644 index 00000000000..aa9f730872a --- /dev/null +++ b/src/mainboard/google/calypso/romstage.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "board.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DELAY_FOR_SHIP_MODE 11000 /* 11sec */ +static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL; +static bool battery_present = true; +static bool battery_below_threshold = false; +static int32_t battery_cfet_status = 1; /* Active C-FET */ +static int32_t battery_dfet_status = 1; /* Active D-FET */ +static bool battery_is_cutoff = false; +static bool battery_needs_recovery = false; +static bool chipset_dload_mode_active = false; /* Mode for crashlog */ + +/* + * is_off_mode - Check if the system is booting due to an off-mode power event. + * + * This function provides the board-level policy wrapper for detecting if the + * system power-on was triggered by an external charging event (e.g., cable + * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING. + * + * @return true if the system was triggered by a specific off-mode reason + * (e.g., charging cable insertion). + * @return false otherwise. + */ +static bool is_off_mode(void) +{ + /* placeholder */ + return false; +} + +static enum boot_mode_t set_boot_mode(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return boot_mode; + + enum boot_mode_t boot_mode_new; + + if (!battery_present) { + boot_mode_new = LB_BOOT_MODE_NO_BATTERY; + } else if (google_chromeec_is_rtc_event()) { + boot_mode_new = LB_BOOT_MODE_RTC_WAKE; + } else if (is_off_mode()) { + boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING; + } else if (battery_below_threshold) { + if (google_chromeec_is_charger_present()) + boot_mode_new = LB_BOOT_MODE_LOW_BATTERY_CHARGING; + else + boot_mode_new = LB_BOOT_MODE_LOW_BATTERY; + } else { + boot_mode_new = LB_BOOT_MODE_NORMAL; + } + + boot_mode = boot_mode_new; + return boot_mode_new; +} + +static void platform_init_lightbar(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) + return; + + /* + * Early initialization of the Chrome EC lightbar. + * Ensures visual continuity if the AP firmware disabled the lightbar + * in a previous boot without a subsequent EC reset. + */ + google_chromeec_lightbar_on(); +} +/* + * Update and cache battery status from the EC. + * This should be called once, early in the boot process, + * after the EC is reachable. + */ +static void update_battery_status(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + struct ec_response_battery_get_misc_info misc_info; + bool misc_info_valid = false; + + battery_present = google_chromeec_is_battery_present(); + battery_below_threshold = google_chromeec_is_below_critical_threshold(); + + if (battery_present && (google_chromeec_get_battery_misc_info(&misc_info) == 0)) { + battery_cfet_status = misc_info.cfet_status; + battery_dfet_status = misc_info.dfet_status; + misc_info_valid = true; + } else { + printk(BIOS_WARNING, "Failed to get battery FET status from EC\n"); + battery_cfet_status = -1; + battery_dfet_status = -1; + } + + /* + * SHIP MODE RECOVERY HANDLER: + * Triggered ONLY when the battery info was successfully read, + * and BOTH FETs are explicitly 0 (indicating a locked BMS). + */ + battery_needs_recovery = misc_info_valid && (battery_cfet_status == 0) + && (battery_dfet_status == 0); + + /* + * BATTERY CUTOFF / DISCONNECT DETECTION: + * Triggered when the hardware reports no battery present AND + * the EC FET status read failed (returning -1). + */ + battery_is_cutoff = (battery_cfet_status == -1) && (battery_dfet_status == -1); + +} + +/* Perform romstage early hardware initialization */ +static void mainboard_setup_peripherals_early(void) +{ + platform_init_lightbar(); + + update_battery_status(); + + /* Watchdog must be checked first to avoid erasing watchdog info later. */ + check_wdog(); +} + +/* Perform romstage late hardware initialization */ +static void mainboard_setup_peripherals_late(int mode) +{ + /* + * Power on NVMe early so that the DDR init and other operations + * that follow provide an organic >50ms delay before PCIe PERST + * de-assertion in platform_romstage_postram(), satisfying the + * NVMe spec requirement without a static mdelay(). + */ + gcom_pcie_power_on_ep(); + + if (!chipset_dload_mode_active) { + /* Perform PCIe setup early in async mode if supported to save 100ms */ + if (mode == LB_BOOT_MODE_NORMAL || mode == LB_BOOT_MODE_NO_BATTERY) + qcom_setup_pcie_host(NULL); + else + gcom_pcie_power_off_ep(); + } + + /* + * Enable fingerprint power rail early for stability prior to + * its reset being deasserted in ramstage. + * Requires >=200ms delay after its pin was driven low in bootblock. + */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) { + if (mode == LB_BOOT_MODE_NORMAL || mode == LB_BOOT_MODE_NO_BATTERY) + gpio_output(GPIO_EN_FP_RAILS, 1); + } +} + +static void handle_battery_shipping_recovery(bool board_reset) +{ + printk(BIOS_INFO, "==================================================\n"); + printk(BIOS_INFO, "Device has entered into shipping recovery mode.\n"); + printk(BIOS_INFO, "Please wait ...\n"); + printk(BIOS_INFO, "==================================================\n"); + + enable_slow_battery_charging(); + mdelay(DELAY_FOR_SHIP_MODE); + + if (board_reset) { + printk(BIOS_INFO, "Issuing board reset\n"); + do_board_reset(); + } + + /* Disable charging where `board_reset` is not allowed */ + disable_slow_battery_charging(); + +} + +void platform_romstage_main(void) +{ + mainboard_setup_peripherals_early(); + chipset_dload_mode_active = qclib_check_dload_mode(); + + if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL)) { + uint32_t batt_pct; + if (platform_get_battery_soc_information(&batt_pct)) + printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct); + else + printk(BIOS_WARNING, "Failed to get battery level\n"); + } + + if (!chipset_dload_mode_active) + shrm_fw_load_reset(); + + /* QCLib: DDR init & train */ + qclib_load_and_run(); + + /* Recovery from battery shipping mode */ + if (battery_needs_recovery || battery_is_cutoff) + handle_battery_shipping_recovery(battery_needs_recovery); + + /* Underlying PMIC registers are accessible only at this point */ + set_boot_mode(); + + if (!chipset_dload_mode_active) + aop_fw_load_reset(); + + mainboard_setup_peripherals_late(boot_mode); + + qclib_rerun(); +} + +void platform_romstage_postram(void) +{ + enum boot_mode_t *boot_mode_ptr = cbmem_add(CBMEM_ID_BOOT_MODE, sizeof(*boot_mode_ptr)); + if (boot_mode_ptr) { + *boot_mode_ptr = boot_mode; + printk(BIOS_INFO, "Boot mode is %d\n", *boot_mode_ptr); + } +} diff --git a/src/mainboard/google/cherry/Makefile.mk b/src/mainboard/google/cherry/Makefile.mk index 41ec839afcf..94275bad383 100644 --- a/src/mainboard/google/cherry/Makefile.mk +++ b/src/mainboard/google/cherry/Makefile.mk @@ -21,3 +21,5 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += regulator.c ramstage-y += reset.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index 39d5aa093e4..f76f10dee26 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,8 +8,6 @@ #include #include -#include "gpio.h" - static void nor_set_gpio_pinmux(void) { const struct pad_func *ptr = NULL; diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 7838c5e6802..9ca60c00ae6 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); diff --git a/src/mainboard/google/cherry/gpio.h b/src/mainboard/google/cherry/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/cherry/gpio.h rename to src/mainboard/google/cherry/include/baseboard/gpio.h diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index a0d5f809903..b80ba235fa0 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -18,8 +19,6 @@ #include #include -#include "gpio.h" - /* GPIO to schematics names */ #define GPIO_AP_EDP_BKLTEN GPIO(DGI_D5) #define GPIO_BL_PWM_1V8 GPIO(DISP_PWM0) @@ -103,7 +102,7 @@ static void configure_audio(void) static void mainboard_init(struct device *dev) { if (display_init_required()) - mtk_display_init(); + mtk_display_init(NULL); else printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); diff --git a/src/mainboard/google/cherry/reset.c b/src/mainboard/google/cherry/reset.c index 91ee7c074de..7622a7f32c2 100644 --- a/src/mainboard/google/cherry/reset.c +++ b/src/mainboard/google/cherry/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_RESET, 1); diff --git a/src/mainboard/google/corsola/Makefile.mk b/src/mainboard/google/corsola/Makefile.mk index ef60282a308..5d4380769bb 100644 --- a/src/mainboard/google/corsola/Makefile.mk +++ b/src/mainboard/google/corsola/Makefile.mk @@ -30,3 +30,5 @@ ramstage-y += reset.c ramstage-$(CONFIG_BOARD_GOOGLE_STARMIE) += panel_starmie.c ramstage-$(CONFIG_BOARD_GOOGLE_WUGTRIO) += panel_wugtrio.c ramstage-$(CONFIG_BOARD_GOOGLE_WYRDEER) += panel_wyrdeer.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c index b0aa888347f..fdf9475d2a8 100644 --- a/src/mainboard/google/corsola/boardid.c +++ b/src/mainboard/google/corsola/boardid.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include #include -#include "panel.h" - /* board_id is provided by ec/google/chromeec/ec_boardid.c */ #define ADC_LEVELS 12 diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index 292f1b92e73..c7ba2a2990d 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -#include "gpio.h" - static void usb3_hub_reset(void) { gpio_output(GPIO_USB3_HUB_RST_L, 1); diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index a1674d3c132..8ca5a3b5d37 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include #include #include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { /* Set up open-drain pins */ diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/corsola/gpio.h rename to src/mainboard/google/corsola/include/baseboard/gpio.h diff --git a/src/mainboard/google/corsola/panel.h b/src/mainboard/google/corsola/include/baseboard/panel.h similarity index 97% rename from src/mainboard/google/corsola/panel.h rename to src/mainboard/google/corsola/include/baseboard/panel.h index 9190a237829..0b8d499374b 100644 --- a/src/mainboard/google/corsola/panel.h +++ b/src/mainboard/google/corsola/include/baseboard/panel.h @@ -7,6 +7,7 @@ #include #include #include +#include #define BRIDGE_I2C I2C0 #define PMIC_AW37503_SLAVE 0x3E diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 1a0ab3c9171..e938af163d4 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -12,9 +14,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - static void configure_alc1019(void) { mtcmos_audio_power_on(); @@ -71,7 +70,7 @@ static void mainboard_init(struct device *dev) register_reset_to_bl31(GPIO_RESET.id, true); if (display_init_required()) { - if (mtk_display_init() < 0) + if (mtk_display_init(NULL) < 0) printk(BIOS_ERR, "%s: Failed to init display\n", __func__); } else { if (CONFIG(BOARD_GOOGLE_STARYU_COMMON)) { diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c index 5e773e3a1f8..6f73596974a 100644 --- a/src/mainboard/google/corsola/panel.c +++ b/src/mainboard/google/corsola/panel.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -9,9 +11,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - void aw37503_init(unsigned int bus) { i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x14, 0x1F, 0); diff --git a/src/mainboard/google/corsola/panel_anx7625.c b/src/mainboard/google/corsola/panel_anx7625.c index 048713fafdd..d5c7a184b8d 100644 --- a/src/mainboard/google/corsola/panel_anx7625.c +++ b/src/mainboard/google/corsola/panel_anx7625.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -8,9 +10,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - static void bridge_anx7625_power_on(void) { /* Turn on bridge */ diff --git a/src/mainboard/google/corsola/panel_ps8640.c b/src/mainboard/google/corsola/panel_ps8640.c index 94bf47d3128..55944885e49 100644 --- a/src/mainboard/google/corsola/panel_ps8640.c +++ b/src/mainboard/google/corsola/panel_ps8640.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -8,9 +10,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - static void bridge_ps8640_power_on(void) { /* diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index 5a1228cddf8..e9c7ab9702a 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include -#include "gpio.h" -#include "panel.h" - static void mipi_panel_power_on(void) { struct tps65132s_cfg config = { diff --git a/src/mainboard/google/corsola/panel_tps65132s.c b/src/mainboard/google/corsola/panel_tps65132s.c index 36933c0bc73..e5ae0901871 100644 --- a/src/mainboard/google/corsola/panel_tps65132s.c +++ b/src/mainboard/google/corsola/panel_tps65132s.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include #include -#include "gpio.h" -#include "panel.h" - void tps65132s_power_on(struct tps65132s_cfg *config) { const struct tps65132s_reg_setting reg_settings[] = { diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c index 7a729b2724a..1ce1ba0946a 100644 --- a/src/mainboard/google/corsola/panel_wugtrio.c +++ b/src/mainboard/google/corsola/panel_wugtrio.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include -#include "gpio.h" -#include "panel.h" - static void mipi_panel_power_on(void) { mainboard_set_regulator_voltage(MTK_REGULATOR_VIO18, 1800000); diff --git a/src/mainboard/google/corsola/panel_wyrdeer.c b/src/mainboard/google/corsola/panel_wyrdeer.c index 5d6379d1cee..c21e7f3966c 100644 --- a/src/mainboard/google/corsola/panel_wyrdeer.c +++ b/src/mainboard/google/corsola/panel_wyrdeer.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include -#include "gpio.h" -#include "panel.h" - static void mipi_panel_power_on(void) { struct tps65132s_cfg config = { diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c index 91ee7c074de..7622a7f32c2 100644 --- a/src/mainboard/google/corsola/reset.c +++ b/src/mainboard/google/corsola/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_RESET, 1); diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h index 7955e33ab92..2f11940ce21 100644 --- a/src/mainboard/google/cyan/ec.h +++ b/src/mainboard/google/cyan/ec.h @@ -23,7 +23,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 7e470d6b87e..6a0b98712c3 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -77,6 +77,7 @@ config BOARD_GOOGLE_BOTEN select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_BOXY select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 @@ -93,6 +94,7 @@ config BOARD_GOOGLE_BUGZZY select DRIVERS_I2C_SX9360 select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CAPPY2 select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 @@ -143,10 +145,11 @@ config BOARD_GOOGLE_DRAWCIA select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_DRIBLEE select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 @@ -182,6 +185,7 @@ config BOARD_GOOGLE_KRACKO select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_LALALA select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 @@ -202,6 +206,7 @@ config BOARD_GOOGLE_MADOO select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_MAGOLOR select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 @@ -211,11 +216,13 @@ config BOARD_GOOGLE_MAGOLOR select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_METAKNIGHT select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PIRIKA select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 @@ -246,9 +253,10 @@ config BOARD_GOOGLE_STORO select DRIVERS_I2C_SX9324 select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_IPU + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_TARANZA select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 @@ -279,7 +287,7 @@ if BOARD_GOOGLE_BASEBOARD_DEDEDE config BASEBOARD_DEDEDE_LAPTOP def_bool n select DRIVERS_GFX_GENERIC - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE config CHROMEOS select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c index 50f85c90cba..9fd2a26aa90 100644 --- a/src/mainboard/google/dedede/cfr.c +++ b/src/mainboard/google/dedede/cfr.c @@ -32,6 +32,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index a668412003d..39b408884bb 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -87,7 +87,8 @@ static void mainboard_init(void *chip_info) * For chromeboxes, wait for DP HPD to be asserted before * entering FSP-S, otherwise display init may fail. */ - if (!CONFIG(SYSTEM_TYPE_LAPTOP) && display_init_required()) + if (!CONFIG(SYSTEM_TYPE_LAPTOP) && !CONFIG(SYSTEM_TYPE_CONVERTIBLE) && + display_init_required()) mainboard_wait_for_hpd(); base_pads = baseboard_gpio_table(&base_num); diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d7f91cda461..f03631683a1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -41,7 +41,6 @@ fw_config end chip soc/intel/jasperlake - device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -204,9 +203,6 @@ chip soc/intel/jasperlake # For an offset = 12.580, use 12580 register "ImonOffset" = "0" - # Skip the CPU replacement check - register "SkipCpuReplacementCheck" = "1" - # Sagv Configuration register "SaGv" = "SaGv_Enabled" @@ -284,8 +280,6 @@ chip soc/intel/jasperlake device ref gna on end device ref south_xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index 1e510536a4a..78a5b67ef9f 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -142,6 +142,10 @@ chip soc/intel/jasperlake "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/dedede/variants/boten/include/variant/ec.h b/src/mainboard/google/dedede/variants/boten/include/variant/ec.h index 08870e0627b..99ff519a849 100644 --- a/src/mainboard/google/dedede/variants/boten/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/boten/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index aa54ba3059c..b3e9b3b5241 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -150,8 +150,6 @@ chip soc/intel/jasperlake end device ref south_xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h index 08870e0627b..99ff519a849 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h index 27c930d4f25..f721a22ec7c 100644 --- a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/gooey/overridetree.cb b/src/mainboard/google/dedede/variants/gooey/overridetree.cb index 05144d1ff4e..6f63228bd70 100644 --- a/src/mainboard/google/dedede/variants/gooey/overridetree.cb +++ b/src/mainboard/google/dedede/variants/gooey/overridetree.cb @@ -129,8 +129,6 @@ chip soc/intel/jasperlake end device ref south_xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h index 08870e0627b..99ff519a849 100644 --- a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h index d6c3859c91b..927b8a62d49 100644 --- a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h index 27c930d4f25..f721a22ec7c 100644 --- a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h index 08870e0627b..99ff519a849 100644 --- a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb index 831ef975a28..de9cf55330c 100644 --- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb +++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb @@ -237,6 +237,12 @@ chip soc/intel/jasperlake end end end + device ref pcie_rp8 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end device ref hda on chip drivers/generic/alc1015 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" diff --git a/src/mainboard/google/dedede/variants/storo/include/variant/ec.h b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h index 08870e0627b..99ff519a849 100644 --- a/src/mainboard/google/dedede/variants/storo/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/drallion/cfr.c b/src/mainboard/google/drallion/cfr.c index 805b2870a12..51063ed37b3 100644 --- a/src/mainboard/google/drallion/cfr.c +++ b/src/mainboard/google/drallion/cfr.c @@ -14,6 +14,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1830dd32208..3760655702f 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -239,9 +239,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" diff --git a/src/mainboard/google/eve/cfr.c b/src/mainboard/google/eve/cfr.c index efddc4d7c89..62ef412d7a9 100644 --- a/src/mainboard/google/eve/cfr.c +++ b/src/mainboard/google/eve/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl index 03882c63276..3eac959affd 100644 --- a/src/mainboard/google/fatcat/dsdt.asl +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -25,6 +25,7 @@ DefinitionBlock( #include #include #include + #include } #if CONFIG(EC_GOOGLE_CHROMEEC) diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c index b731f1d4d51..66aa7d80ee7 100644 --- a/src/mainboard/google/fatcat/mainboard.c +++ b/src/mainboard/google/fatcat/mainboard.c @@ -62,18 +62,30 @@ static void mainboard_early(void *unused) BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL); -void __weak fw_config_post_gpio_configure(void) +void __weak variant_pre_dev_init_chips_configure(void) { /* default implementation does nothing */ } static void mainboard_pre_dev_init_chips(void *unused) { - fw_config_post_gpio_configure(); + variant_pre_dev_init_chips_configure(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, mainboard_pre_dev_init_chips, NULL); +void __weak variant_post_dev_init_chips_configure(void) +{ + /* default implementation does nothing */ +} + +static void mainboard_post_dev_init_chips(void *unused) +{ + variant_post_dev_init_chips_configure(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, mainboard_post_dev_init_chips, NULL); + void __weak baseboard_devtree_update(void) { /* Override dev tree settings per baseboard */ diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c index 04b39c58c48..c574d60085b 100644 --- a/src/mainboard/google/fatcat/romstage.c +++ b/src/mainboard/google/fatcat/romstage.c @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include /* @@ -44,6 +46,18 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* Override FSP-M UPD per board if required. */ variant_update_soc_memory_init_params(memupd); + + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + /* Disable CPU ratio override for unstable power scenarios */ + if (!google_chromeec_is_battery_present() || + google_chromeec_is_below_critical_threshold()) { + const struct soc_intel_pantherlake_config *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + if (config->cpu_ratio_override) + m_cfg->CpuRatio = 0; + } } void platform_romstage_pre_mem(void) @@ -55,12 +69,4 @@ void platform_romstage_pre_mem(void) */ if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) google_chromeec_lightbar_on(); - - /* - * Only alert the user (set LED to red in color) if the lid is closed and the battery - * is critically low without AC power. - */ - if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() && - google_chromeec_is_critically_low_on_battery()) - google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00); } diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk index 47123cd318a..82c905f61f1 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk @@ -2,3 +2,4 @@ romstage-y += memory.c ramstage-y += ramstage.c +ramstage-y += reset.c diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c index 224dda7443d..dfb656fc078 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c @@ -1,8 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include +#include #include +/* Threshold for selecting lower-resolution assets */ +#define FHD_WIDTH_THRESHOLD 1920 + +/* + * Helper to determine if the current panel is low-resolution (<= FHD). + */ +static bool is_low_res_panel(void) +{ + const struct hob_graphics_info *ginfo; + size_t size; + + /* Find the graphics information HOB */ + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); + if (!ginfo || ginfo->framebuffer_base == 0) + return false; + + return ginfo->horizontal_resolution <= FHD_WIDTH_THRESHOLD; +} + +/* + * Mainboard-specific override for logo filenames. + */ +const char *mainboard_bmp_logo_filename(void) +{ + if (is_low_res_panel()) + return "cb_plus_logo.bmp"; + + return "cb_logo.bmp"; +} + /* * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) @@ -18,9 +50,9 @@ #define COMMON_PTL_U_POWER_LIMITS \ .pl1_min_power = 10000, \ .pl1_max_power = 15000, \ - .pl2_min_power = 50000, \ - .pl2_max_power = 50000, \ - .pl4_power = 65000 + .pl2_min_power = 25000, \ + .pl2_max_power = 25000, \ + .pl4_power = 25000 const struct cpu_tdp_power_limits power_optimized_limits[] = { { .mch_id = PCI_DID_INTEL_PTL_H_ID_1, @@ -88,6 +120,18 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = { .power_limits_index = PTL_CORE_2, COMMON_PTL_U_POWER_LIMITS }, + { + .mch_id = PCI_DID_INTEL_PTL_U_ID_1, + .cpu_tdp = TDP_25W, + .power_limits_index = PTL_CORE_1, + COMMON_PTL_U_POWER_LIMITS + }, + { + .mch_id = PCI_DID_INTEL_PTL_U_ID_2, + .cpu_tdp = TDP_25W, + .power_limits_index = PTL_CORE_2, + COMMON_PTL_U_POWER_LIMITS + }, }; /* diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/reset.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/reset.c new file mode 100644 index 00000000000..e61255553ce --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/reset.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static void handle_board_poweroff(void *unused) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + /* If lid is open, we do nothing */ + if (CONFIG(VBOOT_LID_SWITCH) && get_lid_switch()) + return; + + const struct lb_framebuffer *fb = get_lb_framebuffer(); + + /* + * Shut down if: + * 1. Framebuffer is NULL (no display initialized) + * OR + * 2. Framebuffer exists but 'has_external_display' is false + */ + if (!fb || !fb->flags.has_external_display) { + printk(BIOS_INFO, "Lid closed, no external display: Initiating shutdown.\n"); + google_chromeec_ap_poweroff(); + } +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, handle_board_poweroff, NULL); diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h index e0f49965797..9fdd55cc6d5 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -19,7 +19,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); void fw_config_configure_pre_mem_gpio(void); void fw_config_gpio_padbased_override(struct pad_config *padbased_table); -void fw_config_post_gpio_configure(void); +void variant_pre_dev_init_chips_configure(void); +void variant_post_dev_init_chips_configure(void); const struct mb_cfg *variant_memory_params(void); void variant_get_spd_info(struct mem_spd *spd_info); diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 329df7e09ad..0d2ae2e8516 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -776,7 +776,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) } } -void fw_config_post_gpio_configure(void) +void variant_pre_dev_init_chips_configure(void) { if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) GPIO_CONFIGURE_PADS(post_x1slot_pads); diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 5ad0dc63c89..766ad7a1d26 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -636,7 +636,7 @@ chip soc/intel/pantherlake chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "wake" = "GPE0_DW0_12" # GPP_A12 - use usb2_port7 as bluetooth_companion + use usb2_port8 as bluetooth_companion device pci 00.0 on probe WIFI WIFI_PCIE_6 probe WIFI WIFI_PCIE_7 diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c index cb42dfb3b0f..58487996451 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/variant.c +++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c @@ -22,6 +22,9 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) config->cnvi_wifi_core = true; config->cnvi_bt_core = true; + if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE))) + config->cnvi_wwan_coex = true; + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S)) || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) { diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb index 3353bf5c8d6..7737d08c96d 100644 --- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb @@ -88,6 +88,9 @@ chip soc/intel/pantherlake [DDI_PORT_A] = DDI_ENABLE_HPD, }" + # VCCSA Shutdown configuration + register "vccsa_shutdown" = "1" # enable (set to 0 for disable) + # Enable CNVi Wi-Fi and Bluetooth register "cnvi_wifi_core" = "true" register "cnvi_bt_core" = "true" @@ -443,6 +446,8 @@ chip soc/intel/pantherlake register "mode" = "THC_HID_I2C_MODE" register "dev_hidi2c.intf.hidi2c.addr" = "0x15" register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x01" + register "dev_hidi2c.intf.hidi2c.interrupt_delay_value" = "100" + register "dev_hidi2c.intf.hidi2c.max_frame_size_value" = "128" register "soc_hidi2c.fm_scl_low_period" = "160" register "soc_hidi2c.fm_scl_high_period" = "146" register "wake_on_touch" = "true" @@ -456,7 +461,7 @@ chip soc/intel/pantherlake end end #Trackpad device ref thc1 on - register "thc_wake_on_touch[1]" = "true" + register "thc_wake_on_touch[1]" = "false" register "thc_mode[1]" = "THC_HID_I2C_MODE" probe TOUCHSCREEN TOUCHSCREEN_RAYDIUM probe TOUCHSCREEN TOUCHSCREEN_ILITEK @@ -467,8 +472,10 @@ chip soc/intel/pantherlake register "dev_hidi2c.cid" = ""PNP0C50"" register "dev_hidi2c.intf.hidi2c.addr" = "0x39" register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0" + register "dev_hidi2c.intf.hidi2c.interrupt_delay_value" = "100" + register "dev_hidi2c.intf.hidi2c.max_frame_size_value" = "128" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" - register "wake_on_touch" = "true" + register "wake_on_touch" = "false" # NOTE: Use GpioInt() in _CRS and does not use GPE. register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" register "active_ltr" = "1" @@ -486,8 +493,10 @@ chip soc/intel/pantherlake register "dev_hidi2c.cid" = ""PNP0C50"" register "dev_hidi2c.intf.hidi2c.addr" = "0x41" register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x0001" + register "dev_hidi2c.intf.hidi2c.interrupt_delay_value" = "100" + register "dev_hidi2c.intf.hidi2c.max_frame_size_value" = "128" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" - register "wake_on_touch" = "true" + register "wake_on_touch" = "false" # NOTE: Use GpioInt() in _CRS and does not use GPE. register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" register "active_ltr" = "1" @@ -508,6 +517,7 @@ chip soc/intel/pantherlake # SoundWire Link 3 ID 0 register "desc" = ""Headset Codec"" register "sub" = ""1337"" + register "detect_us" = "DET_100_US" device generic 3.0 on end end chip drivers/soundwire/cs35l56 diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c index 7f6aa0cdb76..eb1db7839ae 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/gpio.c +++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c @@ -195,7 +195,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E03: GEN5_SSD_RESET_N */ PAD_CFG_GPO(GPP_E03, 1, PLTRST), /* GPP_E05: TCHSCR_RPT_EN */ - PAD_CFG_GPO(GPP_E05, 0, PLTRST), + PAD_CFG_GPO(GPP_E05, 1, PLTRST), /* GPP_E06: NC */ PAD_NC(GPP_E06, NONE), /* GPP_E07 : [] ==> EC_SOC_INT_ODL */ @@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = { /* GPP_F13: TCHSCR_I2C5_SDA */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* GPP_F16: TCHSCR_RST_L */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), + PAD_CFG_GPO(GPP_F16, 0, DEEP), /* GPP_F17: NC */ PAD_NC(GPP_F17, NONE), /* GPP_F18: TCHSCR_INT_L */ @@ -392,6 +392,8 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_E03: GEN5_SSD_RESET_N */ PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_F08: EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h index cced66807a0..277aca3050c 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h +++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h @@ -8,4 +8,6 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +#define TCHSCR_RST_L GPP_F16 + #endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb index 28b2fec9846..ed93b129f08 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb @@ -60,6 +60,9 @@ chip soc/intel/pantherlake .tdp_pl4 = 152, }" + # VCCSA Shutdown configuration + register "vccsa_shutdown" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_CAMERA @@ -473,10 +476,8 @@ chip soc/intel/pantherlake register "generic.desc" = ""Focal Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" register "generic.detect" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" - register "generic.reset_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" - register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "generic.use_gpio_for_status" = "true" register "hid_desc_reg_offset" = "0x01" diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c index 17ce4d2c2fa..76a6378f2bd 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/variant.c +++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c @@ -5,6 +5,7 @@ #include #include #include +#include const char *get_wifi_sar_cbfs_filename(void) { @@ -66,3 +67,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) config->tcss_ports[3] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP); } } + +void variant_post_dev_init_chips_configure(void) +{ + /* ensures touchscreen reset pin is asserted at the correct stage, + satisfying the requirement that reset must occur after BL_ON. */ + gpio_output(TCHSCR_RST_L, 1); + printk(BIOS_INFO, "TSR: assert touchscreen reset pin ...\n"); +} diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c index 9c800742550..6308d455e1e 100644 --- a/src/mainboard/google/fatcat/variants/ruby/gpio.c +++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c @@ -226,7 +226,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E18: TCHPAD_INT# */ PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT), /* GPP_E19: FPMCU_PWREN */ - PAD_CFG_GPO(GPP_E19, 1, DEEP), + PAD_CFG_GPO(GPP_E19, 1, PLTRST), /* GPP_E20: NC */ PAD_NC(GPP_E20, NONE), /* GPP_E21: I2C_PMC_PD_INT_N */ diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk index cc8e0af2eaa..ae5104aecc8 100644 --- a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = H58G56CK8BX146, MT62F1G32D2DS-020 WT:D, K3KL8L80EM-MGCV +SPD_SOURCES += spd/lp5/set-0/spd-15.hex # ID = 1(0b0001) Parts = H58G66EK9BX223, K3KL9L90EM-MGCV +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-020 WT:D diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt index de8e5b3344f..7d628ebcb38 100644 --- a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt +++ b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt DRAM Part Name ID to assign H58G56CK8BX146 0 (0000) MT62F1G32D2DS-020 WT:D 0 (0000) K3KL8L80EM-MGCV 0 (0000) +H58G66EK9BX223 1 (0001) +K3KL9L90EM-MGCV 1 (0001) +MT62F2G32D4DS-020 WT:D 2 (0010) diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt index 149a20f41f9..cc88edf1f2a 100644 --- a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt +++ b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt @@ -12,3 +12,6 @@ H58G56CK8BX146 MT62F1G32D2DS-020 WT:D K3KL8L80EM-MGCV +H58G66EK9BX223 +K3KL9L90EM-MGCV +MT62F2G32D4DS-020 WT:D diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb index 6b37f24a0f2..88993c66775 100644 --- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb @@ -87,6 +87,9 @@ chip soc/intel/pantherlake register "pcore_hysteresis_window_ms" = "3" register "ecore_hysteresis_window_ms" = "3" + # VCCSA Shutdown mitigation setting + register "vccsa_shutdown" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera) @@ -186,7 +189,94 @@ chip soc/intel/pantherlake device generic 0 on end end end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""5V choke"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 88), + TEMP_PCT(70, 78), + TEMP_PCT(65, 68), + TEMP_PCT(60, 58), + + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(80, 88), + TEMP_PCT(75, 78), + TEMP_PCT(70, 68), + TEMP_PCT(65, 58), + + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 88), + TEMP_PCT(70, 78), + TEMP_PCT(65, 68), + TEMP_PCT(60, 58), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 80, 5000), + }" + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 12000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 alias dptf_policy on end + end + end device ref iaa off end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index daaf81410ac..faefa1a2e3d 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -46,6 +46,9 @@ if BOARD_GOOGLE_BASEBOARD_FIZZ config DISABLE_HECI1_AT_PRE_BOOT default y +config INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING + default y + config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/fizz/board.h b/src/mainboard/google/fizz/board.h new file mode 100644 index 00000000000..fe7d3203646 --- /dev/null +++ b/src/mainboard/google/fizz/board.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GOOGLE_FIZZ_BOARD_H +#define MAINBOARD_GOOGLE_FIZZ_BOARD_H + +unsigned int fizz_default_pl2_watts(void); + +#endif diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c index 10df17757cb..becf6155174 100644 --- a/src/mainboard/google/fizz/cfr.c +++ b/src/mainboard/google/fizz/cfr.c @@ -1,10 +1,42 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include +#include "board.h" + +static const struct sm_object tdp_pl1_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl1_override", + .ui_name = "CPU PL1 power limit (W)", + .ui_helptext = "Long-duration CPU package power limit.\n" + "Default: 15 W. Range: 15-35 W.", + .default_value = 15, + .min = 15, + .max = 35, + .step = 1, + .display_flags = 0, +}); + +static void update_tdp_pl2_default(struct sm_object *new) +{ + new->sm_number.default_value = fizz_default_pl2_watts(); +} + +static const struct sm_object tdp_pl2_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl2_override", + .ui_name = "CPU PL2 power limit (W)", + .ui_helptext = "Short-duration CPU package power limit.\n" + "Default: 29 W (U22 SKUs) or 44 W (U42 SKUs). Range: 29-51 W.\n" + "Must be >= PL1 (enforced at boot).", + .default_value = 29, + .min = 29, + .max = 51, + .step = 1, + .display_flags = 0, +}, WITH_CALLBACK(update_tdp_pl2_default)); static struct sm_obj_form system = { .ui_name = "System", @@ -15,6 +47,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, @@ -37,6 +70,9 @@ static struct sm_obj_form power = { .ui_name = "Power", .obj_list = (const struct sm_object *[]) { &power_on_after_fail, + &tdp_pl1_override, + &tdp_pl2_override, + &pkg_power_limit_lock, NULL }, }; @@ -45,6 +81,9 @@ static struct sm_obj_form *sm_root[] = { &system, &ec, &power, +#if CONFIG(INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING) + &cpu_voltage, +#endif NULL }; diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index e908b9e6353..06b877ecc62 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +21,8 @@ #include +#include "board.h" + #define FIZZ_SKU_ID_I7_U42 0x4 #define FIZZ_SKU_ID_I5_U42 0x5 #define FIZZ_SKU_ID_I3_U42 0x6 @@ -29,8 +32,8 @@ #define FIZZ_SKU_ID_CEL_U22 0x0 #define FIZZ_PL2_U42 44 #define FIZZ_PL2_U22 29 -#define FIZZ_PSYSPL2_U22 65 -#define FIZZ_PSYSPL2_U42 90 +#define FIZZ_ADP_WATTS_U22 65 +#define FIZZ_ADP_WATTS_U42 90 #define FIZZ_MAX_TIME_WINDOW 6 #define FIZZ_MIN_DUTYCYCLE 4 /* @@ -69,6 +72,19 @@ static uint8_t board_sku_id(void) return sku_id; } +static bool is_u42_sku(void) +{ + uint8_t sku = board_sku_id(); + return sku == FIZZ_SKU_ID_I7_U42 || + sku == FIZZ_SKU_ID_I5_U42 || + sku == FIZZ_SKU_ID_I3_U42; +} + +unsigned int fizz_default_pl2_watts(void) +{ + return is_u42_sku() ? FIZZ_PL2_U42 : FIZZ_PL2_U22; +} + /* * mainboard_set_power_limits * @@ -102,44 +118,33 @@ static uint8_t board_sku_id(void) static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; - u32 watts; u16 volts_mv, current_ma; - u32 pl2, psyspl2; + u32 adapter_watts; int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); - uint8_t sku = board_sku_id(); - const uint32_t u42_mask = (1 << FIZZ_SKU_ID_I7_U42) | - (1 << FIZZ_SKU_ID_I5_U42) | - (1 << FIZZ_SKU_ID_I3_U42); - /* PL2 value is sku-based, no matter what charger we are using */ - pl2 = FIZZ_PL2_U22; - if ((1 << sku) & u42_mask) - pl2 = FIZZ_PL2_U42; conf->tdp_psyspl3 = conf->tdp_pl4 = 0; /* If we can't get charger info or not PD charger, assume barrel jack */ if (rv != 0 || type != USB_CHG_TYPE_PD) { - /* using the barrel jack, get PsysPL2 based on sku id */ - psyspl2 = FIZZ_PSYSPL2_U22; - /* Running a U42 SKU */ - if ((1 << sku) & u42_mask) - psyspl2 = FIZZ_PSYSPL2_U42; + /* using the barrel jack, get max adapter power based on sku id */ + adapter_watts = is_u42_sku() ? FIZZ_ADP_WATTS_U42 : FIZZ_ADP_WATTS_U22; } else { /* Detected TypeC. Base on max value of adapter */ - watts = ((u32)volts_mv * current_ma) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + adapter_watts = ((u32)volts_mv * current_ma) / 1000000; + conf->tdp_psyspl3 = SET_PSYSPL2(adapter_watts); /* set max possible time window */ conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE; - if ((1 << sku) & u42_mask) - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + if (is_u42_sku()) + conf->tdp_pl4 = SET_PSYSPL2(adapter_watts); } - conf->tdp_pl2_override = pl2; + /* PL2 value is sku-based, no matter what charger we are using */ + conf->tdp_pl2_override = fizz_default_pl2_watts(); + /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); + conf->tdp_psyspl2 = SET_PSYSPL2(adapter_watts); } static uint8_t read_oem_id_from_gpio(void) diff --git a/src/mainboard/google/geralt/Makefile.mk b/src/mainboard/google/geralt/Makefile.mk index 0975c5cd293..2fb5bcaf521 100644 --- a/src/mainboard/google/geralt/Makefile.mk +++ b/src/mainboard/google/geralt/Makefile.mk @@ -25,3 +25,5 @@ ramstage-y += regulator.c ramstage-y += reset.c ramstage-$(CONFIG_BOARD_GOOGLE_CIRI) += panel_ciri.c ramstage-$(CONFIG_BOARD_GOOGLE_GERALT) += panel_geralt.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/geralt/boardid.c b/src/mainboard/google/geralt/boardid.c index 4c53a810c4c..e1a11b3f63a 100644 --- a/src/mainboard/google/geralt/boardid.c +++ b/src/mainboard/google/geralt/boardid.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include -#include "panel.h" /* board_id is provided by ec/google/chromeec/ec_boardid.c */ diff --git a/src/mainboard/google/geralt/bootblock.c b/src/mainboard/google/geralt/bootblock.c index 73b0f8a8dc1..e87a71c9774 100644 --- a/src/mainboard/google/geralt/bootblock.c +++ b/src/mainboard/google/geralt/bootblock.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include "gpio.h" - static void usb3_hub_reset(void) { gpio_output(GPIO_USB3_HUB_RST_L, 1); diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c index df606f957b0..e6b3ea4323c 100644 --- a/src/mainboard/google/geralt/chromeos.c +++ b/src/mainboard/google/geralt/chromeos.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include +#include #include +#include #include #include #include -#include "gpio.h" -#include "panel.h" - void setup_chromeos_gpios(void) { /* Set up open-drain pins */ diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/geralt/gpio.h rename to src/mainboard/google/geralt/include/baseboard/gpio.h diff --git a/src/mainboard/google/geralt/panel.h b/src/mainboard/google/geralt/include/baseboard/panel.h similarity index 95% rename from src/mainboard/google/geralt/panel.h rename to src/mainboard/google/geralt/include/baseboard/panel.h index 381de0d3a79..e715ed5d3fb 100644 --- a/src/mainboard/google/geralt/panel.h +++ b/src/mainboard/google/geralt/include/baseboard/panel.h @@ -6,6 +6,7 @@ #include #include #include +#include void configure_mipi_pwm_backlight(bool enable); void fill_lp_backlight_gpios(struct lb_gpios *gpios); diff --git a/src/mainboard/google/geralt/mainboard.c b/src/mainboard/google/geralt/mainboard.c index b05e8b46312..6549c7ee4b7 100644 --- a/src/mainboard/google/geralt/mainboard.c +++ b/src/mainboard/google/geralt/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -11,8 +12,6 @@ #include #include -#include "gpio.h" - #define AFE_SE_SECURE_CON (AUDIO_BASE + 0x17a8) static void configure_i2s(void) @@ -48,7 +47,7 @@ static void mainboard_init(struct device *dev) mt6359p_init_pmif_arb(); if (display_init_required()) { - if (mtk_display_init() < 0) + if (mtk_display_init(NULL) < 0) printk(BIOS_ERR, "%s: Failed to init display\n", __func__); } else { printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index 6168a42acce..06922755f5c 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -11,9 +13,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - struct panel_description __weak *get_panel_description(uint32_t panel_id) { printk(BIOS_WARNING, "%s: %s: the panel configuration is not ready\n", diff --git a/src/mainboard/google/geralt/panel_ciri.c b/src/mainboard/google/geralt/panel_ciri.c index 448f0c4fff2..9222b4e1171 100644 --- a/src/mainboard/google/geralt/panel_ciri.c +++ b/src/mainboard/google/geralt/panel_ciri.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include -#include "gpio.h" -#include "panel.h" - #define PMIC_TPS65132_I2C I2C3 #define VOLTAGE_5_7V 0x11 #define VOLTAGE_6V 0x14 diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index cd6dbe9b447..aad54f83591 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include "gpio.h" -#include "panel.h" - #define PMIC_TPS65132_I2C I2C3 static void power_on_mipi_boe_tv110c9m_ll0(void) diff --git a/src/mainboard/google/geralt/reset.c b/src/mainboard/google/geralt/reset.c index 05a576b69c3..b0464f5488c 100644 --- a/src/mainboard/google/geralt/reset.c +++ b/src/mainboard/google/geralt/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); diff --git a/src/mainboard/google/geralt/verstage.c b/src/mainboard/google/geralt/verstage.c index e4b19fd9e7f..3ee3e033010 100644 --- a/src/mainboard/google/geralt/verstage.c +++ b/src/mainboard/google/geralt/verstage.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include "gpio.h" - void verstage_mainboard_init(void) { mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 746e326c04a..a80fcecd684 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -38,6 +38,7 @@ config BOARD_GOOGLE_CAROLINE select INTEL_GMA_HAVE_VBT select MAINBOARD_NO_FSP_GOP select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CAVE select BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl index a1276b21678..132194a6a34 100644 --- a/src/mainboard/google/glados/acpi/ec.asl +++ b/src/mainboard/google/glados/acpi/ec.asl @@ -5,6 +5,9 @@ #include #include +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/glados/cfr.c b/src/mainboard/google/glados/cfr.c index 2025ad32ee3..e5843e501e0 100644 --- a/src/mainboard/google/glados/cfr.c +++ b/src/mainboard/google/glados/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index dae3bf71706..7007e342af4 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -43,18 +43,20 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI - select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 config BOARD_GOOGLE_DEWATT select BOARD_GOOGLE_BASEBOARD_GUYBRUSH + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GUYBRUSH select BOARD_GOOGLE_BASEBOARD_GUYBRUSH + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_NIPPERKIN select BOARD_GOOGLE_BASEBOARD_GUYBRUSH select DRIVERS_GFX_GENERIC + select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_GUYBRUSH diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 147112ae004..dbade7e54b5 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -258,20 +258,6 @@ chip soc/amd/cezanne device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb3_port0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))" - device ref usb3_port1 on end - end chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" @@ -296,26 +282,26 @@ chip soc/amd/cezanne register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port3 on end end - end - end - end - device ref xhci_1 on # USB 3.1 (USB1) - chip drivers/usb/acpi - device ref xhci_1_root_hub on chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" + register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))" - device ref usb3_port4 on end + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb3_port0 on end end chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Left Type-A Port"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb3_port5 on end + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" @@ -340,6 +326,20 @@ chip soc/amd/cezanne register "use_gpio_for_status" = "true" device ref usb2_port6 on end end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port3 on end + end end end end diff --git a/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h b/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h index 9e61a440cff..dac67ca295b 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h +++ b/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h @@ -1,3 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + #include + +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + +#endif diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index f6177006afc..9a457312123 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -137,8 +137,7 @@ chip soc/amd/cezanne chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -146,8 +145,7 @@ chip soc/amd/cezanne register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 669bf15d07a..c6e9a7a1110 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -81,8 +81,7 @@ chip soc/amd/cezanne chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -169,8 +168,7 @@ chip soc/amd/cezanne register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" - register "wake" = "GEVENT_5" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_21)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)" diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f9845b701b2..9b3cb03bb0b 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -289,8 +289,7 @@ chip soc/amd/cezanne chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -344,8 +343,7 @@ chip soc/amd/cezanne register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" - register "wake" = "GEVENT_5" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_21)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)" diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1f9a7d2eb05..5db9a5061f0 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -29,12 +29,13 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL select SPI_TPM - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 config BOARD_GOOGLE_AKEMI select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_DRATINI select BOARD_GOOGLE_BASEBOARD_HATCH @@ -50,17 +51,20 @@ config BOARD_GOOGLE_HELIOS select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_HELIOS_DISKSWAP select BOARD_GOOGLE_BASEBOARD_HATCH select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_JINLON select BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_GFX_GENERIC select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_KINDRED select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c index 3ddcdb1a194..52f2bf972d5 100644 --- a/src/mainboard/google/hatch/cfr.c +++ b/src/mainboard/google/hatch/cfr.c @@ -24,6 +24,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index a1a71c0fd0b..771cd1e5b29 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -53,6 +53,9 @@ * ACPI related definitions for ASL code. */ +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 0edbf5ebab8..c7887596ed4 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -14,6 +14,8 @@ config BOARD_GOOGLE_BASEBOARD_JECHT select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select SOC_INTEL_BROADWELL + select RT8168_GET_MAC_FROM_VPD + select RT8168_SUPPORT_LEGACY_VPD_MAC select SUPERIO_ITE_IT8772F select SYSTEM_TYPE_MINIPC @@ -69,4 +71,7 @@ config EDK2_BOOT_TIMEOUT int default 5 +config INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING + default y + endif diff --git a/src/mainboard/google/jecht/Makefile.mk b/src/mainboard/google/jecht/Makefile.mk index 66ffb865552..63f3978d15a 100644 --- a/src/mainboard/google/jecht/Makefile.mk +++ b/src/mainboard/google/jecht/Makefile.mk @@ -10,7 +10,6 @@ romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -ramstage-y += lan.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/jecht/cfr.c b/src/mainboard/google/jecht/cfr.c index 199f2e54d99..86e55a8db87 100644 --- a/src/mainboard/google/jecht/cfr.c +++ b/src/mainboard/google/jecht/cfr.c @@ -1,8 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include +#include + +static const struct sm_object tdp_pl1_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl1_override", + .ui_name = "CPU PL1 power limit (W)", + .ui_helptext = "Long-duration CPU package power limit.\n" + "Default: 15 W. Range: 15-25 W.", + .default_value = 15, + .min = 15, + .max = 25, + .step = 1, + .display_flags = 0, +}); + +static const struct sm_object tdp_pl2_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl2_override", + .ui_name = "CPU PL2 power limit (W)", + .ui_helptext = "Short-duration CPU package power limit.\n" + "Default: 18 W. Range: 15-30 W.\n" + "Must be >= PL1 (enforced at boot).", + .default_value = 18, + .min = 15, + .max = 30, + .step = 1, + .display_flags = 0, +}); static struct sm_obj_form system = { .ui_name = "System", @@ -16,6 +43,9 @@ static struct sm_obj_form power = { .ui_name = "Power", .obj_list = (const struct sm_object *[]) { &power_on_after_fail, + &tdp_pl1_override, + &tdp_pl2_override, + &cpu_power_limit_lock, NULL }, }; @@ -23,6 +53,9 @@ static struct sm_obj_form power = { static struct sm_obj_form *sm_root[] = { &system, &power, +#if CONFIG(INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING) + &cpu_voltage, +#endif NULL }; diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 7c1b953b0c4..f43309dbac3 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 8de489c0ee7..5b20442f415 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -61,7 +61,13 @@ chip northbridge/intel/broadwell device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 + device pci 1c.2 on # PCIe Port #3 + chip drivers/net + register "device_index" = "0" + register "enable_pcie_clkreq" = "true" + device pci 00.0 on end + end + end device pci 1c.3 on end # PCIe Port #4 device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c deleted file mode 100644 index 1f90aa7ccfb..00000000000 --- a/src/mainboard/google/jecht/lan.c +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_ERR, "Invalid Hex digit found: %c - 0x%02x\n", *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (CONFIG(VPD)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_map("vpd.bin", &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(JECHT_NIC_VENDOR_ID, - JECHT_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((JECHT_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c deleted file mode 100644 index 0b3ae01c13b..00000000000 --- a/src/mainboard/google/jecht/mainboard.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "onboard.h" - -static void mainboard_init(struct device *dev) -{ - lan_init(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index ae68fb85834..cffb95eb4f4 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -4,8 +4,6 @@ #define ONBOARD_H #ifndef __ACPI__ -void lan_init(void); - void set_power_led(int state); enum { @@ -15,13 +13,6 @@ enum { }; #endif -/* defines for programming the MAC address */ -#define JECHT_NIC_VENDOR_ID 0x10EC -#define JECHT_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define JECHT_NIC_LED_MODE 0x00 - /* NIC wake is GPIO 8 */ #define JECHT_NIC_WAKE_GPIO 8 diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index e8726993c7c..3998a05f6a0 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); + { 0x0064, 1, 0, USB_PORT_MINI_PCIE }, /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL); + { 0x0040, 1, 0, USB_PORT_INTERNAL }, /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, USB_PORT_INTERNAL); + { 0x0040, 1, 1, USB_PORT_INTERNAL }, /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, USB_PORT_SKIP); + { 0x0000, 0, 0, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); + { 1, 1, 0 }, /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); + { 1, 2, 0 }, /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} + { 1, 2, 0 }, +}; diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index e8726993c7c..3998a05f6a0 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); + { 0x0064, 1, 0, USB_PORT_MINI_PCIE }, /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL); + { 0x0040, 1, 0, USB_PORT_INTERNAL }, /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, USB_PORT_INTERNAL); + { 0x0040, 1, 1, USB_PORT_INTERNAL }, /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, USB_PORT_SKIP); + { 0x0000, 0, 0, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); + { 1, 1, 0 }, /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); + { 1, 2, 0 }, /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} + { 1, 2, 0 }, +}; diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index e8726993c7c..3998a05f6a0 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); + { 0x0064, 1, 0, USB_PORT_MINI_PCIE }, /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL); + { 0x0040, 1, 0, USB_PORT_INTERNAL }, /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, USB_PORT_INTERNAL); + { 0x0040, 1, 1, USB_PORT_INTERNAL }, /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, USB_PORT_SKIP); + { 0x0000, 0, 0, USB_PORT_SKIP }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); + { 1, 0, 0 }, /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); + { 1, 1, 0 }, /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); + { 1, 2, 0 }, /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} + { 1, 2, 0 }, +}; diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 558d735864a..e7cf8ffe4e5 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -3,31 +3,32 @@ #include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0064, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P1: Port 3, USB3 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL); + { 0x0040, 1, 0, USB_PORT_INTERNAL }, /* P2: Port 4, USB4 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, USB_PORT_INTERNAL); + { 0x0040, 1, 1, USB_PORT_INTERNAL }, /* P3: Mini Card */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* P4: Port 1, USB1 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P5: Port 2, USB2 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, USB_PORT_INTERNAL); + { 0x0040, 1, 2, USB_PORT_INTERNAL }, /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL }, /* P7: Pin Header */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, 3, USB_PORT_INTERNAL); + { 0x0040, 1, 3, USB_PORT_INTERNAL }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: USB1 */ - pei_data_usb3_port(pei_data, 0, 1, 2, 0); + { 1, 2, 0 }, /* P2: USB2 */ - pei_data_usb3_port(pei_data, 1, 1, 2, 0); + { 1, 2, 0 }, /* P3: USB3 */ - pei_data_usb3_port(pei_data, 2, 1, 0, 0); + { 1, 0, 0 }, /* P4: USB4 */ - pei_data_usb3_port(pei_data, 3, 1, 1, 0); -} + { 1, 1, 0 }, +}; diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 157c317a620..347a40993b5 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -37,11 +37,12 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_SMU_FANLESS select SOC_AMD_STONEYRIDGE - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 config BOARD_GOOGLE_ALEENA select BOARD_GOOGLE_BASEBOARD_KAHLEE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CAREENA select BOARD_GOOGLE_BASEBOARD_KAHLEE @@ -54,9 +55,11 @@ config BOARD_GOOGLE_LIARA config BOARD_GOOGLE_NUWANI select BOARD_GOOGLE_BASEBOARD_KAHLEE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_TREEYA select BOARD_GOOGLE_BASEBOARD_KAHLEE + select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kukui/Makefile.mk b/src/mainboard/google/kukui/Makefile.mk index e1df671d56b..d22df72ad45 100644 --- a/src/mainboard/google/kukui/Makefile.mk +++ b/src/mainboard/google/kukui/Makefile.mk @@ -30,3 +30,5 @@ ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c ramstage-y += reset.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 13e7f4c38f1..86601ac8ca4 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index d59c230cc3b..cee14632a6e 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include "early_init.h" -#include "gpio.h" #define BOOTBLOCK_EN_L (GPIO(KPROW0)) #define AP_IN_SLEEP_L (GPIO(SRCLKENA0)) diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/kukui/gpio.h rename to src/mainboard/google/kukui/include/baseboard/gpio.h diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/include/baseboard/panel.h similarity index 100% rename from src/mainboard/google/kukui/panel.h rename to src/mainboard/google/kukui/include/baseboard/panel.h diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 22f8150d5e9..bea8df0135a 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include @@ -21,9 +23,6 @@ #include #include -#include "gpio.h" -#include "panel.h" - static void configure_emmc(void) { const gpio_t emmc_pin[] = { @@ -163,7 +162,7 @@ static bool configure_display(void) mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_LINE_END; if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, - panel->s->init) < 0) { + panel->s->init, NULL) < 0) { printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); return false; } diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index 45cf27c64c9..6537bf12b96 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -8,8 +9,6 @@ #include #include -#include "panel.h" - #define ANX7625_I2C_BUS 4 static struct panel_serializable_data anx7625_data = { diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c index 3ad9d6a4a18..4c4de016c36 100644 --- a/src/mainboard/google/kukui/panel_flapjack.c +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "panel.h" +#include static struct panel_description flapjack_panels[] = { [0] = { .name = "BOE_TV101WUM_NG0", .orientation = LB_FB_ORIENTATION_NORMAL}, diff --git a/src/mainboard/google/kukui/panel_kakadu.c b/src/mainboard/google/kukui/panel_kakadu.c index df9a92ebda2..c6593ec41c7 100644 --- a/src/mainboard/google/kukui/panel_kakadu.c +++ b/src/mainboard/google/kukui/panel_kakadu.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "panel.h" +#include static struct panel_description kakadu_panels[] = { [1] = { .name = "BOE_TV105WUM_NW0", .orientation = LB_FB_ORIENTATION_LEFT_UP}, diff --git a/src/mainboard/google/kukui/panel_katsu.c b/src/mainboard/google/kukui/panel_katsu.c index eeb957341e8..df2f2b8ca0f 100644 --- a/src/mainboard/google/kukui/panel_katsu.c +++ b/src/mainboard/google/kukui/panel_katsu.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "panel.h" +#include static struct panel_description katsu_panels[] = { [1] = { .name = "BOE_TV105WUM_NW0", .orientation = LB_FB_ORIENTATION_LEFT_UP}, diff --git a/src/mainboard/google/kukui/panel_kodama.c b/src/mainboard/google/kukui/panel_kodama.c index 35d3d91495b..27d6cf88b3c 100644 --- a/src/mainboard/google/kukui/panel_kodama.c +++ b/src/mainboard/google/kukui/panel_kodama.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "panel.h" +#include static struct panel_description kodama_panels[] = { [1] = { .name = "AUO_B101UAN08_3", .orientation = LB_FB_ORIENTATION_LEFT_UP}, diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c index 30887182d7e..eae41487c16 100644 --- a/src/mainboard/google/kukui/panel_krane.c +++ b/src/mainboard/google/kukui/panel_krane.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "panel.h" +#include static struct panel_description krane_panels[] = { [0] = { .name = "AUO_KD101N80_45NA", .orientation = LB_FB_ORIENTATION_LEFT_UP}, diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c index 283b641ee66..42eca29da95 100644 --- a/src/mainboard/google/kukui/panel_kukui.c +++ b/src/mainboard/google/kukui/panel_kukui.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include "panel.h" - static void power_on_ssd2858(void) { gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 0); diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index c1e8c4cc2cb..5f19e706f31 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,8 +8,6 @@ #include #include -#include "panel.h" - static void power_on_ps8640(void) { /* Disable backlight before turning on bridge */ diff --git a/src/mainboard/google/kukui/reset.c b/src/mainboard/google/kukui/reset.c index 91ee7c074de..7622a7f32c2 100644 --- a/src/mainboard/google/kukui/reset.c +++ b/src/mainboard/google/kukui/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_RESET, 1); diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index c6f357bcdf0..522d26a8f74 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #if CONFIG(VGA_ROM_RUN) diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig deleted file mode 100644 index e40531610b5..00000000000 --- a/src/mainboard/google/myst/Kconfig +++ /dev/null @@ -1,97 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -config BOARD_GOOGLE_BASEBOARD_MYST - def_bool n - -config BOARD_GOOGLE_MYST - select BOARD_GOOGLE_BASEBOARD_MYST - -if BOARD_GOOGLE_BASEBOARD_MYST - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AMD_SOC_CONSOLE_UART - select BOARD_ROMSIZE_KB_16384 - select DISABLE_KEYBOARD_RESET_PIN - select DRIVERS_GENERIC_GPIO_KEYS - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_HID - select DRIVERS_WIFI_GENERIC - select DRIVERS_UART_ACPI - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SMBIOS - select EC_GOOGLE_CHROMEEC_BOARDID - select ELOG - select ELOG_GSMI - select FW_CONFIG - select FW_CONFIG_SOURCE_CHROMEEC_CBI - select GOOGLE_SMBIOS_MAINBOARD_VERSION - select I2C_TPM - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_TPM2 - # TODO (b/290763369): Enable APOB after resolving data_abort in ABL - select SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - select SOC_AMD_COMMON_BLOCK_USE_ESPI - select SOC_AMD_PHOENIX_FSP - select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE - select SYSTEM_TYPE_LAPTOP - select TPM_GOOGLE_TI50 - -config DEVICETREE - default "variants/baseboard/devicetree.cb" - -config DRIVER_TPM_I2C_BUS - hex - default 0x02 - -config DRIVER_TPM_I2C_ADDR - hex - default 0x50 - -config GSC_IRQ_GPIO - int - default 84 - -config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" - -config MAINBOARD_DIR - default "google/myst" - -config MAINBOARD_FAMILY - string - default "Google_Myst" - -config MAINBOARD_PART_NUMBER - default "Myst" if BOARD_GOOGLE_MYST - -config OVERRIDE_DEVICETREE - string - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - -config VARIANT_DIR - string - default "myst" if BOARD_GOOGLE_MYST - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_LID_SWITCH - select VBOOT_SEPARATE_VERSTAGE - -config VBOOT_STARTS_BEFORE_BOOTBLOCK - bool "Enable PSP_verstage" - default y if VBOOT - select SEPARATE_SIGNED_PSPFW - -config VBOOT_STARTS_IN_BOOTBLOCK - bool - default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK - -# Override PSP_SOFTFUSE_BITS from soc/amd/phoenix. -# The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA). -config PSP_SOFTFUSE_BITS - string - default "36 34 28 6" - -endif # BOARD_GOOGLE_BASEBOARD_MYST diff --git a/src/mainboard/google/myst/Kconfig.name b/src/mainboard/google/myst/Kconfig.name deleted file mode 100644 index da8bb4b4e75..00000000000 --- a/src/mainboard/google/myst/Kconfig.name +++ /dev/null @@ -1,6 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -comment "Myst (AMD Ryzen Mobile 7000 (Phoenix))" - -config BOARD_GOOGLE_MYST - bool "-> Myst" diff --git a/src/mainboard/google/myst/Makefile.mk b/src/mainboard/google/myst/Makefile.mk deleted file mode 100644 index 305179e117a..00000000000 --- a/src/mainboard/google/myst/Makefile.mk +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += bootblock.c - -romstage-y += port_descriptors.c - -ramstage-y += ec.c -ramstage-y += mainboard.c -ramstage-y += port_descriptors.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c - -verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c - -subdirs-y += variants/baseboard -subdirs-y += variants/$(VARIANT_DIR) - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include - -APCB_NAME=APCB_PHX_D5 - -ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin),) -$(info APCB sources present.) - -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin - -# The SPD is currently built directly into the APCB. -# Add the below section back in after the apcbtool is updated to handle the -# Phoenix APCB SPD configuration. - -ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/Makefile.mk),) - -LIB_SPD_DEPS = $(SPD_SOURCES) - -APCB_SOURCES = $(obj)/$(APCB_NAME).gen - -$(obj)/$(APCB_NAME).gen: $(SPD_SOURCES) \ - $(APCB_V3A_EDIT_TOOL) \ - $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin - $(APCB_V3A_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin \ - $(obj)/$(APCB_NAME).gen \ - --spd_sources $(SPD_SOURCES) -else -$(info SPD sources not found. Skipping APCB.) -show_notices:: die_no_apcb -endif - -else -$(info APCB sources not found. Skipping APCB.) -show_notices:: warn_no_apcb -endif diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c deleted file mode 100644 index 29d0a5a89e5..00000000000 --- a/src/mainboard/google/myst/bootblock.c +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -void mb_set_up_early_espi(void) -{ - size_t num_gpios; - const struct soc_amd_gpio *gpios; - - variant_espi_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); - - espi_switch_to_spi1_pads(); -} - -void bootblock_mainboard_early_init(void) -{ - size_t num_gpios; - const struct soc_amd_gpio *gpios; - - variant_tpm_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); - - variant_early_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); -} - -void bootblock_mainboard_init(void) -{ - size_t num_gpios; - const struct soc_amd_gpio *gpios; - - variant_bootblock_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); - - // TODO: b:285110121 - temp workaround is to add a dummy flash call - const struct spi_flash *spi = boot_device_spi_flash(); - printk(BIOS_DEBUG, "Initialized spi flash %p\n", spi); -} diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c deleted file mode 100644 index 83ff403935a..00000000000 --- a/src/mainboard/google/myst/chromeos.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -void fill_lb_gpios(struct lb_gpios *gpios) {} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(CROS_WP_GPIO, GPIO_DEVICE_NAME), -}; -DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/myst/chromeos.fmd b/src/mainboard/google/myst/chromeos.fmd deleted file mode 100644 index 81fcbe33601..00000000000 --- a/src/mainboard/google/myst/chromeos.fmd +++ /dev/null @@ -1,39 +0,0 @@ -# TODO(b/276944900): Update for 32 MB support, evaluate WP_RO size -FLASH 16M { - SI_BIOS { - WP_RO 4M { - RO_GSCVD 8K - RO_VPD(PRESERVE) 16K - RO_SECTION { - FMAP 2K - RO_FRID 64 - COREBOOT(CBFS) - GBB 12K - } - } - RW_SECTION_A 5M { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - SIGNED_AMDFW_A 2304K - RW_FWID_A 256 - } - RW_SECTION_B 5M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - SIGNED_AMDFW_B 2304K - RW_FWID_B 256 - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 256K - RW_LEGACY(CBFS) - RW_VBIOS_CACHE 64K - RW_MRC_CACHE 256K - RECOVERY_MRC_CACHE(PRESERVE) 256K - } -} diff --git a/src/mainboard/google/myst/dsdt.asl b/src/mainboard/google/myst/dsdt.asl deleted file mode 100644 index 9c7dc36b96f..00000000000 --- a/src/mainboard/google/myst/dsdt.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ - #include - #include - - Name (LIDS, 0) - - /* Chrome OS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include - /* ACPI code for EC functions */ - #include - } - -} diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c deleted file mode 100644 index 323f0392098..00000000000 --- a/src/mainboard/google/myst/port_descriptors.c +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -static const fsp_ddi_descriptor myst_ddi_descriptors[] = { - { /* DDI0 - eDP */ - .connector_type = DDI_EDP, - .aux_index = DDI_AUX1, - .hdp_index = DDI_HDP1 - }, - { /* DDI1 - HDMI/DP */ - .connector_type = DDI_HDMI, - .aux_index = DDI_AUX2, - .hdp_index = DDI_HDP2 - }, - { /* DDI2 - DP (type C) */ - .connector_type = DDI_DP_W_TYPEC, - .aux_index = DDI_AUX3, - .hdp_index = DDI_HDP3, - }, - { /* DDI3 - DP (type C) */ - .connector_type = DDI_DP_W_TYPEC, - .aux_index = DDI_AUX4, - .hdp_index = DDI_HDP4, - }, - { /* DDI4 - Unused */ - .connector_type = DDI_UNUSED_TYPE, - .aux_index = DDI_AUX5, - .hdp_index = DDI_HDP5, - }, -}; - -void mainboard_get_dxio_ddi_descriptors( - const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, - const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) -{ - variant_get_dxio_descriptors(dxio_descs, dxio_num); - *ddi_descs = myst_ddi_descriptors; - *ddi_num = ARRAY_SIZE(myst_ddi_descriptors); -} diff --git a/src/mainboard/google/myst/romstage.c b/src/mainboard/google/myst/romstage.c deleted file mode 100644 index fc3402a3b63..00000000000 --- a/src/mainboard/google/myst/romstage.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void mb_pre_fspm(FSP_M_CONFIG *mcfg) -{ - size_t num_base_gpios; - const struct soc_amd_gpio *base_gpios; - - baseboard_romstage_gpio_table(&base_gpios, &num_base_gpios); - gpio_configure_pads(base_gpios, num_base_gpios); -} diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb deleted file mode 100644 index 55a14c077be..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ /dev/null @@ -1,377 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -chip soc/amd/phoenix - - # eSPI Configuration - # TODO(b/276913952) bump clock back up to 33MHz once things seem to be working well. - register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, - .generic_io_range[0] = { - .base = 0x62, - .size = 1, - }, - .generic_io_range[1] = { - .base = 0x66, - .size = 1, - }, - .generic_io_range[2] = { - .base = 0x800, /* EC_HOST_CMD_REGION0 */ - .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ - }, - .generic_io_range[3] = { - .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ - .size = 255, /* EC_MEMMAP_SIZE */ - }, - .generic_io_range[4] = { - .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ - .size = 8, /* 0x200 - 0x207 */ - }, - - .io_mode = ESPI_IO_MODE_QUAD, - .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, - .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, - .periph_ch_en = 1, - .vw_ch_en = 1, - .oob_ch_en = 0, - .flash_ch_en = 0, - - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), - }" - - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | - GPIO_I2C2_SCL | GPIO_I2C3_SCL" - - # I2C Pad Control RX Select Configuration - register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad - register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen - register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC - register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB - - # I2C Config - #+-------------------+----------------------------+ - #| Field | Value | - #+-------------------+----------------------------+ - #| I2C0 | Trackpad | - #| I2C1 | Touchscreen | - #| I2C2 | GSC TPM | - #| I2C3 | Speaker, Codec, P-SAR, USB | - #+-------------------+----------------------------+ - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - }" - - register "i2c[1]" = "{ - .speed = I2C_SPEED_FAST, - }" - - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .early_init = true, - }" - - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - }" - - # general purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN - register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD - register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WWAN - register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD - register "gpp_clk_config[4]" = "GPP_CLK_OFF" # SOC_FP_BOOT0 GPIO - register "gpp_clk_config[5]" = "GPP_CLK_OFF" # WLAN_AUX_RST_L GPIO - register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO - - register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works - register "s0ix_enable" = "true" - - register "usb_phy_custom" = "true" - register "usb_phy" = "{ - .Usb2PhyPort[0] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[1] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[2] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[3] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[4] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[5] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[6] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb2PhyPort[7] = { - .compdistune = 0x3, - .pllbtune = 0x1, - .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, - .txpreemppulsetune = 0x0, - .txrisetune = 0x1, - .txvreftune = 0x3, - .txhsxvtune = 0x3, - .txrestune = 0x2, - }, - .Usb3PhyPort[0] = { - .tx_term_ctrl = 0x2, - .rx_term_ctrl = 0x2, - .tx_vboost_lvl_en = 0x0, - .tx_vboost_lvl = 0x5, - }, - .Usb3PhyPort[1] = { - .tx_term_ctrl = 0x2, - .rx_term_ctrl = 0x2, - .tx_vboost_lvl_en = 0x0, - .tx_vboost_lvl = 0x5, - }, - .Usb3PhyPort[2] = { - .tx_term_ctrl = 0x2, - .rx_term_ctrl = 0x2, - .tx_vboost_lvl_en = 0x0, - .tx_vboost_lvl = 0x5, - }, - .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, - .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, - .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, - .BatteryChargerEnable = 0, - .PhyP3CpmP4Support = 0, - }" - - device domain 0 on - device ref gpp_bridge_2_1 on end # WWAN - device ref gpp_bridge_2_2 on # WLAN - chip drivers/wifi/generic - register "wake" = "GEVENT_8" - device pci 00.0 on end - end - end - device ref gpp_bridge_2_3 on end # SD - device ref gpp_bridge_2_4 on end # NVMe - device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - device ref gfx on end # Internal GPU (GFX) - device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) - device ref crypto on end # Crypto Coprocessor - device ref xhci_0 on # USB 3.1 (USB0) - chip drivers/usb/acpi - device ref xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb3_port2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A1 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref usb3_port3 on - probe DAUGHTERBOARD DB_B - end - end - chip drivers/usb/acpi - register "desc" = ""USB3 WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_6)" - register "enable_delay_ms" = "20" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_11)" - register "reset_off_delay_ms" = "20" - device ref usb3_port3 on - probe WWAN WWAN_FM101GL - end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A1 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - device ref usb2_port3 on end - end - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port4 on end - end - chip drivers/usb/acpi - register "desc" = ""World-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port5 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)" - register "enable_delay_ms" = "500" - register "enable_off_delay_ms" = "200" - register "use_gpio_for_status" = "true" - device ref usb2_port6 on end - end - end - end - end - device ref acp on end # Audio Processor (ACP) - device ref mp2 on end # Sensor Fusion Hub (MP2) - end - device ref gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B - device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - device ref usb4_xhci_0 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device ref usb4_xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb3_port0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb2_port0 on end - end - end - end - end - device ref usb4_xhci_1 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device ref usb4_xhci_1_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" - device ref usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" - device ref usb2_port1 on end - end - end - end - end - end - device ref iommu on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 alias chrome_ec on end - end - end - end # domain - device ref uart_0 on end # UART0 - device ref i2c_0 on end - device ref i2c_1 on end - device ref i2c_2 hidden - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Ti50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_84)" - device i2c 50 alias ti50 on end - end - end - device ref i2c_3 on end -end # chip soc/amd/phoenix diff --git a/src/mainboard/google/myst/variants/baseboard/fw_config.c b/src/mainboard/google/myst/variants/baseboard/fw_config.c deleted file mode 100644 index 9d5c9236d8f..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/fw_config.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -static const struct soc_amd_gpio fp_spi_gpio_table[] = { - /* SOC_CLK_FPMCU_R */ - PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), - /* SOC_CLK_FPMCU_R_L */ - PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), - /* SPI_SOC_DO_FPMCU_DI_R */ - PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), - /* SPI_SOC_DI_FPMCU_DO_R */ - PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), -}; - -static const struct soc_amd_gpio fp_uart_gpio_table[] = { - /* UART1_TXD / FPMCU */ - PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), - /* UART1_RXD / FPMCU */ - PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), -}; - -static void fw_config_handle(void *unused) -{ - if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(FP, DISABLED))) { - return; - } - if (fw_config_probe(FW_CONFIG(FP, SPI))) { - printk(BIOS_INFO, "Enabling SPI FP.\n"); - gpio_configure_pads(fp_spi_gpio_table, ARRAY_SIZE(fp_spi_gpio_table)); - } else if (fw_config_probe(FW_CONFIG(FP, UART))) { - printk(BIOS_INFO, "Enabling UART FP.\n"); - gpio_configure_pads(fp_uart_gpio_table, ARRAY_SIZE(fp_uart_gpio_table)); - } else { - printk(BIOS_INFO, "Invalid Fingerprint Setting, leaving FP disabled."); - } -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c deleted file mode 100644 index d6cbe1e194a..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -/* GPIO configuration in ramstage*/ -static const struct soc_amd_gpio base_gpio_table[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* Unused */ - PAD_NC(GPIO_3), - /* EN_PWR_FP */ - PAD_GPO(GPIO_4, LOW), - /* EN_PP3300_TCHPAD */ - PAD_GPO(GPIO_5, HIGH), - /* EN_PP3300_WWAN_X */ - PAD_GPO(GPIO_6, LOW), - /* SOC_PEN_DETECT_ODL */ - PAD_WAKE(GPIO_7, PULL_NONE, EDGE_LOW, S0i3), - /* SOC_TCHPAD_INT_ODL */ - PAD_SCI(GPIO_8, PULL_NONE, LEVEL_LOW), - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), - /* WWAN_RST */ - PAD_GPO(GPIO_11, HIGH), - /* Unused */ - PAD_NC(GPIO_12), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* EC_SOC_WAKE_R_ODL */ - PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), - /* FP_SOC_INT_L */ - PAD_SCI(GPIO_18, PULL_NONE, LEVEL_LOW), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* Unused */ - PAD_NC(GPIO_21), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_NONE), - /* Unused */ - PAD_NC(GPIO_24), - /* GPIO_25-26: Not available */ - /* SOC_PCIE_RST1_R_L */ - PAD_NC(GPIO_27), - /* GPIO_28: Not available */ - /* SD_AUX_RST */ - PAD_GPO(GPIO_29, LOW), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* SSD_AUX_RST */ - PAD_GPO(GPIO_31, LOW), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_37: Not available */ - /* WLAN_AUX_RST_L */ - PAD_GPO(GPIO_38, HIGH), - /* WWAN_AUX_RST_L */ - PAD_GPO(GPIO_39, HIGH), - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_40, LOW), - /* GPIO_41 - GPIO_66: Not available */ - /* GPIO_67 (Unused) */ - PAD_NC(GPIO_67), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SOC_CLK_FPMCU_R if SPI FP populated */ - PAD_NC(GPIO_70), - /* EN_TCHSCR_REPORT */ - PAD_GPO(GPIO_74, LOW), - /* SOC_CLK_FPMCU_R_L if SPI FP populated */ - PAD_NC(GPIO_75), - /* Unused */ - PAD_NC(GPIO_76), - /* ESPI_SOC_CLK_EC_R */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* RAM_ID_0 */ - PAD_GPI(GPIO_78, PULL_NONE), - /* RAM_ID_1 */ - PAD_GPI(GPIO_79, PULL_NONE), - /* ESPI_SOC_D1_EC_R */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI_SOC_D0_EC_R */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ - PAD_NC(GPIO_85), - /* HP_INT_ODL */ - PAD_GPI(GPIO_89, PULL_NONE), - /* EC_SOC_INT_ODL */ - PAD_GPI(GPIO_90, PULL_NONE), - /* TCHSCR_INT_ODL */ - PAD_GPI(GPIO_91, PULL_NONE), - /* CLK_REQ0_L / WLAN */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* SPI_SOC_DO_FPMCU_DI_R if SPI FP populated */ - PAD_NC(GPIO_104), - /* SPI_SOC_DI_FPMCU_DO_R if SPI FP populated */ - PAD_NC(GPIO_105), - /* RAM_ID_2 */ - PAD_GPI(GPIO_106, PULL_NONE), - /* RAM_ID_3 */ - PAD_GPI(GPIO_107, PULL_NONE), - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L / SD */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L / WWAN */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* Unused */ - PAD_NC(GPIO_130), - /* CLK_REQ3_L / SSD */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* SOC_FP_BOOT0 */ - PAD_GPO(GPIO_132, LOW), - /* EN_PP3300_CAM */ - PAD_GPO(GPIO_135, HIGH), - /* Unused */ - PAD_NC(GPIO_136), - /* Unused */ - PAD_NC(GPIO_137), - /* Unused */ - PAD_NC(GPIO_138), - /* SOC_BIOS_WP_OD */ - PAD_GPI(GPIO_139, PULL_NONE), - /* UART1_TXD if UART FP populated */ - PAD_NC(GPIO_140), - /* UART0_RXD / DBG */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART1_RXD if UART FP populated */ - PAD_NC(GPIO_142), - /* UART0_TXD / DBG */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_144, HIGH), - /* I2C0_SCL */ - PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), - /* I2C0_SDA */ - PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), - /* I2C1_SCL */ - PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), - /* I2C1_SDA */ - PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_153, LOW), - /* BT_DISABLE */ - PAD_GPO(GPIO_154, LOW), - /* HDMI_RST */ - PAD_GPO(GPIO_155, HIGH), - /* WLAN_DISABLE */ - PAD_GPO(GPIO_156, LOW), - /* TCHSCR_RST_L */ - PAD_GPO(GPIO_157, HIGH), -}; - -static const struct soc_amd_gpio tpm_gpio_table[] = { - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), -}; - -/* GPIO configuration in bootblock */ -static const struct soc_amd_gpio bootblock_gpio_table[] = { - /* Enable WLAN */ - /* WLAN_DISABLE */ - PAD_GPO(GPIO_156, LOW), -}; - -/* Early GPIO configuration */ -static const struct soc_amd_gpio early_gpio_table[] = { - /* WLAN_AUX_RST_L (ACTIVE LOW) */ - PAD_GPO(GPIO_38, LOW), - /* Power on WLAN */ - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), -}; - -/* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio romstage_gpio_table[] = { - /* Deassert all AUX_RESET lines & PCIE_RST */ - /* SD_AUX_RST */ - PAD_GPO(GPIO_29, LOW), - /* SSD_AUX_RESET */ - PAD_GPO(GPIO_31, LOW), - /* WLAN_AUX_RST_L (ACTIVE LOW) */ - PAD_GPO(GPIO_38, HIGH), - /* WWAN_AUX_RST_L (ACTIVE LOW) */ - PAD_GPO(GPIO_39, HIGH), - /* CLK_REQ0_L / WLAN */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* CLK_REQ1_L / SD */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L / WWAN */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* CLK_REQ3_L / SSD */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* PCIE_RST0_L */ - PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), -}; - -static const struct soc_amd_gpio espi_gpio_table[] = { - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* ESPI1_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* ESPI1_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), -}; - -void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(base_gpio_table); - *gpio = base_gpio_table; -} - -__weak void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(romstage_gpio_table); - *gpio = romstage_gpio_table; -} - -__weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(bootblock_gpio_table); - *gpio = bootblock_gpio_table; -} - -__weak void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(early_gpio_table); - *gpio = early_gpio_table; -} - -void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(espi_gpio_table); - *gpio = espi_gpio_table; -} - -__weak void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = ARRAY_SIZE(tpm_gpio_table); - *gpio = tpm_gpio_table; -} - -__weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -{ - *size = 0; - *gpio = NULL; -} diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index 355f4dc5e77..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include -#include -#include -#include - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BODY_DETECT_CHANGE)) - -#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid, power button or mode change event */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Set GPI for SCI */ -#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */ - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GEVENT_13 /* AGPIO 17 -> GPE 13 */ - -/* Enable MKBP for buttons and switches */ -#define EC_ENABLE_MKBP_DEVICE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Level, ActiveLow, Shared) {1} - -/* Enable EC sync interrupt */ -#define EC_ENABLE_SYNC_IRQ_GPIO - -/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_90 - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h deleted file mode 100644 index bc92b699caa..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__ -#define __BASEBOARD_PORT_DESCRIPTORS_H__ - -#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN -#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN -#define SD_DEVFN PCIE_GPP_2_3_DEVFN -#define NVME_DEVFN PCIE_GPP_2_4_DEVFN - -#define WWAN_DXIO_DESCRIPTOR { \ - .engine_type = UNUSED_ENGINE, \ - .port_present = true, \ - .start_lane = 13, \ - .end_lane = 13, \ - .device_number = PCI_SLOT(WWAN_DEVFN), \ - .function_number = PCI_FUNC(WWAN_DEVFN), \ - .link_speed_capability = GEN3, \ - .turn_off_unused_lanes = true, \ - .clk_req = CLK_REQ2, \ -} - -#define WLAN_DXIO_DESCRIPTOR { \ - .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_lane = 14, \ - .end_lane = 14, \ - .device_number = PCI_SLOT(WLAN_DEVFN), \ - .function_number = PCI_FUNC(WLAN_DEVFN), \ - .link_speed_capability = GEN3, \ - .turn_off_unused_lanes = true, \ - .clk_req = CLK_REQ0, \ -} - -#define SD_DXIO_DESCRIPTOR { \ - .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_lane = 15, \ - .end_lane = 15, \ - .device_number = PCI_SLOT(SD_DEVFN), \ - .function_number = PCI_FUNC(SD_DEVFN), \ - .link_speed_capability = GEN1, \ - .turn_off_unused_lanes = true, \ - .link_hotplug = HOTPLUG_ENHANCED, \ - .clk_req = CLK_REQ1, \ -} - -#define NVME_DXIO_DESCRIPTOR { \ - .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_lane = 16, \ - .end_lane = 19, \ - .device_number = PCI_SLOT(NVME_DEVFN), \ - .function_number = PCI_FUNC(NVME_DEVFN), \ - .link_speed_capability = GEN_MAX, \ - .turn_off_unused_lanes = true, \ - .clk_req = CLK_REQ3, \ -} - -#define EMMC_DXIO_DESCRIPTOR { \ - .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_lane = 16, \ - .end_lane = 16, \ - .device_number = PCI_SLOT(NVME_DEVFN), \ - .function_number = PCI_FUNC(NVME_DEVFN), \ - .link_speed_capability = GEN_MAX, \ - .turn_off_unused_lanes = true, \ - .clk_req = CLK_REQ3, \ -} - -#endif //__BASEBOARD_PORT_DESCRIPTORS_H__ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 540a0c86aae..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include -#include -#include - -/* This function provides base GPIO configuration table. */ -void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* This function provides GPIO settings in romstage. */ -void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* This function provides GPIO init in bootblock. */ -void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* This function provides early GPIO init in early bootblock or psp. */ -void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* This function provides GPIO settings for eSPI bus. */ -void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* - * This function allows variant to override any GPIOs that are different than the base GPIO - * configuration provided by baseboard_gpio_table(). - */ -void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* This function provides GPIO settings for TPM i2c bus. */ -void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); - -/* - * This function allows a variant to override dxio descriptors passed to the FSP. - */ -void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num); - -#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/port_descriptors.c b/src/mainboard/google/myst/variants/baseboard/port_descriptors.c deleted file mode 100644 index b26f3001162..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/port_descriptors.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -enum baseboard_dxio_port_id { - BASEBOARD_DXIO_WWAN, - BASEBOARD_DXIO_WLAN, - BASEBOARD_DXIO_SD, - BASEBOARD_DXIO_STORAGE, -}; - -static fsp_dxio_descriptor myst_dxio_descriptors[] = { - [BASEBOARD_DXIO_WWAN] = WWAN_DXIO_DESCRIPTOR, - [BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, - [BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR, - /* This value modified at runtime, default to emmc */ - [BASEBOARD_DXIO_STORAGE] = EMMC_DXIO_DESCRIPTOR, -}; - -__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) -{ - if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) { - printk(BIOS_DEBUG, "Enabling NVMe.\n"); - myst_dxio_descriptors[BASEBOARD_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR; - } else { - printk(BIOS_DEBUG, "Defaulting to eMMC.\n"); - } - *dxio_descriptor = myst_dxio_descriptors; - *num = ARRAY_SIZE(myst_dxio_descriptors); -} diff --git a/src/mainboard/google/myst/variants/baseboard/smihandler.c b/src/mainboard/google/myst/variants/baseboard/smihandler.c deleted file mode 100644 index 7d439d5c31a..00000000000 --- a/src/mainboard/google/myst/variants/baseboard/smihandler.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include - -void mainboard_smi_sleep(u8 slp_typ) -{ - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S0IX_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); -} - -int mainboard_smi_apmc(u8 apmc) -{ - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); - - return 0; -} diff --git a/src/mainboard/google/myst/variants/myst/Makefile.mk b/src/mainboard/google/myst/variants/myst/Makefile.mk deleted file mode 100644 index 88e75bde52c..00000000000 --- a/src/mainboard/google/myst/variants/myst/Makefile.mk +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -subdirs-y += ./memory diff --git a/src/mainboard/google/myst/variants/myst/include/variant/ec.h b/src/mainboard/google/myst/variants/myst/include/variant/ec.h deleted file mode 100644 index 9e61a440cff..00000000000 --- a/src/mainboard/google/myst/variants/myst/include/variant/ec.h +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/google/myst/variants/myst/memory/Makefile.mk b/src/mainboard/google/myst/variants/myst/memory/Makefile.mk deleted file mode 100644 index 80510d7c0cc..00000000000 --- a/src/mainboard/google/myst/variants/myst/memory/Makefile.mk +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen PHX lp5 src/mainboard/google/myst/variants/myst/memory src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 0(0b0000) Parts = H9JCNNNCP3MLYR-N6E -SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 2(0b0010) Parts = MT62F1G32D2DS-026 WT:B -SPD_SOURCES += spd/lp5/set-1/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt b/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt deleted file mode 100644 index 91c2c580ce8..00000000000 --- a/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen PHX lp5 src/mainboard/google/myst/variants/myst/memory src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -H9JCNNNCP3MLYR-N6E 0 (0000) -MT62F512M32D2DR-031 WT:B 1 (0001) -MT62F1G32D2DS-026 WT:B 2 (0010) -K3KL6L60GM-MGCT 3 (0011) diff --git a/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt b/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt deleted file mode 100644 index c9cb4019fa6..00000000000 --- a/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt +++ /dev/null @@ -1,4 +0,0 @@ -H9JCNNNCP3MLYR-N6E, -MT62F512M32D2DR-031 WT:B, -MT62F1G32D2DS-026 WT:B, -K3KL6L60GM-MGCT, diff --git a/src/mainboard/google/myst/variants/myst/overridetree.cb b/src/mainboard/google/myst/variants/myst/overridetree.cb deleted file mode 100644 index 9dc8f018d81..00000000000 --- a/src/mainboard/google/myst/variants/myst/overridetree.cb +++ /dev/null @@ -1,126 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -fw_config - field FORM_FACTOR 0 - option FORM_FACTOR_CLAMSHELL 0 - option FORM_FACTOR_CONVERTIBLE 1 - end - field FP 1 2 - option DISABLED 0 - option UART 1 - option SPI 2 - end - field WLAN 3 4 - option WLAN_MT7922 0 - option WLAN_MT7925 1 - end - field WWAN 5 6 - option WWAN_DIASABLED 0 - option WWAN_FM101GL 1 - end - field DAUGHTERBOARD 7 9 - option DISABLED 0 - option DB_A 1 - option DB_B 2 - end - field KB_BL 10 - option DISABLED 0 - option ENABLED 1 - end - field STORAGE 11 - option EMMC 0 - option NVME 1 - end -end - -chip soc/amd/phoenix - device domain 0 on end # domain - device ref i2c_0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_8)" - register "wake" = "GEVENT_23" - register "detect" = "1" - device i2c 15 on end - end - end # I2C0 - device ref i2c_1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_91)" - register "generic.detect" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_157)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_74)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end - end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_7)" - register "key.dev_name" = ""EJCT"" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - register "key.debounce_interval" = "100" - register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" - device generic 0 on end - end - end # I2C1 - device ref i2c_3 on - chip drivers/i2c/generic - register "hid" = ""RTL5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_89)" - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - register "detect" = "1" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""10EC1019"" - register "desc" = ""Realtek SPK AMP R"" - register "uid" = "1" - register "detect" = "1" - device i2c 29 on end - end - chip drivers/i2c/generic - register "hid" = ""10EC1019"" - register "desc" = ""Realtek SPK AMP L"" - register "uid" = "2" - register "detect" = "1" - device i2c 2a on end - end - end # I2C3 - device ref uart_1 on - chip drivers/uart/acpi - register "name" = ""CRFP"" - register "desc" = ""Fingerprint Reader"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_18)" - register "wake" = "GEVENT_14" - register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" - register "has_power_resource" = "true" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_40)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" - register "enable_delay_ms" = "3" - device generic 0 alias fpmcu on - probe FP UART - end - end - end -end # chip soc/amd/phoenix diff --git a/src/mainboard/google/myst/verstage.c b/src/mainboard/google/myst/verstage.c deleted file mode 100644 index 23201062143..00000000000 --- a/src/mainboard/google/myst/verstage.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void verstage_mainboard_early_init(void) -{ - const struct soc_amd_gpio *gpios; - size_t num_gpios; - - variant_early_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); -} - -void verstage_mainboard_espi_init(void) -{ - const struct soc_amd_gpio *gpios; - size_t num_gpios; - - variant_espi_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); - - espi_switch_to_spi1_pads(); -} - -void verstage_mainboard_tpm_init(void) -{ - const struct soc_amd_gpio *gpios; - size_t num_gpios; - - variant_tpm_gpio_table(&gpios, &num_gpios); - gpio_configure_pads(gpios, num_gpios); -} diff --git a/src/mainboard/google/oak/Makefile.mk b/src/mainboard/google/oak/Makefile.mk index 79a80ee6c14..0a844935ddb 100644 --- a/src/mainboard/google/oak/Makefile.mk +++ b/src/mainboard/google/oak/Makefile.mk @@ -17,3 +17,5 @@ ramstage-y += mainboard.c ramstage-y += chromeos.c ramstage-y += boardid.c ramstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index 55b6064620a..399bf29905b 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include -#include "gpio.h" +#include static int board_id_value = -1; diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 365b80311e2..c23a683031a 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -1,16 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include +#include #include #include #include #include -#include "gpio.h" - static void i2c_set_gpio_pinmux(void) { gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1); diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 739df2e25bc..73210e63352 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -1,15 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include +#include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { - gpio_input(WRITE_PROTECT); + gpio_input(GPIO_WP); gpio_input_pullup(EC_IN_RW); gpio_input_pullup(EC_IRQ); gpio_input(LID); @@ -32,7 +31,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - return !gpio_get(WRITE_PROTECT); + return !gpio_get(GPIO_WP); } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/include/baseboard/gpio.h similarity index 96% rename from src/mainboard/google/oak/gpio.h rename to src/mainboard/google/oak/include/baseboard/gpio.h index a5b47d5f081..bc1dadea3b1 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/include/baseboard/gpio.h @@ -17,7 +17,7 @@ #define RAM_ID_0 GPIO(RDP2_A) #define RAM_ID_3 GPIO(RDN1_A) /* Write Protect */ -#define WRITE_PROTECT GPIO(EINT4) +#define GPIO_WP GPIO(EINT4) /* Power button */ #define POWER_BUTTON GPIO(EINT14) /* EC Interrupt */ diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 9c8481f6217..4503a899ab2 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -217,7 +217,7 @@ static void display_startup(void) edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL, NULL); if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 75c951b41fc..69fdc8c7c33 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - int cr50_plat_irq_status(void) { return gpio_eint_poll(CR50_IRQ); diff --git a/src/mainboard/google/ocelot/romstage.c b/src/mainboard/google/ocelot/romstage.c index 8f0000c2ce8..9f833e3c82d 100644 --- a/src/mainboard/google/ocelot/romstage.c +++ b/src/mainboard/google/ocelot/romstage.c @@ -22,6 +22,11 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) /* Nothing to do */ } +void __weak variant_post_gpio_configure(void) +{ + /* default implementation does nothing */ +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; @@ -42,4 +47,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* Override FSP-M UPD per board if required. */ variant_update_soc_memory_init_params(memupd); + + variant_post_gpio_configure(); } diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h index 23ac848457a..dc7518029d9 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h @@ -29,6 +29,7 @@ bool variant_is_half_populated(void); void variant_update_soc_memory_init_params(FSPM_UPD *memupd); void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config); bool variant_is_barrel_charger_present(void); +void variant_post_gpio_configure(void); enum s0ix_entry { S0IX_EXIT, diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index 016f531e38d..c5112590f4a 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -67,17 +67,26 @@ chip soc/intel/pantherlake # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true" + # PCH PM SLP miminum assertion width and Reset Power Cycle Duration + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + # Reference: 844458 MOW WW03, 8300097 # fast_vmode_i_trip values are derived from ICCMax with a safety margin. register "enable_fast_vmode[VR_DOMAIN_IA]" = "true" register "cep_enable[VR_DOMAIN_IA]" = "true" register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" - register "cep_enable[VR_DOMAIN_GT]" = "true" register "fast_vmode_i_trip[WCL_SKU_1]" = "{ [VR_DOMAIN_IA] = 38 * 4, [VR_DOMAIN_GT] = 25 * 4, }" + # Set on-board graphics as primary display + register "skip_ext_gfx_scan" = "true" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb index 8da38fe1d89..3dc6224e1b0 100644 --- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb @@ -327,6 +327,7 @@ chip soc/intel/pantherlake device ref ufs on probe STORAGE_TYPE STORAGE_TYPE_UFS probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN + register "ufs_inline_encryption" = "true" end #ToDo: Probe using fw_config after decision. device ref pcie_rp1 on diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c index 9984ef5e890..c69baadfd7c 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c +++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -124,9 +125,29 @@ static const struct pad_config audio_disable_pads[] = { PAD_NC(GPP_S07, NONE), }; -static const struct pad_config x4slot_pads[] = { - /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ +static const struct pad_config power_x4slot_pads[] = { + /* x4 slot power sequence: 2. power = enable; */ + /* GPP_F10: X4_PCIE_SLOT_PWR_EN */ PAD_CFG_GPO(GPP_F10, 1, PLTRST), +}; + +static const struct pad_config clock_request_x4slot_pads[] = { + /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +}; + +static const struct pad_config alt_clock_request_x4slot_pads[] = { + /* GPP_C14: Used to simulate clock request from card */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), +}; + +static const struct pad_config disable_alt_clock_request_x4slot_pads[] = { + /* GPP_C14: Used to simulate clock request from card */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), +}; + +static const struct pad_config reset_deassert_x4slot_pads[] = { + /* x4 slot power sequence: 3. PERST# = de-assert */ /* GPP_E03: X4_DT_PCIE_RST_N */ PAD_CFG_GPO(GPP_E03, 1, PLTRST), /* GPP_D03: X4_SLOT_WAKE_N */ @@ -134,12 +155,14 @@ static const struct pad_config x4slot_pads[] = { }; static const struct pad_config x4slot_disable_pads[] = { - /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ - PAD_CFG_GPO(GPP_F10, 0, PLTRST), - /* GPP_E03: X4_DT_PCIE_RST_N */ - PAD_NC(GPP_E03, NONE), + /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ + PAD_NC(GPP_C11, NONE), /* GPP_D03: X4_SLOT_WAKE_N */ PAD_NC(GPP_D03, NONE), + /* GPP_E03: X4_DT_PCIE_RST_N */ + PAD_NC(GPP_E03, NONE), + /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ + PAD_CFG_GPO(GPP_F10, 0, PLTRST), }; /* @@ -190,13 +213,7 @@ static const struct pad_config wwan_disable_pads[] = { PAD_NC(GPP_E02, NONE), }; -/* Gen4 NVME: at the top M.2 slot */ -static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = { - /* GPP_H18: GEN4_SSD_PWREN */ - PAD_CFG_GPO(GPP_H18, 0, PLTRST), -}; - -static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = { +static const struct pad_config pre_mem_gen4_ssd_pwr_seq_pads[] = { /* GPP_H18: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_H18, 1, PLTRST), }; @@ -495,10 +512,14 @@ void fw_config_configure_pre_mem_gpio(void) if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); - if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads); - } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads); + if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) { + GPIO_CONFIGURE_PADS(power_x4slot_pads); + /* + * Ocelot RVP hardware brings up power earlier, so no need + * to delay 10mS before requesting clock. + */ + GPIO_CONFIGURE_PADS(alt_clock_request_x4slot_pads); + GPIO_CONFIGURE_PADS(clock_request_x4slot_pads); } /* @@ -518,12 +539,20 @@ void fw_config_configure_pre_mem_gpio(void) GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads); if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq_pads); } +} - +void variant_post_gpio_configure(void) +{ + // Deassert SD Card reset if needed + if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) { + GPIO_CONFIGURE_PADS(reset_deassert_x4slot_pads); + udelay(20); + GPIO_CONFIGURE_PADS(disable_alt_clock_request_x4slot_pads); + } } void fw_config_gpio_padbased_override(struct pad_config *padbased_table) @@ -574,8 +603,6 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) if (fw_config_probe(FW_CONFIG(SD, SD_NONE))) GPIO_PADBASED_OVERRIDE(padbased_table, x4slot_disable_pads); - else - GPIO_PADBASED_OVERRIDE(padbased_table, x4slot_pads); if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads); diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c index 658896c0f0a..6ab045e17d0 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c +++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c @@ -67,8 +67,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13: PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14: GPP_B14_DDSP_HPDB */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), /* GPP_B16: COINLESS_MODE_SELECT */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* GPP_B17: SPI_TPM_INT_N */ @@ -105,8 +103,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), /* GPP_C10: WIFI_RF_KILL_N */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ - PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */ @@ -123,10 +119,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* GPP_C22: DDPB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), - /* GPP_C23: DDPB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_D */ /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ @@ -230,8 +222,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_F08, 1, PLTRST), /* GPP_F09: M2_UFS_RST_N */ PAD_CFG_GPO(GPP_F09, 1, DEEP), - /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11), /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ @@ -340,8 +330,35 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_B14: GPP_B14_DDSP_HPDB */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* + * NOTE: The x4 slot power (X4_PCIE_SLOT_PWR_EN from GPP_F10) is pull-high by + * default. Since GPP_F10 PAD defaults to GPI configuration, slot power is + * enabled during early boot. PERST# (GPP_E03) is logically ANDed with PLTRST#, + * ensuring that PLTRST# de-assertion occurs after x4 slot power stabilization. + * This maintains proper x4 slot timing sequences automatically. + * + * If slot power must be disabled at boot, PERST# de-assertion must occur after + * power restoration and satisfy PCIe link training timing requirements. + * The recommended power sequence is: + * + * Step 1 (early stage): clkreq off; PERST# asserted; power off + * Step 2 (pre-memory stage): power on + * Step 3 (RAM stage): PERST# de-asserted; clkreq on (if used) + */ + + /* x4 slot power sequence: 1. no clkreq; PERST=0; power=0 */ + /* Assert reset now to keep chip in reset while we transition required GPIOs */ + /* GPP_E03: X4_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_E03, 0, PLTRST), + /* GPP_B17: SPI_TPM_INT_N */ PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), + /* GPP_C22: DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_H06: I2C3_SDA_PSS */ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* GPP_H07: I2C3_SCL_PSS */ @@ -354,6 +371,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* GPP_H22: I2C1_SCL_TTK_CHROME */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_H18: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_H18, 0, PLTRST), }; /* Pad configuration in romstage */ diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 5a36e4bf0bc..d4185a79f99 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -465,6 +465,7 @@ chip soc/intel/pantherlake device ref ufs on probe STORAGE STORAGE_UFS probe STORAGE STORAGE_UNKNOWN + register "ufs_inline_encryption" = "true" end device ref pcie_rp1 on @@ -492,6 +493,16 @@ chip soc/intel/pantherlake .clk_req = 0, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end end # M.2 WLAN KEY-E device ref pcie_rp6 on diff --git a/src/mainboard/google/ocelot/variants/ocicat/fw_config.c b/src/mainboard/google/ocelot/variants/ocicat/fw_config.c index 8c207ed5e20..7dc48c5b0a2 100644 --- a/src/mainboard/google/ocelot/variants/ocicat/fw_config.c +++ b/src/mainboard/google/ocelot/variants/ocicat/fw_config.c @@ -11,6 +11,97 @@ /* t: table */ #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) +static const struct pad_config pcie_wlan_enable_pads[] = { + /* GPP_A11: WLAN_RST_N */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_E07: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL), +}; + +static const struct pad_config pcie_wlan_disable_pads[] = { + /* GPP_A11: WLAN_RST_N */ + PAD_NC(GPP_A11, NONE), + /* GPP_E07: WIFI_WAKE_N */ + PAD_NC(GPP_E07, NONE), +}; + +static const struct pad_config cnvi_enable_pads[] = { + /* GPP_B09: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_B09, 1, DEEP), + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), +}; + +static const struct pad_config cnvi_disable_pads[] = { + /* GPP_B09: BT_RF_KILL_N */ + PAD_NC(GPP_B09, NONE), + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_NC(GPP_C10, NONE), + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_NC(GPP_F00, NONE), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_NC(GPP_F01, NONE), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_NC(GPP_F02, NONE), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_NC(GPP_F03, NONE), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_NC(GPP_F04, NONE), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_NC(GPP_F05, NONE), +}; + +static const struct pad_config ish_disable_pads[] = { + /* GPP_B05: C_EC_ISH_ALRT */ + PAD_NC(GPP_B05, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_NC(GPP_B19, NONE), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_NC(GPP_B23, NONE), + /* GPP_D06: ISH_UART0_ECAIC_TXD */ + PAD_NC(GPP_D06, NONE), + /* GPP_F23: SMC_LID / ISH_GP9A*/ + PAD_NC(GPP_F23, NONE), +}; + +static const struct pad_config ish_enable_pads[] = { + /* GPP_B05: C_EC_ISH_ALRT */ + PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), + /* GPP_D06: ISH_UART0_ECAIC_TXD */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), + /* GPP_F23: SMC_LID / ISH_GP9A*/ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8), +}; + void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { @@ -25,4 +116,18 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; } + + if (fw_config_probe(FW_CONFIG(WIFI_INTERFACE, WIFI_INTERFACE_PCIE_7))) { + GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_enable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads); + } else if (fw_config_probe(FW_CONFIG(WIFI_INTERFACE, WIFI_INTERFACE_CNVI_7))) { + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(SENSOR_HUB, ISH_PRESENT))) { + GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); + } } diff --git a/src/mainboard/google/ocelot/variants/ocicat/gpio.c b/src/mainboard/google/ocelot/variants/ocicat/gpio.c index 3c2f44b1c9f..fe1a8e2fc6e 100644 --- a/src/mainboard/google/ocelot/variants/ocicat/gpio.c +++ b/src/mainboard/google/ocelot/variants/ocicat/gpio.c @@ -150,9 +150,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D03: NC */ PAD_NC(GPP_D03, NONE), /* GPP_D05: ISH_UART0_ECAIC_RXD */ - PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), + PAD_NC(GPP_D05, NONE), /* GPP_D06: ISH_UART0_ECAIC_TXD */ - PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), + PAD_NC(GPP_D06, NONE), /* GPP_D07: NC */ PAD_NC(GPP_D07, NONE), /* GPP_D08: NC */ @@ -187,8 +187,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E05, NONE), /* GPP_E06: NC */ PAD_NC(GPP_E06, NONE), - /* GPP_E07: LAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW_LOCK(GPP_E07, NONE, EDGE_SINGLE, LOCK_CONFIG), + /* GPP_E07: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL), /* GPP_E08: EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */ @@ -238,7 +238,7 @@ static const struct pad_config gpio_table[] = { /* GPP_F07: NC */ PAD_NC(GPP_F07, NONE), /* GPP_F08: TCH_PNL1_PWR_EN */ - PAD_CFG_GPO(GPP_F08, 1, PLTRST), + PAD_NC(GPP_F08, NONE), /* GPP_F09: M2_UFS_RST_N */ PAD_CFG_GPO(GPP_F09, 1, DEEP), /* GPP_F10: ISH_ACCEL_MB_INT_L */ diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb index 8ed23a71480..a8b5ea39c87 100644 --- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb @@ -244,42 +244,8 @@ chip soc/intel/pantherlake device ref iaa off end - device ref thc0 on - register "thc_wake_on_touch[0]" = "true" - register "thc_mode[0]" = "THC_HID_I2C_MODE" - # THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled. - chip drivers/intel/touch - register "name" = "INTEL_THC0_NAME" - register "mode" = "THC_HID_I2C_MODE" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" - register "enable_delay_ms" = "2" - register "enable_off_delay_ms" = "2" - register "wake_on_touch" = "true" - # NOTE: Use GpioInt() in _CRS and does not use GPE. - register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" - register "active_ltr" = "1" - register "idle_ltr" = "0" - register "connected_device" = "TH_SENSOR_ELAN" - register "add_acpi_dma_property" = "true" - device generic 0 alias touch_0_i2c_elan on end - end - end - device ref thc1 on - register "thc_wake_on_touch[1]" = "true" - register "thc_mode[1]" = "THC_HID_I2C_MODE" - chip drivers/intel/touch - register "name" = "INTEL_THC1_NAME" - register "mode" = "THC_HID_I2C_MODE" - register "wake_on_touch" = "true" - # NOTE: Use GpioInt() in _CRS and does not use GPE. - register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" - register "active_ltr" = "1" - register "idle_ltr" = "0" - register "connected_device" = "TH_SENSOR_ELAN" - register "add_acpi_dma_property" = "true" - device generic 0 alias touch_1_i2c_hynitron on end - end - end + device ref thc0 off end + device ref thc1 off end device ref tcss_xhci on chip drivers/usb/acpi @@ -301,6 +267,7 @@ chip soc/intel/pantherlake end device ref ish on + probe SENSOR_HUB ISH_PRESENT chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 on end @@ -355,6 +322,7 @@ chip soc/intel/pantherlake device ref ufs on probe STORAGE_TYPE STORAGE_UFS probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN + register "ufs_inline_encryption" = "true" end device ref pcie_rp1 on diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c index 935327f2559..733cf6bf3b5 100644 --- a/src/mainboard/google/ocelot/variants/ocicat/variant.c +++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c @@ -15,25 +15,6 @@ const char *get_wifi_sar_cbfs_filename(void) return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE)); } -void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) -{ - /* Touchscreen and Touchpad WOT support: - * +===================+==================+=================+========================+ - * | Touchscreen | Touchpad | PMC_GPE0_DW0 | WOT | - * +===================+==================+=================+========================+ - * | THC-SPI/THC-I2C | THC-I2C | VGPIO | TS, TP | - * +===================+==================+=================+========================+ - * | THC-SPI/THC-I2C | LPSS-I2C | GPP_F18 | TP | - * +===================+==================+=================+========================+ - */ - - config->thc_mode[0] = THC_HID_I2C_MODE; - config->thc_mode[1] = THC_HID_I2C_MODE; - - /* touchscreen: GPP_F18: GPE0_DW0_18 */ - config->pmc_gpe0_dw0 = GPP_F; -} - void variant_update_soc_memory_init_params(FSPM_UPD *memupd) { FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; diff --git a/src/mainboard/google/ocelot/variants/ojal/gpio.c b/src/mainboard/google/ocelot/variants/ojal/gpio.c index acbb9199cf9..b2361ae6e54 100644 --- a/src/mainboard/google/ocelot/variants/ojal/gpio.c +++ b/src/mainboard/google/ocelot/variants/ojal/gpio.c @@ -67,8 +67,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13: PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14: GPP_B14_DDSP_HPDB */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), /* GPP_B16: NC */ PAD_NC(GPP_B16, NONE), /* GPP_B17: SPI_TPM_INT_N */ @@ -125,10 +123,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* GPP_C22: DDPB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), - /* GPP_C23: DDPB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_D */ /* GPP_D01: NC */ @@ -335,8 +329,14 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_B14: GPP_B14_DDSP_HPDB */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), /* GPP_B17: SPI_TPM_INT_N */ PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), + /* GPP_C22: DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_H06: I2C3_SDA_PSS */ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* GPP_H07: I2C3_SCL_PSS */ diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb index b548c3c4684..48941fa7f9d 100644 --- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb @@ -366,6 +366,7 @@ chip soc/intel/pantherlake device ref ufs on probe STORAGE STORAGE_UFS probe STORAGE STORAGE_UNKNOWN + register "ufs_inline_encryption" = "true" end device ref pcie_rp1 on diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 8723820f142..a23d3ce3c3c 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -27,22 +27,25 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select SOC_ESPI select SOC_INTEL_GEMINILAKE select SPI_TPM - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 config BOARD_GOOGLE_AMPTON select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_BLOOG select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_BOBBA select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CASTA select BOARD_GOOGLE_BASEBOARD_OCTOPUS @@ -56,15 +59,18 @@ config BOARD_GOOGLE_FLEEX select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_FOOB select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GARG select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_LICK select BOARD_GOOGLE_BASEBOARD_OCTOPUS @@ -74,6 +80,7 @@ config BOARD_GOOGLE_MEEP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_OCTOPUS select BOARD_GOOGLE_BASEBOARD_OCTOPUS @@ -82,6 +89,7 @@ config BOARD_GOOGLE_PHASER select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_YORP select BOARD_GOOGLE_BASEBOARD_OCTOPUS diff --git a/src/mainboard/google/octopus/cfr.c b/src/mainboard/google/octopus/cfr.c index bedb686b4ef..027e0b58579 100644 --- a/src/mainboard/google/octopus/cfr.c +++ b/src/mainboard/google/octopus/cfr.c @@ -12,6 +12,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 21c68bab82d..40ebf895a95 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -138,8 +138,6 @@ chip soc/intel/apollolake end device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index 857c1f933cd..9a420835258 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -58,6 +58,9 @@ * ACPI related definitions for ASL code. */ +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index a6cac573a33..6e5a3f2c925 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -85,8 +85,6 @@ chip soc/intel/apollolake device domain 0 on device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 11038d7e0a8..b0d6305c690 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -85,8 +85,6 @@ chip soc/intel/apollolake device domain 0 on device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-C Port"" diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index cef94552f7d..af485688913 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -52,7 +52,7 @@ config BOARD_GOOGLE_NAMI select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select SPI_TPM - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_NAUTILUS select BOARD_GOOGLE_BASEBOARD_POPPY @@ -92,7 +92,7 @@ config BOARD_GOOGLE_RAMMUS select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select SPI_TPM - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_SORAKA select BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c index 40bc75656f6..c4e42c2a091 100644 --- a/src/mainboard/google/poppy/cfr.c +++ b/src/mainboard/google/poppy/cfr.c @@ -26,6 +26,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index ebf9ea523b0..585c3017451 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -183,4 +183,7 @@ config EDK2_BOOT_TIMEOUT int default 5 +config INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING + default y + endif # BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c index 10df17757cb..e76e9f2a305 100644 --- a/src/mainboard/google/puff/cfr.c +++ b/src/mainboard/google/puff/cfr.c @@ -1,11 +1,43 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include #include +static const struct sm_object tdp_pl1_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl1_override", + .ui_name = "CPU PL1 power limit (W)", + .ui_helptext = "Long-duration CPU package power limit.\n" + "Default: 15 W. Range: 15-30 W.", + .default_value = 15, + .min = 15, + .max = 30, + .step = 1, + .display_flags = 0, +}); + +static void update_tdp_pl2_default(struct sm_object *new) +{ + new->sm_number.default_value = puff_default_pl2_watts(); +} + +static const struct sm_object tdp_pl2_override = SM_DECLARE_NUMBER({ + .opt_name = "tdp_pl2_override", + .ui_name = "CPU PL2 power limit (W)", + .ui_helptext = "Short-duration CPU package power limit.\n" + "Default: 35 W (U22) or 51 W (U42). Range: 35-51 W.\n" + "Must be >= PL1 (enforced at boot).", + .default_value = 35, + .min = 35, + .max = 51, + .step = 1, + .display_flags = 0, +}, WITH_CALLBACK(update_tdp_pl2_default)); + static struct sm_obj_form system = { .ui_name = "System", .obj_list = (const struct sm_object *[]) { @@ -15,6 +47,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, @@ -37,6 +70,9 @@ static struct sm_obj_form power = { .ui_name = "Power", .obj_list = (const struct sm_object *[]) { &power_on_after_fail, + &tdp_pl1_override, + &tdp_pl2_override, + &pkg_power_limit_lock, NULL }, }; @@ -45,6 +81,9 @@ static struct sm_obj_form *sm_root[] = { &system, &ec, &power, +#if CONFIG(INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING) + &cpu_voltage, +#endif NULL }; diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 3339033df6a..f2021c25d62 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -267,7 +267,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 090dc87be0d..64f9a3d6577 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -198,9 +198,7 @@ chip soc/intel/cannonlake device ref thermal on end device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/board.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/board.h new file mode 100644 index 00000000000..e47f8f43701 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/board.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GOOGLE_PUFF_BOARD_H +#define MAINBOARD_GOOGLE_PUFF_BOARD_H + +unsigned int puff_default_pl2_watts(void); + +#endif diff --git a/src/mainboard/google/puff/variants/baseboard/mainboard.c b/src/mainboard/google/puff/variants/baseboard/mainboard.c index b455c6df0cd..ba5bf854f1b 100644 --- a/src/mainboard/google/puff/variants/baseboard/mainboard.c +++ b/src/mainboard/google/puff/variants/baseboard/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -89,6 +90,16 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 +unsigned int puff_default_pl2_watts(void) +{ + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + const u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + + if (mch_id == PCI_DID_INTEL_CML_ULT || mch_id == PCI_DID_INTEL_CML_ULT_6_2) + return PUFF_U62_U42_PL2; + return PUFF_U22_PL2; +} + static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; @@ -114,11 +125,7 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf) psyspl2 = SET_PSYSPL2(watts); /* Limit PL2 if the adapter is with lower capability */ - if (mch_id == PCI_DID_INTEL_CML_ULT || - mch_id == PCI_DID_INTEL_CML_ULT_6_2) - pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; - else - pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; + pl2 = (psyspl2 > puff_default_pl2_watts()) ? puff_default_pl2_watts() : psyspl2; conf->tdp_psyspl3 = psyspl2; /* set max possible time window */ diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index e8095c62676..dc9cc28a95b 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -240,7 +240,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port 0"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index eee3d480211..badd68c7500 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -326,7 +326,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index a2f53df0b1c..c43c6036c77 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -300,7 +300,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index a635cd2cb3d..fc3792e629a 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -291,7 +291,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 0b539a1a0b7..168eb955f24 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -326,7 +326,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index d0c8b8de949..42bc1cb161b 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -291,7 +291,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index c5407bd0f20..2e8dd42a49b 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -249,7 +249,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index beb53ef4db7..ef62aaa6da3 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -261,7 +261,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 50dcdaf6047..d4f4d470250 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -290,7 +290,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 1373928a929..b6d160ccbef 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -262,7 +262,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 399872e230c..e7208560d12 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -64,6 +64,9 @@ config BOARD_GOOGLE_KIP config BOARD_GOOGLE_NINJA select BOARD_GOOGLE_BASEBOARD_RAMBI select INTEL_GMA_HAVE_VBT + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select RT8168_SUPPORT_LEGACY_VPD_MAC select SYSTEM_TYPE_MINIPC config BOARD_GOOGLE_ORCO @@ -88,6 +91,9 @@ config BOARD_GOOGLE_RAMBI config BOARD_GOOGLE_SUMO select BOARD_GOOGLE_BASEBOARD_RAMBI select INTEL_GMA_HAVE_VBT + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select RT8168_SUPPORT_LEGACY_VPD_MAC select SYSTEM_TYPE_ALL_IN_ONE config BOARD_GOOGLE_SWANKY diff --git a/src/mainboard/google/rambi/Makefile.mk b/src/mainboard/google/rambi/Makefile.mk index e0d552476eb..923eee46e06 100644 --- a/src/mainboard/google/rambi/Makefile.mk +++ b/src/mainboard/google/rambi/Makefile.mk @@ -8,9 +8,6 @@ ramstage-y += w25q64.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c -ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c -ramstage-$(CONFIG_BOARD_GOOGLE_SUMO) += variants/$(VARIANT_DIR)/lan.c - subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 532680b0ef7..14bb820dbaf 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -5,11 +5,11 @@ chip soc/intel/baytrail # SATA port enable mask (2 ports) register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "true" + register "ide_legacy_combined" = "false" # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" + register "usb_route_to_xhci" = "true" # USB Port Disable Mask register "usb2_port_disable_mask" = "0x0" @@ -34,9 +34,9 @@ chip soc/intel/baytrail register "sdcard_cap_high" = "0x0" # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" + register "lpe_acpi_mode" = "true" + register "lpss_acpi_mode" = "true" + register "scc_acpi_mode" = "true" # Enable PIPEA as DP_C register "gpu_pipea_port_select" = "2" # DP_C @@ -47,11 +47,11 @@ chip soc/intel/baytrail register "gpu_pipea_light_off_delay" = "2000" # 200ms # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" + register "vnn_ps2_enable" = "true" + register "vcc_ps2_enable" = "true" # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" + register "disable_slp_x_stretch_sus_fail" = "true" device cpu_cluster 0 on end device domain 0 on diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index df27e39724a..7823a88a041 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -11,9 +11,6 @@ static void mainboard_init(struct device *dev) { mainboard_ec_init(); -#if CONFIG(BOARD_GOOGLE_NINJA) || CONFIG(BOARD_GOOGLE_SUMO) - lan_init(); -#endif } static int mainboard_smbios_data(struct device *dev, int *handle, diff --git a/src/mainboard/google/rambi/variants/banjo/overridetree.cb b/src/mainboard/google/rambi/variants/banjo/overridetree.cb index bd37ec63bda..41ced21bb81 100644 --- a/src/mainboard/google/rambi/variants/banjo/overridetree.cb +++ b/src/mainboard/google/rambi/variants/banjo/overridetree.cb @@ -3,7 +3,7 @@ chip soc/intel/baytrail register "sdcard_cap_low" = "0x0" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 12.0 off end # SD diff --git a/src/mainboard/google/rambi/variants/candy/overridetree.cb b/src/mainboard/google/rambi/variants/candy/overridetree.cb index dcd001b8ae7..e2902585b6d 100644 --- a/src/mainboard/google/rambi/variants/candy/overridetree.cb +++ b/src/mainboard/google/rambi/variants/candy/overridetree.cb @@ -3,7 +3,7 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 18.6 on end # I2C6 diff --git a/src/mainboard/google/rambi/variants/enguarde/overridetree.cb b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb index 5a0589ac43a..67854f57e66 100644 --- a/src/mainboard/google/rambi/variants/enguarde/overridetree.cb +++ b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/expresso/overridetree.cb b/src/mainboard/google/rambi/variants/expresso/overridetree.cb index 6d2d625a57c..3c1e5bde4ea 100644 --- a/src/mainboard/google/rambi/variants/expresso/overridetree.cb +++ b/src/mainboard/google/rambi/variants/expresso/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 18.5 on end # I2C5 diff --git a/src/mainboard/google/rambi/variants/gnawty/overridetree.cb b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb index 5a0589ac43a..67854f57e66 100644 --- a/src/mainboard/google/rambi/variants/gnawty/overridetree.cb +++ b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/heli/overridetree.cb b/src/mainboard/google/rambi/variants/heli/overridetree.cb index fb59964b6ae..7387d40e204 100644 --- a/src/mainboard/google/rambi/variants/heli/overridetree.cb +++ b/src/mainboard/google/rambi/variants/heli/overridetree.cb @@ -3,7 +3,7 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/kip/overridetree.cb b/src/mainboard/google/rambi/variants/kip/overridetree.cb index 5a0589ac43a..67854f57e66 100644 --- a/src/mainboard/google/rambi/variants/kip/overridetree.cb +++ b/src/mainboard/google/rambi/variants/kip/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h index 09c8500edeb..194d3352d4c 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h @@ -5,17 +5,6 @@ #include -#ifndef __ACPI__ -void lan_init(void); -#endif - -/* defines for programming the MAC address */ -#define NINJA_NIC_VENDOR_ID 0x10EC -#define NINJA_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define NINJA_NIC_LED_MODE 0x00 - /* PCH wake signal from EC. */ #define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c deleted file mode 100644 index 8dfdb082263..00000000000 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_ERR, "Invalid Hex digit found: %c - 0x%02x\n", *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (CONFIG(VPD)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_map("vpd.bin", &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(NINJA_NIC_VENDOR_ID, - NINJA_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((NINJA_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/rambi/variants/ninja/overridetree.cb b/src/mainboard/google/rambi/variants/ninja/overridetree.cb index 47527da2b3c..76409a5a543 100644 --- a/src/mainboard/google/rambi/variants/ninja/overridetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/overridetree.cb @@ -6,10 +6,17 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on - device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.2 on # PCIE_PORT3, LAN + chip drivers/net + register "customized_leds" = "0x0087" + register "device_index" = "0" + register "enable_pcie_clkreq" = "true" + device pci 00.0 on end + end + end device pci 1c.3 on end # PCIE_PORT4 end end diff --git a/src/mainboard/google/rambi/variants/orco/overridetree.cb b/src/mainboard/google/rambi/variants/orco/overridetree.cb index 5a0589ac43a..67854f57e66 100644 --- a/src/mainboard/google/rambi/variants/orco/overridetree.cb +++ b/src/mainboard/google/rambi/variants/orco/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/rambi/overridetree.cb b/src/mainboard/google/rambi/variants/rambi/overridetree.cb index 7ba9463447e..23ab39a242a 100644 --- a/src/mainboard/google/rambi/variants/rambi/overridetree.cb +++ b/src/mainboard/google/rambi/variants/rambi/overridetree.cb @@ -3,7 +3,7 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 18.6 on end # I2C6 diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h index 1a5b94df1fb..7cc99383a10 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h @@ -5,17 +5,6 @@ #include -#ifndef __ACPI__ -void lan_init(void); -#endif - -/* defines for programming the MAC address */ -#define SUMO_NIC_VENDOR_ID 0x10EC -#define SUMO_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define SUMO_NIC_LED_MODE 0x00 - /* PCH wake signal from EC. */ #define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c deleted file mode 100644 index 168f8b50dcd..00000000000 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_ERR, "Invalid Hex digit found: %c - 0x%02x\n", *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (CONFIG(VPD)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_map("vpd.bin", &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(SUMO_NIC_VENDOR_ID, - SUMO_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((SUMO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/rambi/variants/sumo/overridetree.cb b/src/mainboard/google/rambi/variants/sumo/overridetree.cb index 35052dc1543..282301e74c1 100644 --- a/src/mainboard/google/rambi/variants/sumo/overridetree.cb +++ b/src/mainboard/google/rambi/variants/sumo/overridetree.cb @@ -3,11 +3,18 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 18.6 on end # I2C6 - device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.2 on # PCIE_PORT3, LAN + chip drivers/net + register "customized_leds" = "0x0087" + register "device_index" = "0" + register "enable_pcie_clkreq" = "true" + device pci 00.0 on end + end + end device pci 1c.3 on end # PCIE_PORT4 end end diff --git a/src/mainboard/google/rambi/variants/swanky/overridetree.cb b/src/mainboard/google/rambi/variants/swanky/overridetree.cb index 5a0589ac43a..67854f57e66 100644 --- a/src/mainboard/google/rambi/variants/swanky/overridetree.cb +++ b/src/mainboard/google/rambi/variants/swanky/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rambi/variants/winky/overridetree.cb b/src/mainboard/google/rambi/variants/winky/overridetree.cb index d09ecbc48da..931b3c4c1ca 100644 --- a/src/mainboard/google/rambi/variants/winky/overridetree.cb +++ b/src/mainboard/google/rambi/variants/winky/overridetree.cb @@ -5,7 +5,7 @@ chip soc/intel/baytrail register "usb2_comp_bg" = "0x4680" # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" + register "pcie_wake_enable" = "true" device domain 0 on device pci 1c.1 on end # PCIE_PORT2 diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index dbbfcfb3605..118d053b4e7 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -9,6 +9,11 @@ config BOARD_GOOGLE_RAURU_COMMON if BOARD_GOOGLE_RAURU_COMMON +config RAURU_HAS_CBI_SKU_ID + def_bool BOARD_GOOGLE_HYLIA || \ + BOARD_GOOGLE_NAVI || \ + BOARD_GOOGLE_RAURU + config RAURU_SDCARD_INIT def_bool BOARD_GOOGLE_RAURU @@ -24,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select COOP_MULTITASKING if BOARD_GOOGLE_SAPPHIRE select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS && !MEDIATEK_WDT_RESET_BY_SW diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk index b13c77ecf66..e8688ffe8dd 100644 --- a/src/mainboard/google/rauru/Makefile.mk +++ b/src/mainboard/google/rauru/Makefile.mk @@ -9,6 +9,7 @@ bootblock-y += bootblock.c romstage-y += romstage.c ramstage-y += boardid.c +ramstage-$(CONFIG_RAURU_HAS_CBI_SKU_ID) += sku_id.c ramstage-y += mainboard.c ramstage-y += panel.c ramstage-y += regulator.c diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index 09194f5c0dd..55ce33ab7d7 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -1,21 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include -#include #include -#include "panel.h" -#include "storage.h" - #define ADC_LEVELS 8 -DEFINE_BITFIELD(STORAGE_TYPE, 11, 9); -DEFINE_BITFIELD(CPU_TYPE, 8, 8); -DEFINE_BITFIELD(PANEL_TYPE, 7, 0); - enum { /* Storage IDs */ STORAGE_ID_LOW_CHANNEL = AUXADC_CHAN_VIN1, @@ -90,22 +84,3 @@ uint32_t storage_id(void) printk(BIOS_DEBUG, "Storage ID: %#02x\n", cached_storage_id); return cached_storage_id; } - -uint32_t sku_id(void) -{ - static uint32_t cached_sku_code = BOARD_ID_INIT; - - if (cached_sku_code == BOARD_ID_INIT) { - cached_sku_code = google_chromeec_get_board_sku(); - - if (cached_sku_code == CROS_SKU_UNKNOWN || - cached_sku_code == CROS_SKU_UNPROVISIONED) { - printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); - cached_sku_code = CROS_SKU_UNPROVISIONED; - SET32_BITFIELDS(&cached_sku_code, STORAGE_TYPE, storage_id()); - } - printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); - } - - return cached_sku_code; -} diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index 6e0a4eea162..f9eb06c0022 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,8 +8,6 @@ #include #include -#include "gpio.h" - static void usb3_hub_reset(void) { gpio_output(GPIO(USB_RST), 1); diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index b784a2f3f79..ea21523a4a6 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { /* Set up open-drain pins */ diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/rauru/gpio.h rename to src/mainboard/google/rauru/include/baseboard/gpio.h diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/include/baseboard/panel.h similarity index 94% rename from src/mainboard/google/rauru/panel.h rename to src/mainboard/google/rauru/include/baseboard/panel.h index d44ff10774a..6c08d01a7ca 100644 --- a/src/mainboard/google/rauru/panel.h +++ b/src/mainboard/google/rauru/include/baseboard/panel.h @@ -4,6 +4,7 @@ #define __MAINBOARD_GOOGLE_RAURU_PANEL_H__ #include +#include uint32_t panel_id(void); void configure_backlight(bool enable); diff --git a/src/mainboard/google/rauru/storage.h b/src/mainboard/google/rauru/include/baseboard/storage.h similarity index 89% rename from src/mainboard/google/rauru/storage.h rename to src/mainboard/google/rauru/include/baseboard/storage.h index a1b4d63ccee..c3ea233722c 100644 --- a/src/mainboard/google/rauru/storage.h +++ b/src/mainboard/google/rauru/include/baseboard/storage.h @@ -3,6 +3,8 @@ #ifndef __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ #define __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ +#include + uint32_t storage_id(void); #endif diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 93489426b8c..b7092e75bb7 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -14,11 +16,9 @@ #include #include #include +#include #include -#include "gpio.h" -#include "storage.h" - #define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) static void configure_tas2563(void) @@ -109,16 +109,52 @@ bool mainboard_needs_pcie_init(void) return mainboard_get_storage_type() == STORAGE_NVME; } +static struct thread_handle display_thread; +static struct thread_mutex display_thread_start_mutex; + +static enum cb_err display_init_thread(void *unused) +{ + /* The display thread takes the mutex to block the main thread from + starting soc_init until the display thread is ready. */ + thread_mutex_lock(&display_thread_start_mutex); + + if (mtk_display_init(&display_thread_start_mutex) < 0) { + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + thread_mutex_unlock(&display_thread_start_mutex); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static void mainboard_final(struct device *dev) +{ + if (!ENV_SUPPORTS_COOP) + return; + thread_join(&display_thread); +} + static void mainboard_init(struct device *dev) { if (display_init_required()) { enable_display_power_rail(); - if (mtk_display_init() < 0) - printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + if (ENV_SUPPORTS_COOP) { + if (thread_run(&display_thread, display_init_thread, NULL)) + die("%s: Failed to start display init thread\n", __func__); + } else { + if (mtk_display_init(NULL) < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + + } } else { printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); } + /* The main thread waits here until the display thread reaches the MIPI + delay window and unlocks this mutex. */ + thread_mutex_lock(&display_thread_start_mutex); + thread_mutex_unlock(&display_thread_start_mutex); + setup_usb_host(); power_on_fpmcu(); configure_audio(); @@ -133,6 +169,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = &mainboard_init; + dev->ops->final = &mainboard_final; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c index beb979a009f..8b3bc7a1912 100644 --- a/src/mainboard/google/rauru/panel.c +++ b/src/mainboard/google/rauru/panel.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include +#include #include #include #include #include #include -#include "gpio.h" -#include "panel.h" - void configure_backlight(bool enable) { gpio_output(GPIO_AP_EDP_BKLTEN, enable); diff --git a/src/mainboard/google/rauru/panel_sapphire.c b/src/mainboard/google/rauru/panel_sapphire.c index 829ef0c54fe..7ceb94f9eda 100644 --- a/src/mainboard/google/rauru/panel_sapphire.c +++ b/src/mainboard/google/rauru/panel_sapphire.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include -#include "gpio.h" -#include "panel.h" - static void mipi_panel_power_on(void) { mt6363_enable_vrf18(true); /* VDD */ diff --git a/src/mainboard/google/rauru/reset.c b/src/mainboard/google/rauru/reset.c index 05a576b69c3..b0464f5488c 100644 --- a/src/mainboard/google/rauru/reset.c +++ b/src/mainboard/google/rauru/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); diff --git a/src/mainboard/google/rauru/sku_id.c b/src/mainboard/google/rauru/sku_id.c new file mode 100644 index 00000000000..0c8df6275ef --- /dev/null +++ b/src/mainboard/google/rauru/sku_id.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +DEFINE_BITFIELD(STORAGE_TYPE, 11, 9); +DEFINE_BITFIELD(CPU_TYPE, 8, 8); +DEFINE_BITFIELD(PANEL_TYPE, 7, 0); + +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN || + cached_sku_code == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = CROS_SKU_UNPROVISIONED; + SET32_BITFIELDS(&cached_sku_code, STORAGE_TYPE, storage_id()); + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} diff --git a/src/mainboard/google/rauru/variants/sapphire/fw_config.c b/src/mainboard/google/rauru/variants/sapphire/fw_config.c index c5a1b6a0f84..aef4b36f7d3 100644 --- a/src/mainboard/google/rauru/variants/sapphire/fw_config.c +++ b/src/mainboard/google/rauru/variants/sapphire/fw_config.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include +#include #include #include @@ -10,3 +12,17 @@ enum audio_amplifier_id get_audio_amp_id(void) return AUD_AMP_ID_UNKNOWN; } + +void fw_config_get_mainboard_override(uint64_t *fw_config) +{ + /* Handle unprovisioned fw_config. */ + if (*fw_config == UNDEFINED_FW_CONFIG) { + /* Reset fw_config to a default value with boot-necessary fields. + For now, setting to 0 is sufficient. */ + *fw_config = 0; + } + + uint32_t id = panel_id(); + printk(BIOS_INFO, "Overriding fw_config PANEL_ID with %u\n", id); + fw_config_value_set_field(fw_config, FW_CONFIG_FIELD(PANEL_ID), id); +} diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 1ce23534320..b8d09b8fd80 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -21,23 +21,26 @@ config BOARD_GOOGLE_BASEBOARD_REEF select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select SOC_INTEL_APOLLOLAKE - select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 config BOARD_GOOGLE_REEF select BOARD_GOOGLE_BASEBOARD_REEF + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_PYRO select BOARD_GOOGLE_BASEBOARD_REEF + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_SAND select BOARD_GOOGLE_BASEBOARD_REEF config BOARD_GOOGLE_SNAPPY select BOARD_GOOGLE_BASEBOARD_REEF + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CORAL select BOARD_GOOGLE_BASEBOARD_REEF + select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_BASEBOARD_REEF diff --git a/src/mainboard/google/reef/cfr.c b/src/mainboard/google/reef/cfr.c index bedb686b4ef..027e0b58579 100644 --- a/src/mainboard/google/reef/cfr.c +++ b/src/mainboard/google/reef/cfr.c @@ -12,6 +12,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 6f22832d5f4..4ad2f97cb15 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -47,6 +47,9 @@ * ACPI related definitions for ASL code. */ +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/rex/cfr.c b/src/mainboard/google/rex/cfr.c index d64bbc7b79a..1cc7f5fe9c0 100644 --- a/src/mainboard/google/rex/cfr.c +++ b/src/mainboard/google/rex/cfr.c @@ -14,6 +14,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 901d4083485..f8d98ce3911 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -80,7 +80,7 @@ chip soc/intel/meteorlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index b973cefbf15..27c095100dd 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -76,7 +76,7 @@ chip soc/intel/meteorlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 1048acb0811..deb05ad62c3 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -80,7 +80,7 @@ chip soc/intel/meteorlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 6df6c7368bc..76e8b40ce5f 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -73,7 +73,7 @@ chip soc/intel/meteorlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index d4f5171d611..2f4bda9554f 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -21,6 +21,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_PLATFORM_DATA_REGION select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL select SOC_INTEL_COMMON_BLOCK_HDA_VERB @@ -48,9 +49,6 @@ config CHROMEOS_WIFI_SAR select SAR_ENABLE select USE_SAR -config DISABLE_HECI1_AT_PRE_BOOT - default y - config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -108,7 +106,7 @@ config VBOOT select VBOOT_LID_SWITCH config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS config CBFS_SIZE default 0x1000000 diff --git a/src/mainboard/google/sarien/cfr.c b/src/mainboard/google/sarien/cfr.c index 805b2870a12..51063ed37b3 100644 --- a/src/mainboard/google/sarien/cfr.c +++ b/src/mainboard/google/sarien/cfr.c @@ -14,6 +14,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/sarien/default.fmd b/src/mainboard/google/sarien/default.fmd deleted file mode 100644 index 4a9738c6c9a..00000000000 --- a/src/mainboard/google/sarien/default.fmd +++ /dev/null @@ -1,11 +0,0 @@ -FLASH 0x2000000 { - SI_BIOS@0x400000 { - MEMORY_MAPPED@0xc00000 { /* 16MiB total */ - RW_MRC_CACHE 0x10000 - SMMSTORE 0x80000 - RO_VPD 0x4000 - FMAP 0x300 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1c8f8a40c28..feb07fb56cc 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -216,9 +216,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 7bc72d67a0d..26e1e66b51e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -221,9 +221,7 @@ chip soc/intel/cannonlake device ref thermal on end device ref xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" diff --git a/src/mainboard/google/sarien/variants/sarien/hda_verb.c b/src/mainboard/google/sarien/variants/sarien/hda_verb.c index feea154b662..0449743bfaa 100644 --- a/src/mainboard/google/sarien/variants/sarien/hda_verb.c +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -116,6 +116,15 @@ const u32 cim_verb_data[] = { 0x0534E01A, 0x05350000, 0x0534E01A, + + 0x8086280b, /* Codec Vendor/Device ID: Intel WhiskeyLake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb index d42dea7478c..42c015038c4 100644 --- a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb @@ -87,8 +87,7 @@ chip soc/amd/mendocino chip drivers/i2c/hid register "generic.hid" = ""PIXA2635"" register "generic.desc" = ""PIXA Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" - register "generic.wake" = "GEVENT_20" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h index 9e61a440cff..dac67ca295b 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h +++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h @@ -1,3 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + #include + +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + +#endif diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index c81fe115273..c913bd9e28a 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -54,8 +54,7 @@ chip soc/amd/mendocino chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" - register "wake" = "GEVENT_20" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "detect" = "1" device i2c 15 on end end @@ -126,8 +125,7 @@ chip soc/amd/mendocino register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" - register "wake" = "GEVENT_15" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb index 3de0ec84d59..e5333dc8f61 100644 --- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb @@ -73,8 +73,7 @@ chip soc/amd/mendocino chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" - register "wake" = "GEVENT_20" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "detect" = "1" device i2c 15 on end end @@ -82,8 +81,7 @@ chip soc/amd/mendocino register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" - register "generic.wake" = "GEVENT_20" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 8272169ddab..2a6cb3b0198 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -121,8 +121,7 @@ chip soc/amd/mendocino chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" - register "wake" = "GEVENT_20" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "detect" = "1" device i2c 15 on end end @@ -149,7 +148,7 @@ chip soc/amd/mendocino register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" @@ -231,8 +230,7 @@ chip soc/amd/mendocino register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" - register "wake" = "GEVENT_15" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 9fcf99f7f77..6f015b7dee2 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -161,16 +161,14 @@ chip soc/amd/mendocino chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" - register "wake" = "GEVENT_20" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid register "generic.hid" = ""GXTP7863"" register "generic.desc" = ""Goodix Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" - register "generic.wake" = "GEVENT_20" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -198,7 +196,7 @@ chip soc/amd/mendocino register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" @@ -243,8 +241,7 @@ chip soc/amd/mendocino register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" - register "wake" = "GEVENT_15" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index a61cb6d46f7..5098a35556c 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -10,6 +10,8 @@ config BOARD_GOOGLE_SKYWALKER_COMMON BOARD_GOOGLE_MACE || \ BOARD_GOOGLE_OBIWAN || \ BOARD_GOOGLE_PADME || \ + BOARD_GOOGLE_R2D2 || \ + BOARD_GOOGLE_SHEEV || \ BOARD_GOOGLE_SKYWALKER || \ BOARD_GOOGLE_TARKIN || \ BOARD_GOOGLE_VADER || \ @@ -62,6 +64,8 @@ config MAINBOARD_PART_NUMBER default "Mace" if BOARD_GOOGLE_MACE default "Obiwan" if BOARD_GOOGLE_OBIWAN default "Padme" if BOARD_GOOGLE_PADME + default "R2d2" if BOARD_GOOGLE_R2D2 + default "Sheev" if BOARD_GOOGLE_SHEEV default "Skywalker" if BOARD_GOOGLE_SKYWALKER default "Tarkin" if BOARD_GOOGLE_TARKIN default "Vader" if BOARD_GOOGLE_VADER diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name index ad04340621a..f9781c507ce 100644 --- a/src/mainboard/google/skywalker/Kconfig.name +++ b/src/mainboard/google/skywalker/Kconfig.name @@ -26,6 +26,12 @@ config BOARD_GOOGLE_OBIWAN config BOARD_GOOGLE_PADME bool "-> Padme" +config BOARD_GOOGLE_R2D2 + bool "-> R2d2" + +config BOARD_GOOGLE_SHEEV + bool "-> Sheev" + config BOARD_GOOGLE_SKYWALKER bool "-> Skywalker" diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk index 4a21a591875..d357b505cfe 100644 --- a/src/mainboard/google/skywalker/Makefile.mk +++ b/src/mainboard/google/skywalker/Makefile.mk @@ -15,3 +15,5 @@ ramstage-y += panel.c ramstage-y += regulator.c ramstage-$(CONFIG_BOARD_GOOGLE_PADME) += panel_padme.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/google/skywalker/boardid.c b/src/mainboard/google/skywalker/boardid.c index e2ba9e13d4c..4539a280098 100644 --- a/src/mainboard/google/skywalker/boardid.c +++ b/src/mainboard/google/skywalker/boardid.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include #include -#include "panel.h" -#include "storage.h" - #define ADC_LEVELS 8 #define PANEL_ADC_LEVELS 3 diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c index 16926851ffc..b840db9a45a 100644 --- a/src/mainboard/google/skywalker/bootblock.c +++ b/src/mainboard/google/skywalker/bootblock.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include #include #include #include #include #include -#include "gpio.h" - void bootblock_mainboard_init(void) { mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS); diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index bbb8fadcb5d..afda0d16e98 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include #include #include #include #include #include -#include "gpio.h" - void setup_chromeos_gpios(void) { gpio_input(GPIO_EC_AP_INT_ODL); diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/skywalker/gpio.h rename to src/mainboard/google/skywalker/include/baseboard/gpio.h diff --git a/src/mainboard/google/skywalker/panel.h b/src/mainboard/google/skywalker/include/baseboard/panel.h similarity index 96% rename from src/mainboard/google/skywalker/panel.h rename to src/mainboard/google/skywalker/include/baseboard/panel.h index f38f50404d6..9ccc41c3c9e 100644 --- a/src/mainboard/google/skywalker/panel.h +++ b/src/mainboard/google/skywalker/include/baseboard/panel.h @@ -7,6 +7,7 @@ #include #include #include +#include #define PMIC_AW37503_SLAVE 0x3E #define PMIC_I2C_BUS I2C6 diff --git a/src/mainboard/google/skywalker/storage.h b/src/mainboard/google/skywalker/include/baseboard/storage.h similarity index 89% rename from src/mainboard/google/skywalker/storage.h rename to src/mainboard/google/skywalker/include/baseboard/storage.h index dbdf2f3c54a..f13a4e9a3de 100644 --- a/src/mainboard/google/skywalker/storage.h +++ b/src/mainboard/google/skywalker/include/baseboard/storage.h @@ -3,6 +3,8 @@ #ifndef __MAINBOARD_GOOGLE_SKYWALKER_STORAGE_H__ #define __MAINBOARD_GOOGLE_SKYWALKER_STORAGE_H__ +#include + uint32_t storage_id(void); #endif diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c index f7191e91400..d0f4c873529 100644 --- a/src/mainboard/google/skywalker/mainboard.c +++ b/src/mainboard/google/skywalker/mainboard.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include +#include +#include #include #include #include @@ -21,10 +24,6 @@ #include #include -#include "gpio.h" -#include "panel.h" -#include "storage.h" - #define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) static void setup_i2s_speaker(void) @@ -157,7 +156,7 @@ static void mainboard_init(struct device *dev) register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true); if (display_init_required()) { - if (mtk_display_init() < 0) + if (mtk_display_init(NULL) < 0) printk(BIOS_ERR, "%s: Failed to init display\n", __func__); } else { printk(BIOS_INFO, "%s: Skipping display init; disabling secure mode\n", diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c index 5856cf40444..ff0a86df229 100644 --- a/src/mainboard/google/skywalker/panel.c +++ b/src/mainboard/google/skywalker/panel.c @@ -1,16 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include +#include #include #include #include - #include #include #include -#include "gpio.h" -#include "panel.h" - static void aw37503_init(unsigned int bus) { i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x13, 0x1F, 0); diff --git a/src/mainboard/google/skywalker/panel_padme.c b/src/mainboard/google/skywalker/panel_padme.c index 13fdaa62cfe..1ecfacc5a95 100644 --- a/src/mainboard/google/skywalker/panel_padme.c +++ b/src/mainboard/google/skywalker/panel_padme.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include "gpio.h" -#include "panel.h" - static struct panel_description padme_panels[] = { [0x22] = { .configure_backlight = panel_configure_backlight, diff --git a/src/mainboard/google/skywalker/reset.c b/src/mainboard/google/skywalker/reset.c index e50cf3bbfa6..d0157da4f50 100644 --- a/src/mainboard/google/skywalker/reset.c +++ b/src/mainboard/google/skywalker/reset.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include #include #include -#include "gpio.h" - void do_board_reset(void) { gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index dc586f1538a..818bf9827ec 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -40,6 +40,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_TI50 if BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 @@ -51,16 +52,19 @@ config BOARD_GOOGLE_CHRONICLER config BOARD_GOOGLE_COLLIS select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_COPANO select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_DELBIN select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_DROBIT select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -71,6 +75,7 @@ config BOARD_GOOGLE_DROBIT config BOARD_GOOGLE_ELDRID select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_ELEMI select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -108,6 +113,7 @@ config BOARD_GOOGLE_VOEMA select DRIVERS_GFX_GENERIC select DRIVERS_INTEL_MIPI_CAMERA select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_VOLET select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -142,6 +148,7 @@ config BOARD_GOOGLE_VOXEL select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c index 3ddcdb1a194..52f2bf972d5 100644 --- a/src/mainboard/google/volteer/cfr.c +++ b/src/mainboard/google/volteer/cfr.c @@ -24,6 +24,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &disable_heci1_at_pre_boot, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index c17dd7cdb77..b95b6076c34 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "drivers/intel/pmc_mux/conn/chip.h" diff --git a/src/mainboard/google/volteer/variants/collis/include/variant/ec.h b/src/mainboard/google/volteer/variants/collis/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/volteer/variants/collis/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/collis/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h b/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h index 7a2a6ff8b77..dac67ca295b 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h index 4a9a461191e..3e5ff526b52 100644 --- a/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h @@ -5,4 +5,9 @@ #include +/* Enable Tablet switch for Windows drivers */ +#if !CONFIG(CHROMEOS) +#define EC_ENABLE_TBMC_DEVICE +#endif + #endif diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index b828a5a0042..07ee99b02b2 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -17,12 +17,15 @@ config BOARD_GOOGLE_DIRINBOZ config BOARD_GOOGLE_EZKINIL select BOARD_GOOGLE_BASEBOARD_TREMBYLE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_GUMBOZ select BOARD_GOOGLE_BASEBOARD_DALBOZ + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_MORPHIUS select BOARD_GOOGLE_BASEBOARD_TREMBYLE + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_SHUBOZ select BOARD_GOOGLE_BASEBOARD_DALBOZ @@ -37,6 +40,7 @@ config BOARD_GOOGLE_VILBOZ config BOARD_GOOGLE_WOOMAX select BOARD_GOOGLE_BASEBOARD_TREMBYLE + select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ @@ -84,7 +88,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_PICASSO - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_CR50 config ELOG_BOOT_COUNT_CMOS_OFFSET diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb index 4af7231eb9f..2f8a712f4f9 100644 --- a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb @@ -11,7 +11,7 @@ chip soc/amd/picasso # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" # See table 5-34 ACPI 6.3 spec - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" + register "common_config.fadt_flags" = "ACPI_FADT_SEALED_CASE" # ACP Configuration register "common_config.acp_config" = "{ @@ -64,7 +64,7 @@ chip soc/amd/picasso .init_khz_preset = 1, }" - register "has_usb2_phy_tune_params" = "1" + register "has_usb2_phy_tune_params" = "true" # Controller0 Port0 Default register "usb_2_port_tune_params[0]" = "{ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index b28a4894c49..2c503aed1d9 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -58,6 +58,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb index 9b5a4c05dbe..b3f1e448055 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb @@ -9,7 +9,7 @@ chip soc/amd/picasso # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" # See table 5-34 ACPI 6.3 spec - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" + register "common_config.fadt_flags" = "ACPI_FADT_SEALED_CASE" # ACP Configuration register "common_config.acp_config" = "{ @@ -62,7 +62,7 @@ chip soc/amd/picasso .init_khz_preset = 1, }" - register "has_usb2_phy_tune_params" = "1" + register "has_usb2_phy_tune_params" = "true" # Controller0 Port0 Default register "usb_2_port_tune_params[0]" = "{ diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 3a6c74a1053..1be6e46068e 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -126,8 +126,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -135,8 +134,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -145,7 +143,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" @@ -159,7 +157,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" @@ -188,8 +186,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" - register "wake" = "GEVENT_10" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end end diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index ffba8853598..63d4e0c641b 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -47,7 +47,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line # 20ms: Firmware ready time @@ -59,7 +59,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "true" @@ -93,8 +93,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -102,8 +101,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index f7cdad96e30..0a4437f5f84 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -198,8 +198,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index dc189408665..e3d935ca789 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -84,8 +84,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -93,8 +92,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -103,7 +101,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb index f7cdad96e30..0a4437f5f84 100644 --- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -198,8 +198,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 2e4595ee96e..c918aa3c0f3 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -101,8 +101,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -110,8 +109,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -151,8 +149,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" - register "wake" = "GEVENT_10" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 hidden end end diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index b0ecb494d9e..49250a8e8f5 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -155,8 +155,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on probe TOUCHPAD REGULAR_TOUCHPAD @@ -165,8 +164,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""ELAN2702"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 15 on diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 62d324688ff..fa547c827d0 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -75,8 +75,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -84,8 +83,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -94,7 +92,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line # 20ms: Firmware ready time @@ -108,7 +106,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "true" @@ -122,8 +120,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" - register "wake" = "GEVENT_10" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end end diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index e49ae8d8d46..93786061af8 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -15,8 +15,18 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { }; static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { +/* + * The proximity sensor is only used for SAR under ChromeOS, and + * can cause an IRQ storm under Windows, so configure as a GPI + * for non-ChromeOS builds to avoid leaving in the baseboard- + * programmed state of GPO/high which could damage the sensor +*/ +#if CONFIG(CHROMEOS) /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), +#else + PAD_GPI(GPIO_40, PULL_NONE), +#endif /* LTE_RST_L */ PAD_GPO(GPIO_89, HIGH), }; diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 8740611c6a7..b694fe01272 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -249,7 +249,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" @@ -275,8 +275,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end @@ -284,8 +283,7 @@ chip soc/amd/picasso register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "generic.wake" = "GEVENT_22" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index d0d47aae030..531df37b536 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -109,8 +109,7 @@ chip soc/amd/picasso chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" - register "wake" = "GEVENT_22" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)" register "detect" = "1" device i2c 15 on end end diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb index 1641472522a..850b56e175e 100644 --- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb +++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/broadwell + register "ec_present" = "true" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/hp/elitebook_820_g2/pei_data.c b/src/mainboard/hp/elitebook_820_g2/pei_data.c index a31f2112ccc..8fd53d5cfd2 100644 --- a/src/mainboard/hp/elitebook_820_g2/pei_data.c +++ b/src/mainboard/hp/elitebook_820_g2/pei_data.c @@ -9,33 +9,32 @@ void mb_get_spd_map(struct spd_info *spdi) spdi->addresses[2] = 0x52; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->ec_present = 1; - +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P1 */ - pei_data_usb2_port(pei_data, 0, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P2: left side port, USB debug */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P3: digitizer and right side ports (Microchip hub) */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P4: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P5: fingerprint reader */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P6: WWAN */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P7: webcam */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P8 */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1 */ - pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P2: left side, USB debug */ - pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P3: right side (Microchip hub) */ - pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P4 */ - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} + { 1, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c index bb182285488..b1228d8723d 100644 --- a/src/mainboard/ibm/sbp1/bootblock.c +++ b/src/mainboard/ibm/sbp1/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 5451156ad15..d3d8de80b81 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -172,7 +172,7 @@ chip soc/intel/alderlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 6886babeb2e..f0177def69d 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -134,7 +134,7 @@ chip soc/intel/alderlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 5207d553a91..4c77eac8bd9 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -109,7 +109,7 @@ chip soc/intel/alderlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/intel/archercity_crb/bootblock.c b/src/mainboard/intel/archercity_crb/bootblock.c index b781b6b0e30..e61a4da45ff 100644 --- a/src/mainboard/intel/archercity_crb/bootblock.c +++ b/src/mainboard/intel/archercity_crb/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index ae8212a8dd1..d3d830baca5 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 82735c65566..025e053b383 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,6 +38,7 @@ chip northbridge/intel/pineview # Northbridge #device pci 1e.2 off end # AC'97 Audio (not on nm10?) #device pci 1e.3 off end # AC'97 Modem (not on nm10?) device pci 1f.0 on # ISA bridge + register "gen2_dec" = "0x007c0291" chip superio/winbond/w83627thg # Super I/O device pnp 4e.0 off end # Floppy device pnp 4e.1 on # Parallel port diff --git a/src/mainboard/intel/d510mo/early_init.c b/src/mainboard/intel/d510mo/early_init.c index f5bab8dd845..0025a8f4dee 100644 --- a/src/mainboard/intel/d510mo/early_init.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -19,8 +19,6 @@ void bootblock_mainboard_early_init(void) | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 732c39604d8..00a8b70da66 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 4b95f52b36b..e94ab6a1934 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/jasperlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -53,9 +51,6 @@ chip soc/intel/jasperlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # Skip the CPU replacement check - register "SkipCpuReplacementCheck" = "1" - register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" @@ -234,8 +229,6 @@ chip soc/intel/jasperlake end device ref south_xhci on chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB3/2 Type-A Left Lower"" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 995e765fffe..8f31f8dc9d5 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -109,7 +109,7 @@ chip soc/intel/meteorlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/nuc_golden_lake/Kconfig similarity index 64% rename from src/mainboard/intel/dcp847ske/Kconfig rename to src/mainboard/intel/nuc_golden_lake/Kconfig index 07e26e8e296..bc0f1854e9c 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/nuc_golden_lake/Kconfig @@ -1,20 +1,23 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_INTEL_DCP847SKE - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE +config BOARD_INTEL_NUC_GOLDEN_LAKE_COMMON + def_bool n select BOARD_ROMSIZE_KB_8192 - select SUPERIO_NUVOTON_NCT6776 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select SERIRQ_CONTINUOUS_MODE select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6776 + +config BOARD_INTEL_DCP847SKE + select BOARD_INTEL_NUC_GOLDEN_LAKE_COMMON + select AZALIA_USE_LEGACY_VERB_TABLE + +if BOARD_INTEL_NUC_GOLDEN_LAKE_COMMON menu "Debugging" @@ -29,18 +32,16 @@ config DISABLE_UART_ON_TESTPADS endmenu config MAINBOARD_DIR - default "intel/dcp847ske" + default "intel/nuc_golden_lake" config MAINBOARD_PART_NUMBER - default "Intel NUC DCP847SKE" + default "NUC DCP847SKE" if BOARD_INTEL_DCP847SKE -config VGA_BIOS_ID - string - default "8086,0106" +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 2 +config VARIANT_DIR + default "dcp847ske" if BOARD_INTEL_DCP847SKE config USBDEBUG_HCD_INDEX int @@ -55,6 +56,6 @@ config MAINBOARD_SMBIOS_MANUFACTURER config MAINBOARD_SMBIOS_PRODUCT_NAME string - default "DCP847SKE" + default "DCP847SKE" if BOARD_INTEL_DCP847SKE -endif # BOARD_INTEL_DCP847SKE +endif # BOARD_INTEL_NUC_GOLDEN_LAKE_COMMON diff --git a/src/mainboard/intel/dcp847ske/Kconfig.name b/src/mainboard/intel/nuc_golden_lake/Kconfig.name similarity index 100% rename from src/mainboard/intel/dcp847ske/Kconfig.name rename to src/mainboard/intel/nuc_golden_lake/Kconfig.name diff --git a/src/mainboard/intel/nuc_golden_lake/Makefile.mk b/src/mainboard/intel/nuc_golden_lake/Makefile.mk new file mode 100644 index 00000000000..8e7a4ded779 --- /dev/null +++ b/src/mainboard/intel/nuc_golden_lake/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_southbridge.c +romstage-y += early_southbridge.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dcp847ske/acpi/ec.asl b/src/mainboard/intel/nuc_golden_lake/acpi/ec.asl similarity index 100% rename from src/mainboard/intel/dcp847ske/acpi/ec.asl rename to src/mainboard/intel/nuc_golden_lake/acpi/ec.asl diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/nuc_golden_lake/acpi/platform.asl similarity index 100% rename from src/mainboard/intel/dcp847ske/acpi/platform.asl rename to src/mainboard/intel/nuc_golden_lake/acpi/platform.asl diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/nuc_golden_lake/acpi/superio.asl similarity index 100% rename from src/mainboard/intel/dcp847ske/acpi/superio.asl rename to src/mainboard/intel/nuc_golden_lake/acpi/superio.asl diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/nuc_golden_lake/acpi_tables.c similarity index 100% rename from src/mainboard/intel/dcp847ske/acpi_tables.c rename to src/mainboard/intel/nuc_golden_lake/acpi_tables.c diff --git a/src/mainboard/intel/dcp847ske/board_info.txt b/src/mainboard/intel/nuc_golden_lake/board_info.txt similarity index 100% rename from src/mainboard/intel/dcp847ske/board_info.txt rename to src/mainboard/intel/nuc_golden_lake/board_info.txt diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/nuc_golden_lake/devicetree.cb similarity index 77% rename from src/mainboard/intel/dcp847ske/devicetree.cb rename to src/mainboard/intel/nuc_golden_lake/devicetree.cb index 954f572b312..5d21afb308e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/nuc_golden_lake/devicetree.cb @@ -1,7 +1,4 @@ chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -11,13 +8,10 @@ chip northbridge/intel/sandybridge # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # 1333MHz RAM frequency - register "max_mem_clock_mhz" = "666" register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on device ref host_bridge on end # Host bridge - device ref peg10 off end # PCIe Bridge for discrete graphics device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -44,24 +38,12 @@ chip northbridge/intel/sandybridge {0, 1, 6} }" - device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet - device ref ehci2 off end # USB2 EHCI #2 device ref hda on end # HD Audio controller - device ref pcie_rp1 on end # PCIe Port #1 (unused) device ref pcie_rp2 on end # PCIe Port #2 (full-length mPCIe/mSATA) device ref pcie_rp3 on end # PCIe Port #3 (half-length mPCIe) - device ref pcie_rp4 off end # PCIe Port #4 - device ref pcie_rp5 off end # PCIe Port #5 - device ref pcie_rp6 off end # PCIe Port #6 - device ref pcie_rp7 off end # PCIe Port #7 - device ref pcie_rp8 off end # PCIe Port #8 device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy @@ -105,8 +87,6 @@ chip northbridge/intel/sandybridge end device ref sata1 on end # SATA Controller 1 device ref smbus on end # SMBus - device ref sata2 off end # SATA Controller 2 - device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/nuc_golden_lake/dsdt.asl similarity index 100% rename from src/mainboard/intel/dcp847ske/dsdt.asl rename to src/mainboard/intel/nuc_golden_lake/dsdt.asl diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/nuc_golden_lake/early_southbridge.c similarity index 100% rename from src/mainboard/intel/dcp847ske/early_southbridge.c rename to src/mainboard/intel/nuc_golden_lake/early_southbridge.c diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/nuc_golden_lake/gma-mainboard.ads similarity index 100% rename from src/mainboard/intel/dcp847ske/gma-mainboard.ads rename to src/mainboard/intel/nuc_golden_lake/gma-mainboard.ads diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/nuc_golden_lake/mainboard.c similarity index 100% rename from src/mainboard/intel/dcp847ske/mainboard.c rename to src/mainboard/intel/nuc_golden_lake/mainboard.c diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/nuc_golden_lake/romstage.c similarity index 100% rename from src/mainboard/intel/dcp847ske/romstage.c rename to src/mainboard/intel/nuc_golden_lake/romstage.c diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/nuc_golden_lake/smihandler.c similarity index 100% rename from src/mainboard/intel/dcp847ske/smihandler.c rename to src/mainboard/intel/nuc_golden_lake/smihandler.c diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/nuc_golden_lake/superio.h similarity index 100% rename from src/mainboard/intel/dcp847ske/superio.h rename to src/mainboard/intel/nuc_golden_lake/superio.h diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/nuc_golden_lake/thermal.h similarity index 100% rename from src/mainboard/intel/dcp847ske/thermal.h rename to src/mainboard/intel/nuc_golden_lake/thermal.h diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/gpio.c similarity index 100% rename from src/mainboard/intel/dcp847ske/gpio.c rename to src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/gpio.c diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/hda_verb.c similarity index 100% rename from src/mainboard/intel/dcp847ske/hda_verb.c rename to src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/hda_verb.c diff --git a/src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/overridetree.cb b/src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/overridetree.cb new file mode 100644 index 00000000000..f6cd0bc9599 --- /dev/null +++ b/src/mainboard/intel/nuc_golden_lake/variants/dcp847ske/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # 1333MHz RAM frequency (Celeron 847) + register "max_mem_clock_mhz" = "666" + + device domain 0 on + chip southbridge/intel/bd82x6x + device ref pcie_rp1 on end # PCIe Port #1 + end + end +end diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index b864da6c05f..1fc1e250c8a 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -100,7 +100,7 @@ chip soc/intel/alderlake }" # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index 6c7ebd6bb73..5d8c3151fe0 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -9,19 +9,20 @@ void mb_get_spd_map(struct spd_info *spdi) spdi->addresses[2] = 0x51; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, +}; - pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); - pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); - pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP, 0 }, + { 1, USB_OC_PIN_SKIP, 0 }, + { 1, USB_OC_PIN_SKIP, 0 }, + { 1, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/inventec/transformers/bootblock.c b/src/mainboard/inventec/transformers/bootblock.c index b781b6b0e30..e61a4da45ff 100644 --- a/src/mainboard/inventec/transformers/bootblock.c +++ b/src/mainboard/inventec/transformers/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 1d2503a7464..e6d2915bdcf 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 27aa3b53286..041a57b7335 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #if CONFIG(VGA_ROM_RUN) #include diff --git a/src/mainboard/lattepanda/mu/devicetree.cb b/src/mainboard/lattepanda/mu/devicetree.cb index 1db9519084d..dabf07a2f10 100644 --- a/src/mainboard/lattepanda/mu/devicetree.cb +++ b/src/mainboard/lattepanda/mu/devicetree.cb @@ -122,7 +122,7 @@ chip soc/intel/alderlake end device ref hda on # HD Audio - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig index 88037170247..2aa9ff154d2 100644 --- a/src/mainboard/lenovo/haswell/Kconfig +++ b/src/mainboard/lenovo/haswell/Kconfig @@ -8,6 +8,7 @@ config BOARD_LENOVO_HASWELL_COMMON select EC_LENOVO_PMH7 select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_LEDLOGO + select H8_HAS_FNLOCK_LED select H8_HAS_PRIMARY_FN_KEYS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -27,6 +28,7 @@ config BOARD_LENOVO_HASWELL_COMMON config BOARD_LENOVO_THINKPAD_T440P select BOARD_LENOVO_HASWELL_COMMON select INTEL_INT15 + select H8_HAS_BAT_CHARGE_BEHAVIOUR config BOARD_LENOVO_THINKPAD_W541 select BOARD_LENOVO_HASWELL_COMMON diff --git a/src/mainboard/lenovo/haswell/variants/w541/romstage.c b/src/mainboard/lenovo/haswell/variants/w541/romstage.c index 69854dbce45..27a38e00c04 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/w541/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb index b5c02cca0f7..168504ebf38 100644 --- a/src/mainboard/lenovo/m900/devicetree.cb +++ b/src/mainboard/lenovo/m900/devicetree.cb @@ -3,7 +3,7 @@ chip soc/intel/skylake register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 92ef6b8e67e..d3bbc599099 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig index b7cc7056999..bd11ddfd364 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig @@ -10,6 +10,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON select EC_LENOVO_PMH7 select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_LEDLOGO + select H8_HAS_FNLOCK_LED select H8_HAS_PRIMARY_FN_KEYS select H8_SUPPORT_BT_ON_WIFI select HAVE_ACPI_RESUME @@ -47,6 +48,7 @@ config BOARD_LENOVO_T480S config BOARD_LENOVO_T580 bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select DRIVERS_INTEL_DTBT select SOC_INTEL_KABYLAKE select MEC1653_HAS_DEBUG_UNLOCK select VARIANT_HAS_DGPU diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c index 9c0da3c37eb..04c04cf1e0f 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C18, NONE), PAD_NC(GPP_C19, NONE), PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ - PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ + PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ @@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_G1, NONE), PAD_NC(GPP_G2, NONE), PAD_NC(GPP_G3, NONE), - PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ - PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ - PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ + PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ + PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ + PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ }; diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9e056772e93..2eae4730ab8 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -139,8 +139,9 @@ chip northbridge/intel/gm45 register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - register "has_uwb" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" + register "has_uwb" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index d4af8253e63..0bb2118128e 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -117,7 +117,8 @@ chip northbridge/intel/ironlake register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 4e4d4a0d8e9..44f0dcd1a1d 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -130,11 +130,10 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xe2" - register "has_keyboard_backlight" = "0" - register "beepmask0" = "0x02" register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xf0" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4ae67ec3f84..a40dbd63c7e 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -122,11 +122,10 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xe2" - register "has_keyboard_backlight" = "0" - register "beepmask0" = "0x02" register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xf0" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 12fed702fd0..a108be84d8c 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -97,8 +97,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xe2" - register "has_keyboard_backlight" = "1" - register "beepmask0" = "0x00" register "beepmask1" = "0x86" register "has_power_management_beeps" = "0" diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index bc947af2873..389672675f6 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -24,6 +24,8 @@ chip northbridge/intel/sandybridge device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy + register "has_thinklight" = "true" + register "has_keyboard_backlight" = "true" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" end diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index c658a34a4dd..44a0714f78f 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index dae8bc7a2d5..7f5ead828e1 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -54,6 +54,7 @@ chip northbridge/intel/sandybridge register "config0" = "0xa6" register "config1" = "0x09" register "config3" = "0xc0" + register "has_keyboard_backlight" = "1" register "evente_enable" = "0x1d" end end diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 9456f85bd4a..7e155564dc8 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -122,7 +122,8 @@ chip northbridge/intel/sandybridge register "beepmask0" = "0x00" register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "false" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 198d603ff75..221d1de422b 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 3ca79999f17..100089e17f7 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -98,11 +98,12 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xc2" - register "has_keyboard_backlight" = "1" + register "has_thinklight" = "true" + register "has_keyboard_backlight" = "true" register "beepmask0" = "0x00" register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" + register "has_power_management_beeps" = "false" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index d9826608563..e488ee37535 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb index 72cc6b54e15..d12035b1b52 100644 --- a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb @@ -43,7 +43,6 @@ chip northbridge/intel/sandybridge register "wwan_gpio_lvl" = "0" register "config1" = "0x01" register "config3" = "0xe2" - register "has_keyboard_backlight" = "0" register "beepmask0" = "0x02" register "has_power_management_beeps" = "1" register "event4_enable" = "0xf0" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 25782e97e06..0635adfe38b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -127,7 +127,8 @@ chip northbridge/intel/i945 register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index dfd11d566cb..e2055e719b4 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -97,8 +97,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0x62" - register "has_keyboard_backlight" = "0" - register "beepmask0" = "0x00" register "beepmask1" = "0x87" register "has_power_management_beeps" = "0" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 2d6ea772147..ee95371883b 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -128,8 +128,9 @@ chip northbridge/intel/gm45 register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - register "has_uwb" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" + register "has_uwb" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 5b6746b718b..7429d0b12b7 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -125,7 +125,8 @@ chip northbridge/intel/ironlake register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/x220/cfr.c b/src/mainboard/lenovo/x220/cfr.c index e37464a07af..727fc5eff76 100644 --- a/src/mainboard/lenovo/x220/cfr.c +++ b/src/mainboard/lenovo/x220/cfr.c @@ -38,7 +38,6 @@ static struct sm_obj_form ec = { &battery_beep, &fn_ctrl_swap, &sticky_fn, - &f1_to_f12_as_primary, &touchpad, &trackpoint, NULL diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 0ca9bcc6a3b..5eacc5ce699 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -120,8 +120,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0x60" - register "has_keyboard_backlight" = "0" - register "beepmask0" = "0x00" register "beepmask1" = "0x86" register "has_power_management_beeps" = "1" diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 1134782675d..649378c3a6d 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -35,5 +35,8 @@ DefinitionBlock( } #include + + #if CONFIG(BOARD_LENOVO_X220) || CONFIG(BOARD_LENOVO_X220I) #include + #endif } diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index cb1d1253595..190c3d9f969 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -51,6 +51,8 @@ chip northbridge/intel/sandybridge register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" + + register "has_keyboard_backlight" = "1" end end end diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 7aed10d4bf8..79ad6135d0f 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -21,6 +21,7 @@ chip northbridge/intel/sandybridge device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy + register "has_thinklight" = "true" register "eventa_enable" = "0x01" register "eventb_enable" = "0xf0" end diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 9b35477c5bf..b7eac3bc535 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_BAT_CHARGE_BEHAVIOUR if BOARD_LENOVO_X230 select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S select H8_HAS_WWAN_GPIO_DETECTION if !BOARD_LENOVO_X230S select NO_UART_ON_SUPERIO diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 735ce4d9d93..9073b22476c 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -101,8 +101,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xe0" - register "has_keyboard_backlight" = "1" - register "beepmask0" = "0x00" register "beepmask1" = "0x86" register "has_power_management_beeps" = "0" diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 1134782675d..5b046ed4fe2 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -35,5 +35,8 @@ DefinitionBlock( } #include + + #if CONFIG(BOARD_LENOVO_X230) || CONFIG(BOARD_LENOVO_X230_EDP) #include + #endif } diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index 1a226faebd2..ac44cfc7df0 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/sandybridge device ref lpc on chip ec/lenovo/h8 register "eventa_enable" = "0x01" + register "has_thinklight" = "true" + register "has_keyboard_backlight" = "true" device pnp ff.2 on end end end diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230_edp/overridetree.cb new file mode 100644 index 00000000000..cf400d1dd41 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230_edp/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device ref lpc on + chip ec/lenovo/h8 + register "has_thinklight" = "true" + register "has_keyboard_backlight" = "true" + end + end + end + end +end diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 86c2e16e7d6..f6c12b1af9f 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -40,6 +40,7 @@ chip northbridge/intel/sandybridge register "config3" = "0xc4" register "event5_enable" = "0x3c" register "evente_enable" = "0x1d" + register "has_keyboard_backlight" = "1" device pnp ff.2 on end end end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 7f28bbae499..ed9c3e61102 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -115,7 +115,8 @@ chip northbridge/intel/i945 register "beepmask0" = "0xfe" register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" register "event2_enable" = "0xff" register "event3_enable" = "0xff" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 827f0c643dc..524bca7ac63 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -38,6 +38,7 @@ DefinitionBlock( } #include + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 238d9490027..0a52a04f6ad 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lenovo/x61/Kconfig b/src/mainboard/lenovo/x61/Kconfig new file mode 100644 index 00000000000..7b66a98e9b9 --- /dev/null +++ b/src/mainboard/lenovo/x61/Kconfig @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_X61 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_M + select NORTHBRIDGE_INTEL_GM965 + select SOUTHBRIDGE_INTEL_I82801HX + select DRIVERS_I2C_CK505 + select SOUTHBRIDGE_RICOH_RL5C476 + select SUPERIO_NSC_PC87382 + select SUPERIO_NSC_PC87392 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVER_LENOVO_SERIALS + select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BDC_GPIO_DETECTION + #select HAVE_OPTION_TABLE + select INTEL_INT15 + #select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select DRIVERS_LENOVO_WACOM + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + +config CBFS_SIZE + default 0x180000 # size of the BIOS region + +config VBOOT_SLOTS_RW_A + default y + +config MAINBOARD_DIR + default "lenovo/x61" + +config MAINBOARD_PART_NUMBER + default "ThinkPad X61" + +config MAX_CPUS + int + default 2 + +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "IBM3780" + +endif diff --git a/src/mainboard/lenovo/x61/Kconfig.name b/src/mainboard/lenovo/x61/Kconfig.name new file mode 100644 index 00000000000..37d3e8483a9 --- /dev/null +++ b/src/mainboard/lenovo/x61/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_X61 + bool "ThinkPad X61 / X61s" diff --git a/src/mainboard/lenovo/x61/Makefile.mk b/src/mainboard/lenovo/x61/Makefile.mk new file mode 100644 index 00000000000..8a0a35e58b9 --- /dev/null +++ b/src/mainboard/lenovo/x61/Makefile.mk @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +smm-y += dock.c +bootblock-y += dock.c +romstage-y += dock.c +ramstage-y += dock.c +ramstage-y += mainboard.c +ramstage-y += cstates.c +ramstage-y += hda_verb.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c +#romstage-y += romstage.c diff --git a/src/mainboard/lenovo/x61/acpi/dock.asl b/src/mainboard/lenovo/x61/acpi/dock.asl new file mode 100644 index 00000000000..24371c9aec6 --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/dock.asl @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "smi.h" + +Scope (\_SB) +{ + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } + + Device(DOCK) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Local0 = Arg0 ^ DSTA + Return (Local0) + } + + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } + } +} + +Scope(\_SB.PCI0.LPCB.EC) +{ + /* + * Vendor DSDT event mapping: + * _Q18 is HKEY hotkey 0x1009, Fn+F9, not a dock event. + * _Q37 and _Q58 are dock attach events. + * _Q50 is an undock request from the dock eject button. + */ + Method(_Q18, 0, NotSerialized) + { + ^HKEY.RHK(0x09) + } + + Method(_Q37, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } + + Method(_Q50, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q58, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } + +} diff --git a/src/mainboard/lenovo/x61/acpi/ec.asl b/src/mainboard/lenovo/x61/acpi/ec.asl new file mode 100644 index 00000000000..7e96ed79a09 --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/lenovo/x61/acpi/gpe.asl b/src/mainboard/lenovo/x61/acpi/gpe.asl new file mode 100644 index 00000000000..d607c380ab5 --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/gpe.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * ThinkPad X61 General Purpose Event handlers + * + * _L18 fires on GPIO8 (H8_WAKE#, routed to GPE bit 24 via gpi8_routing=SCI). + * It reads the 16-bit EC wake-status register and notifies the appropriate + * ACPI devices. Bit meanings match the ThinkPad H8 EC protocol: + * + * bit 1 (0x02) - ring indicator wakeup (no ACPI device to notify) + * bit 2 (0x04) - lid opened + * bit 3 (0x08) - dock event + * bit 4 (0x10) - power/sleep button + * bit 7 (0x80) - AC adapter status change or other wake + * + * Device paths under coreboot's ACPI namespace: + * LID -> \_SB.PCI0.LPCB.EC.LID (defined in ec/lenovo/h8/acpi/lid.asl) + * SLPB -> \_SB.PCI0.LPCB.EC.SLPB (defined in ec/lenovo/h8/acpi/sleepbutton.asl) + * DOCK -> \_SB.DOCK (defined in acpi/dock.asl) + */ + +Scope (\_GPE) +{ + /* + * _L18 - EC wake event (GPIO8 / H8_WAKE#, level-triggered SCI) + * + * Read and dispatch the EC wake source register. The EC clears the + * register after it is read. + */ + Method (_L18, 0, NotSerialized) + { + Local0 = \_SB.PCI0.LPCB.EC.WAKE + + /* bit 2: Lid opened - wake the system via the lid device */ + If ((Local0 & 0x04)) { + Notify (\_SB.PCI0.LPCB.EC.LID, 0x02) // Device Wake + } + + /* bit 3: Dock connect/disconnect event */ + If ((Local0 & 0x08)) { + Notify (\_SB.DOCK, 0x03) // Dock-specific + Notify (\_SB.PCI0.LPCB.EC.SLPB, 0x02) // Device Wake + } + + /* bit 4: Power/sleep button */ + If ((Local0 & 0x10)) { + Notify (\_SB.PCI0.LPCB.EC.SLPB, 0x02) // Device Wake + } + + /* bit 7: Generic wake (AC status change, timer, etc.) */ + If ((Local0 & 0x80)) { + Notify (\_SB.PCI0.LPCB.EC.SLPB, 0x02) // Device Wake + } + } +} diff --git a/src/mainboard/lenovo/x61/acpi/ich8_pci_irqs.asl b/src/mainboard/lenovo/x61/acpi/ich8_pci_irqs.asl new file mode 100644 index 00000000000..495f9e86190 --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/ich8_pci_irqs.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH8. + * + * Bus 05 (secondary) holds the Ricoh multifunction device (device 0): + * 05:00.0 Ricoh RL5c476 II CardBus bridge (INT A) + * 05:00.1 Ricoh R5C832 FireWire controller (INT B) + * 05:00.2 Ricoh R5C822 SD host adapter (INT C) + * + * Additional device numbers (1, 2, 8) appear when an UltraBase dock + * is attached. Routing matches the vendor BIOS APRT/LPRT tables. + */ +If (PICM) { + Return (Package() { + // Ricoh multifunction device (device 0) + Package() { 0x0000ffff, 0, 0, 16}, + Package() { 0x0000ffff, 1, 0, 17}, + Package() { 0x0000ffff, 2, 0, 18}, + Package() { 0x0000ffff, 3, 0, 19}, + + // Dock device 1 + Package() { 0x0001ffff, 0, 0, 16}, + + // Dock device 2 (two functions) + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + + // Dock device 8 + Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + // Ricoh multifunction device (device 0) + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // Dock device 1 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + // Dock device 2 (two functions) + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + + // Dock device 8 + Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/lenovo/x61/acpi/platform.asl b/src/mainboard/lenovo/x61/acpi/platform.asl new file mode 100644 index 00000000000..fb6661801cc --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/platform.asl @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * ThinkPad X61 platform sleep/wake hooks + * + * _PTS (Prepare To Sleep) - called by the OS before entering a sleep state. + * _WAK (Wake) - called by the OS after resuming from sleep. + * + * Vendor BIOS reference: Phoenix BIOS TP-7N DSDT _PTS / _WAK methods. + * + * EC method availability (ec/lenovo/h8/acpi/ec.asl): + * MUTE(n) - audio mute (n=1 mute, n=0 unmute) + * USBP(n) - USB power (n=0 disable, n=1 enable) + * RADI(n) - wireless radios (n=0 off, n=1 on) + * + * HKEY method availability (ec/lenovo/h8/acpi/thinkpad.asl): + * MHKC(n) - enable (n=1) / disable (n=0) all HKEY hotkey events + * WAKE(n) - re-initialise BT/WWAN state after wake (called with sleep type) + */ + +/* + * _PTS - Prepare To Sleep + * Arg0: target sleep state (1=S1, 3=S3, 4=S4, 5=S5) + */ +Method (_PTS, 1) +{ + /* Mute audio to avoid pops on suspend */ + \_SB.PCI0.LPCB.EC.MUTE (1) + + /* Disable USB bus power during sleep */ + \_SB.PCI0.LPCB.EC.USBP (0) + + /* Turn off wireless radios */ + \_SB.PCI0.LPCB.EC.RADI (0) + + /* Disable HKEY hotkey events to prevent spurious wakes */ + \_SB.PCI0.LPCB.EC.HKEY.MHKC (0) +} + +/* + * _WAK - System Wake + * Arg0: sleep state we are resuming from + */ +Method (_WAK, 1) +{ + /* Re-enable HKEY hotkey events */ + \_SB.PCI0.LPCB.EC.HKEY.MHKC (1) + + /* Re-initialise BT/WWAN radio state (restores pre-sleep radio enables) */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + Return (Package () { 0, 0 }) +} + +/* ------------------------------------------------------------------ */ +/* System Bus - _INI */ +/* ------------------------------------------------------------------ */ + +Scope (\_SB) +{ + /* + * Placed at the top level so it runs first, before any device _INI. + * Calls \GOS() to detect the running OS and set OS-compatibility flags + * used by other ACPI methods. + */ + Method (_INI, 0) + { + \GOS () + } +} diff --git a/src/mainboard/lenovo/x61/acpi/superio.asl b/src/mainboard/lenovo/x61/acpi/superio.asl new file mode 100644 index 00000000000..c37cf39f868 --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi/superio.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Dock Super I/O devices. */ +Device (DSIO) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 0x02) + + Method (_STA, 0, NotSerialized) + { + If (\_SB.DOCK._STA ()) { + Return (0x0f) + } + + Return (0x00) + } + + Device (DURT) + { + Name (_HID, EISAID("PNP0501")) + Name (_UID, 0x01) + Name (_EJD, "_SB.DOCK") + + Method (_STA, 0, NotSerialized) + { + If (\_SB.DOCK._STA ()) { + Return (0x0f) + } + + Return (0x00) + } + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) + IRQNoFlags () { 4 } + }) + } + + Device (DLPT) + { + Name (_HID, EISAID("PNP0400")) + Name (_UID, 0x01) + Name (_EJD, "_SB.DOCK") + + Method (_STA, 0, NotSerialized) + { + If (\_SB.DOCK._STA ()) { + Return (0x0f) + } + + Return (0x00) + } + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03bc, 0x03bc, 0x01, 0x03) + IRQNoFlags () { 7 } + }) + } +} diff --git a/src/mainboard/lenovo/x61/acpi_tables.c b/src/mainboard/lenovo/x61/acpi_tables.c new file mode 100644 index 00000000000..8f4f83b826e --- /dev/null +++ b/src/mainboard/lenovo/x61/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/x61/board_info.txt b/src/mainboard/lenovo/x61/board_info.txt new file mode 100644 index 00000000000..73c788fea68 --- /dev/null +++ b/src/mainboard/lenovo/x61/board_info.txt @@ -0,0 +1,7 @@ +Board name: ThinkPad X61/X61s +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2007 diff --git a/src/mainboard/lenovo/x61/cstates.c b/src/mainboard/lenovo/x61/cstates.c new file mode 100644 index 00000000000..c5f4840c8e4 --- /dev/null +++ b/src/mainboard/lenovo/x61/cstates.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const acpi_cstate_t cst_entries[] = { + { + /* ACPI C1 / CPU C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0 } + }, + { + /* ACPI C2 / CPU C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x10, 0 } + }, + { + /* ACPI C3 / CPU C3 */ + 3, 0x37, 250, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x20, 0 } + }, +}; + +int get_cst_entries(const acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/lenovo/x61/data.vbt b/src/mainboard/lenovo/x61/data.vbt new file mode 100644 index 00000000000..f27f843aaf5 Binary files /dev/null and b/src/mainboard/lenovo/x61/data.vbt differ diff --git a/src/mainboard/lenovo/x61/devicetree.cb b/src/mainboard/lenovo/x61/devicetree.cb new file mode 100644 index 00000000000..443efce0fa5 --- /dev/null +++ b/src/mainboard/lenovo/x61/devicetree.cb @@ -0,0 +1,209 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/gm965 + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + device cpu_cluster 0 on ops gm965_cpu_bus_ops end # APIC cluster + + device domain 0 on + ops gm965_pci_domain_ops + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x20b5 + end + device pci 02.0 on # VGA controller + subsystemid 0x17aa 0x20b5 + end + device pci 02.1 on # Display controller + subsystemid 0x17aa 0x20b5 + end + chip southbridge/intel/i82801hx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + register "gpi8_routing" = "2" + register "gpi2_routing" = "2" + + # mainboard.c sets this to true in case dock is found + # register "ide_enable_primary" = "true" + + register "sata_port_map" = "0x01" + + register "gpe0_en" = "0x01040046" + register "alt_gp_smi_en" = "0x0000" + + # Set c-state support + register "c4onc3_enable" = "1" + + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" + + device pci 19.0 on end # GbE LAN + device pci 1a.0 on # UHCI #4 + subsystemid 0x17aa 0x20b0 + end + device pci 1a.1 on # UHCI #5 + subsystemid 0x17aa 0x20b0 + end + device pci 1a.7 on # EHCI #2 + subsystemid 0x17aa 0x20b1 + end + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x20b2 + end + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 on end # PCIe port 2 (WLAN) + device pci 1c.2 off end # PCIe port 3 (not populated) + device pci 1c.3 off end # PCIe port 4 (not populated) + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 + + device pci 1d.0 on # UHCI #1 + subsystemid 0x17aa 0x20b0 + end + device pci 1d.1 on # UHCI #2 + subsystemid 0x17aa 0x20b0 + end + device pci 1d.2 on # UHCI #3 + subsystemid 0x17aa 0x20b0 + end + device pci 1d.7 on # EHCI #1 + subsystemid 0x17aa 0x20b1 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ricoh/rl5c476 + device pci 0.0 on end + end + end + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x20b6 + chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy + register "backlight_enable" = "true" + register "dock_event_enable" = "true" + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x01" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_thinklight" = "true" + register "has_power_management_beeps" = "true" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87382 + device pnp 164e.2 on # IR + io 0x60 = 0x2f8 + end + + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + + device pnp 164e.7 on # GPIO + io 0x60 = 0x1680 + end + + device pnp 164e.19 on # DLPC + io 0x60 = 0x164c + end + end + + chip superio/nsc/pc87392 + device pnp 2e.0 off end #FDC + + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x3bc + irq 0x70 = 7 + end + + device pnp 2e.2 off # Serial Port / IR + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + + device pnp 2e.3 on # Serial Port + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.7 on # GPIO + io 0x60 = 0x1620 + end + + device pnp 2e.a off end # WDT + end + end + device pci 1f.1 on end # IDE controller (UltraBay, primary channel) + device pci 1f.2 on # SATA + subsystemid 0x17aa 0x20b8 + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x20b9 + chip drivers/i2c/ck505 + register "nregs" = "1" + register "mask" = "{ 0xff }" + register "regs" = "{ 0x11 }" + device i2c 69 on end + end + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA/IDE 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/x61/dock.c b/src/mainboard/lenovo/x61/dock.c new file mode 100644 index 00000000000..c1890163851 --- /dev/null +++ b/src/mainboard/lenovo/x61/dock.c @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ +#include +#include +#include +#include +#include +#include +#include "dock.h" +#include +#include +#include + +static const pnp_devfn_t dlpc_dev = PNP_DEV(0x164e, PC87382_DOCK); +static const pnp_devfn_t dlpc_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t dock_gpio = PNP_DEV(0x2e, PC87392_GPIO); +static const pnp_devfn_t dock_parallel = PNP_DEV(0x2e, PC87392_PP); +static const pnp_devfn_t dock_serial = PNP_DEV(0x2e, PC87392_SP1); + +static void select_logical_device(pnp_devfn_t dev) +{ + pnp_write_config(dev, 0x07, dev & 0xff); +} + +static void dlpc_gpio_set_mode(int port, int mode) +{ + pnp_write_config(dlpc_gpio, 0xf0, port); + pnp_write_config(dlpc_gpio, 0xf1, mode); +} + +static void dock_gpio_set_mode(int port, int mode, int irq) +{ + pnp_write_config(dock_gpio, 0xf0, port); + pnp_write_config(dock_gpio, 0xf1, mode); + pnp_write_config(dock_gpio, 0xf2, irq); +} + +static void dock_set_usb_power(bool enable) +{ + if (enable) { + outb(inb(0x1628) | 0x02, 0x1628); + ec_set_bit(H8_CONFIG2, 0); + } else { + outb(inb(0x1628) & ~0x02, 0x1628); + ec_clr_bit(H8_CONFIG2, 0); + } +} + +static void dock_set_ultrabay_power(bool enable) +{ + if (enable) + outb(inb(0x1628) | 0x01, 0x1628); + else + outb(inb(0x1628) & ~0x01, 0x1628); +} + +static void dlpc_gpio_init(void) +{ + select_logical_device(dlpc_gpio); + pnp_set_iobase(dlpc_gpio, PNP_IDX_IO0, 0x1680); + pnp_set_enable(dlpc_gpio, 1); + + dlpc_gpio_set_mode(0x00, 3); + dlpc_gpio_set_mode(0x01, 3); + dlpc_gpio_set_mode(0x02, 0); + dlpc_gpio_set_mode(0x03, 3); + dlpc_gpio_set_mode(0x04, 4); + dlpc_gpio_set_mode(0x20, 4); + dlpc_gpio_set_mode(0x21, 4); + dlpc_gpio_set_mode(0x23, 4); +} + +int dlpc_init(void) +{ + int timeout = 1000; + + /* Enable 14.318MHz CLK on CLKIN */ + pnp_write_config(dlpc_gpio, 0x29, 0xa0); + while (!(pnp_read_config(dlpc_gpio, 0x29) & 0x10) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + select_logical_device(dlpc_dev); + pnp_set_iobase(dlpc_dev, PNP_IDX_IO0, 0x164c); + pnp_set_enable(dlpc_dev, 1); + + dlpc_gpio_init(); + + return 0; +} + +int dock_connect(void) +{ + int timeout = 1000; + + /* Start from the vendor state: dock reset asserted, DLPC powered down. */ + outb(inb(0x1680) & 0xfc, 0x1680); + + outb(0x07, 0x164c); + + timeout = 1000; + + while (!(inb(0x164c) & 8) && timeout--) + udelay(1000); + + if (!timeout) { + /* docking failed, disable DLPC switch */ + outb(0x00, 0x164c); + select_logical_device(dlpc_dev); + pnp_set_enable(dlpc_dev, 0); + return 1; + } + + /* Power up DLPC while keeping D_PLTRST# asserted. */ + outb((inb(0x1680) & 0xfe) | 0x02, 0x1680); + mdelay(100); + /* Deassert D_PLTRST#. */ + outb(inb(0x1680) | 0x03, 0x1680); + + mdelay(100); + + /* startup 14.318MHz Clock */ + pnp_write_config(dock_gpio, 0x29, 0x06); + /* wait until clock is settled */ + timeout = 1000; + while (!(pnp_read_config(dock_gpio, 0x29) & 0x08) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Pin 6: CLKRUN + * Pin 72: #DR1 + * Pin 19: #SMI + * Pin 73: #MTR + */ + pnp_write_config(dock_gpio, 0x24, 0x37); + + /* PNF active HIGH */ + pnp_write_config(dock_gpio, 0x25, 0xa0); + + /* disable FDC */ + pnp_write_config(dock_gpio, 0x26, 0x01); + + /* Enable GPIO IRQ to #SMI */ + pnp_write_config(dock_gpio, 0x28, 0x02); + + select_logical_device(dock_gpio); + pnp_set_iobase(dock_gpio, PNP_IDX_IO0, 0x1620); + + /* init GPIO pins */ + dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP | PC87392_GPIO_PIN_DEBOUNCE, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + + /* enable GPIO */ + pnp_set_enable(dock_gpio, 1); + + /* Enable UltraBay power if a device is present, preserving other dock power bits. */ + dock_set_ultrabay_power(dock_ultrabay_device_present()); + + outb(0x00, 0x1623); + outb(0x82, 0x1622); + outb(inb(0x1624) | 0x40, 0x1624); + + /* Enable dock USB power and mirror slice/dock state into the EC. */ + dock_set_usb_power(true); + + select_logical_device(dock_parallel); + pnp_set_iobase(dock_parallel, PNP_IDX_IO0, 0x3bc); + pnp_set_irq(dock_parallel, PNP_IDX_IRQ0, 7); + pnp_set_enable(dock_parallel, 1); + + select_logical_device(dock_serial); + pnp_set_iobase(dock_serial, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dock_serial, PNP_IDX_IRQ0, 4); + pnp_set_enable(dock_serial, 1); + return 0; +} + +void dock_disconnect(void) +{ + printk(BIOS_DEBUG, "%s enter\n", __func__); + /* Assert D_PLTRST# and DLPCPD before dropping dock power and LPC. */ + outb(inb(0x1680) & 0xfc, 0x1680); + mdelay(10); + + /* Disable dock USB and UltraBay power. */ + dock_set_usb_power(false); + dock_set_ultrabay_power(false); + udelay(10000); + + /* Disconnect LPC bus. */ + outb(0x00, 0x164c); + + printk(BIOS_DEBUG, "%s finish\n", __func__); +} + +int dock_present(void) +{ + return !((inw(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1); +} + +int dock_ultrabay_device_present(void) +{ + return inb(0x1621) & 0x02 ? 0 : 1; +} diff --git a/src/mainboard/lenovo/x61/dock.h b/src/mainboard/lenovo/x61/dock.h new file mode 100644 index 00000000000..1dd48026860 --- /dev/null +++ b/src/mainboard/lenovo/x61/dock.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef THINKPAD_X61_DOCK_H +#define THINKPAD_X61_DOCK_H + +int dock_connect(void); +void dock_disconnect(void); +int dock_present(void); +int dlpc_init(void); +int dock_ultrabay_device_present(void); +#endif diff --git a/src/mainboard/lenovo/x61/dsdt.asl b/src/mainboard/lenovo/x61/dsdt.asl new file mode 100644 index 00000000000..36f9eea0a14 --- /dev/null +++ b/src/mainboard/lenovo/x61/dsdt.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define THINKPAD_EC_GPE 0x12 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + +#include "smi.h" + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + #include + #include "acpi/platform.asl" + + // global NVS and variables + #include + #include + + // General Purpose Events + #include "acpi/gpe.asl" + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + + #include + } + } + + #include + + // Dock support code + #include "acpi/dock.asl" + + #include +} diff --git a/src/mainboard/lenovo/x61/early_init.c b/src/mainboard/lenovo/x61/early_init.c new file mode 100644 index 00000000000..319e291d201 --- /dev/null +++ b/src/mainboard/lenovo/x61/early_init.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + /* decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), D31F0_LPC_IODEC, 0x0210); +} + +static void early_superio_config(void) +{ + int timeout = 100000; + const pnp_devfn_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); + + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void bootblock_mainboard_early_init(void) +{ + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinkpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) +{ + /* Device interrupt pin registers */ + RCBA32(D31IP) = 0x00001230; + RCBA32(D29IP) = 0x40004321; + RCBA32(D26IP) = 0x30000021; + + /* PCIe Interrupts */ + RCBA32(D28IP) = 0x00004321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000002; + + /* dev irq route register */ + RCBA16(D31IR) = 0x1007; + RCBA16(D30IR) = 0x0076; + RCBA16(D29IR) = 0x3210; + RCBA16(D28IR) = 0x7654; + RCBA16(D27IR) = 0x0010; + RCBA16(D26IR) = 0x0654; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA64(IOTR3) = 0x000200f0000c0801ULL; +} + +void mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x51; +} diff --git a/src/mainboard/lenovo/x61/gpio.c b/src/mainboard/lenovo/x61/gpio.c new file mode 100644 index 00000000000..2fad44c292f --- /dev/null +++ b/src/mainboard/lenovo/x61/gpio.c @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * ThinkPad X61 GPIO configuration. + * + * Verified against inteltool.log from physical hardware running vendor BIOS: + * USE_SEL = 0xf97e03fe IO_SEL = 0xc1ee6dfe LVL = 0xe392ddff + * GPI_INV = 0x000039ff + * USE_SEL2 = 0x00010ef6 IO_SEL2 = 0x005501f1 LVL2 = 0x00fe0373 + * USE_SEL3 = 0x00000000 IO_SEL3 = 0x00000000 LVL3 = 0x00000000 + * + * ICH8M-E GPIO is register-compatible with the ICH7 common GPIO framework. + * For direction: 0 = output, 1 = input (GP_IO_SEL convention). + * GPI_INV inverts the polarity of GPIO inputs for SMI/SCI edge detection. + */ + +#include +#include +#include +#include + +/* ================================================================== */ +/* GPIO Set 1 - GPIO0..31 */ +/* ================================================================== */ + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + /* GPIO0 = native (SATA_GP#) */ + .gpio1 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio2 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio3 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio4 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio5 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio6 = GPIO_MODE_GPIO, /* Input, active low (inverted) */ + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# (Bluetooth), active low */ + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# (EC wakes host), active low */ + .gpio9 = GPIO_MODE_GPIO, /* Output, driven low */ + /* GPIO10-16 = native (USB OC, CLKRUN#, etc.) */ + .gpio17 = GPIO_MODE_GPIO, /* Input */ + .gpio18 = GPIO_MODE_GPIO, /* Input */ + .gpio19 = GPIO_MODE_GPIO, /* Input */ + .gpio20 = GPIO_MODE_GPIO, /* Output, driven high */ + .gpio21 = GPIO_MODE_GPIO, /* Input */ + .gpio22 = GPIO_MODE_GPIO, /* Input */ + /* GPIO23 = native */ + .gpio24 = GPIO_MODE_GPIO, /* Input */ + /* GPIO25-26 = native */ + .gpio27 = GPIO_MODE_GPIO, /* Output, driven low */ + .gpio28 = GPIO_MODE_GPIO, /* Output, driven low */ + .gpio29 = GPIO_MODE_GPIO, /* Output, driven high */ + .gpio30 = GPIO_MODE_GPIO, /* Input */ + .gpio31 = GPIO_MODE_GPIO, /* Input */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + /* Only output GPIOs need explicit level; unset fields default to LOW */ + .gpio20 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + /* gpio9=LOW, gpio27=LOW, gpio28=LOW: default */ +}; + +/* GPI_INV vendor value is 0x000039ff. */ +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, /* BDC_PRESENCE#, active low */ + .gpio8 = GPIO_INVERT, /* H8_WAKE#, active low */ + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +/* ================================================================== */ +/* GPIO Set 2 - GPIO32..63 */ +/* ================================================================== */ + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + /* GPIO32 = native */ + .gpio33 = GPIO_MODE_GPIO, /* HDA_DOCK_EN#, output driven high */ + .gpio34 = GPIO_MODE_GPIO, /* Output, driven low */ + /* GPIO35 = native */ + .gpio36 = GPIO_MODE_GPIO, /* Input */ + .gpio37 = GPIO_MODE_GPIO, /* Input */ + .gpio38 = GPIO_MODE_GPIO, /* Input */ + .gpio39 = GPIO_MODE_GPIO, /* Input */ + /* GPIO40 = native */ + .gpio41 = GPIO_MODE_GPIO, /* Output, driven high */ + .gpio42 = GPIO_MODE_GPIO, /* SMBus mux: HIGH=DIMMs/SPD, LOW=AT24RF08C EEPROM */ + .gpio43 = GPIO_MODE_GPIO, /* Output, driven low */ + /* GPIO44-47 = native */ + .gpio48 = GPIO_MODE_GPIO, /* Input */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + /* + * GPIO42 = SMBus mux: HIGH routes SMBus to DIMMs (for SPD reads), + * LOW routes SMBus to the AT24RF08C EEPROM. + * Start HIGH so raminit can read SPD; mb_post_raminit_setup() will + * switch it LOW afterward, matching the X200/T400 pattern. + */ + .gpio42 = GPIO_LEVEL_HIGH, + /* gpio34=LOW, gpio43=LOW: default */ +}; + +/* ================================================================== */ +/* GPIO map */ +/* ================================================================== */ + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; + +enum smbus_mux { + SMBUS_TO_EEPROM, + SMBUS_TO_CK505_SPD, +}; + +static void set_smbus_mux(enum smbus_mux mux) +{ + switch (mux) + { + default: + case SMBUS_TO_EEPROM: + gpio_set(42, GPIO_LEVEL_LOW); + break; + case SMBUS_TO_CK505_SPD: + gpio_set(42, GPIO_LEVEL_HIGH); + break; + } +} + +void mb_post_raminit_setup(void) +{ + set_smbus_mux(SMBUS_TO_EEPROM); +} + +void mb_pre_ck505_init(void) +{ + set_smbus_mux(SMBUS_TO_CK505_SPD); + +} +void mb_post_ck505_init(void) +{ + set_smbus_mux(SMBUS_TO_EEPROM); +} diff --git a/src/mainboard/lenovo/x61/hda_verb.c b/src/mainboard/lenovo/x61/hda_verb.c new file mode 100644 index 00000000000..88957b5f7d3 --- /dev/null +++ b/src/mainboard/lenovo/x61/hda_verb.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Lenovo ThinkPad X61 - HD Audio (Azalia) Codec Verb Table + * + * Extracted from Phoenix BIOS bioscode_7.rom: + * - Verb table header at file offset 0x2B70 + * - 60 verb dwords at file offset 0x2B7D + * - Codec lookup dispatch at 0x5329 + * - Verb send loop at 0x52D7 + * + * Primary codec: Analog Devices AD1984 + * Vendor/Device ID: 0x11D41984 + * Subsystem ID: 0x17AA20D6 (Lenovo ThinkPad X61) + */ + +#include + +static const u32 ad1984_verbs[] = { + AZALIA_SUBVENDOR(0, 0x17aa20d6), + + /* NID 0x11: Headphone output jack (right side) */ + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 15 + )), + + /* NID 0x12: Internal speaker */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), + + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), + + /* NID 0x14: External mic input jack (right side) */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_RED, + AZALIA_JACK_PRESENCE_DETECT, + 2, 1 + )), + + /* NID 0x15: Internal microphone */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_MIC_IN, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 2, 14 + )), + + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(1)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(2)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(3)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(4)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(5)), + + /* NID 0x1C: Dock mic input */ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_SEPARATE_CHASSIS | AZALIA_REAR, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_RED, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + + /* + * Extra init verbs from BIOS at bioscode_7.rom:0x2C2D + * + * Configure amplifier gains, digital converter modes, + * beep generator, power states, and EAPD. + */ + + /* DAC output amp gains */ + 0x00c3b027, /* NID 0x0C: Set output amp, L+R, gain 39 (~-6dB) */ + 0x00d3b027, /* NID 0x0D: Set output amp, L+R, gain 39 (~-6dB) */ + /* Digital converter - set to 0 (PCM mode) */ + 0x00737100, /* NID 0x07: Set digital converter = 0x00 */ + 0x00a37100, /* NID 0x0A: Set digital converter = 0x00 */ + + /* Beep generator config */ + 0x02037318, /* NID 0x20: Set beep amp, index 3, gain 24 */ + 0x0213b01f, /* NID 0x21: Set output amp, L+R, gain 31 (max) */ + /* Mute HP Out and Speaker output amps initially */ + 0x0113b000, /* NID 0x11: Set output amp, L+R, gain 0 (mute) */ + 0x0123b000, /* NID 0x12: Set output amp, L+R, gain 0 (mute) */ + + /* Power state D0 (fully on) for DACs and ADCs */ + 0x00370500, /* NID 0x03: Set power state D0 */ + 0x00470500, /* NID 0x04: Set power state D0 */ + 0x00570500, /* NID 0x05: Set power state D0 */ + 0x00670500, /* NID 0x06: Set power state D0 */ + + 0x00870500, /* NID 0x08: Set power state D0 */ + 0x00970500, /* NID 0x09: Set power state D0 */ + 0x01970500, /* NID 0x19: Set power state D0 */ + /* EAPD enable on internal speaker */ + 0x01270c02, /* NID 0x12: Set EAPD/BTL enable = 0x02 (EAPD on) */ +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Analog Devices AD1984", + .vendor_id = 0x11d41984, + .subsystem_id = 0x17aa20d6, + .address = 0, + .verbs = ad1984_verbs, + .verb_count = ARRAY_SIZE(ad1984_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x61/mainboard.c b/src/mainboard/lenovo/x61/mainboard.c new file mode 100644 index 00000000000..248185c2c0f --- /dev/null +++ b/src/mainboard/lenovo/x61/mainboard.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" +#include +#include +#include + +static void mainboard_init(struct device *dev) +{ + struct device *idedev, *sdhci_dev; + + ec_clr_bit(0x03, 2); + + if (inb(0x164c) & 0x08) { + ec_set_bit(0x03, 2); + ec_write(0x0c, 0x88); + } + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); + + /* If we're resuming from suspend, blink suspend LED */ + if (acpi_is_wakeup_s3()) + ec_write(0x0c, 0xc7); + + idedev = pcidev_on_root(0x1f, 1); + if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { + struct southbridge_intel_i82801hx_config *config = idedev->chip_info; + config->ide_enable_primary = true; + /* enable Ultrabay power */ + outb(inb(0x1628) | 0x01, 0x1628); + ec_write(0x0c, 0x84); + } else { + /* disable Ultrabay power */ + outb(inb(0x1628) & ~0x01, 0x1628); + ec_write(0x0c, 0x04); + } + + /* Set SDHCI write protect polarity "SDWPPol" */ + sdhci_dev = dev_find_device(PCI_VID_RICOH, PCI_DID_RICOH_R5C822, 0); + if (sdhci_dev) { + if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { + /* unlock */ + pci_write_config8(sdhci_dev, 0xf9, 0xfc); + /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ + pci_write_config8(sdhci_dev, 0xfa, 0x20); + /* restore lock */ + pci_write_config8(sdhci_dev, 0xf9, 0x00); + } + } +} + +static void fill_ssdt(const struct device *device) +{ + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_fill_ssdt = fill_ssdt; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/x61/smi.h b/src/mainboard/lenovo/x61/smi.h new file mode 100644 index 00000000000..6f2964b1445 --- /dev/null +++ b/src/mainboard/lenovo/x61/smi.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_LENOVO_X61_SMI_H +#define MAINBOARD_LENOVO_X61_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 + +#endif diff --git a/src/mainboard/lenovo/x61/smihandler.c b/src/mainboard/lenovo/x61/smihandler.c new file mode 100644 index 00000000000..1608785d0d6 --- /dev/null +++ b/src/mainboard/lenovo/x61/smihandler.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" +#include "smi.h" + +/* + * GPIO2 is H8SCI# (the Embedded Controller SCI signal). + * In ICH8, GPI[n] maps to GPE0_STS bit (n + 16), so GPI2 -> GPE0 bit 18 + * (0x12), matching the EC device _GPE value in the DSDT. + */ +#define GPE_EC_SCI 2 + +static void mainboard_smi_dock_connect(void) +{ + ec_clr_bit(0x03, 2); + mdelay(250); + if (!dock_connect()) { + ec_set_bit(0x03, 2); + /* set dock LED to indicate success */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); + } else { + /* blink dock LED to indicate failure */ + ec_write(0x0c, 0x08); + ec_write(0x0c, 0xc9); + } +} + +static void mainboard_smi_dock_disconnect(void) +{ + ec_clr_bit(0x03, 2); + dock_disconnect(); +} + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case SMI_DOCK_CONNECT: + mainboard_smi_dock_connect(); + break; + case SMI_DOCK_DISCONNECT: + mainboard_smi_dock_disconnect(); + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %#02x\n", event); + + switch (event) { + /* Undock key / power loss / Fn-F9 */ + case 0x18: + case 0x27: + case 0x50: + mainboard_smi_dock_disconnect(); + break; + /* Dock event */ + case 0x37: + case 0x58: + mainboard_smi_dock_connect(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi) +{ + if (gpi & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI# to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all pending events, enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* fall back to port 0x62/0x66 for EC query in SMI */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all pending events, enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/bootblock.c b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c index ff38188368c..c3abbd688a6 100644 --- a/src/mainboard/mitaccomputing/whitestone-2/bootblock.c +++ b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include #include diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 7604776d449..00d1f3f7656 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -6,7 +6,7 @@ chip soc/intel/alderlake # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" @@ -406,7 +406,7 @@ chip soc/intel/alderlake device ref hda on subsystemid 0x1462 0x9d25 register "pch_hda_audio_link_hda_enable" = "1" - register "pch_hda_dsp_enable" = "0" + register "pch_hda_dsp_enable" = "false" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 5885f2ab27b..45fd7aa2385 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -6,7 +6,7 @@ chip soc/intel/alderlake # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb index e45fc99b7ac..f8237aec268 100644 --- a/src/mainboard/novacustom/mtl-h/devicetree.cb +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -10,7 +10,7 @@ chip soc/intel/meteorlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable S0ix / Modern Standby register "s0ix_enable" = "1" @@ -24,7 +24,6 @@ chip soc/intel/meteorlake # Thermal register "tcc_offset" = "10" # TCC of 100C - device cpu_cluster 0 on end device domain 0 on device ref system_agent on end device ref igpu on @@ -256,7 +255,7 @@ chip soc/intel/meteorlake subsystemid 0x1558 0xa763 register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_sdi_enable[0]" = "1" - register "pch_hda_dsp_enable" = "1" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_codec_enable" = "1" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c index 46d7e70d1e2..ba69803a10d 100644 --- a/src/mainboard/ocp/deltalake/bootblock.c +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 6bcbfcc473b..517dfe54e0c 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index e9988695aa1..b950939509e 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -56,8 +56,9 @@ config UART_FOR_CONSOLE default 0 config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot.fmd" if VBOOT + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + config MAX_CPUS default 4 diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 2509031f3e5..9492ede8793 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index 0089a5fb463..7cccc309d77 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -6,7 +6,7 @@ chip soc/intel/alderlake # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "common_soc_config" = "{ // Type-C PD I2C bus diff --git a/src/mainboard/protectli/vault_cml/acpi/ec.asl b/src/mainboard/protectli/vault_cml/acpi/ec.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/protectli/vault_cml/acpi/ec.asl +++ b/src/mainboard/protectli/vault_cml/acpi/ec.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 2c8d25752e8..b73f1816748 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -47,7 +47,7 @@ chip soc/intel/cannonlake register "SkipExtGfxScan" = "1" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 0db005f1e87..e11427544e2 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -82,7 +82,6 @@ chip soc/intel/elkhartlake register "DdiPortADdc" = "1" register "DdiPortBDdc" = "1" - device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index 022e424357f..c05f69d7723 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -8,31 +8,32 @@ void mb_get_spd_map(struct spd_info *spdi) spdi->addresses[0] = 0x50; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P1: Left Side Port (USB2 only) */ - pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P2: Right Side Port (USB2) */ - pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P3: Empty */ - pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P4: Camera */ - pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P5: Bluetooth */ - pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P6: Empty */ - pei_data_usb2_port(pei_data, 5, 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P7: Empty */ - pei_data_usb2_port(pei_data, 6, 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P8: SD Card */ - pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Empty */ - pei_data_usb3_port(pei_data, 0, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P2: Right Side Port (USB3) */ - pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P3: Empty */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P4: Empty */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index 7eea6543589..e9d8a728814 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -9,31 +9,32 @@ void mb_get_spd_map(struct spd_info *spdi) spdi->addresses[2] = 0x52; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* P1: Right Side Port (USB2) */ - pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P2: Right Side Port (USB2) */ - pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P3: Left Side Port (USB2 only) */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P4: Left Side Port (USB2 only) */ - pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P5: Empty */ - pei_data_usb2_port(pei_data, 4, 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 0, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* P6: Bluetooth */ - pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P7: Camera */ - pei_data_usb2_port(pei_data, 6, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_SKIP); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_SKIP }, /* P8: SD Card */ - pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* P1: Right Side Port (USB3) */ - pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P2: Right Side Port (USB3) */ - pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + { 1, USB_OC_PIN_SKIP, 0 }, /* P3: Empty */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + { 0, USB_OC_PIN_SKIP, 0 }, /* P4: Empty */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); -} + { 0, USB_OC_PIN_SKIP, 0 }, +}; diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index af1dddd96a5..cee7a26a86e 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -37,7 +37,7 @@ chip soc/intel/cannonlake end device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index 42105e12e06..99c292b8dab 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -22,7 +22,7 @@ chip soc/intel/cannonlake device domain 0 on device ref xhci on chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left Upper"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/purism/librem_jsl/bootblock.c b/src/mainboard/purism/librem_jsl/bootblock.c index e0f480e8ce5..cf609fa270b 100644 --- a/src/mainboard/purism/librem_jsl/bootblock.c +++ b/src/mainboard/purism/librem_jsl/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index a8528f3459d..7c2c99018a5 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -23,10 +23,6 @@ chip soc/intel/jasperlake register "pmc_gpe0_dw1" = "PMC_GPP_D" register "pmc_gpe0_dw2" = "PMC_GPD" - register "SkipCpuReplacementCheck" = "1" - - device cpu_cluster 0 on end - register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -59,8 +55,6 @@ chip soc/intel/jasperlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Fingerprint Reader"" diff --git a/src/mainboard/purism/librem_jsl/romstage.c b/src/mainboard/purism/librem_jsl/romstage.c index e5164577466..929f2510ad6 100644 --- a/src/mainboard/purism/librem_jsl/romstage.c +++ b/src/mainboard/purism/librem_jsl/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include static const struct mb_cfg board_mem_cfg = { .dq_map[DDR_CH0] = { diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 9c6fffae8b4..2717d270e23 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 front right chip drivers/usb/acpi - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB 2.0 Type-A Front Left"" register "type" = "UPC_TYPE_A" diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 9fdbeb64af5..7a6bd343c5c 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index b4bc1119f24..f7ac9dc3ee8 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include void mainboard_pch_lpc_setup(void) diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb index 5c6cbc060bc..15e66359719 100644 --- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index e5544a10eb0..51fb5111bfe 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -101,13 +101,13 @@ chip soc/intel/apollolake # Enable external RTC chip chip drivers/i2c/rx6110sa register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index ae9c3b162c7..82fe0cb1071 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -107,13 +107,13 @@ chip soc/intel/apollolake # Enable external RTC chip chip drivers/i2c/rx6110sa register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 74e30bb3aaf..2a80cf09598 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -98,13 +98,13 @@ chip soc/intel/apollolake # Enable external RTC chip chip drivers/i2c/rx6110sa register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 87e4cc2f416..bf5ce602fc0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -102,13 +102,13 @@ chip soc/intel/apollolake # Enable external RTC chip chip drivers/i2c/rx6110sa register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 86e92d52895..0aecf31df2a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -75,13 +75,13 @@ chip soc/intel/apollolake # Enable external RTC chip chip drivers/i2c/rx6110sa register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index ac16346f2a1..1b5abaa4bf9 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -139,6 +139,9 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + /* Do board specific things */ + variant_mainboard_init(); } static void mainboard_final(void *chip_info) @@ -160,7 +163,11 @@ static void mainboard_final(void *chip_info) } } -/* The following function performs board specific things. */ +/* The following functions perform board specific things. */ +void __weak variant_mainboard_init(void) +{ +} + void __weak variant_mainboard_final(void) { } diff --git a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h index 901047991de..3f6c57c209b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,8 @@ const struct mb_cfg *variant_memcfg_config(void); /* This function can select half-populate DRAM */ bool half_populated(void); -/* The following function performs board specific things. */ +/* The following functions perform board specific things. */ +void variant_mainboard_init(void); void variant_mainboard_final(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 6e85734887d..3860ce9b2fe 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -166,13 +164,13 @@ chip soc/intel/elkhartlake chip drivers/i2c/rx6110sa register "bus_speed" = "I2C_SPEED_STANDARD" register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "bks_on" = "false" + register "bks_off" = "true" + register "iocut_en" = "true" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index c1ebf7b5be0..19ca581ef9e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -161,10 +159,10 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 71baa47b11c..a35cb0e8c38 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -64,6 +62,23 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[2]" = "true" register "PcieRpLtrDisable[4]" = "true" + # Adjust TX Output De-Emphasis for PCIe RP3 to -6.3 dB + register "pcie_mp_cfg[2]" = "{ + .tx_gen2_de_emph_3p5 = 0x1f, + }" + + # Enable PCIe EQ override + register "PcieEqOverrideDefault" = "true" + register "PcieEqMethod" = "FIXED_EQ" + register "PcieEqMode" = "COEFFICIENT_EQ" + register "PcieEqPh3NumberOfPresetsOrCoefficients" = "2" + register "PcieEqPh3PreCursorList[0]" = "10" + register "PcieEqPh3PreCursorList[1]" = "10" + register "PcieEqPh3PostCursorList[0]" = "8" + register "PcieEqPh3PostCursorList[1]" = "8" + register "PcieEqPh1DownstreamPortTransmitterPreset" = "7" + register "PcieEqPh1UpstreamPortTransmitterPreset" = "1" + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" @@ -158,10 +173,10 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index 01349687b8f..cfc660c8b3f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -17,6 +17,17 @@ #define MMC_CAP_BYP_SDR104 (1 << 14) #define MMC_CAP_BYP_DDR50 (1 << 15) +#define GEN2_TUNING_RP (PCI_DEV(0, 0x1c, 0x02)) +#define GEN2_LCTL2_LSTS2_REG 0x70 +#define GEN2_LCTL2_LSTS2_SD (1 << 6) + +#define GEN3_TUNING_BUS 1 +#define GEN3_TUNING_MMIO_BASE 0xfe800000 +#define GEN3_TUNING_RP (PCI_DEV(0, 0x1c, 0x04)) +#define GEN3_TUNING_DEV (PCI_DEV(GEN3_TUNING_BUS, 0, 0)) +#define GEN3_EQ_CONTROL_REG 0x8A8 +#define GEN3_EQ_PRESET_7 0x05008071 + /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ static void disable_sdr_modes(struct resource *res) { @@ -26,6 +37,37 @@ static void disable_sdr_modes(struct resource *res) MMC_CAP_BYP_DDR50); } +void variant_mainboard_init(void) +{ + /* First set up root port bridge to get access to Gen3 device. */ + pci_s_write_config8(GEN3_TUNING_RP, PCI_SECONDARY_BUS, GEN3_TUNING_BUS); + pci_s_write_config8(GEN3_TUNING_RP, PCI_SUBORDINATE_BUS, GEN3_TUNING_BUS); + /* Define an address window to forward to the secondary bus. */ + pci_s_write_config32(GEN3_TUNING_RP, PCI_MEMORY_BASE, + (GEN3_TUNING_MMIO_BASE | (GEN3_TUNING_MMIO_BASE >> 16))); + /* Enable memory mapped transfers. */ + pci_s_write_config32(GEN3_TUNING_RP, PCI_COMMAND, PCI_COMMAND_MEMORY); + /* Now the device is visible on bus 1, dev 0, function 0. */ + pci_s_write_config32(GEN3_TUNING_DEV, PCI_BASE_ADDRESS_0, GEN3_TUNING_MMIO_BASE); + pci_s_write_config32(GEN3_TUNING_DEV, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Selection of Preset 7 for transmitter of DSP for Gen3-Link. */ + pci_s_write_config32(GEN3_TUNING_DEV, GEN3_EQ_CONTROL_REG, GEN3_EQ_PRESET_7); + + /* Now delete all the changes made in config space so that the PCI enumerator can do + its work. */ + pci_s_write_config32(GEN3_TUNING_DEV, PCI_BASE_ADDRESS_0, 0); + pci_s_write_config32(GEN3_TUNING_DEV, PCI_COMMAND, 0); + pci_s_write_config32(GEN3_TUNING_RP, PCI_PRIMARY_BUS, 0x0); + pci_s_write_config32(GEN3_TUNING_RP, PCI_MEMORY_BASE, 0); + pci_s_write_config32(GEN3_TUNING_RP, PCI_COMMAND, 0); + + /* Select -3.5 dB de-emphasis for Gen2 (5.0 GT/s) */ + pci_s_write_config32(GEN2_TUNING_RP, GEN2_LCTL2_LSTS2_REG, + pci_s_read_config32(GEN2_TUNING_RP, GEN2_LCTL2_LSTS2_REG) | + GEN2_LCTL2_LSTS2_SD); +} + void variant_mainboard_final(void) { struct device *dev; diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index f17052076a0..70cbf733019 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -145,10 +143,10 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 5fca41cd4be..3d7c1fe12bf 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -161,10 +159,10 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb index f47fde0cab1..b291abf502d 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -140,6 +138,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Set IccMax for IA (CPU) domain in 1/4 A units + register "IccMax" = "60" + # Disable L1 prefetcher for real-time demands register "L1_prefetcher_disable" = "true" @@ -165,13 +166,14 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" + register "sync_to_cmos_rtc" = "true" device i2c 0x52 on end # RTC RV3028-C7 end # Add dummy I2C device to limit BUS speed to 100 kHz in OS diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb index fcd6de54630..458fd43eb2e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -127,6 +125,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Set IccMax for IA (CPU) domain in 1/4 A units + register "IccMax" = "60" + # Disable L1 prefetcher for real-time demands register "L1_prefetcher_disable" = "true" @@ -135,7 +136,7 @@ chip soc/intel/elkhartlake device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 off end # Integrated Graphics Device device pci 10.0 on # I2C6 # Add dummy I2C device to limit BUS speed to 100 kHz in OS diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb index 34cf91baa2c..d9badd75768 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -110,6 +108,36 @@ chip soc/intel/elkhartlake [PchSerialIoIndexI2C6] = 1, }" + register "common_soc_config" = "{ + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, /* 4,81us */ + .scl_lcnt = 0x1f4, /* 5us */ + .sda_hold = 0x64 /* 1us */ + } + }, + .i2c[4] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, /* 4,81us */ + .scl_lcnt = 0x1f4, /* 5us */ + .sda_hold = 0x64 /* 1us */ + } + }, + .i2c[6] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, /* 4,81us */ + .scl_lcnt = 0x1f4, /* 5us */ + .sda_hold = 0x64 /* 1us */ + } + }, + }" + register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoPci, @@ -142,18 +170,39 @@ chip soc/intel/elkhartlake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 10.0 on end # I2C6 + device pci 10.0 on # I2C6 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device pci 14.0 on end # USB3.1 xHCI device pci 15.0 off end # I2C0 - device pci 15.2 on end # I2C2 + device pci 15.2 on # I2C2 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device pci 16.0 hidden end # Management Engine Interface 1 device pci 17.0 on end # SATA - device pci 19.0 on end # I2C4 + device pci 19.0 on # I2C4 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC @@ -178,13 +227,14 @@ chip soc/intel/elkhartlake # Enable external RTC chip chip drivers/i2c/rv3028c7 register "bus_speed" = "I2C_SPEED_STANDARD" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" register "user_weekday" = "4" register "bckup_sw_mode" = "BACKUP_SW_LEVEL" register "cap_charge" = "CHARGE_OFF" + register "sync_to_cmos_rtc" = "true" device i2c 0x52 on end # RTC RV3028-C7 end # PI7C9X2G608GP PCIe switch configuration diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb index 5477b4697a9..a5acc588b89 100644 --- a/src/mainboard/siemens/mc_rpl/devicetree.cb +++ b/src/mainboard/siemens/mc_rpl/devicetree.cb @@ -23,6 +23,5 @@ chip soc/intel/alderlake device ref igpu on end device ref crashlog off end device ref p2sb on end - device ref smbus on end end end diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig index fdb35b66d52..9886b29d458 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig @@ -5,6 +5,7 @@ if BOARD_SIEMENS_MC_RPL1 config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 + select DRIVERS_I2C_RV3028C7 select DRIVERS_UART_8250IO select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c index ca79d042513..a98e2e0b154 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c @@ -11,6 +11,8 @@ static const struct pad_config gpio_table[] = { /* Community 0 - Gpio Group GPP_B */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), /* I2C2_SDA */ + PAD_CFG_NF(GPP_B6, UP_5K, DEEP, NF2), /* I2C2_SCL */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), PAD_CFG_GPI(GPP_B23, NONE, PLTRST), @@ -30,6 +32,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_H1, NONE, PLTRST), PAD_CFG_GPI(GPP_H2, NONE, PLTRST), PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C4_SDA */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* PCIE_XCLKREQ4 */ diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb index ae514c2f3e8..37265458e3a 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -48,10 +48,10 @@ chip soc/intel/alderlake register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexI2C6] = PchSerialIoPci, }" @@ -64,11 +64,37 @@ chip soc/intel/alderlake # Intel Common SoC Config register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, + .i2c[1] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 420, + .scl_lcnt = 558, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 420, + .scl_lcnt = 550, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 420, + .scl_lcnt = 567, + } + }, .i2c[6] = { - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 420, + .scl_lcnt = 565, + } }, }" @@ -128,7 +154,42 @@ chip soc/intel/alderlake }" end device ref i2c0 on end - device ref i2c6 on end + device ref i2c1 on + # Enable external RTC chip + chip drivers/i2c/rv3028c7 + register "bus_speed" = "I2C_SPEED_STANDARD" + register "set_user_date" = "true" + register "user_year" = "4" + register "user_month" = "7" + register "user_day" = "1" + register "user_weekday" = "4" + register "bckup_sw_mode" = "BACKUP_SW_LEVEL" + register "cap_charge" = "CHARGE_OFF" + register "sync_to_cmos_rtc" = "true" + device i2c 0x52 on end # RTC RV3028-C7 + end + end + device ref i2c2 on + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end + device ref i2c4 on + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end + device ref i2c6 on + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig index 479ec79165e..82379e80c4d 100644 --- a/src/mainboard/starlabs/adl/Kconfig +++ b/src/mainboard/starlabs/adl/Kconfig @@ -27,6 +27,7 @@ config BOARD_STARLABS_ADL_HORIZON select BOARD_STARLABS_ADL_SERIES select DRIVERS_GFX_GENERIC select DRIVERS_I2C_HID + select EC_STARLABS_FAN select HAVE_HDA_DMIC select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_TPM2 @@ -50,7 +51,6 @@ config BOARD_STARLABS_BYTE_ADL select BOARD_STARLABS_ADL_SERIES select CRB_TPM select DRIVERS_PCIE_GENERIC - select EC_STARLABS_FAN select HAVE_INTEL_PTT select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -80,10 +80,6 @@ config DEVICETREE config DIMM_SPD_SIZE default 512 -config EDK2_BOOTSPLASH_FILE - string - default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" - config EC_STARLABS_ITE_BIN_PATH string default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" @@ -138,9 +134,6 @@ config VARIANT_DIR default "i5" if BOARD_STARLABS_LITE_ADL default "y2" if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL -config CMOS_LAYOUT_FILE - default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" - if BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_LITE_ADL config CCD_PORT @@ -168,16 +161,19 @@ endif # MAINBOARD_HAS_TPM2 endif # BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_LITE_ADL -if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL - config MB_STARLABS_PL4_WATTS int - default 65 if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL + default 65 if BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL default 37 if BOARD_STARLABS_LITE_ADL +if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL + config VBOOT select VBOOT_VBNV_FLASH endif # BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL +config EC_STARLABS_LID_SWITCH + default n if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL + endif # BOARD_STARLABS_ADL_SERIES diff --git a/src/mainboard/starlabs/adl/Makefile.mk b/src/mainboard/starlabs/adl/Makefile.mk index f42ebef3ab5..ad15bbd510c 100644 --- a/src/mainboard/starlabs/adl/Makefile.mk +++ b/src/mainboard/starlabs/adl/Makefile.mk @@ -7,5 +7,4 @@ subdirs-y += variants/$(VARIANT_DIR) bootblock-y += bootblock.c ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c -ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += $(wildcard variants/$(VARIANT_DIR)/cfr.c) ramstage-y += mainboard.c diff --git a/src/mainboard/starlabs/adl/acpi/ec.asl b/src/mainboard/starlabs/adl/acpi/ec.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/adl/acpi/ec.asl +++ b/src/mainboard/starlabs/adl/acpi/ec.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/adl/acpi/superio.asl b/src/mainboard/starlabs/adl/acpi/superio.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/adl/acpi/superio.asl +++ b/src/mainboard/starlabs/adl/acpi/superio.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c index 89f7730e453..1fb2a748400 100644 --- a/src/mainboard/starlabs/adl/cfr.c +++ b/src/mainboard/starlabs/adl/cfr.c @@ -4,14 +4,67 @@ #include #include #include +#include #include #include +#if CONFIG(BOARD_STARLABS_BYTE_ADL) || CONFIG(BOARD_STARLABS_BYTE_TWL) +static const struct pcie_pm_option_names pciexp_lan1_names = { + .clk_pm = "pciexp_lan1_clk_pm", + .aspm = "pciexp_lan1_aspm", + .l1ss = "pciexp_lan1_l1ss", + .speed = "pciexp_speed", +}; + +static const struct pcie_pm_option_names pciexp_lan2_names = { + .clk_pm = "pciexp_lan2_clk_pm", + .aspm = "pciexp_lan2_aspm", + .l1ss = "pciexp_lan2_l1ss", + .speed = "pciexp_speed", +}; +#endif + +static const struct pcie_pm_option_names pciexp_ssd_names = { + .clk_pm = "pciexp_ssd_clk_pm", + .aspm = "pciexp_ssd_aspm", + .l1ss = "pciexp_ssd_l1ss", + .speed = "pciexp_speed", +}; + +void mainboard_get_pcie_pm_options(const struct pcie_rp_config *rp_cfg, + unsigned int index, + bool is_cpu_rp, + struct pcie_pm_option_names *names) +{ + (void)rp_cfg; + + if (!names || is_cpu_rp) + return; + +#if CONFIG(BOARD_STARLABS_ADL_HORIZON) || CONFIG(BOARD_STARLABS_LITE_ADL) + if (index == PCH_RP(9)) + *names = pciexp_ssd_names; +#elif CONFIG(BOARD_STARLABS_BYTE_ADL) || CONFIG(BOARD_STARLABS_BYTE_TWL) + switch (index) { + case PCH_RP(9): + *names = pciexp_lan1_names; + return; + case PCH_RP(10): + *names = pciexp_lan2_names; + return; + case PCH_RP(12): + *names = pciexp_ssd_names; + return; + } +#endif +} + #if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE) static struct sm_obj_form audio_video_group = { .ui_name = "Audio/Video", .obj_list = (const struct sm_object *[]){ µphone, + &hda_dsp, &webcam, NULL, }, @@ -80,10 +133,22 @@ static struct sm_obj_form io_expansion_group = { static struct sm_obj_form pcie_power_management_group = { .ui_name = "PCIe Power Management", .obj_list = - (const struct sm_object *[]){ - &pciexp_aspm, - &pciexp_clk_pm, - &pciexp_l1ss, + (const struct sm_object *[]){ +#if CONFIG(BOARD_STARLABS_ADL_HORIZON) || CONFIG(BOARD_STARLABS_LITE_ADL) + &pciexp_ssd_clk_pm, + &pciexp_ssd_aspm, + &pciexp_ssd_l1ss, +#elif CONFIG(BOARD_STARLABS_BYTE_ADL) || CONFIG(BOARD_STARLABS_BYTE_TWL) + &pciexp_lan1_clk_pm, + &pciexp_lan1_aspm, + &pciexp_lan1_l1ss, + &pciexp_lan2_clk_pm, + &pciexp_lan2_aspm, + &pciexp_lan2_l1ss, + &pciexp_ssd_clk_pm, + &pciexp_ssd_aspm, + &pciexp_ssd_l1ss, +#endif NULL, }, }; @@ -98,13 +163,24 @@ static struct sm_obj_form performance_group = { #if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE) &memory_speed, #endif - &power_profile, NULL}, + &power_profile, + &pl1_override, + &pl2_override, +#if CONFIG(STARLABS_LEGACY_PL4) + &pl4_override, +#endif + &tcc_temp, + NULL}, }; static struct sm_obj_form security_group = { .ui_name = "Security", .obj_list = (const struct sm_object *[]){&bios_lock, &intel_tme, &me_state, - &me_state_counter, NULL}, + &me_state_counter, +#if CONFIG(SOC_INTEL_ALDERLAKE) + &ibecc, +#endif + NULL}, }; static struct sm_obj_form suspend_lid_group = { diff --git a/src/mainboard/starlabs/adl/dsdt.asl b/src/mainboard/starlabs/adl/dsdt.asl index 367d6af038f..4f65639dd4f 100644 --- a/src/mainboard/starlabs/adl/dsdt.asl +++ b/src/mainboard/starlabs/adl/dsdt.asl @@ -26,7 +26,7 @@ DefinitionBlock( #include /* PS/2 Keyboard */ - #include + #include #endif } diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c index d7a0dab9a8d..711170fbeb1 100644 --- a/src/mainboard/starlabs/adl/mainboard.c +++ b/src/mainboard/starlabs/adl/mainboard.c @@ -2,8 +2,6 @@ #include #include -#include -#include #include static void starlabs_configure_mainboard(void *unused) diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt index a101af780b8..f62deff97a0 100644 Binary files a/src/mainboard/starlabs/adl/variants/hz/data.vbt and b/src/mainboard/starlabs/adl/variants/hz/data.vbt differ diff --git a/src/mainboard/starlabs/adl/variants/hz/devtree.c b/src/mainboard/starlabs/adl/variants/hz/devtree.c index c53fbb3bd09..e2dcc258720 100644 --- a/src/mainboard/starlabs/adl/variants/hz/devtree.c +++ b/src/mainboard/starlabs/adl/variants/hz/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/adl/variants/hz/hda_verb.c b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c index 813c0f0458f..73ccd59d69b 100644 --- a/src/mainboard/starlabs/adl/variants/hz/hda_verb.c +++ b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c @@ -78,7 +78,7 @@ const u32 cim_verb_data[] = { 0x02050008, 0x02040000, 0x0205000c, - 0x02043f00, + 0x02044b00, /* ALC269 Default 4 */ 0x02050015, 0x02048002, diff --git a/src/mainboard/starlabs/adl/variants/hz/ramstage.c b/src/mainboard/starlabs/adl/variants/hz/ramstage.c index de25c0a7e5d..3e9cfb13c4f 100644 --- a/src/mainboard/starlabs/adl/variants/hz/ramstage.c +++ b/src/mainboard/starlabs/adl/variants/hz/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include @@ -8,8 +7,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { configure_pin_mux(supd); } - -const char *mainboard_vbt_filename(void) -{ - return "vbt.bin"; -} diff --git a/src/mainboard/starlabs/adl/variants/hz/romstage.c b/src/mainboard/starlabs/adl/variants/hz/romstage.c index 9162509387a..9b02f7d96f7 100644 --- a/src/mainboard/starlabs/adl/variants/hz/romstage.c +++ b/src/mainboard/starlabs/adl/variants/hz/romstage.c @@ -1,10 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include +#define MEMORY_SPEED_DEFAULT 1 + +uint8_t fsp_memory_mainboard_version(void) +{ + return starlabs_get_memory_speed_option(MEMORY_SPEED_DEFAULT); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { const struct mb_cfg mem_config = { @@ -92,11 +101,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) const struct mem_spd lpddr5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = get_uint_option("memory_speed", 1), + .cbfs_index = fsp_memory_mainboard_version(), }; memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; }; diff --git a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk index 4bd5ef44c06..2651d0a065a 100644 --- a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk +++ b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += gpio.c romstage-y += romstage.c +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/adl/variants/i5/cfr.c b/src/mainboard/starlabs/adl/variants/i5/cfr.c index 5593cb55316..fb14effbcf2 100644 --- a/src/mainboard/starlabs/adl/variants/i5/cfr.c +++ b/src/mainboard/starlabs/adl/variants/i5/cfr.c @@ -5,6 +5,7 @@ #include #include #include +#include void cfr_card_reader_update(struct sm_object *new_obj) { diff --git a/src/mainboard/starlabs/adl/variants/i5/data.vbt b/src/mainboard/starlabs/adl/variants/i5/data.vbt index 13c5b92d61f..a9d55e4d0b9 100644 Binary files a/src/mainboard/starlabs/adl/variants/i5/data.vbt and b/src/mainboard/starlabs/adl/variants/i5/data.vbt differ diff --git a/src/mainboard/starlabs/adl/variants/i5/devtree.c b/src/mainboard/starlabs/adl/variants/i5/devtree.c index 4d76c77bb81..dfd5a42e8ee 100644 --- a/src/mainboard/starlabs/adl/variants/i5/devtree.c +++ b/src/mainboard/starlabs/adl/variants/i5/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/adl/variants/i5/hda_verb.c b/src/mainboard/starlabs/adl/variants/i5/hda_verb.c index f7529371d66..18e40f49dc1 100644 --- a/src/mainboard/starlabs/adl/variants/i5/hda_verb.c +++ b/src/mainboard/starlabs/adl/variants/i5/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { 0x02050008, 0x02040000, 0x0205000c, - 0x02043f00, + 0x02044b00, /* ALC269 Default 4 */ 0x02050015, 0x02048002, diff --git a/src/mainboard/starlabs/adl/variants/i5/ramstage.c b/src/mainboard/starlabs/adl/variants/i5/ramstage.c index de25c0a7e5d..3e9cfb13c4f 100644 --- a/src/mainboard/starlabs/adl/variants/i5/ramstage.c +++ b/src/mainboard/starlabs/adl/variants/i5/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include @@ -8,8 +7,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { configure_pin_mux(supd); } - -const char *mainboard_vbt_filename(void) -{ - return "vbt.bin"; -} diff --git a/src/mainboard/starlabs/adl/variants/i5/romstage.c b/src/mainboard/starlabs/adl/variants/i5/romstage.c index 13c31ea8099..ae096b2a098 100644 --- a/src/mainboard/starlabs/adl/variants/i5/romstage.c +++ b/src/mainboard/starlabs/adl/variants/i5/romstage.c @@ -1,10 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include +#define MEMORY_SPEED_DEFAULT 0 + +uint8_t fsp_memory_mainboard_version(void) +{ + return starlabs_get_memory_speed_option(MEMORY_SPEED_DEFAULT); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { const struct mb_cfg mem_config = { @@ -93,11 +102,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) const struct mem_spd lpddr5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = get_uint_option("memory_speed", 0), + .cbfs_index = fsp_memory_mainboard_version(), }; memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; }; diff --git a/src/mainboard/starlabs/adl/variants/y2/devtree.c b/src/mainboard/starlabs/adl/variants/y2/devtree.c index 3824fe9a7ea..d4b7b699359 100644 --- a/src/mainboard/starlabs/adl/variants/y2/devtree.c +++ b/src/mainboard/starlabs/adl/variants/y2/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/adl/variants/y2/romstage.c b/src/mainboard/starlabs/adl/variants/y2/romstage.c index 5f8ebd602f4..e2463e5a9a7 100644 --- a/src/mainboard/starlabs/adl/variants/y2/romstage.c +++ b/src/mainboard/starlabs/adl/variants/y2/romstage.c @@ -26,6 +26,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; }; diff --git a/src/mainboard/starlabs/cezanne/Kconfig b/src/mainboard/starlabs/cezanne/Kconfig new file mode 100644 index 00000000000..4d621acb3eb --- /dev/null +++ b/src/mainboard/starlabs/cezanne/Kconfig @@ -0,0 +1,107 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_STARLABS_CEZANNE_SERIES + def_bool n + select AMD_FWM_POSITION_820000_DEFAULT + select AMD_SOC_CONSOLE_UART + select AZALIA_HDA_CODEC_SUPPORT + select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_16384 + select DISABLE_KEYBOARD_RESET_PIN + select DRIVERS_EFI_VARIABLE_STORE + select DRIVERS_I2C_HID + select DRIVERS_OPTION_CFR_ENABLED + select DRIVERS_PCIE_RTD3_DEVICE + select EC_STARLABS_ITE + select EC_STARLABS_FAN + select EC_STARLABS_MERLIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_HDA_DMIC + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select SERIRQ_CONTINUOUS_MODE + select SOC_AMD_CEZANNE + select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF + select SPI_FLASH_WINBOND + select VGA_BIOS + +config BOARD_STARLABS_BYTE_CEZANNE + select BOARD_STARLABS_CEZANNE_SERIES + select SYSTEM_TYPE_MINIPC + +config BOARD_STARLABS_STARBOOK_CEZANNE + select BOARD_STARLABS_CEZANNE_SERIES + select EC_STARLABS_KBL_LEVELS + select SYSTEM_TYPE_LAPTOP + +if BOARD_STARLABS_CEZANNE_SERIES + +config ADD_APCB_SOURCES + bool "Add PSP customisation files" + +config APCB_SOURCES_PATH + string "Path to APCB files" + +config CONSOLE_SERIAL + default n if !EDK2_DEBUG + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config EC_GPE_SCI + default 0x17 + +config EC_STARLABS_ADD_ITE_BIN + default y if BOARD_STARLABS_STARBOOK_CEZANNE + +config EC_STARLABS_ITE_BIN_PATH + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAINBOARD_DIR + default "starlabs/cezanne" + +config MAINBOARD_FAMILY + default "B6-A" if BOARD_STARLABS_STARBOOK_CEZANNE + default "Y1" if BOARD_STARLABS_BYTE_CEZANNE + +config MAINBOARD_PART_NUMBER + default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_CEZANNE + default "Byte Mk I" if BOARD_STARLABS_BYTE_CEZANNE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "StarBook" if BOARD_STARLABS_STARBOOK_CEZANNE + default "Byte" if BOARD_STARLABS_BYTE_CEZANNE + +config POST_IO + default y if BOARD_STARLABS_STARBOOK_CEZANNE + default n if BOARD_STARLABS_BYTE_CEZANNE + +config PSP_LOAD_MP2_FW + default y + +config PSP_POSTCODES_ON_ESPI + default n + +config S3_VGA_ROM_RUN + default n + +config VARIANT_DIR + default "starbook" if BOARD_STARLABS_STARBOOK_CEZANNE + default "byte" if BOARD_STARLABS_BYTE_CEZANNE + +config EFS_SPI_SPEED + default 3 # 66MHz + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 0 # 66MHz + +endif diff --git a/src/mainboard/starlabs/cezanne/Kconfig.name b/src/mainboard/starlabs/cezanne/Kconfig.name new file mode 100644 index 00000000000..de491befe1d --- /dev/null +++ b/src/mainboard/starlabs/cezanne/Kconfig.name @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "Star Labs Cezanne Series" + +config BOARD_STARLABS_BYTE_CEZANNE + bool "Star Labs Byte Mk I (Ryzen 7 5800U)" + +config BOARD_STARLABS_STARBOOK_CEZANNE + bool "Star Labs StarBook Mk VI (Ryzen 7 5800U)" diff --git a/src/mainboard/starlabs/cezanne/Makefile.mk b/src/mainboard/starlabs/cezanne/Makefile.mk new file mode 100644 index 00000000000..d1e5fac7a3a --- /dev/null +++ b/src/mainboard/starlabs/cezanne/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +subdirs-y += variants/$(VARIANT_DIR) + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c +ramstage-y += mainboard.c + +ifeq ($(CONFIG_ADD_APCB_SOURCES),y) +APCB_SOURCES = $(call strip_quotes, $(CONFIG_APCB_SOURCES_PATH))/APCB_CZN_D4_Updatable.bin +APCB_SOURCES_68 = $(call strip_quotes,$(CONFIG_APCB_SOURCES_PATH))/APCB_CZN_D4_Updatable_68.bin +APCB_SOURCES_RECOVERY = $(call strip_quotes,$(CONFIG_APCB_SOURCES_PATH))/APCB_CZN_D4_DefaultRecovery.bin +endif diff --git a/src/mainboard/starlabs/cezanne/acpi/mainboard.asl b/src/mainboard/starlabs/cezanne/acpi/mainboard.asl new file mode 100644 index 00000000000..34b90af325e --- /dev/null +++ b/src/mainboard/starlabs/cezanne/acpi/mainboard.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" +} diff --git a/src/mainboard/starlabs/cezanne/acpi/sleep.asl b/src/mainboard/starlabs/cezanne/acpi/sleep.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/cezanne/board.fmd b/src/mainboard/starlabs/cezanne/board.fmd new file mode 100644 index 00000000000..87e33dd3c8b --- /dev/null +++ b/src/mainboard/starlabs/cezanne/board.fmd @@ -0,0 +1,10 @@ +FLASH 0x1000000 { + SI_ALL { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x80000 + CONSOLE@0xb0000 0x20000 + FMAP@0xd0000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/cezanne/board_info.txt b/src/mainboard/starlabs/cezanne/board_info.txt new file mode 100644 index 00000000000..7928cf16a65 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Star Labs +Board name: StarBook Mk VI AMD +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2024 diff --git a/src/mainboard/starlabs/cezanne/bootblock.c b/src/mainboard/starlabs/cezanne/bootblock.c new file mode 100644 index 00000000000..d62444ae390 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + const struct soc_amd_gpio *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); + + lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + lpc_enable_decode(DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT); +} diff --git a/src/mainboard/starlabs/cezanne/cfr.c b/src/mainboard/starlabs/cezanne/cfr.c new file mode 100644 index 00000000000..1db7ac34a25 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/cfr.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +enum { + STARLABS_CFR_ASPM_DISABLE = 1, + STARLABS_CFR_ASPM_L0S, + STARLABS_CFR_ASPM_L1, + STARLABS_CFR_ASPM_L0S_L1, + STARLABS_CFR_ASPM_AUTO, +}; + +enum { + STARLABS_CFR_L1SS_DISABLED = 1, + STARLABS_CFR_L1SS_L1_1, + STARLABS_CFR_L1SS_L1_2, +}; + +static void cezanne_update_pcie_clk_pm(struct sm_object *new_obj) +{ + if (!CONFIG(PCIEXP_CLK_PM)) + new_obj->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS; +} + +static void cezanne_update_pcie_aspm(struct sm_object *new_obj) +{ + if (!CONFIG(PCIEXP_ASPM)) + new_obj->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS; +} + +static void cezanne_update_pcie_l1ss(struct sm_object *new_obj) +{ + if (!CONFIG(PCIEXP_ASPM) || !CONFIG(PCIEXP_L1_SUB_STATE)) + new_obj->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS; +} + +static const struct cfr_default_override cezanne_cfr_overrides[] = { + CFR_OVERRIDE_ENUM("pciexp_wifi_aspm", STARLABS_CFR_ASPM_L1), + CFR_OVERRIDE_ENUM("pciexp_ssd_aspm", STARLABS_CFR_ASPM_L1), + CFR_OVERRIDE_END +}; + +static const struct sm_object microphone = SM_DECLARE_BOOL({ + .opt_name = "microphone", + .ui_name = "Microphone", + .ui_helptext = "Enable or disable the built-in microphone", + .default_value = true, +}); + +static const struct sm_object power_profile = SM_DECLARE_ENUM({ + .opt_name = "power_profile", + .ui_name = "Power Profile", + .ui_helptext = "Select whether to maximize performance, battery life or both.", + .default_value = PP_BALANCED, + .values = (const struct sm_enum_value[]) { + { "Power Saver", PP_POWER_SAVER }, + { "Balanced", PP_BALANCED }, + { "Performance", PP_PERFORMANCE }, + SM_ENUM_VALUE_END }, +}); + +#define STARBOOK_CEZANNE_DECLARE_PCIE_PM_OBJECTS(_suffix, _label) \ +static const struct sm_object pciexp_##_suffix##_clk_pm = SM_DECLARE_BOOL({ \ + .opt_name = "pciexp_" #_suffix "_clk_pm", \ + .ui_name = _label " Clock Power Management", \ + .ui_helptext = "Enable or disable clock power management for " _label ".", \ + .default_value = true, \ +}, WITH_CALLBACK(cezanne_update_pcie_clk_pm)); \ + \ +static const struct sm_object pciexp_##_suffix##_aspm = SM_DECLARE_ENUM({ \ + .opt_name = "pciexp_" #_suffix "_aspm", \ + .ui_name = _label " ASPM", \ + .ui_helptext = "Control Active State Power Management for " _label ".", \ + .default_value = STARLABS_CFR_ASPM_L1, \ + .values = (const struct sm_enum_value[]) { \ + { "Disabled", STARLABS_CFR_ASPM_DISABLE }, \ + { "L0s", STARLABS_CFR_ASPM_L0S }, \ + { "L1", STARLABS_CFR_ASPM_L1 }, \ + { "L0sL1", STARLABS_CFR_ASPM_L0S_L1 }, \ + { "Auto", STARLABS_CFR_ASPM_AUTO }, \ + SM_ENUM_VALUE_END }, \ +}, WITH_DEP_VALUES(&pciexp_##_suffix##_clk_pm, true), \ + WITH_CALLBACK(cezanne_update_pcie_aspm)) + +#define STARBOOK_CEZANNE_DECLARE_PCIE_L1SS_OBJECT(_suffix, _label) \ +static const struct sm_object pciexp_##_suffix##_l1ss = SM_DECLARE_ENUM({ \ + .opt_name = "pciexp_" #_suffix "_l1ss", \ + .ui_name = _label " L1 Substates", \ + .ui_helptext = "Control PCIe L1 substates for " _label ".", \ + .default_value = STARLABS_CFR_L1SS_L1_2, \ + .values = (const struct sm_enum_value[]) { \ + { "Disabled", STARLABS_CFR_L1SS_DISABLED }, \ + { "L1.1", STARLABS_CFR_L1SS_L1_1 }, \ + { "L1.2", STARLABS_CFR_L1SS_L1_2 }, \ + SM_ENUM_VALUE_END }, \ +}, WITH_DEP_VALUES(&pciexp_##_suffix##_clk_pm, true), \ + WITH_CALLBACK(cezanne_update_pcie_l1ss)) + +STARBOOK_CEZANNE_DECLARE_PCIE_PM_OBJECTS(wifi, "Wi-Fi"); +STARBOOK_CEZANNE_DECLARE_PCIE_PM_OBJECTS(ssd, "SSD"); +STARBOOK_CEZANNE_DECLARE_PCIE_L1SS_OBJECT(ssd, "SSD"); + +#undef STARBOOK_CEZANNE_DECLARE_PCIE_PM_OBJECTS +#undef STARBOOK_CEZANNE_DECLARE_PCIE_L1SS_OBJECT + +static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({ + .opt_name = "bluetooth_rtd3", + .ui_name = "Bluetooth Runtime-D3", + .ui_helptext = "Enable or disable Bluetooth power optimization.\n" + "Recommended to disable when booting Windows.", + .default_value = false, +}); + +static const struct sm_object wifi = SM_DECLARE_BOOL({ + .opt_name = "wifi", + .ui_name = "Wi-Fi", + .ui_helptext = "Enable or disable the built-in Wi-Fi", + .default_value = true, +}); + +static struct sm_obj_form audio_video_group = { + .ui_name = "Audio/Video", + .obj_list = (const struct sm_object *[]) { + µphone, + NULL + }, +}; + +static struct sm_obj_form battery_group = { + .ui_name = "Battery", + .obj_list = (const struct sm_object *[]) { + #if CONFIG(EC_STARLABS_CHARGING_SPEED) + &charging_speed, + #endif + #if CONFIG(EC_STARLABS_MAX_CHARGE) + &max_charge, + #endif + NULL + }, +}; + +static struct sm_obj_form debug_group = { + .ui_name = "Debug", + .obj_list = (const struct sm_object *[]) { + &debug_level, + NULL + }, +}; + +static struct sm_obj_form keyboard_group = { + .ui_name = "Keyboard", + .obj_list = (const struct sm_object *[]) { + &fn_ctrl_swap, + &kbl_timeout, + NULL + }, +}; + +static struct sm_obj_form leds_group = { + .ui_name = "LEDs", + .obj_list = (const struct sm_object *[]) { + &charge_led, + &power_led, + NULL + }, +}; + +static struct sm_obj_form pcie_power_management_group = { + .ui_name = "PCIe Power Management", + .obj_list = (const struct sm_object *[]) { + &pciexp_wifi_clk_pm, + &pciexp_wifi_aspm, + &pciexp_ssd_clk_pm, + &pciexp_ssd_aspm, + &pciexp_ssd_l1ss, + NULL + }, +}; + +static struct sm_obj_form performance_group = { + .ui_name = "Performance", + .obj_list = (const struct sm_object *[]) { + &fan_mode, + &power_profile, + NULL + }, +}; + +static struct sm_obj_form security_group = { + .ui_name = "Security", + .obj_list = (const struct sm_object *[]) { + NULL + }, +}; + +static struct sm_obj_form suspend_lid_group = { + .ui_name = "Suspend & Lid", + .obj_list = (const struct sm_object *[]) { + #if CONFIG(EC_STARLABS_LID_SWITCH) + &lid_switch, + #endif + NULL + }, +}; + +static struct sm_obj_form wireless_group = { + .ui_name = "Wireless", + .obj_list = (const struct sm_object *[]) { + &bluetooth_rtd3, + &wifi, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &audio_video_group, + &battery_group, + &debug_group, + &keyboard_group, + &leds_group, + &pcie_power_management_group, + &performance_group, + &security_group, + &suspend_lid_group, + &wireless_group, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + cfr_register_overrides(cezanne_cfr_overrides); + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/starlabs/cezanne/dsdt.asl b/src/mainboard/starlabs/cezanne/dsdt.asl new file mode 100644 index 00000000000..6a5201d9793 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/dsdt.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20220909 +) +{ + #include + #include + + Name(LIDS, 0) + + Scope (\_SB.PCI0) + { + /* PS/2 Keyboard */ + #include + } + + /* Star Labs EC */ + #include + + Scope (\_SB) + { + /* HID Driver */ + #include + + /* Suspend Methods */ + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/cezanne/fw.cfg b/src/mainboard/starlabs/cezanne/fw.cfg new file mode 100644 index 00000000000..6a2d236414f --- /dev/null +++ b/src/mainboard/starlabs/cezanne/fw.cfg @@ -0,0 +1,37 @@ +# PSP fw config file + +FIRMWARE_LOCATION ../amd_binaries/CZN/PSP +SOC_NAME Cezanne + +PSP_MP2CFG_FILE MP2FWConfig.sbin L2 +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn Lb +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin Lb +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin L2 +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin L1 +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin Lb +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn L2 +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin L2 +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin Lb +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin L2 +PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_CZN_A0.sbin L2 +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin Lb +PSP_TOKEN_UNLOCK_FILE TypeId0x22_SecureEmptyToken.bin Lb +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin Lb +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin L2 +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin L2 +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin L2 +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin L2 +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN.csbin Lb +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin Lb +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin L2 +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin Lb +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin L2 +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin Lb +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin L2 +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin L2 +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin L2 +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_CZN.sbin L2 +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin Lb +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin Lb +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin Lb +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin Lb diff --git a/src/mainboard/starlabs/cezanne/include/variants.h b/src/mainboard/starlabs/cezanne/include/variants.h new file mode 100644 index 00000000000..982da8655cc --- /dev/null +++ b/src/mainboard/starlabs/cezanne/include/variants.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include + +enum cmos_power_profile { + PP_POWER_SAVER = 0, + PP_BALANCED = 1, + PP_PERFORMANCE = 2, +}; +#define NUM_POWER_PROFILES 3 + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback); + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct soc_amd_gpio *variant_early_gpio_table(size_t *num); +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *num); +const struct soc_amd_gpio *variant_gpio_table(size_t *num); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/cezanne/mainboard.c b/src/mainboard/starlabs/cezanne/mainboard.c new file mode 100644 index 00000000000..db9574ec109 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/mainboard.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 15, PIRQ_NC }, + { PIRQ_B, 5, PIRQ_NC }, + { PIRQ_C, 10, PIRQ_NC }, + { PIRQ_D, 11, PIRQ_NC }, + { PIRQ_E, 15, PIRQ_NC }, + { PIRQ_F, 5, PIRQ_NC }, + { PIRQ_G, 10, PIRQ_NC }, + { PIRQ_H, 11, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + // The MISC registers are not interrupt numbers + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +struct chip_operations mainboard_ops = {}; diff --git a/src/mainboard/starlabs/cezanne/romstage.c b/src/mainboard/starlabs/cezanne/romstage.c new file mode 100644 index 00000000000..81d51810d9e --- /dev/null +++ b/src/mainboard/starlabs/cezanne/romstage.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback) +{ + const unsigned int power_profile = get_uint_option("power_profile", fallback); + return power_profile < NUM_POWER_PROFILES ? power_profile : fallback; +} + +void mb_pre_fspm(FSP_M_CONFIG *mcfg) +{ + const struct soc_amd_gpio *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + /* Update Power Profile based on CFR/CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + mcfg->system_configuration = 1; // 10W TDP + break; + case PP_BALANCED: + mcfg->system_configuration = 2; // 15W TDP + break; + case PP_PERFORMANCE: + mcfg->system_configuration = 3; // 25W TDP + break; + } +} diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.mk b/src/mainboard/starlabs/cezanne/variants/byte/Makefile.mk similarity index 57% rename from src/mainboard/google/myst/variants/baseboard/Makefile.mk rename to src/mainboard/starlabs/cezanne/variants/byte/Makefile.mk index 10b34e33793..7ee48b55062 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.mk +++ b/src/mainboard/starlabs/cezanne/variants/byte/Makefile.mk @@ -2,13 +2,9 @@ bootblock-y += gpio.c -ramstage-$(CONFIG_FW_CONFIG) += fw_config.c -ramstage-y += gpio.c -ramstage-y += port_descriptors.c - romstage-y += gpio.c romstage-y += port_descriptors.c -verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c - -smm-y += smihandler.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/starlabs/cezanne/variants/byte/devicetree.cb b/src/mainboard/starlabs/cezanne/variants/byte/devicetree.cb new file mode 100644 index 00000000000..e2ecf3be220 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/byte/devicetree.cb @@ -0,0 +1,124 @@ +chip soc/amd/cezanne + register "system_configuration" = "2" + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + # Memory + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # LAN (02.1 / CLKREQ1) + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # Auxiliary lane (01.2 / CLKREQ4) + register "gpp_clk_config[5]" = "GPP_CLK_REQ" # M.2 SSD (02.4 / CLKREQ5) + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # WIFI (02.2 / CLKREQ6) + + device domain 0 on + device ref iommu on end + device ref gpp_gfx_bridge_1 on # Auxiliary lane + end + device ref gpp_bridge_0 on # LAN + end + device ref gpp_bridge_1 on # WIFI + chip drivers/pcie/rtd3/device + register "name" = ""WIFI"" + device pci 00.0 on end + end + end + device ref gpp_bridge_3 on # M.2 SSD + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end + device ref gpp_bridge_a on + device ref gfx on end + device ref gfx_hda on end + device ref crypto on end + device ref xhci_0 on + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port3 on end + end + end + end + end + device ref xhci_1 on + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB 2.0 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 2.0 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""SD Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 6)" + device ref usb2_port7 on end + end + end + end + end + device ref acp on end + device ref hda on + subsystemid 0x14f1 0x0216 + end + end + device ref gpp_bridge_b on + device ref sata_0 on end + end + end + device ref data_fabric_0 on end + device ref data_fabric_1 on end + device ref data_fabric_2 on end + device ref data_fabric_3 on end + device ref data_fabric_4 on end + device ref data_fabric_5 on end + device ref data_fabric_6 on end + device ref data_fabric_7 on end + device ref uart_0 on end +end diff --git a/src/mainboard/starlabs/cezanne/variants/byte/gpio.c b/src/mainboard/starlabs/cezanne/variants/byte/gpio.c new file mode 100644 index 00000000000..ab6bac25918 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/byte/gpio.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Early pad configuration in bootblock */ +const struct soc_amd_gpio early_gpio_table[] = { + /* EGPIO26: PCIE_RST0# asserted */ + PAD_NFO(GPIO_26, PCIE_RST_L, LOW), + /* EGPIO27: PCIE_RST1# asserted */ + PAD_NFO(GPIO_27, PCIE_RST1_L, LOW), + /* EGPIO113: SMB SCL 0 */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* EGPIO114: SMB SDA 0 */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* EGPIO141: UART0 RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* EGPIO143: UART0 TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Romstage pad configuration. + * + * Keep this table limited to pads backed by the board schematic or by obvious + * SoC-native requirements. + */ +const struct soc_amd_gpio gpio_table[] = { + /* AGPIO0: PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* AGPIO1: SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* AGPIO2: PCIE_WAKE_N */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* AGPIO3: EC_SMI#_APU */ + PAD_GPI(GPIO_3, PULL_NONE), + /* AGPIO4: SSD_DET */ + PAD_GPI(GPIO_4, PULL_NONE), + /* AGPIO5: HDD_DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0, PULL_DOWN), + /* AGPIO6: M2_SSD_DEVSLP */ + PAD_NF(GPIO_6, DEVSLP1, PULL_DOWN), + /* AGPIO7: Not Connected */ + PAD_NC(GPIO_7), + /* AGPIO8: Not Connected */ + PAD_NC(GPIO_8), + /* AGPIO9: BIOS_S0_EC */ + PAD_GPO(GPIO_9, HIGH), + /* AGPIO10: S0A3 */ + PAD_NF(GPIO_10, S0A3, PULL_NONE), + /* AGPIO11: BLINK */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* AGPIO12: LLB_L */ + PAD_NF(GPIO_12, LLB_L, PULL_NONE), + /* AGPIO16: USB OC0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* AGPIO17: Unused */ + PAD_NC(GPIO_17), + /* AGPIO18: WLAN_WAKE_N */ + PAD_GPI(GPIO_18, PULL_UP), + /* AGPIO19: I2C 3 SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* AGPIO20: I2C 3 SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* AGPIO21: LPC_PD_L */ + PAD_NF(GPIO_21, LPC_PD_L, PULL_NONE), + /* AGPIO22: EC_SCI#_APU / LPC_PME_L */ + PAD_NF_SCI(GPIO_22, LPC_PME_L, PULL_NONE, EDGE_LOW), + /* AGPIO23: AC_PRESENT */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* AGPIO24: LAN_WAKE_N */ + PAD_GPI(GPIO_24, PULL_UP), + /* AGPIO26: PCIE_RST0# */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* AGPIO27: PCIE_RST1# */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* AGPIO29: SPI0 TPM 1 CS2 */ + /* AGPIO30: Not Connected */ + /* AGPIO31: Unused */ + PAD_NC(GPIO_31), + /* AGPIO32: LPC_RST */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), + /* AGPIO40: M.2_SSD_PEDET_R */ + PAD_GPI(GPIO_40, PULL_NONE), + /* AGPIO41: Unavailable */ + /* EGPIO42: Not Connected */ + PAD_NC(GPIO_42), + /* EGPIO67: SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* AGPIO68: Test Point 90 */ + /* EGPIO69: BT_RF_KILL_N */ + PAD_GPO(GPIO_69, HIGH), + /* EGPIO70: Test Point 89 */ + /* EGPIO74: LPCCLK0 */ + PAD_NF(GPIO_74, LPCCLK0, PULL_NONE), + /* EGPIO75: LPCCLK1 */ + PAD_NF(GPIO_75, LPCCLK1, PULL_NONE), + /* EGPIO76: SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* AGPIO84: Unused */ + PAD_NC(GPIO_84), + /* AGPIO85: Unused */ + PAD_NC(GPIO_85), + /* AGPIO86: EC_SMI_N */ + PAD_NF(GPIO_86, LPC_SMI_L, PULL_UP), + /* AGPIO87: LPC Serial Interrupt Request */ + PAD_NF(GPIO_87, SERIRQ, PULL_NONE), + /* AGPIO88: LPC Clock Run */ + PAD_NF(GPIO_88, LPC_CLKRUN_L, PULL_NONE), + /* AGPIO89: Unused GPIO output */ + PAD_GPO(GPIO_89, LOW), + /* AGPIO90: Unused GPIO output */ + PAD_GPO(GPIO_90, HIGH), + /* AGPIO91: WIFI_DISABLE_N */ + PAD_GPO(GPIO_91, HIGH), + /* AGPIO92: Unused GPIO output */ + PAD_GPO(GPIO_92, HIGH), + /* EGPIO104: LAD 0 */ + PAD_NF(GPIO_104, LAD0, PULL_NONE), + /* EGPIO105: LAD 1 */ + PAD_NF(GPIO_105, LAD1, PULL_NONE), + /* EGPIO106: LAD 2 */ + PAD_NF(GPIO_106, LAD2, PULL_NONE), + /* EGPIO107: LAD 3 */ + PAD_NF(GPIO_107, LAD3, PULL_NONE), + /* EGPIO108: ESPI Alert */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_UP), + /* EGPIO109: LFRAME */ + PAD_NF(GPIO_109, LFRAME_L, PULL_NONE), + /* AGPIO115: Clock Request 1 */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* AGPIO116: Clock Request 2 (Not Used) */ + PAD_NC(GPIO_116), + /* EGPIO120: Clock Request 5 */ + PAD_NF(GPIO_120, CLK_REQ5_L, PULL_UP), + /* EGPIO121: Clock Request 6 */ + PAD_NF(GPIO_121, CLK_REQ6_L, PULL_UP), + /* AGPIO129: ESPI_RESET_L / KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), + /* AGPIO130: SATA_ACT_L */ + PAD_NF(GPIO_130, SATA_ACT_L, PULL_UP), + /* EGPIO131: Clock Request 3 (Not Used) */ + PAD_NC(GPIO_131), + /* EGPIO132: Clock Request 4 */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), + /* EGPIO140: Not Connected */ + PAD_NC(GPIO_140), + /* EGPIO141: UART0 RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* EGPIO142: Test Point 96 */ + PAD_NC(GPIO_142), + /* EGPIO143: UART0 TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* EGPIO144: Not Connected */ + PAD_NC(GPIO_144), + /* EGPIO145: I2C 0 SCL (Not Used) */ + /* EGPIO146: I2C 0 SDA (Not Used) */ + /* EGPIO147: I2C 1 SCL (Not Used) */ + /* EGPIO147: I2C 1 SDA (Not Used) */ +}; + +const struct soc_amd_gpio *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/cezanne/variants/byte/hda_verb.c b/src/mainboard/starlabs/cezanne/variants/byte/hda_verb.c new file mode 100644 index 00000000000..3e75a32efd6 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/byte/hda_verb.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15098, /* Codec Vendor / Device ID: Conexant CX20632 */ + 0x14f10216, /* Subsystem ID */ + 14, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID: 0x14f10216 */ + AZALIA_SUBVENDOR(0, 0x14f10216), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + /* Front headset jack */ + AZALIA_PIN_CFG(0, 0x19, 0x042b1010), + /* Front mic jack */ + AZALIA_PIN_CFG(0, 0x1a, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + /* Board-specific analog path; keep reference firmware pin config */ + AZALIA_PIN_CFG(0, 0x1e, 0x90a61120), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x20, AZALIA_PIN_CFG_NC(0)), + /* Board-specific analog path; keep reference firmware pin config */ + AZALIA_PIN_CFG(0, 0x21, 0x90171110), + AZALIA_PIN_CFG(0, 0x26, AZALIA_PIN_CFG_NC(0)), + + /* Enable EAPD */ + 0x01870c02, + 0x01870c02, + 0x01870c02, + 0x01870c02, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/cezanne/variants/byte/port_descriptors.c b/src/mainboard/starlabs/cezanne/variants/byte/port_descriptors.c new file mode 100644 index 00000000000..82166ef5883 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/byte/port_descriptors.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define BYTE_DUMMY_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 23, \ + .device_number = 1, \ + .function_number = 1, \ + .clk_req = CLK_REQ0, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define BYTE_M2_NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 3, \ + .link_speed_capability = GEN_MAX, \ + .device_number = 2, \ + .function_number = 4, \ + .link_aspm = ASPM_DISABLED, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ5, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define BYTE_M2_SATA_DXIO_DESCRIPTOR { \ + .engine_type = SATA_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 2, \ + .end_logical_lane = 3, \ + .gpio_group_id = 1, \ + .channel_type = SATA_CHANNEL_LONG, \ +} + +#define BYTE_LAN_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 6, \ + .end_logical_lane = 6, \ + .link_speed_capability = GEN_MAX, \ + .device_number = 2, \ + .function_number = 1, \ + .link_aspm = ASPM_DISABLED, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ1, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define BYTE_WIFI_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 7, \ + .end_logical_lane = 7, \ + .link_speed_capability = GEN_MAX, \ + .device_number = 2, \ + .function_number = 2, \ + .link_aspm = ASPM_DISABLED, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ6, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define BYTE_SATA_DXIO_DESCRIPTOR { \ + .engine_type = SATA_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 9, \ + .gpio_group_id = 1, \ + .channel_type = SATA_CHANNEL_LONG, \ +} + +enum byte_dxio_port_idx { + BYTE_DXIO_DUMMY, + BYTE_DXIO_M2_SSD_DESC = 1, + BYTE_DXIO_LAN, + BYTE_DXIO_WIFI, + BYTE_DXIO_SATA_SSD, +}; + +static fsp_dxio_descriptor byte_dxio_descriptors[] = { + [BYTE_DXIO_DUMMY] = BYTE_DUMMY_DXIO_DESCRIPTOR, + [BYTE_DXIO_M2_SSD_DESC] = BYTE_M2_NVME_DXIO_DESCRIPTOR, + [BYTE_DXIO_LAN] = BYTE_LAN_DXIO_DESCRIPTOR, + [BYTE_DXIO_WIFI] = BYTE_WIFI_DXIO_DESCRIPTOR, + [BYTE_DXIO_SATA_SSD] = BYTE_SATA_DXIO_DESCRIPTOR, +}; + +static void byte_select_ssd_dxio_descriptor(void) +{ + fsp_dxio_descriptor *m2_ssd = &byte_dxio_descriptors[BYTE_DXIO_M2_SSD_DESC]; + + gpio_input(GPIO_40); + + /* + * The Y1 M.2 socket exposes PEDET as "OC-PCIe" with the socket note: + * "PCIe SSD: NC / SATA SSD: GND". With the board-side pull-up, PCIe + * devices leave the line high while SATA devices pull it low. + */ + if (gpio_get(GPIO_40)) { + printk(BIOS_INFO, "DXIO: detected PCIe SSD on lanes 0-3\n"); + return; + } + + printk(BIOS_INFO, "DXIO: detected SATA SSD; routing lanes 2-3 to SATA\n"); + *m2_ssd = (fsp_dxio_descriptor)BYTE_M2_SATA_DXIO_DESCRIPTOR; +} + +static fsp_ddi_descriptor byte_ddi_descriptors[] = { + /* DDI0: HDMI */ + { + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1, + }, + /* DDI1: HDMI */ + { + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2, + }, + /* DDI2: Not Used */ + { + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + /* DDI3: DisplayPort over USB-C */ + { + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + /* DDI4: Not Used */ + { + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, +}; + +void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + byte_select_ssd_dxio_descriptor(); + + *dxio_descs = byte_dxio_descriptors; + *dxio_num = ARRAY_SIZE(byte_dxio_descriptors); + *ddi_descs = byte_ddi_descriptors; + *ddi_num = ARRAY_SIZE(byte_ddi_descriptors); +} diff --git a/src/mainboard/starlabs/cezanne/variants/starbook/Makefile.mk b/src/mainboard/starlabs/cezanne/variants/starbook/Makefile.mk new file mode 100644 index 00000000000..7ee48b55062 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/starbook/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += port_descriptors.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/starlabs/cezanne/variants/starbook/devicetree.cb b/src/mainboard/starlabs/cezanne/variants/starbook/devicetree.cb new file mode 100644 index 00000000000..e06e2479cd9 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/starbook/devicetree.cb @@ -0,0 +1,153 @@ +chip soc/amd/cezanne + # Memory + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + + register "system_configuration" = "2" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_OFF" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SSD + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # WLAN + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_0 on # SSD + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end + device ref gpp_bridge_3 on # WIFI + chip drivers/pcie/rtd3/device + register "name" = ""WIFI"" + device pci 00.0 on end + end + end + device ref gpp_bridge_a on + device ref gfx on end + device ref gfx_hda on end + device ref crypto on end + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Rear Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal USB 2.0 Hub"" + register "type" = "UPC_TYPE_HUB" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb3_port0 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_69)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_69)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port3 on end + end + end + end + end + device ref acp on end + device ref hda on + subsystemid 0x14f1 0x0216 + end + end + device ref gpp_bridge_b on + device ref sata_1 on end + end + device ref gpp_bridge_c off end + device ref lpc_bridge on + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + end + device ref i2c_3 on + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref uart_0 on end +end diff --git a/src/mainboard/starlabs/cezanne/variants/starbook/gpio.c b/src/mainboard/starlabs/cezanne/variants/starbook/gpio.c new file mode 100644 index 00000000000..1d469b8a1c7 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/starbook/gpio.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Early pad configuration in bootblock */ +/* clang-format off */ +const struct soc_amd_gpio early_gpio_table[] = { + /* PCIe */ + PAD_NFO(GPIO_26, PCIE_RST_L, LOW), /* Reset asserted */ + PAD_GPO(GPIO_40, LOW), /* AUX reset asserted */ + + /* Debug Connector */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), /* RXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), /* TXD */ +}; +/* clang-format on */ + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* clang-format off */ +const struct soc_amd_gpio gpio_table[] = { + /* Power */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), /* Power Button */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), /* Platform Reset */ + PAD_NFO(GPIO_10, S0A3, HIGH), /* S0i3 Support */ + PAD_NF(GPIO_12, LLB_L, PULL_NONE), /* Battery Low */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* Charger Connected */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), /* Reset deasserted */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_UP), /* LPC Reset */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), /* EC Reset */ + PAD_NF(GPIO_130, SATA_ACT_L, PULL_UP), /* SATA Activity */ + PAD_GPI(GPIO_144, PULL_NONE), /* Shutdown */ + + /* EC and LPC */ + PAD_SCI(GPIO_8, PULL_UP, EDGE_HIGH), /* EC SCI */ + PAD_NF_SCI(GPIO_22, LPC_PME_L, PULL_UP, EDGE_HIGH), /* LPC PME */ + PAD_NF(GPIO_74, LPCCLK0, PULL_NONE), /* LPC Clock EC */ + PAD_NF(GPIO_75, LPCCLK1, PULL_NONE), /* LPC Clock 1 */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), /* SPI ROM Grant */ + PAD_NF(GPIO_86, LPC_SMI_L, PULL_UP), /* EC SMI */ + PAD_NF(GPIO_87, SERIRQ, PULL_NONE), /* LPC SERIRQ */ + PAD_NF(GPIO_88, LPC_CLKRUN_L, PULL_NONE), /* Clock Run */ + PAD_NF(GPIO_104, LAD0, PULL_NONE), /* LPC LAD0 */ + PAD_NF(GPIO_105, LAD1, PULL_NONE), /* LPC LAD1 */ + PAD_NF(GPIO_106, LAD2, PULL_NONE), /* LPC LAD2 */ + PAD_NF(GPIO_107, LAD3, PULL_NONE), /* LPC LAD3 */ + PAD_NF(GPIO_109, LFRAME_L, PULL_NONE), /* LPC Frame */ + + /* SSD */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_HIGH), /* Wake */ + PAD_GPI(GPIO_4, PULL_NONE), /* Detect */ + PAD_NF(GPIO_5, DEVSLP0, PULL_DOWN), /* Device Sleep */ + PAD_GPO(GPIO_40, HIGH), /* AUX reset deasserted */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), /* Clock Request */ + + /* Wireless */ + PAD_SCI(GPIO_18, PULL_UP, EDGE_HIGH), /* WLAN Wake */ + PAD_GPO(GPIO_69, HIGH), /* Bluetooth RF Kill */ + PAD_GPO(GPIO_91, HIGH), /* WiFi Disable */ + PAD_NF(GPIO_121, CLK_REQ6_L, PULL_UP), /* Clock Request */ + + /* Touchpad */ + PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), /* Interrupt */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* Clock */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* Data */ + + /* High-Definition Audio */ + PAD_NF(GPIO_108, GPIOxx, PULL_UP), /* Interrupt */ + + /* SMBus */ + PAD_NF(GPIO_113, SCL0, PULL_NONE), /* Clock */ + PAD_NF(GPIO_114, SDA0, PULL_NONE), /* Data */ + + /* USB */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), /* Type-C VBUS OC */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), /* USB OC1 */ + + /* Not connected */ + PAD_NC(GPIO_3), + PAD_NC(GPIO_6), + PAD_NC(GPIO_7), + PAD_NC(GPIO_11), + PAD_NC(GPIO_21), + PAD_NC(GPIO_24), + PAD_NC(GPIO_27), + PAD_NC(GPIO_29), + PAD_NC(GPIO_30), + PAD_NC(GPIO_31), + PAD_NC(GPIO_42), + PAD_NC(GPIO_67), + PAD_NC(GPIO_68), + PAD_NC(GPIO_70), + PAD_NC(GPIO_84), + PAD_NC(GPIO_85), + PAD_NC(GPIO_89), + PAD_NC(GPIO_90), + PAD_NC(GPIO_92), + PAD_NC(GPIO_116), + PAD_NC(GPIO_120), + PAD_NC(GPIO_131), + PAD_NC(GPIO_132), + PAD_NC(GPIO_140), + PAD_NC(GPIO_142), + PAD_NC(GPIO_145), + PAD_NC(GPIO_146), + PAD_NC(GPIO_147), + PAD_NC(GPIO_148), + PAD_NC(GPIO_256), + PAD_NC(GPIO_257), + PAD_NC(GPIO_258), + PAD_NC(GPIO_259), + PAD_NC(GPIO_260), + PAD_NC(GPIO_261), + PAD_NC(GPIO_262), + PAD_NC(GPIO_263), + PAD_NC(GPIO_264), + PAD_NC(GPIO_265), + PAD_NC(GPIO_266), + PAD_NC(GPIO_267), + PAD_NC(GPIO_268), + PAD_NC(GPIO_269), + PAD_NC(GPIO_270), + PAD_NC(GPIO_271), +}; +/* clang-format on */ + + +/* Pad configuration in romstage. */ +const struct soc_amd_gpio *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/cezanne/variants/starbook/hda_verb.c b/src/mainboard/starlabs/cezanne/variants/starbook/hda_verb.c new file mode 100644 index 00000000000..058d7f04be1 --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/starbook/hda_verb.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15098, /* Codec Vendor / Device ID: Conexant CX20632 */ + 0x14f10216, /* Subsystem ID */ + 15, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID: 0x14f10216 */ + AZALIA_SUBVENDOR(0, 0x14f10216), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_TOP, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 4, + 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, + 0 + )), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_TOP, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, + 0 + )), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x20, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x26, AZALIA_PIN_CFG_NC(0)), + + /* Enable EAPD */ + 0x01870c02, + 0x01870c02, + 0x01870c02, + 0x01870c02, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/cezanne/variants/starbook/port_descriptors.c b/src/mainboard/starlabs/cezanne/variants/starbook/port_descriptors.c new file mode 100644 index 00000000000..736f61bd60a --- /dev/null +++ b/src/mainboard/starlabs/cezanne/variants/starbook/port_descriptors.c @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#define NVME_DET_GPIO GPIO_4 + +#define STARBOOK_WIFI_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 6, \ + .end_logical_lane = 6, \ + .link_speed_capability = GEN_MAX, \ + .device_number = 2, \ + .function_number = 4, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ6, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define STARBOOK_M2_SATA_DXIO_DESCRIPTOR { \ + .engine_type = SATA_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 9, \ + .channel_type = SATA_CHANNEL_LONG, \ +} + +#define STARBOOK_M2_NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 11, \ + .link_speed_capability = GEN_MAX, \ + .device_number = 2, \ + .function_number = 1, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ1, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +#define STARBOOK_DUMMY_MXM_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 23, \ + .turn_off_unused_lanes = true, \ + .port_params = { PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122 }, \ +} + +enum { + STARLABS_CFR_ASPM_DISABLE = 1, + STARLABS_CFR_ASPM_L0S, + STARLABS_CFR_ASPM_L1, + STARLABS_CFR_ASPM_L0S_L1, + STARLABS_CFR_ASPM_AUTO, +}; + +enum { + STARLABS_CFR_L1SS_DISABLED = 1, + STARLABS_CFR_L1SS_L1_1, + STARLABS_CFR_L1SS_L1_2, +}; + +enum starbook_dxio_port_idx { + STARBOOK_DXIO_WIFI, + STARBOOK_DXIO_M2_STORAGE, + STARBOOK_DXIO_DUMMY_MXM, +}; + +static fsp_dxio_descriptor starbook_dxio_descriptors[] = { + [STARBOOK_DXIO_WIFI] = STARBOOK_WIFI_DXIO_DESCRIPTOR, + [STARBOOK_DXIO_M2_STORAGE] = STARBOOK_M2_NVME_DXIO_DESCRIPTOR, + [STARBOOK_DXIO_DUMMY_MXM] = STARBOOK_DUMMY_MXM_DXIO_DESCRIPTOR, +}; + +static void starbook_set_dxio_aspm(fsp_dxio_descriptor *desc, unsigned int aspm) +{ + desc->link_aspm = ASPM_L1; + + switch (aspm) { + case STARLABS_CFR_ASPM_DISABLE: + desc->link_aspm = ASPM_DISABLED; + break; + case STARLABS_CFR_ASPM_L0S: + desc->link_aspm = ASPM_L0s; + break; + case STARLABS_CFR_ASPM_L1: + desc->link_aspm = ASPM_L1; + break; + case STARLABS_CFR_ASPM_L0S_L1: + desc->link_aspm = ASPM_L0sL1; + break; + case STARLABS_CFR_ASPM_AUTO: + default: + break; + } +} + +static void starbook_set_dxio_l1ss(fsp_dxio_descriptor *desc, unsigned int l1ss) +{ + desc->link_aspm_L1_1 = true; + desc->link_aspm_L1_2 = true; + + switch (l1ss) { + case STARLABS_CFR_L1SS_DISABLED: + desc->link_aspm_L1_1 = false; + desc->link_aspm_L1_2 = false; + break; + case STARLABS_CFR_L1SS_L1_1: + desc->link_aspm_L1_1 = true; + desc->link_aspm_L1_2 = false; + break; + case STARLABS_CFR_L1SS_L1_2: + default: + break; + } +} + +static void starbook_update_dxio_power_management(void) +{ + fsp_dxio_descriptor *wifi = &starbook_dxio_descriptors[STARBOOK_DXIO_WIFI]; + fsp_dxio_descriptor *ssd = &starbook_dxio_descriptors[STARBOOK_DXIO_M2_STORAGE]; + + if (get_uint_option("wifi", 1) == 0) { + wifi->engine_type = UNUSED_ENGINE; + wifi->port_present = false; + } + + wifi->clk_req = get_uint_option("pciexp_wifi_clk_pm", 1) ? CLK_REQ6 : CLK_ENABLE; + if (ssd->engine_type == PCIE_ENGINE) + ssd->clk_req = get_uint_option("pciexp_ssd_clk_pm", 1) ? CLK_REQ1 : CLK_ENABLE; + + starbook_set_dxio_aspm(wifi, get_uint_option("pciexp_wifi_aspm", + STARLABS_CFR_ASPM_L1)); + if (ssd->engine_type == PCIE_ENGINE) + starbook_set_dxio_aspm(ssd, get_uint_option("pciexp_ssd_aspm", + STARLABS_CFR_ASPM_L1)); + + starbook_set_dxio_l1ss(wifi, STARLABS_CFR_L1SS_DISABLED); + if (ssd->engine_type == PCIE_ENGINE) + starbook_set_dxio_l1ss(ssd, get_uint_option("pciexp_ssd_l1ss", + STARLABS_CFR_L1SS_L1_2)); +} + +static void starbook_select_m2_storage_dxio(void) +{ + gpio_input(NVME_DET_GPIO); + + if (gpio_get(NVME_DET_GPIO)) { + printk(BIOS_INFO, "DXIO: detected PCIe SSD on lanes 8-11\n"); + } else { + printk(BIOS_INFO, "DXIO: detected SATA SSD; routing lanes 8-9 to SATA\n"); + starbook_dxio_descriptors[STARBOOK_DXIO_M2_STORAGE] = + (fsp_dxio_descriptor)STARBOOK_M2_SATA_DXIO_DESCRIPTOR; + } +} + +static fsp_ddi_descriptor starbook_ddi_descriptors[] = { + /* DDI0: eDP */ + { + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + /* DDI1: HDMI */ + { + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + /* DDI2: Not Used */ + { + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + /* DDI3: Not Used */ + { + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + /* DDI4: Display Port (via Type-C) */ + { + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + starbook_select_m2_storage_dxio(); + starbook_update_dxio_power_management(); + + *dxio_descs = starbook_dxio_descriptors; + *dxio_num = ARRAY_SIZE(starbook_dxio_descriptors); + *ddi_descs = starbook_ddi_descriptors; + *ddi_num = ARRAY_SIZE(starbook_ddi_descriptors); +} diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig index 5501d43efe4..74052ca75f0 100644 --- a/src/mainboard/starlabs/common/Kconfig +++ b/src/mainboard/starlabs/common/Kconfig @@ -2,17 +2,46 @@ if VENDOR_STARLABS +config EDK2_BOOTSPLASH_FILE + string + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +config STARLABS_MEMORY_SETTINGS_VERSION + bool + default y if PLATFORM_USES_FSP2_0 && CACHE_MRC_SETTINGS + select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + menu "Star Labs Settings" config BOOTMEDIA_SMM_BWP - def_bool y + bool + default y if SOC_INTEL_COMMON_BLOCK_SMM config BOOTMEDIA_SMM_BWP_RUNTIME_OPTION - def_bool y + bool + depends on BOOTMEDIA_SMM_BWP + default y if SOC_INTEL_COMMON_BLOCK_SMM + +config USE_LEGACY_8254_TIMER + default n if VENDOR_STARLABS + +config USE_PC_CMOS_ALTCENTURY + default n if VENDOR_STARLABS config DRIVERS_EFI_FW_INFO def_bool y +config STARLABS_COMMON_POWERCAP + bool + default y if SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + +config STARLABS_COMMON_CFR + bool + default y if CPU_INTEL_COMMON + +config STARLABS_LEGACY_PL4 + bool + config STARLABS_NVME_POWER_SEQUENCE bool "Enable NVMe/M.2 slot power sequence" depends on SOC_INTEL_COMMON_BLOCK_GPIO @@ -34,6 +63,9 @@ config STARLABS_NVME_POWER_SEQUENCE `variant_nvme_power_sequence_pads()` and `variant_nvme_power_sequence_post_pads()`. +config TCG_OPAL_S3_UNLOCK + default y + config MB_COMMON_DIR string default "starlabs/common" @@ -48,6 +80,9 @@ config STARLABS_ACPI_EFI_OPTION_SMI (e.g. keyboard backlight and trackpad state) to the UEFI variable store via an SMM APMC SMI handler. +config SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE + default n + source "src/mainboard/starlabs/common/hda/Kconfig" endmenu diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk index 6887c47a7d7..6bbf96bf2d8 100644 --- a/src/mainboard/starlabs/common/Makefile.mk +++ b/src/mainboard/starlabs/common/Makefile.mk @@ -2,6 +2,7 @@ subdirs-$(CONFIG_VENDOR_STARLABS) += cfr subdirs-$(CONFIG_VENDOR_STARLABS) += hda +subdirs-$(CONFIG_BOARD_STARLABS_STARFIGHTER_SERIES) += touchpad subdirs-$(CONFIG_VENDOR_STARLABS) += powercap subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux subdirs-$(CONFIG_VENDOR_STARLABS) += smbios diff --git a/src/mainboard/starlabs/common/cfr/Makefile.mk b/src/mainboard/starlabs/common/cfr/Makefile.mk index 00b8b806b30..19be2cdd4b6 100644 --- a/src/mainboard/starlabs/common/cfr/Makefile.mk +++ b/src/mainboard/starlabs/common/cfr/Makefile.mk @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/cfr -ramstage-y += cfr.c +ramstage-$(CONFIG_STARLABS_COMMON_CFR) += cfr.c diff --git a/src/mainboard/starlabs/common/cfr/cfr.c b/src/mainboard/starlabs/common/cfr/cfr.c index 44ee68323ee..5fe65d6854e 100644 --- a/src/mainboard/starlabs/common/cfr/cfr.c +++ b/src/mainboard/starlabs/common/cfr/cfr.c @@ -2,8 +2,65 @@ #include #include +#include +#include +#include #include +static char pl1_helptext[160]; +static char pl2_helptext[160]; +static char pl4_helptext[160]; +static char tcc_temp_helptext[192]; + +static void update_power_limit_helptext(struct sm_object *new_obj, + const struct starlabs_power_profile_bounds *bounds) +{ + const char *opt_name; + char *helptext = NULL; + size_t helptext_size = 0; + + if (!new_obj || !bounds || new_obj->kind != SM_OBJ_NUMBER) + return; + + opt_name = new_obj->sm_number.opt_name; + + if (strcmp(opt_name, "pl1_override") == 0) { + helptext = pl1_helptext; + helptext_size = sizeof(pl1_helptext); + snprintf(helptext, helptext_size, + "Long-duration CPU package power limit in Watts. " + "Range: %u-%u W. Default: %u W.", + bounds->min_pl1, bounds->max_pl1, bounds->default_pl1); + } else if (strcmp(opt_name, "pl2_override") == 0) { + helptext = pl2_helptext; + helptext_size = sizeof(pl2_helptext); + snprintf(helptext, helptext_size, + "Short-duration CPU package power limit in Watts. " + "Range: %u-%u W. Default: %u W. " + "Runtime clamped so PL2 never exceeds PL4.", + bounds->min_pl2, bounds->max_pl2, bounds->default_pl2); + } else if (strcmp(opt_name, "pl4_override") == 0) { + helptext = pl4_helptext; + helptext_size = sizeof(pl4_helptext); + snprintf(helptext, helptext_size, + "Hard CPU package power limit in Watts. " + "Range: %u-%u W. Default: %u W.", + bounds->min_pl4, bounds->max_pl4, bounds->default_pl4); + } else if (strcmp(opt_name, "tcc_temp") == 0) { + helptext = tcc_temp_helptext; + helptext_size = sizeof(tcc_temp_helptext); + snprintf(helptext, helptext_size, + "CPU temperature in Celsius where thermal throttling starts. " + "Range: %u-%u C. Default: %u C. " + "Higher values let the CPU run hotter before throttling.", + bounds->min_tcc_temp, bounds->max_tcc_temp, + bounds->default_tcc_temp); + } + + if (helptext) + new_obj->sm_number.ui_helptext = helptext; +} + void __weak cfr_card_reader_update(struct sm_object *new_obj) { (void)new_obj; @@ -14,6 +71,52 @@ void __weak cfr_touchscreen_update(struct sm_object *new_obj) (void)new_obj; } +void starlabs_cfr_custom_profile_update(struct sm_object *new_obj) +{ + struct starlabs_power_profile_bounds bounds; + + if (!new_obj || new_obj->kind != SM_OBJ_NUMBER) + return; + + if (!starlabs_get_power_profile_bounds(config_of_soc(), &bounds)) + return; + + if (strcmp(new_obj->sm_number.opt_name, "pl1_override") == 0) { + new_obj->sm_number.default_value = bounds.default_pl1; + new_obj->sm_number.min = bounds.min_pl1; + new_obj->sm_number.max = bounds.max_pl1; + new_obj->sm_number.step = 1; + update_power_limit_helptext(new_obj, &bounds); + return; + } + + if (strcmp(new_obj->sm_number.opt_name, "pl2_override") == 0) { + new_obj->sm_number.default_value = bounds.default_pl2; + new_obj->sm_number.min = bounds.min_pl2; + new_obj->sm_number.max = bounds.max_pl2; + new_obj->sm_number.step = 1; + update_power_limit_helptext(new_obj, &bounds); + return; + } + + if (strcmp(new_obj->sm_number.opt_name, "pl4_override") == 0) { + new_obj->sm_number.default_value = bounds.default_pl4; + new_obj->sm_number.min = bounds.min_pl4; + new_obj->sm_number.max = bounds.max_pl4; + new_obj->sm_number.step = 1; + update_power_limit_helptext(new_obj, &bounds); + return; + } + + if (strcmp(new_obj->sm_number.opt_name, "tcc_temp") == 0) { + new_obj->sm_number.default_value = bounds.default_tcc_temp; + new_obj->sm_number.min = bounds.min_tcc_temp; + new_obj->sm_number.max = bounds.max_tcc_temp; + new_obj->sm_number.step = 1; + update_power_limit_helptext(new_obj, &bounds); + } +} + static const struct cfr_default_override starlabs_cfr_overrides[] = { CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_L0S_L1), CFR_OVERRIDE_END diff --git a/src/mainboard/starlabs/common/gnvs.c b/src/mainboard/starlabs/common/gnvs.c index 7e119470ab5..1fe0b8c85c0 100644 --- a/src/mainboard/starlabs/common/gnvs.c +++ b/src/mainboard/starlabs/common/gnvs.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include size_t size_of_dnvs(void) diff --git a/src/mainboard/starlabs/common/hda/dmic.c b/src/mainboard/starlabs/common/hda/dmic.c index cf1b243866e..bf09f8a5f9f 100644 --- a/src/mainboard/starlabs/common/hda/dmic.c +++ b/src/mainboard/starlabs/common/hda/dmic.c @@ -14,8 +14,9 @@ static void disable_microphone(uint8_t *base) azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb)); } -void mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid) +void __weak mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid) { + (void)viddid; if (get_uint_option("microphone", 1) == 0) disable_microphone(base); } diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h index 1a0dabbe867..b8b13b2809c 100644 --- a/src/mainboard/starlabs/common/include/common/cfr.h +++ b/src/mainboard/starlabs/common/include/common/cfr.h @@ -4,11 +4,14 @@ #define _STARLABS_CMN_CFR_H_ #include +#include #include #include +#include void cfr_card_reader_update(struct sm_object *new_obj); void cfr_touchscreen_update(struct sm_object *new_obj); +void starlabs_cfr_custom_profile_update(struct sm_object *new_obj); void starlabs_cfr_register_overrides(void); static const struct sm_object accelerometer = SM_DECLARE_BOOL({ @@ -83,18 +86,147 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({ .default_value = true, }); +static const struct sm_object hda_dsp = SM_DECLARE_BOOL({ + .opt_name = "hda_dsp", + .ui_name = "Digital Signal Processor", + .ui_helptext = "Enable or disable the Intel HD Audio Digital Signal Processor.\n" + "Recommended to disable when booting Windows.", + .default_value = true, +}); + +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || \ + CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE) +static const struct sm_object ibecc = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ibecc_enable", + .ui_name = "In-Band ECC", + .ui_helptext = "Enable or disable In-Band ECC. Enabling this option reduces " + "available RAM because memory is reserved for ECC data.", + .default_value = false, +}); +#endif + static const struct sm_object power_profile = SM_DECLARE_ENUM({ .opt_name = "power_profile", .ui_name = "Power Profile", - .ui_helptext = "Select whether to maximize performance, battery life or both.", - .default_value = PP_PERFORMANCE, + .ui_helptext = "Choose maximum battery life, balanced behaviour, " + "maximum performance, or custom CPU power and " + "thermal settings.", + .default_value = PP_BALANCED, .values = (const struct sm_enum_value[]) { { "Power Saver", PP_POWER_SAVER }, { "Balanced", PP_BALANCED }, { "Performance", PP_PERFORMANCE }, + { "Custom", PP_CUSTOM }, SM_ENUM_VALUE_END }, }); +static const struct sm_object pl1_override = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "pl1_override", + .ui_name = "Sustained CPU Power Limit (PL1, W)", + .ui_helptext = "Long-duration CPU package power limit in Watts.", + .default_value = 0, + .step = 1, +}, WITH_DEP_VALUES(&power_profile, PP_CUSTOM), + WITH_CALLBACK(starlabs_cfr_custom_profile_update)); + +static const struct sm_object pl2_override = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "pl2_override", + .ui_name = "Short Boost CPU Power Limit (PL2, W)", + .ui_helptext = "Short-duration CPU package power limit in Watts. " + "Runtime clamped so PL2 never exceeds PL4.", + .default_value = 0, + .step = 1, +}, WITH_DEP_VALUES(&power_profile, PP_CUSTOM), + WITH_CALLBACK(starlabs_cfr_custom_profile_update)); + +static const struct sm_object pl4_override = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "pl4_override", + .ui_name = "Hard CPU Power Limit (PL4, W)", + .ui_helptext = "Hard CPU package power limit in Watts. This can only be reduced " + "from the stock board limit.", + .default_value = 0, + .step = 1, +}, WITH_DEP_VALUES(&power_profile, PP_CUSTOM), + WITH_CALLBACK(starlabs_cfr_custom_profile_update)); + +static const struct sm_object tcc_temp = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "tcc_temp", + .ui_name = "CPU Thermal Throttling Temperature (TCC, C)", + .ui_helptext = "CPU temperature in Celsius where thermal throttling " + "starts. Higher values let the CPU run hotter " + "before throttling.", + .default_value = 0, + .step = 1, +}, WITH_DEP_VALUES(&power_profile, PP_CUSTOM), + WITH_CALLBACK(starlabs_cfr_custom_profile_update)); + +static void starlabs_update_pcie_clk_pm(struct sm_object *new_obj) +{ + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)) + new_obj->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS; +} + +static void starlabs_update_pcie_aspm(struct sm_object *new_obj) +{ + if (!CONFIG(PCIEXP_ASPM)) + new_obj->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS; +} + +static void starlabs_update_pcie_l1ss(struct sm_object *new_obj) +{ + if (!CONFIG(PCIEXP_ASPM) || !CONFIG(PCIEXP_L1_SUB_STATE)) + new_obj->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS; +} + +#define STARLABS_DECLARE_PCIE_PM_OBJECTS(_suffix, _label) \ +static const struct sm_object pciexp_##_suffix##_clk_pm = SM_DECLARE_BOOL({ \ + .opt_name = "pciexp_" #_suffix "_clk_pm", \ + .ui_name = _label " Clock Power Management", \ + .ui_helptext = "Enable or disable clock power management for " _label ".", \ + .default_value = true, \ +}, WITH_CALLBACK(starlabs_update_pcie_clk_pm)); \ + \ +static const struct sm_object pciexp_##_suffix##_aspm = SM_DECLARE_ENUM({ \ + .opt_name = "pciexp_" #_suffix "_aspm", \ + .ui_name = _label " ASPM", \ + .ui_helptext = "Control Active State Power Management for " _label ".", \ + .default_value = ASPM_L0S_L1, \ + .values = (const struct sm_enum_value[]) { \ + { "Disabled", ASPM_DISABLE }, \ + { "L0s", ASPM_L0S }, \ + { "L1", ASPM_L1 }, \ + { "L0sL1", ASPM_L0S_L1 }, \ + { "Auto", ASPM_AUTO }, \ + SM_ENUM_VALUE_END }, \ +}, WITH_DEP_VALUES(&pciexp_##_suffix##_clk_pm, true), \ + WITH_CALLBACK(starlabs_update_pcie_aspm)); \ + \ +static const struct sm_object pciexp_##_suffix##_l1ss = SM_DECLARE_ENUM({ \ + .opt_name = "pciexp_" #_suffix "_l1ss", \ + .ui_name = _label " L1 Substates", \ + .ui_helptext = "Control PCIe L1 substates for " _label ".", \ + .default_value = L1_SS_L1_2, \ + .values = (const struct sm_enum_value[]) { \ + { "Disabled", L1_SS_DISABLED }, \ + { "L1.1", L1_SS_L1_1 }, \ + { "L1.2", L1_SS_L1_2 }, \ + SM_ENUM_VALUE_END }, \ +}, WITH_DEP_VALUES(&pciexp_##_suffix##_clk_pm, true), \ + WITH_CALLBACK(starlabs_update_pcie_l1ss)) + +STARLABS_DECLARE_PCIE_PM_OBJECTS(wifi, "WiFi"); +STARLABS_DECLARE_PCIE_PM_OBJECTS(ssd, "SSD"); +STARLABS_DECLARE_PCIE_PM_OBJECTS(ssd2, "SSD 2"); +STARLABS_DECLARE_PCIE_PM_OBJECTS(lan1, "LAN 1"); +STARLABS_DECLARE_PCIE_PM_OBJECTS(lan2, "LAN 2"); + +#undef STARLABS_DECLARE_PCIE_PM_OBJECTS + static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({ .opt_name = "s0ix_enable", .ui_name = "Modern Standby (S0ix)", @@ -111,6 +243,66 @@ static const struct sm_object thunderbolt = SM_DECLARE_BOOL({ .default_value = true, }); +static const struct sm_object touchpad_haptics = SM_DECLARE_ENUM({ + .opt_name = "touchpad_haptics", + .ui_name = "Touchpad Vibration Intensity", + .ui_helptext = "Choose how strong the touchpad click vibration feels.", + .default_value = STARLABS_TOUCHPAD_HAPTICS_DEFAULT, + .values = (const struct sm_enum_value[]) { + { "Off", 0 }, + { "Low", 1 }, + { "Medium", 2 }, + { "High", 3 }, + { "Maximum", 4 }, + SM_ENUM_VALUE_END, + }, +}); + +static const struct sm_object touchpad_force_press = SM_DECLARE_ENUM({ + .opt_name = "touchpad_force_press", + .ui_name = "Touchpad Click Force", + .ui_helptext = "Choose how much force it takes to click the touchpad.", + .default_value = STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT, + .values = (const struct sm_enum_value[]) { + { "Minimal", STARLABS_TOUCHPAD_FORCE_MINIMAL }, + { "Low", STARLABS_TOUCHPAD_FORCE_LOW }, + { "Average", STARLABS_TOUCHPAD_FORCE_AVERAGE }, + { "High", STARLABS_TOUCHPAD_FORCE_HIGH }, + { "Hulk", STARLABS_TOUCHPAD_FORCE_HULK }, + SM_ENUM_VALUE_END, + }, +}); + +static const struct sm_object touchpad_force_release = SM_DECLARE_ENUM({ + .opt_name = "touchpad_force_release", + .ui_name = "Touchpad Release Force", + .ui_helptext = "Choose how much force it takes for the touchpad click to release.", + .default_value = STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT, + .values = (const struct sm_enum_value[]) { + { "Minimal", STARLABS_TOUCHPAD_FORCE_MINIMAL }, + { "Low", STARLABS_TOUCHPAD_FORCE_LOW }, + { "Average", STARLABS_TOUCHPAD_FORCE_AVERAGE }, + { "High", STARLABS_TOUCHPAD_FORCE_HIGH }, + { "Hulk", STARLABS_TOUCHPAD_FORCE_HULK }, + SM_ENUM_VALUE_END, + }, +}); + +static const struct sm_object touchpad_report_rate = SM_DECLARE_ENUM({ + .opt_name = "touchpad_report_rate", + .ui_name = "Touchpad Tracking Speed", + .ui_helptext = "Choose how quickly the touchpad reports movement.", + .default_value = STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT, + .values = (const struct sm_enum_value[]) { + { "Relaxed", STARLABS_TOUCHPAD_RATE_RELAXED }, + { "Balanced", STARLABS_TOUCHPAD_RATE_BALANCED }, + { "Fast", STARLABS_TOUCHPAD_RATE_FAST }, + { "Ludicrous", STARLABS_TOUCHPAD_RATE_LUDICROUS }, + { "Plaid", STARLABS_TOUCHPAD_RATE_PLAID }, + SM_ENUM_VALUE_END, + }, +}); + static const struct sm_object touchscreen = SM_DECLARE_BOOL({ .opt_name = "touchscreen", .ui_name = "Touchscreen", @@ -141,8 +333,8 @@ static const struct sm_object webcam = SM_DECLARE_BOOL({ static const struct sm_object wifi = SM_DECLARE_BOOL({ .opt_name = "wifi", - .ui_name = "WiFi", - .ui_helptext = "Enable or disable the built-in WiFi", + .ui_name = "Wi-Fi", + .ui_helptext = "Enable or disable the built-in Wi-Fi", .default_value = true, }); diff --git a/src/mainboard/starlabs/common/include/common/memory.h b/src/mainboard/starlabs/common/include/common/memory.h new file mode 100644 index 00000000000..ce405b262ce --- /dev/null +++ b/src/mainboard/starlabs/common/include/common/memory.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_STARLABS_COMMON_MEMORY_H +#define MAINBOARD_STARLABS_COMMON_MEMORY_H + +#include +#include + +#define STARLABS_MEMORY_SPEED_MAX 2 + +static inline unsigned int starlabs_get_memory_speed_option(unsigned int default_speed) +{ + unsigned int speed = get_uint_option("memory_speed", default_speed); + + if (speed > STARLABS_MEMORY_SPEED_MAX) { + printk(BIOS_WARNING, "Invalid memory_speed option %u, using %u\n", speed, + STARLABS_MEMORY_SPEED_MAX); + speed = STARLABS_MEMORY_SPEED_MAX; + } + + return speed; +} + +#endif /* MAINBOARD_STARLABS_COMMON_MEMORY_H */ diff --git a/src/mainboard/starlabs/common/include/common/powercap.h b/src/mainboard/starlabs/common/include/common/powercap.h index 2447ce9851e..5d8ae5dcd97 100644 --- a/src/mainboard/starlabs/common/include/common/powercap.h +++ b/src/mainboard/starlabs/common/include/common/powercap.h @@ -9,8 +9,27 @@ enum cmos_power_profile { PP_POWER_SAVER = 0, PP_BALANCED = 1, PP_PERFORMANCE = 2, + PP_CUSTOM = 3, }; -#define NUM_POWER_PROFILES 3 +#define NUM_POWER_PROFILES 4 + +struct starlabs_power_profile_bounds { + uint32_t default_pl1; + uint32_t min_pl1; + uint32_t max_pl1; + uint32_t default_pl2; + uint32_t min_pl2; + uint32_t max_pl2; + uint32_t default_pl4; + uint32_t min_pl4; + uint32_t max_pl4; + uint32_t default_tcc_temp; + uint32_t min_tcc_temp; + uint32_t max_tcc_temp; +}; + +bool starlabs_get_power_profile_bounds(const config_t *cfg, + struct starlabs_power_profile_bounds *bounds); void update_power_limits(config_t *cfg); diff --git a/src/mainboard/starlabs/common/include/common/touchpad.h b/src/mainboard/starlabs/common/include/common/touchpad.h new file mode 100644 index 00000000000..11f253672ee --- /dev/null +++ b/src/mainboard/starlabs/common/include/common/touchpad.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _STARLABS_CMN_TOUCHPAD_H_ +#define _STARLABS_CMN_TOUCHPAD_H_ + +#include + +#define STARLABS_TOUCHPAD_HAPTICS_DEFAULT 2 +#define STARLABS_TOUCHPAD_HAPTICS_MAX 4 + +#define STARLABS_TOUCHPAD_FORCE_MINIMAL 50 +#define STARLABS_TOUCHPAD_FORCE_LOW 125 +#define STARLABS_TOUCHPAD_FORCE_AVERAGE 250 +#define STARLABS_TOUCHPAD_FORCE_HIGH 350 +#define STARLABS_TOUCHPAD_FORCE_HULK 500 + +#define STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT STARLABS_TOUCHPAD_FORCE_AVERAGE +#define STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT STARLABS_TOUCHPAD_FORCE_MINIMAL + +#define STARLABS_TOUCHPAD_RATE_RELAXED 80 +#define STARLABS_TOUCHPAD_RATE_BALANCED 111 +#define STARLABS_TOUCHPAD_RATE_FAST 160 +#define STARLABS_TOUCHPAD_RATE_LUDICROUS 208 +#define STARLABS_TOUCHPAD_RATE_PLAID 255 + +#define STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT 111 +#define STARLABS_TOUCHPAD_REPORT_RATE_MIN 1 +#define STARLABS_TOUCHPAD_REPORT_RATE_MAX 255 + +#define STARLABS_TOUCHPAD_HID_DESC_REG 0x0020 +#define STARLABS_TOUCHPAD_I2C_ADDR 0x2c +#define STARLABS_TOUCHPAD_I2C_BUS 0 + +#define STARLABS_TOUCHPAD_HAPTICS_REPORT_ID 0x0a +#define STARLABS_TOUCHPAD_FORCE_REPORT_ID 0x0b +#define STARLABS_TOUCHPAD_USER_REG_REPORT_ID 0x43 +#define STARLABS_TOUCHPAD_USER_REG_BANK 0x00 +#define STARLABS_TOUCHPAD_USER_REG_ADDR_RATE 0x12 + +/* + * The HID descriptor may not be live immediately when this hook runs, but + * these command/data registers are stable enough to perform early HID bring-up. + */ +#define STARLABS_TOUCHPAD_FALLBACK_CMD_REG 0x0022 +#define STARLABS_TOUCHPAD_FALLBACK_DATA_REG 0x0023 + +#define STARLABS_TOUCHPAD_RETRIES 3 +#define STARLABS_TOUCHPAD_RETRY_DELAY_MS 20 +#define STARLABS_TOUCHPAD_WAKE_DELAY_MS 1 +#define STARLABS_TOUCHPAD_VERIFY_RETRIES 8 +#define STARLABS_TOUCHPAD_VERIFY_DELAY_MS 5 +#define STARLABS_TOUCHPAD_RESET_READY_RETRIES 24 +#define STARLABS_TOUCHPAD_RESET_READY_DELAY_MS 5 + +#define I2C_HID_OPCODE_RESET 0x01 +#define I2C_HID_OPCODE_GET_REPORT 0x02 +#define I2C_HID_OPCODE_SET_REPORT 0x03 +#define I2C_HID_OPCODE_SET_POWER 0x08 +#define I2C_HID_REPORT_TYPE_FEATURE 0x03 + +#define I2C_HID_PWR_ON 0x00 + +enum starlabs_touchpad_desc_offset { + TOUCHPAD_DESC_CMD_REG = 16, + TOUCHPAD_DESC_DATA_REG = 18, + TOUCHPAD_DESC_LENGTH = 30, +}; + +struct starlabs_touchpad_op_ctx { + unsigned int bus; + uint16_t cmd_reg; + uint16_t data_reg; + uint16_t press; + uint16_t release; + uint8_t bank; + uint8_t addr; + uint8_t value; + uint8_t level; +}; + +#endif /* _STARLABS_CMN_TOUCHPAD_H_ */ diff --git a/src/mainboard/starlabs/common/powercap/Makefile.mk b/src/mainboard/starlabs/common/powercap/Makefile.mk index 1ff73ef3d0e..b4e53e20f83 100644 --- a/src/mainboard/starlabs/common/powercap/Makefile.mk +++ b/src/mainboard/starlabs/common/powercap/Makefile.mk @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -ramstage-y += powercap.c +ramstage-$(CONFIG_STARLABS_COMMON_POWERCAP) += powercap.c CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/powercap diff --git a/src/mainboard/starlabs/common/powercap/powercap.c b/src/mainboard/starlabs/common/powercap/powercap.c index 21b879f5cfd..3c38ee7c604 100644 --- a/src/mainboard/starlabs/common/powercap/powercap.c +++ b/src/mainboard/starlabs/common/powercap/powercap.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include @@ -16,24 +18,208 @@ static uint16_t round_up_to_5(uint16_t value) return DIV_ROUND_UP(value, 5) * 5; } +/* + * Power profile policy: + * + * - Power Saver targets roughly two thirds of nominal TDP. + * - Balanced uses nominal TDP. + * - Performance targets roughly one third above nominal TDP. + * - Custom defaults to the Performance values and allows up to 50% above + * nominal TDP. + * + * This keeps the preset profiles ordered consistently across low- and + * high-TDP parts, while reserving a small amount of extra headroom for + * manual tuning. + */ +static uint32_t get_power_saver_pl1(uint32_t tdp) +{ + return MAX(1U, (tdp * 2) / 3); +} + +static uint32_t get_performance_pl1(uint32_t tdp) +{ + return MAX(tdp, DIV_ROUND_UP(tdp * 4, 3)); +} + +static uint32_t get_max_pl1(uint32_t tdp) +{ + return MAX(tdp, DIV_ROUND_UP(tdp * 3, 2)); +} + +static bool use_derived_pl4(void) +{ + return CONFIG(EC_STARLABS_MERLIN) && !CONFIG(STARLABS_LEGACY_PL4); +} + +static uint32_t get_board_pl4(uint32_t tdp) +{ + uint32_t pl4 = CONFIG_MB_STARLABS_PL4_WATTS; + + /* + * Newer Merlin EC boards update PL4 dynamically at runtime. Keep a + * boot-time ceiling in coreboot by adding the CPU's maximum PL1 budget + * to the board power budget. + */ + if (use_derived_pl4() && tdp) + pl4 += get_max_pl1(tdp); + + return pl4; +} + +static uint32_t get_entry_pl4(const struct soc_power_limits_config *entry, + uint32_t fallback_tdp) +{ + uint32_t tdp = fallback_tdp; + uint32_t pl4; + + if (entry && entry->tdp_pl1_override) + tdp = entry->tdp_pl1_override; + + pl4 = get_board_pl4(tdp); + + if (use_derived_pl4() && entry && entry->tdp_pl4) + pl4 = MIN(pl4, entry->tdp_pl4); + + return pl4; +} + +static uint32_t get_power_profile_pl4(const config_t *cfg, uint32_t tdp) +{ + uint32_t pl4 = get_board_pl4(tdp); + + if (!use_derived_pl4()) + return pl4; + + const struct soc_power_limits_config *limits = + (const struct soc_power_limits_config *)&cfg->power_limits_config; + size_t limit_count = + sizeof(cfg->power_limits_config) / sizeof(struct soc_power_limits_config); + + for (size_t i = 0; i < limit_count; i++) { + const struct soc_power_limits_config *entry = &limits[i]; + + if (entry->tdp_pl1_override == tdp) + pl4 = MIN(pl4, get_entry_pl4(entry, tdp)); + } + + return pl4; +} + +static uint32_t get_tj_max(void) +{ +#if CONFIG(BOARD_STARLABS_LITE_GLK) || CONFIG(BOARD_STARLABS_LITE_GLKR) + return 100; +#elif CONFIG(BOARD_STARLABS_BYTE_ADL) || CONFIG(BOARD_STARLABS_BYTE_TWL) || \ + CONFIG(BOARD_STARLABS_LITE_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_ADL_N) + return 105; +#else + return 110; +#endif +} + +static uint32_t tcc_temp_to_offset(uint32_t tj_max, uint32_t temp) +{ + return tj_max > temp ? tj_max - temp : 0; +} + +static uint32_t tcc_offset_to_temp(uint32_t tj_max, uint32_t offset) +{ + return tj_max > offset ? tj_max - offset : 0; +} + +bool starlabs_get_power_profile_bounds(const config_t *cfg, + struct starlabs_power_profile_bounds *bounds) +{ + uint32_t stock_pl1, stock_pl4, stock_tcc_offset, tj_max; + uint32_t min_pl1, default_pl1, max_pl1; + uint32_t min_pl2, default_pl2, max_pl2; + + if (!cfg || !bounds) + return false; + + stock_pl1 = get_cpu_tdp(); + if (!stock_pl1) + return false; + stock_pl4 = get_power_profile_pl4(cfg, stock_pl1); + stock_tcc_offset = CONFIG(EC_STARLABS_FAN) ? 10 : 20; + tj_max = get_tj_max(); + min_pl1 = get_power_saver_pl1(stock_pl1); + default_pl1 = get_performance_pl1(stock_pl1); + max_pl1 = get_max_pl1(stock_pl1); + min_pl2 = round_up_to_5(min_pl1 * 2); + default_pl2 = round_up_to_5(default_pl1 * 2); + max_pl2 = MIN(round_up_to_5(max_pl1 * 2), stock_pl4); + default_pl2 = clamp_u32(min_pl2, default_pl2, max_pl2); + + bounds->default_pl1 = default_pl1; + bounds->min_pl1 = min_pl1; + bounds->max_pl1 = max_pl1; + + bounds->default_pl2 = default_pl2; + bounds->min_pl2 = min_pl2; + bounds->max_pl2 = max_pl2; + + bounds->default_pl4 = stock_pl4; + bounds->min_pl4 = default_pl2; + bounds->max_pl4 = stock_pl4; + + bounds->default_tcc_temp = tcc_offset_to_temp(tj_max, stock_tcc_offset); + bounds->min_tcc_temp = tcc_offset_to_temp(tj_max, stock_tcc_offset + 20); + bounds->max_tcc_temp = bounds->default_tcc_temp; + + return true; +} + void update_power_limits(config_t *cfg) { - uint8_t performance_scale = 100; uint32_t performance_tcc_offset = CONFIG(EC_STARLABS_FAN) ? 10 : 20; + uint32_t tj_max = get_tj_max(); + const enum cmos_power_profile profile = get_power_profile(PP_BALANCED); + uint32_t cpu_tdp = get_cpu_tdp(); + struct starlabs_power_profile_bounds bounds; + bool have_bounds = starlabs_get_power_profile_bounds(cfg, &bounds); + uint16_t custom_pl1 = 0, custom_pl2 = 0, custom_pl4 = 0; + uint32_t custom_tcc_temp = 0; /* Scale PL1 & PL2 based on CMOS settings */ - switch (get_power_profile(PP_POWER_SAVER)) { + switch (profile) { case PP_POWER_SAVER: - performance_scale -= 50; cfg->tcc_offset = performance_tcc_offset + 20; break; case PP_BALANCED: - performance_scale -= 25; cfg->tcc_offset = performance_tcc_offset + 10; break; case PP_PERFORMANCE: cfg->tcc_offset = performance_tcc_offset; break; + case PP_CUSTOM: + if (have_bounds) { + custom_pl1 = clamp_u32(bounds.min_pl1, + get_uint_option("pl1_override", bounds.default_pl1), + bounds.max_pl1); + if (CONFIG(STARLABS_LEGACY_PL4)) { + custom_pl4 = clamp_u32(bounds.min_pl4, + get_uint_option("pl4_override", bounds.default_pl4), + bounds.max_pl4); + } else { + custom_pl4 = bounds.default_pl4; + } + custom_pl2 = clamp_u32(bounds.min_pl2, + get_uint_option("pl2_override", bounds.default_pl2), + bounds.max_pl2); + custom_pl2 = MIN(custom_pl2, custom_pl4); + custom_pl2 = MAX(custom_pl2, custom_pl1); + custom_tcc_temp = get_uint_option("tcc_temp", 0); + if (!custom_tcc_temp) + custom_tcc_temp = tcc_offset_to_temp(tj_max, + get_uint_option("tcc_offset", performance_tcc_offset)); + custom_tcc_temp = clamp_u32(bounds.min_tcc_temp, custom_tcc_temp, + bounds.max_tcc_temp); + cfg->tcc_offset = tcc_temp_to_offset(tj_max, custom_tcc_temp); + } else { + cfg->tcc_offset = performance_tcc_offset; + } + break; } struct soc_power_limits_config *limits = @@ -43,15 +229,40 @@ void update_power_limits(config_t *cfg) for (size_t i = 0; i < limit_count; i++) { struct soc_power_limits_config *entry = &limits[i]; - uint16_t tdp, pl1, pl2; + uint16_t tdp, pl1, pl2, pl4; - entry->tdp_pl4 = (uint16_t)CONFIG_MB_STARLABS_PL4_WATTS; + if (profile == PP_CUSTOM && have_bounds) { + pl4 = CONFIG(STARLABS_LEGACY_PL4) ? custom_pl4 : + get_entry_pl4(entry, cpu_tdp); + entry->tdp_pl1_override = custom_pl1; + entry->tdp_pl2_override = MIN(custom_pl2, pl4); + entry->tdp_pl4 = pl4; + continue; + } + + pl4 = get_entry_pl4(entry, cpu_tdp); + entry->tdp_pl4 = pl4; tdp = entry->tdp_pl1_override; if (!tdp) continue; - pl1 = (tdp * performance_scale) / 100; + switch (profile) { + case PP_POWER_SAVER: + pl1 = get_power_saver_pl1(tdp); + break; + case PP_BALANCED: + pl1 = tdp; + break; + case PP_PERFORMANCE: + pl1 = get_performance_pl1(tdp); + break; + case PP_CUSTOM: + default: + pl1 = tdp; + break; + } + pl2 = round_up_to_5(pl1 * 2); entry->tdp_pl1_override = pl1; diff --git a/src/mainboard/starlabs/common/smbios/smbios.c b/src/mainboard/starlabs/common/smbios/smbios.c index 00e6f249c76..eb263dc1ab4 100644 --- a/src/mainboard/starlabs/common/smbios/smbios.c +++ b/src/mainboard/starlabs/common/smbios/smbios.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include #include +#include #include +#include #include -#include -#include + +#define SERIAL_NUMBER_OPTION "serial_number" +#define SERIAL_NUMBER_MAX_LENGTH 64 /* Get the Embedded Controller firmware version */ void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) @@ -23,6 +23,88 @@ const char *smbios_system_sku(void) return CONFIG_MAINBOARD_FAMILY; } +static size_t copy_serial_number_prefix(char *dest, size_t dest_size) +{ + size_t i; + size_t j = 0; + + if (!dest || !dest_size) + return 0; + + for (i = 0; CONFIG_MAINBOARD_FAMILY[i] && j + 1 < dest_size; i++) { + if (CONFIG_MAINBOARD_FAMILY[i] != '-') + dest[j++] = CONFIG_MAINBOARD_FAMILY[i]; + } + + dest[j] = '\0'; + return j; +} + +static bool serial_number_prefix_matches(const char *prefix, size_t prefix_len) +{ + size_t i; + + if (prefix_len > sizeof(CONFIG_MAINBOARD_SERIAL_NUMBER) - 1) + return false; + + for (i = 0; i < prefix_len; i++) { + if (CONFIG_MAINBOARD_SERIAL_NUMBER[i] != prefix[i]) + return false; + } + + return true; +} + +static unsigned int serial_number_fallback(void) +{ + char prefix[SERIAL_NUMBER_MAX_LENGTH]; + const char *serial_number = CONFIG_MAINBOARD_SERIAL_NUMBER; + const size_t prefix_len = copy_serial_number_prefix(prefix, sizeof(prefix)); + unsigned int value = 0; + size_t i; + + if (!serial_number_prefix_matches(prefix, prefix_len)) + return 0; + + for (i = prefix_len; serial_number[i]; i++) { + if (serial_number[i] < '0' || serial_number[i] > '9') + return 0; + value = value * 10 + serial_number[i] - '0'; + } + + return value; +} + +static int serial_number_suffix_width(const char *prefix, size_t prefix_len) +{ + const size_t fallback_len = sizeof(CONFIG_MAINBOARD_SERIAL_NUMBER) - 1; + + if (!serial_number_prefix_matches(prefix, prefix_len) || fallback_len <= prefix_len) + return 5; + + return fallback_len - prefix_len; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[SERIAL_NUMBER_MAX_LENGTH]; + static bool serial_number_loaded; + + if (!serial_number_loaded) { + char prefix[SERIAL_NUMBER_MAX_LENGTH]; + const size_t prefix_len = copy_serial_number_prefix(prefix, sizeof(prefix)); + const int suffix_width = serial_number_suffix_width(prefix, prefix_len); + const unsigned int suffix = get_uint_option(SERIAL_NUMBER_OPTION, + serial_number_fallback()); + + snprintf(serial_number, sizeof(serial_number), "%s%0*u", prefix, suffix_width, + suffix); + serial_number_loaded = true; + } + + return serial_number; +} + u8 smbios_mainboard_feature_flags(void) { return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; diff --git a/src/mainboard/starlabs/common/touchpad/Makefile.mk b/src/mainboard/starlabs/common/touchpad/Makefile.mk new file mode 100644 index 00000000000..e65f7118d06 --- /dev/null +++ b/src/mainboard/starlabs/common/touchpad/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += touchpad.c diff --git a/src/mainboard/starlabs/common/touchpad/touchpad.c b/src/mainboard/starlabs/common/touchpad/touchpad.c new file mode 100644 index 00000000000..56d1823b190 --- /dev/null +++ b/src/mainboard/starlabs/common/touchpad/touchpad.c @@ -0,0 +1,502 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include + +static struct starlabs_touchpad_op_ctx starlabs_touchpad_cached_ctx; +static int starlabs_touchpad_cached_ctx_valid; + +static void buf_set_le16(uint8_t *buf, size_t offset, uint16_t value) +{ + buf[offset] = value & 0xff; + buf[offset + 1] = value >> 8; +} + +static size_t starlabs_touchpad_encode_command(uint8_t *buf, uint8_t opcode, + uint8_t report_type, + uint8_t report_id) +{ + size_t length = 0; + + if (report_id < 0x0f) { + buf[length++] = (report_type << 4) | report_id; + buf[length++] = opcode; + } else { + buf[length++] = (report_type << 4) | 0x0f; + buf[length++] = opcode; + buf[length++] = report_id; + } + + return length; +} + +static int starlabs_touchpad_set_report(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t report_id, + const uint8_t *payload, + size_t payload_len) +{ + uint8_t buf[16]; + size_t cmd_len = 0; + size_t report_len = sizeof(uint16_t); + + if (report_id) + report_len++; + report_len += payload_len; + + buf_set_le16(buf, cmd_len, cmd_reg); + cmd_len += sizeof(uint16_t); + cmd_len += starlabs_touchpad_encode_command(buf + cmd_len, + I2C_HID_OPCODE_SET_REPORT, + I2C_HID_REPORT_TYPE_FEATURE, + report_id); + buf_set_le16(buf, cmd_len, data_reg); + cmd_len += sizeof(uint16_t); + buf_set_le16(buf, cmd_len, report_len); + cmd_len += sizeof(uint16_t); + + if (report_id) + buf[cmd_len++] = report_id; + + memcpy(buf + cmd_len, payload, payload_len); + cmd_len += payload_len; + + return i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, cmd_len); +} + +static int starlabs_touchpad_get_report(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t report_id, + uint8_t *payload, size_t payload_len) +{ + uint8_t cmd_buf[8]; + uint8_t rx_buf[16]; + struct i2c_msg segs[2]; + size_t cmd_len = 0; + size_t report_len; + size_t response_len; + int ret; + + buf_set_le16(cmd_buf, cmd_len, cmd_reg); + cmd_len += sizeof(uint16_t); + cmd_len += starlabs_touchpad_encode_command(cmd_buf + cmd_len, + I2C_HID_OPCODE_GET_REPORT, + I2C_HID_REPORT_TYPE_FEATURE, + report_id); + buf_set_le16(cmd_buf, cmd_len, data_reg); + cmd_len += sizeof(uint16_t); + + report_len = payload_len + (report_id ? 1 : 0); + response_len = sizeof(uint16_t) + report_len; + if (response_len > sizeof(rx_buf)) + return -1; + + segs[0].flags = 0; + segs[0].slave = STARLABS_TOUCHPAD_I2C_ADDR; + segs[0].buf = cmd_buf; + segs[0].len = cmd_len; + segs[1].flags = I2C_M_RD; + segs[1].slave = STARLABS_TOUCHPAD_I2C_ADDR; + segs[1].buf = rx_buf; + segs[1].len = response_len; + + ret = i2c_transfer(bus, segs, ARRAY_SIZE(segs)); + if (ret != 0) + return ret; + + response_len = rx_buf[0] | (rx_buf[1] << 8); + if (response_len < sizeof(uint16_t) + report_len) + return -1; + + if (report_id && rx_buf[2] != report_id) + return -1; + + memcpy(payload, rx_buf + sizeof(uint16_t) + (report_id ? 1 : 0), payload_len); + + return 0; +} + +static int starlabs_touchpad_reset(unsigned int bus, uint16_t cmd_reg) +{ + uint8_t buf[4]; + size_t cmd_len = 0; + + buf_set_le16(buf, cmd_len, cmd_reg); + cmd_len += sizeof(uint16_t); + cmd_len += starlabs_touchpad_encode_command(buf + cmd_len, + I2C_HID_OPCODE_RESET, + 0, 0); + + return i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, cmd_len); +} + +static int starlabs_touchpad_set_haptics(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t level) +{ + return starlabs_touchpad_set_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_HAPTICS_REPORT_ID, + &level, sizeof(level)); +} + +static int starlabs_touchpad_set_force(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint16_t press, + uint16_t release) +{ + uint8_t payload[4]; + + buf_set_le16(payload, 0, press); + buf_set_le16(payload, 2, release); + + return starlabs_touchpad_set_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_FORCE_REPORT_ID, + payload, sizeof(payload)); +} + +static int starlabs_touchpad_write_user_reg(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t bank, + uint8_t addr, uint8_t value) +{ + const uint8_t payload[] = { addr, bank, value }; + + return starlabs_touchpad_set_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_USER_REG_REPORT_ID, + payload, sizeof(payload)); +} + +static int starlabs_touchpad_get_haptics(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t *level) +{ + return starlabs_touchpad_get_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_HAPTICS_REPORT_ID, + level, sizeof(*level)); +} + +static int starlabs_touchpad_get_force(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint16_t *press, + uint16_t *release) +{ + uint8_t payload[4]; + int ret; + + ret = starlabs_touchpad_get_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_FORCE_REPORT_ID, + payload, sizeof(payload)); + if (ret != 0) + return ret; + + *press = payload[0] | (payload[1] << 8); + *release = payload[2] | (payload[3] << 8); + + return 0; +} + +static int starlabs_touchpad_read_user_reg(unsigned int bus, uint16_t cmd_reg, + uint16_t data_reg, uint8_t *bank, + uint8_t *addr, uint8_t *value) +{ + uint8_t payload[3]; + int ret; + + ret = starlabs_touchpad_get_report(bus, cmd_reg, data_reg, + STARLABS_TOUCHPAD_USER_REG_REPORT_ID, + payload, sizeof(payload)); + if (ret != 0) + return ret; + + *addr = payload[0]; + *bank = payload[1]; + *value = payload[2]; + + return 0; +} + +static int starlabs_touchpad_set_haptics_op(void *arg) +{ + const struct starlabs_touchpad_op_ctx *ctx = arg; + + return starlabs_touchpad_set_haptics(ctx->bus, ctx->cmd_reg, + ctx->data_reg, ctx->level); +} + +static int starlabs_touchpad_set_force_op(void *arg) +{ + const struct starlabs_touchpad_op_ctx *ctx = arg; + + return starlabs_touchpad_set_force(ctx->bus, ctx->cmd_reg, + ctx->data_reg, + ctx->press, ctx->release); +} + +static int starlabs_touchpad_write_user_reg_op(void *arg) +{ + const struct starlabs_touchpad_op_ctx *ctx = arg; + + return starlabs_touchpad_write_user_reg(ctx->bus, ctx->cmd_reg, + ctx->data_reg, ctx->bank, + ctx->addr, ctx->value); +} + +static int starlabs_touchpad_reset_op(void *arg) +{ + const struct starlabs_touchpad_op_ctx *ctx = arg; + + return starlabs_touchpad_reset(ctx->bus, ctx->cmd_reg); +} + +static int starlabs_touchpad_verify_haptics(const struct starlabs_touchpad_op_ctx *ctx) +{ + uint8_t level = 0; + int ret = -1; + int attempt; + + for (attempt = 0; attempt < STARLABS_TOUCHPAD_VERIFY_RETRIES; attempt++) { + ret = starlabs_touchpad_get_haptics(ctx->bus, ctx->cmd_reg, + ctx->data_reg, &level); + if (ret == 0 && level == ctx->level) + return 0; + mdelay(STARLABS_TOUCHPAD_VERIFY_DELAY_MS); + } + + return ret == 0 ? -1 : ret; +} + +static int starlabs_touchpad_verify_force(const struct starlabs_touchpad_op_ctx *ctx) +{ + uint16_t press = 0; + uint16_t release = 0; + int ret = -1; + int attempt; + + for (attempt = 0; attempt < STARLABS_TOUCHPAD_VERIFY_RETRIES; attempt++) { + ret = starlabs_touchpad_get_force(ctx->bus, ctx->cmd_reg, + ctx->data_reg, &press, &release); + if (ret == 0 && press == ctx->press && release == ctx->release) + return 0; + mdelay(STARLABS_TOUCHPAD_VERIFY_DELAY_MS); + } + + return ret == 0 ? -1 : ret; +} + +static int starlabs_touchpad_verify_user_reg(const struct starlabs_touchpad_op_ctx *ctx) +{ + uint8_t bank = 0; + uint8_t addr = 0; + uint8_t value = 0; + int ret = -1; + int attempt; + + for (attempt = 0; attempt < STARLABS_TOUCHPAD_VERIFY_RETRIES; attempt++) { + ret = starlabs_touchpad_read_user_reg(ctx->bus, ctx->cmd_reg, + ctx->data_reg, &bank, + &addr, &value); + if (ret == 0 && bank == ctx->bank && addr == ctx->addr && value == ctx->value) + return 0; + mdelay(STARLABS_TOUCHPAD_VERIFY_DELAY_MS); + } + + return ret == 0 ? -1 : ret; +} + +static int starlabs_touchpad_wait_for_reset_ready(const struct starlabs_touchpad_op_ctx *ctx) +{ + uint8_t level; + int ret = -1; + int attempt; + + for (attempt = 0; attempt < STARLABS_TOUCHPAD_RESET_READY_RETRIES; attempt++) { + ret = starlabs_touchpad_get_haptics(ctx->bus, ctx->cmd_reg, + ctx->data_reg, &level); + if (ret == 0) + return 0; + mdelay(STARLABS_TOUCHPAD_RESET_READY_DELAY_MS); + } + + return ret == 0 ? -1 : ret; +} + +static void starlabs_touchpad_init_ctx(struct starlabs_touchpad_op_ctx *ctx) +{ + *ctx = (struct starlabs_touchpad_op_ctx) { + .bus = STARLABS_TOUCHPAD_I2C_BUS, + .cmd_reg = STARLABS_TOUCHPAD_FALLBACK_CMD_REG, + .data_reg = STARLABS_TOUCHPAD_FALLBACK_DATA_REG, + .level = get_uint_option("touchpad_haptics", + STARLABS_TOUCHPAD_HAPTICS_DEFAULT), + .press = get_uint_option("touchpad_force_press", + STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT), + .release = get_uint_option("touchpad_force_release", + STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT), + .bank = STARLABS_TOUCHPAD_USER_REG_BANK, + .addr = STARLABS_TOUCHPAD_USER_REG_ADDR_RATE, + .value = get_uint_option("touchpad_report_rate", + STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT), + }; +} + +static int starlabs_touchpad_retry(int (*op)(void *arg), void *arg) +{ + int ret; + int attempt; + + for (attempt = 0; attempt < STARLABS_TOUCHPAD_RETRIES; attempt++) { + ret = op(arg); + if (ret == 0) + return 0; + mdelay(STARLABS_TOUCHPAD_RETRY_DELAY_MS); + } + + return ret; +} + +static void starlabs_touchpad_cache_ctx(void) +{ + if (starlabs_touchpad_cached_ctx_valid) + return; + + starlabs_touchpad_init_ctx(&starlabs_touchpad_cached_ctx); + starlabs_touchpad_cached_ctx_valid = 1; +} + +static int starlabs_touchpad_wake(const struct starlabs_touchpad_op_ctx *ctx) +{ + uint8_t wake_byte; + + (void)i2c_read_raw(ctx->bus, STARLABS_TOUCHPAD_I2C_ADDR, &wake_byte, 1); + mdelay(STARLABS_TOUCHPAD_WAKE_DELAY_MS); + + return 0; +} + +static int starlabs_touchpad_ensure_user_reg(const struct starlabs_touchpad_op_ctx *ctx) +{ + int ret; + + ret = starlabs_touchpad_verify_user_reg(ctx); + if (ret == 0) + return 0; + + ret = starlabs_touchpad_retry(starlabs_touchpad_write_user_reg_op, (void *)ctx); + if (ret != 0) + return ret; + + return starlabs_touchpad_verify_user_reg(ctx); +} + +static int starlabs_touchpad_ensure_force(const struct starlabs_touchpad_op_ctx *ctx) +{ + int ret; + + ret = starlabs_touchpad_verify_force(ctx); + if (ret == 0) + return 0; + + ret = starlabs_touchpad_retry(starlabs_touchpad_set_force_op, (void *)ctx); + if (ret != 0) + return ret; + + return starlabs_touchpad_verify_force(ctx); +} + +static void starlabs_touchpad_prepare_settings(void *arg) +{ + int ret; + + (void)arg; + + starlabs_touchpad_cache_ctx(); + starlabs_touchpad_wake(&starlabs_touchpad_cached_ctx); + + ret = starlabs_touchpad_retry(starlabs_touchpad_write_user_reg_op, + &starlabs_touchpad_cached_ctx); + if (ret != 0) { + printk(BIOS_WARNING, + "Touchpad settings: early report rate write %u failed: %d\n", + starlabs_touchpad_cached_ctx.value, ret); + } + + ret = starlabs_touchpad_retry(starlabs_touchpad_set_force_op, + &starlabs_touchpad_cached_ctx); + if (ret != 0) { + printk(BIOS_WARNING, + "Touchpad settings: early force write %u/%u failed: %d\n", + starlabs_touchpad_cached_ctx.press, + starlabs_touchpad_cached_ctx.release, ret); + } +} + +static void starlabs_touchpad_apply_settings(void *arg) +{ + int ret; + const struct starlabs_touchpad_op_ctx *ctx; + + (void)arg; + + starlabs_touchpad_cache_ctx(); + ctx = &starlabs_touchpad_cached_ctx; + + starlabs_touchpad_wake(ctx); + + ret = starlabs_touchpad_ensure_user_reg(ctx); + if (ret != 0) { + printk(BIOS_ERR, "Touchpad settings: failed to verify report rate %u: %d\n", + ctx->value, ret); + return; + } + + ret = starlabs_touchpad_ensure_force(ctx); + if (ret != 0) { + printk(BIOS_ERR, + "Touchpad settings: failed to verify force thresholds %u/%u: %d\n", + ctx->press, ctx->release, ret); + return; + } + + ret = starlabs_touchpad_retry(starlabs_touchpad_set_haptics_op, (void *)ctx); + if (ret == 0) + ret = starlabs_touchpad_verify_haptics(ctx); + if (ret != 0) { + printk(BIOS_WARNING, + "Touchpad settings: direct haptics write failed, retrying after reset: %d\n", + ret); + ret = starlabs_touchpad_retry(starlabs_touchpad_reset_op, (void *)ctx); + if (ret != 0) { + printk(BIOS_ERR, + "Touchpad settings: failed to reset device before haptics write: %d\n", + ret); + return; + } + + ret = starlabs_touchpad_wait_for_reset_ready(ctx); + if (ret != 0) { + printk(BIOS_ERR, + "Touchpad settings: touchpad did not become ready after reset: %d\n", + ret); + return; + } + + ret = starlabs_touchpad_retry(starlabs_touchpad_set_haptics_op, (void *)ctx); + if (ret == 0) + ret = starlabs_touchpad_verify_haptics(ctx); + if (ret != 0) { + printk(BIOS_ERR, "Touchpad settings: failed to set haptics level %u: %d\n", + ctx->level, ret); + return; + } + } + + printk(BIOS_INFO, + "Touchpad settings: applied via regs 0x%04x/0x%04x; " + "haptics=%u click=%u release=%u rate=%u\n", + ctx->cmd_reg, ctx->data_reg, ctx->level, + ctx->press, ctx->release, ctx->value); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, starlabs_touchpad_prepare_settings, + NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, starlabs_touchpad_apply_settings, + NULL); diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig index a9fcd13ed7b..35cbef82f51 100644 --- a/src/mainboard/starlabs/lite/Kconfig +++ b/src/mainboard/starlabs/lite/Kconfig @@ -7,9 +7,12 @@ config BOARD_STARLABS_LITE_SERIES select DRIVERS_EFI_VARIABLE_STORE select DRIVERS_OPTION_CFR_ENABLED select DRIVERS_I2C_HID + select FSP_COMPRESS_FSP_M_LZMA + select FSP_COMPRESS_FSP_S_LZMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_INTEL_PTT + select VALIDATE_INTEL_DESCRIPTOR select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select CRB_TPM @@ -60,7 +63,11 @@ config EC_VARIANT_DIR config FMDFILE default "src/mainboard/starlabs/lite/vboot.fmd" if VBOOT - default "src/mainboard/starlabs/lite/board.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFWI_FITC_CONFIG_PROFILE + default "glk" if BOARD_STARLABS_LITE_GLK + default "glkr" if BOARD_STARLABS_LITE_GLKR config MAINBOARD_DIR default "starlabs/lite" @@ -90,10 +97,6 @@ config TRACKPAD_INTERRUPT default 0x1 if BOARD_STARLABS_LITE_GLK default 0x0 if BOARD_STARLABS_LITE_GLKR -config EDK2_BOOTSPLASH_FILE - string - default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" - config UART_FOR_CONSOLE default 2 diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c index 4a91a46a066..4a52f75a147 100644 --- a/src/mainboard/starlabs/lite/cfr.c +++ b/src/mainboard/starlabs/lite/cfr.c @@ -53,7 +53,9 @@ static struct sm_obj_form keyboard_group = { static struct sm_obj_form security_group = { .ui_name = "Security", .obj_list = (const struct sm_object *[]) { +#if CONFIG(BOOTMEDIA_SMM_BWP_RUNTIME_OPTION) &bios_lock, +#endif &intel_tme, NULL }, @@ -75,6 +77,9 @@ static struct sm_obj_form performance_group = { .ui_name = "Performance", .obj_list = (const struct sm_object *[]) { &power_profile, + &pl1_override, + &pl2_override, + &tcc_temp, NULL }, }; diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c index 7234cbd07ff..f78a7ec1066 100644 --- a/src/mainboard/starlabs/lite/devtree.c +++ b/src/mainboard/starlabs/lite/devtree.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/lite/dsdt.asl b/src/mainboard/starlabs/lite/dsdt.asl index c47ebb016f1..c73920005bc 100644 --- a/src/mainboard/starlabs/lite/dsdt.asl +++ b/src/mainboard/starlabs/lite/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( #include /* PS/2 Keyboard */ - #include + #include } #include diff --git a/src/mainboard/starlabs/lite/mainboard.c b/src/mainboard/starlabs/lite/mainboard.c index cd46529c0fb..6113446481f 100644 --- a/src/mainboard/starlabs/lite/mainboard.c +++ b/src/mainboard/starlabs/lite/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include static void init_mainboard(void *chip_info) diff --git a/src/mainboard/starlabs/lite/variants/glk/board.fmd b/src/mainboard/starlabs/lite/variants/glk/board.fmd new file mode 100644 index 00000000000..d2053fcf2f2 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glk/board.fmd @@ -0,0 +1,59 @@ +# Complete IFWI Map +# Start (hex) End (hex) Length (hex) Area Name +# ----------- --------- ------------ --------- +# +# 00000000 007FFFFF 00800000 Full Flash Image +# 00000014 00000017 00000004 FLMAP0 - Flash Map 0 Register +# 00000018 0000001B 00000004 FLMAP1 - Flash Map 1 Register +# 0000001C 0000001F 00000004 FLMAP2 - Flash Map 2 Register +# 00000030 0000003B 0000000C FCBA - Flash Component Registers +# 00000040 00000043 00000004 FLREG0 - Flash Region 0 (Flash Descriptor) Register +# 00000044 00000047 00000004 FLREG1 - Flash Region 1 (IFWI) Register +# 00000048 0000004B 00000004 FLREG2 - Flash Region 2 (Intel(R) TXE) Register +# 00000050 00000053 00000004 FLREG4 - Flash Region 4 (Platform Data) Register +# 00000054 00000057 00000004 FLREG5 - Flash Region 5 (Device Expansion) Register +# 00000060 00000063 00000004 FLREG8 - Flash Region 8 (Embedded Controller) Register +# 00000080 00000083 00000004 FLMSTR1 - Flash Master 1 (Host CPU/BIOS) +# 00000084 00000087 00000004 FLMSTR2 - Flash Master 2 (Intel(R) TXE) +# 00000090 00000093 00000004 FLMSTR5 - Flash Master 5 (EC) +# 00000100 000002FF 00000200 FPSBA - SoC Straps (Including Padding) +# 00000DF0 00000EFF 00000110 VSCC Table +# 00000DF0 00000DF7 00000008 GD25LQ64 +# 00001000 0033FFFF 0033F000 Boot Partition 1 +# 00001000 000C2FFF 000C2000 Primary Boot Partition +# 00001200 0000120F 00000010 IFP Overrides Partition +# 00001210 00001317 00000108 Unified Emulation Partition (UEP) +# 00002000 00002FFF 00001000 OEM SMIP Partition +# 00003000 0000DFFF 0000B000 CSE RBE Partition +# 0000E000 0001CFFF 0000F000 PMCP +# 0001D000 0007DFFF 00061000 CSE BUP Partition +# 0007E000 000A3FFF 00026000 uCode Partition +# 0007E040 0009083F 00012800 uCode Patch 1 +# 00090840 000A303F 00012800 uCode Patch 2 +# 000A4000 000C0FFF 0001D000 IBB Partition +# 000C1000 000C2FFF 00002000 Debug Token Partition +# 000C3000 001C6FFF 00104000 Secondary Boot Partition +# 000C4000 001C6FFF 00103000 CSE Main Partition +# 00340000 0067EFFF 0033F000 Boot Partition 2 +# 00340000 003401FF 00000200 Primary Boot Partition +# 00340200 0062FFFF 002EFE00 Secondary Boot Partition +# 00341000 0062FFFF 002EF000 OBB Partition +# 0067F000 0077FFFF 00101000 Device Expansion Region +# 00780000 007FFFFF 00080000 EC Region + +# coreboot only needs to know about the OBB. It's nested inside OBBP, to account for +# the header. +FLASH 8M { + OBBP@0x342000 { + OBB@0x0 0x2ee000 { + FPF_STATUS@0x0 0x1000 + UNIFIED_MRC_CACHE@0xe000 0x11000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VAR_MRC_CACHE@0x10000 0x1000 + } + SMMSTORE@0x2e000 0x80000 + FMAP@0xae000 0x200 + COREBOOT(CBFS)@0xae200 0x1ffe00 + } + } +} diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index 8de2d686229..496562813b4 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_FSP" # Graphics # TODO: @@ -22,8 +23,6 @@ chip soc/intel/apollolake register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_bios_config_lockdown" = "1" - register "enhanced_cstates" = "1" - register "pnp_settings" = "PNP_PERF_POWER" register "mod_phy_if_value" = "0x12" @@ -47,12 +46,7 @@ chip soc/intel/apollolake register "pcie_rp_deemphasis_enable[4]" = "1" register "pcie_rp_deemphasis_enable[5]" = "1" - # GPE configuration - register "gpe0_dw1" = "PMC_GPE_NW_63_32" - register "gpe0_dw2" = "PMC_GPE_N_95_64" - register "gpe0_dw3" = "PMC_GPE_NW_31_0" - - register "slp_s3_assertion_width_usecs" = "28000" + register "slp_s3_assertion_width_usecs" = "1000" device domain 0 on device ref igd on @@ -65,7 +59,7 @@ chip soc/intel/apollolake device generic 0 on end end end - device ref pmc off end + device ref pmc hidden end device ref p2sb on end device ref fast_spi on end device ref sram on end @@ -84,8 +78,11 @@ chip soc/intel/apollolake register "usb3_port[1]" = "PORT_EN(OC_SKIP)" # Motherboard USB 3.0 Type-A - register "usb2_port[3]" = "PORT_EN(OC1)" - register "usb3_port[0]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC_SKIP)" + register "usb3_port[0]" = "PORT_EN(OC_SKIP)" + + # Internal Webcam + register "usb2_port[4]" = "PORT_EN(OC_SKIP)" # Daughterboard USB 3.0 Type-A register "usb2_port[5]" = "PORT_EN(OC_SKIP)" @@ -93,6 +90,73 @@ chip soc/intel/apollolake # Daughterboard SD Card register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb3_port2 on end + end + + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb3_port1 on end + end + + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port5 on end + end + + chip drivers/usb/acpi + register "desc" = ""Daughterboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""Daughterboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb3_port5 on end + end + + chip drivers/usb/acpi + register "desc" = ""SD Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port7 on end + end + + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_33)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_33)" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port9 on end + end + end + end end device ref i2c4 on end device ref i2c7 on @@ -100,7 +164,7 @@ chip soc/intel/apollolake end device ref uart0 on end device ref uart2 on end - device ref spi2 on end + device ref spi2 off end device ref lpc_espi on register "gen1_dec" = "0x00040069" register "gen2_dec" = "0x00fc0201" diff --git a/src/mainboard/starlabs/lite/variants/glk/gpio.c b/src/mainboard/starlabs/lite/variants/glk/gpio.c index 321082ce3bb..e92271c7809 100644 --- a/src/mainboard/starlabs/lite/variants/glk/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glk/gpio.c @@ -21,423 +21,234 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } /* Pad configuration in ramstage. */ +/* clang-format off */ const struct pad_config gpio_table[] = { - /* ------- GPIO Group NorthWest ------- */ - /* GPIO_0: XDP_H_TCK */ + /* General Purpose I/O Deep */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1), /* Power Button */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1), /* Sleep S0 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1), /* Sleep S3 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1), /* Sleep S4 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1), /* Suspend Power Ack */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1), /* Battery Low */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1), /* Suspend Clock */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1), /* Suspend Status */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_142, 1, DEEP, UP_20K, IGNORE, SAME), /* Wake */ + + /* SPI Flash */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1), /* Chip Select */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1), /* MOSI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1), /* MISO */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1), /* IO 2 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1), /* IO 3 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1), /* Clock */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_97, NATIVE, DEEP, NF1), /* Clock Feedback */ + + /* Touchpad */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* Data */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* Clock */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_177, NONE, PLTRST), /* Interrupt */ + + /* Wireless */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_33, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD), /* Bluetooth RF Kill */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_34, 1, DEEP, NONE, IGNORE, DISPUPD), /* WiFi RF Kill */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* BRI Data */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* BRI Response */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* RGI Data */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* RGI Response */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* RF Reset */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1), /* XTAL Clock Request */ + + /* Display */ + PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0), /* DDC Data */ + PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0), /* DDC Clock */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), /* Panel Power */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), /* Backlight Enable */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), /* Backlight PWM */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* HDMI Hot Plug */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DDI1 Hot Plug */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* eDP Hot Plug */ + + /* High-Definition Audio */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* Clock */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* Sync */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* Data Input */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* Data Output */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* Reset */ + + /* PCH */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1), /* Platform Reset */ + PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME), /* Interrupt */ + _PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), /* Thermal Trip */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* Processor Hot */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1), /* Reset Button */ + PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME), /* SCI */ + PAD_CFG_GPI_SMI_IOS(GPIO_67, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), /* SMI */ + + /* SMBus */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* Clock */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* Data */ + + /* Config Straps [ Low / High ] */ + PAD_CFG_GPO(GPIO_27, 0, DEEP), /* eMMC [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPIO_28, 1, DEEP), /* SPI [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPIO_83, 0, DEEP), /* LPC [ 3.3V / 1.8V ] */ + PAD_CFG_GPO(GPIO_84, 0, DEEP), /* SPI Boot [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPIO_174, 1, DEEP), /* VDD2 [ 1.20V / 1.24V ] */ + PAD_CFG_GPO(GPIO_175, 0, DEEP), /* Bus [ LPC / eSPI ] */ + PAD_NC(GPIO_0, DN_20K), - /* GPIO_1: XDP_H_TRST_N */ PAD_NC(GPIO_1, DN_20K), - /* GPIO_2: XDP_H_TMS */ PAD_NC(GPIO_2, DN_20K), - /* GPIO_3: XDP_H_TDI */ PAD_NC(GPIO_3, DN_20K), - /* GPIO_4: XDP_H_TDO */ PAD_NC(GPIO_4, DN_20K), - /* GPIO_5: Not Connected */ PAD_NC(GPIO_5, DN_20K), - /* GPIO_6: XDP_H_PREQ_N */ PAD_NC(GPIO_6, DN_20K), - /* GPIO_7: XDP_H_PRDY_N */ PAD_NC(GPIO_7, DN_20K), - /* GPIO_8: Not Connected */ PAD_NC(GPIO_8, DN_20K), - /* GPIO_9: Not Connected */ PAD_NC(GPIO_9, DN_20K), - /* GPIO_10: Not Connected */ PAD_NC(GPIO_10, DN_20K), - /* GPIO_11: Not Connected */ PAD_NC(GPIO_11, DN_20K), - /* GPIO_12: Not Connected */ PAD_NC(GPIO_12, DN_20K), - /* GPIO_13: ACCEL1_INT */ PAD_NC(GPIO_13, DN_20K), - /* GPIO_14: ACCEL2_INT */ PAD_NC(GPIO_14, DN_20K), - /* GPIO_15: Not Connected */ PAD_NC(GPIO_15, DN_20K), - /* GPIO_16: SATA_DEVSLP */ PAD_NC(GPIO_16, NONE), - /* GPIO_17: Not Connected */ PAD_NC(GPIO_17, DN_20K), - /* GPIO_18: Not Connected */ PAD_NC(GPIO_18, DN_20K), - /* GPIO_19: PMIC_IRQ# */ - PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME), - /* GPIO_20: Not Connected */ PAD_NC(GPIO_20, DN_20K), - /* GPIO_21: WLAN_WWAN_COEX3 */ PAD_NC(GPIO_21, DN_20K), - /* GPIO_22: WLAN_WWAN_COEX3 */ PAD_NC(GPIO_22, DN_20K), - /* GPIO_23: WLAN_WWAN_COEX3 */ PAD_NC(GPIO_23, DN_20K), - /* GPIO_24: Not Connected */ PAD_NC(GPIO_24, DN_20K), - /* GPIO_25: Not Connected */ PAD_NC(GPIO_25, DN_20K), - /* GPIO_26: TPNL_INT# */ PAD_NC(GPIO_26, DN_20K), - /* GPIO_27: eMMC Strap */ - PAD_NC(GPIO_27, NONE), - /* GPIO_28: SPI Strap */ - PAD_NC(GPIO_28, NONE), - /* GPIO_29: Not Connected */ PAD_NC(GPIO_29, DN_20K), - /* GPIO_30: Not Connected */ PAD_NC(GPIO_30, DN_20K), - /* GPIO_31: Not Connected */ PAD_NC(GPIO_31, DN_20K), - /* GPIO_32: Not Connected */ PAD_NC(GPIO_32, DN_20K), - /* GPIO_33: BT_ON_SOC */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_33, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD), - /* GPIO_34: WIFI_ON_SOC */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_34, 1, DEEP, NONE, IGNORE, DISPUPD), - /* GPIO_35: Not Connected */ PAD_NC(GPIO_35, DN_20K), - /* GPIO_36: Not Connected */ PAD_NC(GPIO_36, DN_20K), - /* GPIO_37: Not Connected */ PAD_NC(GPIO_37, DN_20K), - /* GPIO_38: WAKE_SCI# */ - PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME), - /* GPIO_39: FP_RST# */ PAD_NC(GPIO_39, DN_20K), - /* GPIO_40: Not Connected */ PAD_NC(GPIO_40, DN_20K), - /* GPIO_41: Not Connected */ PAD_NC(GPIO_41, DN_20K), - /* GPIO_42: SECURITY_FLASH */ PAD_NC(GPIO_42, DN_20K), - /* GPIO_43: GPIO_43 */ PAD_NC(GPIO_43, DN_20K), - /* GPIO_44: USB OC0 */ PAD_NC(GPIO_44, DN_20K), - /* GPIO_45: USB_OC1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), - /* GPIO_46: Not Connected */ + PAD_NC(GPIO_45, DN_20K), PAD_NC(GPIO_46, DN_20K), - /* GPIO_47: Not Connected */ PAD_NC(GPIO_47, DN_20K), - /* GPIO_48: PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), - /* GPIO_49: PMC_I2C_SCL */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), - /* GPIO_50: I2C_0 SDA */ PAD_NC(GPIO_50, DN_20K), - /* GPIO_51: I2C_0 SDL */ PAD_NC(GPIO_51, DN_20K), - /* GPIO_52: I2C_1 SDA */ PAD_NC(GPIO_52, DN_20K), - /* GPIO_53: I2C_1 SDL */ PAD_NC(GPIO_53, DN_20K), - /* GPIO_54: I2C_2 SDA */ PAD_NC(GPIO_54, DN_20K), - /* GPIO_55: I2C_2 SDL */ PAD_NC(GPIO_55, DN_20K), - /* GPIO_56: I2C_3 SDA */ PAD_NC(GPIO_56, DN_20K), - /* GPIO_57: I2C_3 SDL */ PAD_NC(GPIO_57, DN_20K), - /* GPIO_58: I2C4_SDA */ PAD_NC(GPIO_58, DN_20K), - /* GPIO_59: I2C4_SCL */ PAD_NC(GPIO_59, DN_20K), - /* GPIO_60: UART0 RXD */ PAD_NC(GPIO_60, DN_20K), - /* GPIO_61: UART0 TXD */ PAD_NC(GPIO_61, DN_20K), - /* GPIO_62: UART0 RTS */ PAD_NC(GPIO_62, DN_20K), - /* GPIO_63: UART0 CTS */ PAD_NC(GPIO_63, DN_20K), - /* GPIO_66: GPIO_66 */ PAD_NC(GPIO_66, DN_20K), - /* GPIO_67: SMC_EXTSMI# */ - PAD_CFG_GPI_SMI_IOS(GPIO_67, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), - /* GPIO_68: Not Connected */ PAD_NC(GPIO_68, DN_20K), - /* GPIO_69: Not Connected */ PAD_NC(GPIO_69, DN_20K), - /* GPIO_70: Not Connected */ PAD_NC(GPIO_70, DN_20K), - /* GPIO_71: Not Connected */ PAD_NC(GPIO_71, DN_20K), - /* GPIO_72: Not Connected */ PAD_NC(GPIO_72, DN_20K), - /* GPIO_73: Not Connected */ PAD_NC(GPIO_73, DN_20K), - /* GPIO_74: PMIC_THERMTRIP# */ - _PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), - PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), - /* GPIO_75: PROCHOT#_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), - /* GPIO_211: EMMC_RST#_CPU */ - PAD_NC(GPIO_211, UP_20K), - /* GPIO_212: BRD_ID_0 */ - PAD_NC(GPIO_212, DN_20K), - /* GPIO_213: BRD_ID_1 */ - PAD_NC(GPIO_213, DN_20K), - /* GPIO_214: BRD_ID_2 */ - PAD_NC(GPIO_214, DN_20K), - - /* ------- GPIO Group North ------- */ - /* GPIO_76: Not Connected */ PAD_NC(GPIO_76, DN_20K), - /* GPIO_77: Not Connected */ PAD_NC(GPIO_77, DN_20K), - /* GPIO_78: Not Connected */ PAD_NC(GPIO_78, DN_20K), - /* GPIO_79: GPIO_79 */ PAD_NC(GPIO_79, DN_20K), - /* GPIO_80: FP_FS0 */ PAD_NC(GPIO_80, DN_20K), - /* GPIO_81: GPIO_81 */ PAD_NC(GPIO_81, DN_20K), - /* GPIO_82: FP_MISO */ PAD_NC(GPIO_82, DN_20K), - /* GPIO_83: LPC 1.8V/3.3V Select */ - PAD_NC(GPIO_83, DN_20K), - /* GPIO_84: Allow SPI Boot */ - PAD_NC(GPIO_84, UP_20K), - /* GPIO_85: Not Connected */ PAD_NC(GPIO_85, DN_20K), - /* GPIO_86: GPIO_86 */ PAD_NC(GPIO_86, DN_20K), - /* GPIO_87: Not Connected */ PAD_NC(GPIO_87, DN_20K), - /* GPIO_88: Not Connected */ PAD_NC(GPIO_88, DN_20K), - /* GPIO_89: Not Connected */ PAD_NC(GPIO_89, DN_20K), - /* GPIO_90: FLASH_SPI_CS0_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1), - /* GPIO_91: Not Connected */ PAD_NC(GPIO_91, DN_20K), - /* GPIO_92: FLASH_SPI_MOSI */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1), - /* GPIO_93: FLASH_SPI_MISO */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1), - /* GPIO_94: FLASH_SPI_IO2 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1), - /* GPIO_95: FLASH_SPI_IO3 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1), - /* GPIO_96: FLASH_SPI_CLK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1), - /* GPIO_98: PMU_PLT_RST#_CPU */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1), - /* GPIO_99: PM_PWRBTN# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1), - /* GPIO_100: SLP_S0# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1), - /* GPIO_101: SLP_S3# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1), - /* GPIO_102: SLP_S4# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1), - /* GPIO_103: SUSPWRDNACK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1), - /* GPIO_104: Not Connected */ PAD_NC(GPIO_104, UP_20K), - /* GPIO_105: GPIO_105 */ PAD_NC(GPIO_105, UP_20K), - /* GPIO_106: PMU_BATLOW# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1), - /* GPIO_107: PMU_RSTBTN# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1), - /* GPIO_108: SUS_CLK */ - PAD_NC(GPIO_108, NONE), - /* GPIO_109: PMU_SUS_STAT# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1), - /* GPIO_110: I2C_5 SDA */ PAD_NC(GPIO_110, DN_20K), - /* GPIO_111: I2C_5 SDL */ PAD_NC(GPIO_111, DN_20K), - /* GPIO_112: I2C_6 SDA */ PAD_NC(GPIO_112, DN_20K), - /* GPIO_113: I2C_6 SCL */ PAD_NC(GPIO_113, DN_20K), - /* GPIO_114: I2C_7 SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - /* GPIO_115: I2C_7 SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - /* GPIO_116: WLAN_PCIE_WAKE# */ PAD_NC(GPIO_116, DN_20K), - /* GPIO_117: Not Connected */ PAD_NC(GPIO_117, DN_20K), - /* GPIO_118: Not Connected */ PAD_NC(GPIO_118, DN_20K), - /* GPIO_119: Not Connected */ PAD_NC(GPIO_119, DN_20K), - /* GPIO_120: WLAN_CLK_REQ# */ PAD_NC(GPIO_120, DN_20K), - /* GPIO_121: Not Connected */ PAD_NC(GPIO_121, DN_20K), - /* GPIO_122: Not Connected */ PAD_NC(GPIO_122, DN_20K), - /* GPIO_123: Not Connected */ PAD_NC(GPIO_123, DN_20K), - /* GPIO_124: DDI0_DDC_SDA */ - PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0), - /* GPIO_125: DDI0_DDC_SCL */ - PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0), - /* GPIO_126: Not Connected */ PAD_NC(GPIO_126, DN_20K), - /* GPIO_127: Not Connected */ PAD_NC(GPIO_127, DN_20K), - /* GPIO_128: EDP_VDD_EN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), - /* GPIO_129: EDP_BKLT_EN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), - /* GPIO_130: eDP_BKLCTL_3P3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD), - /* GPIO_131: HDMI_HPD_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - /* GPIO_132: DDI1_HPD_SOC_N */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - /* GPIO_133: EDP_HPD_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - /* GPIO_134: Touch_Panel_RST# */ PAD_NC(GPIO_134, DN_20K), - /* GPIO_135: TCH_HOME_KEY */ PAD_NC(GPIO_135, DN_20K), - /* GPIO_136: Not Connected */ PAD_NC(GPIO_136, DN_20K), - /* GPIO_137: Not Connected */ PAD_NC(GPIO_137, DN_20K), - /* GPIO_138: Not Connected */ PAD_NC(GPIO_138, DN_20K), - /* GPIO_139: Not Connected */ PAD_NC(GPIO_139, DN_20K), - /* GPIO_140: Not Connected */ PAD_NC(GPIO_140, DN_20K), - /* GPIO_141: Not Connected */ PAD_NC(GPIO_141, DN_20K), - /* GPIO_142: PMU_WAKE# */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_142, 1, DEEP, UP_20K, IGNORE, SAME), - /* GPIO_143: Not Connected */ PAD_NC(GPIO_143, DN_20K), - /* GPIO_144: Not Connected */ PAD_NC(GPIO_144, DN_20K), - /* GPIO_145: Not Connected */ PAD_NC(GPIO_145, DN_20K), - /* GPIO_146: Not Connected */ PAD_NC(GPIO_146, DN_20K), - /* GPIO 147 through 156 are configured by the TXE */ - /* GPIO_147: LPC_SERIRQ */ - /* GPIO_148: LPC_CLK0 */ - /* GPIO_149: LPC_CLK_DBG_CPU */ - /* GPIO_150: LPC_AD0 */ - /* GPIO_151: LPC_AD1 */ - /* GPIO_152: LPC_AD2 */ - /* GPIO_153: LPC_AD3 */ - /* GPIO_154: LPC_CLKRUN# */ - /* GPIO_155: LPC_FRAME# */ - - /* ----- GPIO Group Audio ----- */ - /* GPIO_156: FP_INT# */ - /* GPIO_157: Not Connected */ + /* GPIO 147 through 155 are configured by the TXE. */ + PAD_NC(GPIO_156, DN_20K), PAD_NC(GPIO_157, DN_20K), - /* GPIO_158: Not Connected */ PAD_NC(GPIO_158, DN_20K), - /* GPIO_159: Not Connected */ PAD_NC(GPIO_159, DN_20K), - /* GPIO_160: Not Connected */ PAD_NC(GPIO_160, DN_20K), - /* GPIO_161: GPIO_161 */ PAD_NC(GPIO_161, DN_20K), - /* GPIO_162: Not Connected */ PAD_NC(GPIO_162, DN_20K), - /* GPIO_163: GPIO_163 */ PAD_NC(GPIO_163, DN_20K), - /* GPIO_164: GPIO_164 */ PAD_NC(GPIO_164, DN_20K), - /* GPIO_165: GPIO_165 */ PAD_NC(GPIO_165, DN_20K), - /* GPIO_166: HDA_BCLK_CPU_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - /* GPIO_167: HDA_SYNC_CPU_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - /* GPIO_168: GPIO_168 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - /* GPIO_169: HDA_SDATAOUT */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - /* GPIO_170: HDA_RST# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - /* GPIO_171: Not Connected */ PAD_NC(GPIO_171, DN_20K), - /* GPIO_172: Not Connected */ PAD_NC(GPIO_172, DN_20K), - /* GPIO_173: Not Connected */ PAD_NC(GPIO_173, DN_20K), - /* GPIO_174: VDD2 1.20V / 1.24V Mode */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_174, 1, DEEP, DN_20K, TxLASTRxE, ENPU), - /* GPIO_175: eSPI / LPC Mode */ - PAD_NC(GPIO_175, NONE), - - /* ----- GPIO Group SCC ----- */ - /* GPIO_176: Not Connected */ PAD_NC(GPIO_176, DN_20K), - /* GPIO_177: TP_INT# */ - PAD_CFG_GPI_GPIO_DRIVER(GPIO_177, NONE, PLTRST), - /* GPIO_178: Not Connected */ PAD_NC(GPIO_178, DN_20K), - /* GPIO_187: Not Connected */ - PAD_NC(GPIO_187, DN_20K), - /* GPIO_179: Not Connected */ PAD_NC(GPIO_179, DN_20K), - /* GPIO_181: Not Connected */ + PAD_NC(GPIO_180, DN_20K), PAD_NC(GPIO_181, DN_20K), - /* GPIO_182: Not Connected */ PAD_NC(GPIO_182, DN_20K), - /* GPIO_183: Not Connected */ PAD_NC(GPIO_183, DN_20K), - /* GPIO_184: Not Connected */ PAD_NC(GPIO_184, DN_20K), - /* GPIO_185: WLAN_RST_N_R */ PAD_NC(GPIO_185, DN_20K), - /* GPIO_186: Not Connected */ PAD_NC(GPIO_186, DN_20K), - /* GPIO_188: Not Connected */ + PAD_NC(GPIO_187, DN_20K), PAD_NC(GPIO_188, DN_20K), - /* GPIO_210: Not Connected */ - PAD_NC(GPIO_210, DN_20K), - /* GPIO_189: Not Connected */ PAD_NC(GPIO_189, DN_20K), - /* GPIO_190: Not Connected */ PAD_NC(GPIO_190, DN_20K), - /* GPIO_191: eSPI Flash Sharing */ - PAD_NC(GPIO_191, NONE), - /* GPIO_192: CNVI_BRI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), - /* GPIO_193: CNVI_RGI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), - /* GPIO_194: GPIO_194 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), - /* GPIO_195: CNVI_RF_RESET_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), - /* GPIO_198: EMMC_CLK */ + PAD_NC(GPIO_197, DN_20K), PAD_NC(GPIO_198, DN_20K), - /* GPIO_200: EMMC_DATA_0 */ + PAD_NC(GPIO_199, DN_20K), PAD_NC(GPIO_200, DN_20K), - /* GPIO_201: EMMC_DATA_1 */ PAD_NC(GPIO_201, DN_20K), - /* GPIO_202: EMMC_DATA_2 */ PAD_NC(GPIO_202, DN_20K), - /* GPIO_203: EMMC_DATA_3 */ PAD_NC(GPIO_203, DN_20K), - /* GPIO_204: EMMC_DATA_4 */ PAD_NC(GPIO_204, DN_20K), - /* GPIO_205: EMMC_DATA_5 */ PAD_NC(GPIO_205, DN_20K), - /* GPIO_206: EMMC_DATA_6 */ PAD_NC(GPIO_206, DN_20K), - /* GPIO_207: EMMC_DATA_7 */ PAD_NC(GPIO_207, DN_20K), - /* GPIO_208: EMMC_CMD */ PAD_NC(GPIO_208, DN_20K), - /* GPIO_209: EMMC_STROBE */ PAD_NC(GPIO_209, DN_20K), + PAD_NC(GPIO_210, DN_20K), + PAD_NC(GPIO_211, UP_20K), + PAD_NC(GPIO_212, DN_20K), + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), }; +/* clang-format on */ const struct pad_config *variant_gpio_table(size_t *num) { diff --git a/src/mainboard/starlabs/lite/variants/glk/hda_verb.c b/src/mainboard/starlabs/lite/variants/glk/hda_verb.c index 0e8869c6c1f..a27c8892084 100644 --- a/src/mainboard/starlabs/lite/variants/glk/hda_verb.c +++ b/src/mainboard/starlabs/lite/variants/glk/hda_verb.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ 0x10ec111e, /* Subsystem ID */ - 15, /* Number of jacks (NID entries) */ + 15, /* Number of verb entries */ /* Reset Codec First */ AZALIA_RESET(0x1), @@ -16,20 +17,56 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb-table */ AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x14, 0x94171110), - AZALIA_PIN_CFG(0, 0x15, 0x042b1010), - AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1a, 0x93171110), - AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_SPEAKERS, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_RIGHT, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_COMBINATION, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_COMBINATION, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_LEFT, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)), 0x00370600, 0x00270600, - 0x00b707C0, + 0x00b707c0, 0x00d70740, 0x0017a200, @@ -37,18 +74,8 @@ const u32 cim_verb_data[] = { 0x0017a208, 0x00170500, - 0x8086280d, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(2, 0x80860101), - - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - AZALIA_PIN_CFG(2, 0x07, 0x18560030), }; -const u32 pc_beep_verbs[] = { -}; +const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/lite/board.fmd b/src/mainboard/starlabs/lite/variants/glkr/board.fmd similarity index 84% rename from src/mainboard/starlabs/lite/board.fmd rename to src/mainboard/starlabs/lite/variants/glkr/board.fmd index 065ea619bd4..52575a27948 100644 --- a/src/mainboard/starlabs/lite/board.fmd +++ b/src/mainboard/starlabs/lite/variants/glkr/board.fmd @@ -36,24 +36,23 @@ # 000C4000 001C6FFF 00103000 CSE Main Partition # 00380000 006FEFFF 0037F000 Boot Partition 2 # 00380000 003801FF 00000200 Primary Boot Partition -# 00380200 0062FFFF 002AFE00 Secondary Boot Partition -# 00381000 0062FFFF 002AF000 OBB Partition -# 006FF000 007FFFFF 00101000 TXE Data Region +# 00380200 0066FFFF 002EFE00 Secondary Boot Partition +# 00381000 0066FFFF 002EF000 OBB Partition +# 006FF000 007FFFFF 00101000 Device Expansion Region # coreboot only needs to know about the OBB. It's nested inside OBBP, to account for # the header. FLASH 8M { OBBP@0x382000 { OBB@0x0 0x2ee000 { - FMAP@0xe000 0x10000 - COREBOOT(CBFS)@0x1e000 0x210000 - FPF_STATUS@0x22e000 0x10000 - UNIFIED_MRC_CACHE@0x23e000 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x10000 + FPF_STATUS@0x0 0x1000 + UNIFIED_MRC_CACHE@0xe000 0x11000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VAR_MRC_CACHE@0x10000 0x1000 } - SMMSTORE@0x26e000 0x80000 + SMMSTORE@0x2e000 0x80000 + FMAP@0xae000 0x200 + COREBOOT(CBFS)@0xae200 0x1ffe00 } } } diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index bd25b0e68dd..4ec957358bf 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -22,8 +22,6 @@ chip soc/intel/apollolake register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_bios_config_lockdown" = "1" - register "enhanced_cstates" = "1" - register "pnp_settings" = "PNP_PERF_POWER" register "mod_phy_if_value" = "0x12" @@ -47,12 +45,7 @@ chip soc/intel/apollolake register "pcie_rp_deemphasis_enable[4]" = "1" register "pcie_rp_deemphasis_enable[5]" = "1" - # GPE configuration - register "gpe0_dw1" = "PMC_GPE_NW_63_32" - register "gpe0_dw2" = "PMC_GPE_N_95_64" - register "gpe0_dw3" = "PMC_GPE_NW_31_0" - - register "slp_s3_assertion_width_usecs" = "28000" + register "slp_s3_assertion_width_usecs" = "1000" device domain 0 on device ref igd on @@ -65,7 +58,7 @@ chip soc/intel/apollolake device generic 0 on end end end - device ref pmc on end + device ref pmc hidden end device ref p2sb on end device ref fast_spi on end device ref sram on end @@ -80,19 +73,87 @@ chip soc/intel/apollolake end device ref xhci on # Motherboard USB 3.0 Type-C - register "usb2_port[0]" = "PORT_EN(OC1)" - register "usb3_port[0]" = "PORT_EN(OC1)" + register "usb2_port[0]" = "PORT_EN(OC_SKIP)" + register "usb3_port[0]" = "PORT_EN(OC_SKIP)" # Motherboard USB 3.0 Type-A - register "usb2_port[1]" = "PORT_EN(OC0)" - register "usb3_port[1]" = "PORT_EN(OC0)" + register "usb2_port[1]" = "PORT_EN(OC_SKIP)" + register "usb3_port[1]" = "PORT_EN(OC_SKIP)" # Daughterboard USB 3.0 Type-A - register "usb2_port[3]" = "PORT_EN(OC1)" - register "usb3_port[4]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC_SKIP)" + register "usb3_port[4]" = "PORT_EN(OC_SKIP)" # Daughterboard SD Card register "usb2_port[5]" = "PORT_EN(OC_SKIP)" + + # Internal Webcam + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb3_port1 on end + end + + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Motherboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb3_port2 on end + end + + chip drivers/usb/acpi + register "desc" = ""Daughterboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Daughterboard USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port5 on end + end + + chip drivers/usb/acpi + register "desc" = ""SD Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port6 on end + end + + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "1" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port7 on end + end + + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port8 on end + end + end + end end device ref i2c4 on end device ref i2c7 on @@ -100,7 +161,7 @@ chip soc/intel/apollolake end device ref uart0 on end device ref uart2 on end - device ref spi2 on end + device ref spi2 off end device ref lpc_espi on register "gen1_dec" = "0x00040069" register "gen2_dec" = "0x00fc0201" diff --git a/src/mainboard/starlabs/lite/variants/glkr/gpio.c b/src/mainboard/starlabs/lite/variants/glkr/gpio.c index 41d2b47c300..9a48e7305c8 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glkr/gpio.c @@ -245,7 +245,7 @@ const struct pad_config gpio_table[] = { /* GPIO_107: PMU_RSTBTN# */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1), /* GPIO_108: SUS_CLK */ - PAD_NC(GPIO_108, NONE), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1), /* GPIO_109: PMU_SUS_STAT# */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1), /* GPIO_110: I2C_5 SDA */ diff --git a/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c index ebbd4606fe6..d4f7d7ab232 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c +++ b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ 0x10ec111e, /* Subsystem ID */ - 15, /* Number of jacks (NID entries) */ + 15, /* Number of verb entries */ /* Reset Codec First */ AZALIA_RESET(0x1), @@ -16,20 +17,56 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb-table */ AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x14, 0x94171110), - AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x18, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1a, 0x93171110), - AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_SPEAKERS, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_RIGHT, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_COMBINATION, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_LEFT, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_COMBINATION, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, + 0 + )), 0x00370600, 0x00270600, - 0x00b707C0, + 0x00b707c0, 0x00d70740, 0x0017a200, @@ -37,18 +74,8 @@ const u32 cim_verb_data[] = { 0x0017a208, 0x00170500, - 0x8086280d, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(2, 0x80860101), - - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - AZALIA_PIN_CFG(2, 0x07, 0x18560030), }; -const u32 pc_beep_verbs[] = { -}; +const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index bae92d02399..42e36ce2324 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -30,6 +30,7 @@ config BOARD_STARLABS_LABTOP_KBL select HAVE_SPD_IN_CBFS select SOC_INTEL_KABYLAKE select SPI_FLASH_GIGADEVICE + select STARLABS_LEGACY_PL4 select TPM2 config BOARD_STARLABS_LABTOP_CML @@ -41,6 +42,7 @@ config BOARD_STARLABS_LABTOP_CML select CRB_TPM select SOC_INTEL_COMETLAKE_1 select SPI_FLASH_WINBOND + select STARLABS_LEGACY_PL4 select TPM2 config BOARD_STARLABS_STARBOOK_TGL @@ -150,10 +152,6 @@ config EC_STARLABS_ITE_BIN_PATH config EC_VARIANT_DIR default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL -config EDK2_BOOTSPLASH_FILE - string - default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" @@ -249,9 +247,4 @@ config BOARD_SUPPORTS_HOTPLUG default y if BOARD_STARLABS_STARBOOK_ADL default n -config BOARD_USES_FIXED_MODE_VBT - bool - default y if BOARD_STARLABS_STARBOOK_ADL_N || BOARD_STARLABS_STARBOOK_MTL - default n - endif diff --git a/src/mainboard/starlabs/starbook/acpi/ec.asl b/src/mainboard/starlabs/starbook/acpi/ec.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/starbook/acpi/ec.asl +++ b/src/mainboard/starlabs/starbook/acpi/ec.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/starbook/acpi/superio.asl b/src/mainboard/starlabs/starbook/acpi/superio.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/starbook/acpi/superio.asl +++ b/src/mainboard/starlabs/starbook/acpi/superio.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c index a561666812c..7f388ff7b54 100644 --- a/src/mainboard/starlabs/starbook/cfr.c +++ b/src/mainboard/starlabs/starbook/cfr.c @@ -4,13 +4,87 @@ #include #include #include +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM) +#include +#endif #include #include +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM) +static const struct pcie_pm_option_names pciexp_wifi_names = { + .clk_pm = "pciexp_wifi_clk_pm", + .aspm = "pciexp_wifi_aspm", + .l1ss = "pciexp_wifi_l1ss", + .speed = "pciexp_speed", +}; + +static const struct pcie_pm_option_names pciexp_ssd_names = { + .clk_pm = "pciexp_ssd_clk_pm", + .aspm = "pciexp_ssd_aspm", + .l1ss = "pciexp_ssd_l1ss", + .speed = "pciexp_speed", +}; + +void mainboard_get_pcie_pm_options(const struct pcie_rp_config *rp_cfg, + unsigned int index, + bool is_cpu_rp, + struct pcie_pm_option_names *names) +{ + (void)rp_cfg; + + if (!names) + return; + +#if CONFIG(BOARD_STARLABS_STARBOOK_RPL) + if (is_cpu_rp) { + if (index == CPU_RP(1)) + *names = pciexp_ssd_names; + return; + } +#else + if (is_cpu_rp) + return; +#endif + +#if CONFIG(BOARD_STARLABS_STARBOOK_ADL) + switch (index) { + case PCH_RP(5): + *names = pciexp_wifi_names; + return; + case PCH_RP(9): + *names = pciexp_ssd_names; + return; + } +#elif CONFIG(BOARD_STARLABS_STARBOOK_ADL_N) + switch (index) { + case PCH_RP(7): + *names = pciexp_wifi_names; + return; + case PCH_RP(9): + *names = pciexp_ssd_names; + return; + } +#elif CONFIG(BOARD_STARLABS_STARBOOK_MTL) + switch (index) { + case PCH_RP(9): + *names = pciexp_wifi_names; + return; + case PCH_RP(10): + *names = pciexp_ssd_names; + return; + } +#elif CONFIG(BOARD_STARLABS_STARBOOK_RPL) + if (index == PCH_RP(5)) + *names = pciexp_wifi_names; +#endif +} +#endif + static struct sm_obj_form audio_video_group = { .ui_name = "Audio/Video", .obj_list = (const struct sm_object *[]) { µphone, + &hda_dsp, &webcam, NULL }, @@ -69,14 +143,20 @@ static struct sm_obj_form pcie_power_management_group = { .ui_name = "PCIe Power Management", .obj_list = (const struct sm_object *[]) { #if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM) - #if CONFIG(BOARD_STARLABS_STARBOOK_RPL) - &pciexp_aspm_cpu, + #if CONFIG(BOARD_STARLABS_STARBOOK_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_ADL_N) || \ + CONFIG(BOARD_STARLABS_STARBOOK_MTL) || CONFIG(BOARD_STARLABS_STARBOOK_RPL) + &pciexp_wifi_clk_pm, + &pciexp_wifi_aspm, + &pciexp_wifi_l1ss, + &pciexp_ssd_clk_pm, + &pciexp_ssd_aspm, + &pciexp_ssd_l1ss, #else &pciexp_aspm, - #endif &pciexp_clk_pm, &pciexp_l1ss, #endif + #endif NULL }, }; @@ -92,6 +172,12 @@ static struct sm_obj_form performance_group = { &hyper_threading, #endif &power_profile, + &pl1_override, + &pl2_override, + #if CONFIG(STARLABS_LEGACY_PL4) + &pl4_override, + #endif + &tcc_temp, #if CONFIG(SOC_INTEL_METEORLAKE) &vpu, #endif @@ -109,6 +195,10 @@ static struct sm_obj_form security_group = { &intel_tme, &me_state, &me_state_counter, + #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || \ + CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE) + &ibecc, + #endif NULL }, }; diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index a1e411549d2..480145217f9 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include /* PS/2 Keyboard */ - #include + #include } #include diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c index 93982cf8071..bd857d6ee62 100644 --- a/src/mainboard/starlabs/starbook/mainboard.c +++ b/src/mainboard/starlabs/starbook/mainboard.c @@ -2,8 +2,6 @@ #include #include -#include -#include #include static void starlabs_configure_gpios(void *unused) @@ -18,8 +16,3 @@ static void starlabs_configure_gpios(void *unused) BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_gpios, NULL); struct chip_operations mainboard_ops = {}; - -const char *mainboard_vbt_filename(void) -{ - return "vbt.bin"; -} diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt index 711e5311d30..fe19a320f77 100644 Binary files a/src/mainboard/starlabs/starbook/variants/adl/data.vbt and b/src/mainboard/starlabs/starbook/variants/adl/data.vbt differ diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 55cc2d5cb59..7c10a50abf9 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP UPDs register "eist_enable" = "true" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "energy_efficient_turbo" = "true" register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c index c98504a60fd..9a02f7c5e15 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c index e57cc32a3dd..234c0abc7a3 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c @@ -29,6 +29,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt index 0cd0ec4b777..9e028cbe75d 100644 Binary files a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt and b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt differ diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c index 11aa0f42f30..b17964a5ddf 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c index 7141d59301a..c105a7eab7a 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c @@ -26,6 +26,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index c9595dc6fdc..8848ff5b678 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # FSP UPDs register "eist_enable" = "true" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "SaGv" = "SaGv_Enabled" # Graphics diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c index c6ebe0a3846..ccd6d0d7590 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c index a2c42c3d3b4..87c9eea6811 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt index f855dabf240..6018e334b54 100644 Binary files a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt and b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt differ diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c index ceeac0e33df..6f3c01a7f81 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index ceff083d00c..12cee9df89a 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -29,6 +29,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcfg_init(mupd, &mem_config, &ddr5_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt index 32a044ccf76..8b3f851aa48 100644 Binary files a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt and b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt differ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c index e7ced59fdcc..24afc877b63 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c index c1d646f860a..e0dbb3659b7 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c @@ -29,6 +29,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/starlabs/starbook/variants/tgl/data.vbt b/src/mainboard/starlabs/starbook/variants/tgl/data.vbt index ca57e717f30..0efa421a97f 100644 Binary files a/src/mainboard/starlabs/starbook/variants/tgl/data.vbt and b/src/mainboard/starlabs/starbook/variants/tgl/data.vbt differ diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 3221a73a20a..35912ddec8e 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig index b7795cc6aa1..8a8a583e9db 100644 --- a/src/mainboard/starlabs/starfighter/Kconfig +++ b/src/mainboard/starlabs/starfighter/Kconfig @@ -48,10 +48,6 @@ config BOARD_STARLABS_STARFIGHTER_MTL if BOARD_STARLABS_STARFIGHTER_SERIES -config BOARD_USES_FIXED_MODE_VBT - bool - default y - config CCD_PORT int default 4 @@ -81,10 +77,6 @@ config EC_STARLABS_ITE_BIN_PATH string default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" -config EDK2_BOOTSPLASH_FILE - string - default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/mainboard/starlabs/starfighter/acpi/ec.asl b/src/mainboard/starlabs/starfighter/acpi/ec.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/starfighter/acpi/ec.asl +++ b/src/mainboard/starlabs/starfighter/acpi/ec.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/starfighter/acpi/superio.asl b/src/mainboard/starlabs/starfighter/acpi/superio.asl index 853b0877b33..16990d45f42 100644 --- a/src/mainboard/starlabs/starfighter/acpi/superio.asl +++ b/src/mainboard/starlabs/starfighter/acpi/superio.asl @@ -1 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c index 2d3c6c3967a..bf9f852d16b 100644 --- a/src/mainboard/starlabs/starfighter/cfr.c +++ b/src/mainboard/starlabs/starfighter/cfr.c @@ -4,10 +4,100 @@ #include #include #include +#include #include #include #include +static const struct pcie_pm_option_names pciexp_wifi_names = { + .clk_pm = "pciexp_wifi_clk_pm", + .aspm = "pciexp_wifi_aspm", + .l1ss = "pciexp_wifi_l1ss", + .speed = "pciexp_speed", +}; + +static const struct pcie_pm_option_names pciexp_ssd_names = { + .clk_pm = "pciexp_ssd_clk_pm", + .aspm = "pciexp_ssd_aspm", + .l1ss = "pciexp_ssd_l1ss", + .speed = "pciexp_speed", +}; + +static const struct pcie_pm_option_names pciexp_ssd2_names = { + .clk_pm = "pciexp_ssd2_clk_pm", + .aspm = "pciexp_ssd2_aspm", + .l1ss = "pciexp_ssd2_l1ss", + .speed = "pciexp_speed", +}; + +void mainboard_get_pcie_pm_options(const struct pcie_rp_config *rp_cfg, + unsigned int index, + bool is_cpu_rp, + struct pcie_pm_option_names *names) +{ + (void)rp_cfg; + + if (!names) + return; + +#if CONFIG(BOARD_STARLABS_STARFIGHTER_RPL) + if (is_cpu_rp) { + if (index == CPU_RP(1)) + *names = pciexp_ssd_names; + return; + } +#else + if (is_cpu_rp) + return; +#endif + +#if CONFIG(BOARD_STARLABS_STARFIGHTER_RPL) + switch (index) { + case PCH_RP(5): + *names = pciexp_wifi_names; + return; + case PCH_RP(9): + *names = pciexp_ssd2_names; + return; + } +#elif CONFIG(BOARD_STARLABS_STARFIGHTER_MTL) + switch (index) { + case PCH_RP(9): + *names = pciexp_wifi_names; + return; + case PCH_RP(10): + *names = pciexp_ssd_names; + return; + case PCH_RP(1): + *names = pciexp_ssd2_names; + return; + } +#endif +} + +#if CONFIG(BOARD_STARLABS_STARFIGHTER_MTL) +static const struct sm_object firmware_enable_amp = SM_DECLARE_BOOL({ + .opt_name = "firmware_enable_amp", + .ui_name = "Firmware Enables AMP", + .ui_helptext = "Enabled: assert LINE2 EAPD and drive GPIO2 high " + "during HDA initialization.\n" + "Disabled: leave the speaker amp off for OS runtime " + "sequencing.", + .default_value = true, +}); +#endif + +static struct sm_obj_form audio_group = { + .ui_name = "Audio", + .obj_list = (const struct sm_object *[]) { + &hda_dsp, + #if CONFIG(BOARD_STARLABS_STARFIGHTER_MTL) + &firmware_enable_amp, + #endif + NULL + }, +}; + static struct sm_obj_form battery_group = { .ui_name = "Battery", .obj_list = (const struct sm_object *[]) { @@ -48,6 +138,17 @@ static struct sm_obj_form keyboard_group = { }, }; +static struct sm_obj_form trackpad_group = { + .ui_name = "Trackpad", + .obj_list = (const struct sm_object *[]) { + &touchpad_haptics, + &touchpad_force_press, + &touchpad_force_release, + &touchpad_report_rate, + NULL + }, +}; + static struct sm_obj_form leds_group = { .ui_name = "LEDs", .obj_list = (const struct sm_object *[]) { @@ -61,12 +162,15 @@ static struct sm_obj_form pcie_power_management_group = { .ui_name = "PCIe Power Management", .obj_list = (const struct sm_object *[]) { #if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM) - &pciexp_aspm, - #if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) - &pciexp_aspm_cpu, - #endif - &pciexp_clk_pm, - &pciexp_l1ss, + &pciexp_wifi_clk_pm, + &pciexp_wifi_aspm, + &pciexp_wifi_l1ss, + &pciexp_ssd_clk_pm, + &pciexp_ssd_aspm, + &pciexp_ssd_l1ss, + &pciexp_ssd2_clk_pm, + &pciexp_ssd2_aspm, + &pciexp_ssd2_l1ss, #endif NULL }, @@ -82,6 +186,12 @@ static struct sm_obj_form performance_group = { &hyper_threading, &memory_speed, &power_profile, + &pl1_override, + &pl2_override, + #if CONFIG(STARLABS_LEGACY_PL4) + &pl4_override, + #endif + &tcc_temp, #if CONFIG(SOC_INTEL_METEORLAKE) &vpu, #endif @@ -96,6 +206,9 @@ static struct sm_obj_form security_group = { &intel_tme, &me_state, &me_state_counter, + #if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE) + &ibecc, + #endif NULL }, }; @@ -122,18 +235,22 @@ static struct sm_obj_form virtualization_group = { static struct sm_obj_form wireless_group = { .ui_name = "Wireless", .obj_list = (const struct sm_object *[]) { + &bluetooth, &bluetooth_rtd3, + &wifi, NULL }, }; static struct sm_obj_form *sm_root[] = { + &audio_group, &battery_group, &debug_group, #if CONFIG(DRIVERS_INTEL_USB4_RETIMER) &io_expansion_group, #endif &keyboard_group, + &trackpad_group, &leds_group, &pcie_power_management_group, &performance_group, diff --git a/src/mainboard/starlabs/starfighter/dsdt.asl b/src/mainboard/starlabs/starfighter/dsdt.asl index a2b00e54ea9..d3af9a9725e 100644 --- a/src/mainboard/starlabs/starfighter/dsdt.asl +++ b/src/mainboard/starlabs/starfighter/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include /* PS/2 Keyboard */ - #include + #include } #include diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c index e0b6ffae490..bd857d6ee62 100644 --- a/src/mainboard/starlabs/starfighter/mainboard.c +++ b/src/mainboard/starlabs/starfighter/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include static void starlabs_configure_gpios(void *unused) diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk index 93240a13077..19f5cb80ff6 100644 --- a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk +++ b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk @@ -8,6 +8,7 @@ romstage-y += romstage.c ramstage-y += board_id.c ramstage-y += devtree.c ramstage-y += gpio.c +ramstage-y += hda.c ramstage-y += hda_verb.c ramstage-y += ramstage.c $(call add_vbt_to_cbfs, vbt_qhd.bin, data_qhd.vbt) diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt index cd70aad5d91..36220dffc0a 100644 Binary files a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt and b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt differ diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt index 2235579a167..58c31033a36 100644 Binary files a/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt and b/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt differ diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c index a7ed4a749f5..e6f45793202 100644 --- a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c +++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/hda.c b/src/mainboard/starlabs/starfighter/variants/mtl/hda.c new file mode 100644 index 00000000000..5c3bc4dec19 --- /dev/null +++ b/src/mainboard/starlabs/starfighter/variants/mtl/hda.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define STARFIGHTER_GPIO2 0x04 +#define STARFIGHTER_EAPD 0x02 + +static const uint32_t speaker_amp_enable_verb[] = { + 0x05750003, + 0x057486a6, + 0x02050034, + 0x02048204, + + 0x0205001b, + 0x02040a0b, + 0x02050046, + 0x02040004, + + 0x02050008, + 0x02046a0c, + 0x02050040, + 0x02041800, + + 0x02050037, + 0x02044a06, + 0x0205004c, + 0x02044803, + + 0x02050019, + 0x02040a10, + 0x02050035, + 0x020488aa, + + AZALIA_VERB_12B(0, 0x01, 0x716, STARFIGHTER_GPIO2), + AZALIA_VERB_12B(0, 0x01, 0x717, STARFIGHTER_GPIO2), + AZALIA_VERB_12B(0, 0x01, 0x715, STARFIGHTER_GPIO2), + AZALIA_VERB_12B(0, ALC269_LINE2, 0x70c, STARFIGHTER_EAPD), +}; + +static const uint32_t microphone_disable_verb[] = { + AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_CFG_NC(0)), +}; + +void mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid) +{ + (void)viddid; + + if (get_uint_option("microphone", 1) == 0) + azalia_program_verb_table(base, microphone_disable_verb, + ARRAY_SIZE(microphone_disable_verb)); + + if (get_uint_option("firmware_enable_amp", 1)) + azalia_program_verb_table(base, speaker_amp_enable_verb, + ARRAY_SIZE(speaker_amp_enable_verb)); +} diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c index 9c73edc6abe..79f62f536db 100644 --- a/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c +++ b/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c @@ -7,7 +7,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0235, /* Codec Vendor / Device ID: Realtek ALC235 */ 0x20147017, /* Subsystem ID */ - 18, /* Number of verb entries */ + 13, /* Number of verb entries */ /* Reset Codec First */ AZALIA_RESET(0x1), @@ -36,7 +36,7 @@ const u32 cim_verb_data[] = { 4, 0 )), - /* Internal speakers are connected to LINE2 and external amps */ + /* Internal speakers are connected to LINE2 */ AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_DESC( AZALIA_INTEGRATED, AZALIA_INTERNAL | AZALIA_FRONT, @@ -74,30 +74,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)), - 0x05750003, - 0x057486a6, - 0x02050034, - 0x02048204, - - 0x0205001b, - 0x02040a0b, - 0x02050046, - 0x02040004, - - 0x02050008, - 0x02046a0c, - 0x02050040, - 0x02041800, - - 0x02050037, - 0x02044a06, - 0x0205004c, - 0x02044803, - - 0x02050019, - 0x02040a10, - 0x02050035, - 0x020488aa, }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c index 4a50059cd52..4c1169348bb 100644 --- a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c @@ -1,11 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include #include #include +#define MEMORY_SPEED_DEFAULT 1 + static uint8_t strap_to_memcfg_index(uint8_t strap) { switch (strap) { @@ -23,6 +28,26 @@ static uint8_t memcfg_and_speed_to_cbfs_index(uint8_t memcfg, unsigned int speed return (uint8_t)(memcfg * 3 + speed); } +static unsigned int get_memory_speed_option(void) +{ + return starlabs_get_memory_speed_option(MEMORY_SPEED_DEFAULT); +} + +static uint8_t get_spd_cbfs_index(void) +{ + const uint8_t strap = get_memory_config_straps(); + const uint8_t memcfg = strap_to_memcfg_index(strap); + const unsigned int speed = get_memory_speed_option(); + const uint8_t cbfs_index = memcfg_and_speed_to_cbfs_index(memcfg, speed); + + return cbfs_index; +} + +uint8_t fsp_memory_mainboard_version(void) +{ + return get_spd_cbfs_index(); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { const struct mb_cfg mem_config = { @@ -86,16 +111,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const uint8_t cbfs_index = get_spd_cbfs_index(); + + printk(BIOS_INFO, "Memory straps=%u SPD index=%u\n", get_memory_config_straps(), + cbfs_index); const struct mem_spd lpddr5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = memcfg_and_speed_to_cbfs_index( - strap_to_memcfg_index(get_memory_config_straps()), - get_uint_option("memory_speed", 1)), + .cbfs_index = cbfs_index, }; memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt index b0222677f63..92c96c4f967 100644 Binary files a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt and b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt differ diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c index 7609e0c5154..f7293170141 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c index 6e4471589eb..6ffe593f7f2 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include @@ -12,8 +11,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd) if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; } - -const char *mainboard_vbt_filename(void) -{ - return "vbt.bin"; -} diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c index 42425606881..f4fde893a2e 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include @@ -7,6 +10,8 @@ #include +#define MEMORY_SPEED_DEFAULT 1 + static uint8_t get_memory_config_straps(void) { /* @@ -59,6 +64,26 @@ static uint8_t memcfg_and_speed_to_cbfs_index(uint8_t memcfg, unsigned int speed return (uint8_t)(memcfg * 3 + speed); } +static unsigned int get_memory_speed_option(void) +{ + return starlabs_get_memory_speed_option(MEMORY_SPEED_DEFAULT); +} + +static uint8_t get_spd_cbfs_index(void) +{ + const uint8_t strap = get_memory_config_straps(); + const uint8_t memcfg = strap_to_memcfg_index(strap); + const unsigned int speed = get_memory_speed_option(); + const uint8_t cbfs_index = memcfg_and_speed_to_cbfs_index(memcfg, speed); + + return cbfs_index; +} + +uint8_t fsp_memory_mainboard_version(void) +{ + return get_spd_cbfs_index(); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { const struct mb_cfg mem_config = { @@ -122,16 +147,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const uint8_t cbfs_index = get_spd_cbfs_index(); + + printk(BIOS_INFO, "Memory straps=%u SPD index=%u\n", get_memory_config_straps(), + cbfs_index); const struct mem_spd lpddr5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = memcfg_and_speed_to_cbfs_index( - strap_to_memcfg_index(get_memory_config_straps()), - get_uint_option("memory_speed", 1)), + .cbfs_index = cbfs_index, }; memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); + mupd->FspmConfig.PchHdaDspEnable = get_uint_option("hda_dsp", 1); + const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index fbf896c6ae9..d25288420f4 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -28,6 +28,16 @@ chip soc/intel/skylake [6] = 1, [7] = 1, }" + register "SataPortsHotPlug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index a444da0441e..16dec041321 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -4,10 +4,10 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/addw1/Makefile.mk b/src/mainboard/system76/addw1/Makefile.mk index 09424595d72..1447b6a87f5 100644 --- a/src/mainboard/system76/addw1/Makefile.mk +++ b/src/mainboard/system76/addw1/Makefile.mk @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/addw1/acpi/mainboard.asl b/src/mainboard/system76/addw1/acpi/mainboard.asl index 4e67439c569..2f01acc0bc4 100644 --- a/src/mainboard/system76/addw1/acpi/mainboard.asl +++ b/src/mainboard/system76/addw1/acpi/mainboard.asl @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index cd93ddcc148..093ce97c4b3 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc @@ -55,6 +55,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device ref igpu on end device ref dptf on end diff --git a/src/mainboard/system76/addw1/romstage.c b/src/mainboard/system76/addw1/romstage.c index 02634ba2ad2..f5b0308f727 100644 --- a/src/mainboard/system76/addw1/romstage.c +++ b/src/mainboard/system76/addw1/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include static const struct cnl_mb_cfg memcfg = { .spd[0] = { @@ -20,5 +22,20 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, +#ifdef DGPU_PWRGD + .power_good_gpio = DGPU_PWRGD, +#endif + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c index 340d97d2f0e..2d9351275ae 100644 --- a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155865d1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155865d1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155865d1, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/addw1/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h similarity index 53% rename from src/mainboard/system76/addw1/include/variant/gpio.h rename to src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h index 95d576294f6..c78f11b4cd0 100644 --- a/src/mainboard/system76/addw1/include/variant/gpio.h +++ b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h @@ -3,7 +3,16 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x65d11558 + +#ifndef __ACPI__ void variant_configure_early_gpios(void); void variant_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/addw1/variants/addw2/gpio.c b/src/mainboard/system76/addw1/variants/addw2/gpio.c index e6355550bc6..2013e454a8f 100644 --- a/src/mainboard/system76/addw1/variants/addw2/gpio.c +++ b/src/mainboard/system76/addw1/variants/addw2/gpio.c @@ -254,7 +254,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_K20, NONE), PAD_NC(GPP_K21, NONE), PAD_CFG_GPO(GPP_K22, 0, DEEP), // DGPU_OVRM - PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK + //PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK }; void variant_configure_gpios(void) diff --git a/src/mainboard/system76/addw1/variants/addw2/gpio_early.c b/src/mainboard/system76/addw1/variants/addw2/gpio_early.c index 9af888be4cf..14cee554a3d 100644 --- a/src/mainboard/system76/addw1/variants/addw2/gpio_early.c +++ b/src/mainboard/system76/addw1/variants/addw2/gpio_early.c @@ -6,8 +6,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c index 54ff866b50c..32bf0339a34 100644 --- a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155865e1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155865e1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155865e1, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h new file mode 100644 index 00000000000..255b7c7905f --- /dev/null +++ b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_PWRGD GPP_K23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x65e11558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 18c5e9b2d19..70a7f826f84 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -2,7 +2,6 @@ config BOARD_SYSTEM76_ADL_COMMON def_bool n - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL @@ -11,6 +10,7 @@ config BOARD_SYSTEM76_ADL_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -35,10 +35,12 @@ config BOARD_SYSTEM76_GALP6 config BOARD_SYSTEM76_GAZE17_3050 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA select EC_SYSTEM76_EC_DGPU config BOARD_SYSTEM76_GAZE17_3060_B select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA select EC_SYSTEM76_EC_DGPU select MAINBOARD_USES_IFD_GBE_REGION @@ -48,11 +50,15 @@ config BOARD_SYSTEM76_LEMP11 config BOARD_SYSTEM76_ORYP9 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC_DGPU config BOARD_SYSTEM76_ORYP10 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ADL_COMMON @@ -97,12 +103,22 @@ config MAINBOARD_VERSION default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8 + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + config CONSOLE_POST default y config D3COLD_SUPPORT default n +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/system76/adl/Makefile.mk b/src/mainboard/system76/adl/Makefile.mk index c5334f1f0cf..727ce27218c 100644 --- a/src/mainboard/system76/adl/Makefile.mk +++ b/src/mainboard/system76/adl/Makefile.mk @@ -2,6 +2,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +endif + bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/adl/acpi/mainboard.asl b/src/mainboard/system76/adl/acpi/mainboard.asl index c982a9ee4cb..f7453fc339e 100644 --- a/src/mainboard/system76/adl/acpi/mainboard.asl +++ b/src/mainboard/system76/adl/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(DRIVERS_GFX_NVIDIA) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,11 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + +#if CONFIG(DRIVERS_GFX_NVIDIA) + Scope (PEG2) { + #include + } +#endif } } diff --git a/src/mainboard/system76/adl/board.fmd b/src/mainboard/system76/adl/board.fmd index f50c357d918..4dab3c448f8 100644 --- a/src/mainboard/system76/adl/board.fmd +++ b/src/mainboard/system76/adl/board.fmd @@ -6,7 +6,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/adl/cmos-csme.default b/src/mainboard/system76/adl/cmos-csme.default new file mode 100644 index 00000000000..d61046df6b0 --- /dev/null +++ b/src/mainboard/system76/adl/cmos-csme.default @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 4e2731859fb..1ab4f4a0469 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -14,13 +14,12 @@ chip soc/intel/alderlake register "eist_enable" = "true" # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # Thermal register "tcc_offset" = "8" device domain 0 on - device ref system_agent on end device ref igpu on # DDIA is eDP, DDIB is HDMI register "ddi_portA_config" = "1" @@ -65,7 +64,6 @@ chip soc/intel/alderlake register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 @@ -88,6 +86,5 @@ chip soc/intel/alderlake register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" end device ref smbus on end - device ref fast_spi on end end end diff --git a/src/mainboard/system76/adl/variants/darp8/hda_verb.c b/src/mainboard/system76/adl/variants/darp8/hda_verb.c index cbfee1ff5d0..f8ef3f2cb3c 100644 --- a/src/mainboard/system76/adl/variants/darp8/hda_verb.c +++ b/src/mainboard/system76/adl/variants/darp8/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, - 0x15587716, - 12, +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15587716), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15587716, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 3af580229b8..d9c1a713ccc 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, diff --git a/src/mainboard/system76/adl/variants/galp6/gpio.c b/src/mainboard/system76/adl/variants/galp6/gpio.c index b73f06b7908..b0a0bfb6d21 100644 --- a/src/mainboard/system76/adl/variants/galp6/gpio.c +++ b/src/mainboard/system76/adl/variants/galp6/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A16, NONE), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_A20, NONE), PAD_NC(GPP_A21, NONE), PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN diff --git a/src/mainboard/system76/adl/variants/galp6/gpio_early.c b/src/mainboard/system76/adl/variants/galp6/gpio_early.c index 66577bd2458..9be063a62b3 100644 --- a/src/mainboard/system76/adl/variants/galp6/gpio_early.c +++ b/src/mainboard/system76/adl/variants/galp6/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART2_RXD (actually UART0) PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART2_TXD (actually UART0) + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/adl/variants/galp6/hda_verb.c b/src/mainboard/system76/adl/variants/galp6/hda_verb.c index 8679812a0c1..84653f2243a 100644 --- a/src/mainboard/system76/adl/variants/galp6/hda_verb.c +++ b/src/mainboard/system76/adl/variants/galp6/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x15584041, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15584041), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15584041, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c index a30eec1cef5..ab5947c7672 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE# PAD_NC(GPP_A21, NONE), PAD_NC(GPP_A22, NONE), diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c index 85b9307d456..e0a49fd5a00 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c index 80421433144..e3ccd6ea9a1 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x1558866d, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x1558866d), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -27,4 +23,16 @@ const u32 pc_beep_verbs[] = { 0x02040202, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x1558866d, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h b/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h new file mode 100644 index 00000000000..923a91536c6 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_A19 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x866d1558 + +#endif diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 511e0535b77..876576f7c9d 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -40,6 +40,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref pcie4_0 on # PCIe PEG0 x4, Clock 0 (SSD2) diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c index 5e6cf7dd52a..c91bb2af2fd 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c index ad895761b0d..2aba23c5b9a 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A16, NONE), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE# PAD_NC(GPP_A21, NONE), PAD_NC(GPP_A22, NONE), diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c index c2009a8e561..4abf95026f0 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c @@ -5,6 +5,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c index 4a17c369f68..6959fc88c9f 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x1558867c, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x1558867c), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x1558867c, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h b/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h new file mode 100644 index 00000000000..ebb118e8bfe --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_A19 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x867c1558 + +#endif diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index de679352932..a81796db0fd 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -40,6 +40,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on # DDIA is eDP diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c index 5e6cf7dd52a..c91bb2af2fd 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/lemp11/hda_verb.c b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c index 699031759e6..694670cb168 100644 --- a/src/mainboard/system76/adl/variants/lemp11/hda_verb.c +++ b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, - 0x15587718, - 12, +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15587718), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15587718, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio.c b/src/mainboard/system76/adl/variants/oryp10/gpio.c index 5c56f80e162..ef1883a57ef 100644 --- a/src/mainboard/system76/adl/variants/oryp10/gpio.c +++ b/src/mainboard/system76/adl/variants/oryp10/gpio.c @@ -109,7 +109,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D9, NONE), PAD_NC(GPP_D10, NONE), PAD_NC(GPP_D11, NONE), - PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 PAD_NC(GPP_D15, NONE), diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio_early.c b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c index 382fe0fd295..5fda88c367d 100644 --- a/src/mainboard/system76/adl/variants/oryp10/gpio_early.c +++ b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU + PAD_CFG_GPI(GPP_D12, NONE, DEEP), // DGPU_PWRGD_R }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c index 60f0266a230..2897762fc44 100644 --- a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c +++ b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155867f5, /* Subsystem ID */ - 152, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155867f5), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -165,6 +161,18 @@ const u32 cim_verb_data[] = { 0x0205002b, 0x02043000, 0x0205002c, 0x0204b424, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155867f5, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h new file mode 100644 index 00000000000..1650b725da7 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_D12 +#define DGPU_GC6 GPP_A7 +#define DGPU_SSID 0x65f51558 + +#endif diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index b213892232b..94b10599608 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -25,6 +25,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on register "ddi_portA_config" = "1" diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c index 86ecf32826c..5b0999acf3f 100644 --- a/src/mainboard/system76/adl/variants/oryp10/romstage.c +++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -20,6 +22,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/oryp9/gpio.c b/src/mainboard/system76/adl/variants/oryp9/gpio.c index 5c56f80e162..ef1883a57ef 100644 --- a/src/mainboard/system76/adl/variants/oryp9/gpio.c +++ b/src/mainboard/system76/adl/variants/oryp9/gpio.c @@ -109,7 +109,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D9, NONE), PAD_NC(GPP_D10, NONE), PAD_NC(GPP_D11, NONE), - PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 PAD_NC(GPP_D15, NONE), diff --git a/src/mainboard/system76/adl/variants/oryp9/gpio_early.c b/src/mainboard/system76/adl/variants/oryp9/gpio_early.c index 382fe0fd295..28d5cbf559d 100644 --- a/src/mainboard/system76/adl/variants/oryp9/gpio_early.c +++ b/src/mainboard/system76/adl/variants/oryp9/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU + PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/adl/variants/oryp9/hda_verb.c b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c index d591275bbff..1b086bebb00 100644 --- a/src/mainboard/system76/adl/variants/oryp9/hda_verb.c +++ b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155867f5, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155867f5), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155867f5, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h new file mode 100644 index 00000000000..1650b725da7 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_D12 +#define DGPU_GC6 GPP_A7 +#define DGPU_SSID 0x65f51558 + +#endif diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index e41c0a278a4..3cbf1b984f3 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -25,6 +25,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on register "ddi_portA_config" = "1" diff --git a/src/mainboard/system76/adl/variants/oryp9/romstage.c b/src/mainboard/system76/adl/variants/oryp9/romstage.c index 5e6cf7dd52a..c91bb2af2fd 100644 --- a/src/mainboard/system76/adl/variants/oryp9/romstage.c +++ b/src/mainboard/system76/adl/variants/oryp9/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig index 7c7e42e10be..23934153cd6 100644 --- a/src/mainboard/system76/bonw14/Kconfig +++ b/src/mainboard/system76/bonw14/Kconfig @@ -4,11 +4,12 @@ if BOARD_SYSTEM76_BONW14 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID + select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME diff --git a/src/mainboard/system76/bonw14/Makefile.mk b/src/mainboard/system76/bonw14/Makefile.mk index 2efcac5f428..89b8816938e 100644 --- a/src/mainboard/system76/bonw14/Makefile.mk +++ b/src/mainboard/system76/bonw14/Makefile.mk @@ -10,3 +10,4 @@ romstage-y += romstage.c ramstage-y += ramstage.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += tas5825m.c diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 4064c00b556..9f39eece76d 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O @@ -58,11 +58,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) register "PcieClkSrcUsage[7]" = "0x40" register "PcieClkSrcClkReq[7]" = "7" - - device pci 00.0 on end # VGA controller - device pci 00.1 on end # Audio device - device pci 00.2 on end # USB xHCI Host controller - device pci 00.3 on end # USB Type-C UCSI controller + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device ref dptf on end device ref thermal on end @@ -175,6 +176,15 @@ chip soc/intel/cannonlake device ref hda on register "PchHdaAudioLinkHda" = "1" end - device ref smbus on end + device ref smbus on + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + chip drivers/i2c/tas5825m + register "id" = "1" + device i2c 4f on end # (8bit address: 0x9e) + end + end end end diff --git a/src/mainboard/system76/bonw14/hda_verb.c b/src/mainboard/system76/bonw14/hda_verb.c index 5b6c4f4c5c0..0ff761a2158 100644 --- a/src/mainboard/system76/bonw14/hda_verb.c +++ b/src/mainboard/system76/bonw14/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x15587714, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x15587714), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x15587714, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/bonw14/tas5825m-normal.c b/src/mainboard/system76/bonw14/tas5825m-normal.c new file mode 100644 index 00000000000..81695effd80 --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m-normal.c @@ -0,0 +1,1240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +static int tas5825m_setup_normal(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x0C, 0xCC, 0xCD, + 0x00, 0x0C, 0xCC, 0xCD, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xA9, 0x15, 0xB8, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x01, 0x33, 0x51, 0x50, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, + 0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, + 0xF8, 0x5C, 0x9F, 0x28, 0x07, 0xD1, 0x27, 0x3E, + 0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27, 0x3E, + 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F, 0x28, + 0x08, 0x00, 0x00, 0x00, 0xF0, 0x71, 0x4C, 0x87, + 0x07, 0x91, 0xC6, 0x22, 0x0F, 0x8E, 0xB3, 0x79, + 0xF8, 0x6E, 0x39, 0xDE, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B, + 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5, + 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57, + 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51, 0x2E, + 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0, 0x7B, + 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92, 0xE5, + 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D, 0x1B, + 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F, 0x71, 0xB3, + 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0, 0x4E, 0xFB, + 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0, 0x3F, 0x52, + 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7, + 0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29, + 0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29, 0xCB, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFC, 0xDB, 0x0F, 0xF0, 0x3A, 0xC4, 0xBE, + 0x07, 0xC9, 0x51, 0x50, 0x0F, 0xC5, 0x3B, 0x42, + 0xF8, 0x39, 0xD3, 0xA1, 0x07, 0xFC, 0x38, 0xBF, + 0xF0, 0x47, 0x14, 0xF2, 0x07, 0xBE, 0x4A, 0x80, + 0x0F, 0xB8, 0xEB, 0x0E, 0xF8, 0x45, 0x7C, 0xC1, + 0x07, 0xEB, 0xF6, 0xEF, 0xF1, 0x08, 0x7E, 0x56, + 0x07, 0x17, 0x63, 0xC3, 0x0E, 0xF7, 0x81, 0xAA, + 0xF8, 0xFC, 0xA5, 0x4E, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xD1, 0x27, 0x3E, + 0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27, 0x3E, + 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F, 0x28, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, + 0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, + 0xF8, 0x5C, 0x9F, 0x28, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0x71, 0x4C, 0x87, 0x07, 0x91, 0xC6, 0x22, + 0x0F, 0x8E, 0xB3, 0x79, 0xF8, 0x6E, 0x39, 0xDE, + 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B, + 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5, + 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57, + 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51, 0x2E, + 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0, 0x7B, + 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92, 0xE5, + 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D, 0x1B, + 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F, 0x71, 0xB3, + 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0, 0x4E, 0xFB, + 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0, 0x3F, 0x52, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7, + 0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29, + 0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29, 0xCB, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x07, 0xFB, 0x25, 0x84, 0xF0, 0x49, 0xA3, 0xCE, + 0x07, 0xC7, 0xA6, 0xCB, 0x0F, 0xB6, 0x5C, 0x32, + 0xF8, 0x3D, 0x33, 0xB1, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x86, 0x43, 0x99, 0xFF, 0x02, 0xE6, 0x50, + 0x00, 0x77, 0xAC, 0xFD, 0x0F, 0xD7, 0xE6, 0xBF, + 0xF8, 0x27, 0x42, 0x5B + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x64, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4E, 0xBB); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4F, 0xB0); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/system76/bonw14/tas5825m-sub.c b/src/mainboard/system76/bonw14/tas5825m-sub.c new file mode 100644 index 00000000000..28987d9be20 --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m-sub.c @@ -0,0 +1,1240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +static int tas5825m_setup_sub(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x04); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x5A, 0x84, + 0x00, 0x1E, 0x5A, 0x84, 0x00, 0x40, 0x26, 0xE7, + 0x00, 0x40, 0x26, 0xE7, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xEB, 0x8F, 0xA8, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x01, 0xEB, 0x55, 0xAC, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x01, 0x0A, 0x7A, 0x00, 0x02, 0x14, 0xF5, + 0x00, 0x01, 0x0A, 0x7A, 0x0F, 0x7B, 0xDB, 0x58, + 0xF8, 0x7F, 0xFA, 0xBE, 0x00, 0x01, 0x0A, 0x7A, + 0x00, 0x02, 0x14, 0xF5, 0x00, 0x01, 0x0A, 0x7A, + 0x0F, 0x7B, 0xDB, 0x58, 0xF8, 0x7F, 0xFA, 0xBE, + 0x07, 0xFD, 0xF9, 0x62, 0xF0, 0x25, 0x7A, 0x1B, + 0x07, 0xDC, 0xC4, 0xC6, 0x0F, 0xDA, 0x85, 0xE5, + 0xF8, 0x25, 0x41, 0xD8, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF7, 0xFF, 0xB5, 0xF0, 0x4F, 0x8C, 0x33, + 0x07, 0xBA, 0x32, 0x37, 0x0F, 0xB0, 0x73, 0xCD, + 0xF8, 0x4D, 0xCE, 0x15, 0x07, 0xFA, 0x6B, 0x45, + 0xF0, 0x68, 0xC7, 0x1B, 0x07, 0x9E, 0xF0, 0xFB, + 0x0F, 0x97, 0x38, 0xE5, 0xF8, 0x66, 0xA3, 0xC0, + 0x07, 0xFE, 0x8C, 0x9C, 0xF0, 0x34, 0xCF, 0xDE, + 0x07, 0xCD, 0x94, 0xFF, 0x0F, 0xCB, 0x30, 0x22, + 0xF8, 0x33, 0xDE, 0x65, 0x07, 0xFE, 0x73, 0xDB, + 0xF0, 0x38, 0x93, 0x60, 0x07, 0xCA, 0x38, 0xAE, + 0x0F, 0xC7, 0x6C, 0xA0, 0xF8, 0x37, 0x53, 0x77, + 0x07, 0xF8, 0xC1, 0xBE, 0xF0, 0x88, 0xCB, 0x7D, + 0x07, 0x82, 0x08, 0xA9, 0x0F, 0x77, 0x34, 0x83, + 0xF8, 0x85, 0x35, 0x99, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4, + 0xF0, 0x22, 0x72, 0x97, 0x07, 0xEE, 0xC6, 0xB4, + 0x0F, 0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C, 0xCB, + 0x07, 0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67, 0xAD, + 0x07, 0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98, 0x53, + 0xF8, 0x33, 0xBE, 0x30, 0x08, 0x13, 0x15, 0xCB, + 0xF0, 0x0E, 0xB9, 0x1C, 0x07, 0xDE, 0xDC, 0x2A, + 0x0F, 0xF1, 0x86, 0x85, 0xF8, 0x0E, 0x4D, 0xAB, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xEE, 0xC6, 0xB4, 0xF0, 0x22, 0x72, 0x97, + 0x07, 0xEE, 0xC6, 0xB4, 0x0F, 0xDD, 0x77, 0x9C, + 0xF8, 0x22, 0x5C, 0xCB, 0x07, 0xF4, 0x93, 0x76, + 0xF0, 0x34, 0x67, 0xAD, 0x07, 0xD7, 0xAE, 0x5A, + 0x0F, 0xCB, 0x98, 0x53, 0xF8, 0x33, 0xBE, 0x30, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x13, 0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C, + 0x07, 0xDE, 0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85, + 0xF8, 0x0E, 0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x85, 0xC0, 0x8D, 0xFF, 0x02, 0x2B, 0x75, + 0x00, 0x78, 0xBE, 0x6E, 0x0F, 0xE2, 0x46, 0xF6, + 0xF8, 0x1D, 0x0E, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xAA, 0xC3, + 0xFF, 0xFD, 0x55, 0x85, 0xFF, 0xFE, 0xAA, 0xC3, + 0x0F, 0x2F, 0x01, 0x62, 0xF8, 0xCB, 0xA9, 0xA8, + 0x07, 0x98, 0xD5, 0xEF, 0xF0, 0xCE, 0x54, 0x23, + 0x07, 0x98, 0xD5, 0xEF, 0x0F, 0x2F, 0x01, 0x62, + 0xF8, 0xCB, 0xA9, 0xA8, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x64, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4E, 0xBB); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4F, 0xB0); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/system76/bonw14/tas5825m.c b/src/mainboard/system76/bonw14/tas5825m.c new file mode 100644 index 00000000000..95680fae92d --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "tas5825m-normal.c" +#include "tas5825m-sub.c" + +int tas5825m_setup(struct device *dev, int id) +{ + if (id == 0) + return tas5825m_setup_normal(dev); + if (id == 1) + return tas5825m_setup_sub(dev); + return -1; +} diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig index ee435de5fab..4bb47296756 100644 --- a/src/mainboard/system76/cml-u/Kconfig +++ b/src/mainboard/system76/cml-u/Kconfig @@ -4,7 +4,6 @@ if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_LEMP9 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID diff --git a/src/mainboard/system76/cml-u/Makefile.mk b/src/mainboard/system76/cml-u/Makefile.mk index 921112cee91..20b245cbbf6 100644 --- a/src/mainboard/system76/cml-u/Makefile.mk +++ b/src/mainboard/system76/cml-u/Makefile.mk @@ -3,7 +3,7 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 14de0548ea5..b7bd9521c17 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -22,7 +22,7 @@ chip soc/intel/cannonlake # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/cml-u/gpio_early.c b/src/mainboard/system76/cml-u/variants/darp6/gpio_early.c similarity index 100% rename from src/mainboard/system76/cml-u/gpio_early.c rename to src/mainboard/system76/cml-u/variants/darp6/gpio_early.c diff --git a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c index 59dc7b84652..8ca2a7cda1e 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15581404, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581404), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -20,17 +16,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1e, 0x02451130), +}; - /* Intel GPU HDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +static const u32 intel_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15581404, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/kbl-u/gpio_early.c b/src/mainboard/system76/cml-u/variants/galp4/gpio_early.c similarity index 100% rename from src/mainboard/system76/kbl-u/gpio_early.c rename to src/mainboard/system76/cml-u/variants/galp4/gpio_early.c diff --git a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c index b96f726f761..95786e0b47e 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15581403, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581403), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -22,6 +18,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15581403, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/whl-u/gpio_early.c b/src/mainboard/system76/cml-u/variants/lemp9/gpio_early.c similarity index 100% rename from src/mainboard/system76/whl-u/gpio_early.c rename to src/mainboard/system76/cml-u/variants/lemp9/gpio_early.c diff --git a/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c index 5a520ed459a..1ca427d0bae 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15581401, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581401), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -20,17 +16,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +}; - /* Intel GPU HDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +static const u32 intel_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15581401, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index ea0ef2ded75..07df66fb63e 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -4,10 +4,10 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU diff --git a/src/mainboard/system76/gaze15/Makefile.mk b/src/mainboard/system76/gaze15/Makefile.mk index 72f13667d31..ab7df6c275e 100644 --- a/src/mainboard/system76/gaze15/Makefile.mk +++ b/src/mainboard/system76/gaze15/Makefile.mk @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl index b235437c25d..610cdd12bad 100644 --- a/src/mainboard/system76/gaze15/acpi/mainboard.asl +++ b/src/mainboard/system76/gaze15/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include @@ -8,6 +10,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index be36abf73f0..492f05afa3d 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc @@ -54,6 +54,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/include/variant/gpio.h deleted file mode 100644 index 95d576294f6..00000000000 --- a/src/mainboard/system76/gaze15/include/variant/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -void variant_configure_early_gpios(void); -void variant_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/gaze15/romstage.c b/src/mainboard/system76/gaze15/romstage.c index 02634ba2ad2..f7e959134e8 100644 --- a/src/mainboard/system76/gaze15/romstage.c +++ b/src/mainboard/system76/gaze15/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include static const struct cnl_mb_cfg memcfg = { .spd[0] = { @@ -20,5 +22,18 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/system76/gaze15/variants/gaze14/gpio.c b/src/mainboard/system76/gaze15/variants/gaze14/gpio.c index 23d3a2ddeff..ea8e4bc3417 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/gpio.c +++ b/src/mainboard/system76/gaze15/variants/gaze14/gpio.c @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_K19, NONE, DEEP), // XXX: SMI# PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH - PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_K23, NONE), // DGPU_PRSNT# }; diff --git a/src/mainboard/system76/gaze15/variants/gaze14/gpio_early.c b/src/mainboard/system76/gaze15/variants/gaze14/gpio_early.c index 38b1bc43740..a2c24627340 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/gpio_early.c +++ b/src/mainboard/system76/gaze15/variants/gaze14/gpio_early.c @@ -6,9 +6,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c index fe08d03dd52..6ef93dd51a3 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC269VC */ - 0x10ec0269, /* Vendor ID */ - 0x15588560, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc269vc_verbs[] = { AZALIA_SUBVENDOR(0, 0x15588560), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC269", + .vendor_id = 0x10ec0269, + .subsystem_id = 0x15588560, + .address = 0, + .verbs = realtek_alc269vc_verbs, + .verb_count = ARRAY_SIZE(realtek_alc269vc_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h new file mode 100644 index 00000000000..3c560710bbd --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_PWRGD GPP_K22 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x85501558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/gaze15/variants/gaze15/gpio.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c index b7ae347d372..df7a462c834 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/gpio.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c @@ -267,7 +267,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR PAD_CFG_GPO(GPP_K20, 1, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH - PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT# }; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c index 38b1bc43740..a2c24627340 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c @@ -6,9 +6,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c index d6c3f28a8f2..54bc03cfbaa 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15588520, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15588520), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -22,6 +18,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15588520, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h new file mode 100644 index 00000000000..9690a886c0d --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_PWRGD GPP_K22 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x85201558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig index 0157d5c1aed..af72f678702 100644 --- a/src/mainboard/system76/kbl-u/Kconfig +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -1,10 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_SYSTEM76_GALP2 || BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE +config BOARD_SYSTEM76_KBL_U_COMMON + def_bool n select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID @@ -24,6 +21,17 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_MEASURED_BOOT +config BOARD_SYSTEM76_GALP2 + select BOARD_SYSTEM76_KBL_U_COMMON + +config BOARD_SYSTEM76_GALP3 + select BOARD_SYSTEM76_KBL_U_COMMON + +config BOARD_SYSTEM76_GALP3_B + select BOARD_SYSTEM76_KBL_U_COMMON + +if BOARD_SYSTEM76_KBL_U_COMMON + config DISABLE_HECI1_AT_PRE_BOOT default y diff --git a/src/mainboard/system76/kbl-u/Makefile.mk b/src/mainboard/system76/kbl-u/Makefile.mk index bf3828de968..4decebf6adf 100644 --- a/src/mainboard/system76/kbl-u/Makefile.mk +++ b/src/mainboard/system76/kbl-u/Makefile.mk @@ -3,8 +3,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += ramstage.c -ramstage-y += gpio.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 30e1bb0cee1..4d7ec7eba6e 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -103,7 +103,6 @@ chip soc/intel/skylake }" device domain 0 on - device ref system_agent on end device ref igpu on end device ref sa_thermal on end device ref south_xhci on diff --git a/src/mainboard/system76/kbl-u/gpio.c b/src/mainboard/system76/kbl-u/variants/galp2/gpio.c similarity index 100% rename from src/mainboard/system76/kbl-u/gpio.c rename to src/mainboard/system76/kbl-u/variants/galp2/gpio.c diff --git a/src/mainboard/system76/kbl-u/variants/galp2/gpio_early.c b/src/mainboard/system76/kbl-u/variants/galp2/gpio_early.c new file mode 100644 index 00000000000..80f37c65535 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp2/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c index f2ff8bd336c..24a57e2b5e7 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC269VC */ - 0x10ec0269, /* Vendor ID */ - 0x15581303, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc269vc_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581303), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -19,16 +15,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - /* Intel, KabylakeHDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +}; + +static const u32 intel_kabylake_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC269", + .vendor_id = 0x10ec0269, + .subsystem_id = 0x15581303, + .address = 0, + .verbs = realtek_alc269vc_verbs, + .verb_count = ARRAY_SIZE(realtek_alc269vc_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_kabylake_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_kabylake_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/gpio.c b/src/mainboard/system76/kbl-u/variants/galp3-b/gpio.c new file mode 100644 index 00000000000..5c5662e1fcc --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), // PM_BATLOW# + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), // AC_PRESENT + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // PCH_SLP_WLAN# + PAD_NC(GPD10, NONE), // SLP_S5# + PAD_NC(GPD11, NONE), // PCH_GPD11 + + /* ------- GPIO Group A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_NC(GPP_A7, NONE), // G_INT1 + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // PCLK_TPM + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), // LAN_WAKEUP# + PAD_NC(GPP_A12, NONE), // PCH_GPP_A12 + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUSACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // TBTA_ACE_GPIO3 + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN + PAD_CFG_GPO(GPP_A20, 0, DEEP), // TBTA_ACE_GPIO0 + PAD_CFG_GPO(GPP_A21, 1, PLTRST), // TBT_FRC_PWR + PAD_CFG_GPO(GPP_A22, 0, PWROK), // PS8338B_SW + PAD_CFG_GPO(GPP_A23, 0, PWROK), // PS8338B_PCH + + /* ------- GPIO Group B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1 + PAD_NC(GPP_B2, NONE), // VRALERT# + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), // PCIECLKRQ0# + PAD_NC(GPP_B6, NONE), // PCIECLKRQ1# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), // PCH_GPP_B15 + PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 + PAD_NC(GPP_B17, NONE), // PCH_GPP_B17 + PAD_NC(GPP_B18, NONE), // GSPI0_BBS0 - No Reboot strap + PAD_NC(GPP_B19, NONE), // PCH_GPP_B19 + PAD_NC(GPP_B20, NONE), // PCH_GPP_B20 + PAD_NC(GPP_B21, NONE), // PCH_GPP_B21 + PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - Boot BIOS strap + PAD_NC(GPP_B23, NONE), // PCH_GPP_B23 + + /* ------- GPIO Group C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 + PAD_NC(GPP_C3, NONE), // SML0CLK + PAD_NC(GPP_C4, NONE), // SML0DATA + PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 + PAD_NC(GPP_C6, NONE), // SML1CLK + PAD_NC(GPP_C7, NONE), // SML1DATA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), // TBTA_ACE_GPIO2 + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT + PAD_NC(GPP_C14, NONE), // TBTA_MRESET + PAD_NC(GPP_C15, NONE), // TBTA_ACE_GPIO7 + PAD_NC(GPP_C16, NONE), // T_SDA + PAD_NC(GPP_C17, NONE), // T_SCL + PAD_NC(GPP_C18, NONE), + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000), // SWI# + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), // UEART2_RTS_N + PAD_NC(GPP_C23, NONE), // UART2_CTS_N + + /* ------- GPIO Group D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), // PCH_GPP_D4 + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON + PAD_NC(GPP_D9, NONE), // T_INT + PAD_NC(GPP_D10, NONE), // EDP_DET + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET# + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group E ------- */ + PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 + PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), // SATAGP2 + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), // DEVSLP0 + PAD_NC(GPP_E5, NONE), // DEVSLP1 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2 + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATA_LED# + PAD_NC(GPP_E9, NONE), // USB_OC#12 + PAD_NC(GPP_E10, NONE), // USB_OC#34 + PAD_NC(GPP_E11, NONE), // USB_OC#56 + PAD_NC(GPP_E12, NONE), // USB_OC#78 + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI# + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), // MDP_CTRLDATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), // LIGHT_KB_DET# + + /* ------- GPIO Group G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // TBT Detect + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0 + PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1 + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/gpio_early.c b/src/mainboard/system76/kbl-u/variants/galp3-b/gpio_early.c new file mode 100644 index 00000000000..80f37c65535 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c index affce10c387..b32f2d74269 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC269VC */ - 0x10ec0269, /* Vendor ID */ - 0x15581414, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc269vc_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581414), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -19,16 +15,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - /* Intel, KabylakeHDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +}; + +static const u32 intel_kabylake_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC269", + .vendor_id = 0x10ec0269, + .subsystem_id = 0x15581414, + .address = 0, + .verbs = realtek_alc269vc_verbs, + .verb_count = ARRAY_SIZE(realtek_alc269vc_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_kabylake_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_kabylake_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/kbl-u/variants/galp3/gpio.c b/src/mainboard/system76/kbl-u/variants/galp3/gpio.c new file mode 100644 index 00000000000..5c5662e1fcc --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), // PM_BATLOW# + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), // AC_PRESENT + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // PCH_SLP_WLAN# + PAD_NC(GPD10, NONE), // SLP_S5# + PAD_NC(GPD11, NONE), // PCH_GPD11 + + /* ------- GPIO Group A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_NC(GPP_A7, NONE), // G_INT1 + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // PCLK_TPM + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), // LAN_WAKEUP# + PAD_NC(GPP_A12, NONE), // PCH_GPP_A12 + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUSACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // TBTA_ACE_GPIO3 + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN + PAD_CFG_GPO(GPP_A20, 0, DEEP), // TBTA_ACE_GPIO0 + PAD_CFG_GPO(GPP_A21, 1, PLTRST), // TBT_FRC_PWR + PAD_CFG_GPO(GPP_A22, 0, PWROK), // PS8338B_SW + PAD_CFG_GPO(GPP_A23, 0, PWROK), // PS8338B_PCH + + /* ------- GPIO Group B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1 + PAD_NC(GPP_B2, NONE), // VRALERT# + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), // PCIECLKRQ0# + PAD_NC(GPP_B6, NONE), // PCIECLKRQ1# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), // PCH_GPP_B15 + PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 + PAD_NC(GPP_B17, NONE), // PCH_GPP_B17 + PAD_NC(GPP_B18, NONE), // GSPI0_BBS0 - No Reboot strap + PAD_NC(GPP_B19, NONE), // PCH_GPP_B19 + PAD_NC(GPP_B20, NONE), // PCH_GPP_B20 + PAD_NC(GPP_B21, NONE), // PCH_GPP_B21 + PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - Boot BIOS strap + PAD_NC(GPP_B23, NONE), // PCH_GPP_B23 + + /* ------- GPIO Group C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 + PAD_NC(GPP_C3, NONE), // SML0CLK + PAD_NC(GPP_C4, NONE), // SML0DATA + PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 + PAD_NC(GPP_C6, NONE), // SML1CLK + PAD_NC(GPP_C7, NONE), // SML1DATA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), // TBTA_ACE_GPIO2 + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT + PAD_NC(GPP_C14, NONE), // TBTA_MRESET + PAD_NC(GPP_C15, NONE), // TBTA_ACE_GPIO7 + PAD_NC(GPP_C16, NONE), // T_SDA + PAD_NC(GPP_C17, NONE), // T_SCL + PAD_NC(GPP_C18, NONE), + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000), // SWI# + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), // UEART2_RTS_N + PAD_NC(GPP_C23, NONE), // UART2_CTS_N + + /* ------- GPIO Group D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), // PCH_GPP_D4 + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON + PAD_NC(GPP_D9, NONE), // T_INT + PAD_NC(GPP_D10, NONE), // EDP_DET + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET# + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group E ------- */ + PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 + PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), // SATAGP2 + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), // DEVSLP0 + PAD_NC(GPP_E5, NONE), // DEVSLP1 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2 + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATA_LED# + PAD_NC(GPP_E9, NONE), // USB_OC#12 + PAD_NC(GPP_E10, NONE), // USB_OC#34 + PAD_NC(GPP_E11, NONE), // USB_OC#56 + PAD_NC(GPP_E12, NONE), // USB_OC#78 + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI# + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), // MDP_CTRLDATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), // LIGHT_KB_DET# + + /* ------- GPIO Group G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // TBT Detect + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0 + PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1 + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/variants/galp3/gpio_early.c b/src/mainboard/system76/kbl-u/variants/galp3/gpio_early.c new file mode 100644 index 00000000000..80f37c65535 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c index 66222e1a9cd..dfc087c4c43 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC269VC */ - 0x10ec0269, /* Vendor ID */ - 0x15581313, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc269vc_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581313), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -19,16 +15,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - /* Intel, KabylakeHDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +}; + +static const u32 intel_kabylake_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC269", + .vendor_id = 0x10ec0269, + .subsystem_id = 0x15581313, + .address = 0, + .verbs = realtek_alc269vc_verbs, + .verb_count = ARRAY_SIZE(realtek_alc269vc_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_kabylake_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_kabylake_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/meer9/Kconfig b/src/mainboard/system76/meer9/Kconfig new file mode 100644 index 00000000000..0ee14993cd9 --- /dev/null +++ b/src/mainboard/system76/meer9/Kconfig @@ -0,0 +1,84 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SYSTEM76_MEER9_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CRB_TPM + select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_INTEL_PTT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_SUPPORT_RESIZABLE_BARS + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_METEORLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_MINIPC + +config BOARD_SYSTEM76_MEER9 + select BOARD_SYSTEM76_MEER9_COMMON + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + +if BOARD_SYSTEM76_MEER9_COMMON + +config MAINBOARD_DIR + default "system76/meer9" + +config VARIANT_DIR + default "meer9" if BOARD_SYSTEM76_MEER9 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "meer9" if BOARD_SYSTEM76_MEER9 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Meerkat" if BOARD_SYSTEM76_MEER9 + +config MAINBOARD_VERSION + default "meer9" if BOARD_SYSTEM76_MEER9 + +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + +config CONSOLE_POST + default y + +config D3COLD_SUPPORT + default n + +config DIMM_SPD_SIZE + default 1024 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config ONBOARD_VGA_IS_PRIMARY + default y + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 36 + +config POST_DEVICE + default n + +config TPM_MEASURED_BOOT + default y + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/system76/meer9/Kconfig.name b/src/mainboard/system76/meer9/Kconfig.name new file mode 100644 index 00000000000..516503db022 --- /dev/null +++ b/src/mainboard/system76/meer9/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SYSTEM76_MEER9 + bool "meer9" diff --git a/src/mainboard/system76/meer9/Makefile.mk b/src/mainboard/system76/meer9/Makefile.mk new file mode 100644 index 00000000000..d687753afad --- /dev/null +++ b/src/mainboard/system76/meer9/Makefile.mk @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c diff --git a/src/mainboard/system76/meer9/acpi/mainboard.asl b/src/mainboard/system76/meer9/acpi/mainboard.asl new file mode 100644 index 00000000000..99e94438ac4 --- /dev/null +++ b/src/mainboard/system76/meer9/acpi/mainboard.asl @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sio.asl" + #include "sleep.asl" + #include "s76.asl" +} diff --git a/src/mainboard/system76/meer9/acpi/s76.asl b/src/mainboard/system76/meer9/acpi/s76.asl new file mode 100644 index 00000000000..12f4ed9f1f2 --- /dev/null +++ b/src/mainboard/system76/meer9/acpi/s76.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +// 0x85 - OLED screen toggle +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + OperationRegion (HMIO, SystemIO, 0x295, 0x02) + Field (HMIO, ByteAcc, NoLock, Preserve) { + // Hardware manager index + HMID, 8, + // Hardware manager data + HMDT, 8, + } + + Method (INIT, 0, Serialized) { + Printf ("S76D: INIT") + Return (0) + } + + Method (FINI, 0, Serialized) { + Printf ("S76D: FINI") + Return (0) + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) {} + + // Get Keyboard Backlight Kind + // 0 - No backlight + // 1 - White backlight + // 2 - RGB backlight + Method (GKBK, 0, Serialized) { + Return (0) + } + + // Get Keyboard Brightness + Method (GKBB, 0, Serialized) { + Return (0) + } + + // Set Keyboard Brightness + Method (SKBB, 1, Serialized) {} + + // Get Keyboard Color + Method (GKBC, 0, Serialized) { + Return (0) + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) {} + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan" + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + // Set bank 0 + HMID = 0x4E + HMDT = 0x80 + + // Read fan duty cycle + HMID = 0x4B + Local0 = HMDT + + // Read fan RPM (low) + HMID = 0x33 + Local1 = HMDT + + // Read fan RPM (high) + HMID = 0x32 + Local2 = HMDT + + Return ((Local2 << 16) | (Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp" + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + // Set bank 0 + HMID = 0x4E + HMDT = 0x80 + + // Read temperature + HMID = 0x19 + Local0 = HMDT + + Return (Local0) + } +} diff --git a/src/mainboard/system76/meer9/acpi/sio.asl b/src/mainboard/system76/meer9/acpi/sio.asl new file mode 100644 index 00000000000..4f91a837120 --- /dev/null +++ b/src/mainboard/system76/meer9/acpi/sio.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset(0xE5), + SRE5, 8, /* Register 0xE5 */ + } + + Method (ENTR, 0, Serialized) { + // Enter config mode + SI2E = 0x87 + SI2E = 0x87 + } + + Method (EXIT, 0, Serialized) { + // Exit config mode + SI2E = 0xAA + } + + Method (PTS, 0, Serialized) { + ENTR() + + // Turn on fading LED + SLDN = 0x15 + SRE5 = 0x43 + + EXIT() + } + + Method (WAK, 0, Serialized) { + ENTR() + + // Turn off fading LED + SLDN = 0x15 + SRE5 = 0x42 + + EXIT() + } +} diff --git a/src/mainboard/system76/meer9/acpi/sleep.asl b/src/mainboard/system76/meer9/acpi/sleep.asl new file mode 100644 index 00000000000..0212e7aeeb8 --- /dev/null +++ b/src/mainboard/system76/meer9/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.SIO.PTS() +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.SIO.WAK() +} diff --git a/src/mainboard/system76/meer9/board_info.txt b/src/mainboard/system76/meer9/board_info.txt new file mode 100644 index 00000000000..7d87752e22f --- /dev/null +++ b/src/mainboard/system76/meer9/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: System76 +Category: desktop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/system76/meer9/bootblock.c b/src/mainboard/system76/meer9/bootblock.c new file mode 100644 index 00000000000..86b980bddef --- /dev/null +++ b/src/mainboard/system76/meer9/bootblock.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +// nuvoton_pnp_enter_conf_state +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +// nuvoton_pnp_exit_conf_state +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void superio_init(void) +{ + //TODO: use superio driver? + pnp_devfn_t dev = PNP_DEV(0x2E, 0x00); + + printk(BIOS_DEBUG, "entering PNP config mode\n"); + pnp_enter_conf_state(dev); + + printk(BIOS_DEBUG, "configure global PNP\n"); + //TODO: document these + pnp_write_config(dev, 0x1A, 0x88); // Default is 0x03 + pnp_write_config(dev, 0x1B, 0x00); // Default is 0x03 + pnp_write_config(dev, 0x1D, 0x08); // Default is 0x00 + pnp_write_config(dev, 0x2C, 0x03); // Default is 0x0F + pnp_write_config(dev, 0x2F, 0xE4); // Default is 0x74 + + printk(BIOS_DEBUG, "configure GPIO (logical device 7)\n"); + dev = PNP_DEV(0x2E, 0x07); + pnp_set_logical_device(dev); + // Enable GPIO 0, 5, and 6 + pnp_write_config(dev, 0x30, 0x61); // Default is 0x00 + // Set GPIO 00-06 as output, 07 as input + pnp_write_config(dev, 0xE0, 0x80); // Default is 0xFF + // Set GPIO 00-02 and 04-05 high + pnp_write_config(dev, 0xE1, 0x37); // Default is 0x00 + // Set GPIO 53-54 as output, 50-52 and 55-57 as input + pnp_write_config(dev, 0xF8, 0xE7); // Default is 0xFF + // Set GPIO 53-53 high + pnp_write_config(dev, 0xF9, 0x18); // Default is 0x00 + + printk(BIOS_DEBUG, "configure GPIO (logical device 8)\n"); + dev = PNP_DEV(0x2E, 0x08); + pnp_set_logical_device(dev); + // Disable WDT1 + pnp_write_config(dev, 0x30, 0x00); // Default is 0x01 + // GPIO0 multi-function select, set GPIO0 as SUSLED + pnp_write_config(dev, 0xE0, 0x01); // Default is 0x00 + pnp_write_config(dev, 0xE9, 0x00); // Default is 0xFF TODO? + pnp_write_config(dev, 0xEA, 0x00); // Default is 0xFF TODO? + + printk(BIOS_DEBUG, "configure GPIO (logical device 9)\n"); + dev = PNP_DEV(0x2E, 0x09); + pnp_set_logical_device(dev); + // Enable GPIO 8 and 9 + pnp_write_config(dev, 0x30, 0x03); // Default is 0x00 + // GPIO 80-86 set as input, 87 as output + pnp_write_config(dev, 0xF0, 0x7F); // Default is 0xFF + // GPIO 87 set high + pnp_write_config(dev, 0xF1, 0x80); // Default is 0xFF + + printk(BIOS_DEBUG, "configure ACPI (logical device A)\n"); + dev = PNP_DEV(0x2E, 0x0A); + pnp_set_logical_device(dev); + // User-defined resume state after power loss + pnp_write_config(dev, 0xE4, 0x60); // Default is 0x00 + + printk(BIOS_DEBUG, "configure hardware monitor (logical device B)\n"); + dev = PNP_DEV(0x2E, 0x0B); + pnp_set_logical_device(dev); + // Enable hardware monitor + pnp_write_config(dev, 0x30, 0x01); // Default is 0x00 + // Set address base to 0x290 + pnp_write_config(dev, 0x60, 0x02); + pnp_write_config(dev, 0x61, 0x90); + + printk(BIOS_DEBUG, "configure GPIO (logical device F)\n"); + dev = PNP_DEV(0x2E, 0x0F); + pnp_set_logical_device(dev); + // Set GPIO 00, 01, and 07 as open drain, and 2-6 as push-pull + pnp_write_config(dev, 0xE0, 0x83); // Default is 0xFF + // Set GPIO 52-57 as open drain, and 50-51 as push-pull + pnp_write_config(dev, 0xE5, 0xFC); // Default is 0xFF + // Set GPIO 60-62 and 65-67 as open drain, and 63-64 as push-pull + pnp_write_config(dev, 0xE6, 0xE7); // Default is 0xFF + // Set GPIO 80-86 as open drain, and 87 as push-pull + pnp_write_config(dev, 0xE8, 0x7F); // Default is 0xFF + + printk(BIOS_DEBUG, "configure fading LED (logical device 15)\n"); + dev = PNP_DEV(0x2E, 0x15); + pnp_set_logical_device(dev); + // Configure fading LED (divide by 4, frequency 1 Khz, off) + pnp_write_config(dev, 0xE5, 0x42); + + printk(BIOS_DEBUG, "configure deep sleep (logical device 16)\n"); + dev = PNP_DEV(0x2E, 0x16); + pnp_set_logical_device(dev); + // Set deep sleep delay time to 0s + pnp_write_config(dev, 0xE2, 0x00); + + printk(BIOS_DEBUG, "exiting PNP config mode\n"); + pnp_exit_conf_state(dev); +} + +static void hm_write(uint8_t reg, uint8_t value) +{ + outb(reg, 0x295); + outb(value, 0x296); +} + +static void hm_init(void) +{ + // Bank 2 + hm_write(0x4E, 0x82); + + // Enable PECI 3.0 with routine function + hm_write(0x00, 0x85); + + // Enable PECI agent 30 + hm_write(0x02, 0x10); + + // PECI Tbase0 = 110C + hm_write(0x04, 110); + + // Bank 3 + hm_write(0x4E, 0x83); + + // Enable PECI agent 0 mode + hm_write(0x90, 0x01); + + // Bank 1 + hm_write(0x4E, 0x81); + + // CPUFAN T1 = 50C + hm_write(0x70, 50); + // CPUFAN FD1 = 25% = 0x3F + hm_write(0x74, 0x3F); + + // CPUFAN T2 = 75C + hm_write(0x71, 75); + // CPUFAN FD2 = 50% = 0x7F + hm_write(0x75, 0x7F); + + // CPUFAN T3 = 90C + hm_write(0x72, 90); + // CPUFAN FD3 = 75% = 0xBF + hm_write(0x76, 0xBF); + + // CPUFAN T4 = 99C + hm_write(0x73, 99); + // CPUFAN FD4 = 100% = 0xFF + hm_write(0x77, 0xFF); + + // CPUFAN critical temperature = 105C + hm_write(0x2A, 105); + // By default critical duty is 0xFF + + // CPUFAN step up time = 1s + hm_write(0x24, 10); + + // CPUFAN step down time = 0.5s + hm_write(0x25, 5); + + // Use PECI agent 0 as CPUFAN monitoring source + hm_write(0x20, 0x0C); + + // CPUFAN Smart Fan IV mode + hm_write(0x23, 0x40); +} + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); + superio_init(); + hm_init(); +} diff --git a/src/mainboard/system76/meer9/cmos.default b/src/mainboard/system76/meer9/cmos.default new file mode 100644 index 00000000000..d2ca53be53c --- /dev/null +++ b/src/mainboard/system76/meer9/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +me_state=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/system76/meer9/cmos.layout b/src/mainboard/system76/meer9/cmos.layout new file mode 100644 index 00000000000..7e710295c57 --- /dev/null +++ b/src/mainboard/system76/meer9/cmos.layout @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +409 2 e 7 power_on_after_fail +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +7 0 Disable +7 1 Enable +7 2 Keep + +checksums + +checksum 408 799 984 diff --git a/src/mainboard/system76/meer9/devicetree.cb b/src/mainboard/system76/meer9/devicetree.cb new file mode 100644 index 00000000000..fa73141e4ec --- /dev/null +++ b/src/mainboard/system76/meer9/devicetree.cb @@ -0,0 +1,51 @@ +chip soc/intel/meteorlake + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Thermal + register "tcc_offset" = "11" # 110C - 11C = 99C + + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 40, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + + device domain 0 on + device ref igpu on + # DDIA is HDMI1, DDIB is HDMI2 + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref vpu on end + device ref ioe_shared_sram on end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref soc_espi on + register "gen1_dec" = "0x007c0281" # Port 0x280 to 0x2FF (hardware monitor) + register "gen2_dec" = "0x000c0081" # Port 0x80 to 0x8F (debug) + end + device ref p2sb on end + device ref hda on + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/system76/meer9/dsdt.asl b/src/mainboard/system76/meer9/dsdt.asl new file mode 100644 index 00000000000..cf8d58d4345 --- /dev/null +++ b/src/mainboard/system76/meer9/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS +#include + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/meer9/include/mainboard/gpio.h b/src/mainboard/system76/meer9/include/mainboard/gpio.h new file mode 100644 index 00000000000..c6393beebb6 --- /dev/null +++ b/src/mainboard/system76/meer9/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/meer9/ramstage.c b/src/mainboard/system76/meer9/ramstage.c new file mode 100644 index 00000000000..c6fca5fcd4a --- /dev/null +++ b/src/mainboard/system76/meer9/ramstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); + + // The DACC feature resets CMOS and causes a system reset if the + // firmware does not send this message within 10 seconds of power on. + printk(BIOS_DEBUG, "Handling DACC\n"); + do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, 0xBA >> 1, 0x0F, 0xAA); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/meer9/variants/meer9/board.fmd b/src/mainboard/system76/meer9/variants/meer9/board.fmd new file mode 100644 index 00000000000..a5499a2daa0 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 10160K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 512K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/meer9/variants/meer9/board_info.txt b/src/mainboard/system76/meer9/variants/meer9/board_info.txt new file mode 100644 index 00000000000..dcb8a8bd1f8 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/board_info.txt @@ -0,0 +1,2 @@ +Board name: meer9 +Release year: 2024 diff --git a/src/mainboard/system76/meer9/variants/meer9/data.vbt b/src/mainboard/system76/meer9/variants/meer9/data.vbt new file mode 100644 index 00000000000..93276b46fac Binary files /dev/null and b/src/mainboard/system76/meer9/variants/meer9/data.vbt differ diff --git a/src/mainboard/system76/meer9/variants/meer9/gpio.c b/src/mainboard/system76/meer9/variants/meer9/gpio.c new file mode 100644 index 00000000000..c7fc1810b78 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS0# + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A07, NONE), + PAD_NC(GPP_A08, NONE), + PAD_NC(GPP_A09, NONE), + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPI(GPP_A11, NONE, PLTRST), + PAD_CFG_GPI(GPP_A12, NONE, PLTRST), + PAD_CFG_GPI(GPP_A13, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A14, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A15, NONE, PLTRST), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALERT0# + PAD_CFG_GPI(GPP_A17, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A18, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), + PAD_CFG_GPI(GPP_A20, NATIVE, DEEP), + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMCALERT# + + PAD_CFG_GPI(GPP_B00, NONE, PLTRST), + PAD_CFG_GPI(GPP_B01, NONE, PLTRST), + PAD_CFG_GPI(GPP_B02, NONE, PLTRST), + PAD_CFG_GPI(GPP_B03, NONE, PLTRST), + PAD_CFG_GPI(GPP_B04, NONE, PLTRST), + PAD_CFG_GPI(GPP_B05, NONE, PLTRST), + PAD_CFG_GPI(GPP_B06, NONE, PLTRST), + PAD_CFG_GPI(GPP_B07, NONE, PLTRST), + PAD_CFG_GPO(GPP_B08, 1, PLTRST), + PAD_CFG_GPI(GPP_B09, NONE, PLTRST), + PAD_CFG_GPI(GPP_B10, NONE, PLTRST), + PAD_CFG_GPI(GPP_B11, NONE, PLTRST), + PAD_CFG_GPI(GPP_B12, NONE, PLTRST), + PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), // PLTRST# + PAD_CFG_GPI(GPP_B14, NONE, PLTRST), + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF2), // HDMI_HPD2 + PAD_CFG_GPI(GPP_B17, NONE, PLTRST), + PAD_CFG_GPO(GPP_B18, 1, PLTRST), + PAD_CFG_GPO(GPP_B19, 1, PLTRST), + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), + PAD_CFG_GPI(GPP_B21, NONE, PLTRST), + PAD_CFG_GPI(GPP_B22, NONE, PLTRST), + PAD_CFG_GPI(GPP_B23, NONE, PLTRST), + + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C00, NONE, DEEP, NF1), // SMBCLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C01, NONE, DEEP, NF1), // SMBDATA + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C03, NONE, DEEP, NF1), // SML0CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C04, NONE, DEEP, NF1), // SML0DATA + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C05, UP_20K, DEEP, NF1), // SM0ALERT# + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1), // SML1CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1), // SML1DATA + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C08, NONE, DEEP, NF1), // SML1ALERT# + PAD_CFG_NF(GPP_C09, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // SRCCLKREQ1# + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), // SRCCLKREQ2# + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // SRCCLKREQ3# + PAD_CFG_GPI(GPP_C13, NONE, PLTRST), + PAD_NC(GPP_C14, NONE), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_GPI(GPP_C20, NONE, PLTRST), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_C23, NONE, PLTRST), + + PAD_CFG_GPO(GPP_D00, 0, PWROK), + PAD_CFG_GPI(GPP_D01, NONE, PLTRST), + PAD_CFG_GPI(GPP_D02, NONE, PLTRST), + PAD_CFG_GPI(GPP_D03, NONE, PLTRST), + PAD_CFG_GPO(GPP_D04, 1, PWROK), + PAD_CFG_GPO(GPP_D05, 1, PLTRST), + PAD_CFG_GPO(GPP_D06, 1, PLTRST), + PAD_CFG_GPO(GPP_D07, 1, PLTRST), + PAD_CFG_GPO(GPP_D08, 1, PLTRST), + PAD_CFG_GPO(GPP_D09, 0, PWROK), // ME_OVERRIDE + PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1), // HDA_BCLK + PAD_CFG_NF(GPP_D11, NATIVE, PLTRST, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NATIVE, PLTRST, NF1), // HDA_SDO + PAD_CFG_NF(GPP_D13, NATIVE, PLTRST, NF1), // HDA_SDI0 + PAD_CFG_GPI(GPP_D14, NONE, PLTRST), + PAD_CFG_GPI(GPP_D15, NONE, PLTRST), + PAD_CFG_GPI(GPP_D16, NONE, PLTRST), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), // HDA_RST# + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SRCCLKREQ6# + PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SRCCLKREQ8# + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_D22, NATIVE, PLTRST), + PAD_CFG_GPI(GPP_D23, NATIVE, PLTRST), + + PAD_CFG_GPI(GPP_E00, NONE, PLTRST), + PAD_CFG_GPI(GPP_E01, NONE, PLTRST), + PAD_CFG_GPI(GPP_E02, NONE, PLTRST), + PAD_CFG_GPI(GPP_E03, NONE, PLTRST), + PAD_CFG_GPO(GPP_E04, 0, PLTRST), + PAD_CFG_GPO(GPP_E05, 1, PLTRST), + PAD_CFG_GPI(GPP_E06, NONE, PLTRST), + PAD_CFG_GPI(GPP_E07, NONE, PLTRST), + PAD_CFG_NF(GPP_E08, NONE, PLTRST, NF1), // DDPA_CTRLDATA + PAD_CFG_GPI(GPP_E09, NONE, PLTRST), + PAD_CFG_GPI(GPP_E10, NONE, PLTRST), + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + PAD_CFG_GPI(GPP_E13, NONE, PLTRST), + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_E15, NONE, PLTRST), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_E16, NONE, PLTRST, NF2), // VRALERT# + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E22, DN_20K, PLTRST, NF1), // DDPA_CTRLCLK + + PAD_CFG_NF(GPP_F00, NONE, PLTRST, NF1), // CNV_BRI_DT + PAD_CFG_NF(GPP_F01, UP_20K, PLTRST, NF1), // CNV_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, PLTRST, NF1), // CNV_BRI_RSP + PAD_CFG_NF(GPP_F03, UP_20K, PLTRST, NF1), // CNV_RGI_DT + PAD_CFG_NF(GPP_F04, NONE, PLTRST, NF1), // CNV_RGI_RSP + PAD_CFG_NF(GPP_F05, NONE, PLTRST, NF3), // CNV_RF_RESET# + PAD_CFG_NF(GPP_F06, NONE, PLTRST, NF1), // MODEM_CLKREQ + PAD_CFG_TERM_GPO(GPP_F07, 1, DN_20K, PWROK), // CNV_PA_BLANKING + PAD_CFG_GPI(GPP_F08, DN_20K, PLTRST), + PAD_CFG_GPI(GPP_F09, NONE, PLTRST), + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI(GPP_F14, NONE, PLTRST), + PAD_CFG_GPI(GPP_F15, NONE, PLTRST), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), + PAD_CFG_GPI(GPP_F17, NONE, PLTRST), + PAD_CFG_GPI(GPP_F18, NONE, PLTRST), + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + PAD_CFG_GPI(GPP_F23, NONE, PLTRST), + + PAD_CFG_GPI(GPP_H00, NONE, PLTRST), + PAD_CFG_GPI(GPP_H01, NONE, PLTRST), + PAD_CFG_GPI(GPP_H02, NONE, PLTRST), + PAD_NC(GPP_H03, NONE), + PAD_CFG_NF(GPP_H04, NONE, PLTRST, NF2), // CNV_MFUART2_RXD + PAD_CFG_NF(GPP_H05, NONE, PLTRST, NF2), // CNV_MFUART2_TXD + PAD_CFG_GPI(GPP_H06, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_H07, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_H08, NONE, PLTRST), + PAD_CFG_GPI(GPP_H09, NONE, PLTRST), + PAD_CFG_GPI(GPP_H10, NONE, PLTRST), + PAD_CFG_GPI(GPP_H11, NONE, PLTRST), + PAD_NC(GPP_H12, NONE), + PAD_CFG_GPI(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI(GPP_H14, NONE, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1), // DDPB_CTRLCLK + PAD_CFG_NF(GPP_H17, NONE, PLTRST, NF1), // DDPB_CTRLDATA + PAD_NC(GPP_H18, NONE), + PAD_CFG_NF(GPP_H19, NONE, PLTRST, NF1), // CCG6DF_I2C_SDA (PD) + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), // CCG6DF_I2C_SCL (PD) + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + + PAD_CFG_GPI(GPP_S00, NONE, PLTRST), + PAD_CFG_GPI(GPP_S01, NONE, PLTRST), + PAD_CFG_GPI(GPP_S02, NONE, PLTRST), + PAD_CFG_GPI(GPP_S03, NONE, PLTRST), + PAD_CFG_GPI(GPP_S04, NONE, PLTRST), + PAD_CFG_GPI(GPP_S05, NONE, PLTRST), + PAD_CFG_GPI(GPP_S06, NONE, PLTRST), + PAD_CFG_GPI(GPP_S07, NONE, PLTRST), + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // BATLOW# + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // ACPRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // SOC_WAKE# + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWRBTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SLP_S3# + PAD_CFG_NF(GPP_V05, UP_20K, PLTRST, NF1), // SLP_S4# + PAD_CFG_NF(GPP_V06, NATIVE, PLTRST, NF1), + PAD_CFG_NF(GPP_V07, NATIVE, PLTRST, NF1), + PAD_CFG_NF(GPP_V08, UP_20K, PLTRST, NF1), // SUSCLK + PAD_CFG_NF(GPP_V09, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_V10, NONE, PLTRST, NF1), + PAD_CFG_GPI(GPP_V11, NONE, PLTRST), + PAD_NC(GPP_V12, NONE), + PAD_CFG_NF(GPP_V13, NONE, PLTRST, NF1), + PAD_CFG_GPI(GPP_V14, NONE, PLTRST), // WAKE# + PAD_CFG_GPI(GPP_V15, NONE, PLTRST), + PAD_CFG_GPI(GPP_V16, NONE, PLTRST), + PAD_CFG_GPI(GPP_V17, NONE, PLTRST), + PAD_NC(GPP_V18, NONE), + PAD_CFG_NF(GPP_V19, NONE, PLTRST, NF1), + PAD_NC(GPP_V20, NONE), + PAD_NC(GPP_V21, NONE), + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/meer9/variants/meer9/gpio_early.c b/src/mainboard/system76/meer9/variants/meer9/gpio_early.c new file mode 100644 index 00000000000..b3cd0c99242 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/meer9/variants/meer9/hda_verb.c b/src/mainboard/system76/meer9/variants/meer9/hda_verb.c new file mode 100644 index 00000000000..3bb685b25a0 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/hda_verb.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc256_verbs[] = { + AZALIA_SUBVENDOR(0, 0x18490256), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), // DMIC + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), // DMIC + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), // Front (Port-D) + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // NPC + AZALIA_PIN_CFG(0, 0x19, 0x02a11020), // MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), // LINE2 (Port-E) + AZALIA_PIN_CFG(0, 0x1d, 0x40400001), // BEEP-IN + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // S/PDIF-OUT + AZALIA_PIN_CFG(0, 0x21, 0x02211010), // HP1-OUT (Port-I) + + // Enable HP-JD + 0x0205001B, 0x02040A4B, 0x0205001B, 0x02040A4B, +}; + +const u32 pc_beep_verbs[] = { + // Dos beep path - 1 + 0x02170C00, 0x02050036, 0x02041151, 0x021707C0, + // Dos beep path - 2 + 0x0213B000, 0x02170C02, 0x02170C02, 0x02170C02, +}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x18490256, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/meer9/variants/meer9/overridetree.cb b/src/mainboard/system76/meer9/variants/meer9/overridetree.cb new file mode 100644 index 00000000000..b6285aee334 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/overridetree.cb @@ -0,0 +1,105 @@ +chip soc/intel/meteorlake + device domain 0 on + #TODO: all the devices have different subsystem product IDs + #subsystemid 0x1849 TODO inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # TBT + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3 Front + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB3 Rear */ + [1] = USB2_PORT_MID(OC_SKIP), /* USB3 Rear */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB2 Header */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB2 Header */ + [4] = USB2_PORT_TYPE_C(OC_SKIP), /* TBT */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */ + [6] = USB2_PORT_MID(OC_SKIP), /* USB3 Front */ + [7] = USB2_PORT_MID(OC_SKIP), /* USB3 Front */ + [8] = USB2_PORT_MID(OC_SKIP), /* M.2 Key M */ + [9] = USB2_PORT_MID(OC_SKIP), /* M.2 Key E */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3 Rear */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3 Rear */ + }" + end + device ref pcie_rp5 on + # GLAN1 + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + device ref pcie_rp6 on + # GLAN2 + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp7 on + # M.2 Key-E1 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + end + device ref pcie_rp10 on + # M.2 Key-M1 + # XXX: Schematics show RP[13:16] used + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on + # M.2 Key-M2 + # XXX: Schematics show RP[17:20] used + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[0]" = "1" # SATA 0 + register "sata_ports_dev_slp[0]" = "1" + end + device ref hda on + subsystemid 0x1849 0x0256 + end + end +end diff --git a/src/mainboard/system76/meer9/variants/meer9/ramstage.c b/src/mainboard/system76/meer9/variants/meer9/ramstage.c new file mode 100644 index 00000000000..c0c90dd45d3 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable TCP1 and TCP2 USB-A conversion + // BIT 0:3 is mapping to PCH XHCI USB2 port + // BIT 4:5 is reserved + // BIT 6 is orientational + // BIT 7 is enable + params->EnableTcssCovTypeA[1] = 0x86; + params->EnableTcssCovTypeA[2] = 0x87; + + // XXX: Enabling C10 reporting causes system to constantly enter and + // exit opportunistic suspend when idle. + params->PchEspiHostC10ReportEnable = 0; +} diff --git a/src/mainboard/system76/meer9/variants/meer9/romstage.c b/src/mainboard/system76/meer9/variants/meer9/romstage.c new file mode 100644 index 00000000000..b047f523ac5 --- /dev/null +++ b/src/mainboard/system76/meer9/variants/meer9/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig index 761c599fdae..2fdac37e027 100644 --- a/src/mainboard/system76/mtl/Kconfig +++ b/src/mainboard/system76/mtl/Kconfig @@ -2,13 +2,13 @@ config BOARD_SYSTEM76_MTL_COMMON def_bool n - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID select DRIVERS_I2C_HID select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -134,4 +134,12 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n +config CBFS_SIZE + hex + default 0x400000 + + config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x4000 + endif diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index 899788d4c60..bc1695b4752 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -16,10 +16,7 @@ chip soc/intel/meteorlake # Thermal register "tcc_offset" = "8" - device cpu_cluster 0 on end - device domain 0 on - device ref system_agent on end device ref igpu on # DDIA is eDP, TCP2 is HDMI register "ddi_port_A_config" = "1" @@ -46,7 +43,6 @@ chip soc/intel/meteorlake register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on end device ref soc_espi on register "gen1_dec" = "0x00040069" # EC PM channel register "gen2_dec" = "0x00fc0e01" # AP/EC command @@ -64,6 +60,5 @@ chip soc/intel/meteorlake register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" end device ref smbus on end - device ref fast_spi on end end end diff --git a/src/mainboard/system76/mtl/variants/darp10/board.fmd b/src/mainboard/system76/mtl/variants/darp10/board.fmd index 8539c86e1ee..c8f3fcea5e4 100644 --- a/src/mainboard/system76/mtl/variants/darp10/board.fmd +++ b/src/mainboard/system76/mtl/variants/darp10/board.fmd @@ -4,7 +4,7 @@ FLASH 32M { SI_ME 10640K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/mtl/variants/darp10/hda_verb.c b/src/mainboard/system76/mtl/variants/darp10/hda_verb.c index 2915f4d9ebf..d66ae314660 100644 --- a/src/mainboard/system76/mtl/variants/darp10/hda_verb.c +++ b/src/mainboard/system76/mtl/variants/darp10/hda_verb.c @@ -2,24 +2,20 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC245 */ - 0x10ec0245, /* Vendor ID */ - 0x1558a763, /* Subsystem ID */ - 40, /* Number of entries */ +static const u32 realtek_alc245_verbs[] = { //AZALIA_SUBVENDOR(0, 0x1558a763), AZALIA_SUBVENDOR(0, 0x1558a743), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x04211020), 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, @@ -54,6 +50,18 @@ const u32 cim_verb_data[] = { 0x01470c02, 0x01470c02, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC245", + .vendor_id = 0x10ec0245, + .subsystem_id = 0x1558a763, + .address = 0, + .verbs = realtek_alc245_verbs, + .verb_count = ARRAY_SIZE(realtek_alc245_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c index 0e3baf2ad69..63dfb351519 100644 --- a/src/mainboard/system76/mtl/variants/darp10/ramstage.c +++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c @@ -9,8 +9,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // BIT 4:5 is reserved // BIT 6 is orientational // BIT 7 is enable - // TODO: Add to coreboot FSP headers as no Client FSP release will be made. - //params->EnableTcssCovTypeA[1] = 0x82; + params->EnableTcssCovTypeA[1] = 0x82; // XXX: Enabling C10 reporting causes system to constantly enter and // exit opportunistic suspend when idle. diff --git a/src/mainboard/system76/mtl/variants/darp11/board.fmd b/src/mainboard/system76/mtl/variants/darp11/board.fmd index 2b8860d67ff..532555e0307 100644 --- a/src/mainboard/system76/mtl/variants/darp11/board.fmd +++ b/src/mainboard/system76/mtl/variants/darp11/board.fmd @@ -4,7 +4,7 @@ FLASH 32M { SI_ME 8612K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/mtl/variants/darp11/hda_verb.c b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c index 2915f4d9ebf..d66ae314660 100644 --- a/src/mainboard/system76/mtl/variants/darp11/hda_verb.c +++ b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c @@ -2,24 +2,20 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC245 */ - 0x10ec0245, /* Vendor ID */ - 0x1558a763, /* Subsystem ID */ - 40, /* Number of entries */ +static const u32 realtek_alc245_verbs[] = { //AZALIA_SUBVENDOR(0, 0x1558a763), AZALIA_SUBVENDOR(0, 0x1558a743), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x04211020), 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, @@ -54,6 +50,18 @@ const u32 cim_verb_data[] = { 0x01470c02, 0x01470c02, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC245", + .vendor_id = 0x10ec0245, + .subsystem_id = 0x1558a763, + .address = 0, + .verbs = realtek_alc245_verbs, + .verb_count = ARRAY_SIZE(realtek_alc245_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/darp11/ramstage.c b/src/mainboard/system76/mtl/variants/darp11/ramstage.c index 0e3baf2ad69..63dfb351519 100644 --- a/src/mainboard/system76/mtl/variants/darp11/ramstage.c +++ b/src/mainboard/system76/mtl/variants/darp11/ramstage.c @@ -9,8 +9,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // BIT 4:5 is reserved // BIT 6 is orientational // BIT 7 is enable - // TODO: Add to coreboot FSP headers as no Client FSP release will be made. - //params->EnableTcssCovTypeA[1] = 0x82; + params->EnableTcssCovTypeA[1] = 0x82; // XXX: Enabling C10 reporting causes system to constantly enter and // exit opportunistic suspend when idle. diff --git a/src/mainboard/system76/mtl/variants/lemp13/board.fmd b/src/mainboard/system76/mtl/variants/lemp13/board.fmd index 965e6bc3197..4e3ba09c6ca 100644 --- a/src/mainboard/system76/mtl/variants/lemp13/board.fmd +++ b/src/mainboard/system76/mtl/variants/lemp13/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 10128K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c index fa135ad3403..7fba906005c 100644 --- a/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c +++ b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c @@ -2,24 +2,19 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC245 */ - 0x10ec0245, /* Vendor ID */ - 0x15582624, /* Subsystem ID */ - 34, /* Number of entries */ - +static const u32 realtek_alc245_verbs[] = { AZALIA_SUBVENDOR(0, 0x15582624), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x04211020), 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, @@ -45,6 +40,18 @@ const u32 cim_verb_data[] = { 0x02050010, 0x02040020, 0x02050010, 0x02040020, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC245", + .vendor_id = 0x10ec0245, + .subsystem_id = 0x15582624, + .address = 0, + .verbs = realtek_alc245_verbs, + .verb_count = ARRAY_SIZE(realtek_alc245_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c index f99c93b0f2c..26a52e4c88d 100644 --- a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c +++ b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c @@ -11,9 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // BIT 4:5 is reserved // BIT 6 is orientational // BIT 7 is enable - // TODO: Add to coreboot FSP headers as no Client FSP release will be made. - //params->EnableTcssCovTypeA[1] = 0x81; - //params->EnableTcssCovTypeA[3] = 0x85; + params->EnableTcssCovTypeA[1] = 0x81; + params->EnableTcssCovTypeA[3] = 0x85; // Disable reporting CPU C10 state over eSPI (causes LED flicker). params->PchEspiHostC10ReportEnable = 0; diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig index a74bea2339c..b567520f372 100644 --- a/src/mainboard/system76/oryp5/Kconfig +++ b/src/mainboard/system76/oryp5/Kconfig @@ -4,10 +4,10 @@ if BOARD_SYSTEM76_ORYP5 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/oryp5/acpi/mainboard.asl b/src/mainboard/system76/oryp5/acpi/mainboard.asl index 17d2221ab4c..f816e3f2dad 100644 --- a/src/mainboard/system76/oryp5/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp5/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x17 /* GPP_B23 */ #define EC_GPE_SWI 0x26 /* GPP_G6 */ #include @@ -9,6 +11,10 @@ Scope (\_SB) #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index b72d9ba854d..7ed47cbeb75 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O @@ -62,6 +62,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/oryp5/hda_verb.c b/src/mainboard/system76/oryp5/hda_verb.c index 3f63cb3bc56..2465d954dee 100644 --- a/src/mainboard/system76/oryp5/hda_verb.c +++ b/src/mainboard/system76/oryp5/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155896e1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155896e1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155896e1, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp5/include/mainboard/gpio.h b/src/mainboard/system76/oryp5/include/mainboard/gpio.h index c6393beebb6..2bfbd100afb 100644 --- a/src/mainboard/system76/oryp5/include/mainboard/gpio.h +++ b/src/mainboard/system76/oryp5/include/mainboard/gpio.h @@ -3,7 +3,16 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x95e61558 + +#ifndef __ACPI__ void mainboard_configure_early_gpios(void); void mainboard_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/oryp5/romstage.c b/src/mainboard/system76/oryp5/romstage.c index 455a2bb9196..ec24f532b23 100644 --- a/src/mainboard/system76/oryp5/romstage.c +++ b/src/mainboard/system76/oryp5/romstage.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include @@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + // Allow memory speeds higher than 2666 MT/s memupd->FspmConfig.SaOcSupport = 1; diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index 8fd023d56a7..62efe91273a 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -4,10 +4,10 @@ if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7 config BOARD_SPECIFIC_OPTIONS def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/oryp6/Makefile.mk b/src/mainboard/system76/oryp6/Makefile.mk index ab8e965d872..af0b83b615a 100644 --- a/src/mainboard/system76/oryp6/Makefile.mk +++ b/src/mainboard/system76/oryp6/Makefile.mk @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/oryp6/acpi/mainboard.asl b/src/mainboard/system76/oryp6/acpi/mainboard.asl index b235437c25d..610cdd12bad 100644 --- a/src/mainboard/system76/oryp6/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp6/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include @@ -8,6 +10,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/oryp6/bootblock.c b/src/mainboard/system76/oryp6/bootblock.c index 0dc25dd200b..b351fbd8ef6 100644 --- a/src/mainboard/system76/oryp6/bootblock.c +++ b/src/mainboard/system76/oryp6/bootblock.c @@ -3,7 +3,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); } diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index bcb75d0b3ce..94064b2a027 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O @@ -59,6 +59,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/oryp6/include/variant/gpio.h b/src/mainboard/system76/oryp6/include/variant/gpio.h deleted file mode 100644 index 95d576294f6..00000000000 --- a/src/mainboard/system76/oryp6/include/variant/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -void variant_configure_early_gpios(void); -void variant_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/oryp6/romstage.c b/src/mainboard/system76/oryp6/romstage.c index 8ea791a2d10..964b14c6a97 100644 --- a/src/mainboard/system76/oryp6/romstage.c +++ b/src/mainboard/system76/oryp6/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include #include static const struct cnl_mb_cfg memcfg = { @@ -21,6 +23,19 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + variant_configure_fspm(memupd); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/system76/oryp6/variants/oryp6/gpio.c b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c index e90ea875f5d..bb3073c6ea5 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/gpio.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c @@ -257,7 +257,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPO(GPP_K22, 0, DEEP), // OVRM - PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_gpios(void) diff --git a/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c b/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c index cc60c322b27..357baacb53e 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c @@ -7,12 +7,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N - PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH - PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 + + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c index f9f6746c555..6a884442516 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155850d3, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155850d3), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155850d3, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h new file mode 100644 index 00000000000..e995e94bc8c --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_PWRGD GPP_K23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x50d31558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/oryp6/variants/oryp7/gpio.c b/src/mainboard/system76/oryp6/variants/oryp7/gpio.c index 88fb95a06fa..185f8d5b7aa 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/gpio.c +++ b/src/mainboard/system76/oryp6/variants/oryp7/gpio.c @@ -257,7 +257,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_K20, NONE), PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPO(GPP_K22, 0, DEEP), // OVRM - PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_gpios(void) diff --git a/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c b/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c index cc60c322b27..357baacb53e 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c +++ b/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c @@ -7,12 +7,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N - PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH - PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 + + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c index c46b63e60de..e7bdcf14234 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155865e5, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155865e5), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155865e5, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h new file mode 100644 index 00000000000..2980c0b1750 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_PWRGD GPP_K23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x65e51558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index c46ed2dada5..e683c45656a 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -2,13 +2,13 @@ config BOARD_SYSTEM76_RPL_COMMON def_bool n - select AZALIA_USE_LEGACY_VERB_TABLE select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_BAYHUB_LV2 if !BOARD_SYSTEM76_BONW15 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID select DRIVERS_I2C_HID select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -27,6 +27,8 @@ config BOARD_SYSTEM76_RPL_COMMON config BOARD_SYSTEM76_ADDW3 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select MAINBOARD_USES_IFD_GBE_REGION @@ -35,12 +37,25 @@ config BOARD_SYSTEM76_ADDW3 config BOARD_SYSTEM76_ADDW4 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S config BOARD_SYSTEM76_BONW15 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select DRIVERS_INTEL_DTBT + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_ALDERLAKE_PCH_S + +config BOARD_SYSTEM76_BONW15_B + select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select PCIEXP_HOTPLUG @@ -58,6 +73,15 @@ config BOARD_SYSTEM76_GALP7 config BOARD_SYSTEM76_GAZE18 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select EC_SYSTEM76_EC_DGPU + select SOC_INTEL_ALDERLAKE_PCH_P + +config BOARD_SYSTEM76_GAZE20 + select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P @@ -69,12 +93,16 @@ config BOARD_SYSTEM76_LEMP12 config BOARD_SYSTEM76_ORYP11 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_SYSTEM76_ORYP12 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_I2C_TAS5825M select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU @@ -83,6 +111,8 @@ config BOARD_SYSTEM76_ORYP12 config BOARD_SYSTEM76_SERW13 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + #select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select PCIEXP_HOTPLUG @@ -97,9 +127,11 @@ config VARIANT_DIR default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 + default "bonw15-b" if BOARD_SYSTEM76_BONW15_B default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "gaze20" if BOARD_SYSTEM76_GAZE20 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp12" if BOARD_SYSTEM76_ORYP12 @@ -112,9 +144,11 @@ config MAINBOARD_PART_NUMBER default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 + default "bonw15-b" if BOARD_SYSTEM76_BONW15_B default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "gaze20" if BOARD_SYSTEM76_GAZE20 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp12" if BOARD_SYSTEM76_ORYP12 @@ -122,10 +156,10 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_SMBIOS_PRODUCT_NAME default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 - default "Bonobo WS" if BOARD_SYSTEM76_BONW15 + default "Bonobo WS" if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B default "Darter Pro" if BOARD_SYSTEM76_DARP9 default "Galago Pro" if BOARD_SYSTEM76_GALP7 - default "Gazelle" if BOARD_SYSTEM76_GAZE18 + default "Gazelle" if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_GAZE20 default "Lemur Pro" if BOARD_SYSTEM76_LEMP12 default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 default "Serval WS" if BOARD_SYSTEM76_SERW13 @@ -134,20 +168,36 @@ config MAINBOARD_VERSION default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 + default "bonw15-b" if BOARD_SYSTEM76_BONW15_B default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "gaze20" if BOARD_SYSTEM76_GAZE20 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp12" if BOARD_SYSTEM76_ORYP12 default "serw13" if BOARD_SYSTEM76_SERW13 +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9 + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + config CONSOLE_POST default y config D3COLD_SUPPORT default n +config DRIVERS_GFX_NVIDIA_BRIDGE + default 0x02 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + default 80 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B + default 45 + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + default 25 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index 41842651f16..0a09982133a 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -9,6 +9,9 @@ config BOARD_SYSTEM76_ADDW4 config BOARD_SYSTEM76_BONW15 bool "bonw15" +config BOARD_SYSTEM76_BONW15_B + bool "bonw15-b" + config BOARD_SYSTEM76_DARP9 bool "darp9" @@ -18,6 +21,9 @@ config BOARD_SYSTEM76_GALP7 config BOARD_SYSTEM76_GAZE18 bool "gaze18" +config BOARD_SYSTEM76_GAZE20 + bool "gaze20" + config BOARD_SYSTEM76_LEMP12 bool "lemp12" diff --git a/src/mainboard/system76/rpl/Makefile.mk b/src/mainboard/system76/rpl/Makefile.mk index 2c8dfba322e..a5011cdba0f 100644 --- a/src/mainboard/system76/rpl/Makefile.mk +++ b/src/mainboard/system76/rpl/Makefile.mk @@ -2,6 +2,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +endif + bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/rpl/acpi/mainboard.asl b/src/mainboard/system76/rpl/acpi/mainboard.asl index c982a9ee4cb..63ccf020d55 100644 --- a/src/mainboard/system76/rpl/acpi/mainboard.asl +++ b/src/mainboard/system76/rpl/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(DRIVERS_GFX_NVIDIA) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,17 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + +#if CONFIG(DRIVERS_GFX_NVIDIA) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15) || CONFIG(BOARD_SYSTEM76_BONW15_B) + Scope (PEG2) { + #include + } +#else + Scope (PEG1) { + #include + } +#endif +#endif // CONFIG(DRIVERS_GFX_NVIDIA) } } diff --git a/src/mainboard/system76/rpl/cmos-csme.default b/src/mainboard/system76/rpl/cmos-csme.default new file mode 100644 index 00000000000..d61046df6b0 --- /dev/null +++ b/src/mainboard/system76/rpl/cmos-csme.default @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 5acf4bba056..5d549cf896f 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/alderlake register "eist_enable" = "true" # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # Thermal register "tcc_offset" = "8" @@ -24,7 +24,6 @@ chip soc/intel/alderlake register "disable_package_c_state_demotion" = "true" device domain 0 on - device ref system_agent on end device ref igpu on # DDIA is eDP, DDIB is HDMI register "ddi_portA_config" = "1" @@ -48,7 +47,6 @@ chip soc/intel/alderlake register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 @@ -72,6 +70,5 @@ chip soc/intel/alderlake register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" end device ref smbus on end - device ref fast_spi on end end end diff --git a/src/mainboard/system76/rpl/variants/addw3/board.fmd b/src/mainboard/system76/rpl/variants/addw3/board.fmd index 187263e5cc5..451ca7aeefa 100644 --- a/src/mainboard/system76/rpl/variants/addw3/board.fmd +++ b/src/mainboard/system76/rpl/variants/addw3/board.fmd @@ -4,7 +4,7 @@ FLASH 32M { SI_ME 3944K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/addw3/gpio.c b/src/mainboard/system76/rpl/variants/addw3/gpio.c index ca72259851b..e31a90aac07 100644 --- a/src/mainboard/system76/rpl/variants/addw3/gpio.c +++ b/src/mainboard/system76/rpl/variants/addw3/gpio.c @@ -262,7 +262,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), PAD_NC(GPP_R7, NONE), - PAD_CFG_GPI(GPP_R8, NONE, PLTRST), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_R8, NONE, PLTRST), // DGPU_PWRGD_R PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD PAD_NC(GPP_R10, NONE), PAD_NC(GPP_R11, NONE), diff --git a/src/mainboard/system76/rpl/variants/addw3/gpio_early.c b/src/mainboard/system76/rpl/variants/addw3/gpio_early.c index b6914ad7164..4b77e6c6bf7 100644 --- a/src/mainboard/system76/rpl/variants/addw3/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/addw3/gpio_early.c @@ -6,7 +6,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, PLTRST), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH }; diff --git a/src/mainboard/system76/rpl/variants/addw3/hda_verb.c b/src/mainboard/system76/rpl/variants/addw3/hda_verb.c index 08f3aff2319..c4fb8044d74 100644 --- a/src/mainboard/system76/rpl/variants/addw3/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/addw3/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x1558a671, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x1558a671), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x1558a671, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h new file mode 100644 index 00000000000..eeb49623730 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_R8 +#define DGPU_GC6 GPP_F8 +#define DGPU_SSID 0xa6711558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/addw3/romstage.c b/src/mainboard/system76/rpl/variants/addw3/romstage.c index 30a904544cd..905485e7b93 100644 --- a/src/mainboard/system76/rpl/variants/addw3/romstage.c +++ b/src/mainboard/system76/rpl/variants/addw3/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/addw4/board.fmd b/src/mainboard/system76/rpl/variants/addw4/board.fmd index b2615d1e171..9da2cbdf4f5 100644 --- a/src/mainboard/system76/rpl/variants/addw4/board.fmd +++ b/src/mainboard/system76/rpl/variants/addw4/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 3944K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio.c b/src/mainboard/system76/rpl/variants/addw4/gpio.c index 471212b8883..b6379f3482e 100644 --- a/src/mainboard/system76/rpl/variants/addw4/gpio.c +++ b/src/mainboard/system76/rpl/variants/addw4/gpio.c @@ -262,7 +262,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), PAD_NC(GPP_R7, NONE), - PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + //PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD PAD_NC(GPP_R10, NONE), PAD_NC(GPP_R11, NONE), diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio_early.c b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c index b6914ad7164..4014113950e 100644 --- a/src/mainboard/system76/rpl/variants/addw4/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c @@ -6,7 +6,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH }; diff --git a/src/mainboard/system76/rpl/variants/addw4/hda_verb.c b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c index 3850d3411e4..c227db741f1 100644 --- a/src/mainboard/system76/rpl/variants/addw4/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c @@ -2,12 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC245 */ - 0x10ec0245, /* Vendor ID */ - 0x15580353, /* Subsystem ID */ - 35, /* Number of entries */ - +static const u32 realtek_alc245_verbs[] = { 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, AZALIA_SUBVENDOR(0, 0x15580353), @@ -15,13 +10,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x04211020), 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, @@ -47,6 +42,18 @@ const u32 cim_verb_data[] = { 0x02050010, 0x02040020, 0x02050010, 0x02040020, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC245", + .vendor_id = 0x10ec0245, + .subsystem_id = 0x15580353, + .address = 0, + .verbs = realtek_alc245_verbs, + .verb_count = ARRAY_SIZE(realtek_alc245_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h new file mode 100644 index 00000000000..98b6d7b143f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_R8 +#define DGPU_SSID 0x03531558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/addw4/romstage.c b/src/mainboard/system76/rpl/variants/addw4/romstage.c index fe9103240cd..171264ecdac 100644 --- a/src/mainboard/system76/rpl/variants/addw4/romstage.c +++ b/src/mainboard/system76/rpl/variants/addw4/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to hybrid graphics mupd->FspmConfig.PrimaryDisplay = 4; diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/board.fmd b/src/mainboard/system76/rpl/variants/bonw15-b/board.fmd new file mode 100644 index 00000000000..9da2cbdf4f5 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 3944K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 512K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/board_info.txt b/src/mainboard/system76/rpl/variants/bonw15-b/board_info.txt new file mode 100644 index 00000000000..9dae13e21c3 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/board_info.txt @@ -0,0 +1,2 @@ +Board name: bonw15-b +Release year: 2024 diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/data.vbt b/src/mainboard/system76/rpl/variants/bonw15-b/data.vbt new file mode 100644 index 00000000000..fedf53f295c Binary files /dev/null and b/src/mainboard/system76/rpl/variants/bonw15-b/data.vbt differ diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/gpio.c b/src/mainboard/system76/rpl/variants/bonw15-b/gpio.c new file mode 100644 index 00000000000..63179d3699f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/gpio.c @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + _PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000), // PCH_LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7 + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN_N + PAD_NC(GPD10, NONE), + PAD_CFG_GPO(GPD11, 0, DEEP), // LANPHYPC + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_ALERT0# + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, DEEP), // PCH_BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, NONE), // PS8461_SW + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), // 2.5G_LAN_EN + PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1), // PMCALERT# (tied high) + PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPO(GPP_B22, 1, DEEP), // LAN_RST# + PAD_CFG_GPI(GPP_B23, NONE, RSMRST), // GPP_B23 (XTAL FREQ SEL1) + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, PLTRST), // TLS confidentiality strap + PAD_CFG_GPO(GPP_C3, 0, DEEP), // GPPC_I2C2_SDA (Pantone) + PAD_CFG_GPO(GPP_C4, 0, DEEP), // GPPC_I2C2_SCL (Pantone) + PAD_NC(GPP_C5, NONE), // eSPI disable strap + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA (TPS65994) + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL (TPS65994) + // GPP_C20 (UART2_RXD) configured in bootblock + // GPP_C21 (UART2_TXD) configured in bootblock + PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN (TPS65994) + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), + PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), // GPP_E0_TBT_RST# + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // GPP_E_9_USB_OC0_N + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), // GPP_E_10_USB_OC1_N + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), // GPP_E_11_USB_OC2_N + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), // GPP_E_12_USB_OC3_N + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + _PAD_CFG_STRUCT(GPP_E19, 0x42880100, 0x0000), // GPP_E19_TBT_WAKE# + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GC6_FB_EN_PCH + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_CFG_GPI(GPP_F14, NONE, DEEP), // TBT5 strap + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + // GPP_F22 (DGPU_PWR_EN) configured in bootblock + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // GPU SKU strap (L: X9, H: X11) + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // DDS strap (L: Non-DDS, H: DDS) + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Smart AMP strap (L: TI, H: Realtek) + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM_N + PAD_CFG_GPI(GPP_G6, NONE, DEEP), // Pantone (L: W/O, H: W) + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), // WLAN_WAKE_N + // GPP_H3 (WLAN_CLKREQ9#) configured by FSP + // GPP_H4 (SSD1_CLKREQ10#) configured by FSP + // GPP_H5 (SSD2_CLKREQ11#) configured by FSP + // GPP_H6 (SSD3_CLKREQ12#) configured by FSP + // GPP_H7 (TBT_CLKREQ13#) configured by FSP + // GPP_H8 (GPU_PCIE_CLKREQ14#) configured by FSP + // GPP_H9 (GLAN_CLKREQ15#) configured by FSP + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_GPI(GPP_H12, NONE, RSMRST), // eSPI flash sharing mode strap (L: MAF, H: SAF) + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPI(GPP_H15, NONE, RSMRST), // JTAG ODT disable strap (L: Disable, H: Enable) + PAD_NC(GPP_H16, NONE), + PAD_CFG_GPO(GPP_H17, 1, DEEP), // M.2_PLT_RST_CNTRL3# + PAD_CFG_GPI(GPP_H18, NONE, RSMRST), // VCCPSPI strap (L: 3.3V, H: 1.8V) + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), // TBT_MRESET_PCH + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + _PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000), // G_DP_DHPD_E + _PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000), // DP_D_HPD + _PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000), // DP_A_HPD + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), // GPP_I_11_USB_OC4_N + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), // GPP_I_12_USB_OC5_N + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), // GPP_I_13_USB_OC6_N + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), // GPP_I_14_USB_OC7_N + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_CFG_GPI(GPP_I18, NONE, PWROK), // No reboot strap (L: Disable, H: Enable) + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_CFG_GPI(GPP_I22, NONE, PWROK), // Boot BIOS strap (L: MAF or SAF, H: eSPI) + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + // GPP_K6 missing + // GPP_K7 missing + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // GPP_K_8_CORE_VID_0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // GPP_K_9_CORE_VID_1 + PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2), + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_CFG_GPO(GPP_R7, 1, DEEP), // GPP_R7_TBT_RTD3 + //PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_NC(GPP_R19, NONE), + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), // GPPS_DMIC_CLK + PAD_NC(GPP_S5, NONE), // GPPS_DMIC_DATA + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/gpio_early.c b/src/mainboard/system76/rpl/variants/bonw15-b/gpio_early.c new file mode 100644 index 00000000000..f097ec63d3e --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/gpio_early.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/hda_verb.c b/src/mainboard/system76/rpl/variants/bonw15-b/hda_verb.c new file mode 100644 index 00000000000..e69e6dea629 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/hda_verb.c @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc1220_verbs[] = { + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + AZALIA_SUBVENDOR(0, 0x15583702), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), + + // ALC1318 smart amp + 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, + 0x02050058, 0x02048ed1, 0x02050063, 0x0204e430, + 0x02050016, 0x02048020, 0x02050016, 0x02048020, + 0x02050043, 0x02043005, 0x02050058, 0x02048ed1, + 0x02050063, 0x0204e430, 0x05b50000, 0x05b43530, + 0x05750002, 0x05741400, 0x05b5000a, 0x05b45520, + 0x02050042, 0x020486cb, 0x0143b000, 0x01470700, + 0x02050036, 0x02042a6a, 0x02050008, 0x0204800b, + 0x02050007, 0x020403c3, 0x01470c02, 0x01470c02, + 0x00c37100, 0x01b3b000, 0x01b70700, 0x00b37417, + 0x0205001b, 0x02044002, 0x0205001b, 0x02044002, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c000, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f20d, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f212, 0x0205002b, 0x0204003e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c001, + 0x0205002b, 0x02040002, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c003, 0x0205002b, 0x02040022, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c004, + 0x0205002b, 0x02040044, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c005, 0x0205002b, 0x02040044, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c007, + 0x0205002b, 0x02040064, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c00e, 0x0205002b, 0x020400e7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f223, + 0x0205002b, 0x0204007f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f224, 0x0205002b, 0x020400db, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f225, + 0x0205002b, 0x020400ee, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f226, 0x0205002b, 0x0204003f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f227, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f21a, 0x0205002b, 0x02040078, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f242, + 0x0205002b, 0x0204003c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c120, 0x0205002b, 0x02040040, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c321, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c200, + 0x0205002b, 0x020400d8, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c201, 0x0205002b, 0x02040027, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c202, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c400, 0x0205002b, 0x0204000e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c401, + 0x0205002b, 0x02040043, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c402, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c403, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c404, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c406, + 0x0205002b, 0x02040040, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c407, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c408, + 0x0205002b, 0x0204003f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c300, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df00, 0x0205002b, 0x02040010, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204df5f, + 0x0205002b, 0x02040001, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df60, 0x0205002b, 0x020400a7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ea00, + 0x0205002b, 0x02040047, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c203, 0x0205002b, 0x02040004, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c206, + 0x0205002b, 0x02040078, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x02040065, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e706, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e707, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e806, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e807, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce60, 0x0205002b, 0x020400e3, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c130, + 0x0205002b, 0x02040051, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e000, 0x0205002b, 0x020400a8, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02044100, 0x02050029, 0x02041888, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c121, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, + + // XXX: Duplicate last 2 u32s to keep in 4-dword blocks + 0x0205002c, 0x0204b423, +}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x15583702, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/bonw15-b/include/variant/gpio.h new file mode 100644 index 00000000000..002b9d1130a --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F22 +#define DGPU_PWRGD GPP_R8 +#define DGPU_GC6 GPP_F8 +#define DGPU_SSID 0x37021558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15-b/overridetree.cb new file mode 100644 index 00000000000..33cf3a1a870 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/overridetree.cb @@ -0,0 +1,164 @@ +chip soc/intel/alderlake + # Support 5600 MT/s memory + register "max_dram_speed_mts" = "5600" + + device domain 0 on + subsystemid 0x1558 0x3702 inherit + + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Front) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Rear) */ + [5] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [6] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */ + /* Port reset messaging cannot be used, + * so do not use USB2_PORT_TYPE_C for these */ + [8] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt (Right, Front) */ + [9] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt with PD (Right, Rear) */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Front) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Rear) */ + }" + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Type-A 3.2 Gen 2 (Left, Front)"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A 3.2 Gen 2 (Left, Rear)"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""Per-key RGB"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Thunderbolt (Right, Front)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Thunderbolt with PD (Right, Rear)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port14 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A 3.2 Gen 2 (Left, Front)"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A 3.2 Gen 2 (Left, Rear)"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port3 on end + end + end + end + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # CPU PCIe RP#3 x4, CLKOUT 2, CLKREQ 11 (SSD2) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 2, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + + device ref pcie5_1 on + # CPU PCIe RP#2 x8, Clock 14 (DGPU) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 14, + .clk_req = 14, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pcie4_0 on + # CPU PCIe RP#1 x4, Clock 12 (SSD3) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 12, + .clk_req = 12, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD3)" "SlotDataBusWidth4X" + end + + device ref pcie_rp7 on + # PCH RP#7 x1, Clock 13 (GLAN) + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 15, + .clk_req = 15, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + + device ref pcie_rp8 on + # PCH RP#8 x1, Clock 9 (WLAN) + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 9, + .clk_req = 9, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + + device ref pcie_rp9 on + # PCH RP#9 x4, Clock 15 (TBT) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 13, + .clk_req = 13, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR, + }" + end + + device ref pcie_rp21 on + # PCH RP#21 x4, Clock 10 (SSD1) + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .clk_src = 10, + .clk_req = 10, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + end +end diff --git a/src/mainboard/system76/rpl/variants/bonw15-b/romstage.c b/src/mainboard/system76/rpl/variants/bonw15-b/romstage.c new file mode 100644 index 00000000000..905485e7b93 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15-b/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/rpl/variants/bonw15/board.fmd b/src/mainboard/system76/rpl/variants/bonw15/board.fmd index b2615d1e171..9da2cbdf4f5 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/board.fmd +++ b/src/mainboard/system76/rpl/variants/bonw15/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 3944K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/bonw15/gpio.c b/src/mainboard/system76/rpl/variants/bonw15/gpio.c index d0685d5dc43..878cb23e8bf 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/gpio.c +++ b/src/mainboard/system76/rpl/variants/bonw15/gpio.c @@ -262,7 +262,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), PAD_NC(GPP_R7, NONE), - PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + //PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD PAD_NC(GPP_R10, NONE), PAD_NC(GPP_R11, NONE), diff --git a/src/mainboard/system76/rpl/variants/bonw15/gpio_early.c b/src/mainboard/system76/rpl/variants/bonw15/gpio_early.c index cea38b54cec..f097ec63d3e 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/bonw15/gpio_early.c @@ -6,7 +6,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH }; diff --git a/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c b/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c index d5537b4a7e2..e1adfb4dee3 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c @@ -2,12 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x15583702, /* Subsystem ID */ - 243, /* Number of entries */ - +static const u32 realtek_alc1220_verbs[] = { 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, AZALIA_SUBVENDOR(0, 0x15583702), AZALIA_RESET(1), @@ -258,6 +253,18 @@ const u32 cim_verb_data[] = { 0x0205002c, 0x0204b423, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x15583702, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h new file mode 100644 index 00000000000..002b9d1130a --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F22 +#define DGPU_PWRGD GPP_R8 +#define DGPU_GC6 GPP_F8 +#define DGPU_SSID 0x37021558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/bonw15/romstage.c b/src/mainboard/system76/rpl/variants/bonw15/romstage.c index 30a904544cd..905485e7b93 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/romstage.c +++ b/src/mainboard/system76/rpl/variants/bonw15/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/darp9/board.fmd b/src/mainboard/system76/rpl/variants/darp9/board.fmd index fdf1ebdf52b..dc4ac4685f4 100644 --- a/src/mainboard/system76/rpl/variants/darp9/board.fmd +++ b/src/mainboard/system76/rpl/variants/darp9/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/darp9/hda_verb.c b/src/mainboard/system76/rpl/variants/darp9/hda_verb.c index 57961ee2d2e..c2ad20a9c49 100644 --- a/src/mainboard/system76/rpl/variants/darp9/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/darp9/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x155851b1, /* Subsystem ID */ - 19, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { 0x0205001a, 0x02048003, 0x0205001a, 0x0204c003, AZALIA_SUBVENDOR(0, 0x155851b1), AZALIA_RESET(1), @@ -28,6 +24,18 @@ const u32 cim_verb_data[] = { 0x00170503, 0x0143b000, 0x0213b000, 0x02170740, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x155851b1, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index 3dc27864fe0..b83ad748329 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, diff --git a/src/mainboard/system76/rpl/variants/galp7/board.fmd b/src/mainboard/system76/rpl/variants/galp7/board.fmd index fdf1ebdf52b..dc4ac4685f4 100644 --- a/src/mainboard/system76/rpl/variants/galp7/board.fmd +++ b/src/mainboard/system76/rpl/variants/galp7/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/galp7/gpio.c b/src/mainboard/system76/rpl/variants/galp7/gpio.c index 8e3532fe698..9bc2e74dd62 100644 --- a/src/mainboard/system76/rpl/variants/galp7/gpio.c +++ b/src/mainboard/system76/rpl/variants/galp7/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_A20, NONE), PAD_NC(GPP_A21, NONE), PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN diff --git a/src/mainboard/system76/rpl/variants/galp7/gpio_early.c b/src/mainboard/system76/rpl/variants/galp7/gpio_early.c index 85b9307d456..38cbc97ed71 100644 --- a/src/mainboard/system76/rpl/variants/galp7/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/galp7/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/rpl/variants/galp7/hda_verb.c b/src/mainboard/system76/rpl/variants/galp7/hda_verb.c index 8679812a0c1..84653f2243a 100644 --- a/src/mainboard/system76/rpl/variants/galp7/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/galp7/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x15584041, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15584041), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15584041, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/gaze18/board.fmd b/src/mainboard/system76/rpl/variants/gaze18/board.fmd index fdf1ebdf52b..dc4ac4685f4 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/board.fmd +++ b/src/mainboard/system76/rpl/variants/gaze18/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/gaze18/gpio.c b/src/mainboard/system76/rpl/variants/gaze18/gpio.c index 1f603fc966b..b4d0666409a 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/gpio.c +++ b/src/mainboard/system76/rpl/variants/gaze18/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A16, NONE), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE# PAD_NC(GPP_A21, NONE), PAD_NC(GPP_A22, NONE), diff --git a/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c b/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c index 85b9307d456..38cbc97ed71 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c index 743cfb72c8c..d61d7481758 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x15585630, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15585630), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15585630, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h new file mode 100644 index 00000000000..f7d470e02f4 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_A19 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x56301558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/gaze18/romstage.c b/src/mainboard/system76/rpl/variants/gaze18/romstage.c index 1e597c72a69..64276a1c46b 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/romstage.c +++ b/src/mainboard/system76/rpl/variants/gaze18/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -19,6 +21,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/gaze20/board.fmd b/src/mainboard/system76/rpl/variants/gaze20/board.fmd new file mode 100644 index 00000000000..dc4ac4685f4 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 4824K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 512K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/gaze20/board_info.txt b/src/mainboard/system76/rpl/variants/gaze20/board_info.txt new file mode 100644 index 00000000000..4d60ca7c13d --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze20 +Release year: 2025 diff --git a/src/mainboard/system76/rpl/variants/gaze20/data.vbt b/src/mainboard/system76/rpl/variants/gaze20/data.vbt new file mode 100644 index 00000000000..f01115566a7 Binary files /dev/null and b/src/mainboard/system76/rpl/variants/gaze20/data.vbt differ diff --git a/src/mainboard/system76/rpl/variants/gaze20/gpio.c b/src/mainboard/system76/rpl/variants/gaze20/gpio.c new file mode 100644 index 00000000000..830efb6d56f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), // LANRTD3_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // Not documented + PAD_CFG_GPI(GPD9, NONE, DEEP), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // DP_HPD + PAD_NC(GPP_A16, NONE), + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // MDP_B_HPD + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + _PAD_CFG_STRUCT(GPP_A20, 0x86880100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_A21, 0x86880100, 0x0000), // NVVDD_TALERT# + PAD_CFG_GPO(GPP_A22, 1, PLTRST), // LAN_PWR_EN + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_PCH) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_NC(GPP_B4, NONE), + PAD_CFG_GPO(GPP_B5, 0, DEEP), // PS8461_SW + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + // GPP_B9 missing + // GPP_B10 missing + PAD_CFG_GPI(GPP_B11, NONE, PLTRST), // PMCALERT# + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap + PAD_CFG_GPO(GPP_B15, 1, PLTRST), // WLAN_RST#_R + _PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000), // INTP_OUT + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // NO REBOOT strap + // GPP_B19 missing + // GPP_B20 missing + // GPP_B21 missing + // GPP_B22 missing + PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_SSD2_PWR_EN + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPO(GPP_C5, 1, PLTRST), // LAN_RTD3#, TLS CONFIDENTIALITY strap + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + // GPP_C8 missing + // GPP_C9 missing + // GPP_C10 missing + // GPP_C11 missing + // GPP_C12 missing + // GPP_C13 missing + // GPP_C14 missing + // GPP_C15 missing + // GPP_C16 missing + // GPP_C17 missing + // GPP_C18 missing + // GPP_C19 missing + // GPP_C20 missing + // GPP_C21 missing + // GPP_C22 missing + // GPP_C23 missing + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + // GPP_D5 (SSD1_CLKREQ#) configured by FSP + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + // GPP_D8 (GPU_PCIE_CLKREQ3#) configured by FSP + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), // strap + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), // strap + PAD_CFG_GPO(GPP_D13, 0, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_SSD1_PWR_EN + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 0, DEEP), // TEST_R + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_E2, NONE), // BOARD_ID5 + PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap + PAD_NC(GPP_E7, NONE), + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_NC(GPP_E9, NONE), // SWI# + PAD_NC(GPP_E10, NONE), // strap + PAD_NC(GPP_E11, NONE), // strap + PAD_NC(GPP_E12, NONE), // BOARD_ID4 + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), // strap + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), // strap + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST# + // GPP_F5 (XTAL_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // GPP_LAN_RST# + // GPP_F8 missing + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), // strap + PAD_NC(GPP_F11, NONE), // BOARD_ID3 + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_NC(GPP_F14, NONE), // BOARD_ID1 + PAD_NC(GPP_F15, NONE), // BOARD_ID2 + PAD_NC(GPP_F16, NONE), // BOARD_ID6 + PAD_NC(GPP_F17, NONE), // BOARD_ID7 + PAD_CFG_GPO(GPP_F18, 1, DEEP), // CCD_FW_WP# + // GPP_F19 (GLAN_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST# + PAD_CFG_GPO(GPP_F21, 1, PLTRST), // M2_SSD2_RST# + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), // strap + PAD_NC(GPP_H1, NONE), // strap + PAD_NC(GPP_H2, NONE), // strap + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // SMD_7411 + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // SMC_7411 + PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RX) configured in bootblock + // GPP_H11 (UART0_TX) configured in bootblock + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + // GPP_H14 missing + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // I_MDP_CLK + // GPP_H16 missing + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // I_MDP_DATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + // GPP_H19 (SSD2_CLKREQ4#) configured by FSP + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + // GPP_H23 (WLAN_CLKREQ5#) configured by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/gaze20/gpio_early.c b/src/mainboard/system76/rpl/variants/gaze20/gpio_early.c new file mode 100644 index 00000000000..38cbc97ed71 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/gpio_early.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/gaze20/hda_verb.c b/src/mainboard/system76/rpl/variants/gaze20/hda_verb.c new file mode 100644 index 00000000000..97c277ccdc9 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc255_verbs[] = { + AZALIA_SUBVENDOR(0, 0x15582560), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x41e79b45), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), +}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC255", + .vendor_id = 0x10ec0255, + .subsystem_id = 0x15582560, + .address = 0, + .verbs = realtek_alc255_verbs, + .verb_count = ARRAY_SIZE(realtek_alc255_verbs), + }, + { /* terminator */ } +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/gaze20/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/gaze20/include/variant/gpio.h new file mode 100644 index 00000000000..4d3a913d0f4 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_A19 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x25601558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/gaze20/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze20/overridetree.cb new file mode 100644 index 00000000000..153f0618bf6 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/overridetree.cb @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + register "max_dram_speed_mts" = "6400" + + device domain 0 on + subsystemid 0x1558 0x2560 inherit + + device ref igpu on + # DDIA is eDP, DDIB is mDP, TCP3 (DDI4) is USB-C + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_4] = DDI_ENABLE_HPD, + }" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB Type-C */ + [1] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 Type-A audio board */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.0 Type-A motherboard */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.0 Type-A audio board */ + [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-C */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.0 Type-A motherboard */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.0 Type-A audio board */ + }" + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 2.0 Type-A audio board"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A motherboard"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A audio board"" + register "type" = "UPC_TYPE_A" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A motherboard"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 3.0 Type-A motherboard"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port4 on end + end + end + end + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # CPU RP#2 x8, Clock 3 (GPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie4_0 on + # CPU RP#1 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref pcie4_1 on + # CPU RP#3 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp5 on + # PCH RP#5 x1, Clock 5 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref pcie_rp7 on + # PCH RP#7 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + end +end diff --git a/src/mainboard/system76/rpl/variants/gaze20/romstage.c b/src/mainboard/system76/rpl/variants/gaze20/romstage.c new file mode 100644 index 00000000000..64276a1c46b --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze20/romstage.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/rpl/variants/lemp12/board.fmd b/src/mainboard/system76/rpl/variants/lemp12/board.fmd index fdf1ebdf52b..dc4ac4685f4 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/board.fmd +++ b/src/mainboard/system76/rpl/variants/lemp12/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c index 410d44cf584..8b34fe0e4b0 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x15587724, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15587724), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15587724, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp11/board.fmd b/src/mainboard/system76/rpl/variants/oryp11/board.fmd index fdf1ebdf52b..dc4ac4685f4 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/board.fmd +++ b/src/mainboard/system76/rpl/variants/oryp11/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 4824K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio.c b/src/mainboard/system76/rpl/variants/oryp11/gpio.c index 20ecef6b6c5..e4908a3624f 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/gpio.c +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# _PAD_CFG_STRUCT(GPP_A18, 0x86880100, 0x0000), // HDMI_HPD - PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_A20, 1, DEEP), // DGPU_OVRM PAD_CFG_GPO(GPP_A21, 1, DEEP), // GPIO_LANRTD3 PAD_CFG_GPO(GPP_A22, 1, DEEP), diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c index 85b9307d456..38cbc97ed71 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c index 368e83e4fe6..6690ae16c48 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c @@ -2,12 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155866a2, /* Subsystem ID */ - 243, /* Number of entries */ - +static const u32 realtek_alc1220_verbs[] = { 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, AZALIA_SUBVENDOR(0, 0x155866a2), AZALIA_RESET(1), @@ -258,6 +253,18 @@ const u32 cim_verb_data[] = { 0x0205002c, 0x0204b423, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155866a2, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h new file mode 100644 index 00000000000..cb849968337 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_PWRGD GPP_A19 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x66a21558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/oryp11/romstage.c b/src/mainboard/system76/rpl/variants/oryp11/romstage.c index 1e597c72a69..64276a1c46b 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/romstage.c +++ b/src/mainboard/system76/rpl/variants/oryp11/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -19,6 +21,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/oryp12/board.fmd b/src/mainboard/system76/rpl/variants/oryp12/board.fmd index b2615d1e171..9da2cbdf4f5 100644 --- a/src/mainboard/system76/rpl/variants/oryp12/board.fmd +++ b/src/mainboard/system76/rpl/variants/oryp12/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 3944K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/oryp12/gpio.c b/src/mainboard/system76/rpl/variants/oryp12/gpio.c index becce050064..a547c1272df 100644 --- a/src/mainboard/system76/rpl/variants/oryp12/gpio.c +++ b/src/mainboard/system76/rpl/variants/oryp12/gpio.c @@ -264,7 +264,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_R5, 0, DEEP), // PCH_MUTE (XXX: SMART_AMP_EN) PAD_NC(GPP_R6, NONE), PAD_NC(GPP_R7, NONE), - PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD PAD_NC(GPP_R10, NONE), PAD_NC(GPP_R11, NONE), diff --git a/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c b/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c index b6914ad7164..a36c4d5b7ed 100644 --- a/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c @@ -6,7 +6,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH }; diff --git a/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c index 9bd1e6da489..7d28a164b2b 100644 --- a/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c @@ -2,12 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155866a6, /* Subsystem ID */ - 24, /* Number of entries */ - +static const u32 realtek_alc1220_verbs[] = { 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, AZALIA_SUBVENDOR(0, 0x155866a6), @@ -15,14 +10,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60120), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40a7952d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, 0x02050058, 0x02048ed1, 0x02050063, 0x0204e430, @@ -36,6 +31,18 @@ const u32 cim_verb_data[] = { 0x0205001b, 0x02044002, 0x0205001b, 0x02044002, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155866a6, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h new file mode 100644 index 00000000000..3af23101af9 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_R8 +#define DGPU_SSID 0x66a61558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/oryp12/romstage.c b/src/mainboard/system76/rpl/variants/oryp12/romstage.c index fe9103240cd..171264ecdac 100644 --- a/src/mainboard/system76/rpl/variants/oryp12/romstage.c +++ b/src/mainboard/system76/rpl/variants/oryp12/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to hybrid graphics mupd->FspmConfig.PrimaryDisplay = 4; diff --git a/src/mainboard/system76/rpl/variants/serw13/board.fmd b/src/mainboard/system76/rpl/variants/serw13/board.fmd index b2615d1e171..9da2cbdf4f5 100644 --- a/src/mainboard/system76/rpl/variants/serw13/board.fmd +++ b/src/mainboard/system76/rpl/variants/serw13/board.fmd @@ -3,7 +3,7 @@ FLASH 32M { SI_ME 3944K SI_BIOS@16M 16M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/rpl/variants/serw13/gpio.c b/src/mainboard/system76/rpl/variants/serw13/gpio.c index acdf54846b7..a8bd0b5f453 100644 --- a/src/mainboard/system76/rpl/variants/serw13/gpio.c +++ b/src/mainboard/system76/rpl/variants/serw13/gpio.c @@ -262,7 +262,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), PAD_NC(GPP_R7, NONE), - PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD PAD_NC(GPP_R10, NONE), PAD_NC(GPP_R11, NONE), diff --git a/src/mainboard/system76/rpl/variants/serw13/gpio_early.c b/src/mainboard/system76/rpl/variants/serw13/gpio_early.c index fe6584546b3..51f2b818145 100644 --- a/src/mainboard/system76/rpl/variants/serw13/gpio_early.c +++ b/src/mainboard/system76/rpl/variants/serw13/gpio_early.c @@ -4,10 +4,12 @@ #include static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN - PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RX PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TX + + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/system76/rpl/variants/serw13/hda_verb.c b/src/mainboard/system76/rpl/variants/serw13/hda_verb.c index 191eadf1b69..5a9c51ed260 100644 --- a/src/mainboard/system76/rpl/variants/serw13/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/serw13/hda_verb.c @@ -2,12 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x1558d502, /* Subsystem ID */ - 241, - +static const u32 realtek_alc1220_verbs[] = { 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, AZALIA_SUBVENDOR(0, 0x1558d502), AZALIA_RESET(1), @@ -256,6 +251,18 @@ const u32 cim_verb_data[] = { 0x0205002c, 0x0204b423, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x1558d502, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h new file mode 100644 index 00000000000..42e17ce073e --- /dev/null +++ b/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_R8 +#define DGPU_GC6 GPP_A11 +#define DGPU_SSID 0xd5021558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/serw13/romstage.c b/src/mainboard/system76/rpl/variants/serw13/romstage.c index 30a904544cd..365f6390e80 100644 --- a/src/mainboard/system76/rpl/variants/serw13/romstage.c +++ b/src/mainboard/system76/rpl/variants/serw13/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig index 7a0d3f56951..89a58f13fae 100644 --- a/src/mainboard/system76/tgl-h/Kconfig +++ b/src/mainboard/system76/tgl-h/Kconfig @@ -1,18 +1,16 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B || BOARD_SYSTEM76_ORYP8 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE +config BOARD_SYSTEM76_TGL_H_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID - select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP8 select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -21,10 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_LPSS_UART_FOR_CONSOLE select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE16_3060_B select NO_UART_ON_SUPERIO - select PCIEXP_HOTPLUG if BOARD_SYSTEM76_ORYP8 - select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G if BOARD_SYSTEM76_ORYP8 select SOC_INTEL_TIGERLAKE select SOC_INTEL_TIGERLAKE_PCH_H select SOC_INTEL_COMMON_BLOCK_HDA_VERB @@ -32,6 +27,24 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_MEASURED_BOOT +config BOARD_SYSTEM76_GAZE16_3050 + select BOARD_SYSTEM76_TGL_H_COMMON + +config BOARD_SYSTEM76_GAZE16_3060 + select BOARD_SYSTEM76_TGL_H_COMMON + +config BOARD_SYSTEM76_GAZE16_3060_B + select BOARD_SYSTEM76_TGL_H_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_SYSTEM76_ORYP8 + select BOARD_SYSTEM76_TGL_H_COMMON + select DRIVERS_I2C_TAS5825M + select PCIEXP_HOTPLUG + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + +if BOARD_SYSTEM76_TGL_H_COMMON + config MAINBOARD_DIR default "system76/tgl-h" @@ -43,7 +56,7 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_SMBIOS_PRODUCT_NAME default "Oryx Pro" if BOARD_SYSTEM76_ORYP8 - default "Gazelle" + default "Gazelle" if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B config MAINBOARD_VERSION default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050 diff --git a/src/mainboard/system76/tgl-h/Makefile.mk b/src/mainboard/system76/tgl-h/Makefile.mk index 7debd0d8c9c..f2fda437b57 100644 --- a/src/mainboard/system76/tgl-h/Makefile.mk +++ b/src/mainboard/system76/tgl-h/Makefile.mk @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/tgl-h/acpi/mainboard.asl b/src/mainboard/system76/tgl-h/acpi/mainboard.asl index c982a9ee4cb..1cf2a28bcad 100644 --- a/src/mainboard/system76/tgl-h/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-h/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +10,8 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Scope (PEG1) { + #include + } } } diff --git a/src/mainboard/system76/tgl-h/board-gbe.fmd b/src/mainboard/system76/tgl-h/board-gbe.fmd index 2bfb31c7527..20d5a7fa018 100644 --- a/src/mainboard/system76/tgl-h/board-gbe.fmd +++ b/src/mainboard/system76/tgl-h/board-gbe.fmd @@ -4,7 +4,7 @@ FLASH 16M { SI_ME 5108K SI_BIOS 11M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/tgl-h/board.fmd b/src/mainboard/system76/tgl-h/board.fmd index 6f3a0381d15..b656073c9d4 100644 --- a/src/mainboard/system76/tgl-h/board.fmd +++ b/src/mainboard/system76/tgl-h/board.fmd @@ -3,7 +3,7 @@ FLASH 16M { SI_ME 5116K SI_BIOS 11M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/tgl-h/bootblock.c b/src/mainboard/system76/tgl-h/bootblock.c index 0dc25dd200b..b351fbd8ef6 100644 --- a/src/mainboard/system76/tgl-h/bootblock.c +++ b/src/mainboard/system76/tgl-h/bootblock.c @@ -3,7 +3,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); } diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 2bda9dc0373..222d412ae73 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/tigerlake # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/tigerlake/fsp_params.c) # Acoustic settings @@ -79,7 +79,6 @@ chip soc/intel/tigerlake # Actual device tree device domain 0 on #From CPU EDS(575683) - device ref system_agent on end device ref igpu on # DDIA is eDP register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -139,11 +138,9 @@ chip soc/intel/tigerlake end end device ref p2sb on end - device ref pmc hidden end device ref hda on register "PchHdaAudioLinkHdaEnable" = "1" end device ref smbus on end - device ref fast_spi on end end end diff --git a/src/mainboard/system76/tgl-h/include/variant/gpio.h b/src/mainboard/system76/tgl-h/include/variant/gpio.h deleted file mode 100644 index 95d576294f6..00000000000 --- a/src/mainboard/system76/tgl-h/include/variant/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -void variant_configure_early_gpios(void); -void variant_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/tgl-h/romstage.c b/src/mainboard/system76/tgl-h/romstage.c index f69bae98eb1..e3d77061eeb 100644 --- a/src/mainboard/system76/tgl-h/romstage.c +++ b/src/mainboard/system76/tgl-h/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include #include static const struct mb_cfg board_cfg = { @@ -21,9 +23,22 @@ static const struct mem_spd spd_info = { void mainboard_memory_init_params(FSPM_UPD *mupd) { - variant_memory_init_params(mupd); - const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + variant_memory_init_params(mupd); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c index 60b82de86fc..f949e34649e 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c @@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_K ------- */ PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM PAD_NC(GPP_K1, NONE), - PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_K3, NONE), PAD_NC(GPP_K4, NONE), PAD_NC(GPP_K5, NONE), diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c index 8c97e7f45ea..8d8943c6d04 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c @@ -6,9 +6,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c index e5804fa5117..122f4701454 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x15585017, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x15585017), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -27,4 +23,16 @@ const u32 pc_beep_verbs[] = { 0x02040202, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x15585017, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h new file mode 100644 index 00000000000..42b7cd86044 --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_K2 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x50151558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index 8382c084a81..63783d73b12 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -8,15 +8,11 @@ chip soc/intel/tigerlake # PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU) register "PcieClkSrcUsage[0]" = "0x42" register "PcieClkSrcClkReq[0]" = "0" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "0" # GFX_CLKREQ0# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref igpu on diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c index ac14b64bf30..5af145a66be 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c @@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_K ------- */ PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM PAD_NC(GPP_K1, NONE), - PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_K3, NONE), PAD_NC(GPP_K4, NONE), PAD_NC(GPP_K5, NONE), diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c index 8c97e7f45ea..8d8943c6d04 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c @@ -6,9 +6,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c index 3399a2d02c1..f0bc5fed291 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC256 */ - 0x10ec0256, /* Vendor ID */ - 0x155850e2, /* Subsystem ID */ - 12, /* Number of entries */ +static const u32 realtek_alc256_verbs[] = { AZALIA_SUBVENDOR(0, 0x155850e2), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -21,6 +17,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC256", + .vendor_id = 0x10ec0256, + .subsystem_id = 0x155850e2, + .address = 0, + .verbs = realtek_alc256_verbs, + .verb_count = ARRAY_SIZE(realtek_alc256_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h new file mode 100644 index 00000000000..1d89884aa1c --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_K2 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x50e11558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index 2915989eeff..60816d571fd 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -8,15 +8,11 @@ chip soc/intel/tigerlake # PCIe PEG1 x16, Clock 9 (DGPU) register "PcieClkSrcUsage[9]" = "0x41" register "PcieClkSrcClkReq[9]" = "9" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "9" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref igpu on diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/gpio.c b/src/mainboard/system76/tgl-h/variants/oryp8/gpio.c index fec0fa8b260..9d1d87e68b7 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/gpio.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/gpio.c @@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_K ------- */ PAD_CFG_GPO(GPP_K0, 0, DEEP), // OVRM PAD_NC(GPP_K1, NONE), - PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_K3, NONE), PAD_NC(GPP_K4, NONE), PAD_NC(GPP_K5, NONE), diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c b/src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c index a15c4866dbf..8d8943c6d04 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c @@ -6,9 +6,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R }; void variant_configure_early_gpios(void) diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c b/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c index 2cdfe5d1992..7997d2454e4 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC1220 */ - 0x10ec1220, /* Vendor ID */ - 0x155865f1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc1220_verbs[] = { AZALIA_SUBVENDOR(0, 0x155865f1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -28,4 +24,16 @@ const u32 pc_beep_verbs[] = { 0x02042a6a, }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC1220", + .vendor_id = 0x10ec1220, + .subsystem_id = 0x155865f1, + .address = 0, + .verbs = realtek_alc1220_verbs, + .verb_count = ARRAY_SIZE(realtek_alc1220_verbs), + }, + { /* terminator */ } +}; + AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h new file mode 100644 index 00000000000..7afe3db4c1c --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_PWRGD GPP_K2 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x65f11558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 331fe179a70..5cee4eff906 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -21,15 +21,11 @@ chip soc/intel/tigerlake # PCIe PEG1 x16, Clock 9 (DGPU) register "PcieClkSrcUsage[9]" = "0x41" register "PcieClkSrcClkReq[9]" = "9" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "9" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref peg0 on diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig index 56f516ff0a3..b3a0e0dd36b 100644 --- a/src/mainboard/system76/tgl-u/Kconfig +++ b/src/mainboard/system76/tgl-u/Kconfig @@ -1,10 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE +config BOARD_SYSTEM76_TGL_U_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL @@ -13,11 +10,10 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC - select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_GALP5 + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE - select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP10 select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MEMORY_MAPPED_TPM @@ -31,6 +27,20 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_MEASURED_BOOT +config BOARD_SYSTEM76_DARP7 + select BOARD_SYSTEM76_TGL_U_COMMON + +config BOARD_SYSTEM76_GALP5 + select BOARD_SYSTEM76_TGL_U_COMMON + select DRIVERS_GFX_NVIDIA + select EC_SYSTEM76_EC_DGPU + +config BOARD_SYSTEM76_LEMP10 + select BOARD_SYSTEM76_TGL_U_COMMON + select HAVE_SPD_IN_CBFS + +if BOARD_SYSTEM76_TGL_U_COMMON + config MAINBOARD_DIR default "system76/tgl-u" @@ -73,4 +83,15 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n +# For galp5 with dGPU +if DRIVERS_GFX_NVIDIA + +config ONBOARD_VGA_IS_PRIMARY + default y + +config DRIVERS_GFX_NVIDIA_BRIDGE + default 0x1c + +endif # DRIVERS_GFX_NVIDIA + endif diff --git a/src/mainboard/system76/tgl-u/acpi/mainboard.asl b/src/mainboard/system76/tgl-u/acpi/mainboard.asl index c982a9ee4cb..6adceba1fdd 100644 --- a/src/mainboard/system76/tgl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-u/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(BOARD_SYSTEM76_GALP5) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" +#if CONFIG(BOARD_SYSTEM76_GALP5) + Scope (RP01) { // Remapped from RP05 + #include + } +#endif } } diff --git a/src/mainboard/system76/tgl-u/board.fmd b/src/mainboard/system76/tgl-u/board.fmd index 6f3a0381d15..b656073c9d4 100644 --- a/src/mainboard/system76/tgl-u/board.fmd +++ b/src/mainboard/system76/tgl-u/board.fmd @@ -3,7 +3,7 @@ FLASH 16M { SI_ME 5116K SI_BIOS 11M { RW_MRC_CACHE 64K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 512K WP_RO { FMAP 4K COREBOOT(CBFS) diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index 94b59701652..f0bdcaf77bb 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/tigerlake # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # System Agent dynamic frequency support register "SaGv" = "SaGv_Enabled" @@ -66,7 +66,6 @@ chip soc/intel/tigerlake # Actual device tree device domain 0 on - device ref system_agent on end device ref igpu on # DDIA is eDP register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -134,6 +133,5 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkHdaEnable" = "1" end device ref smbus on end - device ref fast_spi on end end end diff --git a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c index bcb14c6b629..858a4c979f4 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x155851a1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x155851a1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -22,6 +18,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x155851a1, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c index 7b8e850d8f0..3eeaefe344f 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c @@ -95,7 +95,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_D0, NONE, DEEP), // DGPU_SELECT# PAD_CFG_GPO(GPP_D1, 1, PLTRST), // GPU_EVENT# PAD_CFG_GPI(GPP_D2, NONE, PLTRST), // GC6_FB_EN_PCH - PAD_CFG_GPI(GPP_D3, NONE, PLTRST), // DGPU_PWRGD_R + //PAD_CFG_GPI(GPP_D3, NONE, DEEP), // DGPU_PWRGD_R PAD_NC(GPP_D4, NONE), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD1_CLKREQ# PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // WLAN_CLKREQ# diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c index e2eb8483b36..719f4185fc7 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c @@ -6,6 +6,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + + PAD_CFG_GPI(GPP_D3, NONE, DEEP), // DGPU_PWRGD_R PAD_CFG_GPO(GPP_U4, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN }; diff --git a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c index bf192c0b578..95646d8b590 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15584018, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15584018), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -22,6 +18,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15584018, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h b/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h index 29a4dd22b8e..82f14644dbe 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h +++ b/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h @@ -7,6 +7,7 @@ #define DGPU_RST_N GPP_U4 #define DGPU_PWR_EN GPP_U5 +#define DGPU_PWRGD GPP_D3 #define DGPU_GC6 GPP_D2 #define DGPU_SSID 0x40181558 diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 2d5dc150d68..afceaa10239 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -147,15 +147,11 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "2" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref pcie_rp9 on diff --git a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c index eb4fd3974bb..ee739302f58 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -18,5 +19,18 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .power_good_gpio = DGPU_PWRGD, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c index 52fbda572a8..0dfb2edc99c 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek, ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x155814a1, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x155814a1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -22,6 +18,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x155814a1, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig index cacf252cd94..c570d8bcbc2 100644 --- a/src/mainboard/system76/whl-u/Kconfig +++ b/src/mainboard/system76/whl-u/Kconfig @@ -1,10 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_SYSTEM76_GALP3_C || BOARD_SYSTEM76_DARP5 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select AZALIA_USE_LEGACY_VERB_TABLE +config BOARD_SYSTEM76_WHL_U_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID @@ -27,6 +24,14 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_MEASURED_BOOT +config BOARD_SYSTEM76_GALP3_C + select BOARD_SYSTEM76_WHL_U_COMMON + +config BOARD_SYSTEM76_DARP5 + select BOARD_SYSTEM76_WHL_U_COMMON + +if BOARD_SYSTEM76_WHL_U_COMMON + config MAINBOARD_DIR default "system76/whl-u" diff --git a/src/mainboard/system76/whl-u/Makefile.mk b/src/mainboard/system76/whl-u/Makefile.mk index bf3828de968..4decebf6adf 100644 --- a/src/mainboard/system76/whl-u/Makefile.mk +++ b/src/mainboard/system76/whl-u/Makefile.mk @@ -3,8 +3,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += ramstage.c -ramstage-y += gpio.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 68d1c217838..0fd814879b2 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -22,7 +22,7 @@ chip soc/intel/cannonlake # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O @@ -123,10 +123,9 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device ref lpc_espi on - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x00fc0e01" - register "gen4_dec" = "0x00fc0f01" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/whl-u/gpio.c b/src/mainboard/system76/whl-u/variants/darp5/gpio.c similarity index 100% rename from src/mainboard/system76/whl-u/gpio.c rename to src/mainboard/system76/whl-u/variants/darp5/gpio.c diff --git a/src/mainboard/system76/whl-u/variants/darp5/gpio_early.c b/src/mainboard/system76/whl-u/variants/darp5/gpio_early.c new file mode 100644 index 00000000000..80f37c65535 --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/darp5/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c index 89cbd72bc12..345955674ae 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15581325, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581325), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), @@ -20,17 +16,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1e, 0x02451130), +}; - /* Intel GPU HDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +static const u32 intel_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15581325, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/gpio.c b/src/mainboard/system76/whl-u/variants/galp3-c/gpio.c new file mode 100644 index 00000000000..ca546378e5c --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/galp3-c/gpio.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPI(GPD0, NONE, DEEP), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_NC(GPD7, NONE), // 100k pull up + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, DEEP), // GPD9_RTD3 on galp3-c, NC on darp5 + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up + PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), // 10k pull up + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_NC(GPP_A14, NONE), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK + PAD_NC(GPP_A16, NONE), + PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET# + PAD_NC(GPP_A18, NONE), + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW + PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, NONE), // CORE_VID0 + PAD_NC(GPP_B1, NONE), // CORE_VID1 + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // T16 on galp3-c, NO REBOOT STRAP on darp5 + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), // 20k pull down on galp3-c, T14 on darp5 + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR + PAD_NC(GPP_C2, NONE), // 4.7k pull-up + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPI(GPP_C5, NONE, DEEP), // 4.7k pull down on galp3-c, WLAN_WAKEUP# on darp5 + PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP# on galp3-c, NC on darp5 + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), // TBCIO_PLUG_EVENT + PAD_CFG_GPO(GPP_C10, 1, PLTRST), // TBT_FRC_PWR + PAD_NC(GPP_C11, NONE), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3 + PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN# + PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET + PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL + PAD_NC(GPP_C18, NONE), + PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI# on galp3-c, NC on darp5 + //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp3-c, TP_ATTN# on darp5 + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON + PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), // SWI# + PAD_NC(GPP_D10, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D11, UP_20K, DEEP, LEVEL), // RTD3_PCIE_WAKE# + PAD_NC(GPP_D12, NONE), // 100k pull up on galp3-c, NC on darp5 + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA + PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET# + PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 10k pull up + PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2 + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2 + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), // USB_OC#78 + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), // SMI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI# + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET on galp3-c, NC on darp5 + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0 on galp3-c, NC on darp5 + PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1 on galp3-c, NC on darp5 + PAD_CFG_GPI(GPP_G5, NONE, DEEP), // BOARD_ID + PAD_NC(GPP_G6, NONE), + PAD_CFG_GPI(GPP_G7, NONE, DEEP), // TBT_Detect + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), // G_INT1 10k pull up + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_CFG_GPI(GPP_H21, NONE, DEEP), // GPPC_H21; LOW: 38.4/19.2M, HI: 24M + PAD_CFG_GPO(GPP_H22, 1, PLTRST), // TBT_RTD3_PWR_EN_R + PAD_CFG_GPI(GPP_H23, NONE, DEEP), // WIGIG_PEWAKE on galp3-c, NC on darp5 +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/gpio_early.c b/src/mainboard/system76/whl-u/variants/galp3-c/gpio_early.c new file mode 100644 index 00000000000..80f37c65535 --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/galp3-c/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c index 451f938e72e..2595285bfa3 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c @@ -2,11 +2,7 @@ #include -const u32 cim_verb_data[] = { - /* Realtek ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15581323, /* Subsystem ID */ - 13, /* Number of entries */ +static const u32 realtek_alc293_verbs[] = { AZALIA_SUBVENDOR(0, 0x15581323), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), @@ -20,17 +16,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738205), AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +}; - /* Intel GPU HDMI */ - 0x8086280b, /* Vendor ID */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of entries */ +static const u32 intel_hdmi_verbs[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), AZALIA_PIN_CFG(2, 0x06, 0x18560010), AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC293", + .vendor_id = 0x10ec0293, + .subsystem_id = 0x15581323, + .address = 0, + .verbs = realtek_alc293_verbs, + .verb_count = ARRAY_SIZE(realtek_alc293_verbs), + }, + { + .name = "Intel Kabylake HDMI", + .vendor_id = 0x8086280b, + .subsystem_id = 0x80860101, + .address = 2, + .verbs = intel_hdmi_verbs, + .verb_count = ARRAY_SIZE(intel_hdmi_verbs), + }, + { /* terminator */ } +}; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/topton/adl/gpio.h b/src/mainboard/topton/adl/gpio.h index ffc528c5753..c45c2e9d4eb 100644 --- a/src/mainboard/topton/adl/gpio.h +++ b/src/mainboard/topton/adl/gpio.h @@ -5,317 +5,107 @@ #include -/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ - - /* ------- GPIO Group GPP_B ------- */ - _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* VRALERT# */ - PAD_NC(GPP_B3, NONE), /* GPIO */ - PAD_NC(GPP_B4, NONE), /* GPIO */ - PAD_NC(GPP_B5, NONE), /* GPIO */ - PAD_NC(GPP_B6, NONE), /* GPIO */ - PAD_NC(GPP_B7, NONE), /* GPIO */ - PAD_NC(GPP_B8, NONE), /* GPIO */ - PAD_NC(GPP_B9, NONE), /* GPIO */ - PAD_NC(GPP_B10, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PMCALERT# */ - _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* SLP_S0# */ - _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* PLTRST# */ - _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SPKR */ - PAD_NC(GPP_B15, NONE), /* GPIO */ - PAD_NC(GPP_B16, NONE), /* GPIO */ - PAD_NC(GPP_B17, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ - PAD_NC(GPP_B19, NONE), /* GPIO */ - PAD_NC(GPP_B20, NONE), /* GPIO */ - PAD_NC(GPP_B21, NONE), /* GPIO */ - PAD_NC(GPP_B22, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI0_CLK_LOOPBK */ - _PAD_CFG_STRUCT(GPP_B25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_CLK_LOOPBK */ - - /* ------- GPIO Group GPP_T ------- */ - PAD_NC(GPP_T0, NONE), /* GPIO */ - PAD_NC(GPP_T1, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_T2, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* FUSA_DIAGTEST_EN */ - _PAD_CFG_STRUCT(GPP_T3, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* FUSA_DIAGTEST_MODE */ - PAD_NC(GPP_T4, NONE), /* GPIO */ - PAD_NC(GPP_T5, NONE), /* GPIO */ - PAD_NC(GPP_T6, NONE), /* GPIO */ - PAD_NC(GPP_T7, NONE), /* GPIO */ - PAD_NC(GPP_T8, NONE), /* GPIO */ - PAD_NC(GPP_T9, NONE), /* GPIO */ - PAD_NC(GPP_T10, NONE), /* GPIO */ - PAD_NC(GPP_T11, NONE), /* GPIO */ - PAD_NC(GPP_T12, NONE), /* GPIO */ - PAD_NC(GPP_T13, NONE), /* GPIO */ - PAD_NC(GPP_T14, NONE), /* GPIO */ - PAD_NC(GPP_T15, NONE), /* GPIO */ - /* ------- GPIO Group GPP_A ------- */ - _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO0 */ - _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO1 */ - _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO2 */ - _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO3 */ - _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_CS0# */ - _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* ESPI_ALERT0# */ - _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* ESPI_ALERT1# */ - PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_A8, 0, PLTRST), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_CLK */ - _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* ESPI_RESET# */ - PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */ - PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* USB_OC1# */ - _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* USB_OC3# */ - PAD_NC(GPP_A17, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), /* DDSP_HPDB */ - _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD1 */ - PAD_NC(GPP_A20, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_A22, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_CS1# */ - _PAD_CFG_STRUCT(GPP_ESPI_CLK_LOOPBK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GPP_ESPI_CLK_LOOPBK */ - - /* ------- GPIO Community 1 ------- */ - - /* ------- GPIO Group GPP_S ------- */ - PAD_NC(GPP_S0, NONE), /* GPIO */ - PAD_NC(GPP_S1, NONE), /* GPIO */ - PAD_NC(GPP_S2, NONE), /* GPIO */ - PAD_NC(GPP_S3, NONE), /* GPIO */ - PAD_NC(GPP_S4, NONE), /* GPIO */ - PAD_NC(GPP_S5, NONE), /* GPIO */ - PAD_NC(GPP_S6, NONE), /* GPIO */ - PAD_NC(GPP_S7, NONE), /* GPIO */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1), // eSPI_IO 0 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1), // eSPI_IO 1 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1), // eSPI IO 2 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1), // eSPI IO 3 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1), // eSPI CS 0 + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // eSPI Alert 0 + PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), // eSPI Alert 1 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, DN_20K, DEEP, NF1), // eSPI CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1), // eSPI RST + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A23, UP_20K, DEEP, NF1), // eSPI CS 1 + PAD_CFG_GPO(GPP_A7, 1, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_A8, 0, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_A11, 1, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_A13, 1, DEEP), // Unknown GPIO + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAXPCIE1 + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // USB OC1 (?) + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB OC3 (?) + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // DDI-B HPD + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), // DDI-1 HPD - /* ------- GPIO Group GPP_I ------- */ - PAD_NC(GPP_I0, NONE), /* GPIO */ - PAD_NC(GPP_I1, NONE), /* GPIO */ - PAD_NC(GPP_I2, NONE), /* GPIO */ - PAD_NC(GPP_I3, NONE), /* GPIO */ - PAD_NC(GPP_I4, NONE), /* GPIO */ - PAD_NC(GPP_I5, NONE), /* GPIO */ - PAD_NC(GPP_I6, NONE), /* GPIO */ - PAD_NC(GPP_I7, NONE), /* GPIO */ - PAD_NC(GPP_I8, NONE), /* GPIO */ - PAD_NC(GPP_I9, NONE), /* GPIO */ - PAD_NC(GPP_I10, NONE), /* GPIO */ - PAD_NC(GPP_I11, NONE), /* GPIO */ - PAD_NC(GPP_I12, NONE), /* GPIO */ - PAD_NC(GPP_I13, NONE), /* GPIO */ - PAD_NC(GPP_I14, NONE), /* GPIO */ - PAD_NC(GPP_I15, NONE), /* GPIO */ - PAD_NC(GPP_I16, NONE), /* GPIO */ - PAD_NC(GPP_I17, NONE), /* GPIO */ - PAD_NC(GPP_I18, NONE), /* GPIO */ - PAD_NC(GPP_I19, NONE), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1 + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), // PMCALERT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0 + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), // PC_SPKR + PAD_CFG_GPO(GPP_B18, 0, PLTRST), // Unknown GPIO + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), // PROCHOT - /* ------- GPIO Group GPP_H ------- */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - PAD_NC(GPP_H4, NONE), /* GPIO */ - PAD_NC(GPP_H5, NONE), /* GPIO */ - PAD_NC(GPP_H6, NONE), /* GPIO */ - PAD_NC(GPP_H7, NONE), /* GPIO */ - PAD_NC(GPP_H8, NONE), /* GPIO */ - PAD_NC(GPP_H9, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), /* UART0_RXD */ - _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSTERM(DISPUPD)), /* UART0_TXD */ - PAD_NC(GPP_H12, NONE), /* GPIO */ - PAD_NC(GPP_H13, NONE), /* GPIO */ - PAD_NC(GPP_H14, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* DDPB_CTRLCLK */ - PAD_NC(GPP_H16, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* DDPB_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* PROC_C10_GATE# */ - _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ4# */ - PAD_NC(GPP_H20, NONE), /* GPIO */ - PAD_NC(GPP_H21, NONE), /* GPIO */ - PAD_NC(GPP_H22, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ5# */ + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMBus CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMBus DATA + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), // SMBus Alert + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLink 0 CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLink 0 DATA + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // SMLink 0 Alert + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMLink 1 CLK + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMLink 1 DATA /* ------- GPIO Group GPP_D ------- */ - PAD_NC(GPP_D0, NONE), /* GPIO */ - PAD_NC(GPP_D1, NONE), /* GPIO */ - PAD_NC(GPP_D2, NONE), /* GPIO */ - PAD_NC(GPP_D3, NONE), /* GPIO */ - PAD_NC(GPP_D4, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ0# */ - _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ1# */ - _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ2# */ - _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ3# */ - _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS2_RX */ - _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS2_TX */ - _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS3_TX */ - _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - PAD_NC(GPP_D15, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_D17, NONE), /* GPIO */ - PAD_NC(GPP_D18, NONE), /* GPIO */ - PAD_NC(GPP_D19, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_GSPI2_CLK_LOOPBK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GPP_GSPI2_CLK_LOOPBK */ - - /* ------- GPIO Group vGPIO ------- */ - PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), /* GPIO */ - _PAD_CFG_STRUCT(GPP_VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | (1 << 1) | 1, 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_VGPIO_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_6 */ - PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), /* GPP_VGPIO_7 */ - PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), /* GPP_VGPIO_8 */ - _PAD_CFG_STRUCT(GPP_VGPIO_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_9 */ - _PAD_CFG_STRUCT(GPP_VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_10 */ - PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), /* GPP_VGPIO_11 */ - PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), /* GPP_VGPIO_12 */ - _PAD_CFG_STRUCT(GPP_VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_13 */ - _PAD_CFG_STRUCT(GPP_VGPIO_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_18 */ - PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), /* GPP_VGPIO_19 */ - PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), /* GPP_VGPIO_20 */ - PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), /* GPP_VGPIO_21 */ - _PAD_CFG_STRUCT(GPP_VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_22 */ - PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), /* GPP_VGPIO_23 */ - PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), /* GPP_VGPIO_24 */ - _PAD_CFG_STRUCT(GPP_VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_25 */ - PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), /* GPP_VGPIO_30 */ - PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), /* GPP_VGPIO_31 */ - PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), /* GPP_VGPIO_32 */ - PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), /* GPP_VGPIO_33 */ - PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* GPP_VGPIO_34 */ - PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* GPP_VGPIO_35 */ - PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* GPP_VGPIO_36 */ - PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* GPP_VGPIO_37 */ - - /* ------- GPIO Community 2 ------- */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SRCCLKREQ0 + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SRCCLKREQ1 + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // SRCCLKREQ2 + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // SRCCLKREQ3 + PAD_CFG_GPO(GPP_D16, 1, PLTRST), // Unknown GPIO - /* ------- GPIO Group GPP_GPD ------- */ - _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* BATLOW# */ - _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* ACPRESENT */ - _PAD_CFG_STRUCT(GPD2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* PWRBTN# */ - _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S3# */ - _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S4# */ - _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ - PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ - _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ - _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_WLAN# */ - _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S5# */ - PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ - _PAD_CFG_STRUCT(GPD_INPUT3VSEL, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_INPUT3VSEL */ - _PAD_CFG_STRUCT(GPD_SLP_LANB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_SLP_LANB */ - _PAD_CFG_STRUCT(GPD_SLP_SUSB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_SLP_SUSB */ - _PAD_CFG_STRUCT(GPD_WAKEB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* GPD_WAKEB */ - _PAD_CFG_STRUCT(GPD_DRAM_RESETB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_DRAM_RESETB */ - - /* ------- GPIO Community 4 ------- */ - - /* ------- GPIO Group GPP_C ------- */ - _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* SMBCLK */ - _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* SMBDATA */ - PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */ - _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */ - PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1CLK */ - _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1DATA */ - PAD_NC(GPP_C8, NONE), /* GPIO */ - PAD_NC(GPP_C9, NONE), /* GPIO */ - PAD_NC(GPP_C10, NONE), /* GPIO */ - PAD_NC(GPP_C11, NONE), /* GPIO */ - PAD_NC(GPP_C12, NONE), /* GPIO */ - PAD_NC(GPP_C13, NONE), /* GPIO */ - PAD_NC(GPP_C14, NONE), /* GPIO */ - PAD_NC(GPP_C15, NONE), /* GPIO */ - PAD_NC(GPP_C16, NONE), /* GPIO */ - PAD_NC(GPP_C17, NONE), /* GPIO */ - PAD_NC(GPP_C18, NONE), /* GPIO */ - PAD_NC(GPP_C19, NONE), /* GPIO */ - PAD_NC(GPP_C20, NONE), /* GPIO */ - PAD_NC(GPP_C21, NONE), /* GPIO */ - PAD_NC(GPP_C22, NONE), /* GPIO */ - PAD_NC(GPP_C23, NONE), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), // Unknown GPIO + PAD_CFG_GPO(GPP_E4, 1, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_E6, 0, DEEP), // Unknown GPIO + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // DDI-A HPD + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), // DDI-A CLK + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), // DDI-A DATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // DDI-2 CLK + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // DDI-2 DATA /* ------- GPIO Group GPP_F ------- */ - _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_BRI_DT */ - _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */ - _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RGI_DT */ - _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */ - _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RF_RESET# */ - _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* MODEM_CLKREQ */ - PAD_NC(GPP_F6, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ - PAD_NC(GPP_F8, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* BOOTMPC */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_F11, NONE), /* GPIO */ - PAD_NC(GPP_F12, NONE), /* GPIO */ - PAD_NC(GPP_F13, NONE), /* GPIO */ - PAD_NC(GPP_F14, NONE), /* GPIO */ - PAD_NC(GPP_F15, NONE), /* GPIO */ - PAD_NC(GPP_F16, NONE), /* GPIO */ - PAD_NC(GPP_F17, NONE), /* GPIO */ - PAD_NC(GPP_F18, NONE), /* GPIO */ - PAD_NC(GPP_F19, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* Reserved */ - _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* Reserved */ - PAD_NC(GPP_F22, NONE), /* GPIO */ - PAD_NC(GPP_F23, NONE), /* GPIO */ - PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ - - /* ------- GPIO Group GPP_HVCMOS ------- */ - _PAD_CFG_STRUCT(GPP_L_BKLTEN, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ - _PAD_CFG_STRUCT(GPP_L_BKLTCTL, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ - _PAD_CFG_STRUCT(GPP_L_VDDEN, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ - _PAD_CFG_STRUCT(GPP_SYS_PWROK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* n/a */ - _PAD_CFG_STRUCT(GPP_SYS_RESETB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* n/a */ - _PAD_CFG_STRUCT(GPP_MLK_RSTB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNV_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNV_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNV_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNV_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNV_RF_RESET + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // MODEM_CLKREQ + PAD_CFG_GPO(GPP_F7, 0, DEEP), // Unknown GPIO + PAD_CFG_GPO(GPP_F10, 1, PLTRST), // Unknown GPIO - /* ------- GPIO Group GPP_E ------- */ - _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - PAD_NC(GPP_E1, NONE), /* GPIO */ - PAD_NC(GPP_E2, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ - PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_E5, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ - PAD_NC(GPP_E8, NONE), /* GPIO */ - PAD_NC(GPP_E9, NONE), /* GPIO */ - PAD_NC(GPP_E10, NONE), /* GPIO */ - PAD_NC(GPP_E11, NONE), /* GPIO */ - PAD_NC(GPP_E12, NONE), /* GPIO */ - PAD_NC(GPP_E13, NONE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), /* DDSP_HPDA */ - PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ - PAD_NC(GPP_E17, NONE), /* GPIO */ - PAD_NC(GPP_E18, NATIVE), /* GPIO */ - PAD_NC(GPP_E19, NATIVE), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* DDPA_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* DDPA_CTRLDATA */ - PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ - - /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_H1, 1, PLTRST), // Unknown GPIO + PAD_CFG_GPO(GPP_H2, 1, RSMRST), // Unknown GPIO + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RXD + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TXD + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // DDI-B CLK + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // DDI-B DATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // PROC_C10_GATE + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SRCCLKREQ4 + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // SRCCLKREQ5 /* ------- GPIO Group GPP_R ------- */ - _PAD_CFG_STRUCT(GPP_R0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* HDA_BCLK */ - _PAD_CFG_STRUCT(GPP_R1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SYNC */ - _PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SDO */ - _PAD_CFG_STRUCT(GPP_R3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SDI0 */ - _PAD_CFG_STRUCT(GPP_R4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* HDA_RST# */ - PAD_NC(GPP_R5, NONE), /* GPIO */ - PAD_NC(GPP_R6, NONE), /* GPIO */ - PAD_NC(GPP_R7, NONE), /* GPIO */ + PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), // HDA_BCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDO + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDI0 + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), // HDA_RST + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, DEEP, NF1), // BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // ACPRESENT + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWRBTN + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SLP_S3 + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SLP_S4 + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A + PAD_CFG_GPO(GPD7, 1, PLTRST), // Unknown GPIO + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5 + PAD_CFG_NF(GPD11, NATIVE, DEEP, NF1), // LANPHYC }; #endif /* CFG_GPIO_H */ diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index f1d3c66346d..b9d84b3e340 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -88,8 +88,7 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ #define HAS_AGESA_FCH_OEM_CALLOUT \ - CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \ - CONFIG(SOUTHBRIDGE_AMD_PI_KERN) + CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) #if HAS_AGESA_FCH_OEM_CALLOUT /* FIXME: Structures included here were supposed to be private to AGESA. */ diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index c24466efe9c..31b001a423a 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include /* warning: Porting.h includes an open #pragma pack(1) */ diff --git a/src/northbridge/intel/broadwell/Makefile.mk b/src/northbridge/intel/broadwell/Makefile.mk index ce037157e20..7c279da34cc 100644 --- a/src/northbridge/intel/broadwell/Makefile.mk +++ b/src/northbridge/intel/broadwell/Makefile.mk @@ -11,7 +11,6 @@ romstage-y += romstage.c romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c ramstage-y += ../haswell/acpi.c -ramstage-y += finalize.c ramstage-y += gma.c ramstage-y += memmap.c romstage-y += memmap.c diff --git a/src/northbridge/intel/broadwell/early_init.c b/src/northbridge/intel/broadwell/early_init.c index ad700701499..d50c2fc0f30 100644 --- a/src/northbridge/intel/broadwell/early_init.c +++ b/src/northbridge/intel/broadwell/early_init.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c deleted file mode 100644 index d71ac0996d3..00000000000 --- a/src/northbridge/intel/broadwell/finalize.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * 16.6 System Agent Configuration Locking - * "5th Generation Intel Core Processor Family BIOS Specification" - * Document Number 535094 - * Revision 2.2.0, August 2014 - * - * To ease reading, first lock PCI registers, then MCHBAR registers. - * Write the MC Lock register first, since more than one bit gets set. - */ -static void broadwell_systemagent_finalize(void) -{ - struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); - - pci_or_config16(host_bridge, GGC, 1 << 0); - pci_or_config32(host_bridge, DPR, 1 << 0); - pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10); - pci_or_config32(host_bridge, REMAPBASE, 1 << 0); - pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0); - pci_or_config32(host_bridge, TOM, 1 << 0); - pci_or_config32(host_bridge, TOUUD, 1 << 0); - pci_or_config32(host_bridge, BDSM, 1 << 0); - pci_or_config32(host_bridge, BGSM, 1 << 0); - pci_or_config32(host_bridge, TSEG, 1 << 0); - pci_or_config32(host_bridge, TOLUD, 1 << 0); - - mchbar_setbits32(0x50fc, 0x8f); /* MC */ - mchbar_setbits32(0x5500, 1 << 0); /* PAVP */ - mchbar_setbits32(0x5880, 1 << 5); /* DDR PTM */ - mchbar_setbits32(0x7000, 1 << 31); - mchbar_setbits32(0x77fc, 1 << 0); - mchbar_setbits32(0x7ffc, 1 << 0); - mchbar_setbits32(0x6800, 1 << 31); - mchbar_setbits32(0x6020, 1 << 0); /* UMA GFX */ - mchbar_setbits32(0x63fc, 1 << 0); /* VTDTRK */ - - /* Read+write the following */ - mchbar_setbits32(0x6030, 0); - mchbar_setbits32(0x6034, 0); - mchbar_setbits32(0x6008, 0); -} - -static void broadwell_finalize(void *unused) -{ - printk(BIOS_DEBUG, "Finalizing chipset.\n"); - - broadwell_systemagent_finalize(); - - broadwell_pch_finalize(); - - /* Indicate finalize step with post code */ - post_code(POSTCODE_OS_BOOT); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h index de3a33ffa85..ca1dec92dbb 100644 --- a/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h +++ b/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h @@ -4,25 +4,13 @@ #define _BROADWELL_PEI_WRAPPER_H_ #include +#include typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); -static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, uint16_t length, - uint8_t enable, uint8_t oc_pin, uint8_t location) -{ - pei_data->usb2_ports[port].length = length; - pei_data->usb2_ports[port].enable = enable; - pei_data->usb2_ports[port].oc_pin = oc_pin; - pei_data->usb2_ports[port].location = location; -} - -static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, uint8_t enable, - uint8_t oc_pin, uint8_t fixed_eq) -{ - pei_data->usb3_ports[port].enable = enable; - pei_data->usb3_ports[port].oc_pin = oc_pin; - pei_data->usb3_ports[port].fixed_eq = fixed_eq; -} +/* TODO: Should be moved to PCH code */ +extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS]; +extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS]; #define SPD_MEMORY_DOWN 0xff @@ -43,7 +31,6 @@ void mb_get_spd_map(struct spd_info *spdi); const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void); void broadwell_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); void copy_spd(struct pei_data *pei_data, struct spd_info *spdi); diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c index bb45c374a80..f0d36ccffa3 100644 --- a/src/northbridge/intel/broadwell/northbridge.c +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -346,11 +347,51 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } +/* + * 16.6 System Agent Configuration Locking + * "5th Generation Intel Core Processor Family BIOS Specification" + * Document Number 535094 + * Revision 2.2.0, August 2014 + * + * To ease reading, first lock PCI registers, then MCHBAR registers. + * Write the MC Lock register first, since more than one bit gets set. + */ +static void northbridge_final(struct device *dev) +{ + pci_or_config16(dev, GGC, 1 << 0); + pci_or_config32(dev, DPR, 1 << 0); + pci_or_config32(dev, MESEG_LIMIT, 1 << 10); + pci_or_config32(dev, REMAPBASE, 1 << 0); + pci_or_config32(dev, REMAPLIMIT, 1 << 0); + pci_or_config32(dev, TOM, 1 << 0); + pci_or_config32(dev, TOUUD, 1 << 0); + pci_or_config32(dev, BDSM, 1 << 0); + pci_or_config32(dev, BGSM, 1 << 0); + pci_or_config32(dev, TSEG, 1 << 0); + pci_or_config32(dev, TOLUD, 1 << 0); + + mchbar_setbits32(0x50fc, 0x8f); /* MC */ + mchbar_setbits32(0x5500, 1 << 0); /* PAVP */ + mchbar_setbits32(0x5880, 1 << 5); /* DDR PTM */ + mchbar_setbits32(0x7000, 1 << 31); + mchbar_setbits32(0x77fc, 1 << 0); + mchbar_setbits32(0x7ffc, 1 << 0); + mchbar_setbits32(0x6800, 1 << 31); + mchbar_setbits32(0x6020, 1 << 0); /* UMA GFX */ + mchbar_setbits32(0x63fc, 1 << 0); /* VTDTRK */ + + /* Read+write the following */ + mchbar_setbits32(0x6030, 0); + mchbar_setbits32(0x6034, 0); + mchbar_setbits32(0x6008, 0); +} + static struct device_operations systemagent_ops = { .read_resources = systemagent_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = systemagent_init, + .final = northbridge_final, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index fe2002fb1f0..c9e953ea233 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -33,4 +33,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data) pei_data->dq_pins_interleaved = cfg->dq_pins_interleaved, pei_data->tx_byte = &send_to_console; pei_data->ddr_refresh_2x = 1; + + memcpy(pei_data->usb2_ports, mainboard_usb2_ports, sizeof(pei_data->usb2_ports)); + memcpy(pei_data->usb3_ports, mainboard_usb3_ports, sizeof(pei_data->usb3_ports)); } diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index d8ed97fdd19..1c9ffabee86 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -184,8 +183,6 @@ void perform_raminit(const struct chipset_power_state *const power_state) struct pei_data pei_data = { 0 }; - mainboard_fill_pei_data(&pei_data); - if (CONFIG(BROADWELL_LPDDR3)) { const struct lpddr3_dq_dqs_map *lpddr3_map = mb_get_lpddr3_dq_dqs_map(); assert(lpddr3_map); diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 0497aa9bb44..fad8ee7421d 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -44,7 +44,6 @@ void broadwell_run_reference_code(void) struct pei_data pei_data; memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); broadwell_fill_pei_data(&pei_data); pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0; diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index 2f42fd0159e..b301bf8db69 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -5,10 +5,11 @@ #include #include #include -#include +#include #include #include #include +#include #include __weak void mainboard_post_raminit(const bool s3resume) @@ -43,7 +44,7 @@ void mainboard_romstage_entry(void) setup_pch_lp_gpios(mainboard_lp_gpio_map); /* Print ME state before MRC */ - intel_me_status(); + intel_early_me_status(); /* Save ME HSIO version */ intel_me_hsio_version(&power_state->hsio_version, &power_state->hsio_checksum); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 444ab162ff9..54b3243b7cf 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -12,7 +12,6 @@ */ #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 70f0736a8ad..4925f991559 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -25,13 +25,13 @@ static unsigned long acpi_fill_dmar(unsigned long current) PCI_CLASS_REVISION); unsigned long tmp = current; - current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE_VC1); current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0); acpi_dmar_drhd_fixup(tmp, current); if (stepping != STEPPING_B2 && igd_active) { tmp = current; - current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE_GFX); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -39,7 +39,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) if (me_active) { tmp = current; - current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE3); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE_ME); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2); @@ -47,7 +47,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE_VC0); /* TODO: reserve GTT for 0.2.0 and 0.2.1? */ return current; diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index f68bfdee7ab..90ab5705244 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -441,7 +441,7 @@ void mb_pre_raminit_setup(sysinfo_t *); /* optional */ void mb_post_raminit_setup(void); /* optional */ struct blc_pwm_t { - char ascii_string[13]; + char __nonstring ascii_string[13]; int pwm_freq; /* In Hz */ }; int get_blc_values(const struct blc_pwm_t **entries); diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 7b0b1e56994..05f808b15f7 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 6a68dff13a0..2349de2eca0 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -7,27 +7,32 @@ #include "gm45.h" +#define MEREMAPBAR 0x10 +#define GFXREMAPBAR 0x18 +#define VC0REMAPBAR 0x20 +#define VC1REMAPBAR 0x28 + void init_iommu(void) { /* FIXME: proper test? */ int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); - mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */ + mchbar_write32(VC1REMAPBAR, IOMMU_BASE_VC1 | 1); /* HDA @ 0:1b.0 */ if (stepping != STEPPING_B2) { /* The official workaround is to run SMM every 64ms. The only winning move is not to play. */ - mchbar_write32(0x18, IOMMU_BASE2 | 1); /* IGD @ 0:2.0-1 */ + mchbar_write32(GFXREMAPBAR, IOMMU_BASE_GFX | 1); /* IGD @ 0:2.0-1 */ } else { /* write-once, so lock it down */ - mchbar_write32(0x18, 0); /* disable IOMMU for IGD @ 0:2.0-1 */ + mchbar_write32(GFXREMAPBAR, 0); /* disable IOMMU for IGD @ 0:2.0-1 */ } if (me_active) { - mchbar_write32(0x10, IOMMU_BASE3 | 1); /* ME @ 0:3.0-3 */ + mchbar_write32(MEREMAPBAR, IOMMU_BASE_ME | 1); /* ME @ 0:3.0-3 */ } else { - mchbar_write32(0x10, 0); /* disable IOMMU for ME */ + mchbar_write32(MEREMAPBAR, 0); /* disable IOMMU for ME */ } - mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */ + mchbar_write32(VC0REMAPBAR, IOMMU_BASE_VC0 | 1); /* all other DMA sources */ if (stepping == STEPPING_B3) { mchbar_setbits8(0xffc, 1 << 4); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index e2ba5542ea3..f6f33f18484 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/memmap.h b/src/northbridge/intel/gm45/memmap.h index e582aa01104..be289e17879 100644 --- a/src/northbridge/intel/gm45/memmap.h +++ b/src/northbridge/intel/gm45/memmap.h @@ -3,9 +3,9 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#define IOMMU_BASE_VC1 0xfed90000 +#define IOMMU_BASE_GFX 0xfed91000 +#define IOMMU_BASE_ME 0xfed92000 +#define IOMMU_BASE_VC0 0xfed93000 #endif /* __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 59a49929d7b..958de899f5a 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 656a6326395..1f78fe63120 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 2e3a97b6e9d..8a313611158 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "gm45.h" diff --git a/src/northbridge/intel/gm965/Kconfig b/src/northbridge/intel/gm965/Kconfig new file mode 100644 index 00000000000..342520999aa --- /dev/null +++ b/src/northbridge/intel/gm965/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_INTEL_GM965 + bool + select HAVE_DEBUG_RAM_SETUP + select VGA + select INTEL_EDID + select INTEL_GMA_ACPI + select INTEL_GMA_SSC_ALTERNATE_REF + select DRAM_SUPPORT_DDR2 + select HAVE_X86_64_SUPPORT + select NEED_SMALL_2MB_PAGE_TABLES + select CACHE_MRC_SETTINGS + +if NORTHBRIDGE_INTEL_GM965 + +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + +config CBFS_SIZE + default 0x100000 + +config VGA_BIOS_ID + string + default "8086,2a02" + +config ECAM_MMCONF_BASE_ADDRESS + default 0xe0000000 + +config ECAM_MMCONF_BUS_NUMBER + default 64 + +config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config MAX_CPUS + int + default 4 + +config INTEL_GMA_BCLV_OFFSET + default 0x61254 + +config INTEL_GMA_BCLM_OFFSET + default 0x61256 + +config FIXED_MCHBAR_MMIO_BASE + default 0xfed14000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + +endif diff --git a/src/northbridge/intel/gm965/Makefile.mk b/src/northbridge/intel/gm965/Makefile.mk new file mode 100644 index 00000000000..9395d3451f9 --- /dev/null +++ b/src/northbridge/intel/gm965/Makefile.mk @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM965),y) + +bootblock-y += bootblock.c + +romstage-y += early_init.c +romstage-y += raminit.c +romstage-y += raminit_receive_enable_calibration.c +romstage-y += raminit_meminfo.c +romstage-y += dmi.c +romstage-y += thermal.c +romstage-y += pm.c +romstage-y += igd.c +romstage-y += romstage.c +romstage-y += memmap.c + +ramstage-y += acpi.c +ramstage-y += gma.c +ramstage-y += memmap.c +ramstage-y += northbridge.c +ramstage-y += pcie.c + +postcar-y += memmap.c + +endif diff --git a/src/northbridge/intel/gm965/acpi.c b/src/northbridge/intel/gm965/acpi.c new file mode 100644 index 00000000000..af4bfb0b3cd --- /dev/null +++ b/src/northbridge/intel/gm965/acpi.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "gm965.h" + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long start, + struct acpi_rsdp *rsdp) +{ + /* GM965 (Crestline) does not support VT-d, so no DMAR table. */ + return start; +} diff --git a/src/northbridge/intel/gm965/acpi/gm965.asl b/src/northbridge/intel/gm965/acpi/gm965.asl new file mode 100644 index 00000000000..29abbcf90d2 --- /dev/null +++ b/src/northbridge/intel/gm965/acpi/gm965.asl @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "hostbridge.asl" +#include + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + // This does not seem to work correctly yet - set values statically for + // now. + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// PCIe graphics port 0:1.0 +#include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/gm965/acpi/hostbridge.asl b/src/northbridge/intel/gm965/acpi/hostbridge.asl new file mode 100644 index 00000000000..0047e19b2ae --- /dev/null +++ b/src/northbridge/intel/gm965/acpi/hostbridge.asl @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) /* 0:0.0 */ + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), /* EPBAR */ + EPEN, 1, /* Enable */ + , 11, + EPBR, 24, /* EPBAR */ + + Offset (0x48), /* MCHBAR */ + MHEN, 1, /* Enable */ + , 13, + MHBR, 22, /* MCHBAR */ + + Offset (0x60), /* PCIec BAR */ + PXEN, 1, /* Enable */ + PXSZ, 2, /* BAR size */ + , 23, + PXBR, 10, /* PCIe BAR */ + + Offset (0x68), /* DMIBAR */ + DMEN, 1, /* Enable */ + , 11, + DMBR, 24, /* DMIBAR */ + + /* ... */ + + Offset (0x90), /* PAM0 */ + , 4, + PM0H, 2, + , 2, + Offset (0x91), /* PAM1 */ + PM1L, 2, + , 2, + PM1H, 2, + , 2, + Offset (0x92), /* PAM2 */ + PM2L, 2, + , 2, + PM2H, 2, + , 2, + Offset (0x93), /* PAM3 */ + PM3L, 2, + , 2, + PM3H, 2, + , 2, + Offset (0x94), /* PAM4 */ + PM4L, 2, + , 2, + PM4H, 2, + , 2, + Offset (0x95), /* PAM5 */ + PM5L, 2, + , 2, + PM5H, 2, + , 2, + Offset (0x96), /* PAM6 */ + PM6L, 2, + , 2, + PM6H, 2, + , 2, + + Offset (0xa0), /* Top of Memory */ + TOM, 8, + + Offset (0xb0), /* Top of Low Used Memory */ + , 4, + TLUD, 12, + } +} + +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers. Highest bus and length get updated later */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, 0, 255, 0, 256,,, PB00) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + /* PCI Memory Region (Top of memory-0xfebfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + /* PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM02) + + /* TPM Area (0xfed40000-0xfed44fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) + +External (A4GS, IntObj) +External (A4GB, IntObj) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + /* Set highest PCI bus and length */ + CreateWordField(MCRS, ^PB00._MAX, BMAX) + CreateWordField(MCRS, ^PB00._LEN, BLEN) + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + BMAX = BLEN - 1 + + /* Find PCI resource area in MCRS */ + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) + + /* + * Fix up PCI memory region: + * Enter actual TOLUD. The TOLUD register contains bits 20-31 of + * the top of memory address. + */ + PMIN = ^MCHC.TLUD << 20 + PLEN = PMAX - PMIN + 1 + + if (A4GS != 0) { + CreateQwordField(MCRS, ^PM02._MIN, MMIN) + CreateQwordField(MCRS, ^PM02._MAX, MMAX) + CreateQwordField(MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + MLEN = A4GS + MMIN = A4GB + MMAX = MMIN + MLEN - 1 + } + + Return (MCRS) +} diff --git a/src/northbridge/intel/gm965/acpi/peg.asl b/src/northbridge/intel/gm965/acpi/peg.asl new file mode 100644 index 00000000000..6a67238317d --- /dev/null +++ b/src/northbridge/intel/gm965/acpi/peg.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 }, + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } + } +} diff --git a/src/northbridge/intel/gm965/bootblock.c b/src/northbridge/intel/gm965/bootblock.c new file mode 100644 index 00000000000..39b6eeedf02 --- /dev/null +++ b/src/northbridge/intel/gm965/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gm965.h" + +static uint32_t encode_pciexbar_length(void) +{ + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} + +void bootblock_early_northbridge_init(void) +{ + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to + * true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); +} diff --git a/src/northbridge/intel/gm965/cfr.h b/src/northbridge/intel/gm965/cfr.h new file mode 100644 index 00000000000..6bf0509b85c --- /dev/null +++ b/src/northbridge/intel/gm965/cfr.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs for nb/gm965 + */ + +#ifndef NB_INTEL_GM965_CFR_H +#define NB_INTEL_GM965_CFR_H + +#include + +enum { + GM965_IGD_UMA_SIZE_1MB, + GM965_IGD_UMA_SIZE_4MB, + GM965_IGD_UMA_SIZE_8MB, + GM965_IGD_UMA_SIZE_16MB, + GM965_IGD_UMA_SIZE_32MB, + GM965_IGD_UMA_SIZE_48MB, + GM965_IGD_UMA_SIZE_64MB, +}; + +/* IGD UMA Size */ +static const struct sm_object gfx_uma_size = SM_DECLARE_ENUM({ + .opt_name = "gfx_uma_size", + .ui_name = "IGD UMA Size", + .ui_helptext = "Size of memory preallocated for internal graphics.", + .default_value = GM965_IGD_UMA_SIZE_32MB, + .values = (const struct sm_enum_value[]) { + { " 1MB", GM965_IGD_UMA_SIZE_1MB }, + { " 4MB", GM965_IGD_UMA_SIZE_4MB }, + { " 8MB", GM965_IGD_UMA_SIZE_8MB }, + { "16MB", GM965_IGD_UMA_SIZE_16MB }, + { "32MB", GM965_IGD_UMA_SIZE_32MB }, + { "48MB", GM965_IGD_UMA_SIZE_48MB }, + { "64MB", GM965_IGD_UMA_SIZE_64MB }, + SM_ENUM_VALUE_END }, +}); + +#endif /* NB_INTEL_GM965_CFR_H */ diff --git a/src/northbridge/intel/gm965/chip.h b/src/northbridge/intel/gm965/chip.h new file mode 100644 index 00000000000..af6f8cdf7f9 --- /dev/null +++ b/src/northbridge/intel/gm965/chip.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef NORTHBRIDGE_INTEL_GM965_CHIP_H +#define NORTHBRIDGE_INTEL_GM965_CHIP_H + +#include + +struct northbridge_intel_gm965_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + struct i915_gpu_controller_info gfx; + u16 default_pwm_freq; + u8 duty_cycle; +}; + +#endif /* NORTHBRIDGE_INTEL_GM965_CHIP_H */ diff --git a/src/northbridge/intel/gm965/dmi.c b/src/northbridge/intel/gm965/dmi.c new file mode 100644 index 00000000000..10725b84dbf --- /dev/null +++ b/src/northbridge/intel/gm965/dmi.c @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - DMI/PCIe Link Initialization + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * BIOS functions: + * FFF897DB (pci_init_dmibar) - DMI link setup from PCI_INIT region + * FFF8BF7A (bar_epbar_dmibar_setup) - EPBAR/DMIBAR register programming + * bioscode_7.rom - DMI/PCIe link init module + * + * This file handles the northbridge (MCH) side of DMI link setup. + * The southbridge side is handled by i82801hx_dmi_setup() in the ICH8-M driver. + * + * Reference: coreboot GM45 pcie.c (init_egress, init_dmi, setup_rcrb) + */ + +#include +#include + +/* BAR base addresses from Kconfig */ +#define MCHBAR_BASE CONFIG_FIXED_MCHBAR_MMIO_BASE +#define DMIBAR_BASE CONFIG_FIXED_DMIBAR_MMIO_BASE +#define EPBAR_BASE CONFIG_FIXED_EPBAR_MMIO_BASE +#define RCBA_BASE CONFIG_FIXED_RCBA_MMIO_BASE + +/* ================================================================== */ +/* Egress Port Setup */ +/* ================================================================== */ + +/* + * init_egress() - Configure the Egress Port (EPBAR) + * + * Sets up virtual channels on the EPBAR for DMI traffic routing. + * VC0 handles normal traffic (TC0), VC1 handles isochronous (TC7). + * + * coreboot equivalent: init_egress() in pcie.c + */ +static void init_egress(void) +{ + printk(BIOS_DEBUG, "%s\n", __func__); + /* VC0: TC0 only */ + epbar_clrbits8(EPVC0RCTL, ~1); + epbar_clrsetbits8(EPPVCCAP1, 7, 1); + + /* VC1 isochronous: matching time slots */ + epbar_write32(EPVC1MTS, 0x0a0a0a0a); + epbar_clrsetbits32(EPVC1RCAP, 127 << 16, 0x0a << 16); + + /* VC1: ID=1, TC7 */ + epbar_clrsetbits32(EPVC1RCTL, 7 << 24, 1 << 24); + epbar_clrsetbits8(EPVC1RCTL, ~1, 1 << 7); + + /* VC1 ARB table: setup and enable */ + epbar_write32(EP_PORTARB(0), 0x55555555); + epbar_write32(EP_PORTARB(1), 0x55555555); + epbar_write32(EP_PORTARB(2), 0x55555555); + epbar_write32(EP_PORTARB(3), 0x55555555); + epbar_write32(EP_PORTARB(4), 0x55555555); + epbar_write32(EP_PORTARB(5), 0x55555555); + epbar_write32(EP_PORTARB(6), 0x55555555); + epbar_write32(EP_PORTARB(7), 0x00005555); + + /* Load ARB table */ + epbar_setbits32(EPVC1RCTL, 1 << 16); + + /* Wait for ARB table load */ + while (epbar_read8(EPVC1RSTS) & 1) + ; + + /* Enable VC1 */ + epbar_setbits32(EPVC1RCTL, 1 << 31); + + /* Wait for VC1 negotiation */ + while (epbar_read8(EPVC1RSTS) & 2) + ; +} + +/* ================================================================== */ +/* DMI Link Setup (Northbridge Side) */ +/* ================================================================== */ + +/* + * init_dmi() - Configure DMI link (MCH side) + * + * Sets up virtual channels, link parameters, and write-once registers + * on the DMIBAR for the MCH-to-ICH link. + * + * coreboot equivalent: init_dmi() in pcie.c + */ +static void init_dmi(void) +{ + printk(BIOS_DEBUG, "%s\n", __func__); + /* VC0: TC0 only */ + dmibar_clrbits8(DMIVC0RCTL, ~1); + dmibar_clrsetbits8(DMIPVCCAP1, 7, 1); + + /* VC1: ID=1, TC7 */ + dmibar_clrsetbits32(DMIVC1RCTL, 7 << 24, 1 << 24); + dmibar_clrsetbits8(DMIVC1RCTL, ~1, 1 << 7); + + /* Enable VC1 */ + dmibar_setbits32(DMIVC1RCTL, 1 << 31); + + /* Wait for VC1 negotiation */ + while (dmibar_read8(DMIVC1RSTS) & VC1NP) + ; + + /* + * Additional DMI configuration from BIOS. + * These magic register writes were observed in bioscode_7.rom + * and match coreboot GM45 init_dmi() exactly. + */ + dmibar_setbits32(0x200, 3 << 13); + dmibar_clrbits32(0x200, 1 << 21); + dmibar_clrsetbits32(0x200, 3 << 26, 2 << 26); + dmibar_write32(0x2c, 0x86000040); + + /* Link flow control credits and configuration */ + dmibar_setbits32(0xfc, 1 << 0); + dmibar_setbits32(0xfc, 1 << 1); + dmibar_setbits32(0xfc, 1 << 4); + + /* + * Stepping-dependent config (cf. GM45 init_dmi). + * Pre-B0 steppings (A0/A1, rev < 2): set bit 11. + * B0+ steppings (rev >= 2, including C0 rev 3): clear bit 11. + * Vendor inteltool confirms 0xFC=0x31 (bit 11 clear) on C0. + */ + if (northbridge_stepping() < 0x02) + dmibar_setbits32(0xfc, 1 << 11); + else + dmibar_clrbits32(0xfc, 1 << 11); + + dmibar_clrbits32(0x204, 3 << 10); + dmibar_clrbits32(0xf4, 1 << 4); + dmibar_setbits32(0xf0, 3 << 24); + + /* Per-lane equalization settings */ + dmibar_write32(0xf04, 0x07050880); + dmibar_write32(0xf44, 0x07050880); + dmibar_write32(0xf84, 0x07050880); + dmibar_write32(0xfc4, 0x07050880); + + /* Lock write-once registers by performing a read-modify-write (OR 0) */ + dmibar_setbits32(0x308, 0); + dmibar_setbits32(0x314, 0); + dmibar_setbits32(0x324, 0); + dmibar_setbits32(0x328, 0); + dmibar_setbits32(0x334, 0); + dmibar_setbits32(0x338, 0); +} + +/* ================================================================== */ +/* RCRB Setup */ +/* ================================================================== */ + +/* + * setup_rcrb() - Configure Root Complex Register Block routing + * + * Programs the EPBAR and DMIBAR with component IDs and link targets + * so the root complex can route transactions between MCH (component 1) + * and ICH (component 2). + * + * coreboot equivalent: setup_rcrb() in pcie.c + */ +static void setup_rcrb(void) +{ + int peg_present; + + printk(BIOS_DEBUG, "%s\n", __func__); + /* + * Egress Port RCRB: + * - Component ID = 1 (MCH) + * - Link1: target = DMIBAR (component 1, link valid) + */ + epbar_clrsetbits32(EPESD, 0xff << 16, 1 << 16); + + epbar_clrsetbits32(EPLE1D, 0xff << 16, (1 << 16) | (1 << 0)); + epbar_write32(EPLE1A, DMIBAR_BASE); + + /* + * PEG Link2 setup: check if D1:F0 (PEG) is present by reading + * its vendor ID. The vendor BIOS reads D1:F0 reg 0x00 and + * skips if 0xFF (device absent). + * + * Vendor BIOS: bioscode_7.rom @ 0x06ac-0x072a + */ + peg_present = (pci_read_config8(D1F0, 0x00) != 0xff); + + if (peg_present) { + /* + * Egress Port Link2 -> PEG: + * - Component ID = 1 (MCH), link valid + */ + epbar_clrsetbits32(EPLE2D, 0xff << 16, (1 << 16) | (1 << 0)); + + /* + * PEG device RCRB (D1:F0 extended config space): + * Configure the PEG endpoint's own link registers to + * point back to the egress port (EPBAR). + * + * 0x144: component ID = 1 + * 0x158: target = EPBAR + * 0x150: component 1, link valid + */ + pci_update_config32(D1F0, 0x144, + ~(0xff << 16), 1 << 16); + pci_write_config32(D1F0, 0x158, + CONFIG_FIXED_EPBAR_MMIO_BASE); + pci_update_config32(D1F0, 0x150, + ~(0xff << 16), (1 << 16) | (1 << 0)); + } + + /* + * DMI Port RCRB: + * - Component ID = 1 (MCH) + * - Link1: target port 0, component 2 (ICH), link valid -> RCBA + * - Link2: component 1 (MCH), link valid -> EPBAR + */ + dmibar_clrsetbits32(DMIESD, 0xff << 16, 1 << 16); + + dmibar_write32(DMILE1A, RCBA_BASE); + dmibar_clrsetbits32(DMILE1D, 0xffff << 16, + (0 << 24) | (2 << 16) | (1 << 0)); + + dmibar_write32(DMILE2A, CONFIG_FIXED_EPBAR_MMIO_BASE); + dmibar_clrsetbits32(DMILE2D, 0xff << 16, (1 << 16) | (1 << 0)); +} + +/* ================================================================== */ +/* ASPM Setup */ +/* ================================================================== */ + +/* + * setup_aspm() - Configure Active State Power Management on DMI + * + * Enables L0s and L1 for mobile platforms (X61 is always mobile). + * + * coreboot equivalent: setup_aspm() in pcie.c (DMI portion) + */ +static void setup_aspm(void) +{ + printk(BIOS_DEBUG, "%s\n", __func__); + /* DMI ASPM prerequisites */ + dmibar_setbits8(0x0e1c, 1 << 0); + dmibar_setbits16(0x0f00, 3 << 8); + dmibar_setbits16(0x0f00, 7 << 3); + dmibar_clrbits32(0x0f14, 1 << 17); + dmibar_clrbits16(0x0e1c, 1 << 8); + + /* + * Stepping-dependent adjustments (cf. GM45 setup_aspm). + * B0+ steppings (rev >= 2): program 0xe2c lane equalization. + */ + if (northbridge_stepping() >= 0x02) { + dmibar_clrsetbits32(0x0e28 + 4, 0xfU << (52 - 32), 0xdU << (52 - 32)); + dmibar_write32(0x0e2c, 0x88d07333); + } + + /* Enable ASPM L0s + L1 on DMI (write-once) - X61 is mobile */ + dmibar_setbits8(DMILCTL, 3 << 0); + + /* Exit latency timing */ + dmibar_clrsetbits32(DMILCAP, 63 << 12, (2 << 12) | (2 << 15)); + dmibar_write8(0x208 + 3, 0); + dmibar_clrbits32(0x208, 3 << 20); +} + +/* ================================================================== */ +/* Public Entry Point */ +/* ================================================================== */ + +/* + * gm965_dmi_init() - Full DMI/PCIe link initialization + * + * Orchestrates egress port, DMI link, RCRB routing, and ASPM setup. + * Should be called after gm965_early_init() and raminit, but before + * PCI device enumeration. + * + * The southbridge side (i82801hx_dmi_setup) must be called first or + * concurrently. After both sides are configured, call + * i82801hx_dmi_poll_vc1() to wait for negotiation. + * + * BIOS equivalent: FFF897DB + FFF8BF7A + bioscode_7.rom + * coreboot equivalent: gm45_late_init() in pcie.c + */ +void gm965_dmi_init(void) +{ + init_egress(); + init_dmi(); + setup_rcrb(); + setup_aspm(); +} diff --git a/src/northbridge/intel/gm965/early_init.c b/src/northbridge/intel/gm965/early_init.c new file mode 100644 index 00000000000..79c99af77db --- /dev/null +++ b/src/northbridge/intel/gm965/early_init.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - Early Initialization + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * BIOS functions: + * FFFE04F5 (early_bar_setup) - Programs MCHBAR/DMIBAR/EPBAR BARs + * FFFE1111 (early_epbar_dmibar) - EPBAR/DMIBAR register setup + * FFFE0F2D (sskpd_check) - Checks SSKPD for 0xCAFE warm boot marker + * FFFE17DC (early_init_main) - Orchestrates Phase 1 + * + * Reference: coreboot GM45 early_init.c (nearly identical for GM965) + */ + +#include +#include +#include + +/* BAR base addresses from Kconfig */ +#define MCHBAR_BASE CONFIG_FIXED_MCHBAR_MMIO_BASE +#define DMIBAR_BASE CONFIG_FIXED_DMIBAR_MMIO_BASE +#define EPBAR_BASE CONFIG_FIXED_EPBAR_MMIO_BASE + +/* + * gm965_early_init() - Phase 1 early northbridge setup + * + * Programs the memory-mapped BAR registers into D0:F0 PCI config space + * and opens PAM regions so the C0000-FFFFF range is accessible as RAM. + * + * Must be called very early, before any MCHBAR/DMIBAR/EPBAR access. + * + * BIOS equivalent: FFFE04F5 + FFFE17DC (16-bit early init) + * coreboot equivalent: gm45_early_init() in early_init.c + */ +void gm965_early_init(void) +{ + /* + * Setup MCHBAR (D0:F0 offset 0x48). + * X61 BIOS uses 0xFED14000 (non-standard; GM45 default is 0xFED10000). + * Bit 0 = enable. + */ + pci_write_config32(D0F0, D0F0_MCHBAR_LO, MCHBAR_BASE | 1); + pci_write_config32(D0F0, D0F0_MCHBAR_HI, 0); + + /* Setup DMIBAR (D0:F0 offset 0x68). */ + pci_write_config32(D0F0, D0F0_DMIBAR_LO, DMIBAR_BASE | 1); + pci_write_config32(D0F0, D0F0_DMIBAR_HI, 0); + + /* Setup EPBAR (D0:F0 offset 0x40). */ + pci_write_config32(D0F0, D0F0_EPBAR_LO, EPBAR_BASE | 1); + pci_write_config32(D0F0, D0F0_EPBAR_HI, 0); + + /* + * Open PAM regions - set C0000-FFFFF to access RAM on both + * reads and writes. This allows decompressed BIOS modules + * (or coreboot ramstage) to be copied into and executed from + * this address range. + * + * PAM0 (0xF0000-0xFFFFF): 0x30 = read/write RAM + * PAM1-6 (0xC0000-0xEFFFF): 0x33 = both halves read/write RAM + * + * BIOS equivalent: observed in early init and PCI_INIT regions. + */ + pci_write_config8(D0F0, D0F0_PAM(0), 0x30); + pci_write_config8(D0F0, D0F0_PAM(1), 0x33); + pci_write_config8(D0F0, D0F0_PAM(2), 0x33); + pci_write_config8(D0F0, D0F0_PAM(3), 0x33); + pci_write_config8(D0F0, D0F0_PAM(4), 0x33); + pci_write_config8(D0F0, D0F0_PAM(5), 0x33); + pci_write_config8(D0F0, D0F0_PAM(6), 0x33); + + /* + * Enable devices (DEVEN register, D0:F0 offset 0x54). + * Default has D0F0 + IGD enabled; ensure PEG is available + * if a discrete GPU is present (X61 has no PEG, but X61s does). + * + * BIOS sets DEVEN during PCI_INIT (FFF89000 region). + * Don't enable ME as somehow the handshake does not succeed. + */ + pci_write_config32(D0F0, D0F0_DEVEN, + DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1); + + /* + * MCHBAR+0x0094: Non-isoch arbitration / channel decode config. + * + * Vendor BIOS (FFFE11DA): reads MCHBAR+0x94, clears bits [20:19], + * then sets bit 20. This is done conditionally in the vendor + * (guarded by a flag from PCI D0:F0 capability probing), but + * the X61 always takes this path. + * + * Bits [20:19] control the non-isoch arbiter decode mode: + * 00 = disabled + * 01 = mode A + * 10 = mode B (vendor setting) + * 11 = mode C + */ + mchbar_clrsetbits32(FSBPMC5, 3 << 19, 2 << 19); + + /* + * DMIBAR+0x0204: DMI link control 2. + * + * Vendor BIOS (FFFE11FE): unconditionally clears bits [11:10]. + * These control DMI link de-emphasis / equalization settings + * that must be cleared before DRAM init begins. + */ + dmibar_clrbits32(DMILCTL2, 3 << 10); +} diff --git a/src/northbridge/intel/gm965/gm965.h b/src/northbridge/intel/gm965/gm965.h new file mode 100644 index 00000000000..3ada91cf5db --- /dev/null +++ b/src/northbridge/intel/gm965/gm965.h @@ -0,0 +1,584 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - register definitions + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * Reference: coreboot GM45 (Cantiga) northbridge + * + * GM965 is the predecessor to GM45. Register layout is largely + * identical at the MCHBAR/DMIBAR/EPBAR level. Key difference: + * GM965 supports DDR2 only; GM45 adds DDR3. + */ + +#ifndef _GM965_H_ +#define _GM965_H_ + +#include +#include +#include +#include + +/* ================================================================== */ +/* PCI Device IDs */ +/* ================================================================== */ + +#define PCI_DID_GM965_MCH 0x2A00 /* Host Bridge */ +#define PCI_DID_GM965_PEG 0x2A01 /* PCI Express Graphics */ +#define PCI_DID_GM965_IGD 0x2A02 /* Integrated Graphics */ +#define PCI_DID_GM965_IGD_1 0x2A03 /* IGD (alt) */ + +/* PCI Devices */ +#define D0F0 PCI_DEV(0, 0, 0) /* Host Bridge */ +#define D1F0 PCI_DEV(0, 1, 0) /* PEG */ +#define D2F0 PCI_DEV(0, 2, 0) /* IGD */ +#define D2F1 PCI_DEV(0, 2, 1) /* IGD Pipe B */ + +/* ================================================================== */ +/* D0:F0 PCI Config Space */ +/* ================================================================== */ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 /* Graphics Memory Control */ +#define D0F0_DEVEN 0x54 /* Device Enable */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90 + (x)) /* PAM0..PAM6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 /* Top of Memory */ +#define D0F0_TOUUD 0xa2 /* Top of Upper Usable DRAM */ +#define D0F0_TOLUD 0xb0 /* Top of Low Usable DRAM */ +#define D0F0_SKPD 0xdc /* Scratchpad */ +#define D0F0_CAPID0 0xe0 /* Capability ID */ + +/* DEVEN bits */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) /* PEG */ +#define DEVEN_D2F0 (1 << 3) /* IGD */ +#define DEVEN_D2F1 (1 << 4) /* IGD Pipe B */ +#define DEVEN_D3F0 (1 << 6) +#define DEVEN_D3F1 (1 << 7) +#define DEVEN_D3F2 (1 << 8) +#define DEVEN_D3F3 (1 << 9) + + +/* D3:F0 Management Engine (ME) */ +#define D3F0 PCI_DEV(0, 3, 0) +#define D3F0_BAR 0xFED10000 + +/* + * D3:F0 HECI (Host Embedded Controller Interface) register offsets + * relative to D3F0_BAR. H_CSR and ME_CSR_HA share the same bit layout. + * The vendor BIOS uses this interface to notify the ME before/after + * a PLL frequency change so the ME can quiesce its clocked logic. + * If ME firmware is absent the whole handshake is skipped and the PLL + * still relocks via the CLKCFG hardware alone. + */ +#define ME_H_CB_WW 0x00 /* Host Circular Buffer Write Window */ +#define ME_H_CSR 0x04 /* Host Control/Status Register */ +#define ME_ME_CB_RW 0x08 /* ME Circular Buffer Read Window */ +#define ME_ME_CSR_HA 0x0c /* ME Control/Status Register (Host Access) */ +/* Bit layout common to ME_H_CSR and ME_ME_CSR_HA */ +#define ME_CSR_IE (1u << 0) /* Interrupt Enable */ +#define ME_CSR_IS (1u << 1) /* Interrupt Status (w1c) */ +#define ME_CSR_IG (1u << 2) /* Interrupt Generate */ +#define ME_CSR_RDY (1u << 3) /* Ready */ +#define ME_CSR_RST (1u << 4) /* Reset */ + +/* D2:F0 IGD config space */ +#define D2F0_BSM 0x5c /* Base of Stolen Memory */ + +/* GGC bits */ +#define GGC_GMS_MASK (0x7 << 4) /* GFX UMA size, bits [6:4] */ + +/* IGD config */ +#define GCFGC_OFFSET 0xf0 +#define GCFGC_CR_MASK (0xf << 0) +#define GCFGC_CS_MASK (0xf << 8) +#define GCFGC_UPDATE (1 << 5) + +/* ================================================================== */ +/* MCHBAR Register Offsets (base = 0xFED14000) */ +/* ================================================================== */ + +/* --- Front Side Bus Power Management --- */ +#define FSBPMC3 0x0040 /* Front Side Bus Power Management Control 3 */ +#define FSBPMC5 0x0094 /* Front Side Bus Power Management Control 5 */ + +/* --- DCC (DRAM Channel Control) --- */ +#define DCC_MCHBAR 0x0200 /* DRAM Channel Control */ +#define DCC2_MCHBAR 0x0204 /* DRAM Channel Control 2 (bits 15:0 = ME size in MB) */ +#define DCC_INTERLEAVED (1 << 1) +#define DCC_NO_CHANXOR (1 << 10) +#define DCC_CMD_SHIFT 16 +#define DCC_CMD_MASK (7 << 16) +#define DCC_CMD_NOP (1 << 16) +#define DCC_CMD_ABP (2 << 16) /* All Banks Precharge */ +#define DCC_SET_MREG (3 << 16) /* MR0 / Mode Register Set */ +#define DCC_SET_EREG (4 << 16) /* Extended Mode Registers */ +#define DCC_SET_EREG_SHIFT 21 +#define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << 21)) +#define DCC_SET_EREGx(x) ((DCC_SET_EREG | (((x)-1) << 21)) & DCC_SET_EREG_MASK) +#define DCC_CMD_CBR (6 << 16) /* CBR Auto-Refresh */ +#define DCC_CMD_NORMAL (7 << 16) +#define DCC_INIT_COMPLETE (1 << 19) /* Initialization Complete (IC) */ +#define DCC_CMD_NORMAL_ANN (DCC_CMD_NORMAL | DCC_INIT_COMPLETE) + +/* --- Clock Crossing --- */ +#define CLKCROSS_DATA3 0x0208 +#define CLKCROSS_DATA2 0x020c +#define CLKCROSS_DATA1 0x0210 +#define WRITE_CTRL 0x0218 +#define MMARB0 0x0220 /* Main Memory Arbiter Control 0 */ +#define MMARB1 0x0224 /* Main Memory Arbiter Control 1 */ +#define SBTEST 0x0230 /* SB Test Register */ +#define POST_JEDEC_TIM0 0x0238 +#define POST_JEDEC_TIM1 0x023c + +/* --- RCOMP --- */ +#define RCOMP_CTRL 0x0400 +#define RCOMP_STATUS 0x0404 +#define RCOMP_CFG 0x040c +#define RCOMP_IO_CFG 0x0410 +#define RCOMP_CFG2 0x0414 +#define RCOMP_CFG3 0x0418 +#define RCOMP_CFG4 0x041c +#define RCOMP_ODT0 0x04d0 +#define RCOMP_ODT1 0x04d4 +#define RCOMP_TABLES 0x0680 /* 9 groups x 64 bytes in MCHBAR */ + +/* + * --- EPDunit / Address Decode (BIOS FFF02A7A + FFF03286) --- + * + * The EPDunit region (MCHBAR 0x0A00-0x0AA0) programs the memory + * controller's secondary address decode and timing logic. Without + * this, the controller does not know how to route transactions to + * channel 1. The RAMINIT copy at FFF0xxxx programs these registers + * between POST 0xFF41 and 0xFF42; the RAMINIT3 copy at FFFF3xxx + * omits them entirely. + * + * The region includes: + * 0x0A00-0x0A07: DRB copies from CxDRBy (halved), per-channel + * 0x0A08-0x0A0B: DRA encoding for ch0 DIMMs (2 x 16-bit) + * 0x0A34-0x0A3F: DRB/DRA copies for ch1 + * 0x0A10-0x0A33: Timing fields (CAS, tRP, tRCD, tRRD, tRFC, etc.) + * 0x0A2E: Capability/init state (bit 5 = 800MT flag) + * 0x0A2F: Channel population mask (bit 0=ch0, bit 1=ch1) + * 0x0A30: Mode control (bit 26 = channel enable) + * 0x0A99-0x0A9F: CAS/rank-dependent scheduling + * 0x0AA0: Per-channel rank topology + */ +#define EPD_C0DRB01 0x0a00 /* ch0 rank0/1 boundaries (2x16-bit, halved) */ +#define EPD_C0DRB23 0x0a04 /* ch0 rank2/3 boundaries (2x16-bit, halved) */ +#define EPD_C0DRA01 0x0a08 /* ch0 slot0 DRA encoding (2x8-bit) */ +#define EPD_C0DRA23 0x0a0a /* ch0 slot1 DRA encoding (2x8-bit) */ +#define EPD_C1DRB01 0x0a34 /* ch1 rank0/1 boundaries (2x16-bit, halved) */ +#define EPD_C1DRB23 0x0a38 /* ch1 rank2/3 boundaries (2x16-bit, halved) */ +#define EPD_C1DRA01 0x0a3c /* ch1 slot0 DRA encoding (2x8-bit) */ +#define EPD_C1DRA23 0x0a3e /* ch1 slot1 DRA encoding (2x8-bit) */ +#define EPD_10 0x0a10 /* control bits */ +#define EPD_11 0x0a11 /* CAS + 8 field */ +#define EPD_13 0x0a13 /* constant bit 2 */ +#define EPD_14 0x0a14 /* CAS in low nibble */ +#define EPD_15 0x0a15 /* CAS-dependent scheduling */ +#define EPD_19 0x0a19 /* tWTR / tRCD+CAS / tRFC_mult */ +#define EPD_1B 0x0a1b /* CAS+4, BtB_WtR */ +#define EPD_1C 0x0a1c /* tRFC direct */ +#define EPD_1D 0x0a1d /* tRRD shifted */ +#define EPD_1F 0x0a1f +#define EPD_20 0x0a20 /* BtB_WtR, tRP, constant */ +#define EPD_22 0x0a22 /* tRTP + tRFC */ +#define EPD_24 0x0a24 /* tRTP_precharge, constants */ +#define EPD_28 0x0a28 /* rank mode / scheduling */ +#define EPD_2C 0x0a2c /* constant 0x12 */ +#define EPD_2D 0x0a2d /* mode bits */ +#define EPD_2E 0x0a2e /* capability / init state */ +#define EPD_2F 0x0a2f /* channel population mask */ +#define EPD_30 0x0a30 /* mode control (bit 26) */ +#define EPD_33 0x0a33 +#define EPD_99 0x0a99 /* CAS/rank scheduling */ +#define EPD_9C 0x0a9c /* CAS/rank scheduling */ +#define EPD_A0 0x0aa0 /* per-channel rank topology */ + +/* --- Clock Configuration --- */ +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << 0) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << 4) +#define CLKCFG_UPDATE (1 << 12) + +#define HPLLVCO_MCHBAR 0x0c0f + +/* --- Scratchpad / Power Management --- */ +#define SSKPD_MCHBAR 0x0c1c +#define MCHBAR_FFC 0x0ffc /* Arbitration control */ +#define PMSTS_MCHBAR 0x0f14 +#define PMSTS_WARM_RESET (1 << 1) +#define PMSTS_SELFREFRESH (1 << 0) + +/* --- PM Init registers (vendor bioscode_5.rom) --- */ +#define PM_CTRL0 0x0040 /* PM control 0 */ +#define PM_CTRL1 0x0044 /* PM control 1 */ +#define PM_NOCARB 0x0090 /* Non-isoch arb (low 16 bits) */ +#define PM_NOCARB_HI 0x0094 /* Non-isoch arb (high 32 bits) */ +#define PM_SCHED 0x0b00 /* PM scheduling */ +#define PM_SCHED_B90 0x0b90 /* PM scheduling 2 */ +#define PM_BD8 0x0bd8 /* PM misc */ +#define CLKCFG_C14 0x0c14 /* Clock config 2 */ +#define CLKCFG_C16 0x0c16 /* Clock config 3 */ +#define CLKCFG_C20 0x0c20 /* Clock config 4 */ +#define HGIPMC2_LO 0x0c38 /* Host-Graphics Interface PM Control 2 (lower 16) */ +#define HGIPMC2_HI 0x0c3a /* Host-Graphics Interface PM Control 2 (upper 16) */ +#define C2C3TT 0x0f00 /* C2 to C3 Transition Timer */ +#define C3C4TT 0x0f04 /* C3 to C4 Transition Timer */ +#define PM_F08 0x0f08 /* C-state transition timer */ +#define PM_F10 0x0f10 /* PM control (bits 1,5 critical) */ +#define PM_F60 0x0f60 /* PM mode */ +#define PM_F80 0x0f80 /* PM enable (bit 31) */ +#define GIPMC1 0x0fb0 /* Graphics Interface Power Management Control 1 */ +#define FSBPMC1 0x0fb8 /* Front Side Bus Power Management Control 1 */ +#define UPMC3 0x0fc0 /* Unit Power Management Control 3 */ + +/* --- IGD init registers (vendor bioscode_7.rom) --- */ +#define IGD_HSYNC_VSYNC 0x0bd0 /* HSync/VSync control (byte 3 and +4) */ + +/* --- Per-Channel Registers (ch0 = base, ch1 = base + 0x100) --- */ +#define CxDRBy_MCHBAR(ch, r) (0x1200 + (ch)*0x100 + ((r)/2)*4) +#define CxDRA_MCHBAR(ch) (0x1208 + (ch)*0x100) +#define CxDRA_HI(ch) (0x120a + (ch)*0x100) /* upper 16 bits of CxDRA */ +#define CxDCLKDIS_MCHBAR(ch) (0x120c + (ch)*0x100) +#define CxDRT0_MCHBAR(ch) (0x1210 + (ch)*0x100) +#define CxDRT1_MCHBAR(ch) (0x1214 + (ch)*0x100) +#define CxDRT2_MCHBAR(ch) (0x1218 + (ch)*0x100) +#define CxDRT3_MCHBAR(ch) (0x121c + (ch)*0x100) +#define CxDRT4_MCHBAR(ch) (0x1220 + (ch)*0x100) +#define CxDRT5_MCHBAR(ch) (0x1224 + (ch)*0x100) +#define CxDRT6_MCHBAR(ch) (0x1228 + (ch)*0x100) +#define CxDRC0_MCHBAR(ch) (0x1230 + (ch)*0x100) +#define CxDRC1_MCHBAR(ch) (0x1234 + (ch)*0x100) +#define CxDRC2_MCHBAR(ch) (0x1238 + (ch)*0x100) +#define CxODT_LOW(ch) (0x1248 + (ch)*0x100) +#define CxODT_HIGH(ch) (0x124c + (ch)*0x100) +#define CxAIT_LO(ch) (0x1250 + (ch)*0x100) /* Adaptive Idle Timer Control low */ +#define CxAIT_HI(ch) (0x1254 + (ch)*0x100) /* Adaptive Idle Timer Control high */ +#define CxODT_MISC(ch) (0x1260 + (ch)*0x100) /* ODT misc control */ +#define CxODT_TIMING(ch) (0x1268 + (ch)*0x100) /* ODT timing */ +#define CxPWR_THROTTLE0(ch) (0x1270 + (ch)*0x100) /* Power throttle 0 */ +#define CxPWR_THROTTLE1(ch) (0x1274 + (ch)*0x100) /* Power throttle 1 */ +#define CxODT_CTRL(ch) (0x12a0 + (ch)*0x100) /* ODT control */ + +/* CxDRC0 bits */ +#define CxDRC0_RANKEN(r) (1 << (24 + (r))) +#define CxDRC0_RANKEN_MASK (0xf << 24) +#define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */ +#define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT) +#define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT) +#define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT) + +/* CxDRC1 bits */ +#define CxDRC1_CKE_TRISTATE(r) (1 << (16 + (r))) /* CKE tri-state enable per rank (set for unpopulated) */ +#define CxDRC1_ADRTRIEN (1 << 11) /* Address tri-state enable */ +#define CxDRC1_CSBTRIEN (1 << 12) /* CS# tri-state enable */ + +/* --- IO Init / Training --- */ +#define IO_INIT_CFG 0x1400 +#define IO_INIT_CLK_DEP 0x140c +#define IO_INIT_CFG2 0x1414 /* Clock-dependent IO config 2 */ +#define IO_INIT_CFG3 0x1418 /* IO strobe config */ +#define IO_INIT_CFG4 0x141c /* IO strobe config 2 */ +#define IO_INIT_CFG5 0x142c /* IO misc config */ +#define DRAM_TYPE_SELECT 0x1434 +#define IO_INIT_CFG6 0x1438 /* IO misc config 2 */ +#define IO_INIT_CFG7 0x1440 /* IO RCOMP code */ +#define IO_RCOMP_CLK_EN 0x1444 /* RCOMP engine clock enable; bit 12 must be set while RCOMP runs */ +#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch)*0x100 + ((3-(s))*4)) +#define CxTRAIN_CFG(ch) (0x1484 + (ch)*0x100) /* Training config */ +#define CxTRAIN_PI(ch) (0x1490 + (ch)*0x100) /* PI settings (8 DWORDs) */ +#define CxRECy_MCHBAR(ch, g) (0x14a0 + (ch)*0x100 + ((3-(g))*4)) +#define REC_DQS_LEVEL(ch) (0x14ac + (ch)*0x100) /* DQS readback, bit 30 */ +#define REC_COARSE_LOW(ch) (0x14b0 + (ch)*0x100) /* Sub-coarse, bits [3:2] */ +#define CxRDTy_MCHBAR(ch, l) (0x14b0 + (ch)*0x100 + ((7-(l))*4)) +#define RW_PTR_CTRL(ch) (0x14f0 + (ch)*0x100) + +/* Training enable */ +#define TRAIN_ENABLE(ch) (0x12a4 + (ch)*0x100) +#define TRAIN_ENABLE_BIT (1 << 31) + +/* --- Power Management / Thermal Throttle --- */ +#define PM_CH_BASE(ch) (0x1000 + (ch)*0x40) +#define PM_CH_CMD(ch) (0x1001 + (ch)*0x40) +#define PM_CH_CTRL(ch) (0x1007 + (ch)*0x40) +#define PM_CH_THRT0(ch) (0x1010 + (ch)*0x40) +#define PM_CH_THRT1(ch) (0x1014 + (ch)*0x40) +#define PM_CH_TSC0(ch) (0x1018 + (ch)*0x40) +#define PM_CH_TSC1(ch) (0x101c + (ch)*0x40) +#define PM_CH_TSC1B(ch) (0x101d + (ch)*0x40) +#define PM_CH_EXTTS(ch) (0x1058 + (ch)*0x40) +#define PM_THRT_CTRL 0x1070 +#define PM_THRT_MODE 0x1080 +#define THERMAL_ENABLE 0x10ef + +/* --- I/O Scheduling / Arbitration --- */ +#define IOSCHED_BASE 0x1120 /* 4 x 32-bit scheduling regs */ +#define IOSCHED_0 0x1120 +#define IOSCHED_1 0x1124 +#define IOSCHED_2 0x1128 +#define IOSCHED_3 0x112c +#define IOSCHED_MISC 0x11b0 +#define IOSCHED_CC 0x11cc /* Scheduling control */ +#define IOSCHED_190 0x1190 +#define IOSCHED_19E 0x119e + +/* ================================================================== */ +/* D1:F0 PEG (PCI Express Graphics) Config Space */ +/* ================================================================== */ + +#define PEG_SSID 0x2c /* Subsystem ID */ +#define PEG_LCAP 0xa4 /* Link Capabilities */ +#define PEG_LCTL 0xa8 /* Link Control */ +#define PEG_LSTS 0xaa /* Link Status */ +#define PEG_SLOTCAP 0xb4 /* Slot Capabilities */ +#define PEG_CAP 0xa2 /* PCI Express Capabilities */ +#define PEG_PEGLC 0xec /* PEG Lane Control */ +#define PEG_NEGWIDTH 0x224 /* Negotiated link width control */ +#define D1F0_VCCAP 0x104 /* VC Capability (ext VC count) */ +#define D1F0_VC0RCTL 0x114 /* VC0 Resource Control */ + +/* PEG_CAP bits */ +#define PEG_CAP_SLOT_IMPL (1 << 8) /* Slot Implemented */ + +/* PEG SLOTCAP fields */ +#define SLOTCAP_SLOTNUM_SHIFT 17 +#define SLOTCAP_POWER_SCALE_SHIFT 15 +#define SLOTCAP_POWER_LIMIT_SHIFT 7 + +/* PEG_PEGLC bits */ +#define PEGLC_GPE_EN_ALL 0x07 /* All GPE enables */ + +/* ================================================================== */ +/* DMIBAR Register Offsets (base = 0xFED18000) */ +/* ================================================================== */ + +#define DMIVCECH 0x000 +#define DMIPVCCAP1 0x004 +#define DMIVC0RCAP 0x010 +#define DMIVC0RCTL 0x014 +#define DMIVC0RSTS 0x01a +#define DMIVC1RCAP 0x01c +#define DMIVC1RCTL 0x020 +#define DMIVC1RSTS 0x026 +#define VC1NP (1 << 1) +#define DMIESD 0x044 +#define DMILE1D 0x050 +#define DMILE1A 0x058 +#define DMILE2D 0x060 +#define DMILE2A 0x068 +#define DMILCAP 0x084 +#define DMILCTL 0x088 +#define DMILSTS 0x08a +#define DMILCTL2 0x204 /* DMI link control 2 */ + +/* ================================================================== */ +/* EPBAR Register Offsets (base = 0xFED19000) */ +/* ================================================================== */ + +#define EPPVCCAP1 0x004 +#define EPPVCCTL 0x00c +#define EPVC0RCAP 0x010 +#define EPVC0RCTL 0x014 +#define EPVC0RSTS 0x01a +#define EPVC1RCAP 0x01c +#define EPVC1RCTL 0x020 +#define EPVC1RSTS 0x026 +#define EPVC1MTS 0x028 +#define EPVC1ITC 0x02c +#define EPVC1IST 0x038 +#define EPESD 0x044 +#define EPLE1D 0x050 +#define EPLE1A 0x058 +#define EPLE2D 0x060 +#define EPLE2A 0x068 +#define EP_PORTARB(x) (0x100 + 4*(x)) + +/* ================================================================== */ +/* Constants */ +/* ================================================================== */ + +#define NUM_CHANNELS 2 +#define NUM_BYTELANES 8 + +/* ================================================================== */ +/* Helpers */ +/* ================================================================== */ + +static inline uint8_t northbridge_stepping(void) +{ + return pci_s_read_config8(D0F0, 0x08); +} + +/* ================================================================== */ +/* Enumerations */ +/* ================================================================== */ + +/* + * FSB / memory clock indices. + * + * These are the vendor BIOS internal indices, which map 1:1 to the + * raw CLKCFG register encodings (MCHBAR + 0xC00): + * + * FSB bits [2:0] (RO): 001 = FSB-533, 010 = FSB-800, 011 = FSB-667 + * DRAM bits [6:4]: 011 = DDR2-533, 100 = DDR2-667 + * + * GM965 supports DDR2-533 and DDR2-667 only (CAPID0 bit 30). + * Values start at 1 so that 0 means "uninitialized" in the CMOS cache. + */ +typedef enum { + FSB_CLOCK_533MHz = 1, /* CLKCFG 001 */ + FSB_CLOCK_800MHz = 2, /* CLKCFG 010 -- TODO only FSB tested */ + FSB_CLOCK_667MHz = 3, /* CLKCFG 011 */ +} fsb_clock_t; + +typedef enum { + MEM_CLOCK_533MT = 1, /* CLKCFG 011 -- DDR2-533 (266 MHz) */ + MEM_CLOCK_667MT = 2, /* CLKCFG 100 -- DDR2-667 (333 MHz) */ +} mem_clock_t; + +typedef enum { + CHANNEL_MODE_SINGLE = 0, + CHANNEL_MODE_DUAL_ASYNC = 1, + CHANNEL_MODE_DUAL_INTERLEAVED = 2, +} channel_mode_t; + +/* ================================================================== */ +/* Data Structures */ +/* ================================================================== */ + +/* Per-DIMM information (decoded from SPD by common DDR2 library) */ +typedef struct { + int present; /* 1 if DIMM is populated */ + int dual_rank; /* 1 if dual-rank */ + int x16; /* 1 if x16 width */ + uint8_t rows; /* number of row address bits */ + uint8_t cols; /* number of column address bits */ + uint8_t banks; /* number of banks (4 or 8) */ + uint16_t page_size; /* page size in bytes */ + uint16_t rank_capacity_mb; /* capacity per rank in MB */ + /* CAS/frequency info (decoded by common DDR2 SPD library) */ + uint8_t cas_supported; /* bitmask of supported CAS latencies */ + uint32_t cycle_time[8]; /* tCK per CAS level in 1/256 ns */ + /* Timing parameters in 1/256 ns (decoded by common DDR2 SPD library) */ + uint32_t tRCD; + uint32_t tRP; + uint32_t tRAS; + uint32_t tWR; + uint32_t tRRD; + uint32_t tRTP; +} dimminfo_t; + +/* Computed timing parameters */ +typedef struct { + uint8_t CAS; + uint8_t tRAS; + uint8_t tRP; + uint8_t tRCD; + uint8_t tRFC; + uint8_t tWR; + uint8_t tRRD; + uint8_t tRTP; + fsb_clock_t fsb_clock; + mem_clock_t mem_clock; + channel_mode_t channel_mode; +} timings_t; + +/* System information */ +typedef struct { + /* Northbridge info */ + uint8_t stepping; + uint32_t capid0; + + /* DIMM info */ + dimminfo_t dimms[4]; /* logical SPD slots; GM965 uses slots 0 and 2 */ + int dimm_count; + int channels; /* 1 or 2 */ + + /* Computed timings */ + timings_t timings; + + /* Memory map */ + uint32_t tolud_mb; /* Top of Low Usable DRAM in MB */ + uint32_t tom_mb; /* Total memory in MB */ + int s3_resume; /* 1 if resuming from S3 */ + + /* Receive-enable training results */ + uint8_t rec_coarse[NUM_CHANNELS]; /* per-channel coarse_high delay */ + uint8_t rec_coarse_low[NUM_CHANNELS]; /* per-channel sub-coarse delay */ + uint8_t rec_fine[NUM_CHANNELS]; /* per-channel fine delay */ + + /* SPD I2C addresses for each slot (0 if empty) */ + uint8_t spd_addr_map[4]; + + /* Raw SPD data (full 128 bytes) for identification fields */ + u8 raw_spd[4][SPD_SIZE_MAX_DDR2]; + + /* Set by raminit() when using cached training data (skip MRC save) */ + int fast_boot; +} sysinfo_t; + +/* ================================================================== */ +/* Function Prototypes */ +/* ================================================================== */ + +/* northbridge/intel/gm965/early_init.c */ +void gm965_early_init(void); + +/* northbridge/intel/gm965/raminit.c */ +void raminit(sysinfo_t *si); +void raminit_stash_mrc_cache(const sysinfo_t *si); + +/* northbridge/intel/gm965/raminit_receive_enable_calibration.c */ +void receive_enable_training(sysinfo_t *si); +void raminit_program_training(sysinfo_t *si); + +/* northbridge/intel/gm965/raminit_meminfo.c */ +void setup_sdram_meminfo(const sysinfo_t *sysinfo); + +/* northbridge/intel/gm965/dmi.c */ +void gm965_dmi_init(void); + +/* northbridge/intel/gm965/thermal.c */ +void gm965_thermal_init(sysinfo_t *si); + +/* northbridge/intel/gm965/pm.c */ +void gm965_pm_init(const sysinfo_t *si); + +/* northbridge/intel/gm965/igd.c */ +void gm965_igd_init(const sysinfo_t *si); +u16 igd_compute_ggc(void); + +/* northbridge/intel/gm965/memmap.c */ +u32 decode_tseg_size(u8 esmramc); +u32 decode_igd_memory_size(u32 gms); + +#include + +/* northbridge/intel/gm965/pcie.c */ +void gm965_pcie_init(struct device *peg); + +struct acpi_rsdp; +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); + +/* romstage mainboard hookups */ +void mb_pre_raminit_setup(sysinfo_t *si); /* optional, weak */ +void mb_post_raminit_setup(void); /* optional, weak */ +void mainboard_lpc_decode(void); /* optional, weak */ +void mainboard_get_spd_map(u8 spd_map[4]); + +#endif /* _GM965_H_ */ diff --git a/src/northbridge/intel/gm965/gma.c b/src/northbridge/intel/gm965/gma.c new file mode 100644 index 00000000000..8e3cc55c40f --- /dev/null +++ b/src/northbridge/intel/gm965/gma.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gm965.h" +#include "chip.h" + +#define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ + +static void gma_func0_init(struct device *dev) +{ + intel_gma_init_igd_opregion(); + + /* Unconditionally reset graphics */ + pci_write_config8(dev, GDRST, 1); + udelay(50); + pci_write_config8(dev, GDRST, 0); + /* wait for device to finish */ + while (pci_read_config8(dev, GDRST) & 1) + ; + + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); +} + +/* This doesn't reclaim stolen UMA memory, but IGD could still + be re-enabled later. */ +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = __pci_0_00_0; + + pci_write_config16(dev, GCFGC_OFFSET, 0xa00); + pci_write_config16(dev_host, D0F0_GGC, (1 << 1)); + + pci_and_config32(dev_host, D0F0_DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); + + dev->enabled = 0; +} + +static void gma_func1_init(struct device *dev) +{ + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); +} + +static void gma_generate_ssdt(const struct device *device) +{ + const struct northbridge_intel_gm965_config *chip = device->chip_info; + + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); +} + +static void gma_func0_read_resources(struct device *dev) +{ + /* Set Untrusted Aperture Size to 256MB */ + pci_update_config8(dev, MSAC, ~0x3, 0x2); + + pci_dev_read_resources(dev); +} + +static const char *gma_acpi_name(const struct device *dev) +{ + return "GFX0"; +} + +static struct device_operations gma_func0_ops = { + .read_resources = gma_func0_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .acpi_fill_ssdt = gma_generate_ssdt, + .vga_disable = gma_func0_disable, + .ops_pci = &pci_dev_ops_pci, + .acpi_name = gma_acpi_name, +}; + +static struct device_operations gma_func1_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func1_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short gm965_gma_func0_ids[] = { + PCI_DID_GM965_IGD, /* 0x2A02 - Mobile Intel GM965/GL960 Express Integrated Graphics */ + 0 +}; + +static const unsigned short gm965_gma_func1_ids[] = { + PCI_DID_GM965_IGD_1, /* 0x2A03 - Mobile Intel GM965/GL960 Express Integrated Graphics (alt) */ + 0 +}; + +static const struct pci_driver gm965_gma_func0_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VID_INTEL, + .devices = gm965_gma_func0_ids, +}; + +static const struct pci_driver gm965_gma_func1_driver __pci_driver = { + .ops = &gma_func1_ops, + .vendor = PCI_VID_INTEL, + .devices = gm965_gma_func1_ids, +}; diff --git a/src/northbridge/intel/gm965/igd.c b/src/northbridge/intel/gm965/igd.c new file mode 100644 index 00000000000..9c3406c7833 --- /dev/null +++ b/src/northbridge/intel/gm965/igd.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - IGD Init + * + * Reverse-engineered from ThinkPad X61 Phoenix BIOS bioscode_7.rom, + * function at file offsets 0x36C0-0x39D1 (PEG negotiation + IGD setup). + * + * The vendor code accumulates flags in a byte (cs:0x3608) during PEG + * link training. Bits [5:4] both set means PEG is absent or failed + * link training -- i.e., IGD-only mode. The subsequent IGD init at + * offset 0x3850 uses those flags to select one of two paths: + * + * - PEG+IGD path (flags[5:4] != 0x30): PEG present and trained. + * Sets PM_F10 bit 0, programs IGD scheduling (0x1190/0x119E). + * + * - IGD-only path (flags[5:4] == 0x30): No PEG, IGD only. + * Writes HSync/VSync (BD0=0xFD), computes display clock from a + * VCO/FSB table and writes D2:F0 config 0xCC, sets PM_CTRL0 bit 31. + * + * The X61 has no discrete GPU, so it always takes the IGD-only path. + * The vendor dump confirms: BD0=0xFD, F10 bit 0 absent, no 0x1190. + */ + +#include +#include +#include +#include + +#include "gm965.h" + +/* + * Display clock table extracted from bioscode_7.rom at file offset 0x3609. + * Indexed by [vco_index][fsb_code], where: + * vco_index = ((D2:F0 config 0x1F0 >> 8) & 0x1F) - 1 + * fsb_code = HPLLVCO bits [2:0] (0=unused, 1=800MHz, 2=667MHz) + * + * Values are display clock dividers written to D2:F0 config 0xCC bits [9:0]. + */ +static const uint16_t display_clock_table[3][4] = { + /* VCO 1 */ { 200, 200, 222, 0 }, + /* VCO 2 */ { 320, 333, 333, 0 }, + /* VCO 3 */ { 400, 400, 381, 0 }, +}; + +/* + * igd_compute_ggc() - Compute GGC register value from user CMOS option + * + * Sets sysinfo->ggc based on the gfx_uma_size NVRAM option. The value + * is later written to D0:F0 offset 0x52 (GGC) by program_memory_map() + * in raminit.c so that the hardware places BSM (Base of Stolen Memory) + * at the right address below TOLUD. + * + * GM965 uses the same GMS encoding as i945. gfx_uma_size maps to the + * GMS field as (gfxsize + 1), so the default of 4 gives GMS=5=32 MB, + * matching the GM45 convention: + * + * gfx_uma_size -> GMS -> stolen size + * 0 -> 1 -> 1 MB + * 1 -> 2 -> 4 MB + * 2 -> 3 -> 8 MB + * 3 -> 4 -> 16 MB + * 4 -> 5 -> 32 MB (default, same as GM45) + * 5 -> 6 -> 48 MB + * 6 -> 7 -> 64 MB + * + * Unlike GM45, GM965 has no separate GTT stolen region (GGMS), so + * only the GMS field (bits [6:4]) is set in GGC; bits [7] and [11:8] stay 0. + * + * coreboot equivalent: igd_compute_ggc() in gm45/igd.c + */ +u16 igd_compute_ggc(void) +{ + const uint32_t deven = pci_read_config32(D0F0, D0F0_DEVEN); + + if (!(deven & DEVEN_D2F0)) { + /* IGD is not present/enabled: set IVD (bit 1), GMS = 0 */ + printk(BIOS_DEBUG, "IGD: disabled, GGC=0x0002 (no stolen memory)\n"); + return 0x0002; + } + + /* + * Read user option. Default 4 -> GMS=5 -> 32 MB, matching the + * GM45 convention. Clamp to 0-6 so GMS stays within 1-7. + */ + u8 gfxsize = get_uint_option("gfx_uma_size", 4); + if (gfxsize > 6) { + printk(BIOS_WARNING, "IGD: gfx_uma_size %u out of range, " + "using default (32 MB)\n", gfxsize); + gfxsize = 4; + } + + const u8 gms = gfxsize + 1; + const u16 ggc = (u16)(gms << 4); + + printk(BIOS_DEBUG, "IGD: gfx_uma_size=%u GMS=%u GGC=0x%04x (%u MB stolen)\n", + gfxsize, gms, ggc, + decode_igd_memory_size(gms) >> 10); + + return ggc; +} + +/* + * gm965_igd_init() - Configure Integrated Graphics Device + * + * Must be called after gm965_pm_init() and PEG/PCIe init. + * Vendor BIOS: bioscode_7.rom PEG negotiation (0x36C0) flows into + * IGD init (0x3850). + */ +void gm965_igd_init(const sysinfo_t *si) +{ + const uint32_t deven = pci_read_config32(D0F0, D0F0_DEVEN); + const int peg_enabled = (deven & DEVEN_D1F0) && + (pci_read_config16(D1F0, 0x00) != 0xffff); + + printk(BIOS_DEBUG, "GM965 IGD init: DEVEN=0x%08x PEG %s\n", + deven, peg_enabled ? "present" : "absent"); + + if (peg_enabled) { + /* + * PEG+IGD path: PEG device present and trained. + * Vendor: offset 0x3872-0x38D4 (flags[5:4] != 0x30) + * + * 1. Set PM_F10 bit 0 (IGD enable in PM controller) + * 2. Program IGD scheduling registers + */ + + /* PM_F10 |= 0x01. Vendor: offset 0x3872-0x3878 */ + mchbar_setbits8(PM_F10, 1 << 0); + + /* + * IGD scheduling registers. + * Vendor: offset 0x38A5-0x38D2 + * Conditioned on HPLLVCO bit 7 clear (always true on X61). + */ + { + const uint8_t hpllvco = mchbar_read8(HPLLVCO_MCHBAR); + if (!(hpllvco & 0x80)) { + mchbar_setbits32(IOSCHED_190, 1 << 14); + mchbar_setbits16(IOSCHED_19E, (1 << 15) | (1 << 12)); + } + } + + printk(BIOS_DEBUG, "GM965 IGD init: PEG+IGD path done " + "(F10=0x%02x)\n", mchbar_read8(PM_F10)); + } else { + /* + * IGD-only path: No PEG device (X61 case). + * Vendor: offset 0x38D7-0x39CF (flags[5:4] == 0x30) + * + * 1. Write HSync/VSync = 0xFD to MCHBAR+0xBD0/BD4 + * 2. Compute display clock from VCO/FSB table + * 3. Set PM_CTRL0 bit 31 + */ + + /* + * HSync/VSync: write 0xFD to BD0 byte 3 and BD4 byte 0. + * Vendor: offset 0x38EC-0x38FB + */ + mchbar_write32(IGD_HSYNC_VSYNC, 0xfd000000); + mchbar_write8(IGD_HSYNC_VSYNC + 4, 0xfd); + + /* + * Display clock computation. + * Vendor: offset 0x3901-0x3944 + * + * The Phoenix helper encodes access width in DX upper bits: + * dx=0x01F0 = WORD read from offset 0xF0 (bit 8 = word) + * So the vendor reads VCO from D2:F0 config 0xF0 (GCFGC) + * bits[12:8], NOT 0x1F0. GCFGC is in standard PCI config + * space and is accessible at romstage (D2F0 enabled in DEVEN). + * It's the same register raminit's program_gcfgc() writes. + * + * fsb_bits comes from HPLLVCO (MCHBAR+0x0C0F) bits[2:0]. + * + * index = (vco_field - 1) * 4 + fsb_bits + * clock_val = display_clock_table[vco_field - 1][fsb_bits] + * D2:F0 config 0xCC = (old & 0xFC00) | clock_val + */ + { + const uint16_t gcfgc = pci_read_config16(D2F0, GCFGC_OFFSET); + const uint8_t hpllvco = mchbar_read8(HPLLVCO_MCHBAR); + const unsigned int vco_field = (gcfgc >> 8) & 0x1f; + const unsigned int fsb_bits = hpllvco & 0x07; + + printk(BIOS_DEBUG, "GM965 IGD: GCFGC=0x%04x " + "HPLLVCO=0x%02x VCO=%d FSB=%d\n", + gcfgc, hpllvco, vco_field, fsb_bits); + + if (vco_field >= 1 && vco_field <= 3 && fsb_bits <= 3) { + const uint16_t clock_val = + display_clock_table[vco_field - 1][fsb_bits]; + + if (clock_val) { + uint16_t cc = pci_read_config16(D2F0, 0xcc); + cc = (cc & 0xfc00) | clock_val; + pci_write_config16(D2F0, 0xcc, cc); + + printk(BIOS_DEBUG, "GM965 IGD: display clock " + "= %d (VCO=%d FSB=%d)\n", + clock_val, vco_field, fsb_bits); + } + } else if (vco_field == 7) { + /* + * VCO field 7: special case handled by raminit's + * program_gcfgc() which programs MCHBAR 0x1190/119E + * instead. No display clock write needed here. + */ + printk(BIOS_DEBUG, "GM965 IGD: VCO=7, display " + "clock handled by raminit\n"); + } else { + printk(BIOS_WARNING, "GM965 IGD: unexpected " + "VCO=%d FSB=%d, skipping display clock\n", + vco_field, fsb_bits); + } + } + + /* + * PM_CTRL0 bit 31. + * Vendor: offset 0x3A46-0x3A5C + * Set only on IGD-only path (not when PEG is present). + */ + mchbar_setbits32(PM_CTRL0, 1 << 31); + + printk(BIOS_DEBUG, "GM965 IGD init: IGD-only path done " + "(BD0=0x%08x CTRL0=0x%08x)\n", + mchbar_read32(IGD_HSYNC_VSYNC), + mchbar_read32(PM_CTRL0)); + } +} diff --git a/src/northbridge/intel/gm965/memmap.c b/src/northbridge/intel/gm965/memmap.c new file mode 100644 index 00000000000..db6e46e0b89 --- /dev/null +++ b/src/northbridge/intel/gm965/memmap.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gm965.h" + +/* + * Decode the Graphics Mode Select (GMS) field of the GGC register to the + * corresponding stolen memory size in kilobytes. + * + * GM965 uses the same GMS encoding as i945 (bits [6:4] of D0:F0 offset 0x52): + * 0 = 0 MB (no stolen memory / IGD disabled) + * 1 = 1 MB + * 2 = 4 MB + * 3 = 8 MB + * 4 = 16 MB + * 5 = 32 MB + * 6 = 48 MB + * 7 = 64 MB + * + * Unlike GM45, GM965 has no separately configurable GTT stolen region (GGMS). + */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 }; + + if (gms >= ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +/* Decodes TSEG region size in bytes. */ +u32 decode_tseg_size(u8 esmramc) +{ + if (!(esmramc & 1)) + return 0; + switch ((esmramc >> 1) & 3) { + case 0: + return 1 * MiB; + case 1: + return 2 * MiB; + case 2: + return 8 * MiB; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +static uintptr_t northbridge_get_tseg_base(void) +{ + const pci_devfn_t dev = D0F0; + const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); + u32 tor; + + /* + * Like i945, gm965 has no separate configurable GTT stolen region. + * BSM (Base of Stolen Memory) in the IGD device directly encodes + * the base of all UMA-stolen memory, so use it when the IGD is + * enabled. Fall back to TOLUD when the IGD is disabled. + */ + if (pci_read_config32(dev, D0F0_DEVEN) & DEVEN_D2F0) + tor = pci_read_config32(D2F0, D2F0_BSM); + else + tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; + + tor -= decode_tseg_size(esmramc); + return tor; +} + +static size_t northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc); +} + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB alignment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +uintptr_t cbmem_top_chipset(void) +{ + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); +} + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. + */ + const uintptr_t top_of_ram = cbmem_top(); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); +} diff --git a/src/northbridge/intel/gm965/northbridge.c b/src/northbridge/intel/gm965/northbridge.c new file mode 100644 index 00000000000..e5590370800 --- /dev/null +++ b/src/northbridge/intel/gm965/northbridge.c @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "gm965.h" + +static uint64_t get_touud(void) +{ + uint64_t touud = pci_read_config16(__pci_0_00_0, D0F0_TOUUD); + touud <<= 20; + return touud; +} + +static void mch_domain_read_resources(struct device *dev) +{ + u64 tom, touud; + u32 tolud; + int idx = 3; + + /* Total Memory 2GB example (32MB UMA, 2MB TSEG): + * + * 00000000 0000MB-2012MB 2012MB RAM (writeback) + * 7dc00000 2012MB-2014MB 2MB TSEG (cbmem_top aligned down to 4MB) + * 7de00000 2014MB-2016MB (alignment gap) + * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached, BSM=0x7e000000) + * 80000000 2048MB TOLUD + * 80000000 2048MB TOM + * + * Total Memory 4GB example (32MB UMA, 2MB TSEG): + * + * 00000000 0000MB-3038MB 3038MB RAM (writeback) + * bdc00000 3036MB-3038MB 2MB TSEG + * be000000 3040MB-3072MB 32MB GFX UMA (uncached, BSM=0xbe000000) + * be000000 3072MB TOLUD + * 100000000 4096MB TOM + * 100000000 4096MB-5120MB 1024MB RAM (writeback) + * 140000000 5120MB TOUUD + * + * Note: unlike GM45, gm965 has no separately configurable GTT stolen + * region (GGMS). BSM directly encodes the base of UMA stolen memory. + */ + + pci_domain_read_resources(dev); + + struct device *mch = __pci_0_00_0; + + /* Top of Upper Usable DRAM, including remap */ + touud = get_touud(); + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; + tolud <<= 16; + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; + tom <<= 27; + + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", + touud, tolud, tom); + + /* Report lowest memory region */ + ram_range(dev, idx++, 0, 0xa0000); + + /* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: Legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_from_to(dev, idx++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, idx++, 0xc0000, 1*MiB); + + /* Report < 4GB memory */ + ram_range(dev, idx++, 1*MiB, cbmem_top()); + + /* TSEG */ + uintptr_t tseg_base; + size_t tseg_size; + smm_region(&tseg_base, &tseg_size); + mmio_range(dev, idx++, tseg_base, tseg_size); + + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tseg_base as unusable */ + if (cbmem_top() < tseg_base) { + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n", + tseg_base - cbmem_top()); + mmio_from_to(dev, idx++, cbmem_top(), tseg_base); + } + + /* graphic memory above TSEG */ + if (tseg_base + tseg_size < tolud) + mmio_from_to(dev, idx++, tseg_base + tseg_size, tolud); + + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + upper_ram_end(dev, idx++, touud); + + mmconf_resource(dev, idx++); +} + +static void mch_domain_set_resources(struct device *dev) +{ + struct resource *resource; + int i; + + for (i = 3; i <= 9; ++i) { + /* Report read resources. */ + resource = probe_resource(dev, i); + if (resource) + report_resource_stored(dev, resource, ""); + } + + assign_resources(dev->downstream); +} + +static void mch_domain_init(struct device *dev) +{ + struct device *mch = __pci_0_00_0; + + /* Enable SERR */ + pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); +} + +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (!is_pci_dev_on_bus(dev, 0)) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + +void northbridge_write_smram(u8 smram) +{ + struct device *dev = __pci_0_00_0; + + pci_write_config8(dev, D0F0_SMRAM, smram); +} + +static void set_above_4g_pci(const struct device *dev) +{ + const uint64_t touud = get_touud(); + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; + + const char *scope = acpi_device_path(dev); + acpigen_write_scope(scope); + acpigen_write_name_qword("A4GB", touud); + acpigen_write_name_qword("A4GS", len); + acpigen_pop_len(); + + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); +} + +static void pci_domain_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + set_above_4g_pci(dev); +} + +struct device_operations gm965_pci_domain_ops = { + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .init = mch_domain_init, + .scan_bus = pci_host_bridge_scan_bus, + .acpi_fill_ssdt = pci_domain_ssdt, + .acpi_name = northbridge_acpi_name, +}; + +struct device_operations gm965_cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = mp_cpu_bus_init, +}; + +static void gm965_init(void *const chip_info) +{ + int dev, fn, bit_base; + + struct device *const d0f0 = __pci_0_00_0; + + /* Always hide ME devices */ + pci_and_config32(d0f0, D0F0_DEVEN, ~(DEVEN_D3F0 | DEVEN_D3F1 | DEVEN_D3F2 | DEVEN_D3F3)); + + /* Hide internal functions based on devicetree info. */ + for (dev = 2; dev > 0; --dev) { + switch (dev) { + case 2: /* IGD */ + fn = 1; + bit_base = 3; + break; + case 1: /* PEG */ + fn = 0; + bit_base = 1; + break; + } + for (; fn >= 0; --fn) { + const struct device *const d = pcidev_on_root(dev, fn); + if (!d || d->enabled) + continue; + pci_and_config32(d0f0, D0F0_DEVEN, ~(1 << (bit_base + fn))); + } + } + + /* Initialize PEG port if enabled */ + struct device *peg = pcidev_on_root(1, 0); + if (peg && peg->enabled) + gm965_pcie_init(peg); +} + +struct chip_operations northbridge_intel_gm965_ops = { + .name = "Intel GM965 Northbridge", + .init = gm965_init, +}; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/northbridge/intel/gm965/pcie.c b/src/northbridge/intel/gm965/pcie.c new file mode 100644 index 00000000000..35f4439b1ba --- /dev/null +++ b/src/northbridge/intel/gm965/pcie.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - PEG Port Initialization + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * BIOS references: + * bioscode_7.rom @ 0x03FC - MOV EAX, 0x80000800 (D1:F0 PCI config access) + * bioscode_5.rom - heavy PCI configuration (includes PEG setup) + * + * This file handles the PCI Express Graphics (PEG) port at D1:F0. + * The X61 may or may not have PEG active (it has integrated graphics, + * but the PEG port exists for potential docking station / external GPU). + * + * The init_pcie() and setup_aspm() PEG portions were previously + * missing from dmi.c. This file completes the coreboot gm45_late_init() + * equivalent by implementing the PEG-specific parts. + * + * Reference: coreboot GM45 pcie.c (init_pcie, setup_aspm PEG portion) + */ + +#include +#include +#include + +#include "gm965.h" + +/* ================================================================== */ +/* PEG Port Initialization */ +/* ================================================================== */ + +/* + * init_pcie() - Configure PEG port (D1:F0) + * + * Programs link width, slot capabilities, GPE enables, and + * virtual channel configuration for the PEG port. + * + * On the X61, PEG is typically not used (integrated GPU only), + * but the BIOS still touches D1:F0 if DEVEN bit 1 is set. + * + * coreboot equivalent: init_pcie() in gm45/pcie.c + */ +static void init_pcie(struct device *peg) +{ + /* + * Set negotiated link width. + * Register 0x224 bits [4:0] = max link width. + * Bit 0 = link valid. + * The X61 doesn't use SDVO over PEG, so if PEG is active + * it would be x16. + * + * coreboot: (peg_x16 ? 16 : 0) | 1 + * For X61 with PEG enabled, assume x16 (no SDVO). + */ + pci_update_config8(peg, PEG_NEGWIDTH, ~0x1f, 16 | 1); /* x16, link valid */ + + /* Clear bit 8 of 0x224 (16-bit access) */ + pci_and_config16(peg, PEG_NEGWIDTH, ~(1 << 8)); + + /* + * Slot configuration. + * coreboot uses devicetree to determine if PEG is a slot. + * The X61 PEG is not an exposed slot - it's either unused + * or connected to a fixed device (docking station GPU). + * Don't set slot-implemented bit. + */ + + /* + * Slot power limits and slot number. + * Use slot 0 (NB PEG), power = 75W (val=75, exp=0). + * coreboot: slot 0 reserved for NB PEG, SB slots count from 1. + */ + { + uint32_t slotcap; + slotcap = (0 << SLOTCAP_SLOTNUM_SHIFT) | + (0 << SLOTCAP_POWER_SCALE_SHIFT) | + (75 << SLOTCAP_POWER_LIMIT_SHIFT); + pci_write_config32(peg, PEG_SLOTCAP, slotcap); + } + + /* + * Enable GPE (General Purpose Events) on PEG lane changes. + * Register 0xEC bits [2:0] = GPE enables. + * coreboot sets all 3 GPE bits. + */ + pci_or_config8(peg, PEG_PEGLC, PEGLC_GPE_EN_ALL); + + /* + * VC0: TC0 only. + * Clear all TC bits except TC0 in VC0 Resource Control. + */ + pci_and_config8(peg, D1F0_VC0RCTL, 1); + + /* + * Extended VC count: clear VC count field (VC0 only). + * Register 0x104 bits [2:0] = extended VC count. + */ + pci_and_config8(peg, D1F0_VCCAP, ~7); +} + +/* ================================================================== */ +/* PEG ASPM Setup */ +/* ================================================================== */ + +/* + * setup_peg_aspm() - Configure ASPM prerequisites on PEG port + * + * Programs numerous stepping-dependent registers on D1:F0 to + * prepare the PEG port for Active State Power Management. + * + * The X61 shipped with B2+ stepping silicon, so we take the + * B2+ code paths consistently. + * + * coreboot equivalent: setup_aspm() PEG portions in gm45/pcie.c + */ +static void setup_peg_aspm(struct device *peg) +{ + /* Set bits [14:13] in register 0x200 */ + pci_or_config32(peg, 0x200, 3 << 13); + + /* Clear bits [27:26] in register 0x0f0 */ + pci_and_config32(peg, 0x0f0, ~((1 << 27) | (1 << 26))); + + /* Set bits [25:24] in register 0x0f0 */ + pci_or_config32(peg, 0x0f0, 3 << 24); + + /* Clear bit 4 in register 0x0f4 */ + pci_and_config32(peg, 0x0f4, ~(1 << 4)); + + /* Set bit 0 in register 0x0fc */ + pci_or_config32(peg, 0x0fc, 1 << 0); + + /* Set bit 1 in register 0x0fc */ + pci_or_config32(peg, 0x0fc, 1 << 1); + + /* Set bit 4 in register 0x0fc */ + pci_or_config32(peg, 0x0fc, 1 << 4); + + /* Clear bits [7:5] in register 0x0fc */ + pci_and_config32(peg, 0x0fc, ~(7 << 5)); + + /* Enable L0s + L1 in LCTL (register 0x0b0) */ + pci_or_config32(peg, 0x0b0, 3 << 0); + + /* Set bits [25:24] in register 0x0f0 again (after LCTL) */ + pci_or_config32(peg, 0x0f0, 3 << 24); + + /* + * Stepping-dependent PEG ASPM (cf. GM45 setup_aspm). + * GM965 rev mapping: 0=A0, 1=A1, 2=B0, 3=C0. + * GM45 pattern: B0-B1 set bits, B2+ clear bits. + * GM965 C0 (rev 3) is equivalent to GM45 B2+. + */ + { + uint8_t stepping = pci_read_config8(__pci_0_00_0, 0x08); + + /* 0x0f0 bit 31: B0 only (rev==2) set, B2+/C0 (rev>=3) clear */ + if (stepping == 0x02) + pci_or_config32(peg, 0x0f0, 1 << 31); + else if (stepping >= 0x03) + pci_and_config32(peg, 0x0f0, ~(1 << 31)); + + /* 0x0fc bit 10: B0 only (rev==2) set, B2+/C0 (rev>=3) clear */ + if (stepping == 0x02) + pci_or_config32(peg, 0x0fc, 1 << 10); + else if (stepping >= 0x03) + pci_and_config32(peg, 0x0fc, ~(1 << 10)); + + /* 0x0fc bit 14: B2+/C0 (rev>=3) set */ + if (stepping >= 0x03) + pci_or_config32(peg, 0x0fc, 1 << 14); + + /* 0x0fc bit 13: B1+ (rev>=1) clear */ + if (stepping >= 0x01) + pci_and_config32(peg, 0x0fc, ~(1 << 13)); + } + + /* + * PEG ASPM extended registers. + * These mirror the DMI ASPM config pattern. + */ + + /* Clear bit 15 in register 0xa08 */ + pci_and_config32(peg, 0xa08, ~(1 << 15)); + + /* Set bit 8 in register 0xa84 */ + pci_or_config32(peg, 0xa84, 1 << 8); + + /* Clear bit 17 in register 0xb14 */ + pci_and_config32(peg, 0xb14, ~(1 << 17)); + + /* Set bits [9:8] in register 0xb00 */ + pci_or_config32(peg, 0xb00, 3 << 8); + + /* Set bits [5:3] in register 0xb00 */ + pci_or_config32(peg, 0xb00, 7 << 3); + + /* Clear then set bit 8 in register 0xa84 */ + pci_and_config32(peg, 0xa84, ~(1 << 8)); + pci_or_config32(peg, 0xa84, 1 << 8); + + /* Register 0xb04: set bits [27:23] = 0x0e, set bit 31 */ + pci_update_config32(peg, 0xb04, ~(0x1f << 23), (0x0e << 23) | (1 << 31)); + + /* Register 0xb04: set bits [30:29] = 01b */ + pci_update_config32(peg, 0xb04, ~(0x03 << 29), 0x01 << 29); +} + +/* ================================================================== */ +/* Public Entry Point */ +/* ================================================================== */ + +/* + * gm965_pcie_init() - Full PEG port initialization + * + * Configures the PEG port and sets up ASPM prerequisites. + * Called from chip ops .init when the PEG device is enabled. + * + * PEG RCRB registers are programmed by setup_rcrb() in dmi.c. + * + * coreboot equivalent: portions of gm45_late_init() in pcie.c + */ +void gm965_pcie_init(struct device *peg) +{ + init_pcie(peg); + setup_peg_aspm(peg); +} diff --git a/src/northbridge/intel/gm965/pm.c b/src/northbridge/intel/gm965/pm.c new file mode 100644 index 00000000000..01f83ff5e3e --- /dev/null +++ b/src/northbridge/intel/gm965/pm.c @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - Power Management Init + * + * Reverse-engineered from ThinkPad X61 Phoenix BIOS bioscode_5.rom, + * function at file offset 0x0050-0x025C (16-bit real-mode, 32-bit + * MCHBAR accesses via edi=0xFED14000 with es: segment override). + * + * This is the GM965 equivalent of GM45's init_pm() in pm.c. + * The register sequence and FSB-indexed lookup tables are + * GM965-specific and differ from GM45. + * + * Without this function, the memory controller operates without + * proper power state management, causing intermittent data + * corruption under sustained load (e.g., memtest86+ failures). + * + * Vendor BIOS calls this from bioscode_5.rom after raminit and + * DMI/PCIe init have completed, but before the payload. + */ + +#include +#include +#include +#include + +#include "gm965.h" + +#define MSR_EXTENDED_CONFIG 0xee + +/* + * FSB-indexed lookup tables extracted from bioscode_5.rom header + * at file offsets 0x04-0x4B. + * + */ + +/* HGIPMC2 upper 16 bits (written to MCHBAR+0x0C3A) */ +static const uint16_t hgipmc2_hi_table[] = { + [FSB_CLOCK_533MHz] = 0x0c3d, + [FSB_CLOCK_667MHz] = 0x0f4c, + [FSB_CLOCK_800MHz] = 0x125c, +}; + +/* HGIPMC2 lower 16 bits (written to MCHBAR+0x0C38) */ +static const uint16_t hgipmc2_lo_table[] = { + [FSB_CLOCK_533MHz] = 0x0bb8, + [FSB_CLOCK_667MHz] = 0x0ea6, + [FSB_CLOCK_800MHz] = 0x1194, +}; + +/* CLKCFG_C16 byte value (OR'd into MCHBAR+0x0C16 low 7 bits) */ +static const uint8_t clkcfg_c16_table[] = { + [FSB_CLOCK_533MHz] = 0x0b, + [FSB_CLOCK_667MHz] = 0x0d, + [FSB_CLOCK_800MHz] = 0x10, +}; + +/* C2/C3 idle timer 0 (written to MCHBAR+0x0F00) */ +static const uint32_t pm_f00_table[] = { + [FSB_CLOCK_533MHz] = 0x00000480, + [FSB_CLOCK_667MHz] = 0x00000600, + [FSB_CLOCK_800MHz] = 0x00000700, +}; + +/* C2/C3 idle timer 1 (written to MCHBAR+0x0F04) */ +static const uint32_t pm_f04_table[] = { + [FSB_CLOCK_533MHz] = 0x00001780, + [FSB_CLOCK_667MHz] = 0x00001d80, + [FSB_CLOCK_800MHz] = 0x00002380, +}; + +/* + * gm965_pm_init() - Configure MCH power management + * + * Must be called after raminit completes but before the payload. + * Vendor BIOS: bioscode_5.rom offset 0x0050, called post-raminit. + * + * Reads MCH stepping from D0:F0+0x08 and FSB clock from CLKCFG + * bits [2:0] to select stepping-dependent and clock-dependent + * register values. + */ +void gm965_pm_init(const sysinfo_t *si) +{ + const uint8_t stepping = northbridge_stepping(); + const unsigned int fsb = si->timings.fsb_clock; + + printk(BIOS_DEBUG, "GM965 PM init: stepping=0x%02x fsb=%d\n", + stepping, fsb); + + /* + * Step 1: CLKCFG_C14 = 0x0010 (16-bit write). + * If PEG device (D1:F0) is absent (reads 0xFF), OR in 0x21. + * + * Vendor: offset 0x0089-0x00A9 + * [edi+0xc14] = 0x10 + * if (D1:F0 config[0] == 0xff): [edi+0xc14] |= 0x21 + * + * (0xC14 is excluded from diff analysis per user, but we + * program it here for completeness as the vendor does.) + */ + mchbar_write16(CLKCFG_C14, 0x0010); + if (pci_read_config8(D1F0, 0x00) == 0xff) + mchbar_setbits16(CLKCFG_C14, 0x21); + + /* Step 2: CLKCFG_C20 = 0x0001. Vendor: offset 0x00AB */ + mchbar_write16(CLKCFG_C20, 0x0001); + + /* + * Step 3: UPMC3 - stepping-dependent PM control word. + * + * Vendor: offset 0x00B5-0x00F8 + * stepping 0 (A0) + NOT (FSB667 && memclk==0x30): 0x041f06fd + * stepping 1 (A1): 0x041f0efd + * stepping >= 2 (B0+): 0x061f0efd + * + * The X61 uses C0 stepping (0x03), so the B0+ path applies. + */ + if (stepping == 0x00) { + /* A0 has a special case for FSB667+memclk combo */ + mchbar_write32(UPMC3, 0x041f06fd); + } else if (stepping == 0x01) { + mchbar_write32(UPMC3, 0x041f0efd); + } else { + /* B0 and later (including C0 on X61) */ + mchbar_write32(UPMC3, 0x061f0efd); + } + + /* Step 4: GIPMC1 = 0x03 (byte). Vendor: offset 0x00FA */ + mchbar_write8(GIPMC1, 0x03); + + /* Step 5: PM_F10 |= 0x02 (set bit 1). Vendor: offset 0x0103 */ + mchbar_setbits8(PM_F10, 1 << 1); + + /* + * Step 6: HGIPMC2 upper (0xC3A) from FSB table. + * Vendor: offset 0x010C-0x0121 + */ + mchbar_write16(HGIPMC2_HI, hgipmc2_hi_table[fsb]); + + /* + * Step 7: CLKCFG_C16 - keep bit 7, set FSB-dependent value. + * Vendor: offset 0x0122-0x013B + */ + mchbar_clrsetbits8(CLKCFG_C16, 0x7f, clkcfg_c16_table[fsb]); + + /* Step 8: FSBPMC1 = 0x03 (byte). Vendor: offset 0x013C */ + mchbar_write8(FSBPMC1, 0x03); + + /* + * Step 9: HGIPMC2 lower (0xC38) from FSB table. + * Vendor: offset 0x0145-0x0155 + * + * CRITICAL: Without this, the host-graphics PM handshake + * timing is wrong (stale reset default 0x1f40 instead of + * the correct FSB-dependent value). + */ + mchbar_write16(HGIPMC2_LO, hgipmc2_lo_table[fsb]); + + /* + * Step 10: PM_F10 |= 0x20 (set bit 5). Vendor: offset 0x0156 + * + * CRITICAL: Bit 5 coordinates PM transitions with the memory + * interface. Must be set AFTER HGIPMC2 is programmed. + */ + mchbar_setbits8(PM_F10, 1 << 5); + + /* + * Step 11: CLKCFG_C16 bits [13:12] = 0x3 (set both). + * Vendor: offset 0x015F-0x0174 + * (read 16-bit, AND 0xC3FF, OR 0x3400, write 16-bit) + */ + mchbar_clrsetbits16(CLKCFG_C16, ~0xc3ffU & 0xffff, 0x3400); + + /* Step 12: PM_F60 = 0x01030419 (fixed). Vendor: offset 0x0175 */ + mchbar_write32(PM_F60, 0x01030419); + + /* + * Steps 13-14: C2/C3 idle timers from FSB table. + * Vendor: offset 0x0182-0x01A6 + */ + mchbar_write32(C2C3TT, pm_f00_table[fsb]); + mchbar_write32(C3C4TT, pm_f04_table[fsb]); + + /* + * Step 15: PM_F08 = 0x730F (16-bit, fixed). + * Vendor: offset 0x01A8 + * + * CRITICAL: This is the C-state transition timer. The reset + * default (0x0300) causes the MC to transition power states + * ~6x too fast, corrupting in-flight memory transactions + * under sustained load. + */ + mchbar_write16(PM_F08, 0x730f); + + /* Step 16: PM_F80 |= bit 31. Vendor: offset 0x01B2 */ + mchbar_setbits32(PM_F80, 1 << 31); + + /* + * Step 17: PM_CTRL0 (0x0040) - clear bits 19,13; set bits 21,9,2. + * Vendor: offset 0x01BF-0x01D2 + * + * Bit 21 is set by the vendor early-init before bioscode_5 runs + * and preserved by its RMW. GM45 pm.c also sets it explicitly + * (line 178). We set it here since coreboot's early_init doesn't. + */ + mchbar_clrsetbits32(PM_CTRL0, (1 << 19) | (1 << 13), + (1 << 21) | (1 << 9) | (1 << 2)); + + /* + * Step 18: PM_CTRL1 (0x0044) - RMW. + * Vendor: offset 0x01D3-0x01F7 + * AND 0xFEFFFFFF (clear bit 24) + * OR 0x42200020 (set bits 30,25,21,5) + * if stepping != A0: OR 0x10 (set bit 4) + */ + { + uint32_t val = mchbar_read32(PM_CTRL1); + val &= 0xfeffffff; + val |= 0x42200020; + if (stepping != 0x00) + val |= 0x10; + mchbar_write32(PM_CTRL1, val); + } + + /* + * Step 19: PM_NOCARB (0x0090) bits [2:0] = 4. + * Vendor: offset 0x01F8-0x020D + */ + mchbar_clrsetbits16(PM_NOCARB, 0x07, 0x04); + + /* + * Step 20: PM_NOCARB_HI (0x0094) - clear bit 18, set bits 29,13,11,8. + * If stepping > 1 (B0+): also set bits 5,4. + * Vendor: offset 0x020E-0x0237 + */ + mchbar_clrbits32(PM_NOCARB_HI, 1 << 18); + mchbar_setbits32(PM_NOCARB_HI, (1 << 29) | (1 << 13) | (1 << 11) | (1 << 8)); + if (stepping > 0x01) + mchbar_setbits32(PM_NOCARB_HI, (1 << 5) | (1 << 4)); + + /* + * Step 21: PM_SCHED (0x0B00) |= 0x01 (16-bit OR, set bit 0). + * Vendor: offset 0x0238 + */ + mchbar_setbits16(PM_SCHED, 1); + + /* + * Step 22: PM_SCHED_B90 (0x0B90) AND 0xFF7FFF7F (clear bits 23,7). + * Vendor: offset 0x0241 + */ + mchbar_clrbits32(PM_SCHED_B90, (1 << 23) | (1 << 7)); + + /* + * Step 23: PM_BD8 (0x0BD8) |= 0x0C (set bits 3,2). + * Vendor: offset 0x024E + */ + mchbar_setbits32(PM_BD8, 0x0c); + + /* + * Step 24: Super Low Frequency Mode (SLFM) enable. + * + * Not in bioscode_5.rom -- set by the vendor's early-init before + * bioscode_5 runs. We add it here following the GM45 pm.c pattern + * (lines 250-259). + * + * When the CPU supports SLFM (MSR 0xEE bit 27), coordinate with + * the memory controller by: + * - Setting CLKCFG bit 14 (SLFM MC coordination) + * - Clearing CLKCFG bit 7 + * - Setting PM_CTRL1 bit 31 (SLFM enable in PM controller) + * + * Without this, the CPU may autonomously enter SLFM but the MC + * doesn't compensate for the clock ratio change, causing timing + * violations on DRAM accesses. + * + * Vendor dump confirms: CLKCFG=0x4342 (bit 14 set, bit 7 clear), + * PM_CTRL1=0xC2200032 (bit 31 set). + */ + { + const int cpu_supports_slfm = + rdmsr(MSR_EXTENDED_CONFIG).lo & (1 << 27); + + if (cpu_supports_slfm) { + mchbar_clrbits16(CLKCFG_MCHBAR, 1 << 7); + mchbar_setbits16(CLKCFG_MCHBAR, 1 << 14); + mchbar_setbits32(PM_CTRL1, 1 << 31); + printk(BIOS_DEBUG, "GM965 PM: SLFM enabled " + "(CLKCFG=0x%08x, CTRL1=0x%08x)\n", + mchbar_read32(CLKCFG_MCHBAR), + mchbar_read32(PM_CTRL1)); + } else { + mchbar_clrbits16(CLKCFG_MCHBAR, 1 << 14); + mchbar_setbits16(CLKCFG_MCHBAR, 1 << 7); + mchbar_clrbits32(PM_CTRL1, 1 << 31); + printk(BIOS_DEBUG, "GM965 PM: SLFM not supported\n"); + } + } + + printk(BIOS_DEBUG, "GM965 PM init: done (UPMC3=0x%08x F08=0x%04x " + "F10=0x%02x C38=0x%04x C3A=0x%04x)\n", + mchbar_read32(UPMC3), + mchbar_read16(PM_F08), + mchbar_read8(PM_F10), + mchbar_read16(HGIPMC2_LO), + mchbar_read16(HGIPMC2_HI)); +} diff --git a/src/northbridge/intel/gm965/raminit.c b/src/northbridge/intel/gm965/raminit.c new file mode 100644 index 00000000000..39c1e63a217 --- /dev/null +++ b/src/northbridge/intel/gm965/raminit.c @@ -0,0 +1,3550 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - RAM Initialization + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * BIOS functions (RAMINIT region FFF00000-FFF03900, 55 functions): + * FFF00240 - raminit main entry (500 bytes) + * FFF01D4F - main sequencer (POST 0xFF17-0xFF43) <- actual execution path + * FFF024C9 - cold boot core (SPD -> freq -> timing -> rank count) + * FFF0200E - DIMM detect and validate (329 bytes) + * FFF02157 - frequency/multiplier selection (392 bytes) + * FFF022DF - timing parameter calculation (490 bytes) + * FFF02A7A - EPD address decode programming (1603 bytes) + * FFF03286 - channel population + EPD enable (112 bytes) + * FFF00B1F - DRAM init command sequence (88 bytes) + * FFF009AD - CLKCFG programming (188 bytes) + * FFF00A8E - DCC programming (140 bytes) + * + * BIOS functions (RAMINIT3 region FFFF3000-FFFF5700, 29 functions): + * FFFF3220 - RAMINIT3 main entry (458 bytes) + * FFFF5115 - secondary sequencer (POST 0xFF17-0xFF43) + * FFFF3C49 - RCOMP/DCC configuration (296 bytes) + * FFFF408F - DRAM timing register programming (881 bytes) + * FFFF4573 - DDR2 JEDEC EMRS1 sequence (561 bytes) + * FFFF4F9D - receive-enable training orchestrator (283 bytes) + * FFFF4E70 - per-channel REC training (3-phase) + * + * NOTE: The RAMINIT copy (FFF0xxxx) is the BIOS's actual execution + * path and contains 55 functions including EPD address decode + * programming that is critical for dual-channel operation. The + * RAMINIT3 copy (FFFF3xxx) is a stripped-down version with only 29 + * functions that omits the EPD programming entirely. This file + * was originally based on RAMINIT3 and has been augmented with the + * EPD functions from the complete RAMINIT copy. + * + * GM965 is DDR2-only (no DDR3). Two DIMMs max (1 per channel). + * + * Reference: coreboot GM45 raminit.c (DDR2 paths) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MRC cache version for GM965 */ +#define MRC_CACHE_VERSION 1 + +/* Cache structure for storing DRAM init state to SPI flash via MRC cache */ +struct gm965_mrc_cache { + uint32_t cpu_id; + uint16_t spd_crc[4]; /* Unique CRC for each DIMM slot */ + dimminfo_t dimms[4]; /* Decoded DIMM attributes */ + timings_t timings; /* Computed timings */ + uint8_t rec_coarse[2]; /* Receive-enable training coarse */ + uint8_t rec_coarse_low[2]; /* Receive-enable training coarse_low */ + uint8_t rec_fine[2]; /* Receive-enable training fine */ + uint8_t raw_spd[4][SPD_SIZE_MAX_DDR2]; /* Full SPD for identification */ +}; + +/* Read SPD unique identification bytes and compute CRC */ +static u16 spd_read_unique_crc(u8 i2c_addr) +{ + u8 spd[128] = {0}; + /* Read bytes 64-72 (9 bytes) */ + if (i2c_eeprom_read(i2c_addr, 64, 9, spd + 64) < 0) { + for (int i = 64; i <= 72; i++) + spd[i] = smbus_read_byte(i2c_addr, i); + } + /* Read bytes 93-98 (6 bytes) */ + if (i2c_eeprom_read(i2c_addr, 93, 6, spd + 93) < 0) { + for (int i = 93; i <= 98; i++) + spd[i] = smbus_read_byte(i2c_addr, i); + } + return spd_ddr2_calc_unique_crc(spd, sizeof(spd)); +} + +/* Copy cached data into sysinfo and recompute derived fields */ +static void copy_cache_to_si(sysinfo_t *si, const struct gm965_mrc_cache *cache) +{ + memcpy(si->dimms, cache->dimms, sizeof(cache->dimms)); + memcpy(&si->timings, &cache->timings, sizeof(cache->timings)); + memcpy(si->rec_coarse, cache->rec_coarse, sizeof(cache->rec_coarse)); + memcpy(si->rec_coarse_low, cache->rec_coarse_low, sizeof(cache->rec_coarse_low)); + memcpy(si->rec_fine, cache->rec_fine, sizeof(cache->rec_fine)); + memcpy(si->raw_spd, cache->raw_spd, sizeof(cache->raw_spd)); + + /* Compute dimm_count and channels */ + si->dimm_count = 0; + int ch0_pop = 0, ch1_pop = 0; + for (int i = 0; i < 4; i++) { + if (si->dimms[i].present) { + si->dimm_count++; + if (i < 2) + ch0_pop = 1; + else + ch1_pop = 1; + } + } + si->channels = (ch0_pop ? 1 : 0) + (ch1_pop ? 1 : 0); +} +/* MCHBAR_BASE needed for RCOMP table direct pointer access */ +#ifndef MCHBAR_BASE +#define MCHBAR_BASE CONFIG_FIXED_MCHBAR_MMIO_BASE +#endif + +/* + * SPD byte offsets and memory type constants are provided by + * (included via ). SPD decoding + * is handled by the common DDR2 library (spd_decode_ddr2()). + */ + +/* + * SPD slave addresses are stored in sysinfo_t.spd_addr_map, populated by + * mainboard_get_spd_map() at the start of raminit(). + * Index maps to logical DIMM slots: 0 = ch0 DIMM0, 2 = ch1 DIMM0. + * Slots 1 and 3 are kept unused on GM965. A zero entry means the slot is + * unpopulated and will be skipped. + */ + +/* ================================================================== */ +/* Timing lookup tables */ +/* ================================================================== */ + +/* + * DDR2 clock period in 1/256 ns units (matching coreboot encoding). + * Index: mem_clock_t value. + */ +/* + * DDR2 clock period in 1/256 ns units. + * Indexed by mem_clock_t: [1]=DDR2-533, [2]=DDR2-667. + * + * DDR2-533 = 266 MHz clock -> tCK = 3.75 ns = 960/256 ns + * DDR2-667 = 333 MHz clock -> tCK = 3.0 ns = 768/256 ns + */ +static const unsigned int tCK_from_clock[] = { + [MEM_CLOCK_533MT] = TCK_266MHZ, /* 3.75 ns */ + [MEM_CLOCK_667MT] = TCK_333MHZ, /* 3.0 ns */ +}; + +/* + * tRFC lookup table: indexed by [mem_clock - 1][chip_capacity]. + * Values in clock cycles = ceil(tRFC_ns / tCK_ns). + * Chip capacity: 0=256Mb, 1=512Mb, 2=1Gb, 3=2Gb. + * + * tRFC_min from JEDEC: 256Mb=75ns, 512Mb=105ns, 1Gb=127.5ns, 2Gb=195ns. + * Verified against inteltool: DRT3[20:13] = 43 for 667MT + 1Gb chips. + */ +static const unsigned int tRFC_table[2][4] = { + /* 256Mb 512Mb 1Gb 2Gb */ + /* 533MT */ { 20, 28, 34, 52 }, + /* 667MT */ { 25, 35, 43, 65 }, +}; + +/* + * tFAW fixed values per memory clock (BIOS uses fixed values, not page-dependent). + * BIOS: FFFF408F - sVar2 lookup: mc=1->14, mc=2->17, mc=3->11 + */ +static const unsigned int tFAW_fixed[] = { + [0] = 11, + [MEM_CLOCK_533MT] = 14, + [MEM_CLOCK_667MT] = 17, +}; + +/* + * CxDRT4 ROM table (BIOS file offset 0x1757D0). + * Each entry is the full register value, masked with 0x10200 (preserve bits 16,9). + * Indexed by mem_clock. + */ +static const uint32_t drt4_rom_table[] = { + [0] = 0x00000000, + [MEM_CLOCK_533MT] = 0x390c2850, + [MEM_CLOCK_667MT] = 0x414e3064, +}; + +/* + * CxDRT5 byte table (BIOS file offset 0x1757E0). + * Values go into bits [19:12] of CxDRT5. Indexed by mem_clock. + */ +static const uint8_t drt5_rom_bytes[] = { + [0] = 0x00, + [MEM_CLOCK_533MT] = 0x50, + [MEM_CLOCK_667MT] = 0x64, +}; + +/* + * CxDRT0 BtB_WtR tWTR equivalent lookup, indexed by mem_clock. + * BIOS: abStack_8[] = {2, 2, 3, 3} - used in WtR formula. + */ +static const uint8_t drt0_twtr_lut[] = { + [0] = 2, + [MEM_CLOCK_533MT] = 2, + [MEM_CLOCK_667MT] = 3, +}; + +/* ================================================================== */ +/* SPD reading and DIMM detection */ +/* ================================================================== */ + +/* + * detect_dimms() - Scan SPD and populate sysinfo DIMM structures + * + * Reads only the first 64 bytes of SPD (timing/geometry data) for + * boot speed -- manufacturer info at bytes 64-127 is not needed for + * raminit. Uses i2c_eeprom_read() block transfer where possible, + * falling back to individual smbus_read_byte() calls. The raw SPD + * data is decoded by the common DDR2 library (spd_decode_ddr2()). + * + * BIOS equivalent: FFF0200E / FFFF48A7 (POST 0xFF05-0xFF08) + * coreboot equivalent: collect_dimm_config() + */ +static void detect_dimms(sysinfo_t *si) +{ + int slot, j; + + si->dimm_count = 0; + si->channels = 0; + + for (slot = 0; slot < 4; slot++) { + dimminfo_t *d = &si->dimms[slot]; + u8 raw_spd[SPD_SIZE_MAX_DDR2] = {}; + struct dimm_attr_ddr2_st decoded; + + /* Skip slots not wired to an SPD device on this board */ + if (!si->spd_addr_map[slot]) { + d->present = 0; + continue; + } + + /* Quick presence check: read memory type byte first */ + if (smbus_read_byte(si->spd_addr_map[slot], SPD_MEMORY_TYPE) + != SPD_MEMORY_TYPE_SDRAM_DDR2) { + printk(BIOS_DEBUG, "SPD slot %d addr 0x%02x: " + "not DDR2, skipping\n", + slot, si->spd_addr_map[slot]); + d->present = 0; + continue; + } + + /* + * Read full 128 bytes of SPD. The timing/geometry data + * is in bytes 0-63, but we'll need identification fields + * from bytes 64-98 later for SMBIOS. + */ + if (i2c_eeprom_read(si->spd_addr_map[slot], 0, SPD_SIZE_MAX_DDR2, + raw_spd) != SPD_SIZE_MAX_DDR2) { + printk(BIOS_DEBUG, "SPD slot %d: i2c block read " + "failed, falling back to byte reads\n", slot); + for (j = 0; j < SPD_SIZE_MAX_DDR2; j++) + raw_spd[j] = smbus_read_byte( + si->spd_addr_map[slot], j); + } + + if (spd_decode_ddr2(&decoded, raw_spd) != SPD_STATUS_OK) { + printk(BIOS_WARNING, "DIMM%d: SPD decode failed, " + "skipping\n", slot); + d->present = 0; + continue; + } + + if (CONFIG(DEBUG_RAM_SETUP)) + dram_print_spd_ddr2(&decoded); + + /* GM965 does not support ECC or registered memory */ + if (decoded.flags.is_ecc) + die("ECC memory not supported by GM965\n"); + if (spd_dimm_is_registered_ddr2(decoded.dimm_type)) + die("Registered memory not supported by GM965\n"); + + d->present = 1; + si->dimm_count++; + + /* Geometry from decoded struct */ + d->dual_rank = (decoded.ranks > 1) ? 1 : 0; + d->rows = decoded.row_bits; + d->cols = decoded.col_bits; + d->banks = decoded.banks; + d->x16 = (decoded.width == 16) ? 1 : 0; + + /* Page size = chip_width_bytes * 2^cols */ + unsigned int chip_width_bytes = decoded.width / 8; + if (chip_width_bytes == 0) + chip_width_bytes = 1; + d->page_size = chip_width_bytes * (1 << d->cols); + + /* Rank capacity from library */ + d->rank_capacity_mb = decoded.ranksize_mb; + + /* CAS and per-CAS cycle times (already in 1/256 ns) */ + d->cas_supported = decoded.cas_supported; + memcpy(d->cycle_time, decoded.cycle_time, + sizeof(d->cycle_time)); + + /* Timing parameters in 1/256 ns from library */ + d->tRCD = decoded.tRCD; + d->tRP = decoded.tRP; + d->tRAS = decoded.tRAS; + d->tWR = decoded.tWR; + d->tRRD = decoded.tRRD; + d->tRTP = decoded.tRTP; + + printk(BIOS_DEBUG, "DIMM%d: %dMB/rank %s rows=%d cols=%d " + "banks=%d CAS=0x%02x tCK=%u (1/256 ns)\n", + slot, d->rank_capacity_mb, + d->dual_rank ? "2R" : "1R", + d->rows, d->cols, d->banks, + d->cas_supported, + d->cycle_time[spd_get_msbs(d->cas_supported)]); + + /* Save raw SPD for later SMBIOS extraction */ + memcpy(si->raw_spd[slot], raw_spd, SPD_SIZE_MAX_DDR2); + } + + if (si->dimm_count == 0) + die("No DIMMs detected (POST 0xE0)"); + + /* + * Determine channel mode. + * Ch0 = slots 0,1; Ch1 = slots 2,3. + * X61 typically has 1 slot per channel (slot 0 and slot 2). + */ + int ch0_pop = si->dimms[0].present || si->dimms[1].present; + int ch1_pop = si->dimms[2].present || si->dimms[3].present; + + if (ch0_pop && ch1_pop) { + si->channels = 2; + si->timings.channel_mode = CHANNEL_MODE_DUAL_INTERLEAVED; + } else { + si->channels = 1; + si->timings.channel_mode = CHANNEL_MODE_SINGLE; + } +} + +/* ================================================================== */ +/* Frequency and CAS latency selection */ +/* ================================================================== */ + +/* + * read_fsb_clock() - Read FSB frequency from CLKCFG register + * + * BIOS equivalent: reads MCHBAR+0xC00 bits [2:0] + */ +static fsb_clock_t read_fsb_clock(void) +{ + uint32_t clkcfg = mchbar_read32(CLKCFG_MCHBAR); + uint8_t fsb_code = clkcfg & CLKCFG_FSBCLK_MASK; + + /* GM965 FSB codes: 1=800MHz, 2=667MHz */ + switch (fsb_code) { + case 1: return FSB_CLOCK_533MHz; + case 2: return FSB_CLOCK_800MHz; + case 3: return FSB_CLOCK_667MHz; + default: return FSB_CLOCK_800MHz; + } +} + +/* + * select_frequency_and_cas() - Find highest common clock and minimum valid CAS + * + * Three-phase algorithm: + * + * Phase 1 - characterise the DIMM population. + * tCKmin_common: max(tCK_min[i]) over all DIMMs - the slowest minimum clock + * period across the population, which sets the fastest frequency every DIMM + * can sustain simultaneously. + * tAA_needed: max(max_cas[i] * tCK_min[i]) - the absolute-time lower bound + * on CAS access latency. In DDR2 a DIMM is characterised at its highest + * supported CAS running at tCK_min, so their product is the minimum tAA the + * system must honour. + * cas_mask: bitwise-AND of every DIMM's CAS latency bitmask - only CAS + * values that every DIMM in the system supports. + * + * Phase 2 - select the memory clock. + * Walk 800->667->533 MT/s; accept the first candidate where: + * (a) tCK_clock >= tCKmin_common (all DIMMs can sustain the frequency) + * (b) clock_mhz <= max_mem_mhz (within the FSB-derived ceiling) + * Clock compatibility is assessed on tCK_min alone, independently of CAS. + * + * Phase 3 - derive CAS at the chosen clock from absolute time. + * cas_needed = ceil(tAA_needed / tCK_clock) + * Then pick the lowest CAS value in cas_mask that satisfies CAS >= cas_needed. + * If no such CAS exists at this clock (rare edge case), fall back to the next + * slower clock and repeat phase 3. + * + * BIOS equivalent: FFF02157 / FFFF49F1 (POST 0xFF09-0xFF10) + * coreboot equivalent: find_common_clock_cas() + */ +static void select_frequency_and_cas(sysinfo_t *si) +{ + int slot; + unsigned int cas_mask = 0xff; /* intersected CAS bitmask */ + unsigned int tCKmin_common = 0; /* max tCK_min across DIMMs (1/256 ns) */ + unsigned int tAA_needed = 0; /* worst-case min access time (1/256 ns) */ + + si->timings.fsb_clock = read_fsb_clock(); + + /* + * Phase 1: characterise the DIMM population. + * + * Timing values are already decoded to 1/256 ns by the common + * DDR2 SPD library (spd_decode_ddr2), so no manual tCK decoding + * is needed here. + */ + for (slot = 0; slot < 4; slot++) { + dimminfo_t *d = &si->dimms[slot]; + if (!d->present) + continue; + + /* Common supported CAS set */ + cas_mask &= d->cas_supported; + + /* Highest CAS this DIMM supports */ + unsigned int max_cas = spd_get_msbs(d->cas_supported); + + /* tCK at max CAS - already in 1/256 ns from library */ + unsigned int tCK = d->cycle_time[max_cas]; + if (tCK > tCKmin_common) + tCKmin_common = tCK; + + /* + * Absolute minimum access time for this DIMM: + * tAA_min = max_cas * tCK_min (both in 1/256 ns units). + * The DIMM is rated to run max_cas at tCK_min, so this is + * the smallest tAA the controller must supply. + */ + unsigned int tAA_dimm = max_cas * tCK; + if (tAA_dimm > tAA_needed) + tAA_needed = tAA_dimm; + } + + if (cas_mask == 0) + die("No common CAS latency (POST 0xEC)"); + + /* + * Phase 2: Memory clock ceiling. + * + * EDS 3.1.37 CAPID0 bit 30 (DDR2 Frequency Capability): + * 0 = all frequencies (DDR2-667 or lower) + * 1 = DDR2-533 only + * FSB-533 also limits to DDR2-533. + */ + unsigned int max_mem_mhz; + const uint32_t capid0_lo = pci_read_config32(D0F0, 0xe0); + if ((capid0_lo & (1 << 30)) || si->timings.fsb_clock == FSB_CLOCK_533MHz) + max_mem_mhz = 266; /* DDR2-533 */ + else + max_mem_mhz = 333; /* DDR2-667 */ + + /* + * Phase 3: select clock then derive CAS from absolute time. + * Try fastest first: DDR2-667 (mc=2), then DDR2-533 (mc=1). + */ + unsigned int best_CAS = 0; + + for (int mc = MEM_CLOCK_667MT; mc >= MEM_CLOCK_533MT; mc--) { + unsigned int clock_mhz; + switch (mc) { + case MEM_CLOCK_667MT: + clock_mhz = 333; + break; + case MEM_CLOCK_533MT: + clock_mhz = 266; + break; + default: + continue; + } + + if (clock_mhz > max_mem_mhz) + continue; + + unsigned int tCK_clock = tCK_from_clock[mc]; + if (tCK_clock < tCKmin_common) + continue; /* clock faster than any DIMM can sustain */ + + /* + * Convert the absolute tAA requirement to clock cycles at + * this frequency, then find the lowest valid CAS in the + * common mask that meets or exceeds that cycle count. + */ + unsigned int cas_needed = DIV_ROUND_UP(tAA_needed, tCK_clock); + if (cas_needed < 3) + cas_needed = 3; + + for (unsigned int cas = cas_needed; cas <= 6; cas++) { + if (cas_mask & (1u << cas)) { + best_CAS = cas; + break; + } + } + + if (best_CAS) { + si->timings.mem_clock = mc; + si->timings.CAS = best_CAS; + break; + } + } + + if (!best_CAS) + die("No valid frequency/CAS combination (POST 0xEC)"); + + printk(BIOS_DEBUG, "DRAM: %s CAS%d (tCKmin_common=%u tCK=%u " + "tAA_needed=%u cas_mask=0x%02x)\n", + si->timings.mem_clock == MEM_CLOCK_667MT ? "DDR2-667" : "DDR2-533", + best_CAS, tCKmin_common, + tCK_from_clock[si->timings.mem_clock], + tAA_needed, cas_mask); +} + +/* ================================================================== */ +/* Timing parameter calculation */ +/* ================================================================== */ + +/* + * calculate_timings() - Compute DRAM timing parameters from SPD + * + * Converts SPD timing values (in ns or 1/4 ns) to clock cycles + * at the selected memory frequency. Takes the worst case across + * all populated DIMMs. + * + * BIOS equivalent: FFF022DF / FFFF4B7F (POST 0xFF11-0xFF15) + * coreboot equivalent: calculate_derived_timings() + */ +static void calculate_timings(sysinfo_t *si) +{ + int slot; + timings_t *t = &si->timings; + unsigned int tCK = tCK_from_clock[t->mem_clock]; + unsigned int tRAS_max = 0, tRP_max = 0, tRCD_max = 0; + unsigned int tWR_max = 0, tRRD_max = 0, tRTP_max = 0; + unsigned int tRFC_max = 0; + + for (slot = 0; slot < 4; slot++) { + dimminfo_t *d = &si->dimms[slot]; + if (!d->present) + continue; + + /* + * All timing values are already in 1/256 ns units, + * decoded by the common DDR2 SPD library. No manual + * conversion from raw SPD byte encodings is needed. + */ + + /* tRAS */ + if (DIV_ROUND_UP(d->tRAS, tCK) > tRAS_max) + tRAS_max = DIV_ROUND_UP(d->tRAS, tCK); + + /* tRP */ + if (DIV_ROUND_UP(d->tRP, tCK) > tRP_max) + tRP_max = DIV_ROUND_UP(d->tRP, tCK); + + /* tRCD */ + if (DIV_ROUND_UP(d->tRCD, tCK) > tRCD_max) + tRCD_max = DIV_ROUND_UP(d->tRCD, tCK); + + /* tWR */ + if (DIV_ROUND_UP(d->tWR, tCK) > tWR_max) + tWR_max = DIV_ROUND_UP(d->tWR, tCK); + + /* tRRD: minimum 2 clocks per JEDEC */ + unsigned int tRRD_clk = DIV_ROUND_UP(d->tRRD, tCK); + if (tRRD_clk < 2) + tRRD_clk = 2; + if (tRRD_clk > tRRD_max) + tRRD_max = tRRD_clk; + + /* tRTP: minimum 2 clocks per JEDEC */ + unsigned int tRTP_clk = DIV_ROUND_UP(d->tRTP, tCK); + if (tRTP_clk < 2) + tRTP_clk = 2; + if (tRTP_clk > tRTP_max) + tRTP_max = tRTP_clk; + + /* + * tRFC: from lookup table based on chip capacity. + * Chip capacity is encoded: 0=256Mb, 1=512Mb, 2=1Gb, 3=2Gb. + */ + unsigned int width_bits = (d->x16) ? 4 : 3; + unsigned int bank_bits = (d->banks == 8) ? 3 : 2; + int cap_idx = d->rows + d->cols + width_bits + bank_bits - 28; + if (cap_idx < 0) + cap_idx = 0; + if (cap_idx > 3) + cap_idx = 3; + unsigned int tRFC = tRFC_table[t->mem_clock - 1][cap_idx]; + if (tRFC > tRFC_max) + tRFC_max = tRFC; + } + + /* Bounds checking (matching BIOS fatal codes) */ + if (tRAS_max < 4 || tRAS_max > 31) + die("tRAS out of range (POST 0xE4)"); + if (tRP_max < 2 || tRP_max > 9) + die("tRP out of range (POST 0xED)"); + if (tRCD_max < 2 || tRCD_max > 9) + die("tRCD out of range (POST 0xEE)"); + if (tRFC_max > 255) + die("tRFC out of range (POST 0xEF)"); + + t->tRAS = tRAS_max; + t->tRP = tRP_max; + t->tRCD = tRCD_max; + t->tWR = tWR_max; + t->tRRD = tRRD_max; + t->tRTP = tRTP_max; + t->tRFC = tRFC_max; + + printk(BIOS_DEBUG, "Timings: CAS%u tRAS=%u tRP=%u tRCD=%u " + "tWR=%u tRFC=%u tRRD=%u tRTP=%u\n", + t->CAS, t->tRAS, t->tRP, t->tRCD, + t->tWR, t->tRFC, t->tRRD, t->tRTP); +} + +/* ================================================================== */ +/* Clock configuration programming */ +/* ================================================================== */ + +/* + * me_pll_handshake() - HECI notification before/after PLL frequency change + * + * Notifies the ME that the host is about to change the PLL (or has just + * finished), giving the ME a chance to quiesce its own clocked logic. + * + * Protocol (vendor: FFF0366A / FFF0335C): + * 1. In H_CSR: assert H_RST, clear H_RDY, trigger H_IG - tells ME a + * transition is starting. + * 2. Poll ME_CSR_HA until ME asserts its RDY bit. + * 3. If H_RDY is still clear: deassert H_RST, assert H_RDY, trigger H_IG + * to acknowledge the ME. + */ +static void me_pll_handshake(volatile uint8_t *d3bar) +{ + uint32_t h_csr; + + /* Step 1: assert reset, clear ready, interrupt ME */ + h_csr = read32(d3bar + ME_H_CSR); + h_csr = (h_csr & ~ME_CSR_RDY) | ME_CSR_RST | ME_CSR_IG; + write32(d3bar + ME_H_CSR, h_csr); + + /* Step 2: wait for ME to signal ready */ + while (!(read32(d3bar + ME_ME_CSR_HA) & ME_CSR_RDY)) + ; + + /* Step 3: restore host-ready state if needed */ + h_csr = read32(d3bar + ME_H_CSR); + if (!(h_csr & ME_CSR_RDY)) { + h_csr = (h_csr & ~ME_CSR_RST) | ME_CSR_RDY | ME_CSR_IG; + write32(d3bar + ME_H_CSR, h_csr); + } +} + +/* + * program_clkcfg_lock() - Program DRAM frequency in CLKCFG and relock PLL + * + * BIOS equivalent: FFFF4DF7 (121 bytes, POST 0xFF18), plus + * FFF009AD (PLL programming, 188 bytes) and + * FFF00A8E (DCC / UPDATE toggle, 140 bytes). + * + * GM965 CLKCFG memory clock encoding in bits [6:4]: + * DDR2-533 (mc=1) -> 3, DDR2-667 (mc=2) -> 4 + * Formula: (mem_clock + 2) << 4 + * + * Sequence: + * 1. Skip PLL relock on warm boot when frequency already matches. + * 2. On A0 stepping only: ensure bits [9:8] are set in CLKCFG. + * 3. Map D3:F0 ME BAR to 0xFED10000 and enable bus mastering. + * D3:F0 is already visible via DEVEN_D3F0 set in gm965_early_init(). + * If ME firmware is absent (D3:F0 returns 0xffff) the HECI + * handshakes are skipped; the PLL still relocks via hardware alone. + * 4. Write new mem clock to CLKCFG (UPDATE clear). + * 5. HECI handshake #1: notify ME of impending frequency change. + * 6. Perform UPDATE toggle (clear -> set -> clear) to latch frequency. + * 7. HECI handshake #2: notify ME the frequency change is complete. + */ +static void program_clkcfg_lock(const sysinfo_t *si) +{ + uint32_t clkcfg_orig = mchbar_read32(CLKCFG_MCHBAR); + uint32_t clkcfg = clkcfg_orig & ~(1 << 17); + uint32_t want_memclk = (si->timings.mem_clock + 2) << 4; + + printk(BIOS_DEBUG, "%s: CLKCFG orig=0x%08x want_memclk=0x%02x\n", + __func__, clkcfg_orig, want_memclk); + + /* + * Vendor (FFFF4DF7): A0 stepping only sets bits 9:8. + * On C0+ these bits are already set from hardware default. + */ + if (northbridge_stepping() == 0x00 + && (clkcfg_orig & 0x300) != 0x300) { + clkcfg |= 0x300; + } else if ((clkcfg_orig & CLKCFG_MEMCLK_MASK) == want_memclk + && si->s3_resume) { + /* + * Frequency already matches AND warm boot - skip PLL + * relock. On cold boot the PLL/UPDATE sequence must + * run even when the strap default equals the target + * frequency (e.g. DDR2-533 on an X61 with CLKCFG + * strap 011). + */ + printk(BIOS_DEBUG, "%s: CLKCFG freq already set (warm)\n", __func__); + return; + } + + /* Map D3:F0 BAR and enable memory + bus-master (vendor: FFF028BA) */ + /* Currently we don't enable ME in early_init.c as this code seems to choke on it */ + const bool me_active = pci_read_config16(D3F0, PCI_DEVICE_ID) != 0xffff; + volatile uint8_t *d3bar = (volatile uint8_t *)(uintptr_t)D3F0_BAR; + if (me_active) { + pci_write_config32(D3F0, PCI_BASE_ADDRESS_0, D3F0_BAR | 1); + pci_or_config8(D3F0, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } + + /* Write new frequency to CLKCFG (UPDATE clear) */ + clkcfg = (clkcfg & ~(CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK)) | want_memclk; + mchbar_write32(CLKCFG_MCHBAR, clkcfg); + + /* HECI handshake #1: notify ME before frequency change */ + if (me_active) + me_pll_handshake(d3bar); + + /* + * UPDATE toggle (vendor: FFF00A33-FFF00A46): + * 1. Write freq with UPDATE clear + * 2. Write freq with UPDATE set -> triggers HW latch + * 3. Write freq with UPDATE clear -> finalize + */ + mchbar_clrsetbits32(CLKCFG_MCHBAR, + CLKCFG_MEMCLK_MASK | CLKCFG_UPDATE, + want_memclk); + mchbar_clrsetbits32(CLKCFG_MCHBAR, + CLKCFG_MEMCLK_MASK, + want_memclk | CLKCFG_UPDATE); + mchbar_clrbits32(CLKCFG_MCHBAR, CLKCFG_UPDATE); + + /* HECI handshake #2: notify ME that frequency change is complete */ + if (me_active) + me_pll_handshake(d3bar); + + printk(BIOS_DEBUG, "%s: CLKCFG after=0x%08x\n", + __func__, mchbar_read32(CLKCFG_MCHBAR)); +} + +/* + * program_gcfgc() - Program IGD render/sampler clocks in GCFGC register + * + * BIOS equivalent: FFFF3844 (197 bytes, POST 0xFF19) + * Despite the post code label, this function programs the IGD's GCFGC + * register (D2:F0 offset 0xF0), NOT the MCHBAR CLKCFG register. + * CLKCFG is handled by the inline code at POST 0xFF18. + * + * HPLLVCO field == 7 is a special case: programs MCHBAR+0x1190/0x119E + * instead of GCFGC. + */ +static void program_gcfgc(const sysinfo_t *si) +{ + /* bits 44:42 of CAPID0, which are "GFX Software Capability ID" */ + uint8_t hpllvco = pci_read_config8(D0F0, 0xe5); + uint8_t vco_field = (hpllvco >> 2) & 7; + + if (vco_field == 7) { + /* + * Special case: VCO field 7 means no standard GCFGC programming. + * BIOS: if D0F0 revision (offset 0x08) == 0, configure + * MCHBAR scheduling registers instead. + */ + if (pci_read_config8(D0F0, PCI_REVISION_ID) == 0) { + mchbar_setbits16(IOSCHED_190, 0x4000); + mchbar_clrsetbits16(IOSCHED_19E, 0xe000, 0x8000); + mchbar_setbits16(IOSCHED_19E, 0x1000); + } + return; + } + + /* Set MCHBAR_FFC bit 24 for non-special VCO */ + mchbar_setbits32(MCHBAR_FFC, 1 << 24); + + /* + * GCFGC render clock encoding (BIOS): + * FSB=800: 800MT->2, 667MT->3, 533MT->4 + * FSB=667: always 5 + * HPLLVCO_field==3 override: 4 + * + * GCFGC byte 0 bits [3:0] = render clock, byte 1 bits [4:0] = display clock + * (fixed 2 for 320/333 MHz) + */ + uint8_t gcfgc_render = 5; /* default for FSB 667 */ + + if (si->timings.fsb_clock == FSB_CLOCK_800MHz) { + switch (si->timings.mem_clock) { + case MEM_CLOCK_533MT: + gcfgc_render = 4; + break; + case MEM_CLOCK_667MT: + gcfgc_render = 3; + break; + } + } + + /* VCO field 3 forces render clock to 4 */ + if (vco_field == 3) + gcfgc_render = 4; + + /* + * Vendor BIOS sequence: + * GCFGC[0] = (GCFGC[0] & 0xd0) | render + * GCFGC[0] |= 0x20 + * GCFGC[0] &= 0xdf + * GCFGC[1] = (GCFGC[1] & 0xe0) | 2 + * + * The bit 5 pulse on GCFGC[0] is required to latch the render + * clock change before programming the display clock. + */ + pci_update_config8(D2F0, GCFGC_OFFSET, ~0x2f, gcfgc_render); + pci_or_config8(D2F0, GCFGC_OFFSET, 0x20); + pci_update_config8(D2F0, GCFGC_OFFSET, ~0x20, 0); + pci_update_config8(D2F0, GCFGC_OFFSET + 1, ~0x1f, 2); /* cdclk of 320/333 MHz */ +} + +/* ================================================================== */ +/* IGD memory frequency / clock crossing setup */ +/* ================================================================== */ + +/* + * Clock crossing ROM tables for POST 0xFF20. + * Table 1 writes to MCHBAR+0x0208/0x020C (CLKCROSS_DATA3/DATA2). + * Table 2 writes to MCHBAR+0x1258/0x125C and 0x1358/0x135C (per-channel crossing). + * Indexed by [mem_clock][fsb_clock], 2 DWORDs per entry. + * + * Extracted from BIOS ROM at file offsets 0x175868 and 0x1757E8. + * ROM index formula: mc + fsb * 4 (NOT fsb + mc * 4). + * Each entry is 2 DWORDs; stride 4 per FSB row, 1 per mc column. + */ +static const uint32_t clkcross_table1[][4][3] = { + [MEM_CLOCK_533MT] = { + [FSB_CLOCK_533MHz] = { 0x000300c0, 0x0030000c }, /* vendor ROM idx=5 (1:1 rate) */ + [FSB_CLOCK_667MHz] = { 0x00070300, 0x00e00018 }, /* vendor ROM idx=13 */ + [FSB_CLOCK_800MHz] = { 0x00070e00, 0x01c00038 }, /* vendor ROM idx=9 + inteltool */ + }, + [MEM_CLOCK_667MT] = { + [FSB_CLOCK_533MHz] = { 0x00000000, 0x00000000 }, /* vendor ROM idx=6 (zeros, N/A on X61) */ + [FSB_CLOCK_667MHz] = { 0x000300c0, 0x0030000c }, /* vendor ROM idx=14 (1:1 rate) */ + [FSB_CLOCK_800MHz] = { 0x00030e00, 0x0070000c }, /* vendor ROM idx=10 + inteltool */ + }, +}; + +static const uint32_t clkcross_table2[][4][3] = { + [MEM_CLOCK_533MT] = { + [FSB_CLOCK_533MHz] = { 0x00100401, 0x00000000 }, /* vendor ROM idx=5 (1:1 rate) */ + [FSB_CLOCK_667MHz] = { 0x10080201, 0x00000040 }, /* vendor ROM idx=13 */ + [FSB_CLOCK_800MHz] = { 0x00020108, 0x00000000 }, /* vendor ROM idx=9 + inteltool */ + }, + [MEM_CLOCK_667MT] = { + [FSB_CLOCK_533MHz] = { 0x00000000, 0x00000000 }, /* vendor ROM idx=6 (zeros, N/A on X61) */ + [FSB_CLOCK_667MHz] = { 0x00100401, 0x00000000 }, /* vendor ROM idx=14 (1:1 rate) */ + [FSB_CLOCK_800MHz] = { 0x00040210, 0x00000000 }, /* vendor ROM idx=10 + inteltool */ + }, +}; + +/* + * set_clkcross_frequencies() - Program clock crossing timings + * + * BIOS equivalent: FFFF392E (140 bytes, POST 0xFF20) + * Writes clock crossing values from ROM tables into MCHBAR registers. + * Also handles 667MT+FSB667 special case (MCHBAR+0x0210 = 0x180). + */ +static void set_clkcross_frequencies(const sysinfo_t *si) +{ + unsigned int mc = si->timings.mem_clock; + unsigned int fsb = si->timings.fsb_clock; + + /* Write clock crossing data to MCHBAR+0x0208/0x020C */ + mchbar_write32(CLKCROSS_DATA3, clkcross_table1[mc][fsb][0]); + mchbar_write32(CLKCROSS_DATA2, clkcross_table1[mc][fsb][1]); + + /* Special case: 667MT + FSB800 -> MCHBAR+0x0210 = 0x180 */ + if (mc == MEM_CLOCK_667MT && fsb == FSB_CLOCK_800MHz) + mchbar_write32(CLKCROSS_DATA1, 0x180); + + /* + * Per-channel clock crossing registers at MCHBAR+0x1258/0x125C + * and 0x1358/0x135C. + * Vendor (FFFF392E) writes to 0xfed15258 = MCHBAR+0x1258. + * Verified: inteltool 0x1258 = 0x00040210 matches table value. + */ + int ch; + for (ch = 0; ch < 2; ch++) { + mchbar_write32(0x1258 + ch * 0x100, clkcross_table2[mc][fsb][0]); + mchbar_write32(0x125c + ch * 0x100, clkcross_table2[mc][fsb][1]); + } +} + +/* ================================================================== */ +/* Pre-JEDEC memory map (temporary) */ +/* ================================================================== */ + +/* + * prejedec_memory_map() - Set up temporary memory map for JEDEC init + * + * Programs CxDRBy with 128MB per rank (dummy) so JEDEC commands can + * be addressed to each rank. + * + * BIOS equivalent: FFFF3EC7 with param=1 (POST 0xFF22) + * coreboot equivalent: prejedec_memory_map() + */ +static void prejedec_memory_map(sysinfo_t *si) +{ + int ch, s; + /* + * Vendor (FFF01278 with param=1) iterates 4 DIMM slots in a + * single loop. Per slot it interleaves 16-bit DRB writes with + * 8-bit DRA writes in a specific order: + * + * write16 DRB[rank_even] (rank 0 or 2 boundary) + * if dual_rank: + * write8 DRA[slot] (full DRA value) + * boundary += rank_size (advance for rank 1/3) + * else: + * dra &= 0x0F (mask to lower nibble) + * write8 DRA[slot] (always, 2nd write for dual) + * write16 DRB[rank_odd] (rank 1 or 3 carry-forward) + * + * Boundary accumulates across both channels; reset to 0 only + * when ch1 has DIMMs (each channel gets its own address space). + * + * rank_size = 4 << banks_shift (ROM base=4 at FFF038B4) + * dra_base = 0x22 (ROM value at FFF038B8) + */ + uint8_t boundary = 0; + + for (ch = 0; ch < 2; ch++) { + /* + * RAMINIT (FFF0133E) resets boundary for ch1 because its + * JEDEC init uses I/O port commands (no address targeting). + * + * RAMINIT3 (FFFF3EC7) does NOT reset when ch1 is populated + * and it's pre-JEDEC, because its JEDEC init (FFFF4573) uses + * DCC + memory-read rank targeting - the read address must + * fall in the correct rank's global address range. + * + * Our jedec_init_ddr2() uses the DCC approach (like RAMINIT3), + * so ch1 DRBs must be global cumulative for get_rank_addr() + * to produce correct addresses. Without this, ch1 rank 1 + * would be addressed at DRB(1,0)<<25 = 128MB, targeting + * ch0 rank 1 instead of ch1 rank 1 at 384MB. + */ + + for (s = 0; s < 2; s++) { + int slot = ch * 2 + s; + uint8_t rank_size = 0; + uint8_t dra = 0; + + if (slot < 4 && si->dimms[slot].present) { + /* + * Vendor (FFF01282) always uses the first ROM table + * entry (rank_size=4, dra=0x22) for pre-JEDEC, + * regardless of bank count. Each rank gets 128 MB + * of address space, which is enough for JEDEC MRS + * targeting via DRB-based rank decode. + */ + rank_size = 4; + dra = 0x22; /* ROM table at FFF037D8 */ + } + + /* Step 1: write16 DRB rank_even boundary */ + boundary += rank_size; + mchbar_write16(CxDRBy_MCHBAR(ch, s * 2), boundary); + + /* + * Steps 2-3: DRA writes. + * + * Dual-rank (FFF012FF-01308): write DRA, advance + * boundary, then write DRA again at the common + * exit (FFF01319). + * + * Single-rank (FFF0130F): mask DRA to lower nibble, + * then write once at FFF01319. + * + * Empty: DRA=0, rank_size=0, one write of 0. + */ + if (slot < 4 && si->dimms[slot].present + && si->dimms[slot].dual_rank) { + mchbar_write8(CxDRA_MCHBAR(ch) + s, dra); + boundary += rank_size; + } else { + dra &= 0x0f; + } + mchbar_write8(CxDRA_MCHBAR(ch) + s, dra); + + /* Step 4: write16 DRB rank_odd carry-forward */ + mchbar_write16(CxDRBy_MCHBAR(ch, s * 2) + 2, boundary); + } + } + + /* + * DCC2: channel address decode (FFF01378). + * + * Write 0 here; the final value is derived from EPD_2E[4:0] + * after program_epd() runs at POST FF41. The vendor also + * writes 0 at this point (EPD not yet programmed on cold boot). + */ + mchbar_write16(DCC2_MCHBAR, 0); + + /* + * TOM / TOLUD / TOUUD - vendor FFF0139F-FFF013B2. + * + * The vendor writes these PCI registers in the SAME function + * that programs DRBs, both for pre-JEDEC and final memory map. + * Without them, TOLUD stays at its reset default (1 MB), and + * the system agent routes all DRAM reads above 1 MB to MMIO + * instead of the memory controller. JEDEC MRS commands for + * rank 1 (at 128 MB) and all channel 1 ranks never reach the + * MC, so only rank 0 channel 0 gets initialized. + * + * Pre-JEDEC total = boundary * 32 MB. With rank_size = 4 + * (128 MB per rank), a 2-DIMM single-rank system has + * boundary = 8, total = 256 MB, matching the vendor trace: + * TOM (0xA0) = 0x0002 (256 >> 7) + * TOLUD (0xB0) = 0x1000 (256 << 4) + * TOUUD (0xA2) = 0x0100 (256) + */ + { + uint32_t total_mb = (uint32_t)boundary * 32; + uint32_t tolud_mb = (total_mb < 3072) ? total_mb : 3072; + + pci_write_config16(D0F0, D0F0_TOM, (total_mb >> 7) & 0x1ff); + pci_write_config16(D0F0, D0F0_TOLUD, tolud_mb << 4); + pci_write_config16(D0F0, D0F0_TOUUD, total_mb); + } + + /* Disable channel XOR during pre-JEDEC */ + mchbar_setbits32(DCC_MCHBAR, DCC_NO_CHANXOR); +} + +/* ================================================================== */ +/* Final memory map programming */ +/* ================================================================== */ + +/* + * program_memory_map() - Set up final memory map with real sizes + * + * Programs CxDRBy with actual rank sizes, sets TOM/TOLUD/TOUUD. + * + * BIOS equivalent: FFFF3EC7 with param=0 (POST 0xFF35) + * coreboot equivalent: program_memory_map() + */ +static void program_memory_map(sysinfo_t *si, u16 ggc) +{ + int ch, s; + uint32_t total_mb = 0; + + /* + * Vendor (FFF01278 with param=0) uses the same per-slot loop + * structure as pre-JEDEC but with real rank sizes from the + * ROM table at FFF038B4: + * rank_size = ROM[cols_idx + cap_idx] << banks_shift + * dra = ROM[cols_idx] at FFF038B8 (0x22/0x33/0x44) + * + * For the final map, boundary resets to 0 per-channel + * (vendor: FFF0133E-01343 saves ch0, resets for ch1). + */ + for (ch = 0; ch < 2; ch++) { + uint8_t boundary = 0; + + for (s = 0; s < 2; s++) { + int slot = ch * 2 + s; + uint8_t rank_size = 0; + uint8_t dra = 0; + + if (slot < 4 && si->dimms[slot].present) { + /* + * Rank size in 32 MB units from SPD geometry. + * Vendor ROM table at FFF038B4: + * index 0 (9 cols): 4 (128 MB) + * index 1 (10 cols): 8 (256 MB) + * index 2 (11 cols): 16 (512 MB) + * Then shifted by banks_shift (8-bank -> +1). + */ + int banks_shift = (si->dimms[slot].banks == 8) ? 1 : 0; + rank_size = (si->dimms[slot].rank_capacity_mb / 32); + if (rank_size == 0) + rank_size = 1; + /* + * banks_shift is already baked into + * rank_capacity_mb from SPD, so no shift + * needed here (unlike pre-JEDEC). + */ + (void)banks_shift; + + /* + * DRA encoding from ROM table at FFF038B8: + * cols 9 -> 0x22, cols 10 -> 0x33, cols 11 -> 0x44 + * Per-rank nibble = (cols - 7). Both nibbles + * set for dual-rank. + */ + uint8_t nibble = si->dimms[slot].cols - 7; + dra = nibble | (nibble << 4); + + total_mb += si->dimms[slot].rank_capacity_mb; + } + + /* Step 1: write16 DRB rank_even boundary */ + boundary += rank_size; + mchbar_write16(CxDRBy_MCHBAR(ch, s * 2), boundary); + + /* + * Steps 2-3: DRA writes, interleaved per vendor + * (FFF01308 + FFF01319). + * + * Dual-rank: write DRA (full), advance boundary + * for rank 1, write DRA again. + * Single-rank: mask DRA lower nibble, write once. + * Empty: dra=0, one write. + */ + if (slot < 4 && si->dimms[slot].present + && si->dimms[slot].dual_rank) { + mchbar_write8(CxDRA_MCHBAR(ch) + s, dra); + boundary += rank_size; + total_mb += si->dimms[slot].rank_capacity_mb; + } else { + dra &= 0x0f; + } + mchbar_write8(CxDRA_MCHBAR(ch) + s, dra); + + /* Step 4: write16 DRB rank_odd carry-forward */ + mchbar_write16(CxDRBy_MCHBAR(ch, s * 2) + 2, boundary); + } + } + + /* + * DCC2: channel address decode (FFF01378). + * + * Write 0 here; the final value is derived from EPD_2E[4:0] + * after program_epd() runs at POST FF41. The vendor also + * writes 0 at this point (EPD not yet programmed on cold boot). + */ + mchbar_write16(DCC2_MCHBAR, 0); + + /* + * Program TOM, TOLUD, TOUUD, and REMAP in D0:F0 PCI config. + * + * Vendor BIOS (D630: FUN_fffec42e, X61: FFF01278/FFFF3EC7): + * + * total = sum of all rank capacities (MB) + * tolud = min(total, 3584MB) [MMIO window starts at 3.5 GB] + * + * When total > tolud + 64 MB, the DRAM above TOLUD is hidden by + * the MMIO aperture. The MCH remap engine re-maps that hidden + * DRAM into the region starting at REMAPBASE (above 4 GB), making + * it accessible again. + * + * Vendor algorithm (register units are MB throughout): + * total_aligned = total & ~63 (64 MB alignment) + * remapbase = max(total_aligned, 4096) + * touud_capped = min(total_aligned, 4096) + * remaplimit = remapbase + (touud_capped - tolud) - 64 + * touud_final = remaplimit + 64 + * + * Register encodings (PCI config D0:F0): + * TOM (0xA0): total >> 7 (128 MB units) + * TOLUD (0xB0): tolud << 4 (1 MB units, bits [14:4]) + * TOUUD (0xA2): touud (1 MB units) + * REMAPBASE (0x98): remapbase >> 6 (64 MB units) + * REMAPLIMIT(0x9A): remaplimit >> 6 (64 MB units) + */ + si->tom_mb = total_mb; + si->tolud_mb = (total_mb < 3072) ? total_mb : 3072; /* cap at 3 GB for MMIO */ + + uint32_t touud_mb = total_mb; + int needs_remap = (total_mb - si->tolud_mb) > 64; + + if (needs_remap) { + /* + * Remap the DRAM hidden behind the MMIO aperture to above + * 4 GB (or above total if total > 4 GB). + * + * GM965 REMAPBASE and REMAPLIMIT registers (D0F0 offsets + * 0x98 and 0x9A) encode Address[35:26] in bits [9:0], but + * require bit 0 (address bit 26) to be 0. This gives + * 128 MB granularity, unlike GM45 which allows 64 MB. + * + * The vendor BIOS handles this by rounding REMAPLIMIT + * down to the nearest even value and setting TOUUD to + * match the actual (smaller) remap window. Up to 64 MB + * of hidden DRAM may be lost. + * + * Vendor inteltool (2x2GB): + * REMAPBASE = 0x0040 (4096 MB, bit 0 = 0) + * REMAPLIMIT = 0x004E (4992 MB, bit 0 = 0) + * TOUUD = 0x13C0 (5056 MB = (78+1)*64) + * TOLUD = 0xC000 (3072 MB, unchanged) + */ + uint32_t total_aligned = total_mb & ~63u; + uint32_t remapbase = (total_aligned > 4096) ? total_aligned : 4096; + uint32_t touud_cap = (total_aligned < 4096) ? total_aligned : 4096; + uint32_t remaplimit = remapbase + (touud_cap - si->tolud_mb) - 64; + + /* Round register values to even (clear bit 0) for 128 MB alignment */ + uint16_t remapbase_reg = (uint16_t)((remapbase >> 6) & 0x03fe); + uint16_t remaplimit_reg = (uint16_t)((remaplimit >> 6) & 0x03fe); + + /* TOUUD must match the actual remap window, not the theoretical size */ + touud_mb = (uint32_t)(remaplimit_reg + 1) * 64; + + pci_write_config16(D0F0, D0F0_REMAPBASE, remapbase_reg); + pci_write_config16(D0F0, D0F0_REMAPLIMIT, remaplimit_reg); + + printk(BIOS_DEBUG, "memmap: remap enabled - " + "REMAPBASE=0x%04x (%uMB) REMAPLIMIT=0x%04x (%uMB) " + "TOUUD=%uMB\n", + remapbase_reg, remapbase, + remaplimit_reg, remaplimit, touud_mb); + } + + printk(BIOS_DEBUG, "memmap: total=%uMB TOM=%uMB TOLUD=%uMB " + "TOUUD=%uMB remap=%d DRA0=0x%08x DRA1=0x%08x\n", + total_mb, total_mb, si->tolud_mb, touud_mb, needs_remap, + mchbar_read32(CxDRA_MCHBAR(0)), + mchbar_read32(CxDRA_MCHBAR(1))); + + pci_write_config16(D0F0, D0F0_TOM, (total_mb >> 7) & 0x1ff); + pci_write_config16(D0F0, D0F0_TOLUD, si->tolud_mb << 4); + pci_write_config16(D0F0, D0F0_TOUUD, touud_mb); + + printk(BIOS_DEBUG, "memmap regs: TOM=0x%04x TOLUD=0x%04x TOUUD=0x%04x" + " REMAPBASE=0x%04x REMAPLIMIT=0x%04x ESMRAMC=0x%02x\n", + pci_read_config16(D0F0, D0F0_TOM), + pci_read_config16(D0F0, D0F0_TOLUD), + pci_read_config16(D0F0, D0F0_TOUUD), + pci_read_config16(D0F0, D0F0_REMAPBASE), + pci_read_config16(D0F0, D0F0_REMAPLIMIT), + pci_read_config8(D0F0, D0F0_ESMRAMC)); + + /* + * Program the GGC (Graphics Memory Control) register. + * + * Writing GGC causes the hardware to compute BSM (Base of Stolen + * Memory) as: BSM = TOLUD - stolen_size. The IGD stolen region + * then occupies [BSM, TOLUD). TSEG is placed just below BSM by + * northbridge_get_tseg_base() in memmap.c. + * + * ggc is returned by igd_compute_ggc() from the gfx_uma_size option. + * If bit 1 (IVD) is set, no memory is stolen and IGD is disabled. + */ + pci_write_config16(D0F0, D0F0_GGC, ggc); + + /* + * Enable TSEG (2 MB) - required for SMM and cbmem. + * + * ESMRAMC register (D0:F0 offset 0x9E): + * bit 0: T_EN (TSEG enable) + * bits [2:1]: TSEG_SZ (00=1M, 01=2M, 10=8M) + * + * GM45 reference: pci_update_config8(D0F0, D0F0_ESMRAMC, + * ~0x07, (1<<1)|(1<<0)); + * Sets T_EN=1, TSEG_SZ=01 (2MB). + */ + pci_update_config8(D0F0, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + + /* + * DCC channel mode is handled by post_jedec_sequence() + * (POST 0xFF34) which clears/sets DCC_INTERLEAVED (bit 1) + * and sets bit 10 (normal operation). + * + * The vendor's final memory map (FFF01278 / FFFF3EC7 with + * param=0) does NOT modify DCC at all - bit 10 stays set + * from post_jedec and must NOT be cleared. + */ +} + +/* ================================================================== */ +/* DRAM timing register programming */ +/* ================================================================== */ + +/* + * program_timings() - Write timing parameters to CxDRT0-CxDRT6 + * + * Programs both channels with computed timing values. + * + * BIOS equivalent: FFF02A7A (1603 bytes) / FFFF408F (881 bytes, POST 0xFF25) + * coreboot equivalent: dram_program_timings() + */ +static void program_timings(sysinfo_t *si) +{ + timings_t *t = &si->timings; + int ch; + + /* + * Compute tRRD adjustment for CxDRT1 bits [12:10]. + * + * Vendor logic (FFF0146B decompiled): + * mc==1 (800MT): default 0, scan DIMMs: + * if (present && cols > 9 && x16) -> trrd_adj = 1 + * mc==2 (667MT): default 1, scan DIMMs: + * if (present && ((cols > 9 && x16) || cols > 10)) -> trrd_adj = 2 + * + * This is a geometry-based check on page size / DIMM width, + * NOT a dual-rank check. Standard x8 DDR2 with 10 columns + * keeps the default. Only x16 DIMMs or those with >10 cols + * (e.g., 2KB page) bump the tRRD value up. + * + * Maps to CxDRT1 tRRD bits [12:10]. + * + * Vendor struct offsets: + * puVar7[-6] = present (byte 0), puVar7[-4] = x16 (byte 2), + * *puVar7 = cols_minus_9 (byte 6) + */ + int trrd_adj = 0; + if (t->mem_clock == MEM_CLOCK_533MT) { + for (int s = 0; s < 4; s++) { + if (si->dimms[s].present + && (si->dimms[s].cols > 9) + && si->dimms[s].x16) + trrd_adj = 1; + } + } else if (t->mem_clock == MEM_CLOCK_667MT) { + trrd_adj = 1; + for (int s = 0; s < 4; s++) { + if (si->dimms[s].present + && (((si->dimms[s].cols > 9) && si->dimms[s].x16) + || (si->dimms[s].cols > 10))) + trrd_adj = 2; + } + } + + for (ch = 0; ch < 2; ch++) { + uint32_t reg; + + /* + * --- CxDRT0 (EDS 4.7.5) --- + * + * Two-step programming: + * 1) Lower 18 bits: from ROM base table per mem_clock. + * 2) Upper word BtB fields (EDS formulas, DDR2 BL=8): + * [30:26] B2BWR2PCSB = WL + BL/2 + tWR = (CAS-1) + 4 + tWR + * [23:20] B2BWR2RDSR = WL + BL/2 + tWTR = (CAS-1) + 4 + tWTR + * Verified: inteltool DRT0 = 0x34b10841, WtP=13, WtR=11. + */ + reg = mchbar_read32(CxDRT0_MCHBAR(ch)); + + /* Step 1: Apply ROM table to lower fields */ + /* + * CxDRT0 base values (ROM table at BIOS file offset 0x175A78). + * Indexed by mem_clock (1-based). Applied with mask 0xfffc4318. + * Sets fields: bits [17:15], [13:10], [7:5], [2:0]. + * Values are the same for both supported freq so use a const. + */ + const uint32_t drt0_base = 0x00010841; + + reg = (reg & 0xfffc4318) | drt0_base; + + /* Step 2: Compute BtB values (tWL = CAS-1, BL/2 = 4) */ + int btb_wtp = (t->CAS - 1) + 4 + t->tWR; + int btb_wtr = (t->CAS - 1) + 4 + drt0_twtr_lut[t->mem_clock]; + + reg = (reg & ~(0xfU << 20)) | ((btb_wtr & 0xf) << 20); + reg = (reg & ~(0x1fU << 26)) | ((btb_wtp & 0x1f) << 26); + mchbar_write32(CxDRT0_MCHBAR(ch), reg); + + /* + * --- CxDRT1 (EDS 4.7.6) --- + * + * Preserve mask 0xcc1fe318 (bits 31:30,27:26,20:19,17:16, + * 13,9:8,4:3 are reserved/preserved). + * [29:28] = tRTP (00=BL/2 for DDR2-533, 01=BL/2+1 for DDR2-667) + * [25:21] = tRAS (Activate to Precharge delay) + * [18] = Precharge to Precharge Delay (keep at 1 clock reset default) + * [15] = tRPALL (Pre-All to Activate, preserved from odt_pre_setup) + * [12:10] = tRRD (Activate to Activate delay) + * [7:5] = tRCD - 2 (DRAM RASB to CASB Delay) + * [2:0] = tRP - 2 (DRAM RASB Precharge) + */ + { + uint32_t drt1_val = (t->tRAS << 21) + | ((t->tRCD - 2) << 5) + | (t->tRP - 2); + if (t->mem_clock == MEM_CLOCK_667MT) + drt1_val |= (1 << 28); + drt1_val |= (trrd_adj << 10); + + reg = mchbar_read32(CxDRT1_MCHBAR(ch)); + reg = (reg & 0xcc1fe318) | drt1_val; + mchbar_write32(CxDRT1_MCHBAR(ch), reg); + } + + /* + * --- CxDRT2 (EDS 4.7.7) --- + * + * [21:17] = tFAW (Rolling Activate Window) + * [4:0] = 0x10 (fixed) + */ + { + const uint32_t tFAW = tFAW_fixed[t->mem_clock]; + uint32_t drt2 = mchbar_read32(CxDRT2_MCHBAR(ch)); + drt2 = (drt2 & ~(0x1f << 0)) | (0x10 << 0); + drt2 = (drt2 & ~(0x1f << 17)) | (tFAW << 17); + mchbar_write32(CxDRT2_MCHBAR(ch), drt2); + } + + /* + * --- CxDRT3 (EDS 4.7.8) --- + * + * [25:23] = CASB Latency (CAS - 3) + * [20:13] = Refresh Cycle Time (tRFC) + * [2:0] = Write Latency (tWL - 2, DDR2: tWL = CAS - 1) + * Verified: inteltool DRT3 = 0x01056282, CAS=5, tRFC=43. + */ + { + const uint32_t tWL = t->CAS - 1; + uint32_t drt3 = mchbar_read32(CxDRT3_MCHBAR(ch)); + drt3 = (drt3 & ~(0x07 << 23)) | ((t->CAS - 3) << 23); + drt3 = (drt3 & ~(0xff << 13)) | (t->tRFC << 13); + drt3 = (drt3 & ~(0x07 << 0)) | ((tWL - 2) << 0); + mchbar_write32(CxDRT3_MCHBAR(ch), drt3); + } + + /* + * --- CxDRT4 --- + * + * BIOS: load full register from ROM table. + */ + mchbar_write32(CxDRT4_MCHBAR(ch), drt4_rom_table[t->mem_clock]); + + /* + * --- CxDRT5 --- + * + * EDS 4.7.10: + * bits [25:22] = TS Read Delay (BL/2 + CL + 2) + * bits [20:12] = Read Slave DLL Lock Timer (ROM table) + * bits [2:1] = DQ/DQS Sense Amp Duration + * Verified: inteltool DRT5 = 0x62c64042, bits[25:22]=11. + */ + { + const uint32_t ts_read_delay = 4 + t->CAS + 2; /* BL/2 + CL + 2 */ + uint32_t drt5 = mchbar_read32(CxDRT5_MCHBAR(ch)); + drt5 = (drt5 & ~(0x00f << 22)) | (ts_read_delay << 22); + drt5 = (drt5 & ~(0x1ff << 12)) | (drt5_rom_bytes[t->mem_clock] << 12); + drt5 = (drt5 & ~(0x003 << 1)) | (1 << 1); + mchbar_write32(CxDRT5_MCHBAR(ch), drt5); + } + + /* --- CxDRT6: ZQ bit clear for DDR2 --- */ + reg = mchbar_read32(CxDRT6_MCHBAR(ch)); + reg &= ~(1 << 2); /* DDR2: no ZQ cal */ + mchbar_write32(CxDRT6_MCHBAR(ch), reg); + } +} + +/* ================================================================== */ +/* Rank enable and DRAM control registers */ +/* ================================================================== */ + +/* + * program_dram_control() - Set CxDRC0/CxDRC1/CxDRC2 for each channel + * + * BIOS equivalent: FFFF408F (tail section, lines 1750-1771) + * + * CxDRC0: bits [10:8] from param[0x20] (rank config byte), bit 3 set + * CxDRC1: rank not-populated bits [17:16], plus constant |= 0xc1800 + * CxDRC2: rank disable bits [25:24], plus constant |= 0xc001000 + */ +static void program_dram_control(sysinfo_t *si) +{ + int ch; + + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + uint32_t reg; + + /* + * CxDRC0 (EDS 4.7.11): DRAM Controller Mode 0 + * [10:8] = RMS: Refresh Mode Select (7.8us = 2) + * [3] = BL: Burst Length 8 + * Verified: inteltool CxDRC0 = 0x4000020a, bits[10:8] = 2. + */ + reg = mchbar_read32(CxDRC0_MCHBAR(ch)); + reg = (reg & ~CxDRC0_RMS_MASK) | CxDRC0_RMS_78US; + reg |= (1 << 3); /* Burst length = 8 */ + mchbar_write32(CxDRC0_MCHBAR(ch), reg); + + /* + * CxDRC1 (EDS 4.7.12): DRAM Controller Mode 1 + * [19:16] = CKE tri-state per rank (set for unpopulated) + * [12] = CSBTRIEN: CS# tri-state enable + * [11] = ADRTRIEN: address tri-state enable + */ + reg = mchbar_read32(CxDRC1_MCHBAR(ch)); + if (!si->dimms[slot].present) { + /* No DIMM: tri-state both ranks' CKE */ + reg |= CxDRC1_CKE_TRISTATE(0) | CxDRC1_CKE_TRISTATE(1); + } else if (!si->dimms[slot].dual_rank) { + /* Single rank: tri-state rank 1's CKE */ + reg |= CxDRC1_CKE_TRISTATE(1); + } + reg |= 0xc0000 | CxDRC1_CSBTRIEN | CxDRC1_ADRTRIEN; + mchbar_write32(CxDRC1_MCHBAR(ch), reg); + + /* + * CxDRC2 (EDS 4.7.13): DRAM Controller Mode 2 + * [27:24] = ODT tri-state per rank (set for unpopulated) + * [13] = Clock Control to DQ Buffers + * [12] = constant + */ + reg = mchbar_read32(CxDRC2_MCHBAR(ch)); + if (!si->dimms[slot].present) { + /* No DIMM: tri-state both ranks' ODT */ + reg |= 0x3000000; + } else if (!si->dimms[slot].dual_rank) { + /* Single rank: tri-state rank 1's ODT */ + reg |= 0x2000000; + } + reg |= 0xc001000; + mchbar_write32(CxDRC2_MCHBAR(ch), reg); + } +} + +/* ================================================================== */ +/* RCOMP Initialization */ +/* ================================================================== */ + +/* + * RCOMP ROM table data - extracted from X61 BIOS at 0xFFFF5910 + * 9 groups x 10 DWORDs (40 bytes) per group = 360 bytes total. + * Copied to MCHBAR RCOMP_TABLES (0x0680) with gaps. + * + * Layout per group in ROM: [6 DWORDs (pull-up/down base)] [4 DWORDs (strength)] + * Layout per group in MCHBAR: 64 bytes with gaps after entries 2 and 5. + */ +static const uint32_t rcomp_rom_table[9][10] = { + { /* Group 0 */ + 0x4c28a249, 0xe38e34d3, 0x3cf3cf38, + 0x4c2ca249, 0xe38e34d3, 0x3cf3cf3c, + 0x00000055, 0x55000000, 0x00000000, 0x00000000 + }, + { /* Group 1 */ + 0xc8186145, 0xc30c2cb2, 0x34d34d30, + 0x481c71c6, 0xb2ca28a2, 0x30c30c30, + 0x00000055, 0x55000000, 0x00000000, 0x00000000 + }, + { /* Group 2 */ + 0xc8186145, 0xc30c2cb2, 0x34d34d30, + 0x481c71c6, 0xb2ca28a2, 0x30c30c30, + 0x00000055, 0x55000000, 0x00000000, 0x80000000 + }, + { /* Group 3 */ + 0xc8186145, 0xc30c2cb2, 0x34d34d30, + 0x481c71c6, 0xb2ca28a2, 0x30c30c30, + 0x00000055, 0x55000000, 0x00000000, 0x80000000 + }, + { /* Group 4 */ + 0xca28a249, 0x24903cb2, 0x4d34d349, + 0xcd34d30c, 0x349140f3, 0x5d759655, + 0x00000088, 0x88000000, 0x00000000, 0x00000000 + }, + { /* Group 5 */ + 0xca28a249, 0x24903cb2, 0x4d34d349, + 0xcd34d30c, 0x349140f3, 0x5d759655, + 0x00000088, 0x88000000, 0x00000000, 0x00000000 + }, + { /* Group 6 */ + 0xca28a249, 0x24903cb2, 0x4d34d349, + 0xca28a249, 0x140e34b2, 0x4d349245, + 0x00000088, 0x88000000, 0x00000000, 0x00000000 + }, + { /* Group 7 */ + 0x4c28a249, 0xe38e34d3, 0x3cf3cf38, + 0x4c2ca249, 0xe38e34d3, 0x3cf3cf3c, + 0x00000055, 0x55000000, 0x00000000, 0x00000000 + }, + { /* Group 8 */ + 0xc8186145, 0xc30c2cb2, 0x34d34d30, + 0x481c71c6, 0xb2ca28a2, 0x30c30c30, + 0x00000055, 0x55000000, 0x00000000, 0x00000000 + }, +}; + +/* + * rcomp_init() - Initialize RCOMP calibration engine + * + * Programs RCOMP registers, copies ROM compensation tables to MCHBAR, + * and starts initial calibration cycle. + * + * BIOS equivalent: FFFF3C49 (296 bytes, POST 0xFF23) + * coreboot equivalent: rcomp_initialization() (DDR2 path) + * + * Key differences from original code (audit findings): + * - RCOMP_STATUS must be: & 0x8888 | 0x1111 + * - RCOMP_CFG must be: & 0xc1ff | 0x2e00 + * - RCOMP_CFG4 must be: & 0x99999999 | 0x11119999 + * - RCOMP_ODT0/1 must be: & 0xc0 | 0x36 (not 0x09) + * - ROM table must be copied to RCOMP_TABLES + */ +static void rcomp_init(sysinfo_t *si) +{ + int g, i; + + /* + * Enable RCOMP engine clock before any RCOMP_CTRL writes. + * Vendor BIOS (fff00ff0): first action at POST ff23 is to set bit 12 + * of MCHBAR[0x1444]. Without this the RCOMP engine has no clock and + * the RCOMP_CTRL bit 0 (busy/GO) never clears. + * Cleared again at POST ff40 after all training is complete. + */ + mchbar_setbits32(IO_RCOMP_CLK_EN, 1 << 12); + + /* + * Step 1: Program RCOMP_CTRL - clear bits 18,4,0; set bits 17,5. + * Bit 0 (RCOMP_GO) is cleared explicitly here so that a stale value + * from a previous boot cycle (warm reset) does not confuse the engine. + * On non-A0 steppings (vendor: DAT_f0000008 != 0), also set bit 18. + * The vendor first writes with bits 17,5 then overwrites with + * bits 18,17,5 if stepping is non-A0. On C0 (X61) bit 18 is + * always set regardless of cold/warm boot. + */ + uint8_t stepping = northbridge_stepping(); + uint32_t rcomp_ctrl = mchbar_read32(RCOMP_CTRL); + rcomp_ctrl &= 0xfffaffee; /* Clear bits 18, 4, and 0 (stale GO bit) */ + rcomp_ctrl |= 0x20020; /* Set bits 17, 5 */ + mchbar_write32(RCOMP_CTRL, rcomp_ctrl); + if (stepping != 0x00) { + rcomp_ctrl |= 0x60020; /* Non-A0: also set bit 18 */ + mchbar_write32(RCOMP_CTRL, rcomp_ctrl); + } + + /* + * Step 2: RCOMP_STATUS - keep bits 15,11,7,3; set bits 12,8,4,0. + * Vendor uses 16-bit access (trace: "=> 2222 / <= 1111"). + * Must NOT use 32-bit access: that would zero out the adjacent + * register at 0x0406-0x0407, corrupting RCOMP engine state. + */ + mchbar_clrsetbits16(RCOMP_STATUS, ~0x8888 & 0xffff, 0x1111); + + /* + * Step 3: RCOMP_CFG - clear bits [13:9], set 13,11,10,9 = 0x2E00. + * Vendor uses 16-bit access (trace: "=> 0100 / <= 2f00"). + * Must NOT use 32-bit access: that would zero out the adjacent + * register at 0x040e-0x040f, preventing RCOMP from completing. + */ + mchbar_clrsetbits16(RCOMP_CFG, ~0xc1ff & 0xffff, 0x2e00); + + /* Step 4: RCOMP_CFG3 - set bit 18 */ + mchbar_setbits32(RCOMP_CFG3, 1 << 18); + + /* Step 5: RCOMP_CFG4 - clear even nibble bits, set pattern */ + mchbar_clrsetbits32(RCOMP_CFG4, ~0x99999999U, 0x11119999); + + /* Step 6: RCOMP_ODT0/1 - keep bits [7:6], set 0x36 in [5:0] */ + mchbar_clrsetbits8(RCOMP_ODT0, 0x3f, 0x36); + mchbar_clrsetbits8(RCOMP_ODT1, 0x3f, 0x36); + + /* + * Step 7: Copy ROM compensation tables to MCHBAR RCOMP_TABLES. + * 9 groups, each occupying 64 bytes in MCHBAR (with gaps). + * + * BIOS layout per group in MCHBAR (64 bytes): + * Offsets 0x00-0x0B: ROM entries 0-2 (12 bytes) + * Offsets 0x0C-0x17: gap (skipped) + * Offsets 0x18-0x23: ROM entries 3-5 (12 bytes) + * Offsets 0x24-0x2F: gap (skipped) + * Offsets 0x30-0x3F: ROM entries 6-9 (16 bytes) + * + * Must use mchbar_write32() (volatile MMIO accessor) - raw pointer + * writes through a non-volatile uint32_t * can be reordered or + * eliminated by the compiler, leaving the RCOMP engine with empty + * tables and preventing calibration from completing. + */ + for (g = 0; g < 9; g++) { + uint16_t tbl_off = RCOMP_TABLES + g * 64; + + /* First 3 DWORDs (entries 0-2) at group offset 0x00 */ + for (i = 0; i < 3; i++) + mchbar_write32(tbl_off + i * 4, rcomp_rom_table[g][i]); + + /* Next 3 DWORDs (entries 3-5) at group offset 0x18 */ + for (i = 0; i < 3; i++) + mchbar_write32(tbl_off + 0x18 + i * 4, rcomp_rom_table[g][3 + i]); + + /* Last 4 DWORDs (entries 6-9 = strength) at group offset 0x30 */ + for (i = 0; i < 4; i++) + mchbar_write32(tbl_off + 0x30 + i * 4, rcomp_rom_table[g][6 + i]); + } + + /* + * Step 8: Program RCOMP_CFG2 clock-dependent value. + * BIOS: DAT_fed14414 = lookup[mem_clock] + lookup[fsb_clock] + */ + /* + * Clock-dependent RCOMP comp codes - from BIOS ROM at 0xFFFF5904/5909 + * and verified against inteltool dump (RCOMP_CFG2 = 0x50 for FSB800+DDR2-667). + * + * Vendor BIOS uses its own sysinfo indices (0x1c, 0x1d) which differ + * from our fsb_clock / mem_clock. Mapped to our enum values: + * fsb_clock: FSB_CLOCK_533MHz=1, FSB_CLOCK_800MHz=2, FSB_CLOCK_667MHz=3 + * mem_clock: MEM_CLOCK_533MT=1, MEM_CLOCK_667MT=2 + * + * ROM FSB table {0x00,0x01,0x05,0x00} @ vendor idx 0-3 + * ROM MEM table {0x00,0x10,0x50,0x00} @ vendor idx 0-3 + * Vendor FSB idx = fsb_clock - 2; MEM idx = mem_clock (direct). + */ + static const uint8_t rcomp_fsb_codes[] = { 0, 0x00, 0x00, 0x01 }; /* indexed by fsb_clock */ + static const uint8_t rcomp_mem_codes[] = { 0, 0x10, 0x50, 0x00 }; /* indexed by mem_clock */ + uint8_t rcomp_code = rcomp_fsb_codes[si->timings.fsb_clock] + + rcomp_mem_codes[si->timings.mem_clock]; + mchbar_write8(RCOMP_CFG2, rcomp_code); + + /* + * Step 9: Re-arm RCOMP comparator with a latch write. + * + * Vendor (fff010fd): reads MCHBAR[0x0418] then writes the same + * value back - a latch write that re-arms the comparator before + * the GO trigger. Do NOT clear bit 17 here: bit 17 is already 0 + * at this point (only bit 18 was set in step 4), and incorrectly + * clearing it causes the teardown write to produce 0x00060000 + * (bits 17+18) instead of the correct 0x00040000 (bit 18 only). + */ + mchbar_write32(RCOMP_CFG3, mchbar_read32(RCOMP_CFG3)); + + /* + * Step 10: Start RCOMP - set bit 0 (GO). + * A1 stepping only: also set bit 1 (vendor: stepping == 0x01). + * On A0 and C0 (all others): bit 0 only. + * + * Vendor uses 8-bit access for the GO trigger (trace: "=> 20 / <= 21") + * to avoid disturbing upper bytes of RCOMP_CTRL which may contain + * hardware-managed state. + */ + if (stepping == 0x01) + mchbar_setbits8(RCOMP_CTRL, 3); + else + mchbar_setbits8(RCOMP_CTRL, 1); + + printk(BIOS_DEBUG, "%s: started RCOMP_CTRL=0x%08x " + "CFG=0x%08x CFG2=0x%02x CFG3=0x%08x CFG4=0x%08x\n", + __func__, + mchbar_read32(RCOMP_CTRL), + mchbar_read32(RCOMP_CFG), + mchbar_read8(RCOMP_CFG2), + mchbar_read32(RCOMP_CFG3), + mchbar_read32(RCOMP_CFG4)); + /* Dump first RCOMP table entries to verify table data in binary. + * Vendor inteltool: 0x688=0x3cf3cf38, 0x6c8=0x34d34d30 */ + printk(BIOS_DEBUG, "%s: table[0x688]=0x%08x " + "table[0x6c8]=0x%08x table[0x6b0]=0x%08x\n", + __func__, + mchbar_read32(RCOMP_TABLES + 0x08), + mchbar_read32(RCOMP_TABLES + 0x48), + mchbar_read32(RCOMP_TABLES + 0x30)); +} + +/* ================================================================== */ +/* DDR2 ODT Setup */ +/* ================================================================== */ + +/* + * CxODT timing lookup tables, extracted from BIOS ROM at 0xFFFF5AB8. + * Indexed by CAS latency (3..6), each entry is {ODT_LOW_mask, ODT_HIGH_mask}. + * These are OR'd with the existing register value (after masking). + * + * CxODT_LOW mask: & 0x8f3f8f88 + * CxODT_HIGH mask: & 0x9f480000 + */ +static const uint32_t odt_timing_table[4][2] = { + /* CAS 3 */ { 0x20001010, 0x60918788 }, /* from ROM at index 0 */ + /* CAS 4 */ { 0x20002020, 0x60928788 }, /* from ROM at index 1 */ + /* CAS 5 */ { 0x20003030, 0x60938788 }, /* from ROM at index 2 */ + /* CAS 6 */ { 0x20004040, 0x60948788 }, /* from ROM at index 3 */ +}; + +/* + * odt_pre_setup() - Pre-JEDEC ODT register setup + * + * BIOS equivalent: FFFF4036 / FFF01412 (89 bytes, POST 0xFF24) + * Sets CxDRA_HI bits and CxDRT1 bit 15 for 8-bank DIMMs. + * + * Vendor decompilation (FFF01412): + * if (present && banks_flag) // banks_flag = SPD[17]>>3 + * CxDRA_HI |= 0x09; + * CxDRT1 |= 0x8000; + * + * The condition gates on 8-bank SDRAM devices (SPD byte 17 == 8), + * NOT on dual-rank. banks_flag in the vendor per-DIMM struct is + * byte 3 = SPD[0x13] >> 3, which is 1 for 8 banks and 0 for 4. + */ +static void odt_pre_setup(sysinfo_t *si) +{ + int ch; + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + /* Clear lower byte of CxDRA upper half */ + mchbar_clrbits16(CxDRA_HI(ch), 0x00ff); + if (slot < 4 && si->dimms[slot].present + && si->dimms[slot].banks == 8) { + mchbar_setbits16(CxDRA_HI(ch), 0x09); + mchbar_setbits32(CxDRT1_MCHBAR(ch), 0x8000); + } + } +} + +/* + * misc_odt_settings() - Program CxODT_LOW/HIGH from ROM lookup table + * + * BIOS equivalent: FFFF4400 (119 bytes, POST 0xFF26) + * These timing values depend on CAS latency. + */ +static void misc_odt_settings(sysinfo_t *si) +{ + int cas_idx = si->timings.CAS - 3; + if (cas_idx < 0) + cas_idx = 0; + if (cas_idx > 3) + cas_idx = 3; + int ch; + for (ch = 0; ch < 2; ch++) { + mchbar_clrsetbits32(CxODT_LOW(ch), ~0x8f3f8f88U, odt_timing_table[cas_idx][0]); + mchbar_clrsetbits32(CxODT_HIGH(ch), ~0x9f480000U, odt_timing_table[cas_idx][1]); + } +} + +/* + * ddr2_odt_setup() - Configure On-Die Termination control registers + * + * BIOS equivalent: FFFF4477 (252 bytes, POST 0xFF27) + * Programs ODT misc, timing, and global write/arbitration registers. + */ +static void ddr2_odt_setup(sysinfo_t *si) +{ + int ch; + + /* + * Per-channel ODT control registers. + * + * Vendor ROM table at 0xFFFF5A88 is indexed by + * [fsb_clkcfg_code][CAS_index], NOT [our_fsb_enum][mem_clock]. + * For FSB800 (clkcfg=2) and FSB667 (clkcfg=3), the table rows + * are identical: value = (CAS - 3) + 4 = CAS + 1. + * Verified: inteltool CxODT_MISC = 0x80000006 (bits[4:0]=6=CAS+1). + * + * ODT_TIMING: vendor uses CAS_index + 2 = (CAS-3) + 2 = CAS - 1. + * Verified: inteltool CxODT_TIMING = 0x00000004 (bits[3:0]=4=CAS-1). + */ + uint8_t odt_misc_val = si->timings.CAS + 1; + + for (ch = 0; ch < 2; ch++) { + /* CxODT_MISC bit 31: vendor sets this first (32-bit OR) */ + mchbar_setbits32(CxODT_MISC(ch), 0x80000000); + + /* CxODT_MISC low byte: keep bits [7:5], set lower 5 from lookup. + * Vendor uses 8-bit access (mov byte) - NOT 32-bit. */ + mchbar_clrsetbits8(CxODT_MISC(ch), 0x1f, odt_misc_val); + + /* CxODT_TIMING: low nibble = CAS - 1 */ + mchbar_clrsetbits8(CxODT_TIMING(ch), 0x0f, si->timings.CAS - 1); + + /* CxODT_CTRL: bits [2:0] = 2 */ + mchbar_clrsetbits8(CxODT_CTRL(ch), 0x07, 0x02); + } + + /* + * Global write/arbitration registers. + * Vendor (odt_setup_FF27, FFFF4525-FFFF454E): WRITE_CTRL bit 4 + * is set only on A0/A1 steppings (CMP [0xF0000008], 1; JA skip). + * On C0+ steppings, bit 4 is NOT set. + */ + uint32_t wr_ctrl = mchbar_read32(WRITE_CTRL) & 0x113ff3ff; + wr_ctrl |= 0x86000400; + if (northbridge_stepping() <= 0x01) + wr_ctrl |= 0x10; /* A0/A1 only */ + mchbar_write32(WRITE_CTRL, wr_ctrl); + + mchbar_clrsetbits32(MMARB0, ~0xfff9ffffU, 0x210000); + mchbar_clrsetbits32(MMARB1, ~0xfffffbffU, 0x300); +} + +/* ================================================================== */ +/* DDR2 Memory IO Init */ +/* ================================================================== */ + +/* + * ddr2_memory_io_init() - Configure DDR2 memory I/O (POST 0xFF28) + * + * Programs IO_INIT_CFG, DRAM_TYPE_SELECT, and related IO registers. + * + * BIOS equivalent: FFFF3D71 (72 bytes, POST 0xFF28) + */ +static void ddr2_memory_io_init_phase1(sysinfo_t *si) +{ + /* IO_INIT_CFG: clear bits 21,19,17,16; set bit 20 */ + mchbar_clrsetbits32(IO_INIT_CFG, 0x002e0000, 0x100000); + + /* IO_INIT_CFG7: set RCOMP code 0x36 */ + mchbar_setbits8(IO_INIT_CFG7, 0x36); + + /* DRAM_TYPE_SELECT: set channel enable bits based on rank population */ + int ch; + for (ch = 0; ch < 2; ch++) { + if (si->dimms[ch * 2].present) + mchbar_setbits32(DRAM_TYPE_SELECT, 0x80000000U >> ch); + } + mchbar_setbits32(DRAM_TYPE_SELECT, 0x4080); /* DDR2 mode + misc */ +} + +/* + * ddr2_memory_io_init_phase2() - Clock-dependent IO configuration (POST 0xFF29) + * + * BIOS equivalent: FFFF3DB9 (192 bytes, POST 0xFF29) + */ +static void ddr2_memory_io_init_phase2(sysinfo_t *si) +{ + int bytelane, ch; + + /* + * IO_INIT_CLK_DEP: clear bits [12:9]. + * Vendor uses 16-bit access (AND 0xe1ff) to avoid disturbing + * upper 16 bits at 0x140e which contain IO config state. + */ + mchbar_clrbits16(IO_INIT_CLK_DEP, 0x1e00); + + /* IO_INIT_CFG2: clock-dependent value from vendor ROM at 0xFFFF58FC. + * Verified: inteltool 0x1414 bits[20:17] = 0x0a for DDR2-667. */ + static const uint8_t io_cfg2_table[] = { 0, 0x0d, 0x0a, 0x08 }; + uint32_t cfg2_val = (uint32_t)io_cfg2_table[si->timings.mem_clock] << 17; + mchbar_clrsetbits32(IO_INIT_CFG2, 0x001f0000, cfg2_val); + + /* IO_INIT_CFG3/CFG4: clear bit 0 of each byte */ + mchbar_clrbits32(IO_INIT_CFG3, 0x01010101); + mchbar_clrbits32(IO_INIT_CFG4, 0x01010101); + + /* IO_INIT_CFG5: clock-dependent lower nibble from vendor ROM at 0xFFFF58E8. + * Verified: inteltool 0x142c low nibble = 0x0a for DDR2-667. */ + static const uint8_t io_cfg5_table[] = { 0, 0x0b, 0x0a, 0x00 }; + mchbar_clrsetbits8(IO_INIT_CFG5, 0x0f, io_cfg5_table[si->timings.mem_clock]); + + /* IO_INIT_CFG6: clear bits [21:20] */ + mchbar_clrbits32(IO_INIT_CFG6, 0x300000); + + /* Per-channel PI (Phase Interpolator) settings from vendor ROM at 0xFFFF58EC. + * Controls DQ byte lane timing - critical for data integrity. + * Verified: inteltool 0x1490-0x14ac = 0x00001111 for DDR2-667. */ + static const uint32_t pi_table[] = { 0, 0x00002121, 0x00001111, 0x00000000 }; + uint32_t pi_val = pi_table[si->timings.mem_clock]; + /* Vendor interleaves ch0/ch1 per byte lane. */ + for (bytelane = 0; bytelane < NUM_BYTELANES; bytelane++) { + for (ch = 0; ch < NUM_CHANNELS; ch++) + mchbar_write32(CxTRAIN_PI(ch) + bytelane * 4, pi_val); + } + + /* Per-channel training config: clear bit 0 if channel populated */ + for (ch = 0; ch < 2; ch++) { + if (si->dimms[ch * 2].present) + mchbar_clrbits8(CxTRAIN_CFG(ch), 0x01); + } +} + +/* + * program_rw_pointer_and_ddr_type() - Configure per-channel RW pointer & TYPE select (POST 0xFF30) + * + * BIOS equivalent: FFFF3E79 (46 bytes, POST 0xFF30) + */ +static void program_rw_pointer_and_ddr_type(sysinfo_t *si) +{ + int ch; + for (ch = 0; ch < 2; ch++) { + if (si->dimms[ch * 2].present) + mchbar_setbits32(RW_PTR_CTRL(ch), 0x300); + } + mchbar_setbits8(DRAM_TYPE_SELECT, 0x40); +} + +/* ================================================================== */ +/* DRAM Clock Enable */ +/* ================================================================== */ + +static void enable_dram_clocks(const sysinfo_t *si) +{ + int ch; + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + if (si->dimms[slot].present) + mchbar_setbits32(CxDCLKDIS_MCHBAR(ch), 0x3); /* Enable both clocks - 32-bit per vendor */ + } +} + +/* ================================================================== */ +/* JEDEC DDR2 Initialization Sequence */ +/* ================================================================== */ + +/* + * jedec_command() - Issue a single JEDEC command via DCC register + * + * The GM965 DCC register at MCHBAR+0x200 controls DRAM commands. + * Writing a command code to bits [18:16] initiates the command. + * The rank address is accessed via a read to the rank's base address. + * + * coreboot equivalent: jedec_command() in raminit.c + */ +static void jedec_command(uintptr_t rankaddr, uint32_t cmd, uint32_t val) +{ + mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, cmd); + read32((void *)(uintptr_t)(rankaddr | val)); +} + +/* + * get_rank_addr() - Get the base address for a rank + * + * Returns the physical address where rank (ch, rank) starts, derived + * from the DRB boundary registers written by prejedec_memory_map(). + * Rank N's start address = rank (N-1)'s upper boundary x 32 MB. + * + * Vendor approach (FFFF4573, FFFF5A98 ROM table): + * The vendor stores 8 pointers to individual 16-bit DRB entries + * in a ROM table at FFFF5A98. The JEDEC loop reads each pointer, + * dereferences it to get the DRB value, then does `<< 25` to + * convert 32 MB units to a byte address. The loop starts with + * rank_addr = 0 and computes the next rank's address at the end + * of each iteration. + * + * This function produces the same result via computed register + * offsets: read the previous rank's DRB, extract the boundary + * from the correct 16-bit half, and shift left by 25. + */ +static uintptr_t get_rank_addr(int ch, int rank) +{ + if (ch == 0 && rank == 0) + return 0; + + /* Start address = upper bound of the previous rank. */ + int prev_ch = ch, prev_rank = rank - 1; + if (prev_rank < 0) { + prev_ch = ch - 1; + prev_rank = 3; /* highest rank index per channel */ + } + uint32_t reg = mchbar_read32(CxDRBy_MCHBAR(prev_ch, prev_rank)); + /* Boundary in 32 MB units: even ranks in bits [8:2], odd in bits [24:18]. */ + uint32_t shift = (prev_rank % 2) * 16; + return ((reg >> shift) & 0x1fc) << 25; +} + +/* + * jedec_init_ddr2() - Run DDR2 JEDEC initialization sequence + * + * Per-rank command sequence (vendor FFF0194F, 635 bytes): + * NOP -> bit15 -> ABP -> EMRS2 -> EMRS3 -> EMRS1(ODT) -> + * MRS(DLL reset) -> ABP -> CBR -> CBR -> MRS(normal) -> + * EMRS1(OCD default) -> EMRS1(OCD exit) -> clear bit15 + * + * BIOS equivalent: FFF0194F (RAMINIT copy, POST 0xFF33, cold boot only) + */ +static void jedec_init_ddr2(sysinfo_t *si) +{ + timings_t *t = &si->timings; + + /* + * DDR2 MRS/EMRS bit encodings (address lines, shifted by 3 for bus width). + * These match the coreboot jedec_init_ddr2() implementation. + */ + int WR = ((t->tWR - 1) & 7) << 12; + int DLLreset = 1 << 11; + int CAS = (t->CAS & 7) << 7; + int BTinterleaved = 1 << 6; + int BL8 = 3 << 3; /* Burst Length 8 */ + int OCDdefault = 7 << 10; /* OCD Calibration Default */ + int ODT_150OHMS = (1 << 9); /* EMRS1 ODT = 150 ohm */ + + int ch, r; + + /* + * Pre-JEDEC setup (FSBPMC3, SBTEST, POST_JEDEC_TIM0/1) + * and write pointer enables (RW_PTR_CTRL bits [9:8]) are already done + * by the sequencer at POST 21 and POST 30 (vc1_isoch_timings). + * The vendor FFF0194F does NOT repeat them here. + */ + + /* JEDEC init sequence for each populated rank */ + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + if (!(slot < 4 && si->dimms[slot].present)) + continue; + + int max_rank = si->dimms[slot].dual_rank ? 2 : 1; + for (r = 0; r < max_rank; r++) { + uintptr_t raddr = get_rank_addr(ch, r); + + printk(BIOS_DEBUG, "JEDEC init: ch%d rank%d addr=0x%08lx\n", + ch, r, (unsigned long)raddr); + + /* + * Vendor (FFF019CA-FFF019E8): issue NOP first, + * then set bit 15 (JEDEC init active). Ordering + * matters - NOP must precede the JEDEC-active flag. + */ + mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, + DCC_CMD_NOP); + mchbar_setbits32(DCC_MCHBAR, 0x8000); + + /* 1. All Banks Precharge */ + jedec_command(raddr, DCC_CMD_ABP, 0); + + /* 2. EMRS2 (MR2) = 0 */ + jedec_command(raddr, DCC_SET_EREGx(2), 0); + + /* 3. EMRS3 (MR3) = 0 */ + jedec_command(raddr, DCC_SET_EREGx(3), 0); + + /* 4. EMRS1 (MR1): enable ODT */ + jedec_command(raddr, DCC_SET_EREG, ODT_150OHMS); + + /* 5. MRS (MR0): DLL reset + CAS + BL */ + jedec_command(raddr, DCC_SET_MREG, + WR | DLLreset | CAS | BTinterleaved | BL8); + + /* 6. All Banks Precharge */ + jedec_command(raddr, DCC_CMD_ABP, 0); + + /* 7. CBR Auto-Refresh (x2) */ + jedec_command(raddr, DCC_CMD_CBR, 0); + udelay(1); + read32((void *)(uintptr_t)raddr); /* second CBR via read */ + + /* 8. MRS (MR0): normal (no DLL reset) */ + jedec_command(raddr, DCC_SET_MREG, + WR | CAS | BTinterleaved | BL8); + + /* + * 9-10. EMRS1: OCD Calibration Default, then Exit. + * + * Vendor (FFF01B79-FFF01B99): sets DCC to EMRS1 + * once, then does two memory reads - OCD cal + * (raddr | 0x1E00) then OCD exit (raddr | 0x200). + * No DCC re-write between them since the command + * type is the same. + */ + mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, + DCC_SET_EREG); + read32((void *)(uintptr_t)(raddr + | OCDdefault | ODT_150OHMS)); + read32((void *)(uintptr_t)(raddr | ODT_150OHMS)); + + /* Clear DCC bit 15 - JEDEC init complete for this rank */ + mchbar_clrbits32(DCC_MCHBAR, 0x8000); + } + } +} + +/* + * post_jedec_sequence() - Transition to normal operation + * + * BIOS equivalent: FFFF3909 (37 bytes, POST 0xFF34) + * + * Clears DRAM_TYPE_SELECT bit 9, sets DCC interleaved mode + * for dual channel, and sets DCC bit 10 (normal operation announce). + */ +static void post_jedec_sequence(sysinfo_t *si) +{ + /* + * Clear DRAM_TYPE_SELECT bit 9 - use 16-bit access to avoid + * disturbing upper 16 bits (bits 31/30 = channel enables set + * at POST 28). Vendor: 16-bit AND 0xFDFF. + */ + mchbar_clrbits16(DRAM_TYPE_SELECT, 0x200); + + /* + * DCC: clear interleave bit, then set if dual-channel. + * BIOS: sets DCC_INTERLEAVED for any nonzero channel_mode + * (i.e., both DUAL_ASYNC and DUAL_INTERLEAVED). + */ + mchbar_clrbits32(DCC_MCHBAR, DCC_INTERLEAVED); + if (si->timings.channel_mode != CHANNEL_MODE_SINGLE) + mchbar_setbits32(DCC_MCHBAR, DCC_INTERLEAVED); + + /* DCC: set bit 10 - announce normal operation */ + mchbar_setbits32(DCC_MCHBAR, 0x400); +} + +/* ================================================================== */ +/* Final Timing Adjust (POST 0xFF36) */ +/* ================================================================== */ + +/* + * final_timing_adjust() - Post-JEDEC clock crossing and timing fixups + * + * BIOS equivalent: FFFF47A4 (125 bytes, POST 0xFF36) + * Sets per-channel clock crossing constants, clears pre-JEDEC bits, + * and programs final SBTEST / POST_JEDEC_TIM values. + */ +static void final_timing_adjust(sysinfo_t *si) +{ + /* Clear DCC bits [10:9] for dual-channel */ + if (si->timings.channel_mode == CHANNEL_MODE_DUAL_INTERLEAVED) + mchbar_clrbits32(DCC_MCHBAR, 0x600); + + /* Per-channel clock crossing constants (hardcoded from BIOS) */ + int ch; + for (ch = 0; ch < 2; ch++) { + mchbar_write32(CxAIT_LO(ch), 0x000006c4); + mchbar_write32(CxAIT_HI(ch), 0x871a066d); + } + + /* Clear CTRL0 bit 1 (pre-JEDEC mode) */ + mchbar_clrbits32(FSBPMC3, 1 << 1); + + /* Final SBTEST, POST_JEDEC_TIM0/1 values from BIOS */ + mchbar_clrsetbits32(SBTEST, 0x00080006U, 0x8000); + mchbar_clrsetbits32(POST_JEDEC_TIM0, 0x03404900U, 0x04bdb600); + mchbar_clrsetbits32(POST_JEDEC_TIM1, 0x03c04900U, 0x003db600); +} + +/* ================================================================== */ +/* DRAM Optimizations (POST 0xFF37) */ +/* ================================================================== */ + +/* + * dram_optimizations() - Set CxDRC1 SSDS field based on rank topology + * + * BIOS equivalent: FFFF4821 (106 bytes, POST 0xFF37) + * The SSDS (Self-refresh Single DIMM Suspend) field in the upper byte + * of CxDRC1 depends on how many ranks are populated per channel. + */ +static void dram_optimizations(sysinfo_t *si) +{ + /* + * SSDS lookup: indexed by rank topology per channel. + * 0 = no DIMM present + * 1 = at least one single-rank DIMM in channel + * 2 = all DIMMs dual-rank (no single-rank DIMMs) + * Values from BIOS ROM at 0xFFFF57C9 (stride 2: bytes 0,2,4). + * Verified: inteltool CxDRC1[31:24] = 0xb1 for dual-rank DIMMs. + */ + static const uint8_t ssds_table[] = { 0x00, 0x91, 0xb1 }; + + /* + * Stepping-dependent SSDS override. + * + * Vendor (FFF01C0D): On non-A0 steppings < 4 (including C0), + * the rank topology index is forced to 2 for all populated + * channels, regardless of whether the DIMM is actually + * dual-rank. This gives SSDS = 0xb1 for both single-rank + * and dual-rank DIMMs on C0 stepping. + * + * Without this, single-rank DIMMs get SSDS = 0x91 while the + * vendor always uses 0xb1 on C0. + */ + uint8_t stepping = northbridge_stepping(); + int force_dual_ssds = (stepping != 0x00 && stepping < 0x04); + + int ch; + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + int rank_count = 0; + if (slot < 4 && si->dimms[slot].present) { + rank_count = si->dimms[slot].dual_rank ? 2 : 1; + if (force_dual_ssds) + rank_count = 2; + } + mchbar_clrsetbits32(CxDRC1_MCHBAR(ch), 0xff000000, + (uint32_t)ssds_table[rank_count] << 24); + } +} + +/* ================================================================== */ +/* EPD Address Decode and Channel Enable (POST 0xFF41) */ +/* ================================================================== */ + +/* + * EPD timing lookup tables for FFF02A7A. + * + * These are extracted from the RAMINIT copy's stack-local arrays. + * Indexed by mem_clock (1=800MT, 2=667MT, 3=533MT). + */ + +/* tWTR equivalent for EPD (same as drt0_twtr_lut) */ +static const uint8_t epd_twtr[] = { + [0] = 2, + [MEM_CLOCK_533MT] = 2, + [MEM_CLOCK_667MT] = 3, +}; + +/* tRFC multiplier for EPD+0x19 bits [15:11] */ +static const uint8_t epd_trfc_mult[] = { + [0] = 9, + [MEM_CLOCK_533MT] = 12, + [MEM_CLOCK_667MT] = 15, +}; + +/* + * Slave-DLL-enable to read delay for EPD+0x24 (Tsdllen2nd in EGLK). + * Note: EGLK indexes this table starting from DDR2-400 (highest index = + * lowest frequency), opposite to the gm965 mem_clock enum ordering. + */ +static const uint8_t epd_rtp_pchg[] = { + [0] = 4, + [MEM_CLOCK_533MT] = 6, + [MEM_CLOCK_667MT] = 7, +}; + +/* tRTP alternate for EPD+0x22 */ +static const uint8_t epd_trtp_alt[] = { + [0] = 2, + [MEM_CLOCK_533MT] = 3, + [MEM_CLOCK_667MT] = 4, +}; + +/* + * epd_dra_encode() - Compute EPD DRA encoding for a DIMM + * + * Returns a 16-bit value: low byte = rank 0 DRA, high byte = rank 1 + * DRA (0 if single-rank, same as rank 0 if dual-rank). + * + * The produced encoding is identical to the CxDRA format used on x4x + * (Eaglelake) and other desktop 9xx/x3x chipsets: bit 7 set means the + * device uses a "large" geometry (>= 4 banks x >= 1KB page), and bits + * [2:0] encode the row/col/width combination. + * + * BIOS equivalent: FFF02A7A DRA loop (fff02b5c-fff02bea) + * + * The index is computed by FFF022DF (timing calculation) at + * fff02450-fff0245e and stored in per-DIMM sysinfo field[4]: + * MOV AL, [ESI+3] ; banks_flag (SPD[17]>>3: 0 or 1) + * ADD AL, [ESI+2] ; + x16_flag (0 or 1) + * ADD AL, [EDX+6] ; + cols + * ADD AL, [EDX+5] ; + rows + * SUB AL, 0x16 ; - 22 + * + * This equals the standard chip capacity index + 1: + * standard = rows + cols + log2(width) + log2(banks) - 28 + * vendor = rows + cols + x16_flag + banks_flag - 22 + * = standard + 1 + * + * Switch on index: + * index=0 -> skip index=1 -> base=0 + * index=2 -> base=2+(banks==8?2:0) + * index=3 -> base=6 index=4 -> base=8 + * result = base + x16; if result > 3 -> result |= 0x80 + */ +static uint16_t epd_dra_encode(const dimminfo_t *d) +{ + /* + * Vendor formula: rows + cols + x16_flag + banks_flag - 22 + * where x16_flag = (chip_width==16)?1:0, banks_flag = (banks==8)?1:0. + * + * Verified against disasm fff02450 and inteltool for two DIMMs: + * DIMM0 (13+10+1+1-22=3) -> base=6, +x16 -> enc=0x87 (ok) + * DIMM2 (14+10+0+1-22=3) -> base=6, +0 -> enc=0x86 (ok) + */ + int idx = d->rows + d->cols + + (d->x16 ? 1 : 0) + + ((d->banks == 8) ? 1 : 0) + - 22; + + if (idx < 0) + idx = 0; + if (idx > 4) + idx = 4; + + int base; + switch (idx) { + case 0: + return 0; /* 256Mb or less - skip */ + case 1: + base = 0; + break; + case 2: + base = (d->banks == 8) ? 4 : 2; + break; + case 3: + base = 6; + break; + case 4: + base = 8; + break; + default: + return 0; + } + + uint8_t enc = base + (d->x16 ? 1 : 0); + if (enc > 3) + enc |= 0x80; + + /* Low byte = rank 0, high byte = rank 1 (0 if single-rank) */ + return (uint16_t)enc | (d->dual_rank ? ((uint16_t)enc << 8) : 0); +} + +/* + * Compute the EPD_A0 upper 16-bit field from the rank-population bitmap. + * Replicates the vendor algorithm at FFF03088: walk each set bit index i; + * if first set bit record dl=i, else dl=i+1; result = (1 << (dl+1)) << 16. + */ +static uint32_t rank_bitmap_to_upper16(uint8_t rank_bitmap) +{ + int dl = 0, first = 1; + + for (int i = 0; i < 5; i++) { + if (rank_bitmap & (1 << i)) { + if (first || dl == 0) { + dl = i; + first = 0; + } else { + dl = i + 1; + } + } + } + return (1U << (dl + 1)) << 16; +} + +/* + * program_epd() - Program EPD address decode and timing + * + * Programs the secondary address decode registers at MCHBAR 0x0A00 + * that the memory controller uses for channel routing, scheduling, + * and the graphics engine's memory access path. + * + * Without this, the controller does not properly route transactions + * to channel 1, causing only channel 0 to function. + * + * BIOS equivalent: FFF02A7A (1603 bytes, called between POST 0xFF41-0xFF42) + * + * The RAMINIT copy at FFF0xxxx (55 functions) is the BIOS's actual + * execution path. The RAMINIT3 copy at FFFF3xxx (29 functions) that + * the rest of this file was based on omits this function entirely. + */ +static void program_epd(sysinfo_t *si) +{ + timings_t *t = &si->timings; + int slot; + unsigned int mc = t->mem_clock; + unsigned int cas = t->CAS; + uint32_t reg; + + /* + * Step 1: Copy rank boundary values from per-channel DRB regs + * to EPD. Values are halved (>> 1) with bit 15 of each + * 16-bit half cleared. + * + * BIOS: two iterations copying CxDRBy(ch,0) and CxDRBy(ch,2) + * to EPD+0x00/0x04 (ch0) and EPD+0x34/0x38 (ch1). + */ + static const uint32_t epd_c0drb[2] = { EPD_C0DRB01, EPD_C0DRB23 }; + static const uint32_t epd_c1drb[2] = { EPD_C1DRB01, EPD_C1DRB23 }; + for (int r = 0; r < 2; r++) { + uint32_t drb0 = mchbar_read32(CxDRBy_MCHBAR(0, r * 2)); + uint32_t drb1 = mchbar_read32(CxDRBy_MCHBAR(1, r * 2)); + mchbar_write32(epd_c0drb[r], (drb0 >> 1) & 0x7fff7fff); + mchbar_write32(epd_c1drb[r], (drb1 >> 1) & 0x7fff7fff); + } + + /* + * Step 2: Write DRA encoding for each DIMM slot. + * Ch0 DIMMs -> EPD_C0DRA01/C0DRA23 (16-bit per slot) + * Ch1 DIMMs -> EPD_C1DRA01/C1DRA23 (16-bit per slot) + * + * BIOS: loops 4 DIMMs, writes 16-bit values. + */ + static const uint32_t epd_dra[4] = { + EPD_C0DRA01, EPD_C0DRA23, + EPD_C1DRA01, EPD_C1DRA23, + }; + for (slot = 0; slot < 4; slot++) { + if (!si->dimms[slot].present) + continue; + mchbar_write16(epd_dra[slot], epd_dra_encode(&si->dimms[slot])); + } + + /* + * Step 3: Program timing fields. + * + * EPD+0x1C is programmed below (32-bit RMW to match vendor). + */ + + /* + * EPD+0x10: clear bit 2, set bit 3. + * + * Vendor (FFF02BFB): 32-bit RMW at 0xA10. Must use 32-bit + * to match vendor bus transaction width. + */ + mchbar_clrsetbits32(EPD_10, 0x04, 0x08); + + /* + * EPD+0x11: low 5 bits = CAS + 8. + * Vendor: 32-bit unaligned RMW at 0xA11. + */ + mchbar_clrsetbits32(EPD_11, 0x1f, (cas + 8) & 0x1f); + + /* + * EPD+0x13: (old & 1) | 4 - set bit 2, keep bit 0 + * Vendor: 8-bit access. + */ + mchbar_clrsetbits8(EPD_13, 0xfe, 0x04); + + /* + * EPD+0x14: low nibble = CAS + * Vendor: 8-bit access. + */ + mchbar_clrsetbits8(EPD_14, 0x0f, cas & 0x0f); + + /* + * EPD+0x15: bits [3:0] and bits [16:13] = CAS - 2 + * BIOS: (old & 0xFFFE1FF0) | (CAS-2)*0x2000 | (CAS-2) + */ + mchbar_clrsetbits32(EPD_15, ~0xfffe1ff0U, + (uint32_t)(cas - 2) | ((uint32_t)(cas - 2) << 13)); + + /* + * EPD+0x19: three sub-fields packed in 16 bits. + * + * bits [5:2] = max(tWTR_tbank2[mc], 2) * 4 + 8 + * bits [10:6] = tRCD + CAS + 3 + * bits [15:11]= tRFC_mult[mc] + * + * BIOS (fff02c97): LEA ECX,[ECX+EAX+3] where ECX=tRCD, EAX=CAS. + * + * Vendor uses three separate 32-bit unaligned RMW at 0x0A19. + * Each reads DWORD, modifies only the lower 16 bits, writes + * DWORD back. Must match vendor access width. + */ + { + unsigned int twtr = epd_twtr[mc]; + if (twtr < 2) + twtr = 2; + unsigned int f1 = twtr * 4 + 8; + unsigned int f2 = (t->tRCD + cas + 3); + unsigned int f3 = epd_trfc_mult[mc]; + + /* Step 1: bits [5:2] - vendor AND 0xFFFFFFC3 */ + mchbar_clrsetbits32(EPD_19, 0x3c, f1 & 0x3c); + /* Step 2: bits [10:6] - vendor AND DX,0xF83F (16-bit AND) */ + mchbar_clrsetbits32(EPD_19, 0x07c0, (f2 & 0x1f) << 6); + /* Step 3: bits [15:11] - vendor AND CH,0x07 */ + mchbar_clrsetbits32(EPD_19, 0xf800, (f3 & 0x1f) << 11); + } + + /* + * EPD+0x1B: two nibbles. + * low nibble = CAS + 4 + * high nibble = tWTR + 3 + CAS + * + * Vendor: two separate 32-bit unaligned RMW at 0x0A1B. + * Step 1: AND 0xFFFFFFF0, OR (CAS+4) + * Step 2: AND DL,0x0F (byte-width AND), OR (btb_wtr << 4) + */ + { + uint32_t lo = (cas + 4) & 0x0f; + uint32_t hi = (epd_twtr[mc] + 3 + cas) & 0x0f; + mchbar_clrsetbits32(EPD_1B, 0x0f, lo); + mchbar_clrsetbits32(EPD_1B, 0xf0, hi << 4); + } + + /* + * EPD+0x1C (EP channel timing): two 32-bit RMW operations. + * bits [8:0] = tRFC + * bits [16:13] = tRRD (raw clocks) + */ + { + mchbar_clrsetbits32(EPD_1C, 0x1ff, t->tRFC & 0x1ff); + mchbar_clrsetbits32(EPD_1C, 0x1e000, + (uint32_t)t->tRRD << 13); + } + + /* + * EPD+0x20: multiple fields. + * bits [3:0] = tWTR + 3 + CAS (BtB_WtR equivalent) + * bits [15:12]= tRP (raw cycle count) + * bit 10 = 1 (constant) + * BIOS (fff02d4f): MOVZX EDI,[EBP-6]; SHL EDI,0xc - writes + * the restored tRP value directly (param[0x39]+2 = tRP). + * Previously added a spurious +2. + */ + { + unsigned int btb_wtr = (epd_twtr[mc] + 3 + cas) & 0x0f; + reg = mchbar_read32(EPD_20); + reg = (reg & 0xfffffff0) | btb_wtr; + reg = (reg & 0xffff04ff) | 0x400 | ((uint32_t)t->tRP << 12); + mchbar_write32(EPD_20, reg); + } + + /* + * EPD+0x22: bits [8:0] = tRTP_alt[mc] + tRFC + * Vendor: 32-bit unaligned RMW at 0x0A22. + */ + mchbar_clrsetbits32(EPD_22, 0x1ff, + (epd_trtp_alt[mc] + t->tRFC) & 0x1ff); + + /* + * EPD+0x24: various fields including tRTP_precharge. + * BIOS: bits [14:12] = 0xe20, plus bStack_b shifted << 20 in + * the 32-bit view from 0x24. The exact layout is: + * (old & 0xFF8FCFE7) | 0xE20 | (rtp_pchg << 20) + */ + { + reg = mchbar_read32(EPD_24); + reg = (reg & 0xff8fcfe7) | 0xe20 + | ((uint32_t)epd_rtp_pchg[mc] << 20); + mchbar_write32(EPD_24, reg); + } + + /* + * EPD+0x28: rank mode / scheduling. + * + * BIOS: clear bit 0 first, then: + * iVar11 = 3 (no ch0 DIMM), or (ch0_single_rank?1:0)+1 + * (old & 0xFB07FD90) | 0x60190 | (iVar11 << 20) | 0x3000000 + * + * Also: (old & 0xFFFF04FF) | rank-dependent bits for dual-rank + */ + { + int rank_mode; + int ch0_pop = si->dimms[0].present || si->dimms[1].present; + if (!ch0_pop) { + rank_mode = 3; + } else { + /* + * BIOS (fff02e02-fff02e12): checks first DIMM's + * dual_rank flag directly: + * CMP [ESI+0x01], 0x01; SETZ CL; INC ECX + * dual_rank -> rank_mode=2, single -> rank_mode=1 + */ + int has_dual = 0; + for (slot = 0; slot < 2; slot++) { + if (si->dimms[slot].present + && si->dimms[slot].dual_rank) + has_dual = 1; + } + rank_mode = has_dual ? 2 : 1; + } + + mchbar_clrbits32(EPD_28, 1); + reg = mchbar_read32(EPD_28); + reg = (reg & 0xfb07fd90) | 0x60190 + | ((uint32_t)rank_mode << 20) + | 0x3000000; + mchbar_write32(EPD_28, reg); + } + + /* + * EPD+0x2C: two 32-bit RMW operations. + * Vendor (fff02e43): AND 0xFFFFFFFA, OR 2 -> then AND CL,0x17 OR 0x10. + * Net result byte 0 = 0x12, but vendor bus transactions are 32-bit. + */ + mchbar_clrsetbits32(EPD_2C, 0x05, 0x02); + mchbar_clrsetbits32(EPD_2C, 0xe8, 0x10); + + /* + * EPD+0x2D: set bits [4:0], clear bits [6:5]. + * Vendor (fff02e67): 32-bit unaligned RMW at 0x0A2D. + */ + mchbar_clrsetbits32(EPD_2D, 0x60, 0x1f); + + /* + * EPD+0x30: mode control register. + * + * BIOS (fff02e79-fff02ee9) builds this in 5 steps, clearing + * fields before setting: + * 1. Lower 16: AND 0xc820, OR 0x0820 -> set bits 11,5 + * 2. AND 0xfffd3fff, OR 0x10000 -> set bit 16 + * 3. AND 0xffdbffff, OR 0x180000 -> set bits 19,20 + * 4. AND 0xfd3fffff, OR 0x1000000 -> set bit 24 + * 5. AND 0xdfffffff, OR 0x40000000 -> set bit 30 + * + * Previous code only OR'd without clearing, leaving stale bits. + */ + { + /* + * Vendor (FFF02E79) does 5 separate read-modify-write + * cycles. The masks never touch bits [28:27] - those + * are preserved from the initial value. Bits [28:27] + * are set by a post-raminit BIOS module (not raminit). + */ + uint32_t reg30 = mchbar_read32(EPD_30); + /* Step 1: clear lower 16 except bits 15,14,11,5; set 11,5 */ + reg30 = (reg30 & 0xffffc820) | 0x820; + /* Step 2: set bit 16, clear bits 17,15,14,13 */ + reg30 = (reg30 & 0xfffd1fff) | 0x10000; + /* Step 3: set bits 19,20; clear bits 21,18 */ + reg30 = (reg30 & 0xffd3ffff) | 0x180000; + /* Step 4: set bit 24; clear bits 25,23,22 */ + reg30 = (reg30 & 0xfd3fffff) | 0x1000000; + /* Step 5: set bit 30; clear bit 29 */ + reg30 = (reg30 & 0xdfffffff) | 0x40000000; + mchbar_write32(EPD_30, reg30); + } + + /* + * EPD+0x99: CAS-dependent scheduling. + * bits [10:9] = CAS - 3 (vendor CAS encoding) + * BIOS: multiple field writes in 0x99/0x9C region. + */ + { + unsigned int cas_enc = cas - 3; + mchbar_clrsetbits32(EPD_99, 0x0600, cas_enc << 9); + mchbar_clrbits32(EPD_99, 0x000f0000); + + /* + * EPD+0x9C: additional CAS and rank-dependent bits. + * BIOS programs this region with complex multi-step RMW. + * The key patterns are: + * bits [15:0]: 0x55 | rank-dependent + * bits [16]: CAS-dependent + * bits [19:17]: CAS-3 + * bits [22:20]: CAS-3 + * bits [24:23]: CAS + * bit [25]: 1 + * bits [31:26]: 0x55 pattern + */ + int ch0_pop = si->dimms[0].present || si->dimms[1].present; + int rank_adj = 0; + if (ch0_pop) { + /* + * BIOS (fff02f14-fff02f22): + * DEC DL; NEG DL; SBB EDX,EDX; ADD EDX,0xa + * dual_rank -> rank_adj=10, single -> rank_adj=9 + */ + int has_dual = 0; + for (slot = 0; slot < 2; slot++) { + if (si->dimms[slot].present + && si->dimms[slot].dual_rank) + has_dual = 1; + } + rank_adj = has_dual ? 10 : 9; + } + + reg = mchbar_read32(EPD_9C); + reg &= 0xfff88855; + /* + * BIOS (fff02f38-fff02f85) builds lower 16 bits: + * byte[0xa9c] = 0x55 (AND 0xf5|0x05, AND 0x5f|0x50) + * byte[0xa9d] = 0x88 (AND 0xf8|0x08, AND 0x8f|0x80) + * Previously had 0x88 which put the 0x88 into the wrong + * byte, producing 0x00dd instead of 0x8855. + */ + reg |= 0x8855 | ((uint32_t)cas_enc << 16) + | ((uint32_t)cas_enc << 19) + | ((uint32_t)cas << 22) + | (1 << 25); + mchbar_write32(EPD_9C, reg); + + /* Clear bit 25 after setting (latch) */ + mchbar_clrbits32(EPD_9C, 1 << 25); + + /* + * EPD_9C bit 31: timing commit flag. + * + * Vendor BIOS (FFF02FE9-FFF02FF8) sets bit 31 as the + * FINAL step after all CAS/tRAS timing fields are + * programmed. The sequence is: + * AND EAX, 0x0FFFFFFF ; clear bits [31:28] + * OR EAX, 0x80000000 ; set bit 31 + * MOV [0xfed14a9c], EAX + * + * Inteltool confirms: vendor=0x81528855 (bit 31 SET), + * coreboot=0x015200dd (bit 31 CLEAR). + */ + mchbar_clrsetbits32(EPD_9C, 0xf0000000U, 0x80000000U); + + /* Apply rank adjustment to bits [23:20] of EPD_99 */ + if (rank_adj) { + /* + * BIOS (fff02f2b): SHL EDX, 0x14 (<<20, not <<16) + * BIOS (fff02f2e): AND EBX, 0xff0fffff (clear [23:20]) + */ + reg = mchbar_read32(EPD_99); + reg = (reg & 0xff0fffff) | ((uint32_t)rank_adj << 20); + mchbar_write32(EPD_99, reg); + } + + /* Set constant high-order pattern */ + mchbar_setbits32(EPD_99, 0x55000000); + } + + /* + * EPD+0x2E: set bit 5 for DDR2-533 (mem_clock == 1). + * Vendor (fff03005): OR dword [0xfed14a2e], 0x20 - 32-bit unaligned. + */ + if (mc == MEM_CLOCK_533MT) + mchbar_setbits32(EPD_2E, 0x20); + + /* + * EPD+0xA0: per-channel rank topology and rank enable. + * + * The RAMINIT copy at FFF01C47 (dram_optimizations) builds + * per-channel rank config bytes at sysinfo+0x43/0x44: + * 0x00 = no DIMMs on channel + * 0x03 = single-rank DIMM (bits [1:0] = chip selects active) + * 0x07 = dual-rank DIMM (bit 2 = dual-rank flag + bits [1:0]) + * + * These are then written to EPD+0xA0 by FFF02A7A: + * bits [2:0] = ch0 rank config (0x03 or 0x07) + * bits [5:4] = ch0 rank topology (0x01=single, 0x03=dual) + * bits [10:8] = ch1 rank config (0x03 or 0x07) + * bits [13:12] = ch1 rank topology (0x01=single, 0x03=dual) + * + * RAMINIT3 (FFFF4821) does NOT build the rank config bytes. + * Without bits [2:0] and [10:8], the EPD address decode + * does not enable rank 1, causing data corruption on dual-rank + * DIMMs (bit-shift errors). + * + * BIOS: _DAT_fed14aa0 = + * ((ch1_cfg << 8) | (old & 0xfffff8f8) | ch0_cfg) & + * 0xffff0f0f | rank_topology_overlay; + */ + { + int ch0_pop = si->dimms[0].present || si->dimms[1].present; + int ch1_pop = si->dimms[2].present || si->dimms[3].present; + + if (ch0_pop || ch1_pop) { + uint32_t rank_topo = 0; + uint8_t ch0_cfg = 0, ch1_cfg = 0; + + /* + * Stepping-dependent rank config override. + * + * Vendor (FFF01C0D): On non-A0 steppings < 4 + * (including C0 = stepping 3 on the X61), the + * rank config byte is forced to 0x07 for ALL + * populated channels regardless of dual-rank. + * + * The vendor builds the rank config in a separate + * function (dram_optimizations, POST FF37) with: + * if (stepping != 0 && stepping < 4): + * if (ch_has_dimm): iVar = 2 + * iVar=2 -> ch_cfg = 4|3 = 0x07 + * + * Without this, single-rank DIMMs get ch_cfg=0x03 + * while the vendor always uses 0x07 on C0. + */ + uint8_t stepping = northbridge_stepping(); + int force_cfg = (stepping != 0x00 && stepping < 0x04); + + /* Ch0: rank config byte + topology */ + if (ch0_pop) { + int ch0_dual = 0; + for (slot = 0; slot < 2; slot++) { + if (si->dimms[slot].present + && si->dimms[slot].dual_rank) + ch0_dual = 1; + } + ch0_cfg = (ch0_dual || force_cfg) ? 0x07 : 0x03; + rank_topo |= ch0_dual ? 0x30 : 0x10; + } + + /* Ch1: rank config byte + topology */ + if (ch1_pop) { + int ch1_dual = 0; + for (slot = 2; slot < 4; slot++) { + if (si->dimms[slot].present + && si->dimms[slot].dual_rank) + ch1_dual = 1; + } + ch1_cfg = (ch1_dual || force_cfg) ? 0x07 : 0x03; + rank_topo |= ch1_dual ? 0x3000 : 0x1000; + } + + /* + * Build EPD+0xA0: + * 1. Clear bits [2:0] and [10:8] (rank config) + * 2. Write ch0_cfg and ch1_cfg + * 3. Clear bits [7:4] and [15:12] (topology) + * 4. Write rank topology overlay + * 5. Compute upper 16 bits from rank population bitmap + */ + reg = mchbar_read32(EPD_A0); + reg = (reg & 0xfffff8f8) | ch0_cfg + | ((uint32_t)ch1_cfg << 8); + reg = (reg & 0xffff0f0f) | rank_topo; + + /* + * Upper 16 bits: rank population count indicator. + * + * RAMINIT FFF03075-FFF030B2 walks a rank bitmap (sysinfo+0x30, + * up to 5 entries) and computes a value shifted into bits [31:16]. + * The algorithm tracks the bit index of each populated rank: + * - First two populated entries: records the bit index + * - Subsequent entries: increments the recorded index by 1 + * Then: upper16 = (1 << (result + 1)) << 16. + * + * For the X61 with 2 dual-rank DIMMs (4 ranks total, bitmap + * bits 0-3), the result is 4, giving (1 << 5) << 16 = 0x200000. + * Vendor inteltool: EPD_A0 = 0x00203737 (bit 21 set). + * + * Build the bitmap: one bit per rank, ordered by slot: + * bit 0 = ch0 slot0 rank0, bit 1 = ch0 slot0 rank1, + * bit 2 = ch1 slot0 rank0, bit 3 = ch1 slot0 rank1. + */ + { + uint8_t rank_bitmap = 0; + int bit = 0; + for (slot = 0; slot < 4; slot++) { + if (si->dimms[slot].present) { + rank_bitmap |= (1 << bit); + bit++; + if (si->dimms[slot].dual_rank) { + rank_bitmap |= (1 << bit); + bit++; + } + } + } + if (rank_bitmap) + reg = (reg & 0xffff) | + rank_bitmap_to_upper16(rank_bitmap); + } + + mchbar_write32(EPD_A0, reg); + } + } + + printk(BIOS_DEBUG, "EPD: DRB0=0x%08x DRB1=0x%08x " + "DRA0=0x%04x DRA1=0x%04x A0=0x%08x\n", + mchbar_read32(EPD_C0DRB01), + mchbar_read32(EPD_C1DRB01), + mchbar_read16(EPD_C0DRA01), + mchbar_read16(EPD_C1DRA01), + mchbar_read32(EPD_A0)); +} + +/* + * program_channel_population() - Set channel enable bits in EPD + * + * Programs EPD+0x2F with per-channel population flags and sets + * EPD+0x30 bit 26. Without bit 1 in EPD+0x2F, the memory + * controller does not route transactions to channel 1. + * + * BIOS equivalent: FFF03286 (112 bytes, between POST 0xFF41-0xFF42) + * + * This function also restores RCOMP_CFG3 state and handles the + * D3:F0 cleanup from the JEDEC init phase. + */ +static void program_channel_population(sysinfo_t *si) +{ + /* + * EPD+0x2F: set per-channel population bits. + * bit 0 = channel 0 has at least one DIMM + * bit 1 = channel 1 has at least one DIMM + * + * BIOS (FFF032AB-FFF032CA): checks each DIMM slot presence. + */ + uint8_t pop = 0; + + if (si->dimms[0].present || si->dimms[1].present) + pop |= 1; /* ch0 populated */ + if (si->dimms[2].present || si->dimms[3].present) + pop |= 2; /* ch1 populated */ + + /* + * Vendor (FFF032B4/FFF032C5): OR dword [0xfed14a2f], 1/2 + * - 32-bit unaligned writes. Match vendor access width. + */ + if (pop & 1) + mchbar_setbits32(EPD_2F, 1); + if (pop & 2) + mchbar_setbits32(EPD_2F, 2); + + /* + * EPD+0x30: set bit 26. + * BIOS (FFF032CC): OR dword [0xfed14a30], 0x4000000 + */ + mchbar_setbits32(EPD_30, 1 << 26); + + printk(BIOS_DEBUG, "EPD channel population: 0x%02x " + "(ch0=%d ch1=%d) EPD_30=0x%08x\n", + mchbar_read8(EPD_2F), pop & 1, (pop >> 1) & 1, + mchbar_read32(EPD_30)); +} + +/* ================================================================== */ +/* DRAM Power Management (POST 0xFF41/0xFF43) */ +/* ================================================================== */ + +/* + * dram_power_mgmt() - Configure DRAM power management and throttling + * + * BIOS equivalent: FFF0255E (202 bytes, RAMINIT copy POST 0xFF43) + * Hardcoded register sequence - no sysinfo inputs. + * + * Vendor register sequence (22 operations, no conditionals): + * 1-2. Copy TSC1B[6:0] -> TSC0 (per channel) - seed thermal sensor + * 3-4. PM_CH_CTRL = 0 (per channel) + * 5-6. PM_CH_THRT0: ch0 = 0x17, ch1 = 0 + * 7-8. PM_CH_THRT1 = 0 (per channel) + * 9-10. PM_CH_TSC1 = 0x98 (per channel) + * 11-12. PM_THRT_MODE = 0x0E, PM_THRT_CTRL = 1 + * 13-14. PM_CH_CMD: ch0 = 0x9200, ch1 = 0 + * 15-16. PM_CH_THRT0 |= 0x80000000 (per channel) + * 17-18. PM_CH_TSC0 |= 0x80 (per channel) + * 19-20. PM_CH_TSC1 |= 0x01 (per channel) -> 0x98 becomes 0x99 + * 21-22. CxPWR_THROTTLE1 |= 0x80000000 (per channel) + */ +static void dram_power_mgmt(void) +{ + /* + * 1-2: Seed TSC0 from TSC1B with bit 7 cleared. + * Vendor reads the thermal sensor readback (TSC1B) and copies + * its lower 7 bits into TSC0 before enabling the sensor. + */ + mchbar_write8(PM_CH_TSC0(0), mchbar_read8(PM_CH_TSC1B(0)) & 0x7f); + mchbar_write8(PM_CH_TSC0(1), mchbar_read8(PM_CH_TSC1B(1)) & 0x7f); + + /* 3-4: Clear PM channel control */ + mchbar_write8(PM_CH_CTRL(0), 0); + mchbar_write8(PM_CH_CTRL(1), 0); + + /* 5-6: PM throttle 0 - ch0 gets base value, ch1 gets 0 */ + mchbar_write32(PM_CH_THRT0(0), 0x17); + mchbar_write32(PM_CH_THRT0(1), 0); + + /* 7-8: PM throttle 1 - both channels 0 */ + mchbar_write32(PM_CH_THRT1(0), 0); + mchbar_write32(PM_CH_THRT1(1), 0); + + /* 9-10: Thermal sensor control 1 - base value (bit 0 set later) */ + mchbar_write8(PM_CH_TSC1(0), 0x98); + mchbar_write8(PM_CH_TSC1(1), 0x98); + + /* 11-12: Global throttle mode and control */ + mchbar_write8(PM_THRT_MODE, 0x0e); + mchbar_write8(PM_THRT_CTRL, 1); + + /* 13-14: PM command - ch0 active, ch1 idle */ + mchbar_write16(PM_CH_CMD(0), 0x9200); + mchbar_write16(PM_CH_CMD(1), 0); + + /* 15-16: Enable PM throttle 0 (set bit 31) */ + mchbar_setbits32(PM_CH_THRT0(0), 1 << 31); + mchbar_setbits32(PM_CH_THRT0(1), 1 << 31); + + /* 17-18: Enable thermal sensor (set bit 7 of TSC0) */ + mchbar_setbits8(PM_CH_TSC0(0), 0x80); + mchbar_setbits8(PM_CH_TSC0(1), 0x80); + + /* 19-20: Set TSC1 bit 0 (0x98 -> 0x99) */ + mchbar_setbits8(PM_CH_TSC1(0), 1); + mchbar_setbits8(PM_CH_TSC1(1), 1); + + /* 21-22: Enable power throttle 1 (set bit 31) */ + mchbar_setbits32(CxPWR_THROTTLE1(0), 1 << 31); + mchbar_setbits32(CxPWR_THROTTLE1(1), 1 << 31); +} + +/* ================================================================== */ +/* Warm Boot / S3 Resume Detection */ +/* ================================================================== */ + +/* + * check_warm_boot() - Check SSKPD and PMSTS for warm boot indicator + * + * BIOS equivalent: FFFE0F2D (sskpd_check) - checks for 0xCAFE marker + * If SSKPD contains 0xCAFE, this is a warm boot and we can skip + * full raminit (just restore timing settings). + * + * BIOS equivalent: FFFF5115 checks MCHBAR+0x0F14 (PMSTS) + * If PMSTS bits [1:0] == 2, warm reset needed + * If PMSTS bit 0 set, self-refresh was maintained + */ +static int check_warm_boot(void) +{ + /* Check SSKPD for magic marker */ + uint16_t sskpd = mchbar_read16(SSKPD_MCHBAR); + if (sskpd == 0xCAFE) + return 1; + + /* Check PMSTS for self-refresh state */ + uint32_t pmsts = mchbar_read32(PMSTS_MCHBAR); + if (pmsts & PMSTS_SELFREFRESH) + return 1; + + return 0; +} + +/* + * reset_on_stale_rcomp() - Reset if RCOMP engine has stale state + * + * Vendor BIOS (FFF00240 / FFFF3220): if the MCH stepping is A0 + * (D0:F0 revision == 0x00) and RCOMP_CTRL bit 1 is set from a + * prior boot, issue a warm reset (CF9=0x06) to clear MCH state. + * + * The vendor guards this with the stepping byte at MMCONFIG + * D0:F0+0x08 (DAT_f0000008), NOT with PMSTS. On A1+ steppings + * (including C0 on the ThinkPad X61), this check never fires. + */ +static void reset_on_stale_rcomp(void) +{ + uint8_t stepping = northbridge_stepping(); + uint32_t rcomp = mchbar_read32(RCOMP_CTRL); + + if (stepping == 0x00 && (rcomp & 2)) { + printk(BIOS_DEBUG, "raminit: A0 stepping RCOMP_CTRL=0x%08x " + "stale - warm reset\n", rcomp); + system_reset(); + } +} + +/* + * init_pmcon() - Set up ICH8 GEN_PMCON registers at raminit entry + * + * Vendor BIOS (FFFF3220, disasm at FFFF3304-FFFF3346): + * 1. If GEN_PMCON_3 bit 3 (SLP_S3# stretch) set from prior boot: + * clear bits 1 (RTC_POWER_FAILED) and 3 (SLP_S3# stretch). + * 2. GEN_PMCON_2: clear status bits 0,3,4; then set bit 7 + * ("DRAM init in progress"). + * + * The bit 7 flag is cleared at POST FF42 when raminit completes. + * If the system resets mid-init, bit 7 remains set - the ICH8 can + * use this to distinguish a clean boot from an interrupted one. + * + * Vendor does two separate writes to GEN_PMCON_2: + * FFFF3304: read, AND 0xE6, write (clear status bits) + * FFFF333D: read, OR 0x80, write (set DRAM_INIT) + */ +static void init_pmcon(void) +{ + if (pci_read_config8(D31F0, D31F0_GEN_PMCON_3) & GEN_PMCON_3_SLP_S4_STRETCH) + pci_and_config8(D31F0, D31F0_GEN_PMCON_3, + (u8)~(RTC_POWER_FAILED | GEN_PMCON_3_SLP_S4_STRETCH)); + + /* Clear status bits 0,3,4 (first write) */ + pci_and_config8(D31F0, D31F0_GEN_PMCON_2, GEN_PMCON_2_W1C_BITS); + + /* Set DRAM init in progress (second write) */ + pci_or_config8(D31F0, D31F0_GEN_PMCON_2, GEN_PMCON_2_DRAM_INIT); +} + +/* + * check_bad_warmboot() - POST FF17: Reset if in bad warm boot state + * + * Vendor BIOS (FFFF5115, disasm at FFFF5120-FFFF5157): + * If PMSTS bits[1:0] == 2 (warm reset without self-refresh): + * 1. GEN_PMCON_3 |= 0x08 - enable SLP_S3# assertion stretch + * 2. GEN_PMCON_2 &= 0x7F - clear DRAM init in progress + * 3. PMSTS |= 2 - confirm warm reset state + * 4. full_reset() - CF9=0x0E (cold reset, never returns) + * + * The PMCON manipulation before reset ensures the ICH8 won't + * assert SLP_S3# prematurely during the reset, and records that + * DRAM init was not in progress when the reset was issued. + */ +static void check_bad_warmboot(void) +{ + uint32_t pmsts = mchbar_read32(PMSTS_MCHBAR); + if ((pmsts & 3) != 2) + return; + + printk(BIOS_DEBUG, "raminit: PMSTS=0x%08x bad warmboot at POST 17" + " - PMCON cleanup + full reset\n", pmsts); + + /* SLP_S3# assertion stretch - prevent premature power-down */ + pci_or_config8(D31F0, D31F0_GEN_PMCON_3, GEN_PMCON_3_SLP_S4_STRETCH); + + /* Clear DRAM init in progress */ + pci_and_config8(D31F0, D31F0_GEN_PMCON_2, (u8)~GEN_PMCON_2_DRAM_INIT); + + /* Confirm warm reset state in PMSTS */ + mchbar_setbits32(PMSTS_MCHBAR, PMSTS_WARM_RESET); + + full_reset(); +} + +/* ================================================================== */ +/* Main RAMINIT Entry Point */ +/* ================================================================== */ + +/* + * raminit() - Full DDR2 memory initialization + * + * Orchestrates the complete DRAM init sequence: + * 1. SPD scan and DIMM detection + * 2. Frequency and CAS latency selection + * 3. Timing parameter calculation + * 4. Clock configuration + * 5. RCOMP calibration + * 6. Pre-JEDEC memory map + * 7. JEDEC DDR2 init sequence + * 8. Post-JEDEC configuration + * 9. Final memory map + * 10. Receive-enable training + * 11. EPD address decode + channel population (from RAMINIT copy) + * + * BIOS POST code progression: 0xFF01 -> 0xFF43 + * + * BIOS equivalent: + * RAMINIT FFF00240 (main) -> FFF01D4F (sequencer) -> FFF02A7A (EPD) + * RAMINIT3 FFFF3220 (main) -> FFFF5115 (sequencer, no EPD) + * + * coreboot equivalent: raminit() in raminit.c + */ +void raminit(sysinfo_t *si) +{ + int fast_boot = 0; + + /* Get board-specific SPD address -> DIMM slot mapping */ + mainboard_get_spd_map(si->spd_addr_map); + + /* Check for warm boot / S3 resume */ + si->s3_resume = check_warm_boot(); + + reset_on_stale_rcomp(); + init_pmcon(); + + /* Attempt fast boot using MRC cache on any boot */ + { + size_t mrc_size = 0; + struct gm965_mrc_cache *cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); + if (cached && mrc_size == sizeof(struct gm965_mrc_cache) && + cached->cpu_id == cpu_get_cpuid()) { + /* Verify SPD unique CRCs for populated slots */ + int valid = 1; + for (int slot = 0; slot < 4; slot++) { + if (cached->dimms[slot].present) { + u16 crc = spd_read_unique_crc(si->spd_addr_map[slot]); + if (crc != cached->spd_crc[slot]) { + valid = 0; + break; + } + } + } + if (valid) { + copy_cache_to_si(si, cached); + fast_boot = 1; + printk(BIOS_DEBUG, "%s: fast boot from MRC cache\n", __func__); + } + } + } + + if (!fast_boot) { + printk(BIOS_DEBUG, "%s: cold boot - scanning DIMMs\n", __func__); + detect_dimms(si); + printk(BIOS_DEBUG, "%s: %d DIMM(s), %d channel(s)\n", + __func__, si->dimm_count, si->channels); + + printk(BIOS_DEBUG, "%s: selecting frequency and CAS\n", __func__); + select_frequency_and_cas(si); + + printk(BIOS_DEBUG, "%s: calculating timings\n", __func__); + calculate_timings(si); + } + + /* + * POST 0xFF17: Bad warm boot check (vendor: FFFF5115). + * If PMSTS bits[1:0]==2, clean up GEN_PMCON registers and + * issue full reset (CF9=0x0E). Must run after init_pmcon() + * set DRAM_INIT but before the sequencer steps begin. + */ + check_bad_warmboot(); + + /* PMSTS bit 0: mark raminit in progress (vendor: FFFF515D) */ + mchbar_setbits32(PMSTS_MCHBAR, PMSTS_SELFREFRESH); + + /* + * POST 0xFF18: Program DRAM frequency in CLKCFG and relock PLL. + * BIOS: FFFF4DF7 (121 bytes) + FFF009AD (PLL) + FFF00A8E (UPDATE toggle) + */ + program_clkcfg_lock(si); + + /* + * POST 0xFF19: IGD GCFGC render/sampler clock setup + * BIOS: FFFF3844 - programs D2F0+0xF0 (GCFGC), NOT CLKCFG + * CLKCFG was already programmed inline at POST 0xFF18 above. + */ + printk(BIOS_DEBUG, "%s: POST 19 - program_gcfgc\n", __func__); + program_gcfgc(si); + + printk(BIOS_DEBUG, "%s: POST 20 - set_clkcross_frequencies\n", __func__); + set_clkcross_frequencies(si); + + printk(BIOS_DEBUG, "%s: POST 21 - pre-JEDEC MCHBAR regs\n", __func__); + mchbar_setbits32(FSBPMC3, 1 << 1); + mchbar_setbits32(SBTEST, 6); + mchbar_setbits32(POST_JEDEC_TIM0, 0x3000000); + mchbar_setbits32(POST_JEDEC_TIM1, 0x3000000); + + printk(BIOS_DEBUG, "%s: POST 22 - prejedec_memory_map\n", __func__); + if (!si->s3_resume) + prejedec_memory_map(si); + + printk(BIOS_DEBUG, "%s: POST 23 - rcomp_init\n", __func__); + rcomp_init(si); + + printk(BIOS_DEBUG, "%s: POST 24 - odt_pre_setup\n", __func__); + odt_pre_setup(si); + + printk(BIOS_DEBUG, "%s: POST 25 - program_timings\n", __func__); + program_timings(si); + program_dram_control(si); + + printk(BIOS_DEBUG, "%s: POST 26 - misc_odt_settings\n", __func__); + misc_odt_settings(si); + + printk(BIOS_DEBUG, "%s: POST 27 - ddr2_odt_setup\n", __func__); + ddr2_odt_setup(si); + + printk(BIOS_DEBUG, "%s: POST 28 - ddr2_memory_io_init_phase1\n", __func__); + ddr2_memory_io_init_phase1(si); + + printk(BIOS_DEBUG, "%s: POST 29 - ddr2_memory_io_init_phase2\n", __func__); + ddr2_memory_io_init_phase2(si); + + printk(BIOS_DEBUG, "%s: POST 30 - program_rw_pointer_and_ddr_type\n", __func__); + program_rw_pointer_and_ddr_type(si); + + printk(BIOS_DEBUG, "%s: POST 31 - enable_dram_clocks\n", __func__); + enable_dram_clocks(si); + + /* + * POST 0xFF32: Wait for RCOMP calibration to complete. + * + * Vendor BIOS (FFFF5115): polls RCOMP_CTRL bit 0 in an infinite + * loop - no timeout. If RCOMP never completes the system hangs + * here, which is correct: proceeding with uncalibrated DRAM I/O + * impedances causes silent data corruption. + * + * Vendor guard: stepping != A1 (DAT_f0000008 != 0x01). + * On A1 stepping only the RCOMP wait is skipped. + * A0 and C0 always wait regardless of cold/warm boot. + */ + printk(BIOS_DEBUG, "%s: POST 32 - waiting for RCOMP " + "(RCOMP_CTRL=0x%08x)\n", __func__, mchbar_read32(RCOMP_CTRL)); + if (northbridge_stepping() != 0x01) { + while (mchbar_read32(RCOMP_CTRL) & 1) + ; + printk(BIOS_DEBUG, "%s: RCOMP done " + "(RCOMP_CTRL=0x%08x)\n", + __func__, mchbar_read32(RCOMP_CTRL)); + } + + /* + * RCOMP teardown (vendor FFFF52BD): + * RCOMP_CFG3 &= ~(1<<17) - clear comparator arm bit + * RCOMP_CTRL &= 0xfffcffcf - clear bits 17,16,5,4 + * CFG3 must be cleared before CTRL. + */ + mchbar_clrbits32(RCOMP_CFG3, 1 << 17); + mchbar_clrbits32(RCOMP_CTRL, (3 << 16) | (3 << 4)); + + /* + * POST 0xFF33: JEDEC initialization. + * + * RAMINIT has two JEDEC init functions - only ONE runs per boot: + * Cold boot (sysinfo[0x40]=0): FFF0194F runs for all ranks. + * FFF030BD is SKIPPED. + * Warm boot (sysinfo[0x40]=1): FFF030BD runs. + * FFF0194F is SKIPPED (EDI=1 from caller). + * + * FFF0194F (cold boot path, 630 bytes) sends the standard DDR2 + * JEDEC MRS sequence per rank with computed timing parameters. + * It uses a ROM table at FFF03B98 containing 8 pointers to + * 16-bit DRB entries for rank addressing - identical to our + * get_rank_addr() which reads the same DRB registers. + * + * Our jedec_init_ddr2() is equivalent to FFF0194F: it sends + * the full MRS sequence (NOP -> ABP -> EMRS2 -> EMRS3 -> + * EMRS1(ODT) -> MRS(DLL reset) -> ABP -> CBRx2 -> MRS(normal) -> + * EMRS1(OCD cal) -> EMRS1(exit)) per populated rank using + * SPD-derived timing parameters. + */ + printk(BIOS_DEBUG, "%s: POST 33 - jedec_init_ddr2\n", __func__); + if (!si->s3_resume) + jedec_init_ddr2(si); + + printk(BIOS_DEBUG, "%s: POST 34 - post_jedec_sequence\n", __func__); + post_jedec_sequence(si); + + printk(BIOS_DEBUG, "%s: POST 35 - program_memory_map\n", __func__); + program_memory_map(si, igd_compute_ggc()); + + printk(BIOS_DEBUG, "%s: POST 36 - final_timing_adjust\n", __func__); + final_timing_adjust(si); + + printk(BIOS_DEBUG, "%s: POST 37 - dram_optimizations\n", __func__); + dram_optimizations(si); + + printk(BIOS_DEBUG, "%s: POST 38 - DCC final\n", __func__); + mchbar_setbits32(DCC_MCHBAR, 0xf8000); + + printk(BIOS_DEBUG, "%s: POST 39 - receive_enable_training " + "(fast_boot=%d)\n", __func__, fast_boot); + if (fast_boot) { + raminit_program_training(si); + } else { + receive_enable_training(si); + } + printk(BIOS_DEBUG, "%s: POST 39 done\n", __func__); + + /* + * POST 0xFF40: RCOMP lock and clock restore. + * + * Vendor BIOS (FFFF5115, FFFF5377): + * 1. If stepping != A0: set RCOMP_CTRL bit 1 (RCOMP_LOCK). + * 2. Clear MCHBAR[0x1444] bit 12 (disable RCOMP engine clock). + * This is the reverse of the enable done at the start of ff23. + * Vendor trace: [0x1444] <= 0x00000115 (bit 12 cleared). + */ + if (northbridge_stepping() != 0x00) + mchbar_setbits8(RCOMP_CTRL, 2); + mchbar_clrbits32(IO_RCOMP_CLK_EN, 1 << 12); + + /* + * POST 0xFF41: EPD address decode and channel population. + * + * The RAMINIT copy at FFF0xxxx (the BIOS's actual execution + * path, 55 functions) programs the EPD register region + * (MCHBAR 0x0A00-0x0AA0) between POST 0xFF41 and 0xFF42. + * The RAMINIT3 copy at FFFF3xxx (29 functions) that the rest + * of this file was originally based on omits these entirely. + * + * Without EPD programming, the memory controller does not + * know how to decode addresses for channel 1. + * + * BIOS flow (FFF01F8A-FFF01FDE): + * 1. RCOMP lock (done above at POST 0xFF40) + * 2. IO_RCOMP_CLK_EN clear (done above) + * 3. If EPD+0x2E capability set: + * a. program_epd() - FFF02A7A (1603 bytes) + * 4. program_channel_population() - FFF03286 (112 bytes) + */ + /* + * EPD gating: match vendor boot-state detection (FFF0287C). + * + * The vendor reads EPD_2E[4:0] at raminit entry and caches + * it in sysinfo[0x30]. On the very first cold boot (power-on), + * EPD_2E is 0 (hardware default - never programmed). The + * vendor uses this to SKIP both program_epd() and + * program_channel_population() on the first cold boot. + * + * Memory still works because the primary DRB/DRA/DCC registers + * are sufficient for basic rank addressing. EPD provides a + * secondary scheduling/decode path that the MC latches from its + * registers; programming it with even slightly wrong values can + * actively break rank addressing that works with HW defaults. + * + * On subsequent boots (warm reset, S3 resume), EPD_2E + * retains its value from the prior successful boot, so + * sysinfo[0x30] != 0 and both EPD functions run. + * + * Vendor sequence (FFF01D4F at POST 0xFF41): + * if (sysinfo[0x30] != 0): + * if (cold_boot): program_epd() + * program_channel_population() + */ + { + uint8_t epd_state = mchbar_read8(EPD_2E) & 0x1f; + + printk(BIOS_DEBUG, "%s: POST 41 - EPD_2E=0x%02x\n", + __func__, epd_state); + + if (epd_state != 0) { + printk(BIOS_DEBUG, "%s: EPD address decode " + "(prior init detected)\n", __func__); + if (!si->s3_resume) + program_epd(si); + program_channel_population(si); + + /* + * DCC2 fixup: read EPD_2E[4:0] and write to DCC2. + * + * Vendor (FFF028B6/FFF01378): DCC2 stores a channel + * address decode value derived from EPD_2E[4:0]. + * These bits are latched by the MC hardware after + * the EPD DRB copies are programmed. + * + * Inteltool confirms: EPD_2E = 0x10, DCC2 = 0x10 + * (ch0 rank0 boundary in 32MB units for 1GB DR DIMM). + */ + uint8_t dcc2_val = mchbar_read8(EPD_2E) & 0x1f; + mchbar_write16(DCC2_MCHBAR, dcc2_val); + printk(BIOS_DEBUG, "%s: DCC2 = 0x%02x\n", + __func__, dcc2_val); + } else { + printk(BIOS_DEBUG, "%s: EPD skipped " + "(first cold boot - HW defaults)\n", __func__); + } + } + + /* + * POST 0xFF42: Clear GEN_PMCON_2 DRAM_INIT bit + * + * Vendor BIOS (FFFF5115, FFFF53A4): GEN_PMCON_2 &= 0x7F + * Clears "DRAM init in progress" - signals raminit completed + * successfully. Matches the set in init_pmcon() at entry. + */ + pci_and_config8(D31F0, D31F0_GEN_PMCON_2, (u8)~GEN_PMCON_2_DRAM_INIT); + + /* + * POST 0xFF43: DRAM power management, thermal init, final cleanup + * BIOS: FFF0255E (RAMINIT) / FFFF53D9 (RAMINIT3) + */ + printk(BIOS_DEBUG, "%s: POST 43 - dram_power_mgmt\n", __func__); + dram_power_mgmt(); + printk(BIOS_DEBUG, "%s: thermal_init\n", __func__); + gm965_thermal_init(si); + + /* + * final_cleanup() is NOT called here. + * + * The RAMINIT copy (FFF02838) has zero callers in the vendor + * BIOS image - confirmed dead code. The MCHBAR dump confirms: + * vendor has 0x0ffc=0x01000000 (bit 23 clear) and no IOSCHED + * registers (0x1120-112c, 0x11b0) programmed. Calling + * final_cleanup() sets bit 23 of 0x0ffc and writes IOSCHED + * values that the vendor never writes from the RAMINIT path. + */ + + mchbar_write32(SSKPD_MCHBAR, 0xCAFE); + + /* Expose fast_boot to romstage so it can stash MRC data after cbmem_recovery() */ + si->fast_boot = fast_boot; + + printk(BIOS_DEBUG, "%s: complete\n", __func__); +} + +/* + * raminit_stash_mrc_cache() - Build MRC cache struct and stash to CBMEM. + * + * Must be called after cbmem_recovery() so CBMEM is available. + * Only called on cold boot (!si->fast_boot) - on fast boot the cache + * is already valid and there's nothing new to save. + */ +void raminit_stash_mrc_cache(const sysinfo_t *si) +{ + struct gm965_mrc_cache cache; + + memset(&cache, 0, sizeof(cache)); + + cache.cpu_id = cpu_get_cpuid(); + + /* Store SPD unique CRCs for cache validation on next boot */ + for (int slot = 0; slot < 4; slot++) { + if (si->dimms[slot].present) + cache.spd_crc[slot] = spd_read_unique_crc(si->spd_addr_map[slot]); + } + + memcpy(cache.dimms, si->dimms, sizeof(cache.dimms)); + memcpy(&cache.timings, &si->timings, sizeof(cache.timings)); + memcpy(cache.rec_coarse, si->rec_coarse, sizeof(cache.rec_coarse)); + memcpy(cache.rec_coarse_low, si->rec_coarse_low, sizeof(cache.rec_coarse_low)); + memcpy(cache.rec_fine, si->rec_fine, sizeof(cache.rec_fine)); + memcpy(cache.raw_spd, si->raw_spd, sizeof(cache.raw_spd)); + + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &cache, sizeof(cache)); + + printk(BIOS_DEBUG, "GM965 MRC cache stashed (%zu bytes)\n", sizeof(cache)); +} diff --git a/src/northbridge/intel/gm965/raminit_meminfo.c b/src/northbridge/intel/gm965/raminit_meminfo.c new file mode 100644 index 00000000000..2cb1fcc7035 --- /dev/null +++ b/src/northbridge/intel/gm965/raminit_meminfo.c @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) - SMBIOS memory information setup + * + * Populates CBMEM memory_info structure for SMBIOS Type 16 and Type 17 + * based on the DIMM configuration discovered during raminit. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static u16 get_mem_clock_mt(mem_clock_t mc) +{ + switch (mc) { + case MEM_CLOCK_533MT: return 533; + case MEM_CLOCK_667MT: return 667; + default: return 0; + } +} + +/* Extract SPD identification fields (IDs, part number, voltage) from cached raw SPD */ +static void ddr2_extract_ids(const sysinfo_t *si, struct dimm_info *dimm, int slot) +{ + const u8 *spd = si->raw_spd[slot]; + if (!spd[0]) /* zeroed means no DIMM */ + return; + + /* Serial number (SPD bytes 95-98) */ + for (int i = 0; i < 4; i++) { + dimm->serial[i] = spd[SPD_ASSEMBLY_SERIAL_NUMBER + i]; + } + + /* Part number (SPD bytes 73-88) - 16 ASCII bytes, null-terminated */ + char part[17]; + for (int i = 0; i < 16; i++) { + part[i] = spd[SPD_MANUFACTURER_PART_NUMBER + i]; + } + part[16] = '\0'; + strncpy((char *)dimm->module_part_number, part, DIMM_INFO_PART_NUMBER_SIZE); + dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; + + /* Manufacturer ID from SPD bytes 64-65 (little-endian 16-bit) */ + dimm->mod_id = (u16)spd[64] | ((u16)spd[65] << 8); + + /* Module type from SPD byte 20 */ + dimm->mod_type = spd[20] & SPD_DDR2_DIMM_TYPE_MASK; + + /* DDR2 operates at 1.8V; just set the standard voltage */ + if (spd[8] != 5) + printk(BIOS_WARNING, "DIMM%d SPD voltage byte (0x%02x) doesn't indicate 1.8V\n", + slot, spd[8]); + dimm->vdd_voltage = 1800; + dimm->vdd_min_voltage = 1800; + dimm->vdd_max_voltage = 1800; +} + +/* Fill CBMEM memory_info for SMBIOS Type 16/17 */ +void setup_sdram_meminfo(const sysinfo_t *si) +{ + struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (!mem_info) { + printk(BIOS_ERR, "Failed to allocate memory info CBMEM\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* System-level memory array information */ + mem_info->ecc_type = MEMORY_ARRAY_ECC_NONE; + mem_info->max_capacity_mib = 4096; /* GM965 max = 4 GB */ + mem_info->number_of_devices = 2; /* Two DIMM slots */ + + const u16 ddr_freq_mt = get_mem_clock_mt(si->timings.mem_clock); + + int dimm_cnt = 0; + + for (int slot = 0; slot < 4; slot++) { + if (!si->dimms[slot].present) + continue; + + struct dimm_info *dimm = &mem_info->dimm[dimm_cnt]; + const int ch = slot / 2; + const int ranks = si->dimms[slot].dual_rank ? 2 : 1; + + /* Capacity from SPD (size of one rank * number of ranks) */ + dimm->dimm_size = si->dimms[slot].rank_capacity_mb * ranks; + + dimm->ddr_type = MEMORY_TYPE_DDR2; + dimm->ddr_frequency = ddr_freq_mt; /* deprecated but set */ + dimm->configured_speed_mts = ddr_freq_mt; + dimm->max_speed_mts = 0; /* Unknown */ + dimm->rank_per_dimm = ranks; + dimm->channel_num = ch; + dimm->dimm_num = slot % 2; + dimm->bank_locator = ch; + + /* GM965 only supports 64-bit non-ECC modules */ + dimm->bus_width = MEMORY_BUS_WIDTH_64; + + /* Extract identification fields from cached raw SPD */ + ddr2_extract_ids(si, dimm, slot); + + /* DDR2 SO-DIMMs are unbuffered and synchronous */ + dimm->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS + | MEMORY_TYPE_DETAIL_UNBUFFERED; + + dimm_cnt++; + } + + mem_info->dimm_cnt = dimm_cnt; + + printk(BIOS_DEBUG, "SMBIOS memory info: %d DIMMs, max capacity %d MB\n", + dimm_cnt, mem_info->max_capacity_mib); +} diff --git a/src/northbridge/intel/gm965/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm965/raminit_receive_enable_calibration.c new file mode 100644 index 00000000000..1f16f24d3b4 --- /dev/null +++ b/src/northbridge/intel/gm965/raminit_receive_enable_calibration.c @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - Receive-Enable Calibration + * + * Receive-enable training adjusts the DQS capture timing for each + * channel to find the optimal DQS sampling point. + * + * BIOS uses a 2-level coarse delay (coarse_high * 4 + coarse_low = 0..63) + * plus a 15-step fine delay (0..14) per combined coarse unit. A DQS level + * test function checks bit 30 of the DQS readback register via actual + * memory reads. + * + * Algorithm (3-phase per channel): + * Phase 1 - Coarse sweep up: while DQS is HIGH, increment combined + * coarse by 1. Finds the DQS falling edge. + * Phase 2 - Fine sweep: step coarse +1, check if DQS went HIGH (back + * off if so), then sweep fine 0->14 (wrapping to next coarse + * on overflow) using test_dqs_level(LOW) until DQS rises. + * Phase 3 - Coarse sweep down: subtract 3, then sweep down by 4 + * combined coarse per step using test_dqs_level(HIGH) until DQS falls. + * Final: add 1 combined coarse (center of window). + * + * BIOS functions (RAMINIT copy - actual execution path): + * FFF00EC9 - orchestrator (POST 0xFF39) + * FFF00DA9 - per-channel training + * FFF00D5C - Phase 1: coarse_sweep_up (-> FFF00B1F) + * FFF00CB2 - Phase 2: fine_sweep (-> FFF00B1F + FFF00B77) + * FFF00C67 - Phase 3: coarse_sweep_down (-> FFF00B1F) + * FFF00C11 - program_rec_timing (with MMIO read-back flush) + * FFF00BF0 - coarse_add + * FFF00BCF - coarse_sub + * FFF00B1F - test_dqs_level(HIGH): RW ptr toggle + memory read + bit 30 HIGH + * FFF00B77 - test_dqs_level(LOW): RW ptr toggle + memory read + bit 30 LOW + * + * Both RAMINIT and RAMINIT3 copies have identical training logic. + * Both DQS level test variants (FFF00B1F and FFF00B77) read from rank_addr + * via [ESP+0xc]. Ghidra's decompiler missed the 2nd parameter in + * FFF00B1F because it uses ESP-relative addressing, not EBP-relative. + * + * Key difference from RAMINIT3: RAMINIT copy does MMIO read-back + * flushes after every register write in program_rec_timing (FFF00C11). + * Both copies use identical post-training cleanup (SET then CLEAR + * of CxDRC1 bit 6, RW_PTR sequencing). + */ + +#include +#include +#include +#include +#include + +/* + * Timing state for receive-enable training. + * BIOS: 4-byte stack-local struct at [ebp-4..ebp-1]. + * combined coarse = coarse_high * 4 + coarse_low (0..63) + * fine = 0..14 (15 steps per combined coarse unit) + */ +typedef struct { + uint8_t coarse_high; /* Main coarse delay, 0-15 -> CxDRT3[10:7] */ + uint8_t coarse_low; /* Sub-coarse delay, 0-3 -> REC_COARSE_LOW[3:2] */ + uint8_t fine; /* Fine delay, 0-14 -> CxTRAIN_CFG[7:4] */ + uint8_t config; /* Fixed = 4 */ +} rec_timing_t; + +static void coarse_add(rec_timing_t *t, int step) +{ + int combined = t->coarse_high * 4 + t->coarse_low + step; + t->coarse_high = (uint8_t)(combined >> 2); + t->coarse_low = (uint8_t)(combined & 3); +} + +/* + * coarse_sub() - Subtract step from combined coarse delay + * BIOS: FFFF3A6F (33 bytes) + */ +static void coarse_sub(rec_timing_t *t, int step) +{ + int combined = t->coarse_high * 4 + t->coarse_low - step; + t->coarse_high = (uint8_t)(combined >> 2); + t->coarse_low = (uint8_t)(combined & 3); +} + +/* + * program_rec_timing() - Write coarse_high and coarse_low to MCHBAR + * BIOS: FFFF3AB1 (86 bytes) + * + * coarse_high -> CxDRT3 (MCHBAR+0x121C+ch*0x100) bits [10:7] + * coarse_low -> REC_COARSE_LOW (MCHBAR+0x14B0+ch*0x100) bits [3:2] + */ +static void program_rec_timing(int ch, const rec_timing_t *t) +{ + /* Write coarse_high to CxDRT3 bits [10:7] (32-bit RMW) */ + uint32_t drt3 = mchbar_read32(CxDRT3_MCHBAR(ch)); + drt3 = (drt3 & ~(0x0fU << 7)) | ((uint32_t)(t->coarse_high & 0x0f) << 7); + mchbar_write32(CxDRT3_MCHBAR(ch), drt3); + /* TODO: Is this read-back necessary? The registers are in the MCH, + * not across PCIe/DMI, so posted-write flush should not be needed. */ + (void)mchbar_read32(CxDRT3_MCHBAR(ch)); + + /* Write coarse_low to REC_COARSE_LOW bits [3:2] (8-bit RMW) */ + uint8_t reg = mchbar_read8(REC_COARSE_LOW(ch)); + reg = (reg & 0xf3) | ((t->coarse_low & 0x03) << 2); + mchbar_write8(REC_COARSE_LOW(ch), reg); + (void)mchbar_read32(REC_COARSE_LOW(ch)); /* TODO: same as above */ +} + +/* + * write_fine_delay() - Write fine timing to CxTRAIN_CFG + * BIOS: inline in fine_sweep at FFFF3BC5 + * + * fine -> CxTRAIN_CFG (MCHBAR+0x1484+ch*0x100) bits [7:4] + */ +static void write_fine_delay(int ch, uint8_t fine) +{ + uint8_t reg = mchbar_read8(CxTRAIN_CFG(ch)); + reg = (reg & 0x0f) | (fine << 4); + mchbar_write8(CxTRAIN_CFG(ch), reg); +} + +/* + * test_dqs_level() - Test if DQS is consistently at the expected level + * + * BIOS: FFF00B1F / FFFF39BF (expect HIGH), FFF00B77 / FFFF3A17 (expect LOW) + * Both are 88 bytes each with identical logic, differing only in the + * polarity of the bit 30 check. + * + * Both RAMINIT and RAMINIT3 copies do the same thing: + * 1. Toggle RW pointers (clear then set bit 9) on both channels + * 2. Read from rank_addr to trigger DQS strobe + * 3. I/O delay (IN AL, 0x61) + * 4. Check bit 30 of REC_DQS_LEVEL + * + * Note: The Ghidra decompiler showed FFF00B1F as having only one + * parameter because both params use ESP-relative addressing. The + * raw disassembly confirms [ESP+0xc] = rank_addr IS dereferenced. + * + * @expect_high: 1 to test for DQS HIGH, 0 to test for DQS LOW. + * Returns 1 if DQS matched the expected level in all 3 samples. + */ +static bool test_dqs_level(int ch, uintptr_t rank_addr, bool expect_high) +{ + int pass = true; + int i; + + for (i = 0; i < 3; i++) { + /* Reset RW pointers: clear bit 9, then set bit 9 - both channels */ + mchbar_clrbits16(RW_PTR_CTRL(0), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(0), 1 << 9); + mchbar_clrbits16(RW_PTR_CTRL(1), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(1), 1 << 9); + + /* Trigger memory read - generates DQS strobe */ + read32((volatile void *)(uintptr_t)rank_addr); + + /* I/O delay for DQS capture latching */ + inb(0x61); + + /* Check DQS level: bit 30 of readback register */ + bool high = !!(mchbar_read32(REC_DQS_LEVEL(ch)) & (1 << 30)); + if (high != expect_high) + pass = false; + } + + return pass; +} + +/* + * IO_INIT_CFG2 training byte table (BIOS file offset 0x175900). + * Indexed by mem_clock. Written to bits [27:23] during training setup. + */ +static const uint8_t io_init_cfg2_training[] = { + [0] = 0x05, + [MEM_CLOCK_533MT] = 0x07, + [MEM_CLOCK_667MT] = 0x09, +}; + +/* + * coarse_sweep_up() - Phase 1: Find falling edge of DQS + * BIOS: FFF00D5C -> FFF00B1F (test_dqs_level HIGH with memory read) + * + * Sweeps combined coarse upward by 1 per iteration. + * Loops while DQS is HIGH, stops when DQS falls. + * Returns 1 on success, -1 on overflow. + */ +static int coarse_sweep_up(int ch, rec_timing_t *t, uintptr_t rank_addr) +{ + /* Test at current timing first */ + if (!test_dqs_level(ch, rank_addr, true)) + return 1; /* Already not HIGH - done */ + + /* Increment combined coarse until DQS falls */ + do { + coarse_add(t, 1); + if (t->coarse_high > 0x0f) + return -1; /* Overflow */ + program_rec_timing(ch, t); + + if (!test_dqs_level(ch, rank_addr, true)) + return 1; /* Found transition */ + } while (1); +} + +/* + * fine_sweep() - Phase 2: Find precise LOW->HIGH DQS edge + * BIOS: FFF00CB2 -> FFF00B1F (test_dqs_level HIGH) + FFF00B77 (test_dqs_level LOW) + * + * 1. Steps combined coarse forward by 1 + * 2. Tests if DQS went HIGH - if so, backs off by 1 (overshot) + * 3. Sweeps fine delay 0->14, wrapping to next combined coarse on overflow + * 4. Uses test_dqs_level(LOW) - loops while DQS is LOW + * 5. Stops when DQS transitions to NOT-LOW (rising edge) + */ +static int fine_sweep(int ch, rec_timing_t *t, uintptr_t rank_addr) +{ + /* Step 1: increment combined coarse by 1 */ + coarse_add(t, 1); + if (t->coarse_high > 0x0f) + return -1; + + program_rec_timing(ch, t); + + /* Step 2: check if DQS went HIGH - if so, back off */ + if (test_dqs_level(ch, rank_addr, true)) { + coarse_sub(t, 1); + program_rec_timing(ch, t); + } + + /* Step 3: fine sweep - loop while DQS is LOW */ + while (test_dqs_level(ch, rank_addr, false)) { + t->fine++; + if (t->fine > 0x0e) { + /* Fine overflow: wrap to 0, increment combined coarse */ + t->fine = 0; + coarse_add(t, 1); + if (t->coarse_high > 0x0f) + return -1; + program_rec_timing(ch, t); + } + /* Write fine delay to CxTRAIN_CFG[7:4] */ + write_fine_delay(ch, t->fine); + } + + return 1; +} + +/* + * coarse_sweep_down() - Phase 3: Find lower window boundary + * BIOS: FFF00C67 -> FFF00B1F (test_dqs_level HIGH with memory read) + * + * Sweeps combined coarse downward by 4 per iteration (= 1 coarse_high unit). + * Loops while DQS is HIGH, stops when DQS falls. + * Returns 1 on success, -1 on underflow. + */ +static int coarse_sweep_down(int ch, rec_timing_t *t, uintptr_t rank_addr) +{ + /* Test at current timing first */ + if (!test_dqs_level(ch, rank_addr, true)) + return 1; /* Already not HIGH - done */ + + do { + if (t->coarse_high == 0) + return -1; /* Underflow */ + coarse_sub(t, 4); + program_rec_timing(ch, t); + + if (!test_dqs_level(ch, rank_addr, true)) + return 1; /* Found lower edge */ + } while (1); +} + +/* + * per_channel_rec_training() - Run 3-phase REC training for one channel + * BIOS: FFFF4E70 (301 bytes) + * + * Computes rank_addr for memory test reads: + * Channel 0: address 0 + * Channel 1 + dual-channel: address 0x40 (next cache line in interleave) + * Channel 1 + single-channel: MCHBAR16(0x1206) << 25 (ch0 boundary) + * + * Initializes timing struct, runs 3 phases, writes final CxDRT5. + */ +static void per_channel_rec_training(int ch, sysinfo_t *si) +{ + rec_timing_t t; + + /* + * BIOS: initial coarse_high = sysinfo[0x22] + 4. + * Vendor stores CAS as index (CAS_actual - 3) at sysinfo[0x22], + * so initial = (CAS - 3) + 4 = CAS + 1. + * Verified at FFFF4E7E: movzx edx, byte [eax+0x22] ; add dl, 4 + */ + t.coarse_high = si->timings.CAS + 1; + t.coarse_low = 0; + t.fine = 0; + t.config = 4; + + /* + * Compute rank address for memory test reads. + * BIOS: FFFF4E83-FFFF4EB4 + * ch0: rank_addr = 0 + * ch1 + dual-channel: rank_addr = 0x40 + * ch1 + single-channel: rank_addr = MCHBAR16(0x1206) << 25 + */ + uintptr_t rank_addr = 0; + if (ch == 1) { + if (si->timings.channel_mode != CHANNEL_MODE_SINGLE) { + rank_addr = 0x40; + } else { + rank_addr = (uint32_t)mchbar_read16(0x1206) << 25; + } + } + + /* + * Arm per-channel training comparator. + * CxTRAIN_CFG: set bit 3, preserve only bit 0, clear rest. + * BIOS: (val & 0x01) | 0x08 + */ + mchbar_clrsetbits8(CxTRAIN_CFG(ch), 0xfe, 1 << 3); + + /* Program initial coarse timing */ + program_rec_timing(ch, &t); + + /* + * Phase 1: Coarse sweep up - find DQS falling edge + * BIOS: FFF00D5C -> FFF00B1F (test_dqs_level HIGH) + */ + if (coarse_sweep_up(ch, &t, rank_addr) != 1) + die_with_post_code(POSTCODE_RAM_FAILURE, "REC: coarse sweep up failed"); + + /* + * Phase 2: Fine sweep - find precise LOW->HIGH edge + * BIOS: FFF00CB2 -> FFF00B1F (overshoot) + FFF00B77 (fine) + */ + if (fine_sweep(ch, &t, rank_addr) != 1) + die_with_post_code(POSTCODE_RAM_FAILURE, "REC: fine sweep failed"); + + /* + * Phase 3: Coarse sweep down - find lower window boundary + * BIOS: FFF00C67 -> FFF00B1F (test_dqs_level HIGH) + */ + coarse_sub(&t, 3); + program_rec_timing(ch, &t); + + if (coarse_sweep_down(ch, &t, rank_addr) != 1) + die_with_post_code(POSTCODE_RAM_FAILURE, "REC: coarse sweep down failed"); + + /* + * Final: add 1 to combined coarse (center of window). + * Verify coarse_high <= 15, then write registers. + */ + coarse_add(&t, 1); + if (t.coarse_high > 0x0f) + die_with_post_code(POSTCODE_RAM_FAILURE, "REC: final bounds exceeded"); + + program_rec_timing(ch, &t); + + /* Store results for CMOS cache / S3 resume restore */ + si->rec_coarse[ch] = t.coarse_high; + si->rec_coarse_low[ch] = t.coarse_low; + si->rec_fine[ch] = t.fine; + + /* + * Write final value to CxDRT5 bits [7:4] = (coarse_high - 1). + * BIOS: 8-bit RMW at MCHBAR+0x1224+ch*0x100. + */ + uint8_t drt5 = mchbar_read8(CxDRT5_MCHBAR(ch)); + drt5 = (drt5 & 0x0f) | (((t.coarse_high - 1) & 0x0f) << 4); + mchbar_write8(CxDRT5_MCHBAR(ch), drt5); + + printk(BIOS_DEBUG, "REC ch%d: coarse_high=%d coarse_low=%d fine=%d " + "DRT3=0x%08x DRT5=0x%02x\n", + ch, t.coarse_high, t.coarse_low, t.fine, + mchbar_read32(CxDRT3_MCHBAR(ch)), + mchbar_read8(CxDRT5_MCHBAR(ch))); +} + +/* + * raminit_program_training() - Write cached training results to hardware. + * + * Called on warm boot / S3 resume instead of receive_enable_training(). + * Programs the same registers that per_channel_rec_training() would, + * then runs the same post-training cleanup sequence. + */ +void raminit_program_training(sysinfo_t *si) +{ + int ch; + + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + if (!(slot < 4 && si->dimms[slot].present)) + continue; + + rec_timing_t t; + t.coarse_high = si->rec_coarse[ch]; + t.coarse_low = si->rec_coarse_low[ch]; + t.fine = si->rec_fine[ch]; + t.config = 4; + + /* Program coarse timing to CxDRT3 + REC_COARSE_LOW */ + program_rec_timing(ch, &t); + + /* Program fine delay to CxTRAIN_CFG */ + write_fine_delay(ch, t.fine); + + /* Write CxDRT5 bits [7:4] = coarse_high - 1 */ + uint8_t drt5 = mchbar_read8(CxDRT5_MCHBAR(ch)); + drt5 = (drt5 & 0x0f) | (((t.coarse_high - 1) & 0x0f) << 4); + mchbar_write8(CxDRT5_MCHBAR(ch), drt5); + } + + /* Post-training cleanup - matches vendor FFFF4F9D */ + mchbar_setbits16(RW_PTR_CTRL(0), 0x0c00); + mchbar_setbits16(RW_PTR_CTRL(1), 0x0c00); + mchbar_clrbits32(TRAIN_ENABLE(0), TRAIN_ENABLE_BIT); + mchbar_clrbits32(TRAIN_ENABLE(1), TRAIN_ENABLE_BIT); + mchbar_setbits8(CxDRC1_MCHBAR(0), 0x40); + mchbar_setbits8(CxDRC1_MCHBAR(1), 0x40); + mchbar_clrbits8(CxDRC1_MCHBAR(0), 0x40); + mchbar_clrbits8(CxDRC1_MCHBAR(1), 0x40); + mchbar_clrbits16(RW_PTR_CTRL(0), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(0), 0x0600); + mchbar_clrbits16(RW_PTR_CTRL(1), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(1), 0x0600); +} + +/* + * receive_enable_training() - Run 3-phase REC training for all channels + * BIOS: FFFF4F9D (orchestrator, 283 bytes) + * + * Pre-training setup: + * 1. Enable training mode (TRAIN_ENABLE bit 31) + * 2. Program IO_INIT_CFG2 bits [27:23] from freq-dependent table + * 3. Clear RW_PTR_CTRL bits [11:10] (16-bit AND 0xF3FF) + * 4. Clear DCC bit 15 (16-bit AND 0x7FFF) + * + * Post-training cleanup (verified 12-step sequence): + * 1-2. Set RW_PTR_CTRL bits [11:10] on both channels + * 3-4. Clear TRAIN_ENABLE bit 31 on both channels + * 5-8. Toggle CxDRC1 bit 6 (set then clear) on both channels + * 9-12. Clear bit 9, then set bits [10:9] of RW_PTR_CTRL + */ +void receive_enable_training(sysinfo_t *si) +{ + int ch; + + /* === Pre-training setup === */ + + /* Enable training mode on both channels */ + mchbar_setbits32(TRAIN_ENABLE(0), TRAIN_ENABLE_BIT); + mchbar_setbits32(TRAIN_ENABLE(1), TRAIN_ENABLE_BIT); + + /* + * Write frequency-dependent value to IO_INIT_CFG2 bits [27:23]. + * BIOS: RMW with mask 0xF07FFFFF, shift << 23. + */ + mchbar_clrsetbits32(IO_INIT_CFG2, + 0x0f800000, /* clear bits [27:23] */ + (uint32_t)io_init_cfg2_training[si->timings.mem_clock] << 23); + + /* Clear RW_PTR_CTRL bits [11:10] - 16-bit AND 0xF3FF */ + mchbar_clrbits16(RW_PTR_CTRL(0), 0x0c00); + mchbar_clrbits16(RW_PTR_CTRL(1), 0x0c00); + + /* Clear DCC bit 15 - 16-bit AND 0x7FFF */ + mchbar_clrbits16(DCC_MCHBAR, 0x8000); + + /* === Per-channel training === */ + + for (ch = 0; ch < 2; ch++) { + int slot = ch * 2; + if (!(slot < 4 && si->dimms[slot].present)) + continue; + per_channel_rec_training(ch, si); + } + + /* + * Post-training cleanup - vendor RAMINIT FFF00E99 (confirmed + * from disassembly at fff00f19-fff00fbc, identical 12-step + * sequence to RAMINIT3 FFFF4F9D). + * + * Order: RW_PTR set bits -> training disable -> CxDRC1 toggle -> + * final RW_PTR clear-bit9/set-bits. + */ + + /* 1-2: Set RW_PTR_CTRL bits [11:10] */ + mchbar_setbits16(RW_PTR_CTRL(0), 0x0c00); + mchbar_setbits16(RW_PTR_CTRL(1), 0x0c00); + + /* 3-4: Disable training mode */ + mchbar_clrbits32(TRAIN_ENABLE(0), TRAIN_ENABLE_BIT); + mchbar_clrbits32(TRAIN_ENABLE(1), TRAIN_ENABLE_BIT); + + /* 5-8: Toggle CxDRC1 bit 6 - SET then CLEAR */ + mchbar_setbits8(CxDRC1_MCHBAR(0), 0x40); + mchbar_setbits8(CxDRC1_MCHBAR(1), 0x40); + mchbar_clrbits8(CxDRC1_MCHBAR(0), 0x40); + mchbar_clrbits8(CxDRC1_MCHBAR(1), 0x40); + + /* 9-12: RW_PTR_CTRL - clear bit 9, then set bits [10:9] */ + mchbar_clrbits16(RW_PTR_CTRL(0), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(0), 0x0600); + mchbar_clrbits16(RW_PTR_CTRL(1), 1 << 9); + mchbar_setbits16(RW_PTR_CTRL(1), 0x0600); +} diff --git a/src/northbridge/intel/gm965/romstage.c b/src/northbridge/intel/gm965/romstage.c new file mode 100644 index 00000000000..176536b0214 --- /dev/null +++ b/src/northbridge/intel/gm965/romstage.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - Romstage Entry Point + * + * Modeled on coreboot GM45 romstage.c, adapted for GM965 + ICH8-M. + * Orchestrates early initialization, RAM init, DMI/PCIe link setup, + * and handoff to ramstage. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +#define GM965_RAM_DEBUG 0 + +/* + * Default SPD address map: one DIMM per channel, standard SA[2:0] strapping. + * Slot 0 = channel 0 DIMM 0, slot 2 = channel 1 DIMM 0. + * Boards with a non-standard wiring override this in their early_init.c. + */ +void __weak mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x00; + spd_map[2] = 0x51; + spd_map[3] = 0x00; +} + +void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo) +{ +} + +void __weak mb_post_raminit_setup(void) +{ +} + +void __weak mainboard_late_rcba_config(void) +{ +} + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(void) +{ + sysinfo_t sysinfo; + int s3resume; + int cbmem_initted; + + /* Basic northbridge setup */ + gm965_early_init(); + + /* First, run everything needed for console output. */ + enable_smbus(); + + /* ASPM related setting, set early by original BIOS. */ + dmibar_clrbits16(0x204, 3 << 10); + + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + + /* RAM initialization */ + memset(&sysinfo, 0, sizeof(sysinfo)); + + mb_pre_raminit_setup(&sysinfo); + + raminit(&sysinfo); + + /* DMI link init: SB side first, then NB side, then poll. + * Vendor order: ich8m_dmi_setup -> gm965_dmi_init -> ich8m_dmi_poll_vc1 + * The NB side waits for VC1 negotiation which requires SB VC1 enabled. */ + printk(BIOS_DEBUG, "romstage: i82801hx_dmi_setup\n"); + i82801hx_dmi_setup(); + printk(BIOS_DEBUG, "romstage: gm965_dmi_init\n"); + gm965_dmi_init(); + printk(BIOS_DEBUG, "romstage: i82801hx_dmi_poll_vc1\n"); + i82801hx_dmi_poll_vc1(); + /* + * PM init: programs MCH power management registers. + * Vendor BIOS: bioscode_5.rom, called after DMI/PCIe init. + * Without this, the memory controller has no proper power state + * management, causing intermittent data corruption under load. + */ + printk(BIOS_DEBUG, "romstage: gm965_pm_init\n"); + gm965_pm_init(&sysinfo); + + /* + * IGD init: programs HSync/VSync, PM_F10 bit 0, IGD scheduling. + * Vendor BIOS: bioscode_7.rom, called after PM init. + */ + printk(BIOS_DEBUG, "romstage: gm965_igd_init\n"); + gm965_igd_init(&sysinfo); + + printk(BIOS_DEBUG, "romstage: write SSKPD=0xcafe\n"); + mchbar_write16(SSKPD_MCHBAR, 0xcafe); + + if (GM965_RAM_DEBUG) { + /* Full MCHBAR dump - all ranges raminit touches, skip zeros */ + for (uint16_t off = 0; off < 0x2000; off += 4) { + uint32_t val = mchbar_read32(off); + if (val) + printk(BIOS_DEBUG, "MCHBAR 0x%04x: 0x%08x\n", off, val); + } + + /* Memory verification: test each rank to confirm training worked. */ + { + printk(BIOS_DEBUG, "romstage: per-rank memory verification\n"); + /* 8 rank slots: ch0 r0/r1/r2/r3, ch1 r0/r1/r2/r3 */ + static const uint16_t drb_offsets[] = { + 0x1200, 0x1200, 0x1204, 0x1204, /* ch0 */ + 0x1300, 0x1300, 0x1304, 0x1304, /* ch1 */ + }; + uint32_t prev_bnd = 0; + for (int rank = 0; rank < 8; rank++) { + uint32_t reg = mchbar_read32(drb_offsets[rank]); + uint32_t bnd = (rank & 1) + ? (reg >> 16) & 0xff + : reg & 0xff; + if (bnd == 0 || bnd == prev_bnd) { + prev_bnd = bnd; + continue; + } + uint32_t rank_start = prev_bnd << 25; + uint32_t test_addr = rank_start + 1 * MiB; + uint32_t tolud = (pci_read_config16(D0F0, D0F0_TOLUD) + & 0xfff0) << 16; + if (test_addr >= tolud) { + prev_bnd = bnd; + continue; + } + printk(BIOS_DEBUG, " rank %d: test at 0x%08x\n", + rank, test_addr); + ram_check(test_addr); + prev_bnd = bnd; + } + } + } + + printk(BIOS_DEBUG, "romstage: cbmem_top=0x%08x\n", + (unsigned int)cbmem_top()); + + printk(BIOS_DEBUG, "romstage: cbmem_recovery\n"); + cbmem_initted = !cbmem_recovery(s3resume); + printk(BIOS_DEBUG, "romstage: cbmem_initted=%d\n", cbmem_initted); + + if (!sysinfo.fast_boot) + raminit_stash_mrc_cache(&sysinfo); + + setup_sdram_meminfo(&sysinfo); + + mb_post_raminit_setup(); + + southbridge_configure_default_intmap(); + mainboard_late_rcba_config(); + + printk(BIOS_DEBUG, "romstage: handoff s3resume=%d\n", s3resume); + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); +} diff --git a/src/northbridge/intel/gm965/thermal.c b/src/northbridge/intel/gm965/thermal.c new file mode 100644 index 00000000000..3d49df3e442 --- /dev/null +++ b/src/northbridge/intel/gm965/thermal.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel GM965 (Crestline) Northbridge - Thermal Sensor Initialization + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * BIOS functions: + * FFF027F0 (thermal_sensor_init_all) - Iterates DIMMs, POST 0xFF42 + * FFF02709 (thermal_sensor_init_per_dimm) - Per-DIMM TSE2004 config + * FFF02628 (smbus_word_read) - SMBus word read protocol + * FFF0269F (smbus_word_write) - SMBus word write protocol + * FFFF56C6 (raminit3_thermal_init) - RAMINIT3 copy + * FFFF55DF (raminit3_thermal_per_dimm) - RAMINIT3 copy + * + * TSE2004-compatible thermal sensors are present on DDR2 DIMMs at + * SMBus addresses 0x18-0x1B (7-bit) = 0x30-0x36 (8-bit with R/W). + * + * Reference: coreboot GM45 thermal.c + JEDEC TSE2004 spec + */ + +#include +#include +#include +#include + +/* + * smbus_write_word() wrapper - coreboot's smbus_host.h does not provide + * a static inline for smbus_write_word, only do_smbus_write_word. + */ +static inline int smbus_write_word(u8 device, u8 address, u16 data) +{ + uintptr_t base = smbus_base(); + return do_smbus_write_word(base, device, address, data); +} + +/* TSE2004 thermal sensor registers */ +#define TSE2004_CAPABILITY 0x00 +#define TSE2004_CONFIG 0x01 +#define TSE2004_ALARM_HIGH 0x02 +#define TSE2004_ALARM_LOW 0x03 +#define TSE2004_CRITICAL 0x04 +#define TSE2004_TEMPERATURE 0x05 +#define TSE2004_MANUF_ID 0x06 +#define TSE2004_DEVICE_ID 0x07 + +/* TSE2004 SMBus base addresses (7-bit: 0x18-0x1B for 4 DIMM slots) */ +#define TSE2004_SLAVE_BASE 0x18 + +/* + * thermal_sensor_init_dimm() - Configure a single DIMM thermal sensor + * + * Reads the capability register to verify a TSE2004 sensor is present, + * then programs alarm thresholds and enables continuous monitoring. + * + * BIOS function: FFF02709 / FFFF55DF (231 bytes) + * The BIOS sets: + * - Alarm high: +85C (0x0A80) + * - Critical: +100C (0x0C80) + * - Config: continuous conversion, comparator mode + */ +static void thermal_sensor_init_dimm(int slot) +{ + uint8_t slave = TSE2004_SLAVE_BASE + slot; + int cap; + + /* Check if sensor is present by reading capability register */ + cap = smbus_read_word(slave, TSE2004_CAPABILITY); + if (cap < 0) + return; /* No sensor on this DIMM */ + + /* + * Program alarm thresholds. + * TSE2004 temperature format: sign(15), 4-bit integer(14:11), + * 4-bit fraction(10:7), 4 reserved(6:3), 3 flags(2:0) + * + * High alarm = +85C = 0x0A80 + * Critical = +100C = 0x0C80 + * Low alarm = +0C = 0x0000 + */ + smbus_write_word(slave, TSE2004_ALARM_HIGH, 0x0A80); + smbus_write_word(slave, TSE2004_CRITICAL, 0x0C80); + smbus_write_word(slave, TSE2004_ALARM_LOW, 0x0000); + + /* + * Configure sensor: + * Bit 10: EVENT output control = active-low (0) + * Bit 9: Tcrit lock = 0 (not locked) + * Bit 8: window lock = 0 (not locked) + * Bits 6:5: resolution = 11 (0.0625 C, ~250ms conversion) + * Bit 4: interrupt clear = 0 + * Bit 3: alarm window = 0 (comparator mode) + * Bit 2: critical only = 0 + * Bit 1: SHDN = 0 (continuous conversion) + * Bit 0: hyst enable = 0 + * + * Value: 0x0060 (resolution = max, continuous, comparator) + */ + smbus_write_word(slave, TSE2004_CONFIG, 0x0060); +} + +/* + * gm965_thermal_init() - Initialize thermal sensors on all populated DIMMs + * + * BIOS function: FFF027F0 (72 bytes, POST 0xFF42) + * + * The vendor's RAMINIT copy (actual execution path, FFF0xxxx) never + * calls the thermal sensor init - FFF027F0 has zero call sites in + * the entire BIOS image. The RAMINIT3 copy (FFFF3xxx, not executed) + * does call its equivalent at FFFF56C6 from FFFF53C5. + * + * The vendor function only programs TSE2004 DIMM thermal sensors via + * SMBus, plus a single conditional MCHBAR write: THERMAL_ENABLE = 0xD0 + * if any sensor was found. It does NOT write any PM_CH / PM_THRT + * registers - those are programmed exclusively by dram_power_mgmt(). + * + * Previous code had GM45-derived MCHBAR writes (0x1070, 0x1080, + * 0x1001-0x105c, 0x1290/0x12b4, 0x11d0/0x11d4) that destructively + * overwrote the values set by dram_power_mgmt(). Removed to match + * the vendor's RAMINIT copy which never does these writes. + */ +void gm965_thermal_init(sysinfo_t *si) +{ + int slot; + int found = 0; + + /* + * Initialize TSE2004 thermal sensors on each populated DIMM. + * X61 has 2 DIMM slots (1 per channel), mapped to: + * Slot 0 = Ch0 DIMM0 = TSE2004 at SMBus 0x18 + * Slot 1 = Ch1 DIMM0 = TSE2004 at SMBus 0x19 + * + * Vendor FFF027F0 iterates all 4 DIMM slots (7-byte stride + * through the per-DIMM array), calls FFF02709 per present DIMM. + */ + for (slot = 0; slot < 4; slot++) { + if (si->dimms[slot].present) { + thermal_sensor_init_dimm(slot); + found = 1; + } + } + + /* + * Vendor FFF027F0 line 29: if any sensor init succeeded, + * write 0xD0 to THERMAL_ENABLE (MCHBAR + 0x10EF). + * Byte write, conditional on sensor presence. + */ + if (found) + mchbar_write8(THERMAL_ENABLE, 0xd0); +} diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index c57f1ec3809..d67cc14660f 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -4,7 +4,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL select CACHE_MRC_SETTINGS - select INTEL_DDI select INTEL_GMA_ACPI select DRAM_SUPPORT_DDR3 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index bd2f7196548..58c1f5bba8c 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include #include #include +#include #include #include -#include "haswell.h" #include +#include + +#include "haswell.h" static unsigned long acpi_fill_dmar(unsigned long current) { diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 8c0f5422df1..1aa98ae5694 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include @@ -52,23 +50,17 @@ static void ABI_X86 send_to_console(unsigned char b) */ static void sdram_initialize(struct pei_data *pei_data) { - size_t mrc_size; - pei_wrapper_entry_t entry; - int ret; - /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - pei_data->saved_data = - mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, - &mrc_size); + size_t mrc_size; + pei_data->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, &mrc_size); if (pei_data->saved_data) { /* MRC cache found */ pei_data->saved_data_size = mrc_size; } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); + printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POSTCODE_RESUME_FAILURE); system_reset(); } else { @@ -76,7 +68,7 @@ static void sdram_initialize(struct pei_data *pei_data) } /* - * Do not use saved pei data. Can be set by mainboard romstage + * Do not use saved pei data. Can be set by mainboard romstage * to force a full train of memory on every boot. */ if (pei_data->disable_saved_data) { @@ -86,13 +78,13 @@ static void sdram_initialize(struct pei_data *pei_data) } /* We don't care about leaking the mapping */ - entry = cbfs_ro_map("mrc.bin", NULL); + pei_wrapper_entry_t entry = cbfs_ro_map("mrc.bin", NULL); if (entry == NULL) die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); - ret = entry(pei_data); + int ret = entry(pei_data); if (ret < 0) die("pei_data version mismatch\n"); @@ -229,6 +221,7 @@ void perform_raminit(const bool s3resume) const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin; pei_data.usb3_ports[i].enable = mainboard_usb3_ports[i].enable; pei_data.usb3_ports[i].oc_pin = map_to_pei_oc_pin(oc_pin); + pei_data.usb3_ports[i].fixed_eq = mainboard_usb3_ports[i].fixed_eq; } /* Broadwell MRC uses ACPI values for boot_mode */ diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c index 2b244c5a697..01ccbeb19a9 100644 --- a/src/northbridge/intel/haswell/early_pcie.c +++ b/src/northbridge/intel/haswell/early_pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/northbridge/intel/haswell/early_peg.c b/src/northbridge/intel/haswell/early_peg.c index 4b923bb7085..bb59d5d6d2b 100644 --- a/src/northbridge/intel/haswell/early_peg.c +++ b/src/northbridge/intel/haswell/early_peg.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f7fad3183dc..fc44a98a57e 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -1,19 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include -#include -#include #include +#include +#include +#include #include #include +#include #include #include +#include #include #include #include -#include #include #include #include @@ -21,64 +21,6 @@ #include "chip.h" #include "haswell.h" -struct gt_reg { - u32 reg; - u32 andmask; - u32 ormask; -}; - -static const struct gt_reg haswell_gt_setup[] = { - /* Enable Counters */ - { 0x0a248, 0x00000000, 0x00000016 }, - { 0x0a000, 0x00000000, 0x00070020 }, - { 0x0a180, 0xff3fffff, 0x15000000 }, - /* Enable DOP Clock Gating */ - { 0x09424, 0x00000000, 0x000003fd }, - /* Enable Unit Level Clock Gating */ - { 0x09400, 0x00000000, 0x00000080 }, - { 0x09404, 0x00000000, 0x40401000 }, - { 0x09408, 0x00000000, 0x00000000 }, - { 0x0940c, 0x00000000, 0x02000001 }, - { 0x0a008, 0x00000000, 0x08000000 }, - /* Wake Rate Limits */ - { 0x0a090, 0xffffffff, 0x00000000 }, - { 0x0a098, 0xffffffff, 0x03e80000 }, - { 0x0a09c, 0xffffffff, 0x00280000 }, - { 0x0a0a8, 0xffffffff, 0x0001e848 }, - { 0x0a0ac, 0xffffffff, 0x00000019 }, - /* Render/Video/Blitter Idle Max Count */ - { 0x02054, 0x00000000, 0x0000000a }, - { 0x12054, 0x00000000, 0x0000000a }, - { 0x22054, 0x00000000, 0x0000000a }, - /* RC Sleep / RCx Thresholds */ - { 0x0a0b0, 0xffffffff, 0x00000000 }, - { 0x0a0b4, 0xffffffff, 0x000003e8 }, - { 0x0a0b8, 0xffffffff, 0x0000c350 }, - /* RP Settings */ - { 0x0a010, 0xffffffff, 0x000f4240 }, - { 0x0a014, 0xffffffff, 0x12060000 }, - { 0x0a02c, 0xffffffff, 0x0000e808 }, - { 0x0a030, 0xffffffff, 0x0003bd08 }, - { 0x0a068, 0xffffffff, 0x000101d0 }, - { 0x0a06c, 0xffffffff, 0x00055730 }, - { 0x0a070, 0xffffffff, 0x0000000a }, - /* RP Control */ - { 0x0a024, 0x00000000, 0x00000b92 }, - /* HW RC6 Control */ - { 0x0a090, 0x00000000, 0x88040000 }, - /* Video Frequency Request */ - { 0x0a00c, 0x00000000, 0x08000000 }, - { 0 }, -}; - -static const struct gt_reg haswell_gt_lock[] = { - { 0x0a248, 0xffffffff, 0x80000000 }, - { 0x0a004, 0xffffffff, 0x00000010 }, - { 0x0a080, 0xffffffff, 0x00000004 }, - { 0x0a180, 0xffffffff, 0x80000000 }, - { 0 }, -}; - /* * Some VGA option roms are used for several chipsets but they only have one PCI ID in their * header. If we encounter such an option rom, we need to do the mapping ourselves. @@ -89,30 +31,39 @@ u32 map_oprom_vendev(u32 vendev) u32 new_vendev = vendev; switch (vendev) { - case 0x80860402: /* GT1 Desktop */ - case 0x80860406: /* GT1 Mobile */ - case 0x8086040a: /* GT1 Server */ - case 0x80860a06: /* GT1 ULT */ - case 0x80860a0e: /* GT1 ULX */ - - case 0x80860412: /* GT2 Desktop */ - case 0x80860416: /* GT2 Mobile */ - case 0x8086041a: /* GT2 Server */ - case 0x8086041e: /* GT1.5 Desktop */ - case 0x80860a16: /* GT2 ULT */ - case 0x80860a1e: /* GT2 ULX */ - - case 0x80860422: /* GT3 Desktop */ - case 0x80860426: /* GT3 Mobile */ - case 0x8086042a: /* GT3 Server */ - case 0x80860a26: /* GT3 ULT */ - - case 0x80860d22: /* GT3e Desktop */ - case 0x80860d16: /* GT1 Mobile 4+3 */ - case 0x80860d26: /* GT2 Mobile 4+3, GT3e Mobile */ - case 0x80860d36: /* GT3 Mobile 4+3 */ - - new_vendev = 0x80860406; /* GT1 Mobile */ + case 0x80860402: /* HSW GT1 Desktop */ + case 0x80860406: /* HSW GT1 Mobile */ + case 0x8086040a: /* HSW GT1 Server */ + case 0x80860a06: /* HSW GT1 ULT */ + case 0x80860a0e: /* HSW GT1 ULX */ + + case 0x80860412: /* HSW GT2 Desktop */ + case 0x80860416: /* HSW GT2 Mobile */ + case 0x8086041a: /* HSW GT2 Server */ + case 0x8086041e: /* HSW GT1.5 Desktop */ + case 0x80860a16: /* HSW GT2 ULT */ + case 0x80860a1e: /* HSW GT2 ULX */ + + case 0x80860422: /* HSW GT3 Desktop */ + case 0x80860426: /* HSW GT3 Mobile */ + case 0x8086042a: /* HSW GT3 Server */ + case 0x80860a26: /* HSW GT3 ULT */ + + case 0x80860d22: /* HSW GT3e Desktop */ + case 0x80860d16: /* HSW GT1 Mobile 4+3 */ + case 0x80860d26: /* HSW GT2 Mobile 4+3, GT3e Mobile */ + case 0x80860d36: /* HSW GT3 Mobile 4+3 */ + + case 0x80861612: /* BDW Halo GT2 */ + case 0x80861622: /* BDW Halo/Desktop GT3 */ + + case 0x80861606: /* BDW ULT GT1 */ + case 0x80861616: /* BDW ULT GT2 */ + case 0x80861626: /* BDW ULT GT3 15W */ + case 0x8086162b: /* BDW ULT GT3 28W */ + case 0x8086161e: /* BDW ULX GT2 */ + + new_vendev = 0x80860406; /* HSW GT1 Mobile */ break; } @@ -141,14 +92,9 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) gtt_write(reg, val); } -static inline void gtt_write_regs(const struct gt_reg *gt) +static inline void gtt_or(u32 reg, u32 ormask) { - for (; gt && gt->reg; gt++) { - if (gt->andmask) - gtt_rmw(gt->reg, gt->andmask, gt->ormask); - else - gtt_write(gt->reg, gt->ormask); - } + gtt_rmw(reg, ~0ul, ormask); } #define GTT_RETRY 1000 @@ -169,45 +115,88 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -static void power_well_enable(void) +static int gtt_pcode_write(u32 mbox, u32 val) { - gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); - gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); + if (!gtt_poll(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0)) + return 0; + + gtt_write(GEN6_PCODE_DATA, val); + gtt_write(GEN6_PCODE_DATA1, 0); + gtt_write(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); + + return gtt_poll(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0); } -static void gma_pm_init_pre_vbios(struct device *dev) +static void gma_pm_init_haswell(void) { printk(BIOS_DEBUG, "GT Power Management Init\n"); - gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; - - power_well_enable(); - - /* - * Enable RC6 - */ + /* Note: we unconditionally enable Render Standby */ /* Enable Force Wake */ - gtt_write(0x0a180, 1 << 5); - gtt_write(0x0a188, 0x00010001); + gtt_or(0xa180, 1 << 5); + gtt_write(0xa188, 0x00010001); gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0); - /* GT Settings */ - gtt_write_regs(haswell_gt_setup); + /* Enable counters except Power Meter */ + gtt_write(0xa248, 0x00000016); + + /* GFXPAUSE settings (C0 and later) */ + gtt_write(0xa000, 0x00070020); + + /* ECO settings (C0 and later), Render Standby */ + gtt_rmw(0xa180, 0xff3fffff, 0x15000000); + + /* Enable DOP Clock Gating */ + gtt_write(0x9424, 0x000003fd); + + /* Enable Unit Level Clock Gating */ + gtt_write(0x9400, 0x00000080); + gtt_write(0x9404, 0x40401000); + gtt_write(0x9408, 0x00000000); + gtt_write(0x940c, 0x02000001); + + /* Set RP1 graphics frequency */ + gtt_write(0xa008, 0x08000000); + + /* Wake Rate Limits */ + gtt_write(0xa090, 0x00000000); + gtt_write(0xa098, 0x03e80000); + gtt_write(0xa09c, 0x00280000); + gtt_write(0xa0a8, 0x0001e848); + gtt_write(0xa0ac, 0x00000019); - /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + /* Render/Video/Blitter Idle Max Count */ + gtt_write(0x02054, 0x0000000a); + gtt_write(0x12054, 0x0000000a); + gtt_write(0x22054, 0x0000000a); + gtt_write(0x1a054, 0x0000000a); - /* Mailbox Data - RC6 VIDS */ - gtt_write(0x138128, 0x00000000); + /* RC Sleep / RCx Thresholds */ + gtt_write(0xa0b0, 0x00000000); + gtt_write(0xa0b4, 0x000003e8); + gtt_write(0xa0b8, 0x0000c350); + + /* RP Settings */ + gtt_write(0xa010, 0x000f4240); + gtt_write(0xa014, 0x12060000); + gtt_write(0xa02c, 0x0000e808); + gtt_write(0xa030, 0x0003bd08); + gtt_write(0xa068, 0x000101d0); + gtt_write(0xa06c, 0x00055730); + gtt_write(0xa070, 0x0000000a); + + /* RP Control */ + gtt_write(0xa024, 0x00000b92); + + /* HW RC6 Control */ + gtt_write(0xa090, 0x88040000); - /* Mailbox Command */ - gtt_write(0x138124, 0x80000004); + /* Video Frequency Request */ + gtt_write(0xa00c, 0x08000000); - /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + /* Set RC6 VIDs */ + gtt_pcode_write(GEN6_PCODE_WRITE_RC6VIDS, 0); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | @@ -216,30 +205,111 @@ static void gma_pm_init_pre_vbios(struct device *dev) GEN6_PM_RP_DOWN_EI_EXPIRED); /* Enable RC6 in idle */ - gtt_write(0x0a094, 0x00040000); + gtt_write(0xa094, 0x00040000); /* PM Lock Settings */ - gtt_write_regs(haswell_gt_lock); + gtt_or(0xa248, 1ul << 31); + gtt_or(0xa004, 1 << 4); + gtt_or(0xa080, 1 << 2); + gtt_or(0xa180, 1ul << 31); } -static void init_display_planes(void) +static u8 systemagent_revision(void) { - int pipe, plane; + return pci_read_config8(pcidev_on_root(0, 0), PCI_REVISION_ID); +} - /* Disable cursor mode */ - for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) { - gtt_write(CURCNTR_IVB(pipe), CURSOR_MODE_DISABLE); - gtt_write(CURBASE_IVB(pipe), 0x00000000); - } +static void gma_pm_init_broadwell(void) +{ + printk(BIOS_DEBUG, "GT Power Management Init\n"); + + /* Note: we unconditionally enable Render Standby */ + + /* Enable Force Wake */ + gtt_write(0xa188, 0x00010001); + gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0); - /* Disable primary plane and set surface base address */ - for (plane = PLANE_A; plane <= PLANE_C; plane++) { - gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE); - gtt_write(DSPSURF(plane), 0x00000000); + /* Enable push bus metric control and shift */ + gtt_write(0xa248, 0x00000004); + gtt_write(0xa250, 0x000000ff); + gtt_write(0xa25c, 0x00000010); + + /* Set GFXPAUSE based on stepping */ + if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) && + haswell_is_ult() && systemagent_revision() <= 9) { + gtt_write(0xa000, 0x300ff); + } else { + gtt_write(0xa000, 0x30020); } - /* Disable VGA display */ - gtt_write(CPU_VGACNTRL, CPU_VGA_DISABLE); + /* ECO settings */ + gtt_write(0xa180, 0x45200000); + + /* Enable DOP Clock Gating */ + gtt_write(0x9424, 0x000000fd); + + /* Enable Unit Level Clock Gating */ + gtt_write(0x9400, 0x00000000); + gtt_write(0x9404, 0x40401000); + gtt_write(0x9408, 0x00000000); + gtt_write(0x940c, 0x02000001); + gtt_write(0x1a054, 0x0000000a); + + /* Set RP1 graphics frequency */ + const u32 rp1_gfx_freq = (mchbar_read32(0x5998) >> 8) & 0xff; + gtt_write(0xa008, rp1_gfx_freq << 24); + + /* Video Frequency Request */ + gtt_write(0xa00c, 0x08000000); + + gtt_write(0x138158, 0x00000009); + gtt_write(0x13815c, 0x0000000d); + + /* Wake Rate Limits */ + gtt_write(0xa090, 0x00000000); + gtt_write(0xa098, 0x03e80000); + gtt_write(0xa09c, 0x00280000); + gtt_write(0xa0a8, 0x0001e848); + gtt_write(0xa0ac, 0x00000019); + + /* Render/Video/Blitter Idle Max Count */ + gtt_write(0x02054, 0x0000000a); + gtt_write(0x12054, 0x0000000a); + gtt_write(0x22054, 0x0000000a); + + /* RC Sleep / RCx Thresholds */ + gtt_write(0xa0b0, 0x00000000); + gtt_write(0xa0b8, 0x00000271); + + /* RP Settings */ + gtt_write(0xa010, 0x000f4240); + gtt_write(0xa014, 0x12060000); + gtt_write(0xa02c, 0x0000e808); + gtt_write(0xa030, 0x0003bd08); + gtt_write(0xa068, 0x000101d0); + gtt_write(0xa06c, 0x00055730); + gtt_write(0xa070, 0x0000000a); + gtt_write(0xa168, 0x00000006); + + /* RP Control */ + gtt_write(0xa024, 0x00000b92); + + /* HW RC6 Control */ + gtt_write(0xa090, 0x90040000); + + /* Set RC6 VIDs */ + gtt_pcode_write(GEN6_PCODE_WRITE_RC6VIDS, 0); + + /* Enable PM Interrupts */ + gtt_write(0x4402c, 0x03000076); + + /* Enable RC6 in idle */ + gtt_write(0xa094, 0x00040000); + + /* PM Lock Settings */ + gtt_or(0xa248, 1ul << 31); + gtt_or(0xa000, 1 << 18); + gtt_or(0xa180, 1ul << 31); } static void gma_setup_panel(struct device *dev) @@ -316,11 +386,6 @@ static void gma_setup_panel(struct device *dev) BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } - /* Get display,pipeline,and DDI registers into a basic sane state */ - power_well_enable(); - - init_display_planes(); - /* * DDI-A params set: * bit 0: Display detected (RO) @@ -331,74 +396,183 @@ static void gma_setup_panel(struct device *dev) if (!conf->gpu_ddi_e_connected) reg32 |= DDI_A_4_LANES; gtt_write(DDI_BUF_CTL_A, reg32); +} + +enum gpu_type { + GPU_TYPE_ULX, + GPU_TYPE_ULT, + GPU_TYPE_TRAD, +}; + +static enum gpu_type get_gpu_type(struct device *dev) +{ + if (haswell_is_ult()) { + const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); + switch (devid) { + case 0x0a0e: + case 0x0a1e: + case 0x161e: + return GPU_TYPE_ULX; + default: + return GPU_TYPE_ULT; + } + } else { + return GPU_TYPE_TRAD; + } +} + +enum gt_cdclk { + GT_CDCLK_DEFAULT = 0, + GT_CDCLK_337, + GT_CDCLK_450, + GT_CDCLK_540, + GT_CDCLK_675, +}; + +static enum gt_cdclk get_cdclk(bool is_broadwell, enum gpu_type type) +{ + /* TODO: Make this a config option? */ + enum gt_cdclk cdclk = GT_CDCLK_DEFAULT; + + /* If CDCLK frequency selection is not supported, 450 MHz is forced */ + if (gtt_read(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) + return GT_CDCLK_450; + + /* + * BDW ULT/ULX requires extra cooling to run at the highest frequency + * TODO: Make this a devicetree setting? + */ + const bool bdw_ult_high_power = false; + + enum gt_cdclk lower_cdclk; + enum gt_cdclk upper_cdclk; + switch (type) { + case GPU_TYPE_ULX: + if (is_broadwell) { + lower_cdclk = GT_CDCLK_337; + upper_cdclk = bdw_ult_high_power ? GT_CDCLK_540 : GT_CDCLK_450; + } else { + lower_cdclk = GT_CDCLK_337; + upper_cdclk = GT_CDCLK_450; + } + break; + case GPU_TYPE_ULT: + if (is_broadwell) { + lower_cdclk = GT_CDCLK_337; + upper_cdclk = bdw_ult_high_power ? GT_CDCLK_675 : GT_CDCLK_540; + } else { + lower_cdclk = GT_CDCLK_450; + upper_cdclk = GT_CDCLK_450; + } + break; + case GPU_TYPE_TRAD: + if (is_broadwell) { + lower_cdclk = GT_CDCLK_337; + upper_cdclk = GT_CDCLK_675; + } else { + lower_cdclk = GT_CDCLK_450; + upper_cdclk = GT_CDCLK_540; + } + break; + default: + lower_cdclk = GT_CDCLK_450; + upper_cdclk = GT_CDCLK_450; + break; + } - /* Set FDI registers - is this required? */ - gtt_write(_FDI_RXA_MISC, 0x00200090); - gtt_write(_FDI_RXA_MISC, 0x0a000000); + if (cdclk == GT_CDCLK_DEFAULT) + cdclk = upper_cdclk; - /* Enable the handshake with PCH display when processing reset */ - gtt_write(NDE_RSTWRN_OPT, RST_PCH_HNDSHK_EN); + /* Clamp CDCLK to supported range */ + return MAX(lower_cdclk, MIN(cdclk, upper_cdclk)); +} - /* Undocumented */ - gtt_write(0x42090, 0x04000000); - gtt_write(0x9840, 0x00000000); - gtt_write(0x42090, 0xa4000000); +static u32 cdsel_from_cdclk(bool is_broadwell, enum gt_cdclk cdclk) +{ + if (!is_broadwell) + return cdclk != GT_CDCLK_450; + + switch (cdclk) { + default: + case GT_CDCLK_450: return 0; + case GT_CDCLK_540: return 1; + case GT_CDCLK_337: return 2; + case GT_CDCLK_675: return 3; + } +} - gtt_write(SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE); +#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 +#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 - /* Undocumented */ - gtt_write(0x42080, 0x00004000); +static void gma_cdclk_init(struct device *dev, bool is_broadwell) +{ + if (is_broadwell) { + /* Inform power controller of upcoming frequency change */ + if (!gtt_pcode_write(BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0)) { + printk(BIOS_ERR, "Failed to inform pcode about cdclk change\n"); + return; + } + } - /* Prepare DDI buffers for DP and FDI */ - intel_prepare_ddi(); + const enum gpu_type type = get_gpu_type(dev); + const enum gt_cdclk cdclk = get_cdclk(is_broadwell, type); - /* Hot plug detect buffer enabled for port A */ - gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE); + assert(cdclk >= GT_CDCLK_337); - /* Enable HPD buffer for digital port D and B */ - gtt_write(PCH_PORT_HOTPLUG, PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE); + const u32 cdsel = cdsel_from_cdclk(is_broadwell, cdclk); /* - * Bits 4:0 - Power cycle delay (default 0x6 --> 500ms) - * Bits 31:8 - Reference divider (0x0004af ----> 24MHz) + * Set CD Clock Frequency Select + * TODO: For BDW, should we switch CDCLK source to FCLK before + * updating the CDCLK frequency selector, or is it a non-issue + * when done so early? */ - gtt_write(PCH_PP_DIVISOR, 0x0004af06); -} + gtt_rmw(LCPLL_CTL, ~LCPLL_CLK_FREQ_MASK, cdsel << 26); -static void gma_pm_init_post_vbios(struct device *dev) -{ - int cdclk = 0; - int devid = pci_read_config16(dev, PCI_DEVICE_ID); - int gpu_is_ulx = 0; + if (is_broadwell || type == GPU_TYPE_ULX) { + /* Inform power controller of selected frequency */ + gtt_pcode_write(HSW_PCODE_DE_WRITE_FREQ_REQ, cdsel); + } - if (devid == 0x0a0e || devid == 0x0a1e) - gpu_is_ulx = 1; + if (is_broadwell) { + u32 cdval, dpdiv; + switch (cdclk) { + case GT_CDCLK_337: + cdval = 337; + dpdiv = 169; + break; + case GT_CDCLK_450: + cdval = 449; + dpdiv = 225; + break; + case GT_CDCLK_540: + cdval = 539; + dpdiv = 270; + break; + case GT_CDCLK_675: + cdval = 674; + dpdiv = 338; + break; + default: + return; + } - /* CD Frequency */ - if ((gtt_read(0x42014) & 0x1000000) || gpu_is_ulx || haswell_is_ult()) - cdclk = 0; /* fixed frequency */ - else - cdclk = 2; /* variable frequency */ + /* Program CD Clock Frequency */ + gtt_rmw(0x46200, 0xfffffc00, cdval); - if (gpu_is_ulx || cdclk != 0) - gtt_rmw(0x130040, 0xf7ffffff, 0x04000000); - else - gtt_rmw(0x130040, 0xf3ffffff, 0x00000000); - - /* More magic */ - if (haswell_is_ult() || gpu_is_ulx) { - if (!gpu_is_ulx) - gtt_write(0x138128, 0x00000000); - else - gtt_write(0x138128, 0x00000001); - gtt_write(0x13812c, 0x00000000); - gtt_write(0x138124, 0x80000017); + /* Set CPU DP AUX 2X bit clock dividers */ + gtt_rmw(0x64010, 0xfffff800, dpdiv); + gtt_rmw(0x64810, 0xfffff800, dpdiv); } +} +static void gma_pm_init_post_vbios(bool is_broadwell) +{ /* Disable Force Wake */ - gtt_write(0x0a188, 0x00010000); + gtt_write(0xa188, 0x00010000); gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 0 << 0); - gtt_write(0x0a188, 0x00000001); + if (!is_broadwell) + gtt_write(0xa188, 0x00000001); } /* Enable SCI to ACPI _GPE._L06 */ @@ -417,16 +591,31 @@ static void gma_enable_swsci(void) static void gma_func0_init(struct device *dev) { + const bool is_broadwell = cpu_is_broadwell(); + int lightup_ok = 0; intel_gma_init_igd_opregion(); + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; + /* Init graphics power management */ - gma_pm_init_pre_vbios(dev); + if (is_broadwell) + gma_pm_init_broadwell(); + else + gma_pm_init_haswell(); + + /* Enable power well for DP and Audio */ + gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); + gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); /* Pre panel init */ gma_setup_panel(dev); + gma_cdclk_init(dev, is_broadwell); + if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -450,7 +639,7 @@ static void gma_func0_init(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - gma_pm_init_post_vbios(dev); + gma_pm_init_post_vbios(is_broadwell); gma_enable_swsci(); } @@ -479,29 +668,36 @@ static struct device_operations gma_func0_ops = { }; static const unsigned short pci_device_ids[] = { - 0x0402, /* Desktop GT1 */ - 0x0412, /* Desktop GT2 */ - 0x041e, /* Desktop GT1.5 */ - 0x0422, /* Desktop GT3 */ - 0x0d22, /* Desktop GT3e */ - 0x0406, /* Mobile GT1 */ - 0x0416, /* Mobile GT2 */ - 0x0426, /* Mobile GT3 */ - 0x040a, /* Server GT1 */ - 0x041a, /* Server GT2 */ - 0x042a, /* Server GT3 */ - 0x0d16, /* Mobile 4+3 GT1 */ - 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ - 0x0d36, /* Mobile 4+3 GT3 */ - 0x0a06, /* ULT GT1 */ - 0x0a16, /* ULT GT2 */ - 0x0a26, /* ULT GT3 */ - 0x0a0e, /* ULX GT1 */ - 0x0a1e, /* ULX GT2 */ + 0x0402, /* HSW Desktop GT1 */ + 0x0412, /* HSW Desktop GT2 */ + 0x041e, /* HSW Desktop GT1.5 */ + 0x0422, /* HSW Desktop GT3 */ + 0x0d22, /* HSW Desktop GT3e */ + 0x0406, /* HSW Mobile GT1 */ + 0x0416, /* HSW Mobile GT2 */ + 0x0426, /* HSW Mobile GT3 */ + 0x040a, /* HSW Server GT1 */ + 0x041a, /* HSW Server GT2 */ + 0x042a, /* HSW Server GT3 */ + 0x0d16, /* HSW Mobile 4+3 GT1 */ + 0x0d26, /* HSW Mobile 4+3 GT2, Mobile GT3e */ + 0x0d36, /* HSW Mobile 4+3 GT3 */ + 0x0a06, /* HSW ULT GT1 */ + 0x0a16, /* HSW ULT GT2 */ + 0x0a26, /* HSW ULT GT3 */ + 0x0a0e, /* HSW ULX GT1 */ + 0x0a1e, /* HSW ULX GT2 */ + 0x1612, /* BDW Halo GT2 */ + 0x1622, /* BDW Halo/Desktop GT3 */ + 0x1606, /* BDW ULT GT1 */ + 0x1616, /* BDW ULT GT2 */ + 0x1626, /* BDW ULT GT3 15W */ + 0x162b, /* BDW ULT GT3 28W */ + 0x161e, /* BDW ULX GT2 */ 0, }; -static const struct pci_driver pch_lpc __pci_driver = { +static const struct pci_driver gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VID_INTEL, .devices = pci_device_ids, diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index d7439ca7b10..b4c49768ba2 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -9,8 +9,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 82e1d6552f2..de5dd611fb2 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,10 +4,11 @@ #define __SIMPLE_DEVICE__ #include +#include +#include #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 91c1920725a..6fa8ec06e52 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c index 54fee0121dc..cd28139ef46 100644 --- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c +++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "raminit_native.h" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 84d9fb57927..c3557be357f 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -1,17 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include -#include #include +#include +#include #include #include #include #include -#include #include -#include #include #include "chip.h" @@ -146,14 +143,10 @@ struct map_entry { static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { - uint64_t value; - uint64_t mask; - /* All registers have a 1MiB granularity */ - mask = ((1ULL << 20) - 1); - mask = ~mask; + const uint64_t mask = ~((1ULL << 20) - 1); - value = 0; + uint64_t value = 0; if (entry->is_64_bit) { value = pci_read_config32(dev, entry->reg + 4); @@ -211,16 +204,14 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { static void mc_read_map_entries(struct device *dev, uint64_t *values) { - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { + for (int i = 0; i < NUM_MAP_ENTRIES; i++) { read_map_entry(dev, &memory_map[i], &values[i]); } } static void mc_report_map_entries(struct device *dev, uint64_t *values) { - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { + for (int i = 0; i < NUM_MAP_ENTRIES; i++) { printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } @@ -230,12 +221,11 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values) static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - int index; uint64_t mc_values[NUM_MAP_ENTRIES]; /* Read in the MAP registers and report their values */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); + mc_read_map_entries(dev, mc_values); + mc_report_map_entries(dev, mc_values); /* * DMA Protected Range can be reserved below TSEG for PCODE patch @@ -274,14 +264,13 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) * * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ - index = *resource_cnt; + int index = *resource_cnt; /* * 0 - > 0xa0000: RAM * 0xa0000 - 0xbffff: Legacy VGA * 0xc0000 - 0xfffff: RAM */ - ram_range(dev, index++, 0, 0xa0000); mmio_from_to(dev, index++, 0xa0000, 0xc0000); reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); @@ -477,6 +466,9 @@ static void northbridge_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit. */ mdelay(1); set_power_limits(28); + + /* Apply OC mailbox settings (e.g. undervolt) after power limits. */ + program_oc_mailbox(); } static void northbridge_final(struct device *dev) diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index 4eeaa3f4158..345f00d53d2 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include +#include #include #include -#include #include #include "chip.h" diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index df0dab76126..dc296d2b105 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include +#include #include +#include #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e940b8d6f41..5b044af4ff9 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b7654172749..dabfe6aa3c8 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 839b7846c4c..c81b23e5225 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index aea1cc5e1e4..6abc8451069 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -8,7 +8,6 @@ #include #include "ironlake.h" #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index ae27d854a30..cc281d9e6fd 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index de2d8400d28..a1bc968710b 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5755eaaf7d5..efb83a0feb6 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 439221f84bc..b024c399560 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -100,10 +100,10 @@ static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) static void setup_sdram_meminfo(ramctr_timing *ctrl) { int channel, slot; - const u16 ddr_freq = (1000 << 8) / ctrl->tCK; + const u16 ddr_clock_mhz = NS2MHZ_DIV256 / ctrl->tCK; FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { - enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, + enum cb_err ret = spd_add_smbios17(channel, slot, ddr_clock_mhz, &ctrl->info.dimm[channel][slot]); if (ret != CB_SUCCESS) printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 51d6786f34c..980c8df8984 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 06380725f63..94df81923a0 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -6,7 +6,6 @@ #include #include "sandybridge.h" #include -#include #include #include #include diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 3e6cf113aed..c7831b85d03 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 85606d4ec85..c070e2fc8f5 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index ec76cea2133..d59f6d3a0f2 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -80,7 +80,7 @@ config BOOTMEDIA_LOCK_TOPSWAP help Select this if you want to write-protect the BOOTBLOCK and COREBOOT (Slot A) regions as specified in the Top Swap FMAP. You will be able to - write to the TOPSWAP and COREBOOT_TS (Slot B) regions and set the + write to the BOOTBLOCK_B and COREBOOT_B (Slot B) regions and set the attempt_slot_b CMOS option to run updated firmware. The BOOTBLOCK and COREBOOT regions will remain a read-only golden copy, which you can then revert to by resetting CMOS. diff --git a/src/security/tcg/opal_s3/Kconfig b/src/security/tcg/opal_s3/Kconfig index a34f34234e9..15f19af46f0 100644 --- a/src/security/tcg/opal_s3/Kconfig +++ b/src/security/tcg/opal_s3/Kconfig @@ -7,6 +7,7 @@ config TCG_OPAL_S3_UNLOCK depends on HAVE_ACPI_RESUME depends on PCI select SMM_OPAL_S3_SCRATCH_CBMEM + select SMM_OPAL_S3_STATE_SMRAM help Provide an SMM handler that accepts an OPAL password for the current sleep cycle and performs an NVMe Security Send/Receive unlock on S3 diff --git a/src/security/tcg/opal_s3/opal_s3_resume.c b/src/security/tcg/opal_s3/opal_s3_resume.c new file mode 100644 index 00000000000..415564c2041 --- /dev/null +++ b/src/security/tcg/opal_s3/opal_s3_resume.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void opal_s3_resume_unlock(void) +{ + u32 rc = call_smm(APM_CNT_OPAL_S3_UNLOCK, 0, NULL); + + if (CONFIG(DEBUG_SMI) && rc) + printk(BIOS_DEBUG, "OPAL-S3: resume unlock rc=0x%x\n", rc); +} diff --git a/src/security/tcg/opal_s3/opal_s3_smm.c b/src/security/tcg/opal_s3/opal_s3_smm.c new file mode 100644 index 00000000000..4802b9dceb0 --- /dev/null +++ b/src/security/tcg/opal_s3/opal_s3_smm.c @@ -0,0 +1,450 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "opal_secure.h" + +#define OPAL_S3_SCRATCH_ALIGN 4096 +#define OPAL_S3_SCRATCH_PAGES 3 +#define OPAL_S3_SCRATCH_MIN_BYTES (OPAL_S3_SCRATCH_PAGES * OPAL_S3_SCRATCH_ALIGN) + +#define OPAL_S3_UNLOCK_RETRY_DELAY_MS 50 +#define OPAL_S3_UNLOCK_RETRIES 10 + +#define OPAL_S3_STATE_SIGNATURE 0x33534c4f /* "OLS3" */ +#define OPAL_S3_STATE_VERSION 0x0001 + +#define OPAL_S3_ARMED_NONE 0 +#define OPAL_S3_ARMED_S3 1 + +#define OPAL_S3_MAX_SECRETS 8 + +struct __packed opal_s3_secret { + u8 valid; + u8 reserved0; + u16 reserved1; + + u8 bus; + u8 dev; + u8 func; + u8 reserved2; + + u16 base_comid; + u8 password_len; + u8 reserved3; + u8 password[OPAL_S3_MAX_PASSWORD_LEN]; + + u32 nvme_bar0_low; + u32 nvme_bar0_high; + + u32 unlocked_cycle; +}; + +struct __packed opal_s3_state { + u32 signature; + u16 version; + u16 size; + + u8 armed_state; + u8 reserved0; + u16 reserved1; + + u32 sleep_cycle; + u32 armed_cycle; + + struct opal_s3_secret secret[OPAL_S3_MAX_SECRETS]; +}; + +static struct opal_s3_state state_fallback; + +static struct opal_s3_state *opal_s3_get_state(void) +{ +#if CONFIG(SMM_OPAL_S3_STATE_SMRAM) + uintptr_t base = 0; + size_t size = 0; + + smm_get_opal_s3_state_buffer(&base, &size); + if (base && size >= sizeof(struct opal_s3_state)) + return (struct opal_s3_state *)(uintptr_t)base; +#endif + + return &state_fallback; +} + +static bool opal_s3_validate_scratch(uintptr_t base, size_t size, uintptr_t *aligned_base_out, + size_t *aligned_size_out) +{ + uintptr_t aligned; + size_t aligned_size; + + if (!base || !size) + return false; + + if (base + size < base) + return false; + + aligned = ALIGN_UP(base, OPAL_S3_SCRATCH_ALIGN); + if (aligned < base) + return false; + + if (aligned - base > size) + return false; + + aligned_size = size - (aligned - base); + if (aligned_size < OPAL_S3_SCRATCH_MIN_BYTES) + return false; + + if ((aligned & (OPAL_S3_SCRATCH_ALIGN - 1)) != 0) + return false; + + if (smm_points_to_smram((void *)(uintptr_t)aligned, OPAL_S3_SCRATCH_MIN_BYTES)) + return false; + + if (aligned + OPAL_S3_SCRATCH_MIN_BYTES < aligned) + return false; + if (aligned + OPAL_S3_SCRATCH_MIN_BYTES > base + size) + return false; + + *aligned_base_out = aligned; + *aligned_size_out = aligned_size; + return true; +} + +static u32 opal_s3_clear_secret(void) +{ + struct opal_s3_state *st = opal_s3_get_state(); + + opal_explicit_bzero(st, sizeof(*st)); + + return 0; +} + +static struct opal_s3_secret *opal_s3_find_secret(struct opal_s3_state *st, + const struct opal_s3_smm_ctx *ctx) +{ + for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) { + struct opal_s3_secret *s = &st->secret[i]; + + if (!s->valid) + continue; + + if (s->bus == ctx->bus && s->dev == ctx->dev && s->func == ctx->func && + s->base_comid == ctx->base_comid) + return s; + } + + return NULL; +} + +static struct opal_s3_secret *opal_s3_alloc_secret(struct opal_s3_state *st) +{ + for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) { + struct opal_s3_secret *s = &st->secret[i]; + + if (!s->valid) + return s; + } + + return NULL; +} + +static u32 opal_s3_set_secret(const struct opal_s3_smm_ctx *ctx) +{ + struct opal_s3_state *st = opal_s3_get_state(); + struct opal_s3_secret *s; + uintptr_t scratch_base = 0; + size_t scratch_size = 0; + uintptr_t aligned_base = 0; + size_t aligned_size = 0; + pci_devfn_t nvme_dev; + + if (!ctx) + return 1; + + if (smm_points_to_smram(ctx, sizeof(*ctx))) + return 2; + + if (ctx->signature != OPAL_S3_SMM_CTX_SIGNATURE) + return 3; + + if (ctx->version != OPAL_S3_SMM_CTX_VERSION) + return 4; + + if (ctx->size < sizeof(*ctx)) + return 5; + + if (ctx->password_len == 0 || ctx->password_len > OPAL_S3_MAX_PASSWORD_LEN) + return 6; + + smm_get_opal_s3_scratch_buffer(&scratch_base, &scratch_size); + if (!opal_s3_validate_scratch(scratch_base, scratch_size, &aligned_base, + &aligned_size)) { + printk(BIOS_ERR, "OPAL: invalid scratch (base=0x%lx size=0x%zx)\n", + (unsigned long)scratch_base, scratch_size); + return 7; + } + + nvme_dev = PCI_DEV(ctx->bus, ctx->dev, ctx->func); + + if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION || + st->size != sizeof(*st)) { + opal_s3_clear_secret(); + st->signature = OPAL_S3_STATE_SIGNATURE; + st->version = OPAL_S3_STATE_VERSION; + st->size = sizeof(*st); + st->armed_state = OPAL_S3_ARMED_NONE; + } + + s = opal_s3_find_secret(st, ctx); + if (!s) + s = opal_s3_alloc_secret(st); + if (!s) + return 8; + + opal_explicit_bzero(s, sizeof(*s)); + s->valid = 1; + s->bus = ctx->bus; + s->dev = ctx->dev; + s->func = ctx->func; + s->base_comid = ctx->base_comid; + s->password_len = ctx->password_len; + memcpy(s->password, ctx->password, ctx->password_len); + + st->signature = OPAL_S3_STATE_SIGNATURE; + st->version = OPAL_S3_STATE_VERSION; + st->size = sizeof(*st); + + s->nvme_bar0_low = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0); + s->nvme_bar0_high = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0 + 4); + + return 0; +} + +static void opal_s3_arm_for_s3(void) +{ + struct opal_s3_state *st = opal_s3_get_state(); + bool any_secret = false; + + if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION || + st->size != sizeof(*st)) + return; + + if (st->armed_state == OPAL_S3_ARMED_S3) + return; + + for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) { + if (!st->secret[i].valid) + continue; + + any_secret = true; + st->secret[i].unlocked_cycle = 0; + } + if (!any_secret) + return; + + st->sleep_cycle++; + st->armed_cycle = st->sleep_cycle; + st->armed_state = OPAL_S3_ARMED_S3; +} + +static void opal_s3_restore_nvme_bar0_if_needed(pci_devfn_t nvme_dev, u32 saved_bar0_low, + u32 saved_bar0_high) +{ + const u32 cur_low = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0); + const u32 cur_base = cur_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + const u32 saved_base = saved_bar0_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + const bool is_saved_mem = + ((saved_bar0_low & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY); + const bool is_saved_64 = + ((saved_bar0_low & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64); + + if (cur_low != 0xffffffff && cur_base != 0) + return; + + if (!saved_bar0_low || saved_base == 0 || !is_saved_mem) + return; + + pci_write_config32(nvme_dev, PCI_BASE_ADDRESS_0, saved_bar0_low); + if (is_saved_64) + pci_write_config32(nvme_dev, PCI_BASE_ADDRESS_0 + 4, saved_bar0_high); +} + +static bool opal_s3_unlock_should_keep_armed(u32 rc) +{ + return rc == 1 || rc == 3; +} + +static u32 opal_s3_unlock_if_armed(void) +{ + struct opal_s3_state *st = opal_s3_get_state(); + u32 rc = 0; + uintptr_t scratch_base = 0; + size_t scratch_size = 0; + uintptr_t aligned_base = 0; + size_t aligned_size = 0; + bool keep_armed = false; + + if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION || + st->size != sizeof(*st)) + return 0x10; + + if (st->armed_state == OPAL_S3_ARMED_NONE) + return 0x11; + + if (st->armed_cycle != st->sleep_cycle) { + printk(BIOS_ERR, "OPAL: unlock rejected (invalid sequence)\n"); + opal_s3_clear_secret(); + return 0x12; + } + + smm_get_opal_s3_scratch_buffer(&scratch_base, &scratch_size); + if (!opal_s3_validate_scratch(scratch_base, scratch_size, &aligned_base, + &aligned_size)) { + printk(BIOS_ERR, "OPAL: scratch invariant failed at unlock\n"); + st->armed_state = OPAL_S3_ARMED_NONE; + st->armed_cycle = 0; + return 2; + } + + for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) { + struct opal_s3_secret *s = &st->secret[i]; + pci_devfn_t nvme_dev; + u32 one_rc; + + if (!s->valid) + continue; + if (s->password_len == 0 || s->password_len > OPAL_S3_MAX_PASSWORD_LEN) + continue; + if (s->unlocked_cycle == st->sleep_cycle) + continue; + + nvme_dev = PCI_DEV(s->bus, s->dev, s->func); + opal_s3_restore_nvme_bar0_if_needed(nvme_dev, s->nvme_bar0_low, + s->nvme_bar0_high); + + one_rc = 1; + for (int attempt = 0; attempt < OPAL_S3_UNLOCK_RETRIES; attempt++) { + if (attempt) + mdelay(OPAL_S3_UNLOCK_RETRY_DELAY_MS); + + one_rc = opal_nvme_opal_unlock(nvme_dev, s->base_comid, s->password, + s->password_len, + (void *)(uintptr_t)aligned_base, + aligned_size); + if (one_rc == 0) + break; + if (one_rc != 1) + break; + } + + if (one_rc == 0) { + s->unlocked_cycle = st->sleep_cycle; + continue; + } + + if (opal_s3_unlock_should_keep_armed(one_rc)) { + keep_armed = true; + if (rc == 0 || rc == 1) + rc = one_rc; + continue; + } + + if (rc == 0) + rc = one_rc; + + s->unlocked_cycle = st->sleep_cycle; + } + + if (!keep_armed) { + st->armed_state = OPAL_S3_ARMED_NONE; + st->armed_cycle = 0; + } + + return rc; +} + +int opal_s3_smi_apmc(u8 apmc) +{ + int node; + u64 rax; + u64 rbx; + u8 subcmd; + u32 ret; + u32 unlock_rc; + + switch (apmc) { + case APM_CNT_OPAL_S3_UNLOCK: + unlock_rc = opal_s3_unlock_if_armed(); + + node = get_apmc_node(apmc); + if (node >= 0) { + const u64 rax_out = unlock_rc; + (void)set_save_state_reg(RAX, node, (void *)&rax_out, sizeof(rax_out)); + } + return 1; + + case APM_CNT_OPAL_SVC: + break; + + default: + return 0; + } + + node = get_apmc_node(apmc); + if (node < 0) + return 0; + + if (get_save_state_reg(RAX, node, &rax, sizeof(rax)) < 0) + return 0; + if (get_save_state_reg(RBX, node, &rbx, sizeof(rbx)) < 0) + return 0; + + subcmd = (rax >> 8) & 0xff; + + switch (subcmd) { + case OPAL_SMM_SUBCMD_SET_SECRET: + ret = opal_s3_set_secret((const struct opal_s3_smm_ctx *)(uintptr_t)rbx); + break; + case OPAL_SMM_SUBCMD_CLEAR_SECRET: + ret = opal_s3_clear_secret(); + break; + default: + ret = 0xfffffffe; + break; + } + + { + const u64 rax_out = ret; + + (void)set_save_state_reg(RAX, node, (void *)&rax_out, sizeof(rax_out)); + } + return 1; +} + +void opal_s3_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S3) + opal_s3_arm_for_s3(); + else + opal_s3_clear_secret(); +} + +void opal_s3_smi_sleep_finalize(u8 slp_typ) +{ + if (slp_typ != ACPI_S3) + opal_s3_clear_secret(); +} diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index def2fc35133..899b73f7b15 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -9,10 +9,6 @@ #include #include -/* This include is available as only if CONFIG_SOC_INTEL_COMMON_BLOCK is - set, which is not guaranteed for this file. */ -#include - static int tpm_log_initialized; static inline int tpm_log_available(void) { @@ -79,17 +75,9 @@ static tpm_result_t tspi_init_crtm(void) void *mapping = NULL; if (CONFIG(INTEL_TOP_SWAP_SEPARATE_REGIONS)) { - enum ts_config top_swap = get_rtc_buc_top_swap_status(); - if (top_swap == TS_ENABLE) - printk(BIOS_INFO, - "CRTM Top Swap: Measuring bootblock in TOPSWAP (will be logged as BOOTBLOCK).\n"); - else - printk(BIOS_INFO, - "CRTM Top Swap: Measuring bootblock in BOOTBLOCK.\n"); - /* * Whether Top Swap is active or not, FMAP always refers to the same - * memory ranges but the contents of BOOTBLOCK and TOPSWAP are swapped. + * memory ranges but the contents of BOOTBLOCK and BOOTBLOCK_B are swapped. * Hence always using BOOTBLOCK region to access the active bootblock. */ mapping = cbfs_unverified_area_type_alloc("BOOTBLOCK", "bootblock", diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 56b8fa8ede3..b69273e5f2c 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -73,6 +73,14 @@ static tpm_result_t tpm_setup_s3_helper(void) default: printk(BIOS_ERR, "TPM: Resume failed (%#x).\n", rc); + if (CONFIG(TPM2)) { + /* + * TODO: Record EV_SEPARATOR event to indicate to host + * that an error has occurred. + */ + printk(BIOS_WARNING, "TPM: Performing restart\n"); + rc = tlcl_startup(); + } break; } diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk index 465205af42e..385a69779f4 100644 --- a/src/security/vboot/Makefile.mk +++ b/src/security/vboot/Makefile.mk @@ -7,6 +7,7 @@ verstage-y += vboot_lib.c romstage-y += vboot_lib.c ramstage-y += vboot_lib.c postcar-y += vboot_lib.c +smm-y += vboot_lib.c vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ $(patsubst -I$(top)/%,-I%,\ @@ -54,6 +55,7 @@ $(eval $(call vboot-for-stage,romstage)) endif $(eval $(call vboot-for-stage,ramstage)) $(eval $(call vboot-for-stage,postcar)) +$(eval $(call vboot-for-stage,smm)) endif # CONFIG_VBOOT_LIB diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index dacd542c8e4..8ff5fedafdb 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -3,7 +3,6 @@ config SOC_AMD_CEZANNE_BASE bool select ACPI_SOC_NVS - select ADD_FSP_BINARIES if USE_AMD_BLOBS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -43,8 +42,10 @@ config SOC_AMD_CEZANNE_BASE select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_EMMC + select SOC_AMD_COMMON_BLOCK_ENABLE_CACHE_ON_RESUME select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL @@ -53,6 +54,7 @@ config SOC_AMD_CEZANNE_BASE select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM @@ -86,12 +88,12 @@ config SOC_AMD_CEZANNE_BASE select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI help AMD Cezanne support config SOC_AMD_CEZANNE bool + select ADD_FSP_BINARIES if USE_AMD_BLOBS select SOC_AMD_CEZANNE_BASE help AMD Cezanne support @@ -104,22 +106,30 @@ config SOC_AMD_RENOIR help AMD Renoir support -if SOC_AMD_CEZANNE_BASE - -config KEEP_ACP_RUNNING_IN_S3 +config SOC_AMD_V2000A bool - default n + select ADD_FSP_BINARIES if USE_AMD_BLOBS + select SOC_AMD_CEZANNE_BASE + select SOC_AMD_SUPPORTS_WARM_RESET + select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR + select HAVE_X86_64_SUPPORT help - Enables AMD Audio Co-Processor (ACP) to remain operational in ACPI - S3 (sleep) state for continued audio processing support. + AMD V2000A support + +if SOC_AMD_CEZANNE_BASE config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/cezanne" if SOC_AMD_CEZANNE + default "src/vendorcode/amd/fsp/renoir" if SOC_AMD_RENOIR || SOC_AMD_V2000A + config FSP_M_FILE string "FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/v2000a/V2000A_M.fd" if SOC_AMD_V2000A #default "3rdparty/amd_blobs/renoir/RENOIR_M.fd" if SOC_AMD_RENOIR default "3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" help @@ -128,6 +138,7 @@ config FSP_M_FILE config FSP_S_FILE string "FSP-S (silicon init) binary path and filename" depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/v2000a/V2000A_S.fd" if SOC_AMD_V2000A #default "3rdparty/amd_blobs/renoir/RENOIR_S.fd" if SOC_AMD_RENOIR default "3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" help @@ -156,12 +167,12 @@ config PSP_APOB_DRAM_ADDRESS config PSP_APOB_DRAM_SIZE hex - default 0x1E000 if SOC_AMD_RENOIR + default 0x1E000 if (SOC_AMD_RENOIR || SOC_AMD_V2000A) default 0x10000 config PSP_SHAREDMEM_BASE hex - default 0x201F000 if VBOOT && SOC_AMD_RENOIR + default 0x201F000 if VBOOT && (SOC_AMD_RENOIR || SOC_AMD_V2000A) default 0x2011000 if VBOOT default 0x0 help @@ -273,10 +284,11 @@ config RO_REGION_ONLY default "apu/amdfw" config ECAM_MMCONF_BASE_ADDRESS - default 0xE0000000 if SOC_AMD_RENOIR + default 0xE0000000 if (SOC_AMD_RENOIR || SOC_AMD_V2000A) default 0xF8000000 config ECAM_MMCONF_BUS_NUMBER + default 256 if (SOC_AMD_RENOIR || SOC_AMD_V2000A) default 64 config MAX_CPUS @@ -287,7 +299,7 @@ config MAX_CPUS config VGA_BIOS_ID string - default "1002,1636" if SOC_AMD_RENOIR + default "1002,1636" if (SOC_AMD_RENOIR || SOC_AMD_V2000A) default "1002,1638" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -295,6 +307,7 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string + default "3rdparty/amd_blobs/v2000a/RenoirGenericVbios.bin" if SOC_AMD_V2000A #default "3rdparty/amd_blobs/renoir/RenoirGenericVbios.bin" if SOC_AMD_RENOIR default "3rdparty/amd_blobs/cezanne/CezanneGenericVbios.bin" @@ -365,6 +378,7 @@ menu "PSP Configuration Options" config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" + default "src/soc/amd/cezanne/fw_v2000a.cfg" if SOC_AMD_V2000A #default "src/soc/amd/cezanne/fw_renoir.cfg" if SOC_AMD_RENOIR default "src/soc/amd/cezanne/fw.cfg" help @@ -416,6 +430,7 @@ config HAVE_PSP_WHITELIST_FILE config PSP_WHITELIST_FILE string "Debug whitelist file path" depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/amd_blobs/v2000a/PSP/wtl-rn.sbin" if SOC_AMD_V2000A #default "3rdparty/amd_blobs/renoir/PSP/wtl-rn.sbin" if SOC_AMD_RENOIR default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" @@ -446,13 +461,6 @@ config PSP_VERSTAGE_SIGNING_TOKEN default "" help Add psp_verstage signature token to the build & PSP Directory Table - -config PSP_RECOVERY_AB - bool "Use A/B Recovery scheme" - default n - help - Enable the PSP A/B Recovery mechanism - endmenu config VBOOT diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index ff32b740fed..675b454f89b 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -19,6 +19,7 @@ bootblock-y += espi_util.c romstage-y += fsp_m_params.c romstage-$(CONFIG_SOC_AMD_CEZANNE) += fsp_m_params_cezanne.c romstage-$(CONFIG_SOC_AMD_RENOIR) += fsp_m_params_renoir.c +romstage-$(CONFIG_SOC_AMD_V2000A) += fsp_m_params_renoir.c ramstage-y += acpi.c ramstage-y += chip.c @@ -38,15 +39,6 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -endif - -ifeq ($(CONFIG_SOC_AMD_RENOIR),y) -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/renoir -endif # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough @@ -191,7 +183,36 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) +# Target an offset into the CBFS. AMDFWTOOL will align it again and +# pad the space between the CBFS file header and the directory table. +# 0x80 accounts for the cbfs_file struct + filename + metadata structs +AMD_FW_AB_POSITION := 0x80 + +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) +CEZANNE_FW_A_RECOVERY=$(if $(call get_fmap_value,FMAP_SECTION_RECOVERY_A_START), $(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_A_START) $(AMD_FW_AB_POSITION)), \ + $(error "CONFIG_PSP_AB_RECOVERY is enabled but region RECOVERY_A is not defined in the flash map")) + +CEZANNE_FW_B_RECOVERY=$(if $(call get_fmap_value,FMAP_SECTION_RECOVERY_B_START), $(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_B_START) $(AMD_FW_AB_POSITION)), \ + $(error "CONFIG_PSP_AB_RECOVERY is enabled but region RECOVERY_B is not defined in the flash map")) + +ifeq ($(CONFIG_SOC_AMD_V2000A),y) + PSP_AB_NVRAM_BASE=$(if $(call get_fmap_value,FMAP_SECTION_PSP_AB_NVRAM_START), \ + $(call _tohex,$(call get_fmap_value,FMAP_SECTION_PSP_AB_NVRAM_START)), \ + $(error "CONFIG_PSP_AB_RECOVERY is enabled but region PSP_AB_NVRAM is not defined in the flash map")) + PSP_AB_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_AB_NVRAM_SIZE) +endif +endif + +OPT_PSP_AB_NVRAM_BASE=$(call add_opt_prefix, $(PSP_AB_NVRAM_BASE), --ab-nvram-base) +OPT_PSP_AB_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_AB_NVRAM_SIZE), --ab-nvram-size) + +OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_AB_RECOVERY), --recovery-ab) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-a-location $(call _tohex, $(CEZANNE_FW_A_RECOVERY))) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-b-location $(call _tohex, $(CEZANNE_FW_B_RECOVERY))) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ @@ -216,6 +237,8 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ $(OPT_RECOVERY_AB) \ + $(OPT_PSP_AB_NVRAM_BASE) \ + $(OPT_PSP_AB_NVRAM_SIZE) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) @@ -236,8 +259,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_BIOS_FWCOMPRESS) \ --location $(CONFIG_AMD_FWM_POSITION) \ - --multilevel \ --output $@ # @@ -250,8 +273,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) $(obj)/amdfw_a.rom: $(obj)/amdfw.rom rm -f $@ @@ -262,7 +285,6 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom $(OPT_APOB_NV_BASE) \ --location $(call _tohex,$(CEZANNE_FW_A_POSITION)) \ --anywhere \ - --multilevel \ --output $@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom @@ -274,7 +296,6 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom $(OPT_APOB_NV_BASE) \ --location $(call _tohex,$(CEZANNE_FW_B_POSITION)) \ --anywhere \ - --multilevel \ --output $@ @@ -294,4 +315,24 @@ apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw endif +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) + +$(obj)/amdfw.rom.ra: $(obj)/amdfw.rom +$(obj)/amdfw.rom.rb: $(obj)/amdfw.rom + +regions-for-file-apu/amdfw_ra = BOOTBLOCK +regions-for-file-apu/amdfw_rb = BOOTBLOCK_B + +cbfs-files-y += apu/amdfw_ra +apu/amdfw_ra-file := $(obj)/amdfw.rom.ra +apu/amdfw_ra-position := $(AMD_FW_AB_POSITION) +apu/amdfw_ra-type := amdfw + +cbfs-files-y += apu/amdfw_rb +apu/amdfw_rb-file := $(obj)/amdfw.rom.rb +apu/amdfw_rb-position := $(AMD_FW_AB_POSITION) +apu/amdfw_rb-type := amdfw + +endif + endif # ($(CONFIG_SOC_AMD_CEZANNE_BASE),y) diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 6d7bbefe193..0230ed76f92 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -45,6 +45,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | ACPI_FADT_PCI_EXPRESS_WAKE | diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl index 647ab748f29..17447fccc76 100644 --- a/src/soc/amd/cezanne/acpi/mmio.asl +++ b/src/soc/amd/cezanne/acpi/mmio.asl @@ -12,7 +12,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index 5749ff80b42..7e915a5adc3 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -43,7 +43,9 @@ Scope(\_SB) { /* Enable DPTC interface with AMD ALIB */ External(\_SB.DPTC, MethodObj) +#if CONFIG(CHROMEOS) #include "rtc_workaround.asl" +#endif /* * Platform Notify diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index a4a80f4cb83..77681e931c6 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -33,7 +33,7 @@ struct device_operations cezanne_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) @@ -57,6 +57,8 @@ struct chip_operations soc_amd_cezanne_ops = { .name = "AMD Cezanne SoC", #elif CONFIG(SOC_AMD_RENOIR) .name = "AMD Renoir SoC", +#elif CONFIG(SOC_AMD_V2000A) + .name = "AMD V2000A SoC", #endif .init = soc_init, .final = soc_final diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 9a1e1d7bab0..787244655c0 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -14,7 +14,7 @@ #if CONFIG(SOC_AMD_CEZANNE) #include -#elif CONFIG(SOC_AMD_RENOIR) +#elif CONFIG(SOC_AMD_RENOIR) || CONFIG(SOC_AMD_V2000A) #include #endif diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 14dba64fa7e..008f6382a45 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -32,12 +32,6 @@ chip soc/amd/cezanne chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off - chip drivers/usb/acpi - device usb 3.0 alias usb3_port0 off end - end - chip drivers/usb/acpi - device usb 3.1 alias usb3_port1 off end - end chip drivers/usb/acpi device usb 2.0 alias usb2_port0 off end end @@ -50,6 +44,12 @@ chip soc/amd/cezanne chip drivers/usb/acpi device usb 2.3 alias usb2_port3 off end end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port1 off end + end end end end @@ -58,12 +58,6 @@ chip soc/amd/cezanne chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off - chip drivers/usb/acpi - device usb 3.0 alias usb3_port4 off end - end - chip drivers/usb/acpi - device usb 3.1 alias usb3_port5 off end - end chip drivers/usb/acpi device usb 2.0 alias usb2_port4 off end end @@ -76,6 +70,12 @@ chip soc/amd/cezanne chip drivers/usb/acpi device usb 2.3 alias usb2_port7 off end end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port3 off end + end end end end diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 52d2e2b7041..17c82e0574a 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,6 +8,26 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; +} + +u8 smbios_cache_speed(u8 level) +{ + return 1; +} + static struct device_operations cpu_dev_ops = { .init = amd_cpu_init, }; diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 9e99da227dc..7289b602c08 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -17,8 +17,7 @@ static void lpc_configure_decodes(void) { - if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) - lpc_enable_port80(); + lpc_enable_port80(); } /* Before console init */ diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 1fabe3a8640..88e8552ff3b 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -152,10 +152,8 @@ static void cgpll_clock_gate_init(void) t = misc_read32(MISC_CLKGATEDCNTL); t |= ALINKCLK_GATEOFFEN; t |= BLINKCLK_GATEOFFEN; - - if (!CONFIG(KEEP_ACP_RUNNING_IN_S3)) { + if (!CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S3)) t |= XTAL_PAD_S3_TURNOFF_EN; - } t |= XTAL_PAD_S5_TURNOFF_EN; misc_write32(MISC_CLKGATEDCNTL, t); @@ -173,7 +171,7 @@ static void cgpll_clock_gate_init(void) void fch_init(void *chip_info) { - if (!CONFIG(SOC_AMD_RENOIR)) + if (!CONFIG(SOC_AMD_V2000A) && !CONFIG(SOC_AMD_RENOIR)) set_resets_to_cold(); i2c_soc_init(); diff --git a/src/soc/amd/cezanne/fw_v2000a.cfg b/src/soc/amd/cezanne/fw_v2000a.cfg new file mode 100644 index 00000000000..c84dbc01e75 --- /dev/null +++ b/src/soc/amd/cezanne/fw_v2000a.cfg @@ -0,0 +1,42 @@ +FIRMWARE_LOCATION 3rdparty/amd_blobs/v2000a/PSP +SOC_NAME Renoir + +# type file + +# PSP +AMD_PUBKEY_FILE RenoirRoot.tkn Lxb +PSPBTLDR_FILE PspBootLoader_prod_RN.sbin +PSPBTLDR_AB_STAGE1_FILE boot_loader_stage1_AB_RECOVERY_prod_RN.sbin Lx1 +PSPRCVR_FILE PspRecoveryBootLoader_prod_RN.sbin +PSPSECUREOS_FILE psp_os_combined_prod_RN.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmwareRN.csbin +PSPSECUREDEBUG_FILE RenoirSecureDebug_PublicKey.bin +PSPTRUSTLETS_FILE FtpmDrv_sha384_TPM_B.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2RN.csbin +PSP_SEC_DEBUG_FILE secure_unlock_RN.sbin +PSP_HW_IPCFG_FILE_SUB0 HwIpCfg_RN_A0.sbin +PSP_IKEK_FILE PspIkekRN.bin Lxb +PSP_SECG0_FILE security_policy_RN_FP6_AM4_PspBl.sbin +PSP_MP2FW0_FILE MP2FWRN.sbin +AMD_DRIVER_ENTRIES drv_sys_prod_RN.sbin +PSP_S0I3_FILE dr_agesa_prod_RN.sbin +PSP_ABL0_FILE AgesaBootloader_U_prod_RN_LPDDR4.csbin +VBIOS_BTLOADER_FILE VbiosBootLoader_prod.sbin +SECURE_POLICY_L1_FILE security_policy_RN_FP6_AM4_tOS.sbin +UNIFIEDUSB_FILE Unified_USB_RN.sbin +DRTMTA_FILE dr_drtm_out_prod.sbin +KEYDBBL_FILE prod_kdb_bl.bin +KEYDB_TOS_FILE prod_kdb_tos.sbin +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_RN.bin +DMCUERAMDCN21_FILE dmcu_eram_Dcn21.sbin +DMCUINTVECTORSDCN21_FILE dmcu_intvectors_Dcn21.sbin +PSPBTLDR_AB_FILE boot_loader_prod_AB_RECOVERY_RN.sbin +SPL_TABLE_FILE spl_table_prod_RN.sbin + +## BDT +RTM_PUBKEY_FILE RtmPubSignedRV.key +PSP_PMUI_FILE_SUB0_INS1 Appb_RN_1D_Lpddr4_Imem.csbin +PSP_PMUI_FILE_SUB0_INS4 Appb_RN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 Appb_RN_1D_Lpddr4_Dmem.csbin +PSP_PMUD_FILE_SUB0_INS4 Appb_RN_2D_Lpddr4_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk index dbf655737fd..a078c28d146 100644 --- a/src/soc/amd/common/Makefile.mk +++ b/src/soc/amd/common/Makefile.mk @@ -51,11 +51,22 @@ amdfw_offset=$(call int-subtract, \ $(CONFIG_AMD_FWM_POSITION) \ $(call get_fmap_value,$(amdfw_region_start))) +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) add_bootblock = \ - $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ - $(CBFSTOOL_ADD_CMD_OPTIONS) + $(CBFSTOOL) $(1) write -r EFS -f $(obj)/amdfw.rom --fill-upward + +else +# Raw fmap section (e.g. AMDFW): cbfstool write. CBFS container: add as apu/amdfw +# (type amdfw) at $(amdfw_offset) within the CBFS region. +amdfw_bootblock_needs_raw_write = $(strip $(filter-out $(subst $(comma),$(spc),$(CBFS_REGIONS)),\ + $(subst $(comma),$(spc),$(strip $(call regions-for-file,apu/amdfw))))) +add_bootblock = $(if $(amdfw_bootblock_needs_raw_write),\ + $(CBFSTOOL) $(1) write -u -r $(call regions-for-file,apu/amdfw) -i 0 -f $(2),\ + $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ + $(CBFSTOOL_ADD_CMD_OPTIONS)) +endif # ifeq ($(CONFIG_PSP_AB_RECOVERY),y) endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) ifeq ($(CONFIG_VBOOT_GSCVD),y) diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig index bc2dddc1f9f..645e3dd4afb 100644 --- a/src/soc/amd/common/block/acp/Kconfig +++ b/src/soc/amd/common/block/acp/Kconfig @@ -11,3 +11,17 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2 help Select this option to perform Audio Co-Processor(ACP) configuration. Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs. + +config SOC_AMD_ACP_KEEP_RUNNING_IN_S3 + bool + depends on SOC_AMD_COMMON_BLOCK_ACP_GEN1 || SOC_AMD_COMMON_BLOCK_ACP_GEN2 + help + Enables AMD Audio Co-Processor (ACP) to remain operational in ACPI + S3 (sleep) state for continued audio processing support. + +config SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX + bool + depends on SOC_AMD_COMMON_BLOCK_ACP_GEN1 || SOC_AMD_COMMON_BLOCK_ACP_GEN2 + help + Enables AMD Audio Co-Processor (ACP) to remain operational in ACPI + S0ix (sleep) state for continued audio processing support. diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c index 836d17b052a..06f63e0fdcb 100644 --- a/src/soc/amd/common/block/acp/acp.c +++ b/src/soc/amd/common/block/acp/acp.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "acp_def.h" diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 44ea1eb8446..fbb88747aca 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -135,3 +135,8 @@ config SOC_AMD_COMMON_BLOCK_UCODE bool help Builds in support for loading uCode. + +config SOC_AMD_COMMON_BLOCK_ENABLE_CACHE_ON_RESUME + bool + help + Enable the Cache on a S3 resume. diff --git a/src/soc/amd/common/block/cpu/cpu.c b/src/soc/amd/common/block/cpu/cpu.c index 13c98b1875a..0d240eddcb1 100644 --- a/src/soc/amd/common/block/cpu/cpu.c +++ b/src/soc/amd/common/block/cpu/cpu.c @@ -15,6 +15,12 @@ int get_cpu_count(void) return 1 + (cpuid_ecx(0x80000008) & 0xff); } +int cpu_node_id(void) +{ + return ((cpuid_ecx(CPUID_ECX_NODE_ID) & CPUID_ECX_NODE_ID_MASK)) + >> CPUID_ECX_NODE_ID_SHIFT; +} + unsigned int get_threads_per_core(void) { return 1 + ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c index 9c90501e000..3236889dbdd 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common.c +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "mca_common_defs.h" @@ -11,8 +12,12 @@ static void mca_check_all_banks(void) struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); - if (!mca_has_expected_bank_count()) - printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + /* + * Only the BSP has access to non CPU (Cache, UMC, ..) MCA banks. + * APs can only access their own CPU MCA banks. + */ + if (boot_cpu() && !mca_has_expected_bank_count()) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks %d!\n", mca_get_bank_count()); if (mca_skip_check()) return; diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index ad4f67e47de..b5cdd8987cc 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -6,6 +6,45 @@ #include #include #include "mca_common_defs.h" +#include "mcax.h" + +union mca_bank_ipid { + struct { + u64 instance_id:32; /* instance ID of this IP */ + u64 hardware_id:12; /* hardware ID of the IP associated with MCA bank */ + u64 instance_id_hi:4; /* High value of instance ID */ + u64 mca_type:16; /* McaType of MCA bank with this IP */ + }; + u64 raw; +}; + +#define MCA_UMC_ID (0x096) + +/* Returns the HardwareID from MSR MCAX_IPID. */ +u16 mcax_bank_hardware_id(unsigned int bank) +{ + union mca_bank_ipid ipid; + ipid.raw = rdmsr(MCAX_IPID_MSR(bank)).raw; + return ipid.hardware_id; +} + +/* Returns the InstanceID from MSR MCAX_IPID. */ +u32 mcax_bank_instance_id(unsigned int bank) +{ + union mca_bank_ipid ipid; + ipid.raw = rdmsr(MCAX_IPID_MSR(bank)).raw; + /* Returns a package unique ID to identify the MCA source. + * Since it does not account for 'instance_id_hi', the ID might not + * be unique across all nodes and cannot be used as global identifier. + */ + return ipid.instance_id; +} + +/* Return true when the bank is for the UMC */ +bool mcax_bank_is_umc(unsigned int bank) +{ + return mcax_bank_hardware_id(bank) == MCA_UMC_ID; +} /* The McaXEnable bit in the config registers of the available MCAX banks is already set by the FSP, so no need to set it here again. */ @@ -60,3 +99,30 @@ void mca_print_error(unsigned int bank) msr = rdmsr(MCA_CTL_MASK_MSR(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } + + +/** + * Fill in FRU text if from MSR SYND1 and SYND2 if supported. + * @param bank The MCA bank to check + * @param fru_text The array to fill + * + * @return CB_SUCCESS on success + */ +enum cb_err amd_mca_fill_fru_from_synd(const int bank, char fru_text[17]) +{ + msr_t msr = rdmsr(MCAX_CONFIG_MSR(bank)); + + if (!(msr.lo & MCAX_CONFIG_MSR_FRU_TEXT)) + return CB_ERR_NOT_IMPLEMENTED; + + msr = rdmsr(MCAX_SYND1_MSR(bank)); + if (!msr.raw) + return CB_ERR; + + strncpy(&fru_text[0], (char *)&msr.raw, sizeof(msr_t)); + msr = rdmsr(MCAX_SYND2_MSR(bank)); + strncpy(&fru_text[8], (char *)&msr.raw, sizeof(msr_t)); + fru_text[16] = 0; + + return CB_SUCCESS; +} diff --git a/src/soc/amd/common/block/cpu/mca/mcax.h b/src/soc/amd/common/block/cpu/mca/mcax.h new file mode 100644 index 00000000000..74a95192751 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mcax.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_MCAX_DEF_H +#define AMD_BLOCK_MCAX_DEF_H + +#include + +enum cb_err amd_mca_fill_fru_from_synd(const int bank, char fru_text[17]); +u16 mcax_bank_hardware_id(unsigned int bank); +u32 mcax_bank_instance_id(unsigned int bank); +bool mcax_bank_is_umc(unsigned int bank); + +#endif /* AMD_BLOCK_MCAX_DEF_H */ diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c index 80ee534f453..8527e8caf19 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -38,13 +38,21 @@ static inline size_t mca_report_size_reqd(int used_registers_per_bank) return size; } -/* Convert an error reported by an MCA bank into BERT information to be reported - * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, +static void fill_generic_entry(acpi_hest_generic_data_v300_t *entry, + struct mca_bank_status *mci) +{ + entry->validation_bits |= ACPI_GENERROR_VALID_FRUID_TEXT; + entry->flags |= CPER_SEC_PRIMARY; + strcpy((char *)entry->fru_text, "ProcessorError"); +} + +/* + * The ACPI driver doesn't recognize/parse the IA32/X64 structure, * which is the best method to report MSR context. As a result, add two * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. */ -void build_bert_mca_error(struct mca_bank_status *mci) +static void bert_log_proc_error(struct mca_bank_status *mci) { acpi_generic_error_status_t *status; acpi_hest_generic_data_v300_t *gen_entry; @@ -64,6 +72,9 @@ void build_bert_mca_error(struct mca_bank_status *mci) goto failed; gen_entry = acpi_hest_generic_data3(status); + + fill_generic_entry(gen_entry, mci); + gen_sec = section_of_acpientry(gen_sec, gen_entry); fill_generic_section(gen_sec, mci); @@ -92,3 +103,12 @@ void build_bert_mca_error(struct mca_bank_status *mci) /* We're here because of a hardware error, don't break something else */ printk(BIOS_ERR, "Not enough room in BERT region for Machine Check error\n"); } + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. + */ +void build_bert_mca_error(struct mca_bank_status *mci) +{ + /* Currently only processor MCAs are reported */ + bert_log_proc_error(mci); +} diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.mk b/src/soc/amd/common/block/cpu/noncar/Makefile.mk index 80072b529d0..88f5c6f58ce 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.mk +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.mk @@ -24,7 +24,7 @@ $(objcbfs)/bootblock_fixed_data.elf: $(objcbfs)/bootblock.elf @printf " OBJCOPY $(notdir $(@))\n" $(OBJCOPY_bootblock) --dump-section .data=$(objcbfs)/data.section $< cp $< $@ - $(OBJCOPY_bootblock) --set-section-flags .datacopy=load \ + $(OBJCOPY_bootblock) --set-section-flags .datacopy=load,alloc \ --set-section-flags .bss=noload --set-section-flags .data=noload $@ $(OBJCOPY_bootblock) --update-section .datacopy=$(objcbfs)/data.section $@ diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c index 419510ee6c2..eabbb78d2c4 100644 --- a/src/soc/amd/common/block/cpu/noncar/bootblock.c +++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -42,4 +43,17 @@ void bootblock_soc_init(void) } fch_early_init(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_ENABLE_CACHE_ON_RESUME) && acpi_is_wakeup_s3()) { + /* + * Disable TwCfgCombineCr0Cd + * FIXME: Unclear why this MSR is restored on S3 resume. + * + * Allows the BSP to use the cache and thus speeds up booting until MPinit + * enables the caches on the other cores. + */ + msr_t msr = rdmsr(BU_CFG_MSR); + msr.raw &= ~COMBINE_CR0_CD; + wrmsr(BU_CFG_MSR, msr); + } } diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index 8c5fbc30e85..887ea68510e 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -64,6 +65,18 @@ void early_cache_setup(void) var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); + /* ROM3 is only accessible in x86_64. Only required when ROM2 doesn't cover whole flash. */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) { + size_t rom3_size = 0; + uint64_t rom3_start = lpc_get_rom3_region(&rom3_size); + + if (rom3_start && rom3_size) { + /* The flash is now no longer cacheable. Reset to WP for performance. */ + rom3_size = 1 << log2_ceil(rom3_size); + var_mtrr_set(&mtrr_ctx.ctx, rom3_start, rom3_size, MTRR_TYPE_WRPROT); + } + } + commit_mtrr_setup(&mtrr_ctx.ctx); /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ diff --git a/src/soc/amd/common/block/cpu/noncar/mpinit.c b/src/soc/amd/common/block/cpu/noncar/mpinit.c index 002c50537f8..276a09b1f9d 100644 --- a/src/soc/amd/common/block/cpu/noncar/mpinit.c +++ b/src/soc/amd/common/block/cpu/noncar/mpinit.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include #include #include @@ -20,6 +22,20 @@ void mp_init_cpus(struct bus *cpu_bus) mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) { + size_t rom3_size = 0; + uint64_t rom3_start = lpc_get_rom3_region(&rom3_size); + + if (rom3_start && rom3_size) { + /* The flash is now no longer cacheable. Reset to WP for performance. */ + rom3_size = 1 << log2_ceil(rom3_size); + mtrr_use_temp_range(rom3_start, rom3_size, MTRR_TYPE_WRPROT); + } + } + + if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)) + psp_rom_armor_init(false); /* FIXME: No capsule updates for now */ + /* SMMINFO only needs to be set up when booting from S5 */ if (!acpi_is_wakeup_s3()) apm_control(APM_CNT_SMMINFO); diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 3dc3dd30f07..d79a6e9221c 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -45,9 +45,8 @@ bootblock_pre_c_entry: /* Copy .data section content */ #include - /* Align the stack and keep aligned for call to bootblock_c_entry() */ + /* Align the stack for call to bootblock_c_entry(). */ and $0xfffffff0, %esp - sub $8, %esp #if ENV_X86_64 movd %mm2, %rdi @@ -55,6 +54,9 @@ bootblock_pre_c_entry: movd %mm1, %rsi or %rsi, %rdi #else + /* Keep stack aligned by accounting for the next to push instructions */ + sub $8, %esp + movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax diff --git a/src/soc/amd/common/block/cpu/smm/smi_apmc.c b/src/soc/amd/common/block/cpu/smm/smi_apmc.c index 7c98405e10c..464239456e0 100644 --- a/src/soc/amd/common/block/cpu/smm/smi_apmc.c +++ b/src/soc/amd/common/block/cpu/smm/smi_apmc.c @@ -91,6 +91,25 @@ void handle_smi_store(void) io_smi->rax = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx); } +static void handle_smi_rom_armor(void) +{ + u8 sub_command; + amd64_smm_state_save_area_t *io_smi; + u32 reg_ebx; + + io_smi = find_save_state(APM_CNT_ROM_ARMOR); + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* ROM Armor handler */ + io_smi->rax = rom_armor_exec(sub_command, (void *)(uintptr_t)reg_ebx); +} + void fch_apmc_smi_handler(void) { const uint8_t cmd = apm_get_apmc(); @@ -111,6 +130,10 @@ void fch_apmc_smi_handler(void) if (CONFIG(SMMSTORE)) handle_smi_store(); break; + case APM_CNT_ROM_ARMOR: + if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)) + handle_smi_rom_armor(); + break; case APM_CNT_SMMINFO: psp_notify_smm(); break; diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 7a6e615df3c..94254a06864 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 12a7bba0e52..ee42c99f19f 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include #include #include #include @@ -212,3 +216,14 @@ void amd_pci_domain_read_resources(struct device *domain) read_soc_memmap_resources(domain, &idx); } } + +void amd_pci_domain_fill_ssdt(const struct device *domain) +{ + pci_domain_fill_ssdt(domain); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT)) { + acpigen_write_scope(acpi_device_path(domain)); + acpigen_write_pci_root_PRT(); + acpigen_pop_len(); + } +} diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 369fd85192e..89b4b1f6ddb 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -41,10 +41,10 @@ struct atif_brightness_output { uint16_t size; /* Size of this object, including size field. */ uint16_t flags; /* Currently all reserved. */ uint8_t error_code; - /* default brightness fields currently ignored by Linux driver. */ + /* Linux uses these values as the initial backlight brightness. */ uint8_t default_brightness_ac; /* Percentage brightness when connected to AC. */ uint8_t default_brightness_dc; /* Percentage brightness when connected to DC. */ - /* The following 2 fields are the only ones honored by Linux driver currently. */ + /* Linux uses these values to scale the backlight range. */ uint8_t min_input_signal_level; /* 0-255 corresponding to 0% */ uint8_t max_input_signal_level; /* 0-255 corresponding to 100% */ /* Array of data points consisting of: @@ -69,6 +69,8 @@ static void generate_atif(const struct device *dev) struct atif_brightness_output brightness_out = { .size = sizeof(brightness_out), .error_code = ATIF_QBTC_ERROR_CODE_SUCCESS, + .default_brightness_ac = 90, + .default_brightness_dc = 60, .min_input_signal_level = 0, .max_input_signal_level = 255, }; diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 8bc0abd9f44..437b56d7f93 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -4,7 +4,6 @@ #include #include #include -#include #include static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index db8b70463c6..90a1ec0695e 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -67,9 +67,12 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries); const struct pci_routing_info *get_pci_routing_info(unsigned int devfn); +unsigned int soc_get_gsi_base(const struct device *dev); + unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); void acpigen_write_pci_GNB_PRT(const struct device *dev); void acpigen_write_pci_FCH_PRT(const struct device *dev); +void acpigen_write_pci_root_PRT(void); #endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h b/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h new file mode 100644 index 00000000000..0447fefca77 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_BACKUP_BOOT_DEVICE_H +#define AMD_BLOCK_BACKUP_BOOT_DEVICE_H + +#include +#include + +enum boot_device { + FLASH_PRIMARY, // primary SPI flash + FLASH_BACKUP, // backup SPI flash +}; + +/* Retrieve the SPI CS index of the backup boot device. */ +int backup_boot_device_spi_cs(void); + +const struct region_device *backup_boot_device_rw(void); +const struct spi_flash *backup_boot_device_spi_flash(void); +int backup_boot_device_rw_subregion(const struct region *sub, + struct region_device *subrd); +int backup_boot_device_sync_subregion(const struct region *sub, + const bool direction_prim_to_sec); + +#endif diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index ce0b2da8163..115fa3f8d49 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -11,6 +11,7 @@ void early_cache_setup(void); int get_cpu_count(void); unsigned int get_threads_per_core(void); +int cpu_node_id(void); void set_cstate_io_addr(void); void write_resume_eip(void); diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index fbed0b22a0a..54ad0b95e9d 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -54,5 +54,6 @@ void data_fabric_get_mmio_base_size(unsigned int reg, resource_t *mmio_base, /* Inform the resource allocator about the usable IO and MMIO regions and PCI bus numbers */ void amd_pci_domain_read_resources(struct device *domain); void amd_pci_domain_scan_bus(struct device *domain); +void amd_pci_domain_fill_ssdt(const struct device *domain); #endif /* AMD_BLOCK_DATA_FABRIC_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/msr_zen.h b/src/soc/amd/common/block/include/amdblocks/msr_zen.h index cde4d7bddad..b2fe911f061 100644 --- a/src/soc/amd/common/block/include/amdblocks/msr_zen.h +++ b/src/soc/amd/common/block/include/amdblocks/msr_zen.h @@ -33,6 +33,7 @@ #define MCAX_ADDR_MSR(bank) MCAX_MSR(bank, MCAX_ADDR_OFFSET) #define MCAX_MISC0_MSR(bank) MCAX_MSR(bank, MCAX_MISC0_OFFSET) #define MCAX_CONFIG_MSR(bank) MCAX_MSR(bank, MCAX_CONFIG_OFFSET) +#define MCAX_CONFIG_MSR_FRU_TEXT BIT(9) #define MCAX_IPID_MSR(bank) MCAX_MSR(bank, MCAX_IPID_OFFSET) #define MCAX_SYND_MSR(bank) MCAX_MSR(bank, MCAX_SYND_OFFSET) #define MCAX_DESTAT_MSR(bank) MCAX_MSR(bank, MCAX_DESTAT_OFFSET) diff --git a/src/soc/amd/common/block/include/amdblocks/pci_devs.h b/src/soc/amd/common/block/include/amdblocks/pci_devs.h index 074bdd804b8..63877a5c041 100644 --- a/src/soc/amd/common/block/include/amdblocks/pci_devs.h +++ b/src/soc/amd/common/block/include/amdblocks/pci_devs.h @@ -3,7 +3,6 @@ #ifndef AMD_BLOCK_PCI_DEVS_H #define AMD_BLOCK_PCI_DEVS_H -#include #if !defined(__SIMPLE_DEVICE__) #include diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 40197396fe1..1e283dc0a0b 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_PSP_H #define AMD_BLOCK_PSP_H +#include #include #include @@ -95,5 +96,39 @@ bool psp_ftpm_is_active(void); void psp_ftpm_needs_recovery(bool *psp_rpmc_nvram, bool *psp_nvram, bool *psp_dir); +#if ENV_RAMSTAGE || ENV_SMM +bool psp_get_hsti_state_rom_armor_enforced(void); +#else +/* ROM Armor might get activated after SMM has been set up. It's safe to return false here. */ +static inline bool psp_get_hsti_state_rom_armor_enforced(void) { return false; } +#endif + +/* Region device accessing the ROM through PSP mailbox */ +extern struct region_device rom_armor_smm_rw; + +/** + * psp_rom_armor_init - Initialize PSP ROM Armor + * + * Must be called from RAMSTAGE to enable ROM Armor. + * Calls into SMM to set up the ROM Armor command buffer and to prepare the + * PSP mailbox communication. Enables the ROM Armor feature on the PSP and + * disables the SPIBAR. + * After this call access to the SPI flash must use PSP mailbox communication + * in SMM. PSP will only grant access to regions marked as writable. + * + * @param allow_capsule_update Whether to allow capsule updates + */ +void psp_rom_armor_init(bool allow_capsule_update); + +/* SMM handler for ROM Armor operations - called from APMC handler */ +uint32_t rom_armor_exec(uint8_t command, void *param); + +/* Region device accessing the ROM through APMC SMI handler */ +extern const struct region_device rom_armor_apm_call_rw; + +/* psp_ab_recovery_toggle_bootpartition - Toggle active partition on next boot. + * @return 0 on success + */ +int psp_ab_recovery_toggle_bootpartition(void); #endif /* AMD_BLOCK_PSP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index d0b9b016d2e..e908c53f707 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -10,17 +10,6 @@ #define EMBEDDED_FW_SIGNATURE 0x55aa55aa -#if CONFIG(SOC_AMD_STONEYRIDGE) - #define SPI_MODE_FIELD spi_readmode_f15_mod_60_6f - #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f -#elif CONFIG(SOC_AMD_PICASSO) - #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f - #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f -#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO) - #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f - #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f -#endif - struct second_gen_efs { /* todo: expand for Server products */ uint32_t gen:1; /* Client products only use bit 0 */ uint32_t reserved:31; @@ -41,7 +30,7 @@ struct embedded_firmware { uint32_t bios2_entry; struct second_gen_efs efs_gen; uint32_t bios3_entry; - uint32_t reserved_2Ch; + uint32_t psp_bak_directory; uint32_t promontory_fw_ptr; uint32_t lp_promontory_fw_ptr; uint32_t reserved_38h; diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index bc395d75c7d..db2984a413d 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -130,9 +130,12 @@ uintptr_t spi_get_bar(void); uint8_t spi_read8(uint8_t reg); uint16_t spi_read16(uint8_t reg); uint32_t spi_read32(uint8_t reg); +void spi_read_block(uint8_t reg, uint8_t *dest, size_t len); + void spi_write8(uint8_t reg, uint8_t val); void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); +void spi_write_block(uint8_t reg, const uint8_t *src, size_t len); /* Returns the active SPI ROM remapping */ uint8_t fch_spi_rom_remapping(void); diff --git a/src/soc/amd/common/block/include/amdblocks/xhci.h b/src/soc/amd/common/block/include/amdblocks/xhci.h index 6d1bc260a44..8eb5f9bd4f8 100644 --- a/src/soc/amd/common/block/include/amdblocks/xhci.h +++ b/src/soc/amd/common/block/include/amdblocks/xhci.h @@ -5,7 +5,6 @@ #include #include -#include #include #include diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 9ff9b0ead72..5e7ba1e75bb 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -32,7 +32,7 @@ static ssize_t spi_dma_readat_mmap(const struct region_device *rd, void *b, size { const struct mem_region_device *mdev; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); memcpy(b, &mdev->base[offset], size); @@ -213,7 +213,7 @@ static void *spi_dma_mmap(const struct region_device *rd, size_t offset, size_t const struct mem_region_device *mdev; void *mapping; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); if (!CONFIG_CBFS_CACHE_SIZE) return &mdev->base[offset]; diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index f9d2908176e..caba691f4ab 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -18,3 +18,13 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER depends on SOC_AMD_COMMON_BLOCK_PCI help Select this option to use AMD common PCIe GPP driver. + +config SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT + bool + depends on SOC_AMD_COMMON_BLOCK_PCI + depends on HAVE_ACPI_TABLES + help + After pci_domain_fill_ssdt(), emit Method(_PRT) on the PCI host bridge + scope for root-bus devices (e.g. PCIe root ports) using + get_pci_routing_table(). Needed when the SoC ACPI sources do not supply + PCI0._PRT. diff --git a/src/soc/amd/common/block/pci/acpi_prt.c b/src/soc/amd/common/block/pci/acpi_prt.c index f748024de9b..ee7340ebdd1 100644 --- a/src/soc/amd/common/block/pci/acpi_prt.c +++ b/src/soc/amd/common/block/pci/acpi_prt.c @@ -11,7 +11,13 @@ #define FCH_IOAPIC_INTERRUPTS 24 #define GNB_GSI_BASE FCH_IOAPIC_INTERRUPTS -static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) +__weak unsigned int soc_get_gsi_base(const struct device *dev) +{ + return GNB_GSI_BASE; +} + +static void acpigen_write_PRT_GSI(const struct device *dev, + const struct pci_routing_info *routing_info) { unsigned int irq; @@ -22,7 +28,7 @@ static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) acpigen_write_PRT_GSI_entry( 0, /* There is only one device attached to the bridge */ i, /* pin */ - GNB_GSI_BASE + irq); + soc_get_gsi_base(dev) + irq); } acpigen_pop_len(); /* Package - APIC Routing */ } @@ -143,7 +149,7 @@ void acpigen_write_pci_GNB_PRT(const struct device *dev) /* Return (Package{...}) */ acpigen_emit_byte(RETURN_OP); - acpigen_write_PRT_GSI(routing_info); + acpigen_write_PRT_GSI(dev, routing_info); /* Else */ acpigen_write_else(); @@ -157,6 +163,147 @@ void acpigen_write_pci_GNB_PRT(const struct device *dev) acpigen_pop_len(); /* Method */ } +/* Counts table rows with a valid bridge_irq; used only for Package() element count. */ +static size_t count_pci_root_prt_entries(const struct pci_routing_info *routing_table, + size_t routing_table_entries) +{ + size_t entries = 0; + + for (size_t i = 0; i < routing_table_entries; ++i) { + if (routing_table[i].bridge_irq != UINT8_MAX) + entries++; + } + + return entries; +} + +/* + * Return payload for the PICM branch: one Package per root-port devfn using GSIs: + * Package (0xNN) // NN = number of root ports + * { + * Package (0x04) + * { + * 0xDDDDFFFF, + * 0xPP, + * 0x00, + * 0x000000GG + * }, + * ... + * } + */ +static void acpigen_write_root_PRT_GSI(const struct pci_routing_info *routing_table, + size_t routing_table_entries, size_t prt_entries) +{ + acpigen_write_package(prt_entries); /* Package - APIC Routing */ + for (size_t i = 0; i < routing_table_entries; ++i) { + if (routing_table[i].bridge_irq == UINT8_MAX) + continue; + + /* + * The HOB's bridge_irq/map byte is not an OS-visible APIC GSI here. + * Route the root port's own INTx through its GNB group/swizzle instead. + */ + acpigen_write_PRT_GSI_entry_devfn(routing_table[i].devfn, + 0, /* root port interrupt pin A */ + GNB_GSI_BASE + pci_calculate_irq(&routing_table[i], 0)); + } + acpigen_pop_len(); /* Package - APIC Routing */ +} + +/* + * Return payload for the PIC branch: one Package per root-port devfn using link objects: + * Package (0xNN) + * { + * Package (0x04) + * { + * 0xDDDDFFFF, + * 0xPP, + * \_SB.INTx, + * 0x00000000 + * }, + * ... + * } + */ +static void acpigen_write_root_PRT_PIC(const struct pci_routing_info *routing_table, + size_t routing_table_entries, size_t prt_entries) +{ + char link_template[] = "\\_SB.INTX"; + unsigned int irq; + + acpigen_write_package(prt_entries); /* Package - PIC Routing */ + for (size_t i = 0; i < routing_table_entries; ++i) { + if (routing_table[i].bridge_irq == UINT8_MAX) + continue; + + irq = pci_calculate_irq(&routing_table[i], 0); + link_template[8] = 'A' + (irq % 8); + acpigen_write_PRT_source_entry_devfn(routing_table[i].devfn, + 0, /* root port interrupt pin A */ + link_template, + 0); + } + acpigen_pop_len(); /* Package - PIC Routing */ +} + +/* + * Host-bridge _PRT for root-bus devices (per devfn from the routing table) + * + * Method (_PRT, 0, NotSerialized) + * { + * If (PICM) + * { + * Return (Package (0xNN) + * { + * Package (0x04) { 0xDDDDFFFF, 0xPP, 0x00, 0x000000GG }, + * ... + * }) + * } + * Else + * { + * Return (Package (0xNN) + * { + * Package (0x04) { 0xDDDDFFFF, 0xPP, \_SB.INTx, 0x00000000 }, + * ... + * }) + * } + * } + */ +void acpigen_write_pci_root_PRT(void) +{ + const struct pci_routing_info *routing_table; + size_t routing_table_entries = 0; + size_t prt_entries; + + routing_table = get_pci_routing_table(&routing_table_entries); + if (!routing_table || !routing_table_entries) + return; + + prt_entries = count_pci_root_prt_entries(routing_table, routing_table_entries); + if (!prt_entries) + return; + + acpigen_write_method("_PRT", 0); + + /* If (PICM) */ + acpigen_write_if(); + acpigen_emit_namestring("PICM"); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_root_PRT_GSI(routing_table, routing_table_entries, prt_entries); + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_root_PRT_PIC(routing_table, routing_table_entries, prt_entries); + + acpigen_pop_len(); /* End Else */ + + acpigen_pop_len(); /* Method */ +} + /* * This method writes a PCI _PRT table that uses the FCH IO-APIC / PIC : * Name (_PRT, Package (0x04) diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 17853faccfd..bcc22e06239 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -20,6 +20,23 @@ config SOC_AMD_COMMON_BLOCK_PSP_GEN2 help Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. +config SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + bool + depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_SMN + help + Allow PSP mailbox access in bootblock and romstage using the SMN + access method to the mailbox registers. + +config PSP_AB_RECOVERY + bool "Use A/B Recovery scheme" + depends on !VBOOT && !CHROMEOS + select CBFS_VERIFICATION + select SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + default n + help + Enable the PSP A/B Recovery mechanism + config SOC_AMD_PSP_SELECTABLE_SMU_FW bool help diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index 9929d72998b..30416265793 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) -romstage-y += psp.c ramstage-y += psp.c smm-y += psp.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi.c @@ -11,12 +10,13 @@ smm-y += psp_smm.c bootblock-y += psp_efs.c verstage-y += psp_efs.c -all-y += ftpm.c +ramstage-$(CONFIG_AMD_CRB_FTPM) += ftpm.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) +romstage-y += psp.c romstage-y += psp_gen1.c ramstage-y += psp_gen1.c @@ -27,12 +27,24 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) +all_x86-$(CONFIG_PSP_AB_RECOVERY) += psp_ab_recovery.c + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS),y) +bootblock-y += psp.c +bootblock-y += psp_gen2.c +bootblock-y += psp_gen2_smn.c +romstage-y += psp.c romstage-y += psp_gen2.c +romstage-y += psp_gen2_smn.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + ramstage-y += psp_gen2.c +ramstage-y += psp_gen2_mmio.c ramstage-$(CONFIG_PSP_PLATFORM_SECURE_BOOT) += psb.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c smm-y += psp_gen2.c +smm-y += psp_gen2_mmio.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen2.c smm-y += psp_smm_gen2.c @@ -40,3 +52,6 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_RPMC) += rpmc.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3) += psp_rom_armor_smm.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3) += psp_rom_armor.c diff --git a/src/soc/amd/common/block/psp/ftpm.c b/src/soc/amd/common/block/psp/ftpm.c index 7e50365f6df..3e657080e4d 100644 --- a/src/soc/amd/common/block/psp/ftpm.c +++ b/src/soc/amd/common/block/psp/ftpm.c @@ -8,12 +8,12 @@ uintptr_t psp_ftpm_base_address(void) { - const uintptr_t psp_base = get_psp_mmio_base(); - if (!psp_base) + const uint64_t base = psp_get_base(); + if (!base) return 0; /* TPM MMIO space starts 0xA0 bytes before MBOX */ - return psp_base + CONFIG_PSPV2_MBOX_CMD_OFFSET - 0xA0; + return base + CONFIG_PSPV2_MBOX_CMD_OFFSET - 0xA0; } /* diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 5e497a2cad5..30016424c03 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -84,13 +84,13 @@ static const char *fuse_status_to_string(uint32_t status) static enum cb_err get_psb_status(uint32_t *psb_status_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = psp_get_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *psb_status_value = read32p(psp_mmio | PSB_STATUS_OFFSET); + *psb_status_value = psp_read32(base, PSB_STATUS_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 98eb0f9e84e..b8e908a928d 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -101,6 +101,36 @@ enum cb_err psp_get_hsti_state(uint32_t *state) return CB_SUCCESS; } +/* + * Returns true if ROM Armor is enforced, that is after PSP command + * MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE has been executed, false otherwise. + * + * When ROM Armor is enforced the result will be cached. + */ +#if ENV_RAMSTAGE || ENV_SMM +bool psp_get_hsti_state_rom_armor_enforced(void) +{ + uint32_t hsti_state; + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)) + return false; + + static bool enforced; + if (enforced) + return true; /* ROM Armor already enforced, no need to check again */ + + if (psp_get_hsti_state(&hsti_state) != CB_SUCCESS) { + printk(BIOS_EMERG, "PSP: Failed to get HSTI state\n"); + return false; + } + enforced = hsti_state & HSTI_STATE_ROM_ARMOR_ENFORCED; + if (enforced) + printk(BIOS_INFO, "PSP: ROM Armor enforced\n"); + + return enforced; +} +#endif + /* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer diff --git a/src/soc/amd/common/block/psp/psp_ab_recovery.c b/src/soc/amd/common/block/psp/psp_ab_recovery.c new file mode 100644 index 00000000000..74ff1461909 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_ab_recovery.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "psp_def.h" + +int psp_ab_recovery_set_bootpartition(const uint32_t partition) +{ + struct mbox_cmd_boot_partition_buffer boot_partition_cmd = { + .header = { + .size = sizeof(boot_partition_cmd) + }, + .boot_partition = partition, + }; + int cmd_status; + + cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_BOOTPARTITION, &boot_partition_cmd); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &boot_partition_cmd.header); + + return cmd_status; +} + +int psp_ab_recovery_get_bootpartition(void) +{ + struct mbox_cmd_boot_partition_buffer boot_partition_cmd = { + .header = { + .size = sizeof(boot_partition_cmd) + }, + .boot_partition = 0xFFFFFFFF, + }; + int cmd_status; + + cmd_status = send_psp_command(MBOX_BIOS_CMD_GET_BOOTPARTITION, &boot_partition_cmd); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &boot_partition_cmd.header); + + if (cmd_status < 0) + return cmd_status; + + return boot_partition_cmd.boot_partition; +} + +int psp_ab_recovery_toggle_bootpartition(void) +{ + int cmd_status = psp_ab_recovery_get_bootpartition(); + if (cmd_status < 0) + return cmd_status; + + return psp_ab_recovery_set_bootpartition(cmd_status ? 0 : 1); +} + +/* + * Select the FMAP region to continue booting from, depending on the state of + * recovery mode as reported by PSP. + */ +const char *cbfs_fmap_region_hint(void) +{ + if (psp_ab_recovery_get_bootpartition() == 1) + return "COREBOOT_B"; + else + return "COREBOOT"; +} diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 9d60c264bf7..8f516c200af 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -27,11 +27,16 @@ #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 #define MBOX_BIOS_CMD_HSTI_QUERY 0x14 +#define HSTI_STATE_ROM_ARMOR_ENFORCED BIT(11) #define MBOX_BIOS_CMD_PSB_AUTO_FUSING 0x21 +#define MBOX_BIOS_CMD_SET_BOOTPARTITION 0x26 +#define MBOX_BIOS_CMD_GET_BOOTPARTITION 0x36 #define MBOX_BIOS_CMD_PSP_CAPS_QUERY 0x27 #define MBOX_BIOS_CMD_SET_SPL_FUSE 0x2d #define MBOX_BIOS_CMD_SET_RPMC_ADDRESS 0x39 #define MBOX_BIOS_CMD_QUERY_SPL_FUSE 0x47 +#define MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE 0x50 +#define MBOX_BIOS_CMD_ARMOR_SPI_TRANSACTION 0x51 #define MBOX_BIOS_CMD_I2C_TPM_ARBITRATION 0x64 #define MBOX_BIOS_CMD_ABORT 0xfe @@ -114,6 +119,17 @@ struct mbox_cmd_late_spl_buffer { uint32_t spl_value; } __packed __aligned(32); +/* + * MBOX_BIOS_CMD_SET_BOOTPARTITION, + * MBOX_BIOS_CMD_GET_BOOTPARTITION + * + * boot_partition is typically 0 or 1. + */ +struct mbox_cmd_boot_partition_buffer { + struct mbox_buffer_header header; + uint32_t boot_partition; +} __packed __aligned(32); + struct dtpm_config { uint32_t gpio; } __packed; @@ -132,6 +148,32 @@ struct mbox_cmd_dtpm_config_buffer { struct dtpm_config config; } __packed __aligned(32); +/* MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE */ +struct mbox_rom_armor_enforce_buffer { + struct mbox_buffer_header header; + uint32_t flash_size; /* Returned by PSP: SPI flash size in bytes */ + uint32_t capsule_update; /* 1 for capsule update/recovery mode, 0 otherwise */ +} __packed __aligned(32); + +enum mbox_rom_armor_transaction { + RA_READ = 1, + RA_WRITE = 2, + RA_ERASE = 3, +}; + +struct mbox_rom_armor_flash_command { + enum mbox_rom_armor_transaction transaction; + uint64_t buffer_ptr; /* Pointer to data buffer. Must not be NULL. */ + uint32_t offset; /* SPI flash offset */ + uint32_t size; /* Transfer size for all operations */ + uint32_t read_back; /* Whether to read back data after write for validation */ +} __packed; + +struct mbox_rom_armor_flash_command_buffer { + struct mbox_buffer_header header; + struct mbox_rom_armor_flash_command cmd; +} __packed __aligned(32); + #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ @@ -161,7 +203,17 @@ enum mbox_p2c_status { MBOX_PSP_SPI_BUSY = 0x0b, }; -uintptr_t get_psp_mmio_base(void); +/* + * PSP register base retrieval and register access functions used by the PSP v2 + * code. Those are used to do the register access depending on the stage either + * via SMN or via MMIO, sinc ethe MMIO access method is only available later in + * boot while the SMN access will already work before that, but has a bit more + * overhead compared to MMIO. + */ +uint64_t psp_get_base(void); +uint32_t psp_read32(uint64_t base, uint32_t offset); +void psp_write32(uint64_t base, uint32_t offset, uint32_t data); +void psp_write64(uint64_t base, uint32_t offset, uint64_t data); void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); @@ -178,4 +230,52 @@ void enable_psp_smi(void); void psp_set_smm_flag(void); void psp_clear_smm_flag(void); +/* psp_ab_recovery_set_bootpartition - Set active partition on next boot. + * @param partition: Active partition on next boot. 0: A, 1: B. + * @return 0 on success + */ +int psp_ab_recovery_set_bootpartition(const uint32_t partition); + +/* psp_ab_recovery_get_bootpartition - Get active partition on next boot. + * @return negative on failure. 0 if A is active boot partition, 1 if B is active + * boot partition. + */ +int psp_ab_recovery_get_bootpartition(void); + +struct mbox_rom_armor_flash_command; +/* + * psp_rom_armor_spi_transaction - Send PSP ROM Armor SPI transaction command to PSP firmware + * + * @param cmd_buf: Command buffer with SPI transaction to execute. + * + * On ROM Armor2: + * READ/WRITE/ERASE + * + * On ROM Armor3: + * WRITE/ERASE + * (READ is not supported on ROM Armor3 as flash contents can be read directly from MMIO) + * + * Communicates with PSP via mailbox to perform the requested SPI flash operation through ROM Armor. + * The PSP firmware will enforce the access based on the command parameters and the + * protection configuration in PSP firmware ('Writable' bit set on PSP directory entries) and + * BIOS directory types 0x6d (whitelisted flash regions) and return the result via the same command buffer. + * + * Returns 0 on success, negative error code on failure. + */ +int psp_rom_armor_spi_transaction(const struct mbox_rom_armor_flash_command *cmd_buf); + +/** + * psp_rom_armor_enter_smm_mode - Active PSP Rom Armor + * @param allow_capsule_update: Indicates if the system is in capsule update mode + * @param flash_size: Pointer to store the flash size retrieved from PSP firmware + * + * After this function is called, PSP Rom Armor will be active and protect + * the SPI flash according to the configuration in PSP firmware. This function + * also retrieves the flash size from PSP firmware and returns it via the + * flash_size output parameter. + * + * Returns: 0 on success, negative error code on failure + */ +int psp_rom_armor_enter_smm_mode(const bool allow_capsule_update, size_t *flash_size); + #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index fa69aea5548..42e00afad19 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -16,14 +16,22 @@ bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) return false; if (efs->signature == EMBEDDED_FW_SIGNATURE) { -#ifndef SPI_MODE_FIELD - printk(BIOS_ERR, "Unknown cpu in psp_efs.h\n"); - printk(BIOS_ERR, "SPI speed/mode not set.\n"); -#else - *mode = efs->SPI_MODE_FIELD; - *speed = efs->SPI_SPEED_FIELD; - ret = true; -#endif + if (CONFIG(SOC_AMD_STONEYRIDGE)) { + *mode = efs->spi_readmode_f15_mod_60_6f; + *speed = efs->fast_speed_new_f15_mod_60_6f; + ret = true; + } else if (CONFIG(SOC_AMD_PICASSO)) { + *mode = efs->spi_readmode_f17_mod_00_2f; + *speed = efs->spi_fastspeed_f17_mod_00_2f; + ret = true; + } else if (CONFIG(SOC_AMD_CEZANNE) || CONFIG(SOC_AMD_MENDOCINO)) { + *mode = efs->spi_readmode_f17_mod_30_3f; + *speed = efs->spi_fastspeed_f17_mod_30_3f; + ret = true; + } else { + printk(BIOS_ERR, "Unknown cpu in psp_efs.h\n"); + printk(BIOS_ERR, "SPI speed/mode not set.\n"); + } } rdev_munmap(boot_device_ro(), efs); return ret; diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index b3cb6ef8ed8..4282f80b93c 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -1,86 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include #include -#include -#include +#include #include +#include +#include +#include #include "psp_def.h" #define PSP_MAILBOX_COMMAND_OFFSET CONFIG_PSPV2_MBOX_CMD_OFFSET /* 4 bytes */ #define PSP_MAILBOX_BUFFER_OFFSET (CONFIG_PSPV2_MBOX_CMD_OFFSET + 4) /* 8 bytes */ -#define IOHC_MISC_PSP_MMIO_REG 0x2e0 - -static uint64_t get_psp_mmio_mask(void) -{ - const struct non_pci_mmio_reg *mmio_regs; - size_t reg_count; - mmio_regs = get_iohc_non_pci_mmio_regs(®_count); - - for (size_t i = 0; i < reg_count; i++) { - if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) - return mmio_regs[i].mask; - } - - printk(BIOS_ERR, "No PSP MMIO register description found.\n"); - return 0; -} - -#define PSP_MMIO_LOCK BIT(8) - -/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, - so we have to read this from the hardware registers */ -uintptr_t get_psp_mmio_base(void) -{ - static uintptr_t psp_mmio_base; - const struct domain_iohc_info *iohc; - size_t iohc_count; - - if (psp_mmio_base) - return psp_mmio_base; - - iohc = get_iohc_info(&iohc_count); - const uint64_t psp_mmio_mask = get_psp_mmio_mask(); - - if (!psp_mmio_mask) - return 0; - - for (size_t i = 0; i < iohc_count; i++) { - uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); - - if (!(reg64 & IOHC_MMIO_EN)) - continue; - - const uint64_t base = reg64 & psp_mmio_mask; - - if (ENV_X86_32 && base >= 4ull * GiB) { - printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); - continue; - } - - /* If the PSP MMIO base is enabled but the register isn't locked, set the lock - bit. This shouldn't happen, but better be a bit too careful here */ - if (!(reg64 & PSP_MMIO_LOCK)) { - printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " - "Locking it.\n", i); - reg64 |= PSP_MMIO_LOCK; - /* Since the lock bit lives in the lower one of the two 32 bit SMN - registers, we only need to write that one to lock it */ - smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, - reg64 & 0xffffffff); - } - - psp_mmio_base = base; - } - - if (!psp_mmio_base) - printk(BIOS_ERR, "No usable PSP MMIO found.\n"); - - return psp_mmio_base; -} - union pspv2_mbox_command { uint32_t val; struct pspv2_mbox_cmd_fields { @@ -92,37 +22,47 @@ union pspv2_mbox_command { } __packed fields; }; -static uint16_t rd_mbox_sts(uintptr_t psp_mmio) +static uint16_t rd_mbox_sts(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, uint8_t cmd) +static void wr_mbox_cmd(uint64_t base, uint8_t cmd) { - union pspv2_mbox_command tmp = { .val = 0 }; + union pspv2_mbox_command tmp, reg = { .val = 0 }; + /* + * When recovery boot is supported (A/B recovery or second SPI flash) then + * the recovery bit must be preserved for FSP. Clear the other fields to + * make sure PSP starts processing the request. + */ + if (CONFIG(PSP_AB_RECOVERY) || + CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) { + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); + reg.fields.recovery = tmp.fields.recovery; + } /* Write entire 32-bit area to begin command execution */ - tmp.fields.mbox_command = cmd; - write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + reg.fields.mbox_command = cmd; + psp_write32(base, PSP_MAILBOX_COMMAND_OFFSET, reg.val); } -static uint8_t rd_mbox_recovery(uintptr_t psp_mmio) +static uint8_t rd_mbox_recovery(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(uint64_t base, void *buffer) { - write64p(psp_mmio | PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + psp_write64(base, PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(uint64_t base, bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; @@ -140,7 +80,7 @@ static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -151,34 +91,41 @@ static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) int send_psp_command(uint32_t command, void *buffer) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = psp_get_base(); int ret = 0; - if (!psp_mmio) + if (!base) return -PSPSTS_NOBASE; - if (rd_mbox_recovery(psp_mmio)) + /* + * When recovery boot is supported (A/B recovery or second SPI flash) and + * when booting from recovery partition the PSP is still functional even when + * reporting recovery mode. + */ + if (!(CONFIG(PSP_AB_RECOVERY) || + CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) && + rd_mbox_recovery(base)) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(base, true)) return -PSPSTS_CMD_TIMEOUT; if (ENV_SMM) psp_set_smm_flag(); /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(base, buffer); + wr_mbox_cmd(base, command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) { + if (wait_command(base, command != MBOX_BIOS_CMD_SX_INFO)) { ret = -PSPSTS_CMD_TIMEOUT; goto out; } /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) { + if (rd_mbox_sts(base)) { ret = -PSPSTS_SEND_ERROR; goto out; } @@ -214,12 +161,12 @@ enum cb_err psp_get_psp_capabilities(uint32_t *capabilities) enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = psp_get_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET); + *msg_38_value = psp_read32(base, CORE_2_PSP_MSG_38_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp_gen2_mmio.c b/src/soc/amd/common/block/psp/psp_gen2_mmio.c new file mode 100644 index 00000000000..14f0327a8cf --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_mmio.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "psp_def.h" + +#define IOHC_MISC_PSP_MMIO_REG 0x2e0 + +static uint64_t get_psp_mmio_mask(void) +{ + const struct non_pci_mmio_reg *mmio_regs; + size_t reg_count; + mmio_regs = get_iohc_non_pci_mmio_regs(®_count); + + for (size_t i = 0; i < reg_count; i++) { + if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) + return mmio_regs[i].mask; + } + + printk(BIOS_ERR, "No PSP MMIO register description found.\n"); + return 0; +} + +#define PSP_MMIO_LOCK BIT(8) + +/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, + so we have to read this from the hardware registers */ +static uintptr_t get_psp_mmio_base(void) +{ + static uintptr_t psp_mmio_base; + const struct domain_iohc_info *iohc; + size_t iohc_count; + + if (psp_mmio_base) + return psp_mmio_base; + + iohc = get_iohc_info(&iohc_count); + const uint64_t psp_mmio_mask = get_psp_mmio_mask(); + + if (!psp_mmio_mask) + return 0; + + for (size_t i = 0; i < iohc_count; i++) { + uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); + + if (!(reg64 & IOHC_MMIO_EN)) + continue; + + const uint64_t base = reg64 & psp_mmio_mask; + + if (ENV_X86_32 && base >= 4ull * GiB) { + printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); + continue; + } + + /* If the PSP MMIO base is enabled but the register isn't locked, set the lock + bit. This shouldn't happen, but better be a bit too careful here */ + if (!(reg64 & PSP_MMIO_LOCK)) { + printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " + "Locking it.\n", i); + reg64 |= PSP_MMIO_LOCK; + /* Since the lock bit lives in the lower one of the two 32 bit SMN + registers, we only need to write that one to lock it */ + smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, + reg64 & 0xffffffff); + } + + psp_mmio_base = base; + } + + if (!psp_mmio_base) + printk(BIOS_ERR, "No usable PSP MMIO found.\n"); + + return psp_mmio_base; +} + +uint64_t psp_get_base(void) +{ + return get_psp_mmio_base(); +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return read32p((uintptr_t)(base | offset)); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + write32p((uintptr_t)(base | offset), data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + write64p((uintptr_t)(base | offset), data); +} diff --git a/src/soc/amd/common/block/psp/psp_gen2_smn.c b/src/soc/amd/common/block/psp/psp_gen2_smn.c new file mode 100644 index 00000000000..45b74874f00 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_smn.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "psp_def.h" + +uint64_t psp_get_base(void) +{ + return SMN_PSP_PUBLIC_BASE; +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return smn_read32(base | offset); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + smn_write32(base | offset, data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + smn_write32(base | (offset + sizeof(uint32_t)), data >> 32); + smn_write32(base | offset, data & 0xffffffff); +} diff --git a/src/soc/amd/common/block/psp/psp_rom_armor.c b/src/soc/amd/common/block/psp/psp_rom_armor.c new file mode 100644 index 00000000000..bec99310906 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_rom_armor.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "psp_rom_armor_apmc.h" + +/* + * Ramstage wrappers that trigger SMI to execute ROM Armor operations in SMM. + * These functions communicate with SMM via CPU registers (call_smm) + */ + +/* + * Read data from the SPI flash via PSP ROM Armor. + * ROM Armor 2 only. + * + * On ROM Armor 3, reads can be done directly through ROM2/ROM3 MMIO, + * so this function is not used. + */ +static ssize_t rom_armor_ramstage_readat(const struct region_device *rd, void *buf, + size_t offset, size_t len) +{ + struct rom_armor_params_read params = { + .buf = buf, + .offset = offset, + .size = len, + }; + u32 ret; + + printk(BIOS_DEBUG, "PSP RomArmor (ramstage): Read offset=0x%zx, len=0x%zx\n", + offset, len); + + if (!buf) { + printk(BIOS_ERR, "PSP RomArmor (ramstage): Invalid read parameters\n"); + return -1; + } + + ret = call_smm(APM_CNT_ROM_ARMOR, ROM_ARMOR_APM_CMD_READ, ¶ms); + + if (ret != ROM_ARMOR_RET_SUCCESS) { + printk(BIOS_ERR, "PSP RomArmor (ramstage): Read failed, ret=%u\n", ret); + return -1; + } + + return len; +} + +static ssize_t rom_armor_ramstage_writeat(const struct region_device *rd, const void *buf, + size_t offset, size_t len) +{ + struct rom_armor_params_write params = { + .buf = buf, + .offset = offset, + .size = len, + }; + u32 ret; + + printk(BIOS_DEBUG, "PSP ROM Armor (ramstage): Write offset=0x%zx, len=0x%zx\n", + offset, len); + + if (!buf || len == 0) { + printk(BIOS_ERR, "PSP ROM Armor (ramstage): Invalid write parameters\n"); + return -1; + } + + ret = call_smm(APM_CNT_ROM_ARMOR, ROM_ARMOR_APM_CMD_WRITE, ¶ms); + + if (ret != ROM_ARMOR_RET_SUCCESS) { + printk(BIOS_ERR, "PSP ROM Armor (ramstage): Write failed, ret=%u\n", ret); + return -1; + } + + return len; +} + +static ssize_t rom_armor_ramstage_eraseat(const struct region_device *rd, + size_t offset, size_t len) +{ + struct rom_armor_params_erase params = { + .offset = offset, + .size = len, + }; + u32 ret; + + printk(BIOS_DEBUG, "PSP ROM Armor (ramstage): Erase offset=0x%zx, len=0x%zx\n", + offset, len); + + ret = call_smm(APM_CNT_ROM_ARMOR, ROM_ARMOR_APM_CMD_ERASE, ¶ms); + + if (ret != ROM_ARMOR_RET_SUCCESS) { + printk(BIOS_ERR, "PSP ROM Armor (ramstage): Erase failed, ret=%u\n", ret); + return -1; + } + + return len; +} + + +/* Region device operations for ramstage - uses APM calls to SMM */ +const struct region_device_ops rom_armor_apm_ops = { + .mmap = NULL, + .munmap = NULL, + .readat = rom_armor_ramstage_readat, /* Only used by ROM Armor 2 */ + .writeat = rom_armor_ramstage_writeat, + .eraseat = rom_armor_ramstage_eraseat, +}; + +const struct region_device rom_armor_apm_call_rw = + REGION_DEV_INIT(&rom_armor_apm_ops, 0, CONFIG_ROM_SIZE); + +void psp_rom_armor_init(bool allow_capsule_update) +{ + enum rom_armor_apm_result ret; + struct rom_armor_params_init params = { + .capsule_update = allow_capsule_update, + }; + ret = call_smm(APM_CNT_ROM_ARMOR, ROM_ARMOR_APM_CMD_INIT, ¶ms); + if (ret != ROM_ARMOR_RET_SUCCESS) + printk(BIOS_EMERG, "Failed to initialize ROM Armor. ret=%u", ret); +} + +static void rom_armor_finalize(void *unused) +{ + /* + * Lock down rom armor APM interface. Only SMMSTORE will be able to access + * the flash through APM interface from here on. + */ + call_smm(APM_CNT_ROM_ARMOR, ROM_ARMOR_APM_CMD_SHUTDOWN, NULL); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, rom_armor_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, rom_armor_finalize, NULL); diff --git a/src/soc/amd/common/block/psp/psp_rom_armor_apmc.h b/src/soc/amd/common/block/psp/psp_rom_armor_apmc.h new file mode 100644 index 00000000000..1ab5bf5fad8 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_rom_armor_apmc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_PSP_ROM_ARMOR_APMC_H +#define AMD_BLOCK_PSP_ROM_ARMOR_APMC_H + +#include +#include + +/* ROM Armor APM sub-commands */ +enum rom_armor_apm_cmd { + ROM_ARMOR_APM_CMD_INIT = 1, + ROM_ARMOR_APM_CMD_READ = 2, + ROM_ARMOR_APM_CMD_WRITE = 3, + ROM_ARMOR_APM_CMD_ERASE = 4, + ROM_ARMOR_APM_CMD_SHUTDOWN = 5, +}; + +/* Return values */ +enum rom_armor_apm_result { + ROM_ARMOR_RET_SUCCESS = 0, + ROM_ARMOR_RET_FAILURE, + ROM_ARMOR_RET_SHUTDOWN, + ROM_ARMOR_RET_NOT_INITIALIZED, + ROM_ARMOR_RET_UNSUPPORTED, +}; + +/* Parameter structures for ROM Armor operations */ +struct rom_armor_params_init { + bool capsule_update; /* 1 for capsule update/recovery mode, 0 otherwise */ +}; + +struct rom_armor_params_read { + void *buf; + size_t offset; + size_t size; +}; + +struct rom_armor_params_write { + const void *buf; + size_t offset; + size_t size; +}; + +struct rom_armor_params_erase { + size_t offset; + size_t size; +}; + +#endif /* AMD_BLOCK_PSP_ROM_ARMOR_APMC_H */ diff --git a/src/soc/amd/common/block/psp/psp_rom_armor_smm.c b/src/soc/amd/common/block/psp/psp_rom_armor_smm.c new file mode 100644 index 00000000000..591705982a9 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_rom_armor_smm.c @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "psp_def.h" +#include "psp_rom_armor_apmc.h" + +static u8 transfer_buffer[4 * KiB] __aligned(32); + +/* + * Read data from the SPI flash via PSP RomArmor. + * ROM Armor 2 only. + * + * On ROM Armor 3, reads can be done directly through ROM2/ROM3 MMIO, + * so this function is not used. + * + * This bypasses direct SPI controller access and uses PSP firmware + * to perform the read operation through RomArmor protocol. + */ +static ssize_t psp_rom_armor_spi_readat(const struct region_device *rd, void *buf, + size_t offset, size_t len) +{ + struct mbox_rom_armor_flash_command cmd; + uint32_t byte_counter; + int ret; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)) + return -1; + + printk(BIOS_DEBUG, "PSP RomArmor rdev_ops: read offset=0x%zx, len=0x%zx\n", + offset, len); + + if (!buf || !len) { + printk(BIOS_ERR, "PSP RomArmor rdev_ops: Invalid read parameters\n"); + return -1; + } + if (len > region_device_sz(&rom_armor_smm_rw) || + offset > region_device_sz(&rom_armor_smm_rw) || + (offset + len) > region_device_sz(&rom_armor_smm_rw)) { + printk(BIOS_ERR, "PSP RomArmor rdev_ops: read range exceeds flash size\n"); + return -1; + } + + cmd.transaction = READ_ACCESS; + cmd.buffer_ptr = (uintptr_t)transfer_buffer; + cmd.read_back = 0; + cmd.offset = offset; + + /* Process read in 4KB chunks */ + for (byte_counter = 0; byte_counter < len; ) { + cmd.size = len - byte_counter; + + if (cmd.size > sizeof(transfer_buffer)) + cmd.size = sizeof(transfer_buffer); + + printk(BIOS_SPEW, " Read chunk: addr=0x%x, len=0x%x\n", + cmd.offset, cmd.size); + + ret = psp_rom_armor_spi_transaction(&cmd); + if (ret < 0) { + printk(BIOS_ERR, "PSP RomArmor rdev_ops: Read transaction failed\n"); + return -1; + } + /* Copy data from mailbox buffer */ + memcpy(buf, transfer_buffer, cmd.size); + buf += cmd.size; + cmd.offset += cmd.size; + byte_counter += cmd.size; + } + + printk(BIOS_DEBUG, "PSP RomArmor rdev_ops: Read complete\n"); + return len; +} + +/* + * Write data to the SPI flash via ROM Armor + * + * Chunks the write into 4KB blocks and communicates with PSP + * to perform write operations through ROM Armor3 protocol. + */ +static ssize_t psp_rom_armor_spi_writeat(const struct region_device *rd, const void *buf, + size_t offset, size_t len) +{ + struct mbox_rom_armor_flash_command cmd = { + .transaction = RA_WRITE, + .buffer_ptr = (uintptr_t)transfer_buffer, + .offset = offset, + .read_back = 0, + }; + uint32_t byte_counter; + const uint8_t *current_buffer; + + printk(BIOS_DEBUG, "ROM Armor rdev_ops: Write offset=0x%zx, len=0x%zx\n", + offset, len); + + if (!buf || len == 0) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Invalid write parameters\n"); + return -1; + } + if (len > region_device_sz(&rom_armor_smm_rw) || + offset > region_device_sz(&rom_armor_smm_rw) || + (offset + len) > region_device_sz(&rom_armor_smm_rw)) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Write range exceeds flash size\n"); + return -1; + } + + /* Process write in 4KB chunks */ + for (byte_counter = 0; byte_counter < len; ) { + current_buffer = (const uint8_t *)buf + byte_counter; + cmd.size = MIN(len - byte_counter, sizeof(transfer_buffer)); + + printk(BIOS_SPEW, " Write chunk: addr=0x%x, len=0x%x\n", + cmd.offset, cmd.size); + + /* Copy data to mailbox buffer */ + memcpy(transfer_buffer, current_buffer, cmd.size); + + int ret = psp_rom_armor_spi_transaction(&cmd); + if (ret < 0) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Write transaction failed\n"); + return -1; + } + + byte_counter += cmd.size; + cmd.offset += cmd.size; + } + + printk(BIOS_DEBUG, "ROM Armor rdev_ops: Write complete\n"); + return len; +} + +/* + * Erase SPI flash sectors via ROM Armor + * + * Supports both 4KB and 64KB erase block sizes for efficiency. + * Uses PSP firmware to perform erase operations through ROM Armor3 protocol. + */ +static ssize_t psp_rom_armor_spi_eraseat(const struct region_device *rd, + size_t offset, size_t len) +{ + struct mbox_rom_armor_flash_command cmd = { + .transaction = RA_ERASE, + .buffer_ptr = (uintptr_t)transfer_buffer, /* Unused, but MUST not be NULL! */ + .offset = offset, + .read_back = 0, + }; + + printk(BIOS_DEBUG, "ROM Armor rdev_ops: Erase offset=0x%zx, len=0x%zx\n", + offset, len); + + if (len == 0 || !IS_ALIGNED(len, 4 * KiB) || !IS_ALIGNED(offset, 4 * KiB)) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Invalid erase parameters\n"); + return -1; + } + if (len > region_device_sz(&rom_armor_smm_rw) || + offset > region_device_sz(&rom_armor_smm_rw) || + (offset + len) > region_device_sz(&rom_armor_smm_rw)) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Erase range exceeds flash size\n"); + return -1; + } + + for (ssize_t remaining = len; remaining;) { + /* + * Use 64KB erase when: + * - Feature is enabled + * - Address is 64KB aligned + * - Enough blocks remain (16 x 4KB = 64KB) + */ + if (CONFIG(SOC_AMD_PSP_ROM_ARMOR_64K_ERASE) && + IS_ALIGNED(cmd.offset, 64 * KiB) && + (remaining >= (64 * KiB))) { + cmd.size = 64 * KiB; + printk(BIOS_SPEW, "ROM Armor rdev_ops: Erase 64KB at 0x%x\n", cmd.offset); + } else { + /* TODO: Figure out when 4KiB is an architecture-specific limitation. */ + cmd.size = 4 * KiB; + printk(BIOS_SPEW, "ROM Armor rdev_ops: Erase 4KB at 0x%x\n", cmd.offset); + } + + int ret = psp_rom_armor_spi_transaction(&cmd); + if (ret < 0) { + printk(BIOS_ERR, "ROM Armor rdev_ops: Erase transaction failed: %d\n", ret); + return ret; + } + cmd.offset += cmd.size; + remaining -= cmd.size; + } + + printk(BIOS_DEBUG, "ROM Armor rdev_ops: Erase complete\n"); + return len; +} + +/* Rom Armor flash ops are only accessible in SMM. */ +static const struct region_device_ops rom_armor_spi_flash_ops = { + .mmap = NULL, + .munmap = NULL, + .readat = psp_rom_armor_spi_readat, + .writeat = psp_rom_armor_spi_writeat, + .eraseat = psp_rom_armor_spi_eraseat, +}; + +struct region_device rom_armor_smm_rw = + REGION_DEV_INIT(&rom_armor_spi_flash_ops, 0, CONFIG_ROM_SIZE); + +/* + * SMM handler for ROM Armor operations + * Called from APMC SMI handler with parameters passed via CPU registers + */ +static bool shutdown; +static bool initialized; + +uint32_t rom_armor_exec(uint8_t command, void *param) +{ + ssize_t ret; + size_t flash_size = 0; + + /* After shutdown don't respond to requests */ + if (shutdown) + return ROM_ARMOR_RET_SHUTDOWN; + + /* Shutdown command doesn't need param */ + if (!param && command != ROM_ARMOR_APM_CMD_SHUTDOWN) + return ROM_ARMOR_RET_FAILURE; + + /* Ensure param does not point to SMM space */ + if (param && smm_points_to_smram(param, sizeof(uintptr_t))) + return ROM_ARMOR_RET_FAILURE; + + switch (command) { + case ROM_ARMOR_APM_CMD_INIT: { + struct rom_armor_params_init *params = param; + + if (initialized) + return ROM_ARMOR_RET_FAILURE; + + printk(BIOS_DEBUG, "%s: Init command received (capsule_update=%d)\n", + __func__, params->capsule_update); + + if (psp_rom_armor_enter_smm_mode(params->capsule_update, &flash_size) != 0) { + printk(BIOS_ERR, "%s: Failed to enter SMM mode\n", __func__); + return ROM_ARMOR_RET_FAILURE; + } + /* Sanity check HSTI status */ + if (!psp_get_hsti_state_rom_armor_enforced()) + return ROM_ARMOR_RET_FAILURE; + + printk(BIOS_INFO, "%s: Initialized with flash size 0x%zx\n", __func__, flash_size); + if (region_device_sz(&rom_armor_smm_rw) != flash_size) { + printk(BIOS_ERR, "%s: Flash size 0x%zx doesn't match CONFIG_ROM_SIZE!\n", + __func__, flash_size); + rom_armor_smm_rw.region.size = flash_size; + } + + initialized = true; + + return ROM_ARMOR_RET_SUCCESS; + } + case ROM_ARMOR_APM_CMD_READ: { + struct rom_armor_params_read *params = param; + + if (!initialized) + return ROM_ARMOR_RET_NOT_INITIALIZED; + + /* Validate parameters */ + if (smm_points_to_smram(params->buf, params->size)) + return ROM_ARMOR_RET_FAILURE; + + printk(BIOS_DEBUG, "%s: Read offset=0x%zx size=0x%zx\n", + __func__, params->offset, params->size); + + ret = psp_rom_armor_spi_readat(&rom_armor_smm_rw, params->buf, + params->offset, params->size); + return (ret == (ssize_t)params->size) ? ROM_ARMOR_RET_SUCCESS : + ROM_ARMOR_RET_FAILURE; + } + + case ROM_ARMOR_APM_CMD_WRITE: { + struct rom_armor_params_write *params = param; + + if (!initialized) + return ROM_ARMOR_RET_NOT_INITIALIZED; + + /* Validate parameters */ + if (smm_points_to_smram(params->buf, params->size)) + return ROM_ARMOR_RET_FAILURE; + + printk(BIOS_DEBUG, "%s: Write src=%p offset=0x%zx size=0x%zx\n", + __func__, params->buf, params->offset, params->size); + + ret = psp_rom_armor_spi_writeat(&rom_armor_smm_rw, params->buf, + params->offset, params->size); + return (ret == (ssize_t)params->size) ? ROM_ARMOR_RET_SUCCESS : + ROM_ARMOR_RET_FAILURE; + } + + case ROM_ARMOR_APM_CMD_ERASE: { + struct rom_armor_params_erase *params = param; + + if (!initialized) + return ROM_ARMOR_RET_NOT_INITIALIZED; + + printk(BIOS_DEBUG, "%s: Erase offset=0x%zx size=0x%zx\n", + __func__, params->offset, params->size); + + ret = psp_rom_armor_spi_eraseat(&rom_armor_smm_rw, + params->offset, params->size); + return (ret == (ssize_t)params->size) ? ROM_ARMOR_RET_SUCCESS : + ROM_ARMOR_RET_FAILURE; + } + case ROM_ARMOR_APM_CMD_SHUTDOWN: + shutdown = true; + printk(BIOS_DEBUG, "%s: Disabled\n", __func__); + return ROM_ARMOR_RET_SUCCESS; + default: + printk(BIOS_ERR, "%s: Unknown command: 0x%02x\n", __func__, command); + } + return ROM_ARMOR_RET_UNSUPPORTED; +} diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index a2b718b160b..963ae4232c0 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -32,43 +33,16 @@ static const char *id_to_region_name(uint64_t target_nv_id) return NULL; } -/* - * Do not cache the location to cope with flash changing underneath (e.g. due - * to an update) - */ -static int lookup_store(uint64_t target_nv_id, struct region_device *rstore) +static enum mbox_p2c_status get_flash_device(const enum boot_device boot_device, + const struct spi_flash **flash) { - /* read_rdev, write_rdev and store_irdev need to be static to not go out of scope when - this function returns */ - static struct region_device read_rdev, write_rdev; - static struct incoherent_rdev store_irdev; - const char *name; - struct region region; - const struct region_device *rdev; - - name = id_to_region_name(target_nv_id); - if (!name) - return -1; + if (boot_device == FLASH_PRIMARY) + *flash = boot_device_spi_flash(); + else if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) + *flash = backup_boot_device_spi_flash(); + else + return MBOX_PSP_INVALID_PARAMETER; - if (fmap_locate_area(name, ®ion) < 0) - return -1; - - if (boot_device_ro_subregion(®ion, &read_rdev) < 0) - return -1; - - if (boot_device_rw_subregion(®ion, &write_rdev) < 0) - return -1; - - rdev = incoherent_rdev_init(&store_irdev, ®ion, &read_rdev, &write_rdev); - if (rdev == NULL) - return -1; - - return rdev_chain(rstore, rdev, 0, region_device_sz(rdev)); -} - -static enum mbox_p2c_status get_flash_device(const struct spi_flash **flash) -{ - *flash = boot_device_spi_flash(); if (*flash == NULL) { printk(BIOS_ERR, "PSP: Unable to find SPI device\n"); return MBOX_PSP_COMMAND_PROCESS_ERROR; @@ -77,16 +51,51 @@ static enum mbox_p2c_status get_flash_device(const struct spi_flash **flash) return MBOX_PSP_SUCCESS; } -static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_id, +static enum mbox_p2c_status find_psp_spi_flash_device_region(const enum boot_device boot_device, + uint64_t target_nv_id, struct region_device *store, const struct spi_flash **flash) { - if (get_flash_device(flash) != MBOX_PSP_SUCCESS) + static struct region_device read_rdev, write_rdev; + static struct incoherent_rdev store_irdev; + const struct region_device *rdev; + const char *name; + struct region region; + + if (get_flash_device(boot_device, flash) != MBOX_PSP_SUCCESS) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + name = id_to_region_name(target_nv_id); + if (!name) return MBOX_PSP_COMMAND_PROCESS_ERROR; - if (lookup_store(target_nv_id, store) < 0) { - printk(BIOS_ERR, "PSP: Unable to find PSP SPI region\n"); + if (fmap_locate_area(name, ®ion) < 0) return MBOX_PSP_COMMAND_PROCESS_ERROR; + + if (boot_device == FLASH_PRIMARY) { + if (boot_device_ro_subregion(®ion, &read_rdev) < 0) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + if (boot_device_rw_subregion(®ion, &write_rdev) < 0) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + rdev = incoherent_rdev_init(&store_irdev, ®ion, &read_rdev, &write_rdev); + if (rdev == NULL) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + return rdev_chain(store, rdev, 0, region_device_sz(rdev)); + + } else if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) { + /* + * FIXME: No backup_boot_device_ro_subregion() implementation yet, so use + * the rw one for both read and write. This is slower! + */ + if (backup_boot_device_rw_subregion(®ion, &write_rdev) < 0) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + return rdev_chain(store, &write_rdev, 0, region_device_sz(&write_rdev)); + } else { + return MBOX_PSP_INVALID_PARAMETER; } return MBOX_PSP_SUCCESS; @@ -138,6 +147,20 @@ static bool spi_controller_busy(void) busy = true; } } + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH) && !busy) { + const struct spi_flash *spi_flash_dev; + uint8_t sr1 = 0; + + spi_flash_dev = backup_boot_device_spi_flash(); + assert(spi_flash_dev); + if (spi_flash_dev) { + /* Read Status Register 1 */ + if (spi_flash_status(spi_flash_dev, &sr1) < 0) + busy = true; + else if (sr1 & BIT(0)) + busy = true; + } + } if (CONFIG(SOC_AMD_PICASSO) && !busy) { // Only implemented on Picasso and Raven Ridge @@ -172,7 +195,7 @@ enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer) target_nv_id = get_psp_spi_info_id(cmd_buf); - ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash); + ret = find_psp_spi_flash_device_region(FLASH_PRIMARY, target_nv_id, &store, &flash); if (ret != MBOX_PSP_SUCCESS) return ret; @@ -220,7 +243,7 @@ enum mbox_p2c_status psp_smi_spi_read(struct mbox_default_buffer *buffer) return MBOX_PSP_COMMAND_PROCESS_ERROR; } - ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash); + ret = find_psp_spi_flash_device_region(FLASH_PRIMARY, target_nv_id, &store, &flash); if (ret != MBOX_PSP_SUCCESS) return ret; @@ -268,7 +291,7 @@ enum mbox_p2c_status psp_smi_spi_write(struct mbox_default_buffer *buffer) return MBOX_PSP_COMMAND_PROCESS_ERROR; } - ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash); + ret = find_psp_spi_flash_device_region(FLASH_PRIMARY, target_nv_id, &store, &flash); if (ret != MBOX_PSP_SUCCESS) return ret; @@ -282,6 +305,21 @@ enum mbox_p2c_status psp_smi_spi_write(struct mbox_default_buffer *buffer) return MBOX_PSP_COMMAND_PROCESS_ERROR; } + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) + return MBOX_PSP_SUCCESS; + + ret = find_psp_spi_flash_device_region(FLASH_BACKUP, target_nv_id, &store, &flash); + + if (ret != MBOX_PSP_SUCCESS) + return ret; + + printk(BIOS_SPEW, "PSP: SPI write 0x%llx bytes at 0x%zx\n", num_bytes, addr); + + if (rdev_writeat(&store, data, addr, (size_t)num_bytes) != (size_t)num_bytes) { + printk(BIOS_ERR, "PSP: Failed to write NVRAM data\n"); + return MBOX_PSP_COMMAND_PROCESS_ERROR; + } + return MBOX_PSP_SUCCESS; } @@ -309,7 +347,7 @@ enum mbox_p2c_status psp_smi_spi_erase(struct mbox_default_buffer *buffer) get_psp_spi_erase(cmd_buf, &target_nv_id, &lba, &num_blocks); - ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash); + ret = find_psp_spi_flash_device_region(FLASH_PRIMARY, target_nv_id, &store, &flash); if (ret != MBOX_PSP_SUCCESS) return ret; @@ -324,6 +362,21 @@ enum mbox_p2c_status psp_smi_spi_erase(struct mbox_default_buffer *buffer) return MBOX_PSP_COMMAND_PROCESS_ERROR; } + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) + return MBOX_PSP_SUCCESS; + + ret = find_psp_spi_flash_device_region(FLASH_BACKUP, target_nv_id, &store, &flash); + + if (ret != MBOX_PSP_SUCCESS) + return ret; + + printk(BIOS_SPEW, "PSP: SPI erase 0x%zx bytes at 0x%zx\n", num_bytes, addr); + + if (rdev_eraseat(&store, addr, num_bytes) != num_bytes) { + printk(BIOS_ERR, "PSP: Failed to erase SPI NVRAM data\n"); + return MBOX_PSP_COMMAND_PROCESS_ERROR; + } + return MBOX_PSP_SUCCESS; } @@ -342,7 +395,7 @@ enum mbox_p2c_status psp_smi_spi_rpmc_inc_mc(struct mbox_default_buffer *buffer) return MBOX_PSP_SPI_BUSY; } - if (get_flash_device(&flash) != MBOX_PSP_SUCCESS) + if (get_flash_device(FLASH_PRIMARY, &flash) != MBOX_PSP_SUCCESS) return MBOX_PSP_COMMAND_PROCESS_ERROR; if (spi_flash_rpmc_increment(flash, cmd_buf->req.counter_address, @@ -350,6 +403,17 @@ enum mbox_p2c_status psp_smi_spi_rpmc_inc_mc(struct mbox_default_buffer *buffer) != CB_SUCCESS) return MBOX_PSP_COMMAND_PROCESS_ERROR; + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH)) + return MBOX_PSP_SUCCESS; + + if (get_flash_device(FLASH_BACKUP, &flash) != MBOX_PSP_SUCCESS) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + + if (spi_flash_rpmc_increment(flash, cmd_buf->req.counter_address, + cmd_buf->req.counter_data, cmd_buf->req.signature) + != CB_SUCCESS) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + return MBOX_PSP_SUCCESS; } @@ -368,7 +432,7 @@ enum mbox_p2c_status psp_smi_spi_rpmc_req_mc(struct mbox_default_buffer *buffer) return MBOX_PSP_SPI_BUSY; } - if (get_flash_device(&flash) != MBOX_PSP_SUCCESS) + if (get_flash_device(FLASH_PRIMARY, &flash) != MBOX_PSP_SUCCESS) return MBOX_PSP_COMMAND_PROCESS_ERROR; if (spi_flash_rpmc_request(flash, cmd_buf->req.counter_address, cmd_buf->req.tag, diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index ef7a018827e..f569a4b3a99 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -98,6 +98,65 @@ int psp_notify_smm(void) return cmd_status; } +int psp_rom_armor_enter_smm_mode(const bool allow_capsule_update, size_t *flash_size) +{ + int cmd_status; + + *flash_size = 0; + + /* Initialize and send ROM Armor Enter SMM Mode command */ + struct mbox_rom_armor_enforce_buffer enforce_buffer = { + .header.size = sizeof(enforce_buffer), + .capsule_update = allow_capsule_update, + }; + + printk(BIOS_SPEW, "PSP: Entering ROM Armor SMM-only mode...\n"); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE, &enforce_buffer); + psp_print_cmd_status(cmd_status, &enforce_buffer.header); + + if (cmd_status || enforce_buffer.header.status) + return -1; + + *flash_size = enforce_buffer.flash_size; + return 0; +} + +int psp_rom_armor_spi_transaction(const struct mbox_rom_armor_flash_command *cmd_buf) +{ + int cmd_status; + struct mbox_rom_armor_flash_command_buffer *buffer; + + /* PSP verifies that this buffer is at the address specified in psp_notify_smm() */ + buffer = (struct mbox_rom_armor_flash_command_buffer *)c2p_buffer.buffer; + assert(buffer); + assert(cmd_buf); + + buffer->header.size = sizeof(*buffer); + buffer->header.status = 0; /* Clear status before sending command */ + memcpy(&buffer->cmd, cmd_buf, sizeof(*cmd_buf)); + + /* Sanity checks */ + assert(buffer->cmd.transaction); + assert(buffer->cmd.buffer_ptr); + assert(buffer->cmd.size); + + printk(BIOS_SPEW, "PSP: Sending transaction type=%u offset=0x%x size=0x%x buffer_ptr=0x%llx read_back=0x%x\n", + buffer->cmd.transaction, buffer->cmd.offset, buffer->cmd.size, + buffer->cmd.buffer_ptr, buffer->cmd.read_back); + + asm volatile ("sfence"); + + /* Send command to PSP */ + cmd_status = send_psp_command(MBOX_BIOS_CMD_ARMOR_SPI_TRANSACTION, buffer); + if (cmd_status || buffer->header.status) { + psp_print_cmd_status(cmd_status, &buffer->header); + return cmd_status ? cmd_status : buffer->header.status; + } + + return 0; +} + /* Notify PSP the system is going to a sleep state. */ void psp_notify_sx_info(uint8_t sleep_type) { diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 085c02a2f68..7d87184a560 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -2,11 +2,20 @@ config SOC_AMD_COMMON_BLOCK_SPI bool + select SPI_FLASH_SFDP if SPI_FLASH help Select this option to add FCH SPI controller functions to the build. This overwrites the structure spi_flash_ops to use FCH SPI code instead of individual SPI specific code. +config SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS + bool + depends on SOC_AMD_COMMON_BLOCK_SPI + help + Select this option when the FCH SPI controller MMIO can be written to + with DWORDs instead of just BYTEs. This is supported since AMD Familiy + 17h Model A0h. + config SOC_AMD_COMMON_BLOCK_SPI_DEBUG bool "Enable SPI debugging" @@ -132,3 +141,62 @@ config TPM_SPI_SPEED 3: 16.66MHz 4: 100MHz 5: 800KHz + +config SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 + bool "Enable ROM Armor 3" + select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_MEMORY_MAPPED + select BOOT_DEVICE_SUPPORTS_WRITES + select SPI_FLASH + select SPI_FLASH_SMM + depends on HAVE_SMI_HANDLER + depends on SOC_AMD_COMMON_BLOCK_PSP + depends on SOC_AMD_COMMON_BLOCK_SPI + depends on !SOC_AMD_COMMON_BLOCK_PSP_SMI + help + Select this option to use PSP ROM Armor3 protocol for SPI flash + operations. This routes SPI read/write/erase operations through + the SMM PSP firmware mailbox interface instead of direct FCH SPI + controller access. After MPinit the SPI will become read only from + x86 perspective and the SPI Ctrl interface will be deactived. + + You will be only able to write SPI regions that are marked 'writable' or + are whitelisted by BIOS directory entries 0x6d (AMD_BIOS_NV_ST). To gain + direct access to the SPI flash, you must issue a reboot. + + WARNING: Since the flash access in the SMI handler is a blocking + operation during which all cores stay in SMM, an erase operation may + lock up the system for a long enough time to be noticeable. Reads and + writes with small data sizes are less problematic. This is AMD + specific design and should be enabled when you don't want to service + PSP SMI requests (see CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI). + +config SOC_AMD_PSP_ROM_ARMOR_64K_ERASE + bool + depends on SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 + default n + help + Enable 64KB erase block size support in addition to 4KB blocks. + This can improve erase performance when erasing large regions. + The PSP firmware must support 64KB erase commands for this to work. + +config SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH + bool + depends on SOC_AMD_COMMON_BLOCK_SPI + depends on !SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 # TODO: remove once this is supported + help + Select this option when there is a second SPI flash + which can be booted of when the primary SPI flash is + corrupted. The recovery mechanism is board specific. + The secondary SPI flash must be of the same type and + same size as the primary SPI flash. + +config BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT + int + depends on SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH + default 1 + help + Which chip select line the backup boot device is connected to. + The assumption here is that chip select 0 and this one have an SPI flash connected to + it. Depending on which chip select of these two we booted from, we deem one of them + our backup/secondary (the one we didn't boot from) SPI flash. diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk index 0dc78d9f3b3..5d75811ebff 100644 --- a/src/soc/amd/common/block/spi/Makefile.mk +++ b/src/soc/amd/common/block/spi/Makefile.mk @@ -28,4 +28,14 @@ ramstage-y += fch_spi_util.c verstage-y += fch_spi_util.c smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH),y) +all_x86-y += backup_boot_device_rw_nommap.c +smm-$(CONFIG_SPI_FLASH_SMM) += backup_boot_device_rw_nommap.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3),y) +all_x86-y += rom_armor_boot_device_rw_nommap.c +smm-y += rom_armor_boot_device_rw_nommap.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 + endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c b/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c new file mode 100644 index 00000000000..8ae4730c9a6 --- /dev/null +++ b/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static struct spi_flash sfg; +static bool sfg_init_done; + +/* + * The assumption here is that chip select 0 and CONFIG_BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT have + * an SPI flash connected to it. Depending on which chip select of these two we booted from, we + * deem one of them our backup/secondary (the one we didn't boot from) SPI flash. + */ +int backup_boot_device_spi_cs(void) +{ + if (boot_device_spi_cs() == 0) + return CONFIG_BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT; + return 0; +} + +static ssize_t spi_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + if (spi_flash_read(&sfg, offset, size, b)) + return -1; + + return size; +} + +static ssize_t spi_writeat(const struct region_device *rd, const void *b, + size_t offset, size_t size) +{ + if (spi_flash_write(&sfg, offset, size, b)) + return -1; + + return size; +} + +static ssize_t spi_eraseat(const struct region_device *rd, + size_t offset, size_t size) +{ + if (spi_flash_erase(&sfg, offset, size)) + return -1; + + return size; +} + +static const struct region_device_ops spi_ops = { + .readat = spi_readat, + .writeat = spi_writeat, + .eraseat = spi_eraseat, +}; + +static const struct region_device spi_rw = + REGION_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE); + +static void backup_boot_device_rw_init(void) +{ + const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; + const int cs = backup_boot_device_spi_cs(); + + if (sfg_init_done == true) + return; + + /* Cannot access backup boot device if ROM Armor is active */ + if (psp_get_hsti_state_rom_armor_enforced()) + return; + + /* Ensure any necessary setup is performed by the drivers. */ + spi_init(); + + if (!spi_flash_probe(bus, cs, &sfg)) + sfg_init_done = true; +} + +/** + * Returns the secondary SPI flash as read-writable region device. + * + * @return NULL on error. The region_device on success. + */ +const struct region_device *backup_boot_device_rw(void) +{ + /* Cannot access backup boot device if ROM Armor is active */ + if (psp_get_hsti_state_rom_armor_enforced()) + return NULL; + + /* Probe for the SPI flash device if not already done. */ + backup_boot_device_rw_init(); + + if (sfg_init_done != true) + return NULL; + + return &spi_rw; +} + +/** + * Returns the secondary SPI flash as spi_flash device. + * + * @return NULL on error. The region_device on success. + */ +const struct spi_flash *backup_boot_device_spi_flash(void) +{ + /* Cannot access backup boot device if ROM Armor is active */ + if (psp_get_hsti_state_rom_armor_enforced()) + return NULL; + + backup_boot_device_rw_init(); + + if (sfg_init_done != true) + return NULL; + + return &sfg; +} + +/** + * Returns a sub-region of the secondary SPI flash. + * + * @param sub The subregion within the SPI flash + * @param subrd The region_device to return + * + * @return 0 on success. + */ +int backup_boot_device_rw_subregion(const struct region *sub, + struct region_device *subrd) +{ + /* Cannot access backup boot device if ROM Armor is active */ + if (psp_get_hsti_state_rom_armor_enforced()) + return -1; + + /* Ensure boot device has been initialized at least once. */ + backup_boot_device_rw_init(); + + const struct region_device *parent = backup_boot_device_rw(); + + if (!parent) + return -1; + + return rdev_chain(subrd, parent, region_offset(sub), region_sz(sub)); +} + +/** + * Synchronize the SPI flash contents from one chip to the other. + * + * @param sub The region to synchronize + * @param direction_prim_to_sec When true synchronize the primary (boot_device_rw()) + * to the secondary (backup_boot_device_rw()). + * When false synchronize the secondary (backup_boot_device_rw()) + * to the primary (boot_device_rw()): + * + * @return 0 on success. + */ +int backup_boot_device_sync_subregion(const struct region *sub, + const bool direction_prim_to_sec) +{ + struct region_device prim, sec; + static uint8_t buffer_prim[64 * KiB], buffer_sec[64 * KiB]; + struct region_device *rdev; + void *data; + int ret; + + const struct spi_flash *flash = boot_device_spi_flash(); + if (!flash) + return -1; + + ret = boot_device_rw_subregion(sub, &prim); + if (ret) + return ret; + + ret = backup_boot_device_rw_subregion(sub, &sec); + if (ret) + return ret; + + /* Set target and source for transfer */ + rdev = direction_prim_to_sec ? &sec : &prim; + data = direction_prim_to_sec ? buffer_prim : buffer_sec; + + size_t remaining = region_device_sz(&prim); + size_t offset = 0, written = 0; + do { + size_t chunk = MIN(remaining, ARRAY_SIZE(buffer_prim)); + chunk = MIN(chunk, flash->sector_size); + + if (rdev_readat(&prim, buffer_prim, offset, chunk) != chunk) + return -1; + if (rdev_readat(&sec, buffer_sec, offset, chunk) != chunk) + return -1; + + if (memcmp(buffer_prim, buffer_sec, chunk) != 0) { + if (rdev_eraseat(rdev, offset, chunk) != chunk) + return -1; + if (rdev_writeat(rdev, data, offset, chunk) != chunk) + return -1; + written += chunk; + } + + remaining -= chunk; + offset += chunk; + } while (remaining); + + printk(BIOS_INFO, "%s: Synced %zu bytes from SPI flash %s->%s\n", __func__, + written, direction_prim_to_sec ? "PRIM" : "SEC", + direction_prim_to_sec ? "SEC" : "PRIM"); + return 0; +} diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index fc182fca5f0..2cf5cf61995 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,11 @@ static const char *remapping[8] = { void show_spi_speeds_and_modes(void) { + if (psp_get_hsti_state_rom_armor_enforced()) { + printk(BIOS_DEBUG, "%s: Skipped as ROM Armor active\n", __func__); + return; + } + uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG); uint32_t val32 = spi_read32(SPI_CNTRL0); uint8_t val8 = fch_spi_rom_remapping(); @@ -107,11 +113,18 @@ static void fch_spi_set_read_mode(u32 mode) uint8_t fch_spi_rom_remapping(void) { + assert(!psp_get_hsti_state_rom_armor_enforced()); + return spi_read8(SPI_ROM_PAGE) & SPI_ROM_PAGE_SEL; } void fch_spi_config_modes(void) { + if (psp_get_hsti_state_rom_armor_enforced()) { + printk(BIOS_DEBUG, "%s: Skipped as ROM Armor active\n", __func__); + return; + } + uint8_t read_mode, fast_speed; uint8_t normal_speed = CONFIG_NORMAL_READ_SPI_SPEED; uint8_t alt_speed = CONFIG_ALT_SPI_SPEED; diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 114c7332441..1f28b4272f0 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -172,7 +173,6 @@ void fch_spi_restore_registers(void) static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { - size_t count; uint8_t cmd; uint8_t *bufin = din; const uint8_t *bufout = dout; @@ -205,14 +205,12 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_write8(SPI_TX_BYTE_COUNT, bytesout); spi_write8(SPI_RX_BYTE_COUNT, bytesin); - for (count = 0; count < bytesout; count++) - spi_write8(SPI_FIFO + count, bufout[count]); + spi_write_block(SPI_FIFO, bufout, bytesout); if (execute_command()) return -1; - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read8(SPI_FIFO + count + bytesout); + spi_read_block(SPI_FIFO + bytesout, bufin, bytesin); return 0; } @@ -342,6 +340,11 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { uint8_t reg8; + if (psp_get_hsti_state_rom_armor_enforced()) { + printk(BIOS_ERR, "PSP ROM Armor is enforced, cannot access SPI flash directly\n"); + return -1; + } + if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) { if (ENV_RAMSTAGE || ENV_SMM) { reg8 = spi_read8(SPI_MISC_CNTRL); diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c index c5d7123b099..21fd5e63947 100644 --- a/src/soc/amd/common/block/spi/fch_spi_util.c +++ b/src/soc/amd/common/block/spi/fch_spi_util.c @@ -40,6 +40,26 @@ uint32_t spi_read32(uint8_t reg) return read32p(spi_get_bar() + reg); } +/* Reads in a block from SPI MMIO. Uses DWORD when possible. */ +void spi_read_block(uint8_t reg, uint8_t *dest, size_t len) +{ + uintptr_t addr = spi_get_bar() + reg; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS)) { + /* DWORD align */ + for (; len && !IS_ALIGNED(addr, 4); len--, dest++, addr++) + *dest = read8p(addr); + + /* Read in DWORDs */ + for (; len >= 4; len -= 4, dest += 4, addr += 4) + *((uint32_t *)dest) = read32p(addr); + } + + /* Read remainder */ + for (; len; len--, dest++, addr++) + *dest = read8p(addr); +} + void spi_write8(uint8_t reg, uint8_t val) { write8p(spi_get_bar() + reg, val); @@ -54,3 +74,23 @@ void spi_write32(uint8_t reg, uint32_t val) { write32p(spi_get_bar() + reg, val); } + +/* Writes out a block to SPI MMIO. Uses DWORD when possible. */ +void spi_write_block(uint8_t reg, const uint8_t *src, size_t len) +{ + uintptr_t addr = spi_get_bar() + reg; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS)) { + /* DWORD align */ + for (; len && !IS_ALIGNED(addr, 4); len--, src++, addr++) + write8p(addr, *src); + + /* Write out DWORDs */ + for (; len >= 4; len -= 4, src += 4, addr += 4) + write32p(addr, *((uint32_t *)src)); + } + + /* Write remainder */ + for (; len; len--, src++, addr++) + write8p(addr, *src); +} diff --git a/src/soc/amd/common/block/spi/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c index 6a917195ce7..6ca377e88af 100644 --- a/src/soc/amd/common/block/spi/mmap_boot.c +++ b/src/soc/amd/common/block/spi/mmap_boot.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #if CONFIG_ROM_SIZE >= (16 * MiB) @@ -22,8 +23,11 @@ const struct region_device *boot_device_ro(void) /* * The following code assumes that ROM2 is mapped at flash offset 0. This is the default * configuration currently enforced by soft-straps. + * When ROM Armor is enabled, don't call fch_spi_rom_remapping() + * because the SPIBAR is no longer accessible. */ - if (fch_spi_rom_remapping() != 0) + const bool rom_armor = psp_get_hsti_state_rom_armor_enforced(); + if (!rom_armor && fch_spi_rom_remapping() != 0) die("Non default SPI ROM remapping is not supported!"); return &boot_dev.rdev; diff --git a/src/soc/amd/common/block/spi/mmap_boot_rom3.c b/src/soc/amd/common/block/spi/mmap_boot_rom3.c index bda3a4d92e1..8f98fa7a97d 100644 --- a/src/soc/amd/common/block/spi/mmap_boot_rom3.c +++ b/src/soc/amd/common/block/spi/mmap_boot_rom3.c @@ -4,6 +4,8 @@ #include #include #include +#include +#include enum window_type { /* Fixed decode window of max 16MiB size just below 4G boundary */ @@ -80,6 +82,17 @@ static void bios_mmap_init(void) if (init_done) return; + const bool rom_armor = psp_get_hsti_state_rom_armor_enforced(); + /* + * The following code assumes that ROM2 is mapped at flash offset 0 and + * that the ROM3 16MByte chunks are linear (0-1-2-3). This is the default + * configuration currently enforced by soft-straps. + * When ROM Armor is enabled, don't call fch_spi_rom_remapping() + * because the SPIBAR is no longer accessible. + */ + if (!rom_armor && fch_spi_rom_remapping() != 0) + die("Non default SPI ROM remapping is not supported!"); + /* * By default, fixed decode window (maximum size 16MiB) is mapped just * below the 4G boundary. This window maps the bottom part of the BIOS diff --git a/src/soc/amd/common/block/spi/rom_armor_boot_device_rw_nommap.c b/src/soc/amd/common/block/spi/rom_armor_boot_device_rw_nommap.c new file mode 100644 index 00000000000..fe531377b08 --- /dev/null +++ b/src/soc/amd/common/block/spi/rom_armor_boot_device_rw_nommap.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static struct spi_flash sfg; +static bool sfg_init_done; + +__weak int boot_device_spi_cs(void) +{ + return 0; /* Default to chip select 0 */ +} + +/* SPI API is used in early stages and as long as Rom Armor isn't active */ +static ssize_t spi_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + if (spi_flash_read(&sfg, offset, size, b)) + return -1; + + return size; +} + +static ssize_t spi_writeat(const struct region_device *rd, const void *b, + size_t offset, size_t size) +{ + if (spi_flash_write(&sfg, offset, size, b)) + return -1; + + return size; +} + +static ssize_t spi_eraseat(const struct region_device *rd, + size_t offset, size_t size) +{ + if (spi_flash_erase(&sfg, offset, size)) + return -1; + + return size; +} + +static const struct region_device_ops spi_ops = { + .readat = spi_readat, + .writeat = spi_writeat, + .eraseat = spi_eraseat, +}; + +static const struct region_device spi_rw = + REGION_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE); + +static void boot_device_rw_init(void) +{ + const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; + const int cs = boot_device_spi_cs(); + + if (sfg_init_done == true) + return; + + /* Ensure any necessary setup is performed by the drivers. */ + spi_init(); + + if (!spi_flash_probe(bus, cs, &sfg)) + sfg_init_done = true; +} + +const struct region_device *boot_device_rw(void) +{ + if (ENV_SMM) { + /* Could return SPI drivers here, but that would increase SMM size. + * ROM Armor is enforced right after SMM has been set up, so it's + * unlikely that something need R/W access to SPI flash before it + * is enforced. + */ + if (!psp_get_hsti_state_rom_armor_enforced()) + return NULL; + + return &rom_armor_smm_rw; + } else if (ENV_RAMSTAGE) { + /* Probe for the SPI flash device if not already done. */ + if (!psp_get_hsti_state_rom_armor_enforced()) { + /* ROM Armor not active, can use SPI controller directly */ + boot_device_rw_init(); + + if (sfg_init_done != true) + return NULL; + + return &spi_rw; + } + /* ROM Armor active, use APM interface */ + return &rom_armor_apm_call_rw; + } else { + /* ROM Armor not active, can use SPI controller directly */ + boot_device_rw_init(); + + if (sfg_init_done != true) + return NULL; + + return &spi_rw; + } +} + +const struct spi_flash *boot_device_spi_flash(void) +{ + if (!psp_get_hsti_state_rom_armor_enforced()) + boot_device_rw_init(); + + if (sfg_init_done != true) + return NULL; + + return &sfg; +} + +int boot_device_wp_region(const struct region_device *rd, + const enum bootdev_prot_type type) +{ + uint32_t ctrlr_pr; + + if (psp_get_hsti_state_rom_armor_enforced()) { + printk(BIOS_ERR, "%s: ROM Armor is active. Cannot access SPI flash\n"); + return -1; + } + + /* Ensure boot device has been initialized at least once. */ + boot_device_init(); + + const struct spi_flash *boot_dev = boot_device_spi_flash(); + + if (boot_dev == NULL) + return -1; + + if (type == MEDIA_WP) { + if (spi_flash_is_write_protected(boot_dev, + region_device_region(rd)) != 1) { + enum spi_flash_status_reg_lockdown lock = + SPI_WRITE_PROTECTION_REBOOT; + if (CONFIG(BOOTMEDIA_SPI_LOCK_REBOOT)) + lock = SPI_WRITE_PROTECTION_REBOOT; + else if (CONFIG(BOOTMEDIA_SPI_LOCK_PIN)) + lock = SPI_WRITE_PROTECTION_PIN; + else if (CONFIG(BOOTMEDIA_SPI_LOCK_PERMANENT)) + lock = SPI_WRITE_PROTECTION_PERMANENT; + + return spi_flash_set_write_protected(boot_dev, + region_device_region(rd), lock); + } + + /* Already write protected */ + return 0; + } + + switch (type) { + case CTRLR_WP: + ctrlr_pr = WRITE_PROTECT; + break; + case CTRLR_RP: + ctrlr_pr = READ_PROTECT; + break; + case CTRLR_RWP: + ctrlr_pr = READ_WRITE_PROTECT; + break; + default: + return -1; + } + + return spi_flash_ctrlr_protect_region(boot_dev, + region_device_region(rd), ctrlr_pr); +} diff --git a/src/soc/amd/common/fsp/Makefile.mk b/src/soc/amd/common/fsp/Makefile.mk index fb78f529252..8f9d2ef898e 100644 --- a/src/soc/amd/common/fsp/Makefile.mk +++ b/src/soc/amd/common/fsp/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + romstage-y += fsp_memmap.c romstage-y += fsp_reset.c romstage-y += fsp_romstage.c diff --git a/src/soc/amd/common/fsp/fsp-acpi.c b/src/soc/amd/common/fsp/fsp-acpi.c index d30456ddf49..529e1f70dfe 100644 --- a/src/soc/amd/common/fsp/fsp-acpi.c +++ b/src/soc/amd/common/fsp/fsp-acpi.c @@ -35,7 +35,7 @@ static unsigned long add_agesa_fsp_acpi_table(guid_t guid, const char *name, acp return current; } - printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + printk(BIOS_DEBUG, "ACPI: * %s (AGESA).\n", name); memcpy(table, data->hob_payload, data->table_size_in_bytes); diff --git a/src/soc/amd/common/pi/amd_late_init.c b/src/soc/amd/common/pi/amd_late_init.c index f797e4137ad..85c7c3a83be 100644 --- a/src/soc/amd/common/pi/amd_late_init.c +++ b/src/soc/amd/common/pi/amd_late_init.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/psp_verstage/boot_dev.c b/src/soc/amd/common/psp_verstage/boot_dev.c index 6ff1e2b713c..dc727f9f2aa 100644 --- a/src/soc/amd/common/psp_verstage/boot_dev.c +++ b/src/soc/amd/common/psp_verstage/boot_dev.c @@ -19,7 +19,7 @@ static void *boot_dev_mmap(const struct region_device *rd, size_t offset, size_t void *mapping = NULL; uint32_t ret; - mdev = container_of(rd, __typeof__(*mdev), rdev); + mdev = container_of(rd, typeof(*mdev), rdev); if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) return &(mdev->base[offset]); @@ -65,7 +65,7 @@ static ssize_t boot_dev_dma_readat(const struct region_device *rd, void *dest, size_t offset, size_t size) { size_t memcpy_size = ALIGN_UP((uintptr_t)dest, DEST_BUF_ALIGNMENT) - (uintptr_t)dest; - const struct mem_region_device *mdev = container_of(rd, __typeof__(*mdev), rdev); + const struct mem_region_device *mdev = container_of(rd, typeof(*mdev), rdev); int ret; if (memcpy_size > size) @@ -94,7 +94,7 @@ static ssize_t boot_dev_dma_readat(const struct region_device *rd, void *dest, static ssize_t boot_dev_readat(const struct region_device *rd, void *dest, size_t offset, size_t size) { - const struct mem_region_device *mdev = container_of(rd, __typeof__(*mdev), rdev); + const struct mem_region_device *mdev = container_of(rd, typeof(*mdev), rdev); if (CONFIG(PSP_VERSTAGE_CCP_DMA)) return boot_dev_dma_readat(rd, dest, offset, size); diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 4754af185f5..522383322da 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -27,6 +27,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_HAS_ESPI1 select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU @@ -42,6 +43,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk index 162180dec46..335c5902adf 100644 --- a/src/soc/amd/genoa_poc/Makefile.mk +++ b/src/soc/amd/genoa_poc/Makefile.mk @@ -112,6 +112,9 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_DEBUG_AMDFWTOOL) \ @@ -126,6 +129,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_BIOS_FWCOMPRESS) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize 0x1000000 @@ -141,7 +145,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ --location $(CONFIG_AMD_FWM_POSITION) \ - --multilevel \ --output $@ # @@ -154,7 +157,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) endif diff --git a/src/soc/amd/genoa_poc/acpi/mmio.asl b/src/soc/amd/genoa_poc/acpi/mmio.asl index 85bb12b0215..52fa4fab9da 100644 --- a/src/soc/amd/genoa_poc/acpi/mmio.asl +++ b/src/soc/amd/genoa_poc/acpi/mmio.asl @@ -12,7 +12,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Name (_STA, 0xb) } diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index d45d3176053..799effc0ba0 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -67,5 +67,5 @@ struct device_operations genoa_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = genoa_domain_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 70a1fc63310..b9161938e63 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -10,7 +10,7 @@ config SOC_AMD_GLINDA_BASE select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI select DRIVERS_USB_PCI_XHCI - select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_M_ZSTD if !ASYNC_FILE_LOADING select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB @@ -23,8 +23,6 @@ config SOC_AMD_GLINDA_BASE select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING - select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK - select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select RTC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct @@ -58,6 +56,7 @@ config SOC_AMD_GLINDA_BASE select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct @@ -70,7 +69,8 @@ config SOC_AMD_GLINDA_BASE select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct @@ -88,9 +88,7 @@ config SOC_AMD_GLINDA_BASE select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI select HAVE_X86_64_SUPPORT help AMD Glinda support @@ -114,6 +112,18 @@ config CHIPSET_DEVICETREE string default "soc/amd/glinda/chipset.cb" +config VGA_BIOS_FILE + string + default "3rdparty/amd_blobs/strix_krackan/KRK2E_GENERIC_vbios.sbin" if SOC_AMD_FAEGAN + default "3rdparty/amd_blobs/strix_krackan/StrixKrackan_Generic_VBIOS.sbin" + +config VGA_BIOS_ID + string + default "1002,1902" if SOC_AMD_FAEGAN + default "1002,150e" + help + The default VGA BIOS PCI vendor/device ID of the GPU and VBIOS. + config CPU_PT_ROM_MAP_GB default 1024 @@ -142,27 +152,6 @@ config PSP_APOB_DRAM_SIZE hex default 0x40000 -config PSP_SHAREDMEM_BASE - hex - default 0x2041000 if VBOOT - default 0x0 - help - This variable defines the base address in DRAM memory where PSP copies - the vboot workbuf. This is used in the linker script to have a static - allocation for the buffer as well as for adding relevant entries in - the BIOS directory table for the PSP. - -config PSP_SHAREDMEM_SIZE - hex - default 0x8000 if VBOOT - default 0x0 - help - Sets the maximum size for the PSP to pass the vboot workbuf and - any logs or timestamps back to coreboot. This will be copied - into main memory by the PSP and will be available when the x86 is - started. The workbuf's base depends on the address of the reset - vector. - config PRE_X86_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -175,10 +164,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config CBFS_MCACHE_SIZE - hex - default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK - config C_ENV_BOOTBLOCK_SIZE hex default 0x20000 @@ -199,6 +184,9 @@ config ROMSTAGE_SIZE help Sets the size of DRAM allocation for romstage in linker script. +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/glinda" + config FSP_M_ADDR hex default 0x20E0000 @@ -218,22 +206,6 @@ config FSP_TEMP_RAM_SIZE help The amount of coreboot-allocated heap and stack usage by the FSP. -config VERSTAGE_ADDR - hex - depends on VBOOT_SEPARATE_VERSTAGE - default 0x21A0000 - help - Sets the address in DRAM where verstage should be loaded if running - as a separate stage on x86. - -config VERSTAGE_SIZE - hex - depends on VBOOT_SEPARATE_VERSTAGE - default 0x80000 - help - Sets the size of DRAM allocation for verstage in linker script if - running as a separate stage on x86. - config ASYNC_FILE_LOADING bool "Loads files from SPI asynchronously" select COOP_MULTITASKING @@ -249,11 +221,6 @@ config CBFS_CACHE_SIZE hex default 0x40000 if CBFS_PRELOAD -config RO_REGION_ONLY - string - depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A - default "apu/amdfw" - config ECAM_MMCONF_BASE_ADDRESS default 0xE0000000 @@ -325,9 +292,11 @@ menu "PSP Configuration Options" config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" - default "src/soc/amd/glinda/fw.cfg" + default "src/soc/amd/glinda/fw_krackan2e_lpddr5.cfg" if SOC_AMD_FAEGAN + default "src/soc/amd/glinda/fw_stx_lpddr5.cfg" help Specify the path/location of AMD PSP Firmware config file. + By default build a LPDDR5 board. config PSP_DISABLE_POSTCODES bool "Disable PSP post codes" @@ -385,82 +354,54 @@ config PSP_SOFTFUSE_BITS See #55758 (NDA) for additional bit definitions. -config PSP_VERSTAGE_FILE - string "Specify the PSP_verstage file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - default "\$(obj)/psp_verstage.bin" - help - Add psp_verstage file to the build & PSP Directory Table - -config PSP_VERSTAGE_SIGNING_TOKEN - string "Specify the PSP_verstage Signature Token file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - default "" - help - Add psp_verstage signature token to the build & PSP Directory Table - config PSPV2_MBOX_CMD_OFFSET - hex default 0x10970 endmenu -config VBOOT - select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - -config VBOOT_STARTS_BEFORE_BOOTBLOCK - def_bool n - depends on VBOOT - select ARCH_VERSTAGE_ARMV7 +menu "RAS Config Options" +choice + prompt "PCIe AER Report Mechanism" + depends on SOC_AMD_FAEGAN + default AMD_PCIE_AER_OS_FIRST_HANDLING help - Runs verstage on the PSP. Only available on - certain ChromeOS branded parts from AMD. + Choose a PCIe AER Report Mechanism. -config VBOOT_HASH_BLOCK_SIZE - hex - default 0x9000 - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - help - Because the bulk of the time in psp_verstage to hash the RO cbfs is - spent in the overhead of doing svc calls, increasing the hash block - size significantly cuts the verstage hashing time as seen below. - - 4k takes 180ms - 16k takes 44ms - 32k takes 33.7ms - 36k takes 32.5ms - There's actually still room for an even bigger stack, but we've - reached a point of diminishing returns. - -config CMOS_RECOVERY_BYTE - hex - default 0x51 - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - help - If the workbuf is not passed from the PSP to coreboot, set the - recovery flag and reboot. The PSP will read this byte, mark the - recovery request in VBNV, and reset the system into recovery mode. +config AMD_PCIE_AER_PFEH_FIRMWARE_FIRST_REPORTING + bool "PFEH-based Firmware First reporting" - This is the byte before the default first byte used by VBNV - (0x26 + 0x0E - 1) +config AMD_PCIE_AER_OS_FIRST_HANDLING + bool "OS First handling" -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +config AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING + bool "Firmware First handling through SMI" +endchoice -config RWA_REGION_ONLY - string - default "apu/amdfw_a" +choice + prompt "AMD NBIO Ras Control V2" + depends on SOC_AMD_FAEGAN + default AMD_NBIO_RAS_MCA_REPORTING if SOC_AMD_FAEGAN + default AMD_NBIO_RAS_DISABLE help - Add a space-delimited list of filenames that should only be in the - RW-A section. + Choose an AMD NBIO RAS control option. -config RWB_REGION_ONLY - string - default "apu/amdfw_b" - help - Add a space-delimited list of filenames that should only be in the - RW-B section. +config AMD_NBIO_RAS_DISABLE + bool "Disable NBIO Ras Control" -endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +config AMD_NBIO_RAS_MCA_REPORTING + bool "MCA reporting" + +config AMD_NBIO_RAS_LEGACY_MODE + bool "Legacy Mode" +endchoice + +config AMD_PCIE_ECRC_ENABLEMENT + bool "PCIe ECRC Enablement" + depends on SOC_AMD_FAEGAN + default y if SOC_AMD_FAEGAN + default n + help + Enable/Disable PCIe ECRC support. +endmenu endif # SOC_AMD_GLINDA_BASE diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk index 1a71769701b..c4781ed2014 100644 --- a/src/soc/amd/glinda/Makefile.mk +++ b/src/soc/amd/glinda/Makefile.mk @@ -5,8 +5,6 @@ ifeq ($(CONFIG_SOC_AMD_GLINDA_BASE),y) -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - # Beware that all-y also adds the compilation unit to verstage on PSP all-y += aoac.c all-y += config.c @@ -20,8 +18,6 @@ all_x86-y += uart.c bootblock-y += early_fch.c bootblock-y += espi_util.c -verstage-y += espi_util.c - romstage-y += fsp_m_params.c ramstage-y += acpi.c @@ -41,23 +37,21 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/glinda/include CPPFLAGS_common += -I$(src)/soc/amd/glinda/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/glinda -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common -# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough -ifeq ($(CONFIG_CBFS_VERIFICATION),y) +# Target an offset into the CBFS. AMDFWTOOL will align it again and +# pad the space between the CBFS file header and the directory table. # 0x80 accounts for the cbfs_file struct + filename + metadata structs AMD_FW_AB_POSITION := 0x80 -else # ($(CONFIG_CBFS_VERIFICATION), y) -# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute -AMD_FW_AB_POSITION := 0x40 -endif # ($(CONFIG_CBFS_VERIFICATION), y) -GLINDA_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) +ifeq ($(CONFIG_PSP_AB_RECOVERY), y) +GLINDA_FW_A_RECOVERY=$(if $(call get_fmap_value,FMAP_SECTION_RECOVERY_A_START), $(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_A_START) $(AMD_FW_AB_POSITION)), \ + $(error "CONFIG_PSP_AB_RECOVERY is enabled but region RECOVERY_A is not defined in the flash map")) -GLINDA_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) +GLINDA_FW_B_RECOVERY=$(if $(call get_fmap_value,FMAP_SECTION_RECOVERY_B_START), $(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_B_START) $(AMD_FW_AB_POSITION)), \ + $(error "CONFIG_PSP_AB_RECOVERY is enabled but region RECOVERY_B is not defined in the flash map")) +endif # # PSP Directory Table items @@ -104,11 +98,6 @@ PSP_RPMC_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_SIZE) # type = 0x55 SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) -else -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool @@ -133,25 +122,12 @@ APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)$(CONFIG_SMMSTORE),yy) +# Rom Armor needs the SMM Store region to be whitelisted +PSP_BIOS_NV_ST_BASE=$(call get_fmap_value,FMAP_SECTION_SMMSTORE_START) +PSP_BIOS_NV_ST_SIZE=$(call get_fmap_value,FMAP_SECTION_SMMSTORE_SIZE) endif -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -SIGNED_AMDFW_A_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) -SIGNED_AMDFW_B_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) -SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed -SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed -endif # CONFIG_SEPARATE_SIGNED_PSPFW - # Helper function to return a value with given bit set # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) @@ -171,9 +147,6 @@ OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size) OPT_PSP_RPMC_NVRAM_BASE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_BASE), --rpmc-nvram-base) OPT_PSP_RPMC_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_SIZE), --rpmc-nvram-size) -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) @@ -183,27 +156,26 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) -OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) -OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) - OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) -# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant -OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) + +OPT_BIOS_NV_ST_BASE=$(call add_opt_prefix, $(PSP_BIOS_NV_ST_BASE), --variable-nvram-base) +OPT_BIOS_NV_ST_SIZE=$(call add_opt_prefix, $(PSP_BIOS_NV_ST_SIZE), --variable-nvram-size) + +OPT_RECOVERY_AB=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-ab) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-a-location $(call _tohex, $(GLINDA_FW_A_RECOVERY))) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-b-location $(call _tohex, $(GLINDA_FW_B_RECOVERY))) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ @@ -221,18 +193,17 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ --load-s0i3 \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_RECOVERY_AB) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) + $(OPT_BIOS_NV_ST_BASE) \ + $(OPT_BIOS_NV_ST_SIZE) \ + $(OPT_BIOS_FWCOMPRESS) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ $(DEP_FILES) \ $(AMDFWTOOL) \ @@ -244,12 +215,29 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) + +$(obj)/amdfw.rom.ra: $(obj)/amdfw.rom +$(obj)/amdfw.rom.rb: $(obj)/amdfw.rom + +regions-for-file-apu/amdfw_ra = BOOTBLOCK +regions-for-file-apu/amdfw_rb = BOOTBLOCK_B + +cbfs-files-y += apu/amdfw_ra +apu/amdfw_ra-file := $(obj)/amdfw.rom.ra +apu/amdfw_ra-position := $(AMD_FW_AB_POSITION) +apu/amdfw_ra-type := amdfw + +cbfs-files-y += apu/amdfw_rb +apu/amdfw_rb-file := $(obj)/amdfw.rom.rb +apu/amdfw_rb-position := $(AMD_FW_AB_POSITION) +apu/amdfw_rb-type := amdfw + +endif # # Extracts everything from the ELF's first PT_LOAD area and compresses it. # This discards everything before PT_LOAD, every symbol, debug information @@ -260,59 +248,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_A_POSITION) \ - $(OPT_SIGNED_AMDFW_A_FILE) \ - --location $(call _tohex,$(GLINDA_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_B_POSITION) \ - $(OPT_SIGNED_AMDFW_B_FILE) \ - --location $(call _tohex,$(GLINDA_FW_B_POSITION)) \ - --anywhere \ - --output $@ - - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom - @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ - -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ - -n apu/amdfw_b_hash -t raw -endif # CONFIG_SEPARATE_SIGNED_PSPFW -endif + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) endif # ($(CONFIG_SOC_AMD_GLINDA_BASE),y) diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index dbe610cb891..5cb8df46acc 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -47,6 +47,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | ACPI_FADT_PCI_EXPRESS_WAKE | diff --git a/src/soc/amd/glinda/acpi/mmio.asl b/src/soc/amd/glinda/acpi/mmio.asl index 75b99703ec7..c592cb3bc67 100644 --- a/src/soc/amd/glinda/acpi/mmio.asl +++ b/src/soc/amd/glinda/acpi/mmio.asl @@ -15,7 +15,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index e227f415993..f6789419d8d 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -35,7 +35,7 @@ struct device_operations glinda_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index d414afee4c7..2263b682a2b 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #include #include #include @@ -14,6 +12,26 @@ static struct device_operations cpu_dev_ops = { .init = amd_cpu_init, }; +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; +} + +u8 smbios_cache_speed(u8 level) +{ + return 1; +} + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, { X86_VENDOR_AMD, GLINDA_B0_CPUID, CPUID_ALL_STEPPINGS_MASK }, @@ -21,7 +39,7 @@ static struct cpu_device_id cpu_table[] = { CPU_TABLE_END }; -static const struct cpu_driver zen_2_3 __cpu_driver = { +static const struct cpu_driver zen_5 __cpu_driver = { .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 1e0b08ced4f..92eb8632017 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -138,8 +138,13 @@ static void cgpll_clock_gate_init(void) t = misc_read32(MISC_CLKGATEDCNTL); t |= ALINKCLK_GATEOFFEN; t |= BLINKCLK_GATEOFFEN; - t |= XTAL_PAD_S0I3_TURNOFF_EN; - t |= XTAL_PAD_S3_TURNOFF_EN; + if (CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX)) + t &= ~XTAL_PAD_S0I3_TURNOFF_EN; + else + t |= XTAL_PAD_S0I3_TURNOFF_EN; + if (!CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S3)) + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; misc_write32(MISC_CLKGATEDCNTL, t); diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index ff5f04c7f2c..cff9b01ae20 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -160,6 +160,31 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda)); mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda)); + /* Faegan only: RAS Config Options */ + if (CONFIG(SOC_AMD_FAEGAN)) { + if (CONFIG(AMD_PCIE_AER_OS_FIRST_HANDLING)) + mcfg->amd_pcie_aer_report_mechanism = 1; + else if (CONFIG(AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING)) + mcfg->amd_pcie_aer_report_mechanism = 2; + else + mcfg->amd_pcie_aer_report_mechanism = 0; + + if (CONFIG(AMD_NBIO_RAS_MCA_REPORTING)) + mcfg->amd_nbio_ras_controlv2 = 1; + else if (CONFIG(AMD_NBIO_RAS_LEGACY_MODE)) + mcfg->amd_nbio_ras_controlv2 = 2; + else + mcfg->amd_nbio_ras_controlv2 = 0; + + mcfg->pcie_ecrc_enablement = CONFIG(AMD_PCIE_ECRC_ENABLEMENT); + printk(BIOS_SPEW, "mcfg->amd_pcie_aer_report_mechanism %x\n", + mcfg->amd_pcie_aer_report_mechanism); + printk(BIOS_SPEW, "mcfg->amd_nbio_ras_controlv2 %x\n", + mcfg->amd_nbio_ras_controlv2); + printk(BIOS_SPEW, "mcfg->pcie_ecrc_enablement %x\n", + mcfg->pcie_ecrc_enablement); + } + if (config->usb_phy_custom) { /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; diff --git a/src/soc/amd/glinda/fw.cfg b/src/soc/amd/glinda/fw.cfg deleted file mode 100644 index 88f79db453e..00000000000 --- a/src/soc/amd/glinda/fw.cfg +++ /dev/null @@ -1,39 +0,0 @@ -# PSP fw config file - -FIRMWARE_LOCATION 3rdparty/amd_blobs/glinda/psp -SOC_NAME Strix - -# type file -AMD_PUBKEY_FILE TypeId0x00_Root.tkn -PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader1.sbin -PSPSECUREOS_FILE TypeId0x02_PspOS.sbin -PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware.sbin -PSPSECUREDEBUG_FILE TypeId0x09_SDU.stkn -PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv.csbin -PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2.sbin -PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock.sbin -PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg.sbin -PSP_IKEK_FILE TypeId0x21_PspiKek.bin -PSP_SECG0_FILE TypeId0x24_SecPolicy.sbin -PSP_MP2FW0_FILE TypeId0x25_Mp2Fw.sbin -AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver.sbin -PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv.sbin -PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_LPDDR5.sbin -VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader.sbin -SECURE_POLICY_L1_FILE TypeId0x45_SecPolicytOS.sbin -UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb.sbin -KEYDBBL_FILE TypeId0x50_KeyDbBl.sbin -KEYDB_TOS_FILE TypeId0x51_KeyDbTos.sbin -SPL_TABLE_FILE TypeId0x55_SplTableBl.sbin -MSMU_FILE TypeId0x5A_Msmu.sbin -SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_Dual66.sbin -DMCUB_FILE TypeId0x71_DmcubFw.sbin -PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2.sbin -TA_IKEK_FILE TypeId0x8D_IkekTa.bin - -# BDT -PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_Lpddr5Imem1.csbin -PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_Lpddr5Dmem1.csbin -PSP_PMUI_FILE_SUB0_INS2 TypeId0x64_Appb_Lpddr5Imem2.csbin -PSP_PMUD_FILE_SUB0_INS2 TypeId0x65_Appb_Lpddr5Dmem2.csbin -PSP_MP2CFG_FILE TypeId0x6a_Mp2FwConfig.sbin diff --git a/src/soc/amd/glinda/fw_krackan2e_lpddr5.cfg b/src/soc/amd/glinda/fw_krackan2e_lpddr5.cfg new file mode 100644 index 00000000000..6b337c3a745 --- /dev/null +++ b/src/soc/amd/glinda/fw_krackan2e_lpddr5.cfg @@ -0,0 +1,71 @@ +# PSP fw config file +FIRMWARE_LOCATION 3rdparty/amd_blobs/strix_krackan/PSP +SOC_NAME Krackan2e + +# type file +# PSP +PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_STXKRK.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_STXKRK.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_STXKRK.sbin +PSP_SMUFW1_SUB1_FILE TypeId0x08_SmuFirmware_KRK.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_STX.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_STXKRK.sbin +PSP_SMUFW2_SUB1_FILE TypeId0x12_SmuFirmware2_KRK.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_STXKRK.sbin +PSP_BOOT_DRIVER_FILE TypeId0x1B_BootDriver_STXKRK.sbin +PSP_SOC_DRIVER_FILE TypeId0x1C_SocDriver_STXKRK.sbin +PSP_DEBUG_DRIVER_FILE TypeId0x1D_DebugDriver_STXKRK.sbin + +PSP_INTERFACE_DRIVER_FILE TypeId0x1F_InterfaceDriver_STXKRK.sbin +PSP_TEEIPKEY_FILE TypeId0x15_drv_ipkeymgr_STXKRK.sbin + +PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_STX.sbin +PSP_HW_IPCFG_FILE_SUB1 TypeId0x20_HwIpCfg_KRK.sbin +PSP_HW_IPCFG_FILE_SUB2 TypeId0x20_HwIpCfg_KRK2e.sbin +PSP_IKEK_FILE TypeId0x21_ikek_STX_PROD.sbin + +PSP_SECG0_FILE TypeId0x24_SecPolicy_STXKRK.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_STXKRK.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_STXKRK.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_STXKRK_LPDDR5.sbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_STXKRK.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecPolicytOS_STXKRK.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_STXKRK.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_STXKRK.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_STXKRK.sbin +MSMU_FILE_SUB1_FILE TypeId0x5A_Msmu_Lpddr5_STXB0KRK.csbin +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_STX.sbin +MPIO_FILE TypeId0x5D_MPIO_STX.sbin +DMCUB_FILE TypeId0x71_DmcubFw_STXKRK.csbin +PSP_RIB_FILE_SUB2 TypeId0x76_DfRib_KRK2E.sbin +AMF_SRAM_FILE TypeId0x85_MPMSram_STXKRK.sbin +AMF_DRAM_FILE_INS0 TypeId0x86_MPMDram_STXKRK.sbin +AMF_MFD_FILE TypeId0x89_MFD.sbin +MPCCX_FILE_SUB1_FILE TypeId0x90_MPCCX_KRK.csbin +LSDMA_FILE TypeId0x94_LSDMA_STX.sbin +FEATURE_TABLE_FILE TypeId0x98_AIM-T_Enable.bin +SRAM_FW_EXT_FILE TypeId0x9D_Overlay_STX.sbin +TA_IKEK_FILE TypeId0x8d_iKEK_TA_STX.bin +PSP_C20MP_FILE TypeId0x95_C20MP_STX.sbin +MINIMSMU_FILE_SUB1_FILE TypeId0x9A_MiniMsmu_Lpddr5_STXB0KRK.csbin + +PSP_GFX_IMMU_FILE_0_SUB1 TypeId0x9B_GFX_IMU_LX7_IRAM_uCode_KRK.sbin +PSP_GFX_IMMU_FILE_1_SUB1 TypeId0x9C_GFX_IMU_LX7_DRAM_uCode_KRK.sbin + +PSP_USB_DP TypeId0xA4_USB_DP_STX.sbin +PSP_USB_SS TypeId0xA5_USB_SSP_STX.sbin +PSP_USB_4 TypeId0xA6_USB4_STX.sbin + +## BDT + +PSP_PMUI_FILE_SUB0_INS7 TypeId0x64_Appb_STX_Lpddr5XImem7.csbin +PSP_PMUI_FILE_SUB0_INSB TypeId0x64_Appb_STX_Lpddr5XImem11.csbin +PSP_PMUI_FILE_SUB0_INSC TypeId0x64_Appb_STX_Lpddr5XImem12.csbin +PSP_PMUI_FILE_SUB0_INSD TypeId0x64_Appb_STX_Lpddr5XImem13.csbin + +PSP_PMUD_FILE_SUB0_INS7 TypeId0x65_Appb_STX_Lpddr5XDmem7.csbin +PSP_PMUD_FILE_SUB0_INSB TypeId0x65_Appb_STX_Lpddr5XDmem11.csbin +PSP_PMUD_FILE_SUB0_INSC TypeId0x65_Appb_STX_Lpddr5XDmem12.csbin +PSP_PMUD_FILE_SUB0_INSD TypeId0x65_Appb_STX_Lpddr5XDmem13.csbin + +PSP_MP2CFG_FILE TypeId0x6a_Mp2FwConfig_STX.sbin diff --git a/src/soc/amd/glinda/fw_stx_lpddr5.cfg b/src/soc/amd/glinda/fw_stx_lpddr5.cfg new file mode 100644 index 00000000000..22168c6fd41 --- /dev/null +++ b/src/soc/amd/glinda/fw_stx_lpddr5.cfg @@ -0,0 +1,71 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/strix_krackan/PSP +SOC_NAME Strix + +# type file +# PSP +PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_STXKRK.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_STXKRK.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_STXKRK.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_STX.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_STX.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_STXKRK.sbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_STX.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_STXKRK.sbin +PSP_TEEIPKEY_FILE TypeId0x15_drv_ipkeymgr_STXKRK.sbin +PSP_BOOT_DRIVER_FILE TypeId0x1B_BootDriver_STXKRK.sbin +PSP_SOC_DRIVER_FILE TypeId0x1C_SocDriver_STXKRK.sbin +PSP_DEBUG_DRIVER_FILE TypeId0x1D_DebugDriver_STXKRK.sbin +PSP_INTERFACE_DRIVER_FILE TypeId0x1F_InterfaceDriver_STXKRK.sbin +PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_STX.sbin +PSP_IKEK_FILE TypeId0x21_ikek_STX_PROD.sbin +PSP_SECG0_FILE TypeId0x24_SecPolicy_STXKRK.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_STXKRK.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_STXKRK.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_STXKRK_LPDDR5.sbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_STXKRK.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecPolicytOS_STXKRK.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_STXKRK.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_STXKRK.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_STXKRK.sbin +MSMU_FILE TypeId0x5A_Msmu_Lpddr5_STX.csbin +MSMU_FILE_SUB1_FILE TypeId0x5A_Msmu_Lpddr5_STXB0KRK.csbin +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_STX.sbin +MPIO_FILE TypeId0x5D_MPIO_STX.sbin +DMCUB_FILE TypeId0x71_DmcubFw_STXKRK.csbin +PSP_RIB_FILE_SUB0 TypeId0x76_DfRib_STX.sbin +PSP_RIB_FILE_SUB1 TypeId0x76_DfRib_KRK.sbin +AMF_SRAM_FILE TypeId0x85_MPMSram_STXKRK.sbin +AMF_DRAM_FILE_INS0 TypeId0x86_MPMDram_STXKRK.sbin +AMF_MFD_FILE TypeId0x89_MFD.sbin +TA_IKEK_FILE TypeId0x8d_iKEK_TA_STX.bin +MPCCX_FILE TypeId0x90_MPCCX_STX.csbin +MPCCX_FILE_SUB1_FILE TypeId0x90_MPCCX_KRK.csbin +LSDMA_FILE TypeId0x94_LSDMA_STX.sbin +PSP_C20MP_FILE TypeId0x95_C20MP_STX.sbin +FEATURE_TABLE_FILE TypeId0x98_AIM-T_Enable.bin +SRAM_FW_EXT_FILE TypeId0x9D_Overlay_STX.sbin + +MINIMSMU_FILE TypeId0x9A_MiniMsmu_Lpddr5_STX.csbin +MINIMSMU_FILE_SUB1_FILE TypeId0x9A_MiniMsmu_Lpddr5_STXB0KRK.csbin + +PSP_GFX_IMMU_FILE_0 TypeId0x9B_GFX_IMU_LX7_IRAM_uCode_STX.sbin +PSP_GFX_IMMU_FILE_1 TypeId0x9C_GFX_IMU_LX7_DRAM_uCode_STX.sbin +SRAM_FW_EXT_FILE TypeId0x9D_Overlay_STX.sbin + +PSP_USB_DP TypeId0xA4_USB_DP_STX.sbin +PSP_USB_SS TypeId0xA5_USB_SSP_STX.sbin +PSP_USB_4 TypeId0xA6_USB4_STX.sbin + +PSP_PMUI_FILE_SUB0_INS7 TypeId0x64_Appb_STX_Lpddr5XImem7.csbin +PSP_PMUI_FILE_SUB0_INSB TypeId0x64_Appb_STX_Lpddr5XImem11.csbin +PSP_PMUI_FILE_SUB0_INSC TypeId0x64_Appb_STX_Lpddr5XImem12.csbin +PSP_PMUI_FILE_SUB0_INSD TypeId0x64_Appb_STX_Lpddr5XImem13.csbin + +PSP_PMUD_FILE_SUB0_INS7 TypeId0x65_Appb_STX_Lpddr5XDmem7.csbin +PSP_PMUD_FILE_SUB0_INSB TypeId0x65_Appb_STX_Lpddr5XDmem11.csbin +PSP_PMUD_FILE_SUB0_INSC TypeId0x65_Appb_STX_Lpddr5XDmem12.csbin +PSP_PMUD_FILE_SUB0_INSD TypeId0x65_Appb_STX_Lpddr5XDmem13.csbin + +PSP_MP2CFG_FILE TypeId0x6a_Mp2FwConfig_STX.sbin diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk deleted file mode 100644 index add7e073610..00000000000 --- a/src/soc/amd/glinda/psp_verstage/Makefile.mk +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) - -subdirs-y += ../../common/psp_verstage - -verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/glinda/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y +=$(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S - -endif diff --git a/src/soc/amd/glinda/psp_verstage/chipset.c b/src/soc/amd/glinda/psp_verstage/chipset.c deleted file mode 100644 index b266fc2820d..00000000000 --- a/src/soc/amd/glinda/psp_verstage/chipset.c +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -#include -#include -#include -#include - -/* - * We can't pass pointer to hash table in the SPI. - * The AMD PSP team specifically required that whole hash table - * should be copied into memory before passing them to the PSP - * to reduce window of TOCTOU. - */ -#define MAX_NUM_HASH_ENTRIES 128 -static struct psp_fw_hash_table hash_table; -static struct psp_fw_entry_hash_256 hash_256[MAX_NUM_HASH_ENTRIES]; -static struct psp_fw_entry_hash_384 hash_384[MAX_NUM_HASH_ENTRIES]; - -void update_psp_fw_hash_table(const char *fname) -{ - uint8_t *spi_ptr = (uint8_t *)cbfs_map(fname, NULL); - uint32_t len; - - if (!spi_ptr) { - printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); - /* - * If we don't supply hash table, the PSP will refuse to boot. - * So returning here is safe to do. - */ - return; - } - - memcpy(&hash_table, spi_ptr, offsetof(struct psp_fw_hash_table, fw_hash_256)); - - if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || - hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", - hash_table.no_of_entries_256, hash_table.no_of_entries_384); - return; - } - - if (hash_table.no_of_entries_256 == 0 && - hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "No entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", - hash_table.no_of_entries_256, hash_table.no_of_entries_384); - return; - } - - spi_ptr += offsetof(struct psp_fw_hash_table, fw_hash_256); - - hash_table.fw_hash_256 = hash_256; - hash_table.fw_hash_384 = hash_384; - len = sizeof(struct psp_fw_entry_hash_256) * hash_table.no_of_entries_256; - memcpy(hash_256, spi_ptr, len); - - spi_ptr += len; - len = sizeof(struct psp_fw_entry_hash_384) * hash_table.no_of_entries_384; - memcpy(hash_384, spi_ptr, len); - - svc_set_fw_hash_table(&hash_table); -} - -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); -} - -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(address, size); -} - -uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) -{ - return 0; -} - -int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, - struct sha_generic_data *sha_op) -{ - if (hash_alg == VB2_HASH_SHA256) { - sha_op->SHAType = SHA_TYPE_256; - sha_op->DigestLen = 32; - } else if (hash_alg == VB2_HASH_SHA384) { - sha_op->SHAType = SHA_TYPE_384; - sha_op->DigestLen = 48; - } else { - return -1; - } - return 0; -} - - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} - -void platform_report_mode(int developer_mode_enabled) -{ - printk(BIOS_INFO, "Reporting %s mode\n", - developer_mode_enabled ? "Developer" : "Normal"); - if (developer_mode_enabled) - svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); - else - svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); -} diff --git a/src/soc/amd/glinda/psp_verstage/svc.c b/src/soc/amd/glinda/psp_verstage/svc.c deleted file mode 100644 index 531e3d5f67f..00000000000 --- a/src/soc/amd/glinda/psp_verstage/svc.c +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -#include "svc.h" - -#include -#include -#include -#include -#include - -void svc_exit(uint32_t status) -{ - uint32_t unused = 0; - SVC_CALL0(SVC_EXIT, unused); -} - -void svc_debug_print(const char *string) -{ - uint32_t unused = 0; - struct cmd_param_debug param = { - .debug_buffer = (char *)string, - .debug_buffer_len = strlen(string), - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT, (void *)¶m, unused); -} - -void svc_debug_print_ex(uint32_t dword0, - uint32_t dword1, uint32_t dword2, uint32_t dword3) -{ - uint32_t unused = 0; - struct cmd_param_debug_ex param = { - .word0 = dword0, - .word1 = dword1, - .word2 = dword2, - .word3 = dword3, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT_EX, (void *)¶m, unused); -} - -uint32_t svc_get_boot_mode(uint32_t *boot_mode) -{ - uint32_t retval = 0; - struct cmd_param_get_boot_mode param = { - .ptr_boot_mode = boot_mode, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_BOOT_MODE, (void *)¶m, retval); - return retval; -} - -void svc_delay_in_usec(uint32_t delay) -{ - uint32_t unused = 0; - struct cmd_param_delay_in_micro_second param = { - .delay = delay, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DELAY_IN_MICRO_SECONDS, (void *)¶m, unused); -} - -uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) -{ - uint32_t retval = 0; - struct cmd_param_spirom_info param = { - .ptr_spirom_info = spi_rom_info, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_SPI_INFO, (void *)¶m, retval); - return retval; -} - -uint32_t svc_map_fch_dev(enum fch_io_device io_device, - uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_map_fch_io_device param = { - .io_device = io_device, - .arg1 = arg1, - .arg2 = arg2, - .pptr_io_device_addr_axi = io_device_axi_addr, - }; - assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_FCH_IO_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_unmap_fch_io_device param = { - .io_device = io_device, - .ptr_io_device_addr_axi = io_device_axi_addr, - }; - assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_FCH_IO_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_map_spi_rom(void *spi_rom_addr, - uint32_t size, void **spi_rom_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_map_spirom param = { - .spirom_addr = (uintptr_t)spi_rom_addr, - .size = size, - .ppspirom_addr_axi = spi_rom_axi_addr, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_SPIROM_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_unmap_spi_rom(void *spi_rom_addr) -{ - uint32_t retval = 0; - struct cmd_param_unmap_spirom param = { - .ptr_spirom_addr_axi = spi_rom_addr, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_SPIROM_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset) -{ - uint32_t retval = 0; - struct cmd_param_psp_update param = { - .ptr_psp_dir_addr = psp_dir_offset, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UPDATE_PSP_BIOS_DIR, (void *)¶m, retval); - return retval; -} - -uint32_t svc_save_uapp_data(void *address, uint32_t size) -{ - uint32_t retval = 0; - struct cmd_param_copy_data_from_uapp param = { - .address = (uintptr_t)address, - .size = size, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_COPY_DATA_FROM_UAPP, (void *)¶m, retval); - return retval; -} - -uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) -{ - unsigned int retval = 0; - struct cmd_param_read_timer_val param = { - .timer_type = type, - .ptr_counter_value = counter_value, - }; - assert(type < PSP_TIMER_TYPE_MAX); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_READ_TIMER_VAL, (void *)¶m, retval); - return retval; -} - -uint32_t svc_reset_system(enum reset_type reset_type) -{ - unsigned int retval = 0; - struct cmd_param_reset_system param = { - .reset_type = reset_type, - }; - assert(reset_type < RESET_TYPE_MAX); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_RESET_SYSTEM, (void *)¶m, retval); - return retval; -} - -uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) -{ - uint32_t retval = 0; - struct cmd_param_sha param = { - .ptr_sha_op = sha_op, - }; - assert(sha_mode == SHA_GENERIC); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SHA, (void *)¶m, retval); - return retval; -} - -uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) -{ - uint32_t retval = 0; - struct cmd_param_modexp param = { - .ptr_modexp = mod_exp_param, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)¶m, retval); - return retval; -} - -uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) -{ - uint32_t retval = 0; - struct cmd_param_ccp_dma param = { - .spi_offset = spi_rom_offset, - .dst_addr = (uintptr_t)dest, - .size = size, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_CCP_DMA, (void *)¶m, retval); - return retval; -} - -uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) -{ - uint32_t retval = 0; - struct cmd_param_set_platform_boot_mode param = { - .boot_mode = boot_mode, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_PLATFORM_BOOT_MODE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table) -{ - uint32_t retval = 0; - struct cmd_param_set_fw_hash_table param = { - .ptr_psp_fw_hash_table = hash_table, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_FW_HASH_TABLE, (void *)¶m, retval); - return retval; -} diff --git a/src/soc/amd/glinda/psp_verstage/svc.h b/src/soc/amd/glinda/psp_verstage/svc.h deleted file mode 100644 index 4a0e75a06af..00000000000 --- a/src/soc/amd/glinda/psp_verstage/svc.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ -/* TODO: See what can be made common */ - -#ifndef PSP_VERSTAGE_SVC_H -#define PSP_VERSTAGE_SVC_H - -#include -#include - -struct cmd_param_sha { - struct sha_generic_data *ptr_sha_op; -}; - -struct cmd_param_debug { - char *debug_buffer; - uint32_t debug_buffer_len; -}; - -struct cmd_param_debug_ex { - uint32_t word0; - uint32_t word1; - uint32_t word2; - uint32_t word3; -}; - -struct cmd_param_modexp { - struct mod_exp_params *ptr_modexp; -}; - -struct cmd_param_psp_update { - unsigned int *ptr_psp_dir_addr; -}; - -struct cmd_param_spirom_info { - struct spirom_info *ptr_spirom_info; -}; - -struct cmd_param_map_spirom { - unsigned int spirom_addr; - unsigned int size; - void **ppspirom_addr_axi; -}; - -struct cmd_param_unmap_spirom { - void *ptr_spirom_addr_axi; -}; - -struct cmd_param_read_timer_val { - enum psp_timer_type timer_type; - uint64_t *ptr_counter_value; -}; - -struct cmd_param_delay_in_micro_second { - uint32_t delay; -}; - -struct cmd_param_reset_system { - uint32_t reset_type; -}; - -struct cmd_param_get_boot_mode { - unsigned int *ptr_boot_mode; -}; - -struct cmd_param_copy_data_from_uapp { - unsigned int address; - unsigned int size; -}; - -struct cmd_param_map_fch_io_device { - enum fch_io_device io_device; - unsigned int arg1; - unsigned int arg2; - void **pptr_io_device_addr_axi; -}; - -struct cmd_param_unmap_fch_io_device { - enum fch_io_device io_device; - void *ptr_io_device_addr_axi; -}; - -struct cmd_param_ccp_dma { - uint32_t spi_offset; - uint32_t dst_addr; - uint32_t size; -}; - -struct cmd_param_set_platform_boot_mode { - uint32_t boot_mode; -}; - -struct cmd_param_set_fw_hash_table { - struct psp_fw_hash_table *ptr_psp_fw_hash_table; -}; - -#endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/soc/amd/glinda/psp_verstage/uart.c b/src/soc/amd/glinda/psp_verstage/uart.c deleted file mode 100644 index d2cba278919..00000000000 --- a/src/soc/amd/glinda/psp_verstage/uart.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Can this be made common? Kconfig option? */ - -#include -#include -#include - -uintptr_t get_uart_base(unsigned int idx) -{ - /* Mapping the UART is not supported. */ - return 0; -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index fcbc53b10c9..79ba6ae1836 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -59,6 +59,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM @@ -72,6 +73,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS select SOC_AMD_COMMON_BLOCK_STB select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC @@ -94,7 +96,6 @@ config SOC_AMD_REMBRANDT_BASE select VBOOT_MUST_REQUEST_DISPLAY if VBOOT select VBOOT_X86_SHA256_ACCELERATION if VBOOT select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI config SOC_AMD_MENDOCINO bool @@ -116,6 +117,9 @@ config CHIPSET_DEVICETREE default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO default "soc/amd/mendocino/chipset_rembrandt.cb" +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/mendocino" + config FSP_M_FILE string "FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk index 4f93e490a45..0f03f965050 100644 --- a/src/soc/amd/mendocino/Makefile.mk +++ b/src/soc/amd/mendocino/Makefile.mk @@ -40,8 +40,6 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/mendocino/include CPPFLAGS_common += -I$(src)/soc/amd/mendocino/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/mendocino -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough ifeq ($(CONFIG_CBFS_VERIFICATION),y) @@ -219,6 +217,9 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) + # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) @@ -244,6 +245,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_BIOS_FWCOMPRESS) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ $(OPT_RECOVERY_AB_SINGLE_COPY) @@ -294,8 +296,8 @@ else $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) endif $(obj)/amdfw_a.rom: $(obj)/amdfw.rom diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 9982d844ab2..d858a0be000 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -46,6 +46,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | ACPI_FADT_PCI_EXPRESS_WAKE | diff --git a/src/soc/amd/mendocino/acpi/mmio.asl b/src/soc/amd/mendocino/acpi/mmio.asl index 21237a781ae..79590498421 100644 --- a/src/soc/amd/mendocino/acpi/mmio.asl +++ b/src/soc/amd/mendocino/acpi/mmio.asl @@ -14,7 +14,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index fb61f5852ad..e3fc97a5c41 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -33,7 +33,7 @@ struct device_operations mendocino_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index fc6c587a87c..d34d10a8354 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -140,8 +140,12 @@ static void cgpll_clock_gate_init(void) t = misc_read32(MISC_CLKGATEDCNTL); t |= ALINKCLK_GATEOFFEN; t |= BLINKCLK_GATEOFFEN; - t |= XTAL_PAD_S0I3_TURNOFF_EN; - t |= XTAL_PAD_S3_TURNOFF_EN; + if (CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX)) + t &= ~XTAL_PAD_S0I3_TURNOFF_EN; + else + t |= XTAL_PAD_S0I3_TURNOFF_EN; + if (!CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S3)) + t |= XTAL_PAD_S3_TURNOFF_EN; t |= XTAL_PAD_S5_TURNOFF_EN; misc_write32(MISC_CLKGATEDCNTL, t); diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 5379baf7dd5..410589400d9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -18,9 +18,6 @@ config SOC_AMD_PHOENIX_BASE select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK select PROVIDES_ROM_SHARING - select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK - # TODO: (b/303516266) Re-enable CCP DMA after addressing a stall - # select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select RTC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP_GEN2 @@ -53,6 +50,7 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM @@ -66,6 +64,7 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART @@ -74,10 +73,8 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select DRAM_SUPPORT_DDR5 - select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select VBOOT_X86_SHA256_ACCELERATION if VBOOT select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI config SOC_AMD_PHOENIX_FSP bool @@ -137,27 +134,6 @@ config PSP_APOB_DRAM_SIZE hex default 0x40000 -config PSP_SHAREDMEM_BASE - hex - default 0x2041000 if VBOOT - default 0x0 - help - This variable defines the base address in DRAM memory where PSP copies - the vboot workbuf. This is used in the linker script to have a static - allocation for the buffer as well as for adding relevant entries in - the BIOS directory table for the PSP. - -config PSP_SHAREDMEM_SIZE - hex - default 0x8000 if VBOOT - default 0x0 - help - Sets the maximum size for the PSP to pass the vboot workbuf and - any logs or timestamps back to coreboot. This will be copied - into main memory by the PSP and will be available when the x86 is - started. The workbuf's base depends on the address of the reset - vector. - config PRE_X86_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -170,10 +146,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config CBFS_MCACHE_SIZE - hex - default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK - config C_ENV_BOOTBLOCK_SIZE hex default 0x20000 @@ -225,11 +197,6 @@ config CBFS_CACHE_SIZE hex default 0x40000 if CBFS_PRELOAD -config RO_REGION_ONLY - string - depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A - default "apu/amdfw" - config ECAM_MMCONF_BASE_ADDRESS default 0xE0000000 @@ -369,85 +336,19 @@ config PSP_SOFTFUSE_BITS Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) See #55758 (NDA) for additional bit definitions. - -config PSP_VERSTAGE_FILE - string "Specify the PSP_verstage file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - default "\$(obj)/psp_verstage.bin" - help - Add psp_verstage file to the build & PSP Directory Table - -config PSP_VERSTAGE_SIGNING_TOKEN - string "Specify the PSP_verstage Signature Token file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - default "" - help - Add psp_verstage signature token to the build & PSP Directory Table - endmenu config VBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config VBOOT_STARTS_BEFORE_BOOTBLOCK - def_bool n - depends on VBOOT - select ARCH_VERSTAGE_ARMV7 - help - Runs verstage on the PSP. Only available on - certain ChromeOS branded parts from AMD. - -config VBOOT_HASH_BLOCK_SIZE - hex - default 0x9000 - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - help - Because the bulk of the time in psp_verstage to hash the RO cbfs is - spent in the overhead of doing svc calls, increasing the hash block - size significantly cuts the verstage hashing time as seen below. - - 4k takes 180ms - 16k takes 44ms - 32k takes 33.7ms - 36k takes 32.5ms - There's actually still room for an even bigger stack, but we've - reached a point of diminishing returns. - -config CMOS_RECOVERY_BYTE - hex - default 0x51 - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - help - If the workbuf is not passed from the PSP to coreboot, set the - recovery flag and reboot. The PSP will read this byte, mark the - recovery request in VBNV, and reset the system into recovery mode. - - This is the byte before the default first byte used by VBNV - (0x26 + 0x0E - 1) - -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK - -config RWA_REGION_ONLY - string - default "apu/amdfw_a" - help - Add a space-delimited list of filenames that should only be in the - RW-A section. - -config RWB_REGION_ONLY - string - default "apu/amdfw_b" - help - Add a space-delimited list of filenames that should only be in the - RW-B section. - -endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK - endif # SOC_AMD_PHOENIX_BASE if SOC_AMD_PHOENIX_FSP +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/phoenix" + config FSP_M_ADDR hex default 0x20E0000 diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 672e10fb8d5..20e750781be 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -4,8 +4,6 @@ ifeq ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - # Beware that all-y also adds the compilation unit to verstage on PSP all-y += aoac.c all-y += config.c @@ -19,8 +17,6 @@ all_x86-y += uart.c bootblock-y += early_fch.c bootblock-y += espi_util.c -verstage-y += espi_util.c - romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c romstage-y += soc_util.c @@ -45,26 +41,6 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi -ifeq ($(CONFIG_SOC_AMD_PHOENIX_FSP),y) -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common -endif - -# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough -ifeq ($(CONFIG_CBFS_VERIFICATION),y) -# 0x80 accounts for the cbfs_file struct + filename + metadata structs -AMD_FW_AB_POSITION := 0x80 -else # ($(CONFIG_CBFS_VERIFICATION), y) -# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute -AMD_FW_AB_POSITION := 0x40 -endif # ($(CONFIG_CBFS_VERIFICATION), y) - -PHOENIX_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -PHOENIX_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) - # # PSP Directory Table items # @@ -110,11 +86,6 @@ PSP_RPMC_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_SIZE) # type = 0x55 SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) -else -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool @@ -149,22 +120,6 @@ APOB_NV_RO_BASE=$(APOB_NV_BASE) endif endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE -ifeq ($(CONFIG_AMDFW_SPLIT),y) -FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) -endif - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) SIGNED_AMDFW_B_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) @@ -191,9 +146,6 @@ OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size) OPT_PSP_RPMC_NVRAM_BASE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_BASE), --rpmc-nvram-base) OPT_PSP_RPMC_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_SIZE), --rpmc-nvram-size) -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) @@ -203,8 +155,6 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) @@ -213,21 +163,13 @@ OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi- OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) -OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) -OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) - OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) - -# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant -OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) -OPT_AMDFW_BODY_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_LOCATION), --body-location) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) MANIFEST_FILE=$(obj)/amdfw_manifest OPT_MANIFEST=$(call add_opt_prefix, $(MANIFEST_FILE), --output-manifest) @@ -248,19 +190,15 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ --load-s0i3 \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_BIOS_FWCOMPRESS) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) \ - $(OPT_AMDFW_BODY_LOCATION) + $(OPT_RECOVERY_AB_SINGLE_COPY) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ $(DEP_FILES) \ $(AMDFWTOOL) \ @@ -272,19 +210,11 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_RO_SIZE) \ $(OPT_APOB_NV_RO_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ $(OPT_MANIFEST) \ --location $(CONFIG_AMD_FWM_POSITION) \ --output $@ -ifeq ($(CONFIG_AMDFW_SPLIT),y) -$(obj)/amdfw.rom.body: $(obj)/amdfw.rom -$(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body) - $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward -endif - # # Extracts everything from the ELF's first PT_LOAD area and compresses it. # This discards everything before PT_LOAD, every symbol, debug information @@ -295,89 +225,12 @@ endif $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_A_POSITION) \ - $(OPT_SIGNED_AMDFW_A_FILE) \ - --location $(call _tohex,$(PHOENIX_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_B_POSITION) \ - $(OPT_SIGNED_AMDFW_B_FILE) \ - --location $(call _tohex,$(PHOENIX_FW_B_POSITION)) \ - --anywhere \ - --output $@ - + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) $(MANIFEST_FILE): $(obj)/amdfw.rom cbfs-files-y += amdfw_manifest amdfw_manifest-file := $(MANIFEST_FILE) amdfw_manifest-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom - @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ - -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ - -n apu/amdfw_b_hash -t raw - if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.1.hash)" ]; then \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ - $(obj)/amdfw_a.rom.signed.1.hash -n apu/amdfw_a_hash1 -t raw; \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ - $(obj)/amdfw_b.rom.signed.1.hash -n apu/amdfw_b_hash1 -t raw; \ - fi - if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.2.hash)" ]; then \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ - $(obj)/amdfw_a.rom.signed.2.hash -n apu/amdfw_a_hash2 -t raw; \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ - $(obj)/amdfw_b.rom.signed.2.hash -n apu/amdfw_b_hash2 -t raw; \ - fi -endif # CONFIG_SEPARATE_SIGNED_PSPFW -endif - -# Add ranges for all components up until the first segment of BIOS to be verified by GSC -ifeq ($(CONFIG_VBOOT_GSCVD),y) -# Adding range for Bootblock -vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) -# Adding range for PSP Stage1 Bootloader -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# Adding range for PSP Verstage -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) -endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) - endif # ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 0f0ec26daeb..c303fe54114 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -52,6 +52,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | ACPI_FADT_PCI_EXPRESS_WAKE | diff --git a/src/soc/amd/phoenix/acpi/mmio.asl b/src/soc/amd/phoenix/acpi/mmio.asl index e3935743322..0679576f0b7 100644 --- a/src/soc/amd/phoenix/acpi/mmio.asl +++ b/src/soc/amd/phoenix/acpi/mmio.asl @@ -14,7 +14,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 89de85c69ab..f627c151746 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -35,7 +35,7 @@ struct device_operations phoenix_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c index 5d15b1dd838..38640c26850 100644 --- a/src/soc/amd/phoenix/cpu.c +++ b/src/soc/amd/phoenix/cpu.c @@ -16,6 +16,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, PHOENIX_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, + { X86_VENDOR_AMD, PHOENIX_HP1_CPUID, CPUID_ALL_STEPPINGS_MASK }, { X86_VENDOR_AMD, PHOENIX2_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, CPU_TABLE_END }; diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index dd3460d0d1d..4a249534959 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -138,8 +138,12 @@ static void cgpll_clock_gate_init(void) t = misc_read32(MISC_CLKGATEDCNTL); t |= ALINKCLK_GATEOFFEN; t |= BLINKCLK_GATEOFFEN; - t |= XTAL_PAD_S0I3_TURNOFF_EN; - t |= XTAL_PAD_S3_TURNOFF_EN; + if (CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX)) + t &= ~XTAL_PAD_S0I3_TURNOFF_EN; + else + t |= XTAL_PAD_S0I3_TURNOFF_EN; + if (!CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S3)) + t |= XTAL_PAD_S3_TURNOFF_EN; t |= XTAL_PAD_S5_TURNOFF_EN; misc_write32(MISC_CLKGATEDCNTL, t); diff --git a/src/soc/amd/phoenix/include/soc/cpu.h b/src/soc/amd/phoenix/include/soc/cpu.h index 8afa95c5573..0089185e212 100644 --- a/src/soc/amd/phoenix/include/soc/cpu.h +++ b/src/soc/amd/phoenix/include/soc/cpu.h @@ -4,6 +4,7 @@ #define AMD_PHOENIX_CPU_H #define PHOENIX_A0_CPUID CPUID_FROM_FMS(0x19, 0x74, 0) +#define PHOENIX_HP1_CPUID CPUID_FROM_FMS(0x19, 0x75, 0) #define PHOENIX2_A0_CPUID CPUID_FROM_FMS(0x19, 0x78, 0) #define PHOENIX2_VBIOS_VID_DID 0x100215c8 diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.mk b/src/soc/amd/phoenix/psp_verstage/Makefile.mk deleted file mode 100644 index 7571b1d4897..00000000000 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.mk +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage - -verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/phoenix/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y +=$(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/phoenix/psp_verstage/chipset.c b/src/soc/amd/phoenix/psp_verstage/chipset.c deleted file mode 100644 index b7efdc9332e..00000000000 --- a/src/soc/amd/phoenix/psp_verstage/chipset.c +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "2api.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PSP_FW_HASH_FILE_NAME(slot, id) "apu/amdfw_" slot "_hash" id -/* - * We can't pass pointer to hash table in the SPI. - * The AMD PSP team specifically required that whole hash table - * should be copied into memory before passing them to the PSP - * to reduce window of TOCTOU. - */ -#define MAX_NUM_HASH_ENTRIES 64 -static struct psp_fw_hash_table hash_table; -static struct psp_fw_entry_hash_256 hash_256[MAX_NUM_HASH_ENTRIES]; -static struct psp_fw_entry_hash_384 hash_384[MAX_NUM_HASH_ENTRIES]; - -static struct psp_fw_hash_table_v2 hash_table_v2; -static struct psp_fw_entry_hash_256_v2 hash_256_v2[MAX_NUM_HASH_ENTRIES]; -static struct psp_fw_entry_hash_384_v2 hash_384_v2[MAX_NUM_HASH_ENTRIES]; - -static void update_one_psp_fw_hash_table_v1(enum verstage_cmd_id cmd, uint8_t *spi_ptr) -{ - uint32_t len; - - memcpy(&hash_table, spi_ptr, offsetof(struct psp_fw_hash_table, fw_hash_256)); - - if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || - hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, - hash_table.no_of_entries_384); - return; - } - - if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "No entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, - hash_table.no_of_entries_384); - return; - } - - spi_ptr += offsetof(struct psp_fw_hash_table, fw_hash_256); - - hash_table.fw_hash_256 = hash_256; - hash_table.fw_hash_384 = hash_384; - len = sizeof(struct psp_fw_entry_hash_256) * hash_table.no_of_entries_256; - memcpy(hash_256, spi_ptr, len); - - spi_ptr += len; - len = sizeof(struct psp_fw_entry_hash_384) * hash_table.no_of_entries_384; - memcpy(hash_384, spi_ptr, len); - - svc_set_fw_hash_table(cmd, &hash_table); -} - -static void update_one_psp_fw_hash_table_v2(enum verstage_cmd_id cmd, uint8_t *spi_ptr) -{ - uint32_t len; - - memcpy(&hash_table_v2, spi_ptr, offsetof(struct psp_fw_hash_table_v2, fw_hash_256)); - - if (hash_table_v2.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || - hash_table_v2.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", hash_table_v2.no_of_entries_256, - hash_table_v2.no_of_entries_384); - return; - } - - if (hash_table_v2.no_of_entries_256 == 0 && hash_table_v2.no_of_entries_384 == 0) { - printk(BIOS_ERR, "No entries in AMD Firmware hash table" - " (SHA256:%d, SHA384:%d)\n", hash_table_v2.no_of_entries_256, - hash_table_v2.no_of_entries_384); - return; - } - - spi_ptr += offsetof(struct psp_fw_hash_table_v2, fw_hash_256); - - hash_table_v2.fw_hash_256 = hash_256_v2; - hash_table_v2.fw_hash_384 = hash_384_v2; - len = sizeof(struct psp_fw_entry_hash_256_v2) * hash_table_v2.no_of_entries_256; - memcpy(hash_256_v2, spi_ptr, len); - - spi_ptr += len; - len = sizeof(struct psp_fw_entry_hash_384_v2) * hash_table_v2.no_of_entries_384; - memcpy(hash_384_v2, spi_ptr, len); - - svc_set_fw_hash_table(cmd, &hash_table_v2); -} - -static void update_one_psp_fw_hash_table(enum verstage_cmd_id cmd, const char *fname) -{ - void *hash_file = cbfs_map(fname, NULL); - uint16_t version; - - if (!hash_file) { - printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); - /* - * If we don't supply hash table, the PSP will refuse to boot. - * So returning here is safe to do. - */ - return; - } - - memcpy(&version, hash_file, sizeof(version)); - assert(version <= 2); - switch (version) { - case 1: - update_one_psp_fw_hash_table_v1(cmd, hash_file); - break; - case 2: - update_one_psp_fw_hash_table_v2(cmd, hash_file); - break; - default: - printk(BIOS_ERR, "%s: Unexpected version %d\n", __func__, version); - } - cbfs_unmap(hash_file); - rdev_munmap(boot_device_ro(), hash_file); -} - -void update_psp_fw_hash_tables(void) -{ - struct vb2_context *ctx = vboot_get_context(); - - if (vboot_is_firmware_slot_a(ctx)) { - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE1, - PSP_FW_HASH_FILE_NAME("a", "")); - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE2, - PSP_FW_HASH_FILE_NAME("a", "1")); - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_TOS, - PSP_FW_HASH_FILE_NAME("a", "2")); - } else { - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE1, - PSP_FW_HASH_FILE_NAME("b", "")); - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE2, - PSP_FW_HASH_FILE_NAME("b", "1")); - update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_TOS, - PSP_FW_HASH_FILE_NAME("b", "2")); - } -} - -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); -} - -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(address, size); -} - -uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) -{ - return 0; -} - -int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, - struct sha_generic_data *sha_op) -{ - if (hash_alg == VB2_HASH_SHA256) { - sha_op->SHAType = SHA_TYPE_256; - sha_op->DigestLen = 32; - } else if (hash_alg == VB2_HASH_SHA384) { - sha_op->SHAType = SHA_TYPE_384; - sha_op->DigestLen = 48; - } else { - return -1; - } - return 0; -} - -void platform_report_mode(int developer_mode_enabled) -{ - printk(BIOS_INFO, "Reporting %s mode\n", - developer_mode_enabled ? "Developer" : "Normal"); - if (developer_mode_enabled) - svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); - else - svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); -} - -void report_prev_boot_status_to_vboot(void) -{ - uint32_t boot_status = 0; - int ret; - struct vb2_context *ctx = vboot_get_context(); - - /* Already in recovery mode. No need to report previous boot status. */ - if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) - return; - - ret = svc_get_prev_boot_status(&boot_status); - if (ret != BL_OK || boot_status) { - printk(BIOS_ERR, "PSPFW failure in previous boot: %d:%#8x\n", ret, boot_status); - vbnv_init(); - vb2api_previous_boot_fail(ctx, VB2_RECOVERY_FW_VENDOR_BLOB, - boot_status ? (int)boot_status : ret); - } -} - -void report_hsp_secure_state(void) -{ - uint32_t hsp_secure_state; - int ret; - - ret = svc_get_hsp_secure_state(&hsp_secure_state); - if (ret != BL_OK) { - printk(BIOS_ERR, "Error reading HSP Secure state: %d\n", ret); - hlt(); - } - - printk(BIOS_INFO, "HSP Secure state: %#8x\n", hsp_secure_state); -} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.c b/src/soc/amd/phoenix/psp_verstage/svc.c deleted file mode 100644 index 1bea8fc4d4e..00000000000 --- a/src/soc/amd/phoenix/psp_verstage/svc.c +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "svc.h" - -#include -#include -#include -#include -#include - -void svc_exit(uint32_t status) -{ - uint32_t unused = 0; - SVC_CALL0(SVC_EXIT, unused); -} - -void svc_debug_print(const char *string) -{ - uint32_t unused = 0; - struct cmd_param_debug param = { - .debug_buffer = (char *)string, - .debug_buffer_len = strlen(string), - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT, (void *)¶m, unused); -} - -void svc_debug_print_ex(uint32_t dword0, - uint32_t dword1, uint32_t dword2, uint32_t dword3) -{ - uint32_t unused = 0; - struct cmd_param_debug_ex param = { - .word0 = dword0, - .word1 = dword1, - .word2 = dword2, - .word3 = dword3, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT_EX, (void *)¶m, unused); -} - -uint32_t svc_get_boot_mode(uint32_t *boot_mode) -{ - uint32_t retval = 0; - struct cmd_param_get_boot_mode param = { - .ptr_boot_mode = boot_mode, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_BOOT_MODE, (void *)¶m, retval); - return retval; -} - -void svc_delay_in_usec(uint32_t delay) -{ - uint32_t unused = 0; - struct cmd_param_delay_in_micro_second param = { - .delay = delay, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DELAY_IN_MICRO_SECONDS, (void *)¶m, unused); -} - -uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) -{ - uint32_t retval = 0; - struct cmd_param_spirom_info param = { - .ptr_spirom_info = spi_rom_info, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_SPI_INFO, (void *)¶m, retval); - return retval; -} - -uint32_t svc_map_fch_dev(enum fch_io_device io_device, - uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_map_fch_io_device param = { - .io_device = io_device, - .arg1 = arg1, - .arg2 = arg2, - .pptr_io_device_addr_axi = io_device_axi_addr, - }; - assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_FCH_IO_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_unmap_fch_io_device param = { - .io_device = io_device, - .ptr_io_device_addr_axi = io_device_axi_addr, - }; - assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_FCH_IO_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_map_spi_rom(void *spi_rom_addr, - uint32_t size, void **spi_rom_axi_addr) -{ - uint32_t retval = 0; - struct cmd_param_map_spirom param = { - .spirom_addr = (uintptr_t)spi_rom_addr, - .size = size, - .ppspirom_addr_axi = spi_rom_axi_addr, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_SPIROM_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_unmap_spi_rom(void *spi_rom_addr) -{ - uint32_t retval = 0; - struct cmd_param_unmap_spirom param = { - .ptr_spirom_addr_axi = spi_rom_addr, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_SPIROM_DEVICE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset) -{ - uint32_t retval = 0; - struct cmd_param_psp_update param = { - .ptr_psp_dir_addr = psp_dir_offset, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UPDATE_PSP_BIOS_DIR, (void *)¶m, retval); - return retval; -} - -uint32_t svc_save_uapp_data(void *address, uint32_t size) -{ - uint32_t retval = 0; - struct cmd_param_copy_data_from_uapp param = { - .address = (uintptr_t)address, - .size = size, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_COPY_DATA_FROM_UAPP, (void *)¶m, retval); - return retval; -} - -uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) -{ - unsigned int retval = 0; - struct cmd_param_read_timer_val param = { - .timer_type = type, - .ptr_counter_value = counter_value, - }; - assert(type < PSP_TIMER_TYPE_MAX); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_READ_TIMER_VAL, (void *)¶m, retval); - return retval; -} - -uint32_t svc_reset_system(enum reset_type reset_type) -{ - unsigned int retval = 0; - struct cmd_param_reset_system param = { - .reset_type = reset_type, - }; - assert(reset_type < RESET_TYPE_MAX); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_RESET_SYSTEM, (void *)¶m, retval); - return retval; -} - -uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) -{ - uint32_t retval = 0; - struct cmd_param_sha param = { - .ptr_sha_op = sha_op, - }; - assert(sha_mode == SHA_GENERIC); - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SHA, (void *)¶m, retval); - return retval; -} - -uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) -{ - uint32_t retval = 0; - struct cmd_param_modexp param = { - .ptr_modexp = mod_exp_param, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)¶m, retval); - return retval; -} - -uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) -{ - uint32_t retval = 0; - struct cmd_param_ccp_dma param = { - .spi_offset = spi_rom_offset, - .dst_addr = (uintptr_t)dest, - .size = size, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_CCP_DMA, (void *)¶m, retval); - return retval; -} - -uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) -{ - uint32_t retval = 0; - struct cmd_param_set_platform_boot_mode param = { - .boot_mode = boot_mode, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_PLATFORM_BOOT_MODE, (void *)¶m, retval); - return retval; -} - -uint32_t svc_set_fw_hash_table(enum verstage_cmd_id cmd, void *hash_table) -{ - uint32_t retval = 0; - struct cmd_param_set_fw_hash_table param = { - .ptr_psp_fw_hash_table = hash_table, - }; - assert(cmd == CMD_SET_FW_HASH_TABLE_STAGE1 || - cmd == CMD_SET_FW_HASH_TABLE_STAGE2 || - cmd == CMD_SET_FW_HASH_TABLE_TOS); - SVC_CALL2(SVC_VERSTAGE_CMD, cmd, (void *)¶m, retval); - return retval; -} - -uint32_t svc_get_prev_boot_status(uint32_t *boot_status) -{ - uint32_t retval = 0; - struct cmd_param_get_prev_boot_status param = { - .ptr_boot_status = boot_status, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_PREV_BOOT_STATUS, (void *)¶m, retval); - return retval; -} - -uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state) -{ - uint32_t retval = 0; - struct cmd_param_get_hsp_secure_state param; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_HSP_SECURE_STATE, (void *)¶m, retval); - *hsp_secure_state = param.hsp_secure_state; - return retval; -} - -uint32_t svc_write_postcode(uint32_t postcode) -{ - uint32_t retval = 0; - struct cmd_param_postcode param = { - .postcode = postcode, - }; - SVC_CALL2(SVC_VERSTAGE_CMD, CMD_WRITE_POSTCODE, (void *)¶m, retval); - return retval; -} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.h b/src/soc/amd/phoenix/psp_verstage/svc.h deleted file mode 100644 index 43b560a8a94..00000000000 --- a/src/soc/amd/phoenix/psp_verstage/svc.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Phoenix */ -/* TODO: See what can be made common */ - -#ifndef PSP_VERSTAGE_SVC_H -#define PSP_VERSTAGE_SVC_H - -#include -#include - -struct cmd_param_sha { - struct sha_generic_data *ptr_sha_op; -}; - -struct cmd_param_debug { - char *debug_buffer; - uint32_t debug_buffer_len; -}; - -struct cmd_param_debug_ex { - uint32_t word0; - uint32_t word1; - uint32_t word2; - uint32_t word3; -}; - -struct cmd_param_modexp { - struct mod_exp_params *ptr_modexp; -}; - -struct cmd_param_psp_update { - unsigned int *ptr_psp_dir_addr; -}; - -struct cmd_param_spirom_info { - struct spirom_info *ptr_spirom_info; -}; - -struct cmd_param_map_spirom { - unsigned int spirom_addr; - unsigned int size; - void **ppspirom_addr_axi; -}; - -struct cmd_param_unmap_spirom { - void *ptr_spirom_addr_axi; -}; - -struct cmd_param_read_timer_val { - enum psp_timer_type timer_type; - uint64_t *ptr_counter_value; -}; - -struct cmd_param_delay_in_micro_second { - uint32_t delay; -}; - -struct cmd_param_reset_system { - uint32_t reset_type; -}; - -struct cmd_param_get_boot_mode { - unsigned int *ptr_boot_mode; -}; - -struct cmd_param_copy_data_from_uapp { - unsigned int address; - unsigned int size; -}; - -struct cmd_param_map_fch_io_device { - enum fch_io_device io_device; - unsigned int arg1; - unsigned int arg2; - void **pptr_io_device_addr_axi; -}; - -struct cmd_param_unmap_fch_io_device { - enum fch_io_device io_device; - void *ptr_io_device_addr_axi; -}; - -struct cmd_param_ccp_dma { - uint32_t spi_offset; - uint32_t dst_addr; - uint32_t size; -}; - -struct cmd_param_set_platform_boot_mode { - uint32_t boot_mode; -}; - -struct cmd_param_set_fw_hash_table { - void *ptr_psp_fw_hash_table; -}; - -struct cmd_param_get_prev_boot_status { - unsigned int *ptr_boot_status; -}; - -struct cmd_param_get_hsp_secure_state { - unsigned int hsp_secure_state; -}; - -struct cmd_param_postcode { - uint32_t postcode; -}; - -#endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/soc/amd/phoenix/psp_verstage/uart.c b/src/soc/amd/phoenix/psp_verstage/uart.c deleted file mode 100644 index d2cba278919..00000000000 --- a/src/soc/amd/phoenix/psp_verstage/uart.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Can this be made common? Kconfig option? */ - -#include -#include -#include - -uintptr_t get_uart_base(unsigned int idx) -{ - /* Mapping the UART is not supported. */ - return 0; -} diff --git a/src/soc/amd/phoenix/soc_util.c b/src/soc/amd/phoenix/soc_util.c index e5677fcfd77..ff3f947cc7a 100644 --- a/src/soc/amd/phoenix/soc_util.c +++ b/src/soc/amd/phoenix/soc_util.c @@ -12,6 +12,8 @@ enum soc_type get_soc_type(void) if (cpuid_match(cpuid, PHOENIX_A0_CPUID, CPUID_ALL_STEPPINGS_MASK)) return SOC_PHOENIX; + if (cpuid_match(cpuid, PHOENIX_HP1_CPUID, CPUID_ALL_STEPPINGS_MASK)) + return SOC_PHOENIX; if (cpuid_match(cpuid, PHOENIX2_A0_CPUID, CPUID_ALL_STEPPINGS_MASK)) return SOC_PHOENIX2; diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f85d420697d..d64fbb8f12b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,7 +75,6 @@ config SOC_AMD_PICASSO select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI select HAVE_X86_64_SUPPORT help AMD Picasso support @@ -182,6 +181,9 @@ config ROMSTAGE_SIZE help Sets the size of DRAM allocation for romstage in linker script. +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/picasso" + config FSP_M_ADDR hex default 0x20C0000 diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index 3f4395478b5..c590f34837d 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -42,8 +42,6 @@ smm-y += root_complex.c CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough @@ -102,12 +100,6 @@ PSP_RPMC_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_SIZE) # BIOS Directory Table items - proper ordering is managed by amdfwtool # -# type = 0x7 -# RSA 2048 signature -#ifeq ($(CONFIG_PSP_PLATFORM_SECURE_BOOT),y) -PSP_BIOS_SIG_SIZE=0x100 -#endif - # type = 0x60 PSP_APCB_FILES=$(APCB_SOURCES) @@ -174,7 +166,6 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_PSP_BIOS_SIG_SIZE=$(call add_opt_prefix, $(PSP_BIOS_SIG_SIZE), --bios-sig-size) OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index d07b38ca579..66df0a5e686 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -49,6 +48,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | ACPI_FADT_PCI_EXPRESS_WAKE | diff --git a/src/soc/amd/picasso/acpi/mmio.asl b/src/soc/amd/picasso/acpi/mmio.asl index d8bbf06aecf..d20f9ccb89f 100644 --- a/src/soc/amd/picasso/acpi/mmio.asl +++ b/src/soc/amd/picasso/acpi/mmio.asl @@ -12,7 +12,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/picasso/acpi_crat.c b/src/soc/amd/picasso/acpi_crat.c index bcc39013a0b..a7318163098 100644 --- a/src/soc/amd/picasso/acpi_crat.c +++ b/src/soc/amd/picasso/acpi_crat.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index e642060ff0a..ecfa19885b1 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -34,7 +34,7 @@ struct device_operations picasso_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index d0974a51211..8fc5815cfb1 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -221,7 +221,7 @@ struct soc_amd_picasso_config { /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ union usb3_force_gen1 usb3_port_force_gen1; - uint8_t has_usb2_phy_tune_params; + bool has_usb2_phy_tune_params; struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; enum { USB_OC_PIN_0 = 0x0, diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 3550349158d..92a234695bf 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6c1eda5d5c5..fff3d1992fa 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -5,7 +5,6 @@ #include #include -#include #include /* diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index fa0eb202d99..1ebfbab94f6 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 9dd8d72876f..036ca77f2c7 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/acpi/mmio.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl index 5e52543f67e..df14a59d2ae 100644 --- a/src/soc/amd/stoneyridge/acpi/mmio.asl +++ b/src/soc/amd/stoneyridge/acpi/mmio.asl @@ -10,7 +10,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ca02a690dd8..ba1edba94b2 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 8e2ebae7568..5f045ed9def 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 1f83448cd3d..d808db20729 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index d40996981e8..b8171b01528 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -7,7 +7,6 @@ #include #include #include -#include unsigned long tsc_freq_mhz(void) { diff --git a/src/soc/amd/strix_halo/Kconfig b/src/soc/amd/strix_halo/Kconfig new file mode 100644 index 00000000000..5d7bc5bfaf6 --- /dev/null +++ b/src/soc/amd/strix_halo/Kconfig @@ -0,0 +1,344 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Evaluate what can be moved to a common directory +# TODO: Update for Strix Halo + +config SOC_AMD_STRIX_HALO_BASE + bool + select ACPI_SOC_NVS + select ARCH_X86 + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select DRIVERS_USB_ACPI + select DRIVERS_USB_PCI_XHCI + select FSP_COMPRESS_FSP_M_LZMA + select FSP_COMPRESS_FSP_S_LZ4 + select GENERIC_GPIO_LIB + select HAVE_ACPI_TABLES + select HAVE_CF9_RESET + select HAVE_EM100_SUPPORT + select HAVE_FSP_GOP + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select PLATFORM_USES_FSP2_0 + select PROVIDES_ROM_SHARING + select RTC + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_MADT + select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GPP_CLK # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I3C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_DOMAIN_ROOT_PRT # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PSP_SPL # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SVI3 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_TSC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PRELOAD_FSPS # TODO: Check if this is still correct + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP # TODO: Check if this is still correct + select SOC_FILL_CPU_CACHE_INFO + select SSE2 + select UDK_2017_BINDING + select DRAM_SUPPORT_DDR5 + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select X86_AMD_FIXED_MTRRS + select HAVE_X86_64_SUPPORT + help + AMD Strix Halo support + +config SOC_AMD_STRIX_HALO + bool + select SOC_AMD_STRIX_HALO_BASE + help + AMD Strix Halo support + +if SOC_AMD_STRIX_HALO_BASE + +config CHIPSET_DEVICETREE + string + default "soc/amd/strix_halo/chipset.cb" + +config VGA_BIOS_FILE + string + default "3rdparty/amd_blobs/strixhalo/STRIX_HALO_GENERIC_vbios.sbin" + +config VGA_BIOS_ID + string + default "1002,150e" + help + The default VGA BIOS PCI vendor/device ID of the GPU and VBIOS. + +config CPU_PT_ROM_MAP_GB + default 1024 + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x2000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x2001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_DRAM_SIZE + hex + default 0x90000 + +config PRE_X86_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Size of the CBMEM console used in PSP verstage. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x20000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config ROMSTAGE_ADDR + hex + default 0x20C0000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x70000 + help + Sets the size of DRAM allocation for romstage in linker script. + +config FSP_HEADER_PATH + default "src/vendorcode/amd/fsp/strix_halo" + +config FSP_M_ADDR + hex + default 0x2130000 + help + Sets the address in DRAM where FSP-M should be loaded. cbfstool + performs relocation of FSP-M to this address. + +config FSP_M_SIZE + hex + default 0xC0000 + help + Sets the size of DRAM allocation for FSP-M in linker script. + +config FSP_TEMP_RAM_SIZE + hex + default 0x40000 + help + The amount of coreboot-allocated heap and stack usage by the FSP. + +config ECAM_MMCONF_BASE_ADDRESS + default 0xE0000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config MAX_CPUS + int + default 32 + help + Maximum number of threads the platform can have. + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedce000 if UART_FOR_CONSOLE = 2 + default 0xfedcf000 if UART_FOR_CONSOLE = 3 + default 0xfedd1000 if UART_FOR_CONSOLE = 4 + +config SMM_TSEG_SIZE + hex + default 0x800000 if HAVE_SMI_HANDLER + default 0x0 + +config SMM_RESERVED_SIZE + hex + default 0x180000 + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + +config ACPI_BERT + bool "Build ACPI BERT Table" + default y + depends on HAVE_ACPI_TABLES + help + Report Machine Check errors identified in POST to the OS in an + ACPI Boot Error Record Table. + +config ACPI_BERT_SIZE + hex + default 0x4000 if ACPI_BERT + default 0x0 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 150 + +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. + +menu "PSP Configuration Options" + +config AMDFW_CONFIG_FILE + string "AMD PSP Firmware config file" + default "src/soc/amd/strix_halo/fw.cfg" + help + Specify the path/location of AMD PSP Firmware config file. + By default build a LPDDR5 board. + +config PSP_DISABLE_POSTCODES + bool "Disable PSP post codes" + help + Disables the output of port80 post codes from PSP. + +config PSP_POSTCODES_ON_ESPI + bool "Use eSPI bus for PSP post codes" + default y + depends on !PSP_DISABLE_POSTCODES + help + Select to send PSP port80 post codes on eSPI bus. + If not selected, PSP port80 codes will be sent on LPC bus. + +config PSP_LOAD_MP2_FW + bool + default n + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'n' + +config PSP_UNLOCK_SECURE_DEBUG + bool "Unlock secure debug" + default y + help + Select this item to enable secure debug options in PSP. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + serial number. This feature requires a signed whitelist image + and bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file path" + depends on HAVE_PSP_WHITELIST_FILE + default "site-local/3rdparty/amd_blobs/strix_halo/PSP/wtl-mrg.sbin" + +config PSP_SOFTFUSE_BITS + string "PSP Soft Fuse bits to enable" + default "6" + help + Space separated list of Soft Fuse bits to enable. + Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) + Bit 7: Disable PSP postcodes on Renoir and newer chips only + (Set by PSP_DISABLE_PORT80) + Bit 15: PSP debug output destination: + 0=SoC MMIO UART, 1=IO port 0x3F8 + Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) + + See #55758 (NDA) for additional bit definitions. + +config PSPV2_MBOX_CMD_OFFSET + default 0x10970 + +config PSP_AB_RECOVERY + bool "Use A/B Recovery scheme" + depends on !VBOOT && !CHROMEOS + select CBFS_VERIFICATION + select SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + default n + help + Enable the PSP A/B Recovery mechanism + +endmenu + +endif # SOC_AMD_STRIX_HALO_BASE diff --git a/src/soc/amd/strix_halo/Makefile.mk b/src/soc/amd/strix_halo/Makefile.mk new file mode 100644 index 00000000000..114b174b012 --- /dev/null +++ b/src/soc/amd/strix_halo/Makefile.mk @@ -0,0 +1,250 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# TODO: Move as much as possible to common +# TODO: Update for Strix Halo + +ifeq ($(CONFIG_SOC_AMD_STRIX_HALO_BASE),y) + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += i3c.c +all_x86-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += espi_util.c + +verstage-y += espi_util.c + +romstage-y += fsp_m_params.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-y += fsp_s_params.c +ramstage-y += mca.c +ramstage-y += memmap.c +ramstage-y += root_complex.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += root_complex.c +smm-y += smihandler.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/strix_halo/include +CPPFLAGS_common += -I$(src)/soc/amd/strix_halo/acpi + +# Target an offset into the CBFS. AMDFWTOOL will align it again and +# pad the space between the CBFS file header and the directory table. +# 0x80 accounts for the cbfs_file struct + filename + metadata structs +AMD_FW_AB_POSITION := 0x80 + +ifeq ($(CONFIG_PSP_AB_RECOVERY), y) +STRIX_HALO_FW_A_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_A_START) $(AMD_FW_AB_POSITION)) +STRIX_HALO_FW_B_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_B_START) $(AMD_FW_AB_POSITION)) +endif + +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x04 +# The flashmap section used for this is expected to be named PSP_NVRAM +PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START) +PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x54 +# The flashmap section used for this is expected to be named PSP_RPMC_NVRAM +PSP_RPMC_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_START) +PSP_RPMC_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_SIZE) + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3)$(CONFIG_SMMSTORE),yy) +# Rom Armor needs the SMM Store region to be whitelisted +PSP_BIOS_NV_ST_BASE=$(call get_fmap_value,FMAP_SECTION_SMMSTORE_START) +PSP_BIOS_NV_ST_SIZE=$(call get_fmap_value,FMAP_SECTION_SMMSTORE_SIZE) +endif + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_NVRAM_BASE=$(call add_opt_prefix, $(PSP_NVRAM_BASE), --nvram-base) +OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size) + +OPT_PSP_RPMC_NVRAM_BASE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_BASE), --rpmc-nvram-base) +OPT_PSP_RPMC_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_SIZE), --rpmc-nvram-size) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) + +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) + +OPT_BIOS_NV_ST_BASE=$(call add_opt_prefix, $(PSP_BIOS_NV_ST_BASE), --variable-nvram-base) +OPT_BIOS_NV_ST_SIZE=$(call add_opt_prefix, $(PSP_BIOS_NV_ST_SIZE), --variable-nvram-size) + +OPT_RECOVERY_AB=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-ab) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-a-location $(call _tohex, $(STRIX_HALO_FW_A_RECOVERY))) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-b-location $(call _tohex, $(STRIX_HALO_FW_B_RECOVERY))) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_NVRAM_BASE) \ + $(OPT_PSP_NVRAM_SIZE) \ + $(OPT_PSP_RPMC_NVRAM_BASE) \ + $(OPT_PSP_RPMC_NVRAM_SIZE) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + --use-pspsecureos \ + --load-s0i3 \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_RECOVERY_AB) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_BIOS_NV_ST_BASE) \ + $(OPT_BIOS_NV_ST_SIZE) \ + $(OPT_BIOS_FWCOMPRESS) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_TABLE_FILE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +ifeq ($(CONFIG_PSP_AB_RECOVERY),y) + +regions-for-file-apu/amdfw_ra = BOOTBLOCK +regions-for-file-apu/amdfw_rb = BOOTBLOCK_B + +cbfs-files-y += apu/amdfw_ra +apu/amdfw_ra-file := $(obj)/amdfw.rom.ra +apu/amdfw_ra-position := $(AMD_FW_AB_POSITION) +apu/amdfw_ra-type := amdfw + +cbfs-files-y += apu/amdfw_rb +apu/amdfw_rb-file := $(obj)/amdfw.rom.rb +apu/amdfw_rb-position := $(AMD_FW_AB_POSITION) +apu/amdfw_rb-type := amdfw + +endif +# +# Extracts everything from the ELF's first PT_LOAD area and compresses it. +# This discards everything before PT_LOAD, every symbol, debug information +# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST +# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at +# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10. +# +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) + +endif # ($(CONFIG_SOC_AMD_STRIX_HALO_BASE),y) diff --git a/src/soc/amd/strix_halo/acpi.c b/src/soc/amd/strix_halo/acpi.c new file mode 100644 index 00000000000..1b38f71d2c7 --- /dev/null +++ b/src/soc/amd/strix_halo/acpi.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ +/* TODO: See what can be made common */ + +/* ACPI - create the Fixed ACPI Description Tables (FADT) */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const struct soc_amd_strix_halo_config *cfg = config_of_soc(); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + + fill_fadt_extended_pm_io(fadt); + + fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + if (cfg->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ +} + +unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, + acpi_rsdp_t *rsdp) +{ + /* IVRS */ + current = acpi_add_ivrs_table(current, rsdp); + + if (CONFIG(PLATFORM_USES_FSP2_0)) + current = acpi_add_fsp_tables(current, rsdp); + + return current; +} + +const acpi_cstate_t cstate_cfg_table[] = { + [0] = { + .ctype = 1, + .latency = 1, + .power = 0, + }, + [1] = { + .ctype = 2, + .latency = 0x12, + .power = 0, + }, + [2] = { + .ctype = 3, + .latency = 350, + .power = 0, + }, +}; + +const acpi_cstate_t *get_cstate_config_data(size_t *size) +{ + *size = ARRAY_SIZE(cstate_cfg_table); + return cstate_cfg_table; +} diff --git a/src/soc/amd/strix_halo/acpi/acp.asl b/src/soc/amd/strix_halo/acpi/acp.asl new file mode 100644 index 00000000000..d272b810429 --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/acp.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* TODO: Update for Strix Halo */ +/* ACP Audio Configuration */ +Scope (\_SB.PCI0.GP41) { + Device (ACPD) { + /* Device addressing for ACP (Audio Coprocessor) */ + Name (_ADR, 0x05) /* Device 0, Function 5 */ + + Name (STAT, 0x3) /* Decoding Resources, Hide from UI */ + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + /* Child Devices - Audio endpoints */ + Device (HDA0) /* HDA0 - HD Audio */ + { + Name (_ADR, 0x01) + } + + Device (PDMC) /* PDM Controller */ + { + Name (_ADR, 0x02) + } + + Device (I2SC) /* I2S Controller */ + { + Name (_ADR, 0x03) + } + + Device (BTSC) /* BT Sideband Controller */ + { + Name (_ADR, 0x04) + } + + Device (SDWC) /* SoundWire Controller */ + { + Name (_ADR, 0x05) + } + + Device(SDWS) /* SoundWire Streaming */ + { + Name (_ADR, 0x06) + } + + Device(USBS) /* USB Sideband */ + { + Name (_ADR, 0x07) + } + } +} diff --git a/src/soc/amd/strix_halo/acpi/globalnvs.asl b/src/soc/amd/strix_halo/acpi/globalnvs.asl new file mode 100644 index 00000000000..5a728ff999e --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/globalnvs.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/amd/strix_halo/include/soc/nvs.h !!! + */ + +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + PM1I, 64, // 0x00 - 0x07 - System Wake Source - PM1 Index + GPEI, 64, // 0x08 - 0x0f - GPE Wake Source +} diff --git a/src/soc/amd/strix_halo/acpi/mmio.asl b/src/soc/amd/strix_halo/acpi/mmio.asl new file mode 100644 index 00000000000..2eddee7fcf4 --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/mmio.asl @@ -0,0 +1,696 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0b) + } +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Shared, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IGPI + } Else { + IRQN = PGPI + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMDI0020") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA0 + } Else { + IRQN = PUA0 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } +#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 0) + AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) +#endif +} + +Device (FUR1) { + Name (_HID, "AMDI0020") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA1 + } Else { + IRQN = PUA1 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } +#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 1) + AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0) +#endif +} + +Device (FUR2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA2 + } Else { + IRQN = PUA2 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } +#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 2) + AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0) +#endif +} + +Device (FUR3) { + Name (_HID, "AMDI0020") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA3 + } Else { + IRQN = PUA3 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } +#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 3) + AOAC_DEVICE(FCH_AOAC_DEV_UART3, 0) +#endif +} + +Device (FUR4) { + Name (_HID, "AMDI0020") + Name (_UID, 0x4) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART4_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA4 + } Else { + IRQN = PUA4 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART4_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART4, 0) +} + +Device (I2C0) { + Name (_HID, "AMDI0010") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0) +} + +Device (I2C1) { + Name (_HID, "AMDI0010") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0) +} + +Device (I2C2) { + Name (_HID, "AMDI0010") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0) +} + +Device (I2C3) +{ +#if CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + Name (_HID, "AMDI0019") +#else + Name (_HID, "AMDI0010") +#endif + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + +/* If this device is shared with PSP, then PSP takes care of power management */ +#if !CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +#endif +} + +Device (I3C0) { + Name (STAT, 0x0) + + /* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */ + Method (_HID, 0x0) { + If (STAT) { + Return ("AMDI5017") + } Else { + Return ("AMDI0016") + } + } + Name (_CID, "MIPI0100") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == PIRQ_NC) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method(_DSD, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension + Package () { + "mipi-i3c-ctrlr-0-subproperties", CTR0, + } + }) + } + + Method(CTR0, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + } + }) + } + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0) +} + +Device (I3C1) { + Name (STAT, 0x0) + + /* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */ + Method (_HID, 0x0) { + If (STAT) { + Return ("AMDI5017") + } Else { + Return ("AMDI0016") + } + } + Name (_CID, "MIPI0100") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == PIRQ_NC) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method(_DSD, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension + Package () { + "mipi-i3c-ctrlr-0-subproperties", CTR0, + } + }) + } + + Method(CTR0, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + } + }) + } + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0) +} + +Device (I3C2) { + Name (STAT, 0x0) + + /* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */ + Method (_HID, 0x0) { + If (STAT) { + Return ("AMDI5017") + } Else { + Return ("AMDI0016") + } + } + Name (_CID, "MIPI0100") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == PIRQ_NC) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method(_DSD, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension + Package () { + "mipi-i3c-ctrlr-0-subproperties", CTR0, + } + }) + } + + Method(CTR0, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + } + }) + } + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0) +} + +Device (I3C3) +{ + Name (STAT, 0x0) + + /* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */ + Method (_HID, 0x0) { + If (STAT) { + Return ("AMDI5017") + } Else { + Return ("AMDI0016") + } + } + Name (_CID, "MIPI0100") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == PIRQ_NC) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + Method(_DSD, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension + Package () { + "mipi-i3c-ctrlr-0-subproperties", CTR0, + } + }) + } + + Method(CTR0, 0, Serialized){ + Return(Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + "mipi-i3c-sw-interface-revision", 0x10000, // 1.0 + } + }) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0) +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "is-rv", 1 }, + }, + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0b) + } +} diff --git a/src/soc/amd/strix_halo/acpi/pci.asl b/src/soc/amd/strix_halo/acpi/pci.asl new file mode 100644 index 00000000000..c8458f7b72a --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/pci.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* TODO: Update for Strix Halo */ + +#include + +/* + * Keep name in sync with SSDT generator pcie_gpp_acpi_name()! + * Currently the name is hex representation of dev->path.pci.devfn. + */ + +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + +/* USB4.0 bridge */ +ACPI_PCI_DEV(GP09, 1, 1) +ACPI_PCI_DEV(GP0A, 1, 2) +ACPI_PCI_DEV(GP0B, 1, 3) + +/* PCIe GPP */ +ACPI_PCI_DEV(GP11, 2, 1) +ACPI_PCI_DEV(GP12, 2, 2) +ACPI_PCI_DEV(GP13, 2, 3) +ACPI_PCI_DEV(GP14, 2, 4) +ACPI_PCI_DEV(GP15, 2, 5) +ACPI_PCI_DEV(GP16, 2, 6) + +/* PCIe GPP */ +ACPI_PCI_DEV(GP19, 3, 1) +ACPI_PCI_DEV(GP1A, 3, 2) +ACPI_PCI_DEV(GP1B, 3, 3) +ACPI_PCI_DEV(GP1C, 3, 4) +ACPI_PCI_DEV(GP1D, 3, 5) +ACPI_PCI_DEV(GP1E, 3, 6) + +/* Internal GPP bridges */ +ACPI_PCI_DEV(GP41, 8, 1) +ACPI_PCI_DEV(GP42, 8, 2) +ACPI_PCI_DEV(GP43, 8, 3) diff --git a/src/soc/amd/strix_halo/acpi/pci_int_defs.asl b/src/soc/amd/strix_halo/acpi/pci_int_defs.asl new file mode 100644 index 00000000000..c69d4db40a3 --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/pci_int_defs.asl @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* TODO: Update for Strix Halo */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} +/* + * All PIC indexes are prefixed with P. + * All IO-APIC indexes are prefixed with I. + */ +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x60), + PGSC, 0x00000008, /* Index 0x60: GEventSci */ + PGSM, 0x00000008, /* Index 0x61: GEventSmi */ + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + + Offset (0x77), + PUA4, 0x00000008, /* Index 0x77: UART4 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xE0), + IGSC, 0x00000008, /* Index 0xE0: GEventSci */ + IGSM, 0x00000008, /* Index 0xE1: GEventSmi */ + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + + Offset (0xF7), + IUA4, 0x00000008, /* Index 0xF7: UART4 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/strix_halo/acpi/soc.asl b/src/soc/amd/strix_halo/acpi/soc.asl new file mode 100644 index 00000000000..8e3bfa7caf0 --- /dev/null +++ b/src/soc/amd/strix_halo/acpi/soc.asl @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include "globalnvs.asl" + +Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include + + #include + + #include + + #include "pci_int_defs.asl" + + #include + + #include "mmio.asl" + + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include + + #include "pci.asl" + } /* End PCI0 scope */ + + #include "acp.asl" + +} /* End \_SB scope */ + +#include + +#include + +#include + +#include + +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) +#include +#endif + +/* Enable DPTC interface with AMD ALIB */ +External(\_SB.DPTC, MethodObj) + +/* + * Platform Notify + * + * This is called by soc/amd/common/acpi/platform.asl. + */ +Method (PNOT) +{ + /* Report AC/DC state to ALIB using WAL1() */ + \WAL1 () + + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } +} diff --git a/src/soc/amd/strix_halo/aoac.c b/src/soc/amd/strix_halo/aoac.c new file mode 100644 index 00000000000..d63ca625878 --- /dev/null +++ b/src/soc/amd/strix_halo/aoac.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ + : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \ + : CONFIG_UART_FOR_CONSOLE == 4 ? FCH_AOAC_DEV_UART4 \ + : -1) +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. The console UART is handled separately from this table. + * + * TODO: Find out which I2C controllers we really need to enable here. + */ +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_ESPI, +}; + +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + +void enable_aoac_devices(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); + + /* Wait for AOAC devices to indicate power and clock OK */ + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + wait_for_aoac_enabled(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} diff --git a/src/soc/amd/strix_halo/chip.c b/src/soc/amd/strix_halo/chip.c new file mode 100644 index 00000000000..9f707cafa35 --- /dev/null +++ b/src/soc/amd/strix_halo/chip.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; +}; + +struct device_operations strix_halo_pci_domain_ops = { + .read_resources = amd_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, + .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, +}; + +static void soc_init(void *chip_info) +{ + default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; + + amd_fsp_silicon_init(); + + data_fabric_print_mmio_conf(); + + fch_init(chip_info); +} + +static void soc_final(void *chip_info) +{ + fch_final(chip_info); +} + +struct chip_operations soc_amd_strix_halo_ops = { + .name = "AMD Strix Halo SoC", + .init = soc_init, + .final = soc_final +}; diff --git a/src/soc/amd/strix_halo/chip.h b/src/soc/amd/strix_halo/chip.h new file mode 100644 index 00000000000..df2378390fe --- /dev/null +++ b/src/soc/amd/strix_halo/chip.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef STRIX_HALO_CHIP_H +#define STRIX_HALO_CHIP_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_amd_strix_halo_config { + struct soc_amd_common_config common_config; + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; + + /* Enable S0iX support */ + bool s0ix_enable; + + enum { + DOWNCORE_AUTO = 0, + DOWNCORE_1 = 1, /* Run with 1 physical core */ + DOWNCORE_2 = 3, /* Run with 2 physical cores */ + DOWNCORE_3 = 4, /* Run with 3 physical cores */ + DOWNCORE_4 = 6, /* Run with 4 physical cores */ + DOWNCORE_5 = 8, /* Run with 5 physical cores */ + DOWNCORE_6 = 9, /* Run with 6 physical cores */ + DOWNCORE_7 = 10, /* Run with 7 physical cores */ + } downcore_mode; + bool disable_smt; /* disable second thread on all physical cores */ + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; + + /* Default */ + uint8_t stapm_boost; + uint32_t stapm_time_constant_s; + uint32_t apu_only_sppt_limit; + uint32_t sustained_power_limit_mW; + uint32_t fast_ppt_limit_mW; + uint32_t slow_ppt_limit_mW; + uint32_t slow_ppt_time_constant_s; + uint32_t thermctl_limit_degreeC; + uint32_t vrm_current_limit_mA; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; + /* Throttle (e.g., Low/No Battery) */ + uint32_t vrm_current_limit_throttle_mA; + uint32_t vrm_maximum_current_limit_throttle_mA; + uint32_t vrm_soc_current_limit_throttle_mA; + + uint8_t smartshift_enable; + + uint8_t system_configuration; + + uint8_t cppc_ctrl; + uint8_t cppc_perf_limit_max_range; + uint8_t cppc_perf_limit_min_range; + uint8_t cppc_epp_max_range; + uint8_t cppc_epp_min_range; + uint8_t cppc_preferred_cores; + + /* telemetry settings */ + uint32_t telemetry_vddcrvddfull_scale_current_mA; + uint32_t telemetry_vddcrvddoffset; + uint32_t telemetry_vddcrsocfull_scale_current_mA; + uint32_t telemetry_vddcrsocoffset; + + /* The array index is the general purpose PCIe clock output number. Values in here + aren't the values written to the register to have the default to be always on. */ + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_DISABLED = 0, + DXIO_PSPP_PERFORMANCE, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + + bool usb_phy_custom; + struct usb_phy_config usb_phy; +}; + +#endif /* STRIX_HALO_CHIP_H */ diff --git a/src/soc/amd/strix_halo/chipset.cb b/src/soc/amd/strix_halo/chipset.cb new file mode 100644 index 00000000000..44d6aaa7960 --- /dev/null +++ b/src/soc/amd/strix_halo/chipset.cb @@ -0,0 +1,157 @@ +# TODO: Update for Strix Halo + +chip soc/amd/strix_halo + device cpu_cluster 0 on + ops amd_cpu_bus_ops + end + device domain 0 on + ops strix_halo_pci_domain_ops + device pci 00.0 alias gnb on ops strix_halo_root_complex_operations end + device pci 00.2 alias iommu off ops amd_iommu_ops end + + device pci 01.0 on end # Dummy device function + device pci 01.1 alias usb4_pcie_bridge_0 off end + device pci 01.2 alias usb4_pcie_bridge_1 off end + device pci 01.3 alias usb4_pcie_bridge_2 off end + + # The PCIe GPP aliases in this SoC match the device and function numbers + device pci 02.0 on end # Dummy device function, do not disable + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + + device pci 03.0 on end # Dummy device function, do not disable + device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end + device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end + device pci 03.3 alias gpp_bridge_3_3 off ops amd_external_pcie_gpp_ops end + device pci 03.4 alias gpp_bridge_3_4 off ops amd_external_pcie_gpp_ops end + device pci 03.5 alias gpp_bridge_3_5 off ops amd_external_pcie_gpp_ops end + device pci 03.6 alias gpp_bridge_3_6 off ops amd_external_pcie_gpp_ops end + + device pci 08.0 on end # Dummy device function, do not disable + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops + device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) + device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) + device pci 0.2 alias crypto off end # Crypto Coprocessor + device pci 0.4 alias xhci_1 off + ops xhci_pci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port7 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port7 off end + end + end + end + end + device pci 0.5 alias acp off ops amd_acp_ops end # Audio Processor (ACP) + device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) + device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) + end + + device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops + device pci 0.0 on end # dummy, do not disable + device pci 0.1 alias npu off end # Neural Processing Unit (NPU) + device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) + device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) + end + + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops + + device pci 0.0 alias xhci_0 off + ops xhci_pci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.3 alias xhci_0_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port6 off end + end + end + end + end + device pci 0.3 alias usb4_xhci_0 off + ops xhci_pci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias usb4_xhci_0_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port0 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port0 off end + end + end + end + end + device pci 0.4 alias usb4_xhci_1 off + ops xhci_pci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias usb4_xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + end + end + end + device pci 0.5 alias usb4_router_0 off end + device pci 0.6 alias usb4_router_1 off end + end + + device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function + device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end + + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end + end + + device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end + device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end + device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end +end diff --git a/src/soc/amd/strix_halo/config.c b/src/soc/amd/strix_halo/config.c new file mode 100644 index 00000000000..88bdae9634f --- /dev/null +++ b/src/soc/amd/strix_halo/config.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include "chip.h" + +const struct soc_amd_common_config *soc_get_common_config(void) +{ + const struct soc_amd_strix_halo_config *cfg = config_of_soc(); + return &cfg->common_config; +} diff --git a/src/soc/amd/strix_halo/cpu.c b/src/soc/amd/strix_halo/cpu.c new file mode 100644 index 00000000000..a54c5b9d6ed --- /dev/null +++ b/src/soc/amd/strix_halo/cpu.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +_Static_assert(CONFIG_MAX_CPUS == 32, "Do not override MAX_CPUS. To reduce the number of " + "available cores, use the downcore_mode and disable_smt devicetree settings instead."); + +static struct device_operations cpu_dev_ops = { + .init = amd_cpu_init, +}; + +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; +} + +u8 smbios_cache_speed(u8 level) +{ + return 1; +} + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, STRIX_HALO_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, + CPU_TABLE_END +}; + +static const struct cpu_driver zen_2_3 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/amd/strix_halo/early_fch.c b/src/soc/amd/strix_halo/early_fch.c new file mode 100644 index 00000000000..1d610e711e2 --- /dev/null +++ b/src/soc/amd/strix_halo/early_fch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* Before console init */ +void fch_pre_init(void) +{ + /* + * PM_04_ACPIMMIO_DECODE_EN which enables the ACPIMMIO decode is already set after + * reset. Since the IO port based indirect PM register space access isn't implemented + * in Phoenix any more, don't call enable_acpimmio_decode_pm04() which uses the + * indirect PM register space access via the IO ports that aren't implemented any more. + */ + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ + lpc_early_init(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); + + fch_spi_early_init(); + fch_smbus_init(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); + fch_disable_legacy_dma_io(); + enable_aoac_devices(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); +} + +/* After console init */ +void fch_early_init(void) +{ + reset_i2c_peripherals(); + pm_set_power_failure_state(); + fch_print_pmxc0_status(); + i2c_soc_early_init(); + show_spi_speeds_and_modes(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); +} diff --git a/src/soc/amd/strix_halo/espi_util.c b/src/soc/amd/strix_halo/espi_util.c new file mode 100644 index 00000000000..33ad278c6e0 --- /dev/null +++ b/src/soc/amd/strix_halo/espi_util.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include + +#define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */ +#define LOCK_SPIX10_BIT2 BIT(3) +#define ESPI_MUX_SPI1 BIT(2) +#define ROM_ADDR_WR_PROT BIT(1) + +void espi_switch_to_spi1_pads(void) +{ + uint8_t reg = spi_read8(ESPI_CNTRL_REGISTER); + + reg |= ESPI_MUX_SPI1; + + spi_write8(ESPI_CNTRL_REGISTER, reg); +} diff --git a/src/soc/amd/strix_halo/fch.c b/src/soc/amd/strix_halo/fch.c new file mode 100644 index 00000000000..b46dcd92b51 --- /dev/null +++ b/src/soc/amd/strix_halo/fch.c @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +static const struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#/GENINT2" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_HPET_L, "HPET_L" }, + { PIRQ_HPET_H, "HPET_H" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_CIR, "CIR" }, + { PIRQ_GPIOA, "GPIOa" }, + { PIRQ_GPIOB, "GPIOb" }, + { PIRQ_GPIOC, "GPIOc" }, + { PIRQ_GSCI, "GEventSci" }, + { PIRQ_GSMI, "GeventSmi" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, + { PIRQ_UART4, "UART4" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void fch_clk_output_48Mhz(void) +{ + uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); + /* Enable BP_X48M0 Clock Output */ + ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; + misc_write32(MISC_CLK_CNTL0, ctrl); +} + +static void fch_init_acpi_ports(void) +{ + u32 reg; + + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + response of the I/O write. */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ +static void gpp_clk_setup(void) +{ + struct soc_amd_strix_halo_config *cfg = config_of_soc(); + gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config)); +} + +static void cgpll_clock_gate_init(void) +{ + uint32_t t; + + t = misc_read32(MISC_CLKGATEDCNTL); + t |= ALINKCLK_GATEOFFEN; + t |= BLINKCLK_GATEOFFEN; + if (CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S0IX)) + t &= ~XTAL_PAD_S0I3_TURNOFF_EN; + else + t |= XTAL_PAD_S0I3_TURNOFF_EN; + if (!CONFIG(SOC_AMD_ACP_KEEP_RUNNING_IN_S3)) + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; + misc_write32(MISC_CLKGATEDCNTL, t); + + t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_S3_DIS; + t |= USB_PHY_CMCLK_S0I3_DIS; + t |= USB_PHY_CMCLK_S5_DIS; + misc_write32(MISC_CGPLL_CONFIGURATION0, t); + + t = pm_read32(PM_ISACONTROL); + t |= ABCLKGATEEN; + pm_write32(PM_ISACONTROL, t); +} + +void fch_init(void *chip_info) +{ + if (!CONFIG(SOC_AMD_SUPPORTS_WARM_RESET)) + set_resets_to_cold(); + i2c_soc_init(); + fch_init_acpi_ports(); + + acpi_pm_gpe_add_events_print_events(); + gpio_add_events(); + + gpp_clk_setup(); + fch_clk_output_48Mhz(); + cgpll_clock_gate_init(); +} + +void fch_final(void *chip_info) +{ +} + +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/strix_halo/fsp_m_params.c b/src/soc/amd/strix_halo/fsp_m_params.c new file mode 100644 index 00000000000..f5874897063 --- /dev/null +++ b/src/soc/amd/strix_halo/fsp_m_params.c @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ +/* TODO: See what can be moved to common */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +__weak void mb_pre_fspm(FSP_M_CONFIG *mcfg) +{ +} + +static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, + const fsp_dxio_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT, + "Too many DXIO descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0])); + } +} + +static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg, + const fsp_ddi_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT, + "Too many DDI descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0])); + } +} + +static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) +{ + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; + + mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, + &fsp_ddi, &num_ddi); + fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio); + fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); +} + +static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + const struct soc_amd_strix_halo_config *config = config_of_soc(); + + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); + + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); + + /* 0 is default */ + mcfg->ccx_down_core_mode = config->downcore_mode; + mcfg->ccx_disable_smt = config->disable_smt; + + /* when stt_control isn't 1, FSP will ignore the other stt values */ + mcfg->stt_control = config->stt_control; + mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; + mcfg->stt_min_limit = config->stt_min_limit; + mcfg->stt_m1 = config->stt_m1; + mcfg->stt_m2 = config->stt_m2; + mcfg->stt_m3 = config->stt_m3; + mcfg->stt_m4 = config->stt_m4; + mcfg->stt_m5 = config->stt_m5; + mcfg->stt_m6 = config->stt_m6; + mcfg->stt_c_apu = config->stt_c_apu; + mcfg->stt_c_gpu = config->stt_c_gpu; + mcfg->stt_c_hs2 = config->stt_c_hs2; + mcfg->stt_alpha_apu = config->stt_alpha_apu; + mcfg->stt_alpha_gpu = config->stt_alpha_gpu; + mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; + mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; + mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; + mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; + mcfg->stt_error_coeff = config->stt_error_coeff; + mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; + + /* all following fields being 0 is a valid config */ + mcfg->stapm_boost = config->stapm_boost; + mcfg->stapm_time_constant = config->stapm_time_constant_s; + mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; + mcfg->sustained_power_limit = config->sustained_power_limit_mW; + mcfg->fast_ppt_limit = config->fast_ppt_limit_mW; + mcfg->slow_ppt_limit = config->slow_ppt_limit_mW; + mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s; + mcfg->thermctl_limit = config->thermctl_limit_degreeC; + + /* 0 is default */ + mcfg->smartshift_enable = config->smartshift_enable; + + /* 0 is default */ + mcfg->system_configuration = config->system_configuration; + + /* when cppc_ctrl is 0 the other values won't be used */ + mcfg->cppc_ctrl = config->cppc_ctrl; + mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; + mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range; + mcfg->cppc_epp_max_range = config->cppc_epp_max_range; + mcfg->cppc_epp_min_range = config->cppc_epp_min_range; + mcfg->cppc_preferred_cores = config->cppc_preferred_cores; + + /* S0i3 enable */ + mcfg->s0i3_enable = config->s0ix_enable; + mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN); + + mcfg->Usb4Rt0En = is_dev_enabled(DEV_PTR(usb4_router_0)); + mcfg->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1)); + mcfg->Usb4Rt0XhciEn = is_dev_enabled(DEV_PTR(usb4_xhci_0)); + mcfg->Usb4Rt1XhciEn = is_dev_enabled(DEV_PTR(usb4_xhci_1)); + + /* voltage regulator telemetry settings */ + mcfg->telemetry_vddcrvddfull_scale_current = + config->telemetry_vddcrvddfull_scale_current_mA; + mcfg->telemetry_vddcrvddoffset = + config->telemetry_vddcrvddoffset; + mcfg->telemetry_vddcrsocfull_scale_current = + config->telemetry_vddcrsocfull_scale_current_mA; + mcfg->telemetry_vddcrsocOffset = + config->telemetry_vddcrsocoffset; + + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + + mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda)); + mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda)); + + if (config->usb_phy_custom) { + /* devicetree config is const, use local copy */ + static struct usb_phy_config lcl_usb_phy; + lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); + if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) { + mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy; + } else { + printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY " + "configuration to 32 bit FSP.\n"); + mcfg->usb_phy_ptr = 0; + } + } else { + mcfg->usb_phy_ptr = 0; + } + + /* Sync AOAC devices */ + int fch_aoac_devs[] = { + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_UART0, + FCH_AOAC_DEV_UART1, + FCH_AOAC_DEV_UART2, + FCH_AOAC_DEV_UART3, + FCH_AOAC_DEV_UART4, + FCH_AOAC_DEV_I3C0, + FCH_AOAC_DEV_I3C1, + FCH_AOAC_DEV_I3C2, + FCH_AOAC_DEV_I3C3, + }; + + for (int i = 0; i < ARRAY_SIZE(fch_aoac_devs); i++) { + const int mask = BIT(fch_aoac_devs[i]); + if (is_aoac_device_enabled(fch_aoac_devs[i])) + mcfg->fch_rt_device_enable_map |= mask; + else + mcfg->fch_rt_device_enable_map &= ~mask; + } + + fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); + mb_pre_fspm(mcfg); +} diff --git a/src/soc/amd/strix_halo/fsp_s_params.c b/src/soc/amd/strix_halo/fsp_s_params.c new file mode 100644 index 00000000000..94b5280a263 --- /dev/null +++ b/src/soc/amd/strix_halo/fsp_s_params.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include + +static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) +{ + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ + scfg->vbios_buffer = (uintptr_t)vbt_get(); +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + FSP_S_CONFIG *scfg = &supd->FspsConfig; + + fsp_assign_vbios_upds(scfg); + + /* + * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB + * before FSP-S was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs + * no SPI operations, we can read the APOB while FSP-S executes. + */ + start_apob_cache_read(); + /* + * We enqueue the payload to be loaded after the APOB. This might cause a bit of + * bus contention when loading uCode and OPROMs, but since those calls happen at + * different points in the boot state machine it's a little harder to sequence all the + * async loading correctly. So in order to keep the complexity down, we enqueue the + * payload preload here. The end goal will be to add uCode and OPROM preloading + * before the payload so that the sequencing is correct. + * + * While FSP-S is executing, it's not currently possible to enqueue other transactions + * because FSP-S doesn't call `thread_yield()`. So the payload will start loading + * right after FSP-S completes. + */ + if (!acpi_is_wakeup_s3()) + payload_preload(); +} diff --git a/src/soc/amd/strix_halo/fw.cfg b/src/soc/amd/strix_halo/fw.cfg new file mode 100644 index 00000000000..6b8db6aaa76 --- /dev/null +++ b/src/soc/amd/strix_halo/fw.cfg @@ -0,0 +1,78 @@ +# PSP fw config file + +# BLOBS NOT ADDED: +# TypeId0x64_Appb_STXHMCR_Lpddr5McrImem7.csbin: not listed in BIOSImageDirectory XML +# TypeId0x65_Appb_STXHMCR_Lpddr5McrDmem7.csbin: not listed in BIOSImageDirectory XML +# TypeId0x88*.sbin: not listed in BIOSImageDirectory XML +# (only as POINT_ENTRY) + +FIRMWARE_LOCATION 3rdparty/amd_blobs/strixhalo/PSP +SOC_NAME Strixhalo + +# type file +AMD_PUBKEY_FILE TypeId0x00_RootKey_STXH.tkn +PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_STXH.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_STXH.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_STXH.sbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_STXH.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_STXH.sbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_STXH.sbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_STXH.sbin +PSP_TEEIPKEY_FILE TypeId0x15_drv_ipkeymgr_STXH.sbin +PSP_BOOT_DRIVER_FILE TypeId0x1B_BootDriver_STXH.sbin +PSP_SOC_DRIVER_FILE TypeId0x1C_SocDriver_STXH.sbin +PSP_DEBUG_DRIVER_FILE TypeId0x1D_DebugDriver_STXH.sbin +PSP_INTERFACE_DRIVER_FILE TypeId0x1F_InterfaceDriver_STXH.sbin +PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_STXH.sbin +PSP_IKEK_FILE TypeId0x21_PspiKek_STXH.bin +PSP_SECG0_FILE TypeId0x24_SecPolicy_STXH.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_STXH.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_STXH.sbin +PSP_MP5FW_SUB0_FILE TypeId0x2A_Mp5Fw_STXH.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_STXH_LPDDR5.sbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_STXH.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecPolicytOS_STXH.sbin +DRTMTA_FILE TypeId0x47_drv_drtm_PROD.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_STXH.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_STXH.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_STXH.sbin +MSMU_FILE TypeId0x5A_Msmu_Lpddr5_STXH.csbin +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_STXH.sbin +PSP_MPIOFW_FILE TypeId0x5D_MPIO_STXH.sbin +TPMLITE_FILE TypeId0x5F_PlutonPlatFw.sbin +DMCUB_FILE TypeId0x71_DmcubFw_STXH.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_STXH.sbin +PSP_RIB_FILE_SUB0 TypeId0x76_DfRib_STXH.sbin +AMF_SRAM_FILE TypeId0x85_MPMSram_STXH.sbin +AMF_DRAM_FILE_INS0 TypeId0x86_MPMDram_STXH.sbin +AMF_MFD_FILE TypeId0x89_MFD_STXH.sbin +TA_IKEK_FILE TypeId0x8d_iKEK_TA_STXH.bin +SFDR_FILE TypeId0x8E_drv_sfdr_SAR_PROD.sbin +LSDMA_FILE TypeId0x94_LSDMA.sbin +PSP_C20MP_FILE TypeId0x95_C20MP_PHY.sbin +FEATURE_TABLE_FILE TypeId0x98_AIM-T_Enable.bin +MINIMSMU_FILE TypeId0x9A_MiniMsmu_Lpddr5_STXH.csbin +PSP_GFX_IMMU_FILE_0 TypeId0x9B_IMU_iram_STXH.sbin +PSP_GFX_IMMU_FILE_1 TypeId0x9C_IMU_dram_STXH.sbin +SRAM_FW_EXT_FILE TypeId0x9D_Overlay_STXH.sbin +PSP_S3_IMG TypeId0xA0_S3Image_STXH_A0.sbin +PSP_USB_DP TypeId0xA4_USB_DP_STXH.sbin +PSP_USB_SS TypeId0xA5_USB_SSP_STXH.sbin +PSP_USB_4 TypeId0xA6_USB4_STXH.sbin + +# BDT +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_STXH_Lpddr5Imem1.csbin +PSP_PMUI_FILE_SUB0_INS2 TypeId0x64_Appb_STXH_Lpddr5Imem2.csbin +PSP_PMUI_FILE_SUB0_INS3 TypeId0x64_Appb_STXH_Lpddr5Imem3.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_STXH_Lpddr5Dmem1.csbin +PSP_PMUD_FILE_SUB0_INS2 TypeId0x65_Appb_STXH_Lpddr5Dmem2.csbin +PSP_PMUD_FILE_SUB0_INS3 TypeId0x65_Appb_STXH_Lpddr5Dmem3.csbin +PSP_PMUI_FILE_SUB0_INSb TypeId0x64_Appb_STXH_Lpddr5XImem11.csbin +PSP_PMUI_FILE_SUB0_INSc TypeId0x64_Appb_STXH_Lpddr5XImem12.csbin +PSP_PMUI_FILE_SUB0_INSd TypeId0x64_Appb_STXH_Lpddr5XImem13.csbin +PSP_PMUD_FILE_SUB0_INSb TypeId0x65_Appb_STXH_Lpddr5XDmem11.csbin +PSP_PMUD_FILE_SUB0_INSc TypeId0x65_Appb_STXH_Lpddr5XDmem12.csbin +PSP_PMUD_FILE_SUB0_INSd TypeId0x65_Appb_STXH_Lpddr5XDmem13.csbin +PSP_PMUI_FILE_SUB0_INS7 TypeId0x64_Appb_STXHMCR_Lpddr5XMcrImem7.csbin +PSP_PMUD_FILE_SUB0_INS7 TypeId0x65_Appb_STXHMCR_Lpddr5XMcrDmem7.csbin +PSP_MP2CFG_FILE TypeId0x6a_Mp2FwConfig_STXH.sbin diff --git a/src/soc/amd/strix_halo/gpio.c b/src/soc/amd/strix_halo/gpio.c new file mode 100644 index 00000000000..271e749b924 --- /dev/null +++ b/src/soc/amd/strix_halo/gpio.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_8, GEVENT_23 }, + { GPIO_9, GEVENT_22 }, + { GPIO_11, GEVENT_5 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_18, GEVENT_14 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_15 }, + { GPIO_29, GEVENT_9 }, + { GPIO_32, GEVENT_17 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, +}; + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} diff --git a/src/soc/amd/strix_halo/i2c.c b/src/soc/amd/strix_halo/i2c.c new file mode 100644 index 00000000000..a44724b61f2 --- /dev/null +++ b/src/soc/amd/strix_halo/i2c.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), +}; + +#if ENV_X86 +static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" } +}; +#else +static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" } +}; + +void i2c_set_bar(unsigned int bus, uintptr_t bar) +{ + if (bus >= ARRAY_SIZE(i2c_ctrlr)) { + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); + return; + } + + i2c_ctrlr[bus].bar = bar; +} +#endif + +void reset_i2c_peripherals(void) +{ + const struct soc_amd_strix_halo_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + const struct soc_amd_strix_halo_config *config = config_of_soc(); + + if (bus >= ARRAY_SIZE(config->i2c_pad)) + return; + + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); +} + +const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); + return i2c_ctrlr; +} + +const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) +{ + const struct soc_amd_strix_halo_config *config = config_of_soc(); + + *num_buses = ARRAY_SIZE(config->i2c); + return config->i2c; +} diff --git a/src/soc/amd/strix_halo/i3c.c b/src/soc/amd/strix_halo/i3c.c new file mode 100644 index 00000000000..0e041942b64 --- /dev/null +++ b/src/soc/amd/strix_halo/i3c.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = { + { APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0}, + { APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1}, + { APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2}, + { APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3} +}; + +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i3c_ctrlr); + return i3c_ctrlr; +} diff --git a/src/soc/amd/strix_halo/include/soc/amd_pci_int_defs.h b/src/soc/amd/strix_halo/include/soc/amd_pci_int_defs.h new file mode 100644 index 00000000000..029a91aa11f --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/amd_pci_int_defs.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_AMD_PCI_INT_DEFS_H +#define AMD_STRIX_HALO_AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ +#define PIRQ_HPET_L PIRQ_MISC1 /* HPET TMR{0..2}_CONF_CAP_L[0:7] */ +#define PIRQ_HPET_H PIRQ_MISC2 /* HPET TMR{0..2}_CONF_CAP_H[15:8] */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ +#define PIRQ_ASF 0x12 /* ASF */ +/* 0x13-0x15 reserved */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +/* 0x17-0x19 reserved */ +#define PIRQ_SDIO 0x1a /* SDIO */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x5f reserved */ +#define PIRQ_GSCI 0x60 /* GEventSci Interrupt */ +#define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_UART4 0x77 /* UART4 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ + +#endif /* AMD_STRIX_HALO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/strix_halo/include/soc/aoac_defs.h b/src/soc/amd/strix_halo/include/soc/aoac_defs.h new file mode 100644 index 00000000000..72c00114ab7 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/aoac_defs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STRIX_HALO_AOAC_DEFS_H +#define AMD_STRIX_HALO_AOAC_DEFS_H + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_I3C1 13 +#define FCH_AOAC_DEV_I3C2 14 +#define FCH_AOAC_DEV_I3C3 15 +#define FCH_AOAC_DEV_UART2 16 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_I3C0 21 +#define FCH_AOAC_DEV_UART3 26 +#define FCH_AOAC_DEV_ESPI 27 + +#endif /* AMD_STRIX_HALO_AOAC_DEFS_H */ diff --git a/src/soc/amd/strix_halo/include/soc/cpu.h b/src/soc/amd/strix_halo/include/soc/cpu.h new file mode 100644 index 00000000000..dcf1819299e --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STRIX_HALO_CPU_H +#define AMD_STRIX_HALO_CPU_H + +#define STRIX_HALO_A0_CPUID CPUID_FROM_FMS(0x1a, 0x70, 0x0) + +#endif /* AMD_STRIX_HALO_CPU_H */ diff --git a/src/soc/amd/strix_halo/include/soc/data_fabric.h b/src/soc/amd/strix_halo/include/soc/data_fabric.h new file mode 100644 index 00000000000..f2125e4ee71 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/data_fabric.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_DATA_FABRIC_H +#define AMD_STRIX_HALO_DATA_FABRIC_H + +#include +#include + +#define IOMS0_FABRIC_ID 0x14 + +#define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) +#define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) + +#define DF_PCI_CFG_MAP_COUNT 8 + +#define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) +#define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) + +union df_pci_cfg_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 6; /* [ 2.. 7] */ + uint32_t segment_num : 8; /* [ 8..15] */ + uint32_t bus_num_base : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +union df_pci_cfg_limit { + struct { + uint32_t dst_fabric_id : 6; /* [ 0.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t bus_num_limit : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_BASE0 DF_REG_ID(0, 0xd00) +#define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04) + +#define DF_IO_REG_COUNT 8 + +#define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) +#define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) + +union df_io_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 3; /* [ 2.. 4] */ + uint32_t ie : 1; /* [ 5.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t io_base : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +union df_io_limit { + struct { + uint32_t dst_fabric_id : 6; /* [ 0.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t io_limit : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_ADDR_SHIFT 12 + +#define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80) +#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) +#define DF_MMIO_SHIFT 16 +#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88) + +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 8 + +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 1; /* [ 2.. 2] */ + uint32_t np : 1; /* [ 3.. 3] */ + uint32_t : 12; /* [15.. 4] */ + uint32_t dst_fabric_id : 6; /* [21..16] */ + uint32_t : 10; /* [31..22] */ + }; + uint32_t raw; +}; + +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t reg_num : 10; /* [10.. 1] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + +#endif /* AMD_STRIX_HALO_DATA_FABRIC_H */ diff --git a/src/soc/amd/strix_halo/include/soc/espi.h b/src/soc/amd/strix_halo/include/soc/espi.h new file mode 100644 index 00000000000..79137d54f14 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/espi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_ESPI_H +#define AMD_STRIX_HALO_ESPI_H + +void espi_switch_to_spi1_pads(void); + +#endif /* AMD_STRIX_HALO_ESPI_H */ diff --git a/src/soc/amd/strix_halo/include/soc/gpio.h b/src/soc/amd/strix_halo/include/soc/gpio.h new file mode 100644 index 00000000000..fa2fbfb278b --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/gpio.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_GPIO_H +#define AMD_STRIX_HALO_GPIO_H + +#define GPIO_DEVICE_NAME "AMDI0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include +#include +#endif /* !__ACPI__ */ + +#include + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 158 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_42 42 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_77 77 +#define GPIO_78 78 +#define GPIO_79 79 +#define GPIO_80 80 +#define GPIO_81 81 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 +#define GPIO_153 153 +#define GPIO_154 154 +#define GPIO_155 155 +#define GPIO_156 156 +#define GPIO_157 157 + +/* IOMUX function names and values */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIOxx 1 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_ZST_STUTTER_RAIL 1 +#define GPIO_8_IOMUX_GPIOxx 0 +#define GPIO_8_IOMUX_TMU_CLK_OUT0 1 +#define GPIO_8_IOMUX_TMU_CLK_OUT1 2 +#define GPIO_9_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3_GPIO 1 +/* GPIO 10 IOMUX == 2 is also GPIOxx */ +#define GPIO_10_IOMUX_DF_VRCONTEXT_0 3 +#define GPIO_11_IOMUX_GPIOxx 0 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_16_IOMUX_USB_OC0_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB_OC1_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_18_IOMUX_USB_OC2_L 0 +#define GPIO_18_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_SMBUS1_SCL 0 +#define GPIO_19_IOMUX_I2C3_SCL 1 +#define GPIO_19_IOMUX_I3C3_SCL 2 +#define GPIO_19_IOMUX_GPIOxx 3 +#define GPIO_20_IOMUX_SMBUS1_SDA 0 +#define GPIO_20_IOMUX_I2C3_SDA 1 +#define GPIO_20_IOMUX_I3C3_SDA 2 +#define GPIO_20_IOMUX_GPIOxx 3 +#define GPIO_21_IOMUX_ESPI_RESET_L 0 +#define GPIO_21_IOMUX_KBRST_L 1 +#define GPIO_21_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_ESPI_ALERT_D1 0 +#define GPIO_22_IOMUX_GPIOxx 1 +/* GPIO 22 IOMUX == 2 is also GPIOxx */ +#define GPIO_22_IOMUX_SD0_CMD 3 +#define GPIO_23_IOMUX_AC_PRES 0 +#define GPIO_23_IOMUX_GPIOxx 1 +#define GPIO_24_IOMUX_USB_OC3_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST0_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_GPIOxx 1 +/* GPIO 31 IOMUX == 2 is also GPIOxx */ +#define GPIO_31_IOMUX_SPI2_CS3_L 3 +#define GPIO_32_IOMUX_GPIOxx 0 +#define GPIO_32_IOMUX_LPC_RST_L 1 +#define GPIO_38_IOMUX_CLK_REQ5_L 0 +#define GPIO_38_IOMUX_GPIOxx 1 +#define GPIO_39_IOMUX_CLK_REQ6_L 0 +#define GPIO_39_IOMUX_GPIOxx 1 +#define GPIO_40_IOMUX_GPIOxx 0 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_42_IOMUX_DF_VRCONTEXT_1 1 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_SPI1_DAT2 0 +#define GPIO_68_IOMUX_GPIOxx 1 +/* GPIO 68 IOMUX == 2 is also GPIOxx */ +#define GPIO_68_IOMUX_SD0_DATA3 3 +#define GPIO_69_IOMUX_SPI1_DAT3 0 +#define GPIO_69_IOMUX_GPIOxx 1 +#define GPIO_69_IOMUX_SD0_CLK 2 +#define GPIO_70_IOMUX_SPI2_CLK 0 +#define GPIO_70_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_SPI1_CS1_L 0 +#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_GFX10_CAC_IPIO0 2 +#define GPIO_75_IOMUX_SPI2_CS1_L 0 +#define GPIO_75_IOMUX_GPIOxx 1 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 +#define GPIO_77_IOMUX_SPI1_CLK 0 +#define GPIO_77_IOMUX_GPIOxx 1 +/* GPIO 77 IOMUX == 2 is also GPIOxx */ +#define GPIO_77_IOMUX_SD0_DATA0 3 +#define GPIO_78_IOMUX_SPI1_CS2_L 0 +#define GPIO_78_IOMUX_GPIOxx 1 +#define GPIO_78_IOMUX_GFX10_CAC_IPIO1 2 +#define GPIO_78_IOMUX_SD0_DATA1 3 +#define GPIO_79_IOMUX_SPI1_CS3_L 0 +#define GPIO_79_IOMUX_GPIOxx 1 +#define GPIO_79_IOMUX_SPI2_CS2_L 2 +#define GPIO_80_IOMUX_SPI1_DAT1 0 +#define GPIO_80_IOMUX_GPIOxx 1 +/* GPIO 80 IOMUX == 2 is also GPIOxx */ +#define GPIO_80_IOMUX_SD0_DATA2 3 +#define GPIO_81_IOMUX_SPI1_DAT0 0 +#define GPIO_81_IOMUX_GPIOxx 1 +#define GPIO_84_IOMUX_FANIN0 0 +#define GPIO_84_IOMUX_GPIOxx 1 +#define GPIO_85_IOMUX_FANOUT0 0 +#define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_GPIOxx 0 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 +#define GPIO_91_IOMUX_SPKR 0 +#define GPIO_91_IOMUX_GPIOxx 1 +#define GPIO_92_IOMUX_CLK_REQ0_L 0 +#define GPIO_92_IOMUX_GPIOxx 1 +#define GPIO_104_IOMUX_SPI2_DAT0 0 +#define GPIO_104_IOMUX_GPIOxx 1 +#define GPIO_105_IOMUX_SPI2_DAT1 0 +#define GPIO_105_IOMUX_GPIOxx 1 +#define GPIO_106_IOMUX_SPI2_DAT2 0 +#define GPIO_106_IOMUX_GPIOxx 1 +#define GPIO_107_IOMUX_SPI2_DAT3 0 +#define GPIO_107_IOMUX_GPIOxx 1 +#define GPIO_113_IOMUX_SMBUS0_SCL 0 +#define GPIO_113_IOMUX_I2C2_SCL 1 +#define GPIO_113_IOMUX_I3C2_SCL 2 +#define GPIO_113_IOMUX_GPIOxx 3 +#define GPIO_114_IOMUX_SMBUS0_SDA 0 +#define GPIO_114_IOMUX_I2C2_SDA 1 +#define GPIO_114_IOMUX_I3C2_SDA 2 +#define GPIO_114_IOMUX_GPIOxx 3 +#define GPIO_115_IOMUX_CLK_REQ1_L 0 +#define GPIO_115_IOMUX_GPIOxx 1 +#define GPIO_116_IOMUX_CLK_REQ2_L 0 +#define GPIO_116_IOMUX_GPIOxx 1 +#define GPIO_130_IOMUX_GPIOxx 0 +#define GPIO_131_IOMUX_CLK_REQ3_L 0 +#define GPIO_131_IOMUX_GPIOxx 1 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 +#define GPIO_132_IOMUX_OSCIN 1 +#define GPIO_132_IOMUX_GPIOxx 2 +#define GPIO_135_IOMUX_GPIOxx 0 +#define GPIO_135_IOMUX_UART2_CTS_L 1 +#define GPIO_135_IOMUX_UART3_TXD 2 +#define GPIO_136_IOMUX_GPIOxx 0 +#define GPIO_136_IOMUX_UART2_RXD 1 +#define GPIO_137_IOMUX_GPIOxx 0 +#define GPIO_137_IOMUX_UART2_RTS_L 1 +#define GPIO_137_IOMUX_UART3_RXD 2 +#define GPIO_138_IOMUX_GPIOxx 0 +#define GPIO_138_IOMUX_UART2_TXD 1 +#define GPIO_139_IOMUX_GPIOxx 0 +#define GPIO_139_IOMUX_UART2_INTR 1 +#define GPIO_140_IOMUX_GPIOxx 0 +#define GPIO_140_IOMUX_UART0_CTS_L 1 +#define GPIO_140_IOMUX_UART1_TXD 2 +#define GPIO_141_IOMUX_GPIOxx 0 +#define GPIO_141_IOMUX_UART0_RXD 1 +#define GPIO_142_IOMUX_GPIOxx 0 +#define GPIO_142_IOMUX_UART0_RTS_L 1 +#define GPIO_142_IOMUX_UART1_RXD 2 +#define GPIO_143_IOMUX_GPIOxx 0 +#define GPIO_143_IOMUX_UART0_TXD 1 +#define GPIO_144_IOMUX_GPIOxx 0 +#define GPIO_144_IOMUX_SHUTDOWN_L 1 +#define GPIO_144_IOMUX_UART0_INTR 2 +#define GPIO_145_IOMUX_I2C0_SCL 0 +#define GPIO_145_IOMUX_I3C0_SCL 1 +#define GPIO_145_IOMUX_GPIOxx 2 +#define GPIO_146_IOMUX_I2C0_SDA 0 +#define GPIO_146_IOMUX_I3C0_SDA 1 +#define GPIO_146_IOMUX_GPIOxx 2 +#define GPIO_147_IOMUX_I2C1_SCL 0 +#define GPIO_147_IOMUX_I3C1_SCL 1 +#define GPIO_147_IOMUX_GPIOxx 2 +#define GPIO_148_IOMUX_I2C1_SDA 0 +#define GPIO_148_IOMUX_I3C1_SDA 1 +#define GPIO_148_IOMUX_GPIOxx 2 +#define GPIO_153_IOMUX_GPIOxx 0 +#define GPIO_153_IOMUX_UART4_CTS_L 1 +#define GPIO_154_IOMUX_GPIOxx 0 +#define GPIO_154_IOMUX_UART4_RTS_L 1 +#define GPIO_155_IOMUX_GPIOxx 0 +#define GPIO_155_IOMUX_UART4_RXD 1 +#define GPIO_156_IOMUX_GPIOxx 0 +#define GPIO_156_IOMUX_UART4_TXD 1 +#define GPIO_157_IOMUX_GPIOxx 0 +#define GPIO_157_IOMUX_UART4_INTR 1 + +#endif /* AMD_STRIX_HALO_GPIO_H */ diff --git a/src/soc/amd/strix_halo/include/soc/i2c.h b/src/soc/amd/strix_halo/include/soc/i2c.h new file mode 100644 index 00000000000..4bb62ef229b --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/i2c.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STRIX_HALO_I2C_H +#define AMD_STRIX_HALO_I2C_H + +#include +#include + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void i2c_set_bar(unsigned int bus, uintptr_t bar); +void reset_i2c_peripherals(void); + +#endif /* AMD_STRIX_HALO_I2C_H */ diff --git a/src/soc/amd/strix_halo/include/soc/iomap.h b/src/soc/amd/strix_halo/include/soc/iomap.h new file mode 100644 index 00000000000..5b06a796cf5 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/iomap.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_IOMAP_H +#define AMD_STRIX_HALO_IOMAP_H + +#define I2C_MASTER_DEV_COUNT 4 +#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) +#define I3C_CTRLR_COUNT 4 + +#if ENV_X86 + +/* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 +#define SPI_BASE_ADDRESS 0xfec10000 + +/* FCH AL2AHB Registers */ +#define ALINK_AHB_ADDRESS 0xfedc0000 + +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 + +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_DMAC4_BASE 0xfedd0000 +#define APU_UART4_BASE 0xfedd1000 + +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + +#endif /* ENV_X86 */ + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define ACPI_IO_BASE 0x0400 +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) +#define SMB_BASE_ADDR 0x0b00 + +#endif /* AMD_STRIX_HALO_IOMAP_H */ diff --git a/src/soc/amd/strix_halo/include/soc/lpc.h b/src/soc/amd/strix_halo/include/soc/lpc.h new file mode 100644 index 00000000000..5ac947e391a --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/lpc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_LPC_H +#define AMD_STRIX_HALO_LPC_H + +/* LPC_MISC_CONTROL_BITS at D14F3x078 */ + +#define LPC_LDRQ0_PU_EN BIT(10) +#define LPC_LDRQ0_PD_EN BIT(9) + +#define SPI_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_STRIX_HALO_LPC_H */ diff --git a/src/soc/amd/strix_halo/include/soc/msr.h b/src/soc/amd/strix_halo/include/soc/msr.h new file mode 100644 index 00000000000..b53e41ef173 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/msr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_MSR_H +#define AMD_STRIX_HALO_MSR_H + +#include + +/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ +union pstate_msr { + struct { + uint64_t cpu_fid_0_11 : 12; /* [ 0..11] */ + uint64_t : 2; /* [12..13] */ + uint64_t cpu_vid_0_7 : 8; /* [14..21] */ + uint64_t idd_value : 8; /* [22..29] */ + uint64_t idd_div : 2; /* [30..31] */ + uint64_t cpu_vid_8 : 1; /* [32..32] */ + uint64_t : 30; /* [33..62] */ + uint64_t pstate_en : 1; /* [63..63] */ + }; + uint64_t raw; +}; + +#endif /* AMD_STRIX_HALO_MSR_H */ diff --git a/src/soc/amd/strix_halo/include/soc/nvs.h b/src/soc/amd/strix_halo/include/soc/nvs.h new file mode 100644 index 00000000000..184e71ce787 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/nvs.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * NOTE: The layout of the global_nvs structure below must match the layout + * in soc/soc/amd/strix_halo/acpi/globalnvs.asl !!! + * + */ + +#ifndef AMD_STRIX_HALO_NVS_H +#define AMD_STRIX_HALO_NVS_H + +#include + +struct __packed global_nvs { + /* Miscellaneous */ + uint64_t pm1i; /* 0x00 - 0x07 - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x08 - 0x0f - GPE Wake Source */ +}; + +#endif /* AMD_STRIX_HALO_NVS_H */ diff --git a/src/soc/amd/strix_halo/include/soc/pci_devs.h b/src/soc/amd/strix_halo/include/soc/pci_devs.h new file mode 100644 index 00000000000..1afc64ab604 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/pci_devs.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_PCI_DEVS_H +#define AMD_STRIX_HALO_PCI_DEVS_H + +#include +#include + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) +#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) + +/* PCIe GFX/GPP Bridge device 1 with no ports */ +#define PCIE_GPP_BRIDGE_1_DEV 0x1 + +/* PCIe GPP Bridge device 2 with up to 6 ports */ +#define PCIE_GPP_BRIDGE_2_DEV 0x2 + +#define PCIE_GPP_2_0_FUNC 1 +#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) +#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) + +#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) +#define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) + +#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) +#define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) + +#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) +#define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) + +#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) +#define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) + +#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) + +/* PCIe Bridges to Bus A, Bus B and Bus C devices */ +#define PCIE_ABC_BRIDGE_DEV 0x8 + +#define PCIE_ABC_A_FUNC 1 +#define PCIE_ABC_A_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) +#define SOC_PCIE_ABC_A_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) + +#define GFX_DEV 0x0 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +#define GFX_HDA_DEV 0x0 +#define GFX_HDA_FUNC 1 +#define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) + +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) + +#define AUDIO_DEV 0x0 +#define AUDIO_FUNC 5 +#define AUDIO_DEVFN PCI_DEVFN(AUDIO_DEV, AUDIO_FUNC) + +#define HD_AUDIO_DEV 0x0 +#define HD_AUDIO_FUNC 6 +#define HD_AUDIO_DEVFN PCI_DEVFN(HD_AUDIO_DEV, HD_AUDIO_FUNC) + +#define PCIE_ABC_B_FUNC 2 +#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) + +#define XGBE0_DEV 0x0 +#define XGBE0_FUNC 2 +#define XGBE0_DEVFN PCI_DEVFN(XGBE0_DEV, XGBE0_FUNC) + +#define XGBE1_DEV 0x0 +#define XGBE1_FUNC 3 +#define XGBE1_DEVFN PCI_DEVFN(XGBE1_DEV, XGBE1_FUNC) + +#define PCIE_ABC_C_FUNC 3 +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) + +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif /* AMD_STRIX_HALO_PCI_DEVS_H */ diff --git a/src/soc/amd/strix_halo/include/soc/platform_descriptors.h b/src/soc/amd/strix_halo/include/soc/platform_descriptors.h new file mode 100644 index 00000000000..2bb04cfda28 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/platform_descriptors.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_PLATFORM_DESCRIPTORS_H +#define AMD_STRIX_HALO_PLATFORM_DESCRIPTORS_H + +#include +#include +#include + +/* Mainboard callback to obtain DXI/PCIe and DDI descriptors. */ +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); + +void mb_pre_fspm(FSP_M_CONFIG *mcfg); + +#endif /* AMD_STRIX_HALO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/strix_halo/include/soc/psp_verstage_addr.h b/src/soc/amd/strix_halo/include/soc/psp_verstage_addr.h new file mode 100644 index 00000000000..b5fe4be399c --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/psp_verstage_addr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_PSP_VERSTAGE_ADDR_H +#define AMD_STRIX_HALO_PSP_VERSTAGE_ADDR_H + +/* + * Start of available space is 0x0 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 208KB + */ +#define PSP_SRAM_START 0x0 +#define PSP_SRAM_SIZE (208K) +#define VERSTAGE_START PSP_SRAM_START + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ + +#define PSP_VERSTAGE_STACK_START 0x2a000 +#define PSP_VERSTAGE_STACK_SIZE (40K) + +#endif /* AMD_STRIX_HALO_PSP_VERSTAGE_ADDR_H */ diff --git a/src/soc/amd/strix_halo/include/soc/smi.h b/src/soc/amd/strix_halo/include/soc/smi.h new file mode 100644 index 00000000000..12410898d0c --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/smi.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_SMI_H +#define AMD_STRIX_HALO_SMI_H + +#include + +#define SMI_GEVENTS 24 +#define SCIMAPS 64 /* 0..63 */ +#define SCI_GPES 32 +#define NUMBER_SMITYPES 160 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_LPC_PME_L 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_LPC_PD_L 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_LPC_SMI_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_ESPI_RESET_L 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_LPC_PME_L) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_LPC_PD_L) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPIO9) \ + | (1 << SMITYPE_G_AGPIO8)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS_EVT_B 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L 32 +#define SMITYPE_FAKE_0 33 +#define SMITYPE_PSP SMITYPE_FAKE_0 +#define SMITYPE_FAKE_1 34 +#define SMITYPE_FAKE_2 35 +#define SMITYPE_ESPI_SCI_B 36 +#define SMITYPE_USB4_0_PME 37 +#define SMITYPE_USB4_1_PME 38 +#define SMITYPE_AZPME 39 +/* 40 Reserved */ +#define SMITYPE_GPIO_CTL 41 +#define SMITYPE_XHC2_PME 42 +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_APU_SCI 54 +#define SMITYPE_INTERNAL_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +#define SMITYPE_DSM_TRIGGER_0 59 +#define SMITYPE_DSM_TRIGGER_1 60 +#define SMITYPE_USB_XHC3_PME_3 61 +#define SMITYPE_USB_XHC3_PME_4 62 +#define SMITYPE_XHC3_PME SMITYPE_USB_XHC3_PME_3 +#define SMITYPE_XHC4_PME SMITYPE_USB_XHC3_PME_4 +#define SMITYPE_CUR_TEMP_STATUS_5 63 +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +/* 67-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIAL_IRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ + +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_FAKESTS0 (1 << 25) +# define SMITRIG0_PSP SMITRIG0_FAKESTS0 +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +#define SMI_MODE_MASK 0x03 + +#endif /* AMD_STRIX_HALO_SMI_H */ diff --git a/src/soc/amd/strix_halo/include/soc/smu.h b/src/soc/amd/strix_halo/include/soc/smu.h new file mode 100644 index 00000000000..4defb947cea --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/smu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_SMU_H +#define AMD_STRIX_HALO_SMU_H + +/* SMU mailbox register offsets in SMN */ +#define SMN_SMU_MESG_ID 0x3b10928 +#define SMN_SMU_MESG_RESP 0x3b10978 +#define SMN_SMU_MESG_ARGS_BASE 0x3b10998 + +#define SMU_NUM_ARGS 6 + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0x0b, +}; + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn gets set by the SMU. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* AMD_STRIX_HALO_SMU_H */ diff --git a/src/soc/amd/strix_halo/include/soc/southbridge.h b/src/soc/amd/strix_halo/include/soc/southbridge.h new file mode 100644 index 00000000000..2d11650312c --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/southbridge.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_SOUTHBRIDGE_H +#define AMD_STRIX_HALO_SOUTHBRIDGE_H + +#include + +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_ISACONTROL 0x04 +#define ABCLKGATEEN BIT(16) +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_SERIRQ_CONF 0x54 +#define PM_SERIRQ_NUM_BITS_17 0x0000 +#define PM_SERIRQ_NUM_BITS_18 0x0004 +#define PM_SERIRQ_NUM_BITS_19 0x0008 +#define PM_SERIRQ_NUM_BITS_20 0x000c +#define PM_SERIRQ_NUM_BITS_21 0x0010 +#define PM_SERIRQ_NUM_BITS_22 0x0014 +#define PM_SERIRQ_NUM_BITS_23 0x0018 +#define PM_SERIRQ_NUM_BITS_24 0x001c +#define PM_SERIRQ_MODE BIT(6) +#define PM_SERIRQ_ENABLE BIT(7) +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) +#define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) +#define PM_SPI_PAD_PU_PD 0x90 +#define PM_LPC_GATING 0xec +#define PM_LPC_AB_NO_BYPASS_EN BIT(2) +#define PM_LPC_A20_EN BIT(1) +#define PM_LPC_ENABLE BIT(0) + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ + +/* FCH MISC Registers 0xfed80e00 */ +#define GPP_CLK_OUTPUT_AVAILABLE 7 + +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S0I3_TURNOFF_EN BIT(19) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10) +#define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) +#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ + +void fch_pre_init(void); +void fch_early_init(void); +void fch_init(void *chip_info); +void fch_final(void *chip_info); + +#endif /* AMD_STRIX_HALO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/strix_halo/include/soc/uart.h b/src/soc/amd/strix_halo/include/soc/uart.h new file mode 100644 index 00000000000..37ac2757134 --- /dev/null +++ b/src/soc/amd/strix_halo/include/soc/uart.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#ifndef AMD_STRIX_HALO_UART_H +#define AMD_STRIX_HALO_UART_H + +#include + +void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ + +#endif /* AMD_STRIX_HALO_UART_H */ diff --git a/src/soc/amd/strix_halo/mca.c b/src/soc/amd/strix_halo/mca.c new file mode 100644 index 00000000000..3dd23f646f9 --- /dev/null +++ b/src/soc/amd/strix_halo/mca.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include + +static const char *const mca_bank_name[] = { + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "L2 cache unit", + [3] = "Decode unit", + [4] = "", + [5] = "Execution unit", + [6] = "Floating point unit", + [7] = "L3 cache unit", + [8] = "L3 cache unit", + [9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "UMC", + [16] = "UMC", + [17] = "UMC", + [18] = "UMC", + [19] = "CS", + [20] = "CS", + [21] = "CS", + [22] = "CS", + [23] = "", + [24] = "", + [25] = "", + [26] = "", + [27] = "PIE", + [28] = "NBIO", + [29] = "KPX_SERDES", + [30] = "KPX_SERDES", + [31] = "", +}; + +bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + +bool mca_is_valid_bank(unsigned int bank) +{ + return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); +} + +const char *mca_get_bank_name(unsigned int bank) +{ + if (mca_is_valid_bank(bank)) + return mca_bank_name[bank]; + else + return ""; +} diff --git a/src/soc/amd/strix_halo/memmap.c b/src/soc/amd/strix_halo/memmap.c new file mode 100644 index 00000000000..fe7cab3b047 --- /dev/null +++ b/src/soc/amd/strix_halo/memmap.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + read_lower_soc_memmap_resources(dev, idx); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000); + mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/strix_halo/root_complex.c b/src/soc/amd/strix_halo/root_complex.c new file mode 100644 index 00000000000..e27bbd3e6f8 --- /dev/null +++ b/src/soc/amd/strix_halo/root_complex.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define DPTC_TOTAL_UPDATE_PARAMS 7 + +struct dptc_input { + uint16_t size; + struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; +} __packed; + +#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow, \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ + .value = _vrmCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ + .value = _vrmMaxCurrentLimit, \ + }, \ + { \ + .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ + .value = _vrmSocCurrentLimit, \ + }, \ + }, \ + } + +static void acipgen_dptci(void) +{ + const struct soc_amd_strix_halo_config *config = config_of_soc(); + + /* Normal mode DPTC values. */ + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); + + /* Low/No Battery */ + struct dptc_input no_battery_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW, + config->vrm_current_limit_throttle_mA, + config->vrm_maximum_current_limit_throttle_mA, + config->vrm_soc_current_limit_throttle_mA); + acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, + sizeof(no_battery_input)); +} + +static void root_complex_fill_ssdt(const struct device *device) +{ + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) + acipgen_dptci(); +} + +static const char *gnb_acpi_name(const struct device *dev) +{ + return "GNB"; +} + +struct device_operations strix_halo_root_complex_operations = { + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_name = gnb_acpi_name, + .acpi_fill_ssdt = root_complex_fill_ssdt, +}; + +static const struct domain_iohc_info iohc_info[] = { + [0] = { + .fabric_id = IOMS0_FABRIC_ID, + .misc_smn_base = SMN_IOHC_MISC_BASE_13B1, + }, +}; + +const struct domain_iohc_info *get_iohc_info(size_t *count) +{ + *count = ARRAY_SIZE(iohc_info); + return iohc_info; +} + +static const struct non_pci_mmio_reg non_pci_mmio[] = { + { 0x2d0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we + tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB + resource. */ + { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, + { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x310, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x320, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, +}; + +const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) +{ + *count = ARRAY_SIZE(non_pci_mmio); + return non_pci_mmio; +} diff --git a/src/soc/amd/strix_halo/smihandler.c b/src/soc/amd/strix_halo/smihandler.c new file mode 100644 index 00000000000..b0c0f583736 --- /dev/null +++ b/src/soc/amd/strix_halo/smihandler.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register + * during the SMN accesses. Since the SMI handler is the last thing that gets called before + * entering S3, this won't interfere with any indirect SMN accesses via the same register pair. + */ +static void fch_slp_typ_handler(void) +{ + uint32_t pci_ctrl, reg32; + uint16_t pm1cnt, reg16; + uint8_t slp_typ, rst_ctrl; + + /* Figure out SLP_TYP */ + pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); + slp_typ = acpi_sleep_from_pm1(pm1cnt); + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ); + + switch (slp_typ) { + case ACPI_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case ACPI_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + break; + case ACPI_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case ACPI_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + if (slp_typ >= ACPI_S3) { + wbinvd(); + + clear_all_smi_status(); + + /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ + pci_ctrl = pm_read32(PM_PCI_CTRL); + pci_ctrl &= ~FORCE_SLPSTATE_RETRY; + pm_write32(PM_PCI_CTRL, pci_ctrl); + + /* Enable SlpTyp */ + rst_ctrl = pm_read8(PM_RST_CTRL1); + rst_ctrl |= SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, rst_ctrl); + + /* + * Before the final command, check if there's pending wake + * event. Read enable first, so that reading the actual status + * is as close as possible to entering S3. The idea is to + * minimize the opportunity for a wake event to happen before + * actually entering S3. If there's a pending wake event, log + * it and continue normal path. S3 will fail and the wake event + * becomes a SCI. + */ + if (CONFIG(ELOG_GSMI)) { + reg16 = acpi_read16(MMIO_ACPI_PM1_EN); + reg16 &= acpi_read16(MMIO_ACPI_PM1_STS); + if (reg16) + elog_add_extended_event( + ELOG_SLEEP_PENDING_PM1_WAKE, + (u32)reg16); + + reg32 = acpi_read32(MMIO_ACPI_GPE0_EN); + reg32 &= acpi_read32(MMIO_ACPI_GPE0_STS); + if (reg32) + elog_add_extended_event( + ELOG_SLEEP_PENDING_GPE0_WAKE, + reg32); + } /* if (CONFIG(ELOG_GSMI)) */ + + if (slp_typ == ACPI_S3) + psp_notify_sx_info(ACPI_S3); + + smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ + printk(BIOS_ERR, "System did not go to sleep\n"); + hlt(); + } +} + +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in fch.c is unrelated to this list. + */ +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +}; + +void *get_smi_source_handler(int source) +{ + size_t i; + + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + + return NULL; +} + +void smm_soc_early_init(void) +{ + if (CONFIG(SPI_FLASH_SMM)) + fch_spi_backup_registers(); +} + +void smm_soc_exit(void) +{ + if (CONFIG(SPI_FLASH_SMM)) + fch_spi_restore_registers(); +} diff --git a/src/soc/amd/strix_halo/uart.c b/src/soc/amd/strix_halo/uart.c new file mode 100644 index 00000000000..1d3c82928f5 --- /dev/null +++ b/src/soc/amd/strix_halo/uart.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct soc_uart_ctrlr_info uart_info[] = { + [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", { + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", { + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + } }, + [2] = { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", { + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + } }, + [3] = { APU_UART3_BASE, FCH_AOAC_DEV_UART3, "FUR3", { + PAD_NF(GPIO_135, UART3_TXD, PULL_NONE), + PAD_NF(GPIO_137, UART3_RXD, PULL_NONE), + } }, + [4] = { APU_UART4_BASE, FCH_AOAC_DEV_UART4, "FUR4", { + PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), + PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), + } }, +}; + +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; +} + +void clear_uart_legacy_config(void) +{ + write16p(FCH_LEGACY_UART_DECODE, 0); +} diff --git a/src/soc/amd/strix_halo/xhci.c b/src/soc/amd/strix_halo/xhci.c new file mode 100644 index 00000000000..15408898946 --- /dev/null +++ b/src/soc/amd/strix_halo/xhci.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct sci_source xhci_sci_sources[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC3_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->path.pci.devfn == XHCI1_DEVFN) { + *gpe = xhci_sci_sources[1].gpe; + return CB_SUCCESS; + } + } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->path.pci.devfn == XHCI0_DEVFN) { + *gpe = xhci_sci_sources[0].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { + *gpe = xhci_sci_sources[2].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; + } + } + + return CB_ERR_ARG; +} + +static void configure_xhci_sci(void *unused) +{ + gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL); diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig index afdedfd94a5..f082ab73c03 100644 --- a/src/soc/amd/turin_poc/Kconfig +++ b/src/soc/amd/turin_poc/Kconfig @@ -41,6 +41,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE + select SOC_AMD_COMMON_BLOCK_HAS_ESPI1 select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN select SOC_AMD_COMMON_BLOCK_I2C @@ -61,6 +62,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART @@ -73,7 +75,6 @@ config SOC_SPECIFIC_OPTIONS select DRAM_SUPPORT_DDR5 select SSE2 select X86_AMD_FIXED_MTRRS - select X86_INIT_NEED_1_SIPI select VBOOT_X86_SHA256_ACCELERATION if VBOOT select UDK_2017_BINDING @@ -216,7 +217,6 @@ config PSP_SOFTFUSE_BITS See #57299 (NDA) for additional bit definitions. config PSPV2_MBOX_CMD_OFFSET - hex default 0x10970 endmenu diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk index 5cbcbea405a..f0591bce593 100644 --- a/src/soc/amd/turin_poc/Makefile.mk +++ b/src/soc/amd/turin_poc/Makefile.mk @@ -127,6 +127,9 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) + OPT_UCODE_FILES=$(foreach i, $(shell seq $(words $(amd_microcode_bins))), \ $(call add_opt_prefix, $(word $(i), $(amd_microcode_bins)), \ --instance $(shell printf "%x" $$(($(i)-1))) --ucode)) @@ -143,6 +146,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_SOFTFUSE) \ --use-pspsecureos \ --load-s0i3 \ + $(OPT_BIOS_FWCOMPRESS) \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ $(OPT_SPL_TABLE_FILE) \ @@ -165,7 +169,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ --location $(CONFIG_AMD_FWM_POSITION) \ - --multilevel \ --output $@ # @@ -178,8 +181,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ \ + $(OPT_BIOS_AMDCOMPRESS) --maxsize $(PSP_BIOSBIN_SIZE) else # Set FIRMWARE_LOCATION to get the microcode files diff --git a/src/soc/amd/turin_poc/acpi/mmio.asl b/src/soc/amd/turin_poc/acpi/mmio.asl index 6ec247f788a..84487be89b6 100644 --- a/src/soc/amd/turin_poc/acpi/mmio.asl +++ b/src/soc/amd/turin_poc/acpi/mmio.asl @@ -12,7 +12,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x1000) }) Name (_STA, 0xb) } diff --git a/src/soc/amd/turin_poc/domain.c b/src/soc/amd/turin_poc/domain.c index 6991fdc5270..d5eb68ac7be 100644 --- a/src/soc/amd/turin_poc/domain.c +++ b/src/soc/amd/turin_poc/domain.c @@ -104,5 +104,5 @@ struct device_operations turin_pci_domain_ops = { .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = turin_domain_acpi_name, - .acpi_fill_ssdt = pci_domain_fill_ssdt, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index cdfa0f75fd8..54b1271725f 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 334ea26e5b7..1118eb04b8f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -56,6 +56,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CAR_ENHANCED_NEM select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU @@ -120,7 +121,6 @@ config SOC_INTEL_ALDERLAKE config SOC_INTEL_RAPTORLAKE bool - select X86_INIT_NEED_1_SIPI help Intel Raptorlake support. Mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. @@ -183,15 +183,6 @@ config ALDERLAKE_CONFIGURE_DESCRIPTOR can only be done if the descriptor region is writable, and should only be used as a temporary workaround. -config ALDERLAKE_CAR_ENHANCED_NEM - bool - default y if !INTEL_CAR_NEM - select INTEL_CAR_NEM_ENHANCED - select CAR_HAS_SF_MASKS - select COS_MAPPED_TO_MSB - select CAR_HAS_L3_PROTECTED_WAYS - select INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE - config MAX_CPUS int default 32 if SOC_INTEL_RAPTORLAKE diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 6de08fc13be..47e725c1e54 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -52,4 +52,6 @@ #include /* GbE 0:1f.6 */ +#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION) #include +#endif diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 9b684d185e7..b3e29ef6d50 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -54,7 +54,6 @@ static struct { { PCI_DID_INTEL_ADL_P_ID_6, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_7, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_8, "Alderlake-P" }, - { PCI_DID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_10, "Alderlake-P" }, { PCI_DID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DID_INTEL_ADL_M_ID_2, "Alderlake-M" }, @@ -105,6 +104,7 @@ static struct { { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" }, { PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+8)" }, { PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (6+4)" }, + { PCI_DID_INTEL_RPL_S_ID_6, "Raptorlake-S (8+12)" }, }; static struct { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 8e143f0f659..2dbaea0eff5 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -92,6 +92,9 @@ enum soc_intel_alderlake_power_limits { RPL_S_8161_95W_CORE, RPL_S_8161_125W_CORE, RPL_S_8161_150W_CORE, + RPL_S_8121_35W_CORE, + RPL_S_8121_65W_CORE, + RPL_S_8121_125W_CORE, RPL_S_881_35W_CORE, RPL_S_881_65W_CORE, RPL_S_881_125W_CORE, @@ -213,6 +216,9 @@ static const struct { { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W }, { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W }, { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_35W_CORE, TDP_35W }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_65W_CORE, TDP_65W }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_125W_CORE, TDP_125W }, { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W }, { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W }, { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index a18da51a89c..4038655c93c 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -115,13 +115,13 @@ chip soc/intel/alderlake device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end - device pci 01.0 alias pcie5_0 off end - device pci 01.1 alias pcie5_1 off end + device pci 01.0 alias pcie5_0 off ops pcie_rp_ops end + device pci 01.1 alias pcie5_1 off ops pcie_rp_ops end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end device pci 05.0 alias ipu off end - device pci 06.0 alias pcie4_0 off end - device pci 06.2 alias pcie4_1 off end + device pci 06.0 alias pcie4_0 off ops pcie_rp_ops end + device pci 06.2 alias pcie4_1 off ops pcie_rp_ops end device pci 07.0 alias tbt_pcie_rp0 off chip soc/intel/common/block/usb4 use tcss_dma0 as usb4_port diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 962a46617b2..966a7bc79de 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -152,6 +152,24 @@ chip soc/intel/alderlake .tdp_pl4 = 380, }" + register "power_limits_config[RPL_S_8121_35W_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 106, + .tdp_pl4 = 194, + }" + + register "power_limits_config[RPL_S_8121_65W_CORE]" = "{ + .tdp_pl1_override = 65, + .tdp_pl2_override = 219, + .tdp_pl4 = 341, + }" + + register "power_limits_config[RPL_S_8121_125W_CORE]" = "{ + .tdp_pl1_override = 125, + .tdp_pl2_override = 253, + .tdp_pl4 = 380, + }" + register "power_limits_config[RPL_S_881_35W_CORE]" = "{ .tdp_pl1_override = 35, .tdp_pl2_override = 106, @@ -268,11 +286,11 @@ chip soc/intel/alderlake device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end - device pci 01.0 alias pcie5_0 off end - device pci 01.1 alias pcie5_1 off end + device pci 01.0 alias pcie5_0 off ops pcie_rp_ops end + device pci 01.1 alias pcie5_1 off ops pcie_rp_ops end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end - device pci 06.0 alias pcie4_0 off end + device pci 06.0 alias pcie4_0 off ops pcie_rp_ops end device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog on end diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 615bd43c310..88ce40178bd 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -217,7 +217,6 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_ADL_P_ID_6, PCI_DID_INTEL_ADL_P_ID_7, PCI_DID_INTEL_ADL_P_ID_8, - PCI_DID_INTEL_ADL_P_ID_9, PCI_DID_INTEL_ADL_P_ID_10 }; const uint16_t adl_s_mch_ids[] = { diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 700fde977b3..6eca7eb4ad9 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -76,7 +76,7 @@ static void tbt_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3d6f824502e..a6a5dc93bdc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -484,7 +484,6 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi case PCI_DID_INTEL_ADL_P_ID_6: case PCI_DID_INTEL_ADL_P_ID_7: case PCI_DID_INTEL_ADL_P_ID_8: - case PCI_DID_INTEL_ADL_P_ID_9: case PCI_DID_INTEL_ADL_P_ID_10: case PCI_DID_INTEL_RPL_P_ID_1: case PCI_DID_INTEL_RPL_P_ID_2: @@ -535,6 +534,7 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi case PCI_DID_INTEL_RPL_S_ID_3: case PCI_DID_INTEL_RPL_S_ID_4: case PCI_DID_INTEL_RPL_S_ID_5: + case PCI_DID_INTEL_RPL_S_ID_6: return ICC_MAX_RPL_S; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h index 80e656c40d5..950c173c57b 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -2,7 +2,7 @@ #ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ -#define INC(x) ((x) + 1) +#include /* * Most of the fixed numbers and macros are based on the GPP groups. * The GPIO groups are accessed through register blocks called diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h index 704b9a7233e..de950e1fc94 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h @@ -2,7 +2,7 @@ #ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_PCH_S_H_ #define _SOC_ALDERLAKE_GPIO_SOC_DEFS_PCH_S_H_ -#define INC(x) ((x) + 1) +#include /* * Most of the fixed numbers and macros are based on the GPP groups. * The GPIO groups are accessed through register blocks called diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index efeac5cecdc..d7923401c70 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -54,8 +54,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { * configuration. */ .half_channel = BIT(0), - /* In mixed topologies, either channel 0 or 1 can be memory-down. */ - .mixed_topo = BIT(0) | BIT(1), + /* In mixed topologies, channel 0 is memory-down. */ + .mixed_topo = BIT(0), }, }, [MEM_TYPE_DDR5] = { @@ -70,8 +70,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { * configuration. */ .half_channel = BIT(0), - /* In mixed topologies, either channel 0 or 1 can be memory-down. */ - .mixed_topo = BIT(0) | BIT(1), + /* In mixed topologies, channel 0 is memory-down. */ + .mixed_topo = BIT(0), }, }, [MEM_TYPE_LP4X] = { diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index d6224658aef..d0dee6c3cde 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -405,8 +405,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = config->ibecc.enable; + if (get_uint_option("ibecc_enable", config->ibecc.enable)) { + m_cfg->Ibecc = true; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 06fddc864bb..d3e529d4c0f 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -187,6 +187,9 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, @@ -260,6 +263,9 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, @@ -333,6 +339,9 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -406,6 +415,9 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 20) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d48a010342a..89c1b4dda8a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -494,4 +494,132 @@ config IFWI_MEASURED_BOOT Measuring the IBBL, IBB and TXE using either PTT or a TPM. The IBB is measured only after it has been loaded into the CSE. +config IFWI_STITCH_IMAGE + bool "Stitch of complete IFWI image" + help + Use coreboot tooling to build and sign the Apollo Lake IFWI image. + This creates BPDT/CPD/MN2 metadata and signs it with OpenSSL. + + Intel FIT and MEU are not used. + + MN2 signatures can be checked with OpenSSL after extracting the + signature and signed manifest bytes: + + openssl dgst -sha256 -verify -signature + +if IFWI_STITCH_IMAGE + +config IFWI_CSE_IMAGE + string "CSE image" + help + Path to the CSE region input image. This is required when + IFWI_STITCH_IMAGE is enabled. Extract this from the CSE/ME flash + region of a known-good vendor IFWI. + +config IFWI_PMCP + string "PMCP sub-partition binary" + help + Path to the PMCP sub-partition binary. This is required when + IFWI_STITCH_IMAGE is enabled. Extract this sub-partition from a + known-good vendor IFWI for the target board. + +config IFWI_PRIVATE_KEY + string "Key to use for manifest" + help + Path to the RSA private key used for IFWI manifest signing. This is + required when IFWI_STITCH_IMAGE is enabled. Validate the key with: + + openssl rsa -in -check -noout + +config IFWI_DESCRIPTOR + string "Flash descriptor binary" + help + Intel flash descriptor used by the native Apollo Lake IFWI stitcher. + Extract this from a reference IFWI with: + + util/ifdtool/ifdtool -x + +config IFWI_UEP_FPF_FLAGS + hex "UEP FPF flags" + default 0xc880 + help + Value to write into the generated UEP fuse-emulation records. + This is kept configurable because the value differs between known + Apollo Lake/Gemini Lake images and the UEP format is not publicly + documented. When matching a vendor IFWI, compare against the UEP + sub-partition records at offsets 0x2c and 0xc4. + +config IFWI_UEP_BOOT_POLICY + hex "UEP Boot Guard policy flags" + default 0x11f + help + Value to write into the generated UEP Boot Guard policy records. + This should match the Boot Guard policy fused for the target. When + matching a vendor IFWI, compare against the UEP sub-partition + records at offsets 0x70 and 0xc4. + +config IFWI_SMIP + string "SMIP payload or sub-partition binary" + help + SMIP payload or full SMIP CPD sub-partition used by the native + Apollo Lake IFWI stitcher. A full sub-partition is re-signed. A raw + payload is wrapped in a native SMIP CPD and signed. Leave empty to + generate a minimal SMIP payload from a dummy IAFW SMIP. + +config IFWI_FITC_CONFIG + string "fitc.cfg CSE BUP directory entry override" + help + Optional fitc.cfg directory entry override added to the CSE BUP + sub-partition by the native Apollo Lake IFWI stitcher. Leave unset + to preserve the entry from IFWI_CSE_IMAGE, or generate one if the + source CSE image has an empty entry. This is the CSE boot partition + configuration normally emitted by FIT. + +choice + prompt "fitc.cfg profile" + default IFWI_FITC_CONFIG_PROFILE_NONE + help + Board profile used when generating the CSE BUP fitc.cfg entry. + +config IFWI_FITC_CONFIG_PROFILE_NONE + bool "None" + +config IFWI_FITC_CONFIG_PROFILE_GLK + bool "Gemini Lake" + +config IFWI_FITC_CONFIG_PROFILE_GLKR + bool "Gemini Lake Refresh" + +endchoice + +config IFWI_FITC_CONFIG_PROFILE + string + default "glk" if IFWI_FITC_CONFIG_PROFILE_GLK + default "glkr" if IFWI_FITC_CONFIG_PROFILE_GLKR + default "" + +config IFWI_EC_IMAGE + string "EC region binary" + help + Optional EC region binary. Leave unset when the descriptor does not + define an EC region. + +config IFWI_BP2_OFFSET + hex "Second boot partition offset" + default 0x0 + help + Flash offset of the second logical boot partition. Use 0 to derive + the offset from the BIOS region described by the flash descriptor. + +config IFWI_FIT_TOOL_VERSION + hex "BPDT FIT tool version" + default 0x0 + help + Value to write into the BPDT FIT tool version field. This is metadata + only and is kept configurable to allow comparisons with + vendor-generated IFWI images. Extract the value from a reference + IFWI BPDT header when exact metadata matching is required. + +endif + endif diff --git a/src/soc/intel/apollolake/Makefile.mk b/src/soc/intel/apollolake/Makefile.mk index 8dc4b5fd467..839cd657c17 100644 --- a/src/soc/intel/apollolake/Makefile.mk +++ b/src/soc/intel/apollolake/Makefile.mk @@ -233,4 +233,92 @@ ifeq ($(CONFIG_IFWI_IBBM_LOAD),y) coreboot: $(objcbfs)/ibbl.rom $(objcbfs)/ibbm.rom $(objcbfs)/obb.rom endif +ifeq ($(CONFIG_IFWI_STITCH_IMAGE),y) +coreboot: $(obj)/coreboot-ifwi.rom + +ifwi_cse_image=$(call strip_quotes,$(CONFIG_IFWI_CSE_IMAGE)) +ifwi_pmcp=$(call strip_quotes,$(CONFIG_IFWI_PMCP)) +ifwi_private_key=$(call strip_quotes,$(CONFIG_IFWI_PRIVATE_KEY)) +ifwi_descriptor=$(call strip_quotes,$(CONFIG_IFWI_DESCRIPTOR)) +ifwi_smip_source=$(call strip_quotes,$(CONFIG_IFWI_SMIP)) +ifwi_fitc_config=$(call strip_quotes,$(CONFIG_IFWI_FITC_CONFIG)) +ifwi_fitc_config_profile=$(call strip_quotes,$(CONFIG_IFWI_FITC_CONFIG_PROFILE)) +ifwi_ec_image=$(call strip_quotes,$(CONFIG_IFWI_EC_IMAGE)) +ifwi_smip_arg=$(if $(ifwi_smip_source),--smip $(ifwi_smip_source),) +ifwi_smip_dep=$(if $(ifwi_smip_source),$(ifwi_smip_source),) +ifwi_fitc_profile_arg=$(if $(ifwi_fitc_config_profile),--fitc-config-profile $(ifwi_fitc_config_profile),) +empty := +space := $(empty) $(empty) +escape_spaces = $(subst $(space),\$(space),$(1)) +ifwi_cse_image_dep=$(call escape_spaces,$(ifwi_cse_image)) +ifwi_pmcp_dep=$(call escape_spaces,$(ifwi_pmcp)) +ifwi_descriptor_dep=$(call escape_spaces,$(ifwi_descriptor)) + +ifeq ($(ifwi_cse_image),) +$(error CONFIG_IFWI_CSE_IMAGE is required when CONFIG_IFWI_STITCH_IMAGE=y) +endif +ifeq ($(ifwi_pmcp),) +$(error CONFIG_IFWI_PMCP is required when CONFIG_IFWI_STITCH_IMAGE=y) +endif +ifeq ($(ifwi_private_key),) +$(error CONFIG_IFWI_PRIVATE_KEY is required when CONFIG_IFWI_STITCH_IMAGE=y) +endif +ifeq ($(ifwi_descriptor),) +$(error CONFIG_IFWI_DESCRIPTOR is required when CONFIG_IFWI_STITCH_IMAGE=y) +endif + +$(obj)/cse_image.bin: $(ifwi_cse_image_dep) + cp "$(ifwi_cse_image)" $@ + +$(obj)/pmcp.bin: $(ifwi_pmcp_dep) + cp "$(ifwi_pmcp)" $@ + +$(obj)/private.pem: $(ifwi_private_key) + cp $< $@ + +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) +patch1=3rdparty/intel-microcode/intel-ucode/06-7a-01 +patch2=3rdparty/intel-microcode/intel-ucode/06-7a-08 +else +patch1=3rdparty/intel-microcode/intel-ucode/06-5c-09 +patch2=3rdparty/intel-microcode/intel-ucode/06-5c-0a +endif + +$(obj)/coreboot-ifwi.rom: $(obj)/cse_image.bin $(CBFSTOOL) \ + $(objcbfs)/ibbl.rom $(objcbfs)/ibbm.rom \ + $(objcbfs)/obb.rom $(obj)/private.pem \ + $(obj)/pmcp.bin \ + $(ifwi_descriptor_dep) \ + $(ifwi_smip_dep) \ + $(if $(ifwi_fitc_config),$(ifwi_fitc_config),) \ + $(ifwi_ec_image) $(patch1) $(patch2) \ + util/apl_ifwi/apl_ifwi.py + python3 util/apl_ifwi/apl_ifwi.py \ + --output $@ \ + --descriptor "$(ifwi_descriptor)" \ + --cse-image $(obj)/cse_image.bin \ + --ibbl $(objcbfs)/ibbl.rom \ + --ibb $(objcbfs)/ibbm.rom \ + --obb $(objcbfs)/obb.rom \ + --private-key $(obj)/private.pem \ + --pmcp $(obj)/pmcp.bin \ + $(ifwi_smip_arg) \ + --uep-fpf-flags $(CONFIG_IFWI_UEP_FPF_FLAGS) \ + --uep-boot-policy $(CONFIG_IFWI_UEP_BOOT_POLICY) \ + --microcode $(patch1) \ + --microcode $(patch2) \ + --bp2-offset $(CONFIG_IFWI_BP2_OFFSET) \ + --fit-tool-version $(CONFIG_IFWI_FIT_TOOL_VERSION) \ + $(ifwi_fitc_profile_arg) \ + $(if $(ifwi_fitc_config),--fitc-config $(ifwi_fitc_config),) \ + $(if $(ifwi_ec_image),--ec $(ifwi_ec_image),) +ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) + printf " FMAP validate IFWI layout\n" + $(CBFSTOOL) $@ layout -w > /dev/null +endif + printf " IFWI overwrite coreboot.rom\n" + cp $@ $(obj)/coreboot.rom + +endif # CONFIG_IFWI_STITCH_IMAGE + endif # if CONFIG_SOC_INTEL_APOLLOLAKE diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 943573fff75..d888781370a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -704,13 +705,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - /* coreboot handles the lockdown */ - silconfig->LockDownGlobalSmi = 0; - silconfig->BiosLock = 0; - silconfig->BiosInterface = 0; - silconfig->WriteProtectionEnable[0] = 0; - silconfig->SpiEiss = 0; - silconfig->RtcLock = 0; + /* coreboot handles lockdown unless the board delegates it to FSP */ + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + + silconfig->LockDownGlobalSmi = lockdown_by_fsp; + silconfig->BiosLock = lockdown_by_fsp; + silconfig->BiosInterface = lockdown_by_fsp; + silconfig->WriteProtectionEnable[0] = lockdown_by_fsp; + silconfig->SpiEiss = lockdown_by_fsp; + silconfig->RtcLock = lockdown_by_fsp; /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb index 547cbee2f87..c0e67f90394 100644 --- a/src/soc/intel/apollolake/chipset_apl.cb +++ b/src/soc/intel/apollolake/chipset_apl.cb @@ -24,6 +24,7 @@ chip soc/intel/apollolake device pci 14.1 alias pcie_rp06 off ops pcie_rp_ops end # PCIE Express Root Port 6 device pci 15.0 alias xhci off ops usb_xhci_ops chip drivers/usb/acpi + register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_root_hub off chip drivers/usb/acpi diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb index dbbab3dab3b..13e4b7fa5bc 100644 --- a/src/soc/intel/apollolake/chipset_glk.cb +++ b/src/soc/intel/apollolake/chipset_glk.cb @@ -25,6 +25,7 @@ chip soc/intel/apollolake device pci 14.1 alias pcie_rp06 off ops pcie_rp_ops end # PCIE Express Root Port 6 device pci 15.0 alias xhci off ops usb_xhci_ops chip drivers/usb/acpi + register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_root_hub off chip drivers/usb/acpi diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index e82b468436a..c0906416e3c 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #define MKHI_GROUP_ID_MCA 0x0a @@ -192,7 +191,7 @@ static void dump_cse_state(void) printk(BIOS_DEBUG, "CSE: Actual IBB Size : %u\n", fwsts3.fields.ibb_size); printk(BIOS_DEBUG, "CSE: Verified Boot Valid : %s\n", - fwsts4.fields.txe_veri_boot_valid ? "PASS" : "FAIL"); + fwsts4.fields.txe_veri_boot_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "CSE: Verified Boot Test : %s\n", fwsts4.fields.txe_veri_boot_test ? "YES" : "NO"); printk(BIOS_DEBUG, "CSE: FPF status : %s\n", @@ -218,7 +217,7 @@ void heci_cse_lockdown(void) * It is safe to disable HECI1 now since we won't be talking to the ME * anymore. */ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index 52dcca8de28..c28ab7c06ca 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include diff --git a/src/soc/intel/apollolake/lockdown.c b/src/soc/intel/apollolake/lockdown.c index 5de4bdd2c13..225e14f088c 100644 --- a/src/soc/intel/apollolake/lockdown.c +++ b/src/soc/intel/apollolake/lockdown.c @@ -17,7 +17,8 @@ static void pmc_lock_smi(void) void soc_lockdown_config(int chipset_lockdown) { - /* APL only supports CHIPSET_LOCKDOWN_COREBOOT */ - if (CONFIG(SOC_INTEL_GEMINILAKE)) + /* Only Gemini Lake exposes SMI_LOCK through the PMC MMIO path. */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT && + CONFIG(SOC_INTEL_GEMINILAKE)) pmc_lock_smi(); } diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index cf50f1addae..cd6e7b80c30 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -7,28 +7,29 @@ #define _BAYTRAIL_CHIP_H_ #include +#include #include struct soc_intel_baytrail_config { - uint8_t enable_xdp_tap; + bool enable_xdp_tap; uint8_t sata_port_map; - uint8_t sata_ahci; - uint8_t ide_legacy_combined; - uint8_t clkreq_enable; + bool sata_ahci; + bool ide_legacy_combined; + bool clkreq_enable; /* VR low power settings -- enable PS2 mode for gfx and core */ - int vnn_ps2_enable; - int vcc_ps2_enable; + bool vnn_ps2_enable; + bool vcc_ps2_enable; /* Disable SLP_X stretching after SUS power well loss. */ - int disable_slp_x_stretch_sus_fail; + bool disable_slp_x_stretch_sus_fail; /* USB Port Disable mask */ uint16_t usb2_port_disable_mask; uint16_t usb3_port_disable_mask; /* USB routing */ - int usb_route_to_xhci; + bool usb_route_to_xhci; /* USB PHY settings specific to the board */ uint32_t usb2_per_port_lane0; @@ -50,12 +51,12 @@ struct soc_intel_baytrail_config { uint32_t sdcard_cap_high; /* Enable devices in ACPI mode */ - int lpss_acpi_mode; - int scc_acpi_mode; - int lpe_acpi_mode; + bool lpss_acpi_mode; + bool scc_acpi_mode; + bool lpe_acpi_mode; /* Allow PCIe devices to wake system from suspend. */ - int pcie_wake_enable; + bool pcie_wake_enable; uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; @@ -72,7 +73,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; int gpu_pipeb_pwm_freq_hz; - int disable_ddr_2x_refresh_rate; + bool disable_ddr_2x_refresh_rate; struct i915_gpu_controller_info gfx; }; diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 38e2d2fbd44..888f862e139 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -199,7 +199,7 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], } } -void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) +void setup_soc_gpios(struct soc_gpio_config *config, bool enable_xdp_tap) { if (config) { setup_gpios(config->ncore, &gpncore_bank); diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 0b19922f14d..91a7ac1e705 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -3,6 +3,7 @@ #ifndef _BAYTRAIL_GPIO_H_ #define _BAYTRAIL_GPIO_H_ +#include #include #include #include @@ -360,7 +361,7 @@ struct gpio_bank { const u8 gpio_f1_range_end; }; -void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); +void setup_soc_gpios(struct soc_gpio_config *config, bool enable_xdp_tap); /* This function is weak and can be overridden by a mainboard function. */ struct soc_gpio_config* mainboard_get_gpios(void); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 4e8dc68e080..107472f592e 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 46e36c7c484..4857aaf74af 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 572f03e33e1..173210f998d 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 27a0cce87ca..186bf7a772e 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd1eb247606..40cea8ff3f4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -12,6 +12,7 @@ config SOC_INTEL_CANNONLAKE_BASE select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO select DRAM_SUPPORT_DDR4 + select DRIVERS_INTEL_OC_MAILBOX select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZMA @@ -97,7 +98,7 @@ config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE select INTEL_CAR_NEM_ENHANCED - select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT + select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE_RAMTOP diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f4785bb3650..b8fd376a50a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -232,6 +232,9 @@ struct soc_intel_cannonlake_config { /* Heci related */ bool DisableHeciRetry; + /* Enable/Disable CPU Replacement check on CML */ + bool cpu_replacement_check; + /* Gfx related */ bool SkipExtGfxScan; diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb index ff68963c3e6..0b68bfd4b23 100644 --- a/src/soc/intel/cannonlake/chipset.cb +++ b/src/soc/intel/cannonlake/chipset.cb @@ -6,9 +6,9 @@ chip soc/intel/cannonlake device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge - device pci 01.0 alias peg0 off end # PCIe x16 - device pci 01.1 alias peg1 off end # PCIe x8 - device pci 01.2 alias peg2 off end # PCIe x4 + device pci 01.0 alias peg0 off ops pcie_rp_ops end # PCIe x16 + device pci 01.1 alias peg1 off ops pcie_rp_ops end # PCIe x8 + device pci 01.2 alias peg2 off ops pcie_rp_ops end # PCIe x4 device pci 02.0 alias igpu off end # Integrated Graphics Device device pci 04.0 alias dptf off end # SA Thermal device device pci 05.0 alias ipu off end # Imaging Processing Unit @@ -19,6 +19,7 @@ chip soc/intel/cannonlake device pci 13.0 alias ish off end # ISH device pci 14.0 alias xhci off ops usb_xhci_ops # USB xHCI chip drivers/usb/acpi + register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_root_hub off chip drivers/usb/acpi diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb index de36773c501..d04283d0235 100644 --- a/src/soc/intel/cannonlake/chipset_pch_h.cb +++ b/src/soc/intel/cannonlake/chipset_pch_h.cb @@ -6,9 +6,9 @@ chip soc/intel/cannonlake device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge - device pci 01.0 alias peg0 off end # PCIe x16 - device pci 01.1 alias peg1 off end # PCIe x8 - device pci 01.2 alias peg2 off end # PCIe x4 + device pci 01.0 alias peg0 off ops pcie_rp_ops end # PCIe x16 + device pci 01.1 alias peg1 off ops pcie_rp_ops end # PCIe x8 + device pci 01.2 alias peg2 off ops pcie_rp_ops end # PCIe x4 device pci 02.0 alias igpu off end # Integrated Graphics Device device pci 04.0 alias dptf off end # SA Thermal device device pci 05.0 alias ipu off end # Imaging Processing Unit @@ -19,6 +19,7 @@ chip soc/intel/cannonlake device pci 13.0 alias ish off end # ISH device pci 14.0 alias xhci off ops usb_xhci_ops # USB xHCI chip drivers/usb/acpi + register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_root_hub off chip drivers/usb/acpi diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 974794bd977..19fcf1387fc 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -88,7 +88,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && + if (soc_disable_heci1_at_pre_boot() && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) heci1_disable(); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2e00018f369..bd8d7e71321 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -626,8 +626,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) s_cfg->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); /* - * coreboot will handle disabling of HECI1 device if `DISABLE_HECI1_AT_PRE_BOOT` - * config is selected hence, don't let FSP to disable the HECI1 device and set + * coreboot will handle disabling of HECI1 device if DISABLE_HECI1_AT_PRE_BOOT / + * disable_heci1_at_pre_boot (CFR) applies; don't let FSP disable HECI1 and set * the `Heci1Disabled` UPD to `0`. */ s_cfg->Heci1Disabled = 0; diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 007c72282b5..222fa4310e1 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c86da261d26..9a9677bf55c 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -64,6 +64,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug)); + tconfig->SkipCpuReplacementCheck = !config->cpu_replacement_check; #else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; #endif diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index ac259908213..ed8a2ceeaef 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (soc_disable_heci1_at_pre_boot() && CONFIG(HECI_DISABLE_USING_SMM)) heci1_disable(); } diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 5cb3418ed6c..eb9018f7500 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -62,6 +63,9 @@ void soc_systemagent_init(struct device *dev) config = config_of_soc(); soc_config = &config->power_limits_config; set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + + /* Apply OC mailbox settings (e.g. undervolt) after power limits. */ + program_oc_mailbox(); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 6ab645727f6..17c594e583e 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -566,6 +566,12 @@ VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_6_2) { VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_2_2) { { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) }, }; +VR_CONFIG_TDC(PCI_DID_INTEL_WHL_ID_W_4) { + { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) }, +}; +VR_CONFIG_TDC(PCI_DID_INTEL_WHL_ID_W_2) { + { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) }, +}; VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_8_2) { { 65, performance, VR_CFG_ALL_DOMAINS_TDC(10, 146, 25, 25) }, { 65, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 117, 25, 25) }, @@ -617,6 +623,8 @@ static const struct vr_lookup vr_config_tdc[] = { VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT), VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_6_2), VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_2_2), + VR_REFITEM_TDC(PCI_DID_INTEL_WHL_ID_W_4), + VR_REFITEM_TDC(PCI_DID_INTEL_WHL_ID_W_2), VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_8_2), VR_REFITEM_TDC(PCI_DID_INTEL_CML_H), VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_4_2), diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 5e6ae6b19f6..3a47524b713 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -53,7 +53,7 @@ config INTEL_TOP_SWAP_SEPARATE_REGIONS depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK && BOOTBLOCK_IN_CBFS default n help - Place the bootblocks in BOOTBLOCK and TOPSWAP regions for easy access, to + Place the bootblocks in BOOTBLOCK and BOOTBLOCK_B regions for easy access, to facilitate firmware updates using the Top Swap as Slot A/Slot B redundancy. Requires a custom .fmd with the regions added at the end. @@ -75,7 +75,7 @@ config TOP_SWAP_REDUNDANCY select INTEL_TOP_SWAP_OPTION_CONTROL help Toggle the Intel Top Swap based redundancy, where the BOOTBLOCK and COREBOOT - regions form a read-only golden copy and TOPSWAP and COREBOOT_TS are an + regions form a read-only golden copy and BOOTBLOCK_B and COREBOOT_B are an update partition. CMOS option "attempt_top_swap" decides which of the slots gets booted, which means the platform can be reverted to the known-good copy via CMOS reset. diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index a6ae454d063..f2df6fb55af 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -16,7 +16,8 @@ #define PEP_S0IX_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" -#define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" +#define EC_S0IX_HOOK_EC "\\_SB.PCI0.LPCB.EC.S0IX" +#define EC_S0IX_HOOK_EC0 "\\_SB.PCI0.LPCB.EC0.S0IX" #define EC_DISPLAY_HOOK "\\_SB.PCI0.LPCB.EC0.EDSX" #define MAINBOARD_HOOK "\\_SB.MS0X" #define MAINBOARD_DISPLAY_HOOK "\\_SB.MDSX" @@ -232,13 +233,22 @@ static void acpi_lpi_get_constraints(void *unused) } } +static void acpigen_call_ec_s0ix_hook(int state) +{ + const char *hooks[] = { EC_S0IX_HOOK_EC, EC_S0IX_HOOK_EC0 }; + + for (size_t i = 0; i < ARRAY_SIZE(hooks); i++) { + acpigen_write_if_cond_ref_of(hooks[i]); + acpigen_emit_namestring(hooks[i]); + acpigen_write_integer(state); + acpigen_write_if_end(); + } +} + static void lpi_s0ix_entry(void *unused) { /* Inform the EC */ - acpigen_write_if_cond_ref_of(EC_S0IX_HOOK); - acpigen_emit_namestring(EC_S0IX_HOOK); - acpigen_write_integer(1); - acpigen_write_if_end(); + acpigen_call_ec_s0ix_hook(1); /* Provide a board level S0ix hook */ acpigen_write_if_cond_ref_of(MAINBOARD_HOOK); @@ -263,10 +273,7 @@ static void lpi_s0ix_entry(void *unused) static void lpi_s0ix_exit(void *unused) { /* Inform the EC */ - acpigen_write_if_cond_ref_of(EC_S0IX_HOOK); - acpigen_emit_namestring(EC_S0IX_HOOK); - acpigen_write_integer(0); - acpigen_write_if_end(); + acpigen_call_ec_s0ix_hook(0); /* Provide a board level S0ix hook */ acpigen_write_if_cond_ref_of(MAINBOARD_HOOK); diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c index 56da3cb91e6..f2b6a1a005a 100644 --- a/src/soc/intel/common/block/aspm/aspm.c +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -74,18 +74,42 @@ static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_c return UPD_INDEX(l1_substates_control); } +void __weak mainboard_get_pcie_pm_options(const struct pcie_rp_config *rp_cfg, + unsigned int index, + bool is_cpu_rp, + struct pcie_pm_option_names *names) +{ + (void)rp_cfg; + (void)index; + + names->clk_pm = "pciexp_clk_pm"; + names->l1ss = "pciexp_l1ss"; + names->aspm = is_cpu_rp ? "pciexp_aspm_cpu" : "pciexp_aspm"; + names->speed = "pciexp_speed"; +} + +static unsigned int get_pcie_pm_option(const char *opt_name, unsigned int fallback) +{ + return opt_name ? get_uint_option(opt_name, fallback) : fallback; +} + void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) + const struct pcie_rp_config *rp_cfg, + unsigned int index) { + struct pcie_pm_option_names options = {0}; + + mainboard_get_pcie_pm_options(rp_cfg, index, false, &options); + s_cfg->PcieRpEnableCpm[index] = - get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + get_pcie_pm_option(options.clk_pm, CONFIG(PCIEXP_CLK_PM)); s_cfg->PcieRpAspm[index] = - aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), false); + aspm_control_to_upd(get_pcie_pm_option(options.aspm, rp_cfg->pcie_rp_aspm), false); s_cfg->PcieRpL1Substates[index] = - l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); + l1ss_control_to_upd(get_pcie_pm_option(options.l1ss, rp_cfg->PcieRpL1Substates)); s_cfg->PcieRpPcieSpeed[index] = - pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); + pcie_speed_control_to_upd( + get_pcie_pm_option(options.speed, rp_cfg->pcie_rp_pcie_speed)); } #if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) @@ -103,17 +127,20 @@ void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, * */ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) + const struct pcie_rp_config *rp_cfg, + unsigned int index) { - bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + struct pcie_pm_option_names options = {0}; + + mainboard_get_pcie_pm_options(rp_cfg, index, true, &options); + bool pciexp_clk_pm = get_pcie_pm_option(options.clk_pm, CONFIG(PCIEXP_CLK_PM)); s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; s_cfg->CpuPcieRpAspm[index] = - aspm_control_to_upd(get_uint_option("pciexp_aspm_cpu", rp_cfg->pcie_rp_aspm), true); + aspm_control_to_upd(get_pcie_pm_option(options.aspm, rp_cfg->pcie_rp_aspm), true); s_cfg->CpuPcieRpL1Substates[index] = - l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); + l1ss_control_to_upd(get_pcie_pm_option(options.l1ss, rp_cfg->PcieRpL1Substates)); } #endif // CONFIG(HAS_INTEL_CPU_ROOT_PORTS) diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 214bd0890e8..1488432e039 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -473,10 +473,6 @@ struct device_operations cnvi_wifi_ops = { }; static const unsigned short wifi_pci_device_ids[] = { - PCI_DID_INTEL_NVL_CNVI_WIFI_0, - PCI_DID_INTEL_NVL_CNVI_WIFI_1, - PCI_DID_INTEL_NVL_CNVI_WIFI_2, - PCI_DID_INTEL_NVL_CNVI_WIFI_3, PCI_DID_INTEL_LNL_CNVI_WIFI_0, PCI_DID_INTEL_LNL_CNVI_WIFI_1, PCI_DID_INTEL_LNL_CNVI_WIFI_2, diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index e51110e1e90..40805d2bf96 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -121,6 +121,18 @@ config CAR_HAS_L3_PROTECTED_WAYS L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program the data ways. +config SOC_INTEL_COMMON_BLOCK_CAR_ENHANCED_NEM + bool + select CAR_HAS_L3_PROTECTED_WAYS if INTEL_CAR_NEM_ENHANCED + select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED + select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE if INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM + help + Common Enhanced NEM (eNEM) configuration for ADL and newer platforms. + Enables INTEL_CAR_NEM_ENHANCED along with the associated cache way + protection and snoop filter mask settings required by these SoCs. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c index fa4c8963a15..28efecc9589 100644 --- a/src/soc/intel/common/block/cpu/smmrelocate.c +++ b/src/soc/intel/common/block/cpu/smmrelocate.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 007b469ba1c..eb6f31328ec 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -331,9 +331,10 @@ cl_node_t *malloc_cl_node(size_t len) return NULL; node->data = malloc(len * sizeof(u32)); - if (!(node->data)) + if (!(node->data)) { + free(node); return NULL; - + } node->size = len * sizeof(u32); node->next = NULL; diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index ce998e4b565..2f16c63a1c5 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -302,6 +302,14 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3 This config will make mainboard use version 3 of the CSE timestamp definitions, it can be used for Panther Lake U/H. +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V5 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 5 of the CSE timestamp + definitions, it can be used for Nova Lake. Version 5 expands the + CSE boot performance response to 96 timestamp entries. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d60b9b51958..916912301d6 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -290,6 +290,26 @@ bool cse_is_hfs1_com_soft_temp_disable(void) return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } +bool cse_is_me_operational(void) +{ + return cse_is_hfs1_cws_normal() && cse_is_hfs1_com_normal(); +} + +#if ENV_RAMSTAGE +bool cse_is_me_state_requested_enabled(void) +{ + const unsigned int me_state_default = CONFIG(CSE_DEFAULT_CFR_OPTION_STATE_DISABLED); + const unsigned int me_state = get_uint_option("me_state", me_state_default); + + return me_state == 0; +} + +bool cse_is_me_enabled(void) +{ + return cse_is_me_state_requested_enabled() && cse_is_me_operational(); +} +#endif + /* * Starting from TGL platform, HFSTS1.spi_protection_mode replaces mfg_mode to indicate * SPI protection status as well as end-of-manufacturing(EOM) status where EOM flow is @@ -1430,7 +1450,7 @@ static void cse_final_ready_to_boot(void) { cse_control_global_reset_lock(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { + if (soc_disable_heci1_at_pre_boot() || cse_is_hfs1_com_soft_temp_disable()) { cse_set_to_d0i3(); heci1_disable(); } diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 625de75bb74..e943a395d13 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index a939369ecdc..c00410a427e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -562,6 +562,7 @@ static struct device_operations fast_spi_dev_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_NVL_HWSEQ_SPI, PCI_DID_INTEL_LNL_HWSEQ_SPI, PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI, PCI_DID_INTEL_ADP_P_HWSEQ_SPI, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 14893869a0a..6cf5ad9f313 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -373,6 +373,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_GT2_2, PCI_DID_INTEL_PTL_H_GT2_3, PCI_DID_INTEL_PTL_H_GT2_4, + PCI_DID_INTEL_PTL_H_GT2_5, + PCI_DID_INTEL_PTL_H_GT2_6, + PCI_DID_INTEL_PTL_H_GT2_7, PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 66ad97dd12d..b65aa4aaa18 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -30,14 +30,6 @@ struct device_operations hda_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_AUDIO_1, - PCI_DID_INTEL_NVL_AUDIO_2, - PCI_DID_INTEL_NVL_AUDIO_3, - PCI_DID_INTEL_NVL_AUDIO_4, - PCI_DID_INTEL_NVL_AUDIO_5, - PCI_DID_INTEL_NVL_AUDIO_6, - PCI_DID_INTEL_NVL_AUDIO_7, - PCI_DID_INTEL_NVL_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 8018ee573de..6ffdefd5b11 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -174,12 +174,6 @@ struct device_operations i2c_dev_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_I2C0, - PCI_DID_INTEL_NVL_I2C1, - PCI_DID_INTEL_NVL_I2C2, - PCI_DID_INTEL_NVL_I2C3, - PCI_DID_INTEL_NVL_I2C4, - PCI_DID_INTEL_NVL_I2C5, PCI_DID_INTEL_LNL_I2C0, PCI_DID_INTEL_LNL_I2C1, PCI_DID_INTEL_LNL_I2C2, diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index de81c37062e..140e6cb5fa3 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -178,10 +178,10 @@ void set_dev_core_type(void); * ... * }; * - * const struct pad_config *variant_early_gpio_table(size_t *num) + * struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) * { - * *num = ARRAY_SIZE(early_gpio_table); - * return early_gpio_table; + * *size = ARRAY_SIZE(min_pci_sleep_states); + * return min_pci_sleep_states; * } * */ diff --git a/src/soc/intel/common/block/include/intelblocks/aspm.h b/src/soc/intel/common/block/include/intelblocks/aspm.h index 297e128eb2b..3c58e8bc88d 100644 --- a/src/soc/intel/common/block/include/intelblocks/aspm.h +++ b/src/soc/intel/common/block/include/intelblocks/aspm.h @@ -3,8 +3,21 @@ #ifndef SOC_INTEL_COMMON_BLOCK_ASPM_H #define SOC_INTEL_COMMON_BLOCK_ASPM_H +#include #include +struct pcie_pm_option_names { + const char *clk_pm; + const char *aspm; + const char *l1ss; + const char *speed; +}; + +void mainboard_get_pcie_pm_options(const struct pcie_rp_config *rp_cfg, + unsigned int index, + bool is_cpu_rp, + struct pcie_pm_option_names *names); + void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, const struct pcie_rp_config *rp_cfg, unsigned int index); diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h index 0185b0c0280..3ee6acfb382 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfr.h +++ b/src/soc/intel/common/block/include/intelblocks/cfr.h @@ -184,4 +184,20 @@ static const struct sm_object bios_lock = SM_DECLARE_BOOL({ .default_value = CONFIG(BOOTMEDIA_SMM_BWP), }, WITH_CALLBACK(update_smm_bwp)); +static const struct sm_object pkg_power_limit_lock = SM_DECLARE_BOOL({ + .opt_name = "pkg_power_limit_lock", + .ui_name = "Package power limit lock", + .ui_helptext = "Lock the package power limits after programming.\n" + "This prevents the power limits from being changed by the OS or runtime tools.", + .default_value = false, +}); + +/* Same semantics as CONFIG_DISABLE_HECI1_AT_PRE_BOOT; runtime override via CMOS/CBFS. */ +static const struct sm_object disable_heci1_at_pre_boot = SM_DECLARE_BOOL({ + .opt_name = "disable_heci1_at_pre_boot", + .ui_name = "Disable HECI1 at end of boot", + .ui_helptext = "Make HECI1 (CSE) function-disabled before handing off to the payload.", + .default_value = CONFIG(DISABLE_HECI1_AT_PRE_BOOT), +}); + #endif /* SOC_INTEL_CMN_CFR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 8bed429da7b..476a8e05282 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -4,6 +4,7 @@ #define SOC_INTEL_COMMON_CSE_H #include +#include #include #include @@ -78,9 +79,6 @@ enum me_fw_sku { ME_HFS3_FW_SKU_LITE = 0x5, }; -/* Number of cse boot performance data */ -#define NUM_CSE_BOOT_PERF_DATA 64 - /* PSR_HECI_FW_DOWNGRADE_BACKUP Command */ #define PSR_HECI_FW_DOWNGRADE_BACKUP 0x3 @@ -301,6 +299,7 @@ enum csme_failure_reason { CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18, }; +#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) /* CSE boot performance data */ struct cse_boot_perf_rsp { struct mkhi_hdr hdr; @@ -314,6 +313,7 @@ struct cse_boot_perf_rsp { /* Boot performance data */ uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA]; } __packed; +#endif /* * Initialize the CSE device. @@ -485,6 +485,28 @@ bool cse_is_hfs1_com_secover_mei_msg(void); */ bool cse_is_hfs1_com_soft_temp_disable(void); +/* + * Check whether ME/CSME is operational (HFSTS1 current working state and + * operation mode are both normal). + */ +bool cse_is_me_operational(void); + +#if ENV_RAMSTAGE +/* + * Check whether ME/CSME is requested enabled via the `me_state` option. + * Returns true when `me_state` is 0 ("Enabled") and false when it is 1 + * ("Disabled"). + */ +bool cse_is_me_state_requested_enabled(void); + +/* + * Check whether ME/CSME is both requested enabled and operational. + */ +bool cse_is_me_enabled(void); +#else +static inline bool cse_is_me_state_requested_enabled(void) { return true; } +#endif + /* * Checks CSE's spi protection mode is protected or unprotected. * Returns true if CSE's spi protection mode is protected, otherwise false. @@ -542,7 +564,9 @@ bool skip_cse_sub_part_update(void); * This command retrieves a set of boot performance timestamps CSME collected during * the last platform boot flow. */ +#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); +#endif /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); @@ -643,4 +667,14 @@ bool is_cse_boot_to_rw(void); */ bool cse_check_host_cold_reset(void); +/* + * Effective DISABLE_HECI1_AT_PRE_BOOT: Kconfig default with optional CFR/CMOS + * override (option name disable_heci1_at_pre_boot). + */ +static inline bool soc_disable_heci1_at_pre_boot(void) +{ + return get_uint_option("disable_heci1_at_pre_boot", + CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) != 0; +} + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h index 66cc7f40db5..153ad46fc0e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -9,6 +9,8 @@ #include "cse_telemetry_v2.h" #elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3) #include "cse_telemetry_v3.h" +#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V5) +#include "cse_telemetry_v5.h" #endif #endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h index 4788f7a0fbf..2ee77d8de81 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h @@ -3,6 +3,9 @@ #ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H #define SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H +/* Number of CSE boot performance data entries */ +#define NUM_CSE_BOOT_PERF_DATA 64 + enum cse_boot_perf_data_v1 { /* CSME ROM start execution */ PERF_DATA_CSME_ROM_START = 0, diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h index 67eb36bfa49..a5d71049481 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h @@ -3,6 +3,9 @@ #ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H #define SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H +/* Number of CSE boot performance data entries */ +#define NUM_CSE_BOOT_PERF_DATA 64 + enum cse_boot_perf_data_v2 { /* CSME ROM start execution */ PERF_DATA_CSME_ROM_START = 0, diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h index 6dbadff986c..f9aae51b8fe 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h @@ -3,6 +3,9 @@ #ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H #define SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H +/* Number of CSE boot performance data entries */ +#define NUM_CSE_BOOT_PERF_DATA 64 + enum cse_boot_perf_data_v3 { /* CSME ROM start execution */ PERF_DATA_CSME_ROM_START = 0, diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v5.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v5.h new file mode 100644 index 00000000000..e6be304e4b3 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v5.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V5_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V5_H + +/* Number of CSE boot performance data entries */ +#define NUM_CSE_BOOT_PERF_DATA 96 + +enum cse_boot_perf_data_v5 { + /* CSME RBE set "Boot Stall Done" indication to PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, + + /* CSME got ICC_CONFIG_START message from PMC */ + PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 16, + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 17, + + /* ESE completed DMU binaries loading */ + PERF_DATA_ESE_LOAD_DMU_COMPLETED = 31, + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 35, + + /* ESE completed AUnit binaries loading */ + PERF_DATA_ESE_LOAD_AUNIT_COMPLETED = 37, + + /* Timestamp when CSME responded to BupGetEarlyBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 95, +}; + +#endif /* SOC_INTEL_COMMON_CSE_TELEMETRY_V5_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_macros.h b/src/soc/intel/common/block/include/intelblocks/gpio_macros.h new file mode 100644 index 00000000000..a033aeac093 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpio_macros.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_COMMON_BLOCK_GPIO_MACROS_H_ +#define _SOC_INTEL_COMMON_BLOCK_GPIO_MACROS_H_ + +#define INC(x) ((x) + 1) + +#endif /* _SOC_INTEL_COMMON_BLOCK_GPIO_MACROS_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 1965b36d595..26f433fb15a 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -101,6 +101,7 @@ #define PKG_POWER_LIMIT_TIME_MASK (0x7f) #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) +#define PKG_POWER_LIMIT_LOCK (1 << 31) #define MSR_CORE_MKTME_ACTIVATION 0x9ff /* SMM save state MSRs */ diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index 6052a3be235..79a89311b36 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -20,3 +20,13 @@ config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR help Mirror LPC registers for IO/MMIO to their corresponding GPMR registers. Required for platforms starting from SPT. + +config SOC_INTEL_COMMON_BLOCK_LPC_GPMR_IOC_1MB + bool + depends on SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR && SOC_INTEL_COMMON_BLOCK_IOC + help + Select this for platforms where IOC uses the 1MB GPMR/LGMR register + encoding. IOC and eSPI do not use identical address field definitions: + IOC encodes the address in bits [27:16], while eSPI uses bits [31:16]. + Enabling this option ensures LPC->GPMR mirroring uses IOC-compatible + encoding instead of assuming the eSPI field layout. diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 385f307a699..4787da70488 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -25,6 +25,7 @@ #define LPC_LGIR_MAX_WINDOW_SIZE 256 #define LPC_GENERIC_MEM_RANGE 0x98 #define LPC_LGMR_ADDR_MASK 0xffff0000 +#define LPC_LGMR_ADDR_1MB(n) ((n) >> 4) #define LPC_LGMR_EN (1 << 0) #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_DECODE_EN 0xd8 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 18cf1670af0..41703e629d3 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -241,8 +241,11 @@ void lpc_open_mmio_window(uintptr_t base, size_t size) lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_GPMR_IOC_1MB)) + lgmr = LPC_LGMR_ADDR_1MB(base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; gpmr_write32(GPMR_LPCGMR, lgmr); + } } /* diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 70a593412c7..96002804427 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ccddb8026fc..e74f509893e 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -67,20 +67,6 @@ struct device_operations pcie_rp_ops = { }; static const unsigned short pcie_device_ids[] = { - PCI_DID_INTEL_NVL_PCIE_RP1, - PCI_DID_INTEL_NVL_PCIE_RP2, - PCI_DID_INTEL_NVL_PCIE_RP3, - PCI_DID_INTEL_NVL_PCIE_RP4, - PCI_DID_INTEL_NVL_PCIE_RP5, - PCI_DID_INTEL_NVL_PCIE_RP6, - PCI_DID_INTEL_NVL_PCIE_RP7, - PCI_DID_INTEL_NVL_PCIE_RP8, - PCI_DID_INTEL_NVL_PCIE_RP9, - PCI_DID_INTEL_NVL_PCIE_RP10, - PCI_DID_INTEL_NVL_PCIE_RP11, - PCI_DID_INTEL_NVL_PCIE_RP12, - PCI_DID_INTEL_NVL_PCIE_RP13, - PCI_DID_INTEL_NVL_PCIE_RP14, PCI_DID_INTEL_LNL_PCIE_RP1, PCI_DID_INTEL_LNL_PCIE_RP2, PCI_DID_INTEL_LNL_PCIE_RP3, diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 3a7c8b4afcb..0927f9fc509 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -138,7 +139,8 @@ static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, enum pcie_rp_type rp_type, - const struct device *dev) + const struct device *dev, + bool trigger_opal_s3_unlock) { const struct device *parent = dev->upstream->dev; @@ -164,6 +166,13 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); acpigen_emit_byte(LOCAL0_OP); acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + /* + * If _ON is called while the power resource is already ON (common during + * resume), still trigger the OPAL S3 unlock request. The SMM handler will + * ignore it unless an S3 resume cycle is armed. + */ + if (trigger_opal_s3_unlock) + acpigen_write_store_int_to_namestr(APM_CNT_OPAL_S3_UNLOCK, "APMC"); acpigen_write_return_op(ONE_OP); acpigen_write_if_end(); @@ -201,6 +210,16 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); + /* + * If this root port has a storage device that can be powered down via RTD3, + * the OPAL S3 unlock may need to wait until _ON powers it back up. + * + * Writing the OPAL S3 APMC command triggers a synchronous SMI. If the OPAL + * S3 resume path is not armed, the SMM handler will ignore the request. + */ + if (trigger_opal_s3_unlock) + acpigen_write_store_int_to_namestr(APM_CNT_OPAL_S3_UNLOCK, "APMC"); + if (config->use_rp_mutex) acpigen_write_release(acpi_device_path_join(parent, RP_MUTEX_NAME)); @@ -384,10 +403,13 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) static bool mutex_created = false; const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); - static const char *const power_res_states[] = {"_PR0"}; + static const char *const power_res_states[] = {"_PR0", "_PR3"}; const struct device *parent = dev->upstream->dev; const char *scope = acpi_device_path(parent); const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); + const bool is_storage = config->is_storage || + (dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE); + const bool trigger_opal_s3_unlock = CONFIG(TCG_OPAL_S3_UNLOCK) && is_storage; const struct fieldlist fieldlist[] = { FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), FIELDLIST_RESERVED(13), @@ -473,6 +495,18 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + if (trigger_opal_s3_unlock) { + const struct opregion apm_opregion = OPREGION("APOR", SYSTEMIO, APM_CNT, 1); + const struct fieldlist apm_fieldlist[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("APMC", 8), + }; + + acpigen_write_opregion(&apm_opregion); + acpigen_write_field("APOR", apm_fieldlist, ARRAY_SIZE(apm_fieldlist), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + } + if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_L23) { pcie_rtd3_acpi_method_dl23(); pcie_rtd3_acpi_method_l23d(); @@ -506,7 +540,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) } pcie_rtd3_acpi_method_status(config); - pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev, trigger_opal_s3_unlock); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type, dev); acpigen_pop_len(); /* PowerResource */ @@ -528,8 +562,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) * Check the sibling device on the root port to see if it is storage class and add the * property for the OS to enable storage D3, or allow it to be enabled by config. */ - if (config->is_storage - || (dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE)) { + if (is_storage) { acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 4758f09f825..1855e18e8f9 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -94,7 +95,6 @@ void set_power_limits(u8 power_limit_1_time, /* Elkhartlake SoC does not shadow PKG_POWER_LIMIT MCHBAR settings to MSR correctly. */ if (CONFIG(SOC_INTEL_ELKHARTLAKE)) { - msr = rdmsr(MSR_PKG_POWER_LIMIT); msr.hi = 0; msr.lo = 0; wrmsr(MSR_PKG_POWER_LIMIT, msr); @@ -121,28 +121,33 @@ void set_power_limits(u8 power_limit_1_time, /* Get power defaults for this SKU */ msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; + tdp = msr.lo & PKG_POWER_LIMIT_MASK; + min_power = (msr.lo >> 16) & PKG_POWER_LIMIT_MASK; + max_power = msr.hi & PKG_POWER_LIMIT_MASK; + max_time = (msr.hi >> 16) & PKG_POWER_LIMIT_TIME_MASK; printk(BIOS_INFO, "CPU TDP = %u Watts\n", tdp / power_unit); if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; /* Set long term power limit to TDP */ limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); + const unsigned int tdp_pl1_override = get_uint_option("tdp_pl1_override", conf->tdp_pl1_override); + tdp_pl1 = tdp_pl1_override ? (tdp_pl1_override * power_unit) : tdp; + /* Validate against hardware limits */ + if (min_power > 0 && tdp_pl1 < min_power) { + printk(BIOS_ERR, "PL1 %uW below hardware minimum %uW, clamping\n", + tdp_pl1 / power_unit, min_power / power_unit); + tdp_pl1 = min_power; + } else if (max_power > 0 && tdp_pl1 > max_power) { + printk(BIOS_ERR, "PL1 %uW exceeds hardware maximum %uW, clamping\n", + tdp_pl1 / power_unit, max_power / power_unit); + tdp_pl1 = max_power; + } + printk(BIOS_INFO, "CPU PL1 = %u Watts\n", tdp_pl1 / power_unit); limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); @@ -155,18 +160,26 @@ void set_power_limits(u8 power_limit_1_time, /* Set short term power limit to 1.25 * TDP if no config given */ limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + const unsigned int tdp_pl2_override = get_uint_option("tdp_pl2_override", conf->tdp_pl2_override); + tdp_pl2 = tdp_pl2_override ? (tdp_pl2_override * power_unit) : ((tdp * 125) / 100); + /* Ensure PL2 isn't less than PL1 */ + if (tdp_pl2 < tdp_pl1) + tdp_pl2 = tdp_pl1; printk(BIOS_INFO, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; + if (get_uint_option("pkg_power_limit_lock", 0)) { + limit.hi |= PKG_POWER_LIMIT_LOCK; + printk(BIOS_INFO, "Locking package power limits\n"); + } + /* Power limit 2 time is only programmable on server SKU */ wrmsr(MSR_PKG_POWER_LIMIT, limit); - /* Set PL2 power limit values in MCHBAR and disable PL1 */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); + /* Set package power limit values in MCHBAR */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; /* Set PsysPl2 */ @@ -236,7 +249,7 @@ u8 get_cpu_tdp(void) /* Get power defaults for this SKU */ msr = rdmsr(MSR_PKG_POWER_SKU); - cpu_tdp = msr.lo & 0x7fff; + cpu_tdp = msr.lo & PKG_POWER_LIMIT_MASK; return cpu_tdp / power_unit; } diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 25c4444511c..eb795b41c24 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -78,7 +78,7 @@ void sync_rtc_buc_top_swap(void) const char *cbfs_fmap_region_hint(void) { if (CONFIG(INTEL_TOP_SWAP_OPTION_CONTROL) && get_rtc_buc_top_swap_status()) - return "COREBOOT_TS"; + return "COREBOOT_B"; else return "COREBOOT"; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index e0fa13e5817..fd72c256857 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,20 @@ __weak void mainboard_smi_espi_handler(void) /* no-op */ } +#define SMMSTORE_SYNC_SMI_SETTLE_USEC 50 +#define SMMSTORE_SYNC_SMI_CLEAR_TRIES 8 + +static void smmstore_drain_sync_smi(void) +{ + int i; + + for (i = 0; i < SMMSTORE_SYNC_SMI_CLEAR_TRIES; i++) { + if (!fast_spi_clear_sync_smi_status()) + return; + udelay(SMMSTORE_SYNC_SMI_SETTLE_USEC); + } +} + /* Inherited from cpu/x86/smm.h resulting in a different signature */ void southbridge_smi_set_eos(void) { @@ -132,6 +147,8 @@ void smihandler_southbridge_sleep( printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); + opal_s3_smi_sleep(slp_typ); + /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); @@ -191,6 +208,8 @@ void smihandler_southbridge_sleep( break; } + opal_s3_smi_sleep_finalize(slp_typ); + /* Allow mainboard to restore wake sources (e.g. for S5 WOL). */ mainboard_smi_sleep_finalize(slp_typ); @@ -279,12 +298,13 @@ static void southbridge_smi_store( * bit is a must prior setting SPI_BIOS_CONTROL_WPD" bit * to avoid 3-strike error. */ - fast_spi_clear_sync_smi_status(); + smmstore_drain_sync_smi(); fast_spi_disable_wp(); } /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx); + smmstore_drain_sync_smi(); save_state_ops->set_reg(RAX, node, &ret, sizeof(ret)); if (wp_enabled) { @@ -372,6 +392,9 @@ void smihandler_southbridge_apmc( break; } + if (opal_s3_smi_apmc(reg8)) + return; + mainboard_smi_apmc(reg8); } diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 5c75a2240b9..81e63625bff 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -123,10 +123,6 @@ struct device_operations spi_dev_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_HWSEQ_SPI, - PCI_DID_INTEL_NVL_SPI0, - PCI_DID_INTEL_NVL_SPI1, - PCI_DID_INTEL_NVL_SPI2, PCI_DID_INTEL_LNL_GSPI0, PCI_DID_INTEL_LNL_GSPI1, PCI_DID_INTEL_LNL_GSPI2, diff --git a/src/soc/intel/common/block/systemagent-server/systemagent_early.c b/src/soc/intel/common/block/systemagent-server/systemagent_early.c index 5cbadfc4ee7..8bf05d5457f 100644 --- a/src/soc/intel/common/block/systemagent-server/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent-server/systemagent_early.c @@ -3,7 +3,6 @@ #define __SIMPLE_DEVICE__ #include -#include #include #include #include diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7ea802ae06d..f15e71d23d3 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -543,7 +543,6 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_ADL_P_ID_6, PCI_DID_INTEL_ADL_P_ID_7, PCI_DID_INTEL_ADL_P_ID_8, - PCI_DID_INTEL_ADL_P_ID_9, PCI_DID_INTEL_ADL_P_ID_10, PCI_DID_INTEL_ADL_M_ID_1, PCI_DID_INTEL_ADL_M_ID_2, @@ -572,6 +571,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_RPL_S_ID_3, PCI_DID_INTEL_RPL_S_ID_4, PCI_DID_INTEL_RPL_S_ID_5, + PCI_DID_INTEL_RPL_S_ID_6, PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index f16d337e644..d1f9243dad4 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -363,9 +363,6 @@ struct device_operations uart_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_UART0, - PCI_DID_INTEL_NVL_UART1, - PCI_DID_INTEL_NVL_UART2, PCI_DID_INTEL_LNL_UART0, PCI_DID_INTEL_LNL_UART1, PCI_DID_INTEL_LNL_UART2, diff --git a/src/soc/intel/common/block/vtd/vtd.c b/src/soc/intel/common/block/vtd/vtd.c index 12ca151c7af..2fcd22cab1e 100644 --- a/src/soc/intel/common/block/vtd/vtd.c +++ b/src/soc/intel/common/block/vtd/vtd.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 28f8231e7be..600095718f1 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -28,7 +28,6 @@ struct device_operations usb_xdci_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_XDCI, PCI_DID_INTEL_MCC_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index a7b56e8d5cf..67c32956245 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,7 +131,6 @@ struct device_operations usb_xhci_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_NVL_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_LWB_XHCI, PCI_DID_INTEL_LWB_XHCI_SUPER, diff --git a/src/soc/intel/common/feature/cbfs_preload/Kconfig b/src/soc/intel/common/feature/cbfs_preload/Kconfig new file mode 100644 index 00000000000..2e62338a7db --- /dev/null +++ b/src/soc/intel/common/feature/cbfs_preload/Kconfig @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_FEATURE_CBFS_PRELOAD + bool + help + Include common CBFS preloading implementation for Intel SoCs. This + driver consolidates the nearly identical CBFS preloading logic across + multiple Intel platform generations. It preloads FSP-S, the payload, + and DSDT prior to device enumeration, taking chipset lockdown mode + into account. diff --git a/src/soc/intel/common/feature/cbfs_preload/Makefile.mk b/src/soc/intel/common/feature/cbfs_preload/Makefile.mk new file mode 100644 index 00000000000..119b9e6cbaa --- /dev/null +++ b/src/soc/intel/common/feature/cbfs_preload/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_CBFS_PRELOAD) += cbfs_preload.c diff --git a/src/soc/intel/pantherlake/cbfs_preload.c b/src/soc/intel/common/feature/cbfs_preload/cbfs_preload.c similarity index 71% rename from src/soc/intel/pantherlake/cbfs_preload.c rename to src/soc/intel/common/feature/cbfs_preload/cbfs_preload.c index 7e2cd56f93e..9b3113de081 100644 --- a/src/soc/intel/pantherlake/cbfs_preload.c +++ b/src/soc/intel/common/feature/cbfs_preload/cbfs_preload.c @@ -11,9 +11,11 @@ static void preload_pre_fsps(void *unused) preload_fsps(); struct soc_intel_common_config *config = chip_get_common_soc_structure(); - /* If chipset lockdown is handled by FSP, CBFS pre-loading must be completed - before FSP-S finishes. In this case, it yields better results to preload the - payload before lockdown.*/ + /* + * If chipset lockdown is handled by FSP, CBFS pre-loading must be + * completed before FSP-S finishes. In this case, it yields better + * results to preload the payload before lockdown. + */ if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP) payload_preload(); } @@ -23,8 +25,10 @@ BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, preload_pre_fsps, NULL); static void preload_post_fsps(void *unused) { struct soc_intel_common_config *config = chip_get_common_soc_structure(); - /* If the chipset lockdown is handled by FSP, SPI DMA is locked, and we cannot - preload any other CBFS files. */ + /* + * If the chipset lockdown is handled by FSP, SPI DMA is locked, and + * we cannot preload any other CBFS files. + */ if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP) return; diff --git a/src/soc/intel/common/feature/elog/Kconfig b/src/soc/intel/common/feature/elog/Kconfig new file mode 100644 index 00000000000..a0eae1b2225 --- /dev/null +++ b/src/soc/intel/common/feature/elog/Kconfig @@ -0,0 +1,19 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_FEATURE_ELOG + bool + help + Include common PCH elog implementation for modern Intel client SoCs. + This consolidates the nearly identical elog.c across multiple Intel + platform generations. Platform-specific differences are handled via + sub-options below. + +if SOC_INTEL_COMMON_FEATURE_ELOG + +config SOC_INTEL_COMMON_FEATURE_ELOG_SMBUS_WAKE + bool + help + Enable SMBUS wake source logging. Select this if the platform's + PCH includes an SMBUS controller that can generate a wake event. + +endif diff --git a/src/soc/intel/common/feature/elog/Makefile.mk b/src/soc/intel/common/feature/elog/Makefile.mk new file mode 100644 index 00000000000..ab04be00117 --- /dev/null +++ b/src/soc/intel/common/feature/elog/Makefile.mk @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ELOG) += elog.c +smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ELOG) += elog.c diff --git a/src/soc/intel/common/feature/elog/elog.c b/src/soc/intel/common/feature/elog/elog.c new file mode 100644 index 00000000000..5d8f85b51a1 --- /dev/null +++ b/src/soc/intel/common/feature/elog/elog.c @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pme_map { + unsigned int devfn; + unsigned int wake_source; +}; + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + gpe0_sts &= gpe0_en; + + for (size_t i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); + } +} + +static void pch_log_rp_wake_source(void) +{ + const struct pme_map pme_map[] = { + { PCI_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCI_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCI_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCI_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCI_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCI_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, +#if CONFIG_MAX_ROOT_PORTS > 6 + { PCI_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCI_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCI_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCI_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCI_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCI_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, +#endif +#if CONFIG_MAX_ROOT_PORTS > 12 + { PCI_DEVFN_PCIE13, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCI_DEVFN_PCIE14, ELOG_WAKE_SOURCE_PME_PCIE14 }, +#endif + }; + + for (size_t i = 0; i < ARRAY_SIZE(pme_map); i++) { + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), + PCI_FUNC(pme_map[i].devfn)))) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + +static void pch_log_pme_internal_wake_source(void) +{ + const struct pme_map ipme_map[] = { + { PCI_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCI_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCI_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCI_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCI_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { PCI_DEVFN_CNVI_BT, ELOG_WAKE_SOURCE_PME_BLUETOOTH }, + { PCI_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + }; + const struct xhci_wake_info xhci_wake_info[] = { + { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCI_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + }; + bool dev_found = false; + + for (size_t i = 0; i < ARRAY_SIZE(ipme_map); i++) { + unsigned int devfn = ipme_map[i].devfn; + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ipme_map[i].wake_source, 0); + dev_found = true; + } + } + + /* Check Thunderbolt ports */ + for (size_t i = 0; i < NUM_TBT_FUNCTIONS; i++) { + unsigned int devfn = PCI_DEVFN_TBT(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + + /* Check DMA devices */ + for (size_t i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { + unsigned int devfn = PCI_DEVFN_TCSS_DMA(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); + dev_found = true; + } + } + + /* + * Probe the XHCI controllers and their USB2 and USB3 ports to determine + * if any of them were wake sources. + */ + dev_found |= xhci_update_wake_event(xhci_wake_info, ARRAY_SIZE(xhci_wake_info)); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express */ + if (ps->pm1_sts & PCIEXPWAK_STS) + pch_log_rp_wake_source(); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + pch_log_pme_internal_wake_source(); + + /* SMBUS Wake */ + if (CONFIG(SOC_INTEL_COMMON_FEATURE_ELOG_SMBUS_WAKE) && + (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(const struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* CSME-Initiated Host Reset with power down */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD) + elog_add_event(ELOG_TYPE_MI_HRPD); + + /* CSME-Initiated Host Reset with power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC) + elog_add_event(ELOG_TYPE_MI_HRPC); + + /* CSME-Initiated Host Reset without power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR) + elog_add_event(ELOG_TYPE_MI_HR); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO2_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +#if CONFIG(POSTPONE_SPI_ACCESS) +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, pch_log_state, NULL); +#else +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); +#endif + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/common/feature/finalize/finalize.c b/src/soc/intel/common/feature/finalize/finalize.c index 7830fb8e637..362c1ec6d21 100644 --- a/src/soc/intel/common/feature/finalize/finalize.c +++ b/src/soc/intel/common/feature/finalize/finalize.c @@ -51,7 +51,7 @@ static void sa_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/common/feature/smihandler/smihandler.c b/src/soc/intel/common/feature/smihandler/smihandler.c index 35726049d03..60a0fd79db0 100644 --- a/src/soc/intel/common/feature/smihandler/smihandler.c +++ b/src/soc/intel/common/feature/smihandler/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f97fdf3e04b..a0f787d33be 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index a3abfe650d5..5cf60f7d4f2 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -78,6 +78,10 @@ config SOC_INTEL_ELKHARTLAKE if SOC_INTEL_ELKHARTLAKE +config CHIPSET_DEVICETREE + string + default "soc/intel/elkhartlake/chipset.cb" + config MAX_CPUS int default 4 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e7593f8d146..07fdcf4831b 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -26,6 +26,11 @@ /* Define config parameters for In-Band ECC (IBECC). */ #define MAX_IBECC_REGIONS 8 +/* Define max PCIe Link EQ coefficients. */ +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10 +/* Define max PCIe Link EQ preset list. */ +#define PCIE_LINK_EQ_PRESETS_MAX 11 + enum ibecc_mode { IBECC_PER_REGION, IBECC_NONE, @@ -108,6 +113,18 @@ enum sata_speed_limit { SATA_GEN2 }; +/* PCIe equalization method */ +enum pcie_eq_method { + HARDWARE_EQ, + FIXED_EQ +}; + +/* PCIe equalization mode */ +enum pcie_eq_mode { + PRESET_EQ, + COEFFICIENT_EQ +}; + struct soc_intel_elkhartlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -250,6 +267,17 @@ struct soc_intel_elkhartlake_config { /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */ uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS]; + /* PCIe link equalization settings */ + bool PcieEqOverrideDefault; + enum pcie_eq_method PcieEqMethod; + enum pcie_eq_mode PcieEqMode; + uint8_t PcieEqPh3NumberOfPresetsOrCoefficients; + uint8_t PcieEqPh3PreCursorList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; + uint8_t PcieEqPh3PostCursorList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; + uint8_t PcieEqPh3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; + uint32_t PcieEqPh1DownstreamPortTransmitterPreset; + uint32_t PcieEqPh1UpstreamPortTransmitterPreset; + /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcDdr50Enabled; @@ -400,6 +428,9 @@ struct soc_intel_elkhartlake_config { unsigned int spread_spectrum; } fivr; + /* IccMax limit for IA (CPU) domain in 1/4 A units (0-1020) */ + uint16_t IccMax; + /* * PCH power button override period. * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s diff --git a/src/soc/intel/elkhartlake/chipset.cb b/src/soc/intel/elkhartlake/chipset.cb new file mode 100644 index 00000000000..98991c6c9b1 --- /dev/null +++ b/src/soc/intel/elkhartlake/chipset.cb @@ -0,0 +1,3 @@ +chip soc/intel/elkhartlake + device cpu_cluster 0 on end +end diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 275413b4efa..509eda5aaa7 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -34,7 +34,7 @@ static void pch_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 082acaf7ae2..dc614662d91 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -393,6 +393,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; } + /* PCIe link equalization config */ + if (config->PcieEqOverrideDefault) { + params->PcieEqOverrideDefault = !!config->PcieEqOverrideDefault; + params->PcieEqMethod = config->PcieEqMethod; + params->PcieEqMode = config->PcieEqMode; + params->PcieEqPh3NumberOfPresetsOrCoefficients = + config->PcieEqPh3NumberOfPresetsOrCoefficients; + for (i = 0; i < PCIE_LINK_EQ_COEFFICIENTS_MAX; i++) { + params->PcieEqPh3PreCursorList[i] = + config->PcieEqPh3PreCursorList[i]; + params->PcieEqPh3PostCursorList[i] = + config->PcieEqPh3PostCursorList[i]; + } + for (i = 0; i < PCIE_LINK_EQ_PRESETS_MAX; i++) { + params->PcieEqPh3PresetList[i] = + config->PcieEqPh3PresetList[i]; + } + params->PcieEqPh1DownstreamPortTransmitterPreset = + config->PcieEqPh1DownstreamPortTransmitterPreset; + params->PcieEqPh1UpstreamPortTransmitterPreset = + config->PcieEqPh1UpstreamPortTransmitterPreset; + } + /* SATA config */ params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); if (params->SataEnable) { @@ -460,7 +483,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX; params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX; params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX; - params->IccMax[0] = ICC_LIMIT_MAX; + params->IccMax[0] = config->IccMax ? config->IccMax : ICC_LIMIT_MAX; params->OneCoreRatioLimit = CORE_RATIO_LIMIT; params->TwoCoreRatioLimit = CORE_RATIO_LIMIT; params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 71bd473ca87..6422a9ef1c8 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -136,8 +137,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->FClkFrequency = 0x1; /* Ib-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = !!config->ibecc.enable; + if (get_uint_option("ibecc_enable", config->ibecc.enable)) { + m_cfg->Ibecc = true; m_cfg->IbeccParity = !!config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) { diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c index eb5a57642f1..266bdbdbea6 100644 --- a/src/soc/intel/elkhartlake/smihandler.c +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -16,7 +15,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 6092824b84a..5d38ad4a5ad 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3fdf82db975..5c809299876 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -329,16 +329,6 @@ struct soc_intel_jasperlake_config { */ uint8_t cpu_ratio_override; - /* Skip CPU replacement check - * - * Setting this option to skip CPU replacement check to avoid the forced MRC training - * for the platforms with soldered down SOC. - * - * false: disable - * true: enable - */ - bool SkipCpuReplacementCheck; - /* * SLP_S3 Minimum Assertion Width Policy * 1 = 60us diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb index cbd5d2efc9f..b687e4e4c59 100644 --- a/src/soc/intel/jasperlake/chipset.cb +++ b/src/soc/intel/jasperlake/chipset.cb @@ -14,6 +14,7 @@ chip soc/intel/jasperlake device pci 12.6 alias gspi2 off ops spi_dev_ops end device pci 14.0 alias south_xhci off ops usb_xhci_ops chip drivers/usb/acpi + register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_root_hub off chip drivers/usb/acpi diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 68d88625b64..e9f6f079a6c 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -139,8 +139,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, FSP_ARRAY_LOAD(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable); FSP_ARRAY_LOAD(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable); - /* Skip the CPU replacement check */ - m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; + /* Skip the CPU replacement check - JSL is a soldered SoC */ + m_cfg->SkipCpuReplacementCheck = 1; /* * Set GpioOverride diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index f2294fe05de..9ea2b2cb60d 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -16,7 +15,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); } diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 0fa2facbe75..76c6b6697d9 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -58,6 +58,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CAR_ENHANCED_NEM select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU @@ -117,7 +118,6 @@ config SOC_INTEL_METEORLAKE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING - select X86_INIT_NEED_1_SIPI select INTEL_KEYLOCKER help Intel Meteorlake support. Mainboards should specify the SoC @@ -160,15 +160,6 @@ config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI -config METEORLAKE_CAR_ENHANCED_NEM - bool - default y if !INTEL_CAR_NEM - select INTEL_CAR_NEM_ENHANCED - select CAR_HAS_SF_MASKS - select COS_MAPPED_TO_MSB - select CAR_HAS_L3_PROTECTED_WAYS - select INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE - config MAX_CPUS int default 22 diff --git a/src/soc/intel/meteorlake/cse_telemetry.c b/src/soc/intel/meteorlake/cse_telemetry.c index 6a599c9306e..a0271ce92c2 100644 --- a/src/soc/intel/meteorlake/cse_telemetry.c +++ b/src/soc/intel/meteorlake/cse_telemetry.c @@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); - timestamp_add(TS_ISSE_DMU_LOAD_END, + timestamp_add(TS_DMU_LOAD_END, start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]); } diff --git a/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h index 09f9b2b3b6b..5846e4eaad6 100644 --- a/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h @@ -2,7 +2,7 @@ #ifndef _SOC_METEORLAKE_GPIO_SOC_DEFS_H_ #define _SOC_METEORLAKE_GPIO_SOC_DEFS_H_ -#define INC(x) ((x) + 1) +#include /* * Most of the fixed numbers and macros are based on the GPP groups. diff --git a/src/soc/intel/meteorlake/include/soc/meminit.h b/src/soc/intel/meteorlake/include/soc/meminit.h index cd978504b6e..0ed05104ae4 100644 --- a/src/soc/intel/meteorlake/include/soc/meminit.h +++ b/src/soc/intel/meteorlake/include/soc/meminit.h @@ -100,9 +100,6 @@ struct mb_cfg { /* Board type */ uint8_t UserBd; - /* Command Mirror */ - uint8_t CmdMirror; - /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ uint8_t LpDdrDqDqsReTraining; }; diff --git a/src/soc/intel/meteorlake/include/soc/soc_info.h b/src/soc/intel/meteorlake/include/soc/soc_info.h index 99ab1b5888d..879e0912dd5 100644 --- a/src/soc/intel/meteorlake/include/soc/soc_info.h +++ b/src/soc/intel/meteorlake/include/soc/soc_info.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + uint8_t get_max_usb20_port(void); uint8_t get_max_usb30_port(void); uint8_t get_max_tcss_port(void); diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index f4cde7e168f..eb405bf8a8e 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -46,8 +46,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { * configuration. */ .half_channel = BIT(0), - /* In mixed topologies, either channel 0 or 1 can be memory-down. */ - .mixed_topo = BIT(0) | BIT(1), + /* In mixed topologies, channel 0 is memory-down. */ + .mixed_topo = BIT(0), }, }, [MEM_TYPE_LP5X] = { diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index d6c0b04782b..e85daa98b1b 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -308,6 +308,15 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + + /* + * Get HDA Subsystem Vendor ID and Device ID from devicetree + * and set it in FSPM UPD. + */ + const struct device_path path = { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_HDA }; + const struct device *dev = find_dev_path(pci_root_bus(), &path); + if (is_dev_enabled(dev) && dev->subsystem_vendor && dev->subsystem_device) + m_cfg->PchHdaSubSystemIds = dev->subsystem_vendor | (dev->subsystem_device << 16); } static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, @@ -386,8 +395,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = config->ibecc.enable; + if (get_uint_option("ibecc_enable", config->ibecc.enable)) { + m_cfg->Ibecc = true; m_cfg->IbeccParity = config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { diff --git a/src/soc/intel/meteorlake/soc_info.c b/src/soc/intel/meteorlake/soc_info.c index 275d56876c3..ed179e3ecfd 100644 --- a/src/soc/intel/meteorlake/soc_info.c +++ b/src/soc/intel/meteorlake/soc_info.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/intel/novalake/Kconfig b/src/soc/intel/novalake/Kconfig new file mode 100644 index 00000000000..7381c12b3e0 --- /dev/null +++ b/src/soc/intel/novalake/Kconfig @@ -0,0 +1,479 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_NOVALAKE_BASE + bool + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_ALL_STAGES_X86_64 + select ARCH_X86 + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CBFS_PRELOAD + select COOP_MULTITASKING + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_VOLTAGE + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS + select DEFAULT_X2APIC_RUNTIME + select DISPLAY_FSP_VERSION_INFO_2 + select DRAM_SUPPORT_DDR5 + select DRIVERS_USB_ACPI + select FAST_SPI_DMA + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_COMPRESS_FSP_S_LZ4 + select FSP_DIMM_INFO + select FSP_M_XIP + select FSPS_HAS_ARCH_UPD + select FSP_USES_CB_DEBUG_EVENT_HANDLER + select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP + select HAVE_FSP_GOP + select HAVE_HYPERTHREADING + select HAVE_INTEL_COMPLIANCE_TEST_MODE + select HAVE_SMI_HANDLER + select HAVE_X86_64_SUPPORT + select IDT_IN_EVERY_STAGE + select INTEL_DESCRIPTOR_MODE_CAPABLE + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select INTEL_GMA_OPREGION_2_1 + select INTEL_GMA_VERSION_2 + select INTEL_KEYLOCKER + select IOAPIC + select MICROCODE_BLOB_UNDISCLOSED + select MP_SERVICES_PPI_V2 + select MRC_CACHE_USING_MRC_VERSION + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select PCIE_CLOCK_CONTROL_THROUGH_P2SB + select PLATFORM_USES_FSP2_4 + select PMC_GLOBAL_RESET_ENABLE_LOCK + select POSTPONE_SPI_ACCESS + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM + select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CAR_ENHANCED_NEM + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES + select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + select SOC_INTEL_COMMON_BLOCK_IOC + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IRQ + select SOC_INTEL_COMMON_BLOCK_LPC_GPMR_IOC_1MB + select SOC_INTEL_COMMON_BLOCK_ME_SPEC_21 + select SOC_INTEL_COMMON_BLOCK_MEMINIT + select SOC_INTEL_COMMON_BLOCK_P2SB2 + select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + select SOC_INTEL_COMMON_BLOCK_PMC_EPOC + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + select SOC_INTEL_COMMON_BLOCK_TRACEHUB + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_FEATURE + select SOC_INTEL_COMMON_FEATURE_CBFS_PRELOAD + select SOC_INTEL_COMMON_FEATURE_ELOG + select SOC_INTEL_COMMON_FEATURE_ESPI + select SOC_INTEL_COMMON_FEATURE_FINALIZE + select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN + select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN + select SOC_INTEL_COMMON_FEATURE_LOCKDOWN + select SOC_INTEL_COMMON_FEATURE_PMUTIL + select SOC_INTEL_COMMON_FEATURE_SMIHANDLER + select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE + select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN + select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF + select SOC_INTEL_COMMON_FEATURE_UART_DEVICES + select SOC_INTEL_COMMON_FSP_RESET + select SOC_INTEL_COMMON_PCH_CLIENT + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_SEND_EOP_LATE + select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION + select SOC_QDF_DYNAMIC_READ_PMC + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_202302_BINDING + select USE_X86_64_SUPPORT + help + Intel Nova Lake support. Mainboards should specify the SoC + type using the `SOC_INTEL_NOVALAKE_*` options instead + of selecting this option directly. + +config SOC_INTEL_NOVALAKE + bool + select SOC_INTEL_NOVALAKE_BASE + help + Intel Nova Lake SoC. This should be selected by all Nova Lake SoC variants. + +config SOC_INTEL_NOVALAKE_H_P + bool + select SOC_INTEL_NOVALAKE + help + Choose this option if the mainboard is built using either a NVL-H or + NVL-P system-on-a-chip SoC. + +if SOC_INTEL_NOVALAKE_BASE + +config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR + default y if CHROMEOS_ENABLE_ESOL + +config SOC_INTEL_NOVALAKE_TCSS_USB4_SUPPORT + bool + default y + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + +config MAX_CPUS + int + default 28 + +config DCACHE_RAM_BASE + default 0xfc200000 # NVL unused area 5MB + +config DCACHE_RAM_SIZE + default 0x200000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x88000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement + (~32KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x80100 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config HEAP_SIZE + hex + default 0x200000 + +config CHIPSET_DEVICETREE + string + default "soc/intel/novalake/chipset.cb" + +config EXT_BIOS_WIN_BASE + default 0xf8000000 + +config EXT_BIOS_WIN_SIZE + default 0x2000000 + +config IFD_CHIPSET + string + default "nvl" + +config IED_REGION_SIZE + hex + default 0x400000 + +# Intel recommends reserving the PCIe TBT root port resources as below: +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 + +endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config MAX_TBT_ROOT_PORTS + int + default 3 + +config MAX_TCSS_PORTS + int + default 3 + +config MAX_ROOT_PORTS + int + default 14 + +config MAX_PCIE_CLOCK_SRC + int + default 9 + +config SMM_TSEG_SIZE + hex + default 0x2000000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0x4100000000 + help + This option allows you to select MMIO Base Address of P2SB#1 aka SoC P2SB. + +config P2SB_2_PCR_BASE_ADDRESS + hex + default 0x4110000000 + help + This option allows you to select MMIO Base Address of P2SB#2 aka SoC P2SB2. + +config ECAM_MMCONF_BASE_ADDRESS + default 0xE0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config CPU_XTAL_HZ + default 38400000 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 2 + +config SOC_INTEL_SPI_DEV_MAX + int + default 2 + +config SOC_INTEL_SPI_PSF_DESTINATION_ID + hex + default 0x5140 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_I3C_DEV_MAX + int + default 2 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config SOC_INTEL_USB2_DEV_MAX + int + default 8 + +config SOC_INTEL_USB3_DEV_MAX + int + default 2 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xFE02C000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +config VBT_DATA_SIZE_KB + int + default 9 + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clock * M) /(N *16) +# NVL UART source clock: 100MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x25a + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0x7fff + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VBOOT_X86_RSA_ACCELERATION + select VBOOT_X86_SHA256_ACCELERATION + +# Default hash block size is 1KiB. Increasing it to 4KiB to improve +# hashing time as well as read time. +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x1000 + +config CBFS_SIZE + hex + default 0x200000 + +config CBFS_MCACHE_SIZE + hex + default 0x8000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x40000 if BUILDING_WITH_DEBUG_FSP + default 0x2000 + +config CONSOLE_CBMEM_BUFFER_SIZE + hex + default 0x100000 if BUILDING_WITH_DEBUG_FSP + default 0x40000 + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/novalake/" + +# Override platform debug consent value: +# 0: Disabled, +# 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix, +# 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix, +# 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional +# low power state, +# 7: User needs to configure Advanced Debug Settings manually. +config SOC_INTEL_COMMON_DEBUG_CONSENT + int + default 4 if SOC_INTEL_DEBUG_CONSENT + +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config DIMM_MAX + default 16 + +config MRC_CHANNEL_WIDTH + int + default 16 + +config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET + hex + default 0x800000 + +config DROP_CPU_FEATURE_PROGRAM_IN_FSP + bool + default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS + default n + help + This is to avoid FSP running basic CPU feature programming on BSP + and on APs using the "CpuFeaturesPei.efi" module. The feature programming + includes enabling x2APIC, MCA, MCE and Turbo etc. + + Most of these feature programming are getting performed today in scope + of coreboot doing MP Init. Running these redundant programming in scope + of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) would + results in CPU exception. + + SoC users to select this config after dropping "CpuFeaturesPei.ffs" module + from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional + feature programming on BSP and APs. + + This feature is default enabled, in case of "coreboot running MP init" + aka MP_SERVICES_PPI_V2_NOOP config is selected. + +config PCIE_LTR_MAX_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max snoop latency value defaults to 15.73 ms. + +config PCIE_LTR_MAX_NO_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms. + +# The default offset to store CSE RW FW version information is at 68. +# However, in Intel Nova Lake based systems that use PSR, the additional +# size required to keep CSE RW FW version information and PSR back-up status +# in adjacent CMOS memory at offset 68 is not available. Therefore, we +# override the default offset to 161, which has enough space to keep both +# the CSE related information together. +config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET + int + default 161 + +config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ + default 0x2005 + help + slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Nova Lake. + +config SOC_PHYSICAL_ADDRESS_WIDTH + int + default 42 + +config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 38400000 + +# Override DEBUG Kconfig to avoid false alarm about stack overflow. +config DEBUG_STACK_OVERFLOW_BREAKPOINTS + bool + default n + +config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES + bool + default n + +# Increase the CBFS cache size to accommodate FSP-S binary pre-loading +# process. +config RAMSTAGE_CBFS_CACHE_SIZE + default 0xd0000 + +# Fast SPI DMA operations require 1 KiB-aligned memory buffers. +config CBFS_CACHE_ALIGN + default 1024 + +endif diff --git a/src/soc/intel/novalake/Makefile.mk b/src/soc/intel/novalake/Makefile.mk new file mode 100644 index 00000000000..3cab901f68c --- /dev/null +++ b/src/soc/intel/novalake/Makefile.mk @@ -0,0 +1,42 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_NOVALAKE_BASE),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += romstage + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gpio.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/pcd.c +bootblock-y += bootblock/report_platform.c + +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c +romstage-y += meminit.c +romstage-y += pcie_rp.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +ramstage-y += fsp_params.c +ramstage-y += p2sb.c +ramstage-y += pcie_rp.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += retimer.c +ramstage-y += systemagent.c +ramstage-y += tcss.c +ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += xhci.c + +CPPFLAGS_common += -I$(src)/soc/intel/novalake +CPPFLAGS_common += -I$(src)/soc/intel/novalake/include + +endif diff --git a/src/soc/intel/novalake/acpi.c b/src/soc/intel/novalake/acpi.c new file mode 100644 index 00000000000..ba4be544b1d --- /dev/null +++ b/src/soc/intel/novalake/acpi.c @@ -0,0 +1,354 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C6_SHORT_LAT, /* 3 */ + C_STATE_C6_LONG_LAT, /* 4 */ + C_STATE_C7_SHORT_LAT, /* 5 */ + C_STATE_C7_LONG_LAT, /* 6 */ + C_STATE_C7S_SHORT_LAT, /* 7 */ + C_STATE_C7S_LONG_LAT, /* 8 */ + C_STATE_C8, /* 9 */ + C_STATE_C9, /* 10 */ + C_STATE_C10, /* 11 */ + NUM_C_STATES +}; + +static const acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = {}, + [C_STATE_C1] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C8_LATENCY, + .power = C8_POWER, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C9_LATENCY, + .power = C9_POWER, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C10_LATENCY, + .power = C10_POWER, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_non_s0ix[] = { + C_STATE_C1, + C_STATE_C6_LONG_LAT, + C_STATE_C7S_LONG_LAT +}; + +static int cstate_set_s0ix[] = { + C_STATE_C1, + C_STATE_C6_LONG_LAT, + C_STATE_C10 +}; + +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + static bool c_state_initialized; + size_t i; + + if (c_state_initialized) + return map; + + const config_t *config = config_of_soc(); + if (config == NULL) { + printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); + return NULL; + } + + int *set; + if (config->s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } + + for (i = 0; i < *entries; i++) { + map[i] = cstate_map[set[i]]; + map[i].ctype = i + 1; + } + c_state_initialized = true; + + return map; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + const config_t *config = config_of_soc(); + if (config == NULL) { + printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); + return; + } + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, cores_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + const config_t *config = config_of_soc(); + if (config == NULL) { + printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); + return; + } + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = sizeof(uint32_t); + + fill_fadt_extended_pm_io(fadt); + + if (config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +static struct min_sleep_state min_pci_sleep_states[] = { + { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, +}; + +struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) +{ + *size = ARRAY_SIZE(min_pci_sleep_states); + return min_pci_sleep_states; +} + +uint32_t soc_read_sci_irq_select(void) +{ + return read32p(soc_read_pmc_base() + IRQ_REG); +} + +static unsigned long soc_fill_dmar(unsigned long current) +{ + uint32_t vtd_engine_enabled = MCHBAR32(GFXVTBAR); + const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool is_ipu_enabled = is_devfn_enabled(PCI_DEVFN_IPU); + bool is_dptf_enabled = is_devfn_enabled(PCI_DEVFN_DPTF); + bool is_npu_enabled = is_devfn_enabled(PCI_DEVFN_NPU); + bool is_iaa_enabled = is_devfn_enabled(PCI_DEVFN_IAA); + bool is_telemetry_enabled = is_devfn_enabled(PCI_DEVFN_TELEMETRY); + + printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx 0x%x\n", __func__, gfxvtbar, MCHBAR32(GFXVTBAR)); + if (vtd_engine_enabled & GFXVT_ENABLED) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar, GFXVT_BASE_SIZE); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + if ((is_ipu_enabled || is_dptf_enabled || is_telemetry_enabled || is_npu_enabled || + is_iaa_enabled) && (vtd_engine_enabled & NONGFXVT_ENABLED)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + 0, 0, (uint64_t)VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE); + if (is_ipu_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); + if (is_dptf_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0); + if (is_telemetry_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_TELEMETRY, 0); + if (is_npu_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0); + if (is_iaa_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + if (vtd_engine_enabled & IOCVT_ENABLED) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, (uint64_t)IOCVTD_BASE_ADDRESS, IOCVTD_BASE_SIZE); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, + V_P2SB_CFG_HBDF_DEV, V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* Add RMRR entry */ + if (vtd_engine_enabled & GFXVT_ENABLED) { + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + } + + if (is_ipu_enabled || is_npu_enabled || is_iaa_enabled) { + const unsigned long tmp = current; + current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + if (is_ipu_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); + if (is_npu_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0); + if (is_iaa_enabled) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0); + + acpi_dmar_satc_fixup(tmp, current); + } + return current; +} + +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(GFXVTBAR) & (GFXVT_ENABLED | NONGFXVT_ENABLED | IOCVT_ENABLED))) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + const config_t *config = config_of_soc(); + if (config == NULL) { + printk(BIOS_ERR, "Configuration could not be retrieved.\n"); + return; + } + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_HIGH; +} diff --git a/src/soc/intel/novalake/acpi/camera_clock_ctl.asl b/src/soc/intel/novalake/acpi/camera_clock_ctl.asl new file mode 100644 index 00000000000..1bdd07e40f4 --- /dev/null +++ b/src/soc/intel/novalake/acpi/camera_clock_ctl.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x3 +#define B_ICLK_PCR_REQUEST 0x4 + +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + +Scope (\_SB.PCI0) { + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 + /* + * Helper function for Read And Or Write + * Arg0 : Clock source select + * Arg1 : And data + * Arg2 : Or data + */ + Method (RAOW, 3, Serialized) + { + OperationRegion (ICLK, SystemMemory, (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 + } + + /* + * Clock control Method + * Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5) + * Arg1: Frequency select + * 2'b00 - 19p2 XTAL + * 2'b01 - 19p2 IMG + * 2'b10 - 19p2 RTC + * 2'b11 - 24 IMG + */ + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) + } +} diff --git a/src/soc/intel/novalake/acpi/gpio.asl b/src/soc/intel/novalake/acpi/gpio.asl new file mode 100644 index 00000000000..ed6012d34aa --- /dev/null +++ b/src/soc/intel/novalake/acpi/gpio.asl @@ -0,0 +1,956 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GPIO_SW_REVISION 0x00010000 + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= COM0_GRP_PAD_START && Arg0 <= COM0_GRP_PAD_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - COM0_GRP_PAD_START + } + /* GPIO Community 1 */ + If (Arg0 >= COM1_GRP_PAD_START && Arg0 <= COM1_GRP_PAD_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - COM1_GRP_PAD_START + } + /* GPIO Community 3 */ + If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - COM3_GRP_PAD_START + } + /* GPIO Community 4 */ + If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - COM4_GRP_PAD_START + } + /* GPIO Community 5*/ + If (Arg0 >= COM5_GRP_PAD_START && Arg0 <= COM5_GRP_PAD_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - COM5_GRP_PAD_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_3) { + Local0 = PID_GPIOCOM3 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS) + } +} + +/* + * GPIO _CRS + * Returns Interrupt and memory resources required for GPIO controller + * + * Arg0 - GPIO Port ID Offset for given community + */ +Method (GCRS, 0x1, Serialized) { + Name (RBFL,ResourceTemplate() { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { + GPIO_IRQ14 + } + QWordMemory ( + ResourceConsumer, , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, /* AddressGranularity */ + 0x0000000000000000, /* AddressMinimum _MIN */ + 0x000000000000FFFF, /* AddressMaximum _MAX */ + 0x0, /* AddressTranslation */ + GPIO_BASE_SIZE, /* RangeLength _LEN */ + , , + RBL0, + AddressRangeMemory, + ) + }) + CreateQWordField (RBFL, RBL0._MIN, CML0) + CreateQWordField (RBFL, RBL0._MAX, CMX0) + CML0 = PCRB (Arg0) + CMX0 = CML0 + GPIO_BASE_SIZE - 1 + Return (RBFL) +} + +/* GPIO Community 0: GPP_D, GPP_C */ +Device (GPI0) +{ + Name (_HID, ACPI_GPIO_HID) + Name (_CID, ACPI_GPIO_CID) + Name (_UID, GPP_COMM0_ID) + Name (_DDN, "GPIO Controller 0") + + Method (_CRS, 0, NotSerialized) + { + Return (^^GCRS (PID_GPIOCOM0)) + } + + Name (_DSD, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x08) + { + Package (0x02) + { + "intc-gpio-sw-revision", + GPIO_SW_REVISION + }, + + Package (0x02) + { + "intc-gpio-community-name", + GPP_COMM0_NAME + }, + + Package (0x02) + { + "intc-gpio-group-count", + NUM_COM0_GROUPS + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + PAD_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + PAD_CFG_LOCK_REG_0 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + HOSTSW_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + GPI_INT_STS_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + GPI_INT_EN_0 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPD + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPC + } + } + }) + + /* first bank/group in community 0: GPP_D */ + Name (GPPD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_D_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_D_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_D_START_OFFSET + } + } + }) + + /* 2nd bank/group in community 0: GPP_C */ + Name (GPPC, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_C_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_C_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_C_START_OFFSET + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* GPIO Community 1: GPP_F, GPP_E */ +Device (GPI1) +{ + Name (_HID, ACPI_GPIO_HID) + Name (_CID, ACPI_GPIO_CID) + Name (_UID, GPP_COMM1_ID) + Name (_DDN, "GPIO Controller 1") + + Method (_CRS, 0, NotSerialized) + { + Return (^^GCRS (PID_GPIOCOM1)) + } + + Name (_DSD, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x08) + { + Package (0x02) + { + "intc-gpio-sw-revision", + GPIO_SW_REVISION + }, + + Package (0x02) + { + "intc-gpio-community-name", + GPP_COMM1_NAME + }, + + Package (0x02) + { + "intc-gpio-group-count", + NUM_COM1_GROUPS + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + PAD_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + PAD_CFG_LOCK_REG_0 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + HOSTSW_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + GPI_INT_STS_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + GPI_INT_EN_0 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPF + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPE + }, + + } + }) + /* first bank/group in community 1: GPP_F */ + Name (GPPF, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_F_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_F_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_F_START_OFFSET + } + } + }) + /* 2nd bank/group in community 1: GPP_E */ + Name (GPPE, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_E_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_E_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_E_START_OFFSET + } + } + }) + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* GPIO Community 3: CPUJTAG1 (reserved), CPUJTAG (reserved), GPP_H, GPP_A, VGPIO3 */ +Device (GPI3) +{ + Name (_HID, ACPI_GPIO_HID) + Name (_CID, ACPI_GPIO_CID) + Name (_UID, GPP_COMM3_ID) + Name (_DDN, "GPIO Controller 2") + + Method (_CRS, 0, NotSerialized) + { + Return (^^GCRS (PID_GPIOCOM3)) + } + + Name (_DSD, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x08) + { + Package (0x02) + { + "intc-gpio-sw-revision", + GPIO_SW_REVISION + }, + + Package (0x02) + { + "intc-gpio-community-name", + GPP_COMM3_NAME + }, + + Package (0x02) + { + "intc-gpio-group-count", + NUM_COM3_GROUPS + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + PAD_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + PAD_CFG_LOCK_REG_0 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + HOSTSW_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + GPI_INT_STS_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + GPI_INT_EN_0 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x05) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + RSV1 + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + RSV2 + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + GPPH + }, + + Package (0x02) + { + "intc-gpio-group-3-subproperties", + GPPA + }, + + Package (0x02) + { + "intc-gpio-group-4-subproperties", + VGP3 + } + } + }) + /* first bank/group in community 3: RSV1 */ + Name (RSV1, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "RSV1" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_RSVD1_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_RSVD1_START_OFFSET + } + } + }) + + /* 2nd bank/group in community 3: RSV2 */ + Name (RSV2, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "RSV2" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_RSVD2_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_RSVD2_START_OFFSET + } + } + }) + + /* 3rd bank/group in community 3: GPP_H */ + Name (GPPH, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_H_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_H_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_H_START_OFFSET + } + } + }) + + /* 4th bank/group in community 3: GPP_A */ + Name (GPPA, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_A_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_A_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_A_START_OFFSET + } + } + }) + + /* 5th bank/group in community 3: VGPIO3 */ + Name (VGP3, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_VGPIO3_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_VGPIO3_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_VGPIO3_START_OFFSET + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* GPIO Community 4: GPP_S */ +Device (GPI4) +{ + Name (_HID, ACPI_GPIO_HID) + Name (_CID, ACPI_GPIO_CID) + Name (_UID, GPP_COMM4_ID) + Name (_DDN, "GPIO Controller 3") + + Method (_CRS, 0, NotSerialized) + { + Return (^^GCRS (PID_GPIOCOM4)) + } + + Name (_DSD, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x08) + { + Package (0x02) + { + "intc-gpio-sw-revision", + GPIO_SW_REVISION + }, + + Package (0x02) + { + "intc-gpio-community-name", + GPP_COMM4_NAME + }, + + Package (0x02) + { + "intc-gpio-group-count", + NUM_COM4_GROUPS + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + PAD_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + PAD_CFG_LOCK_REG_0 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + HOSTSW_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + GPI_INT_STS_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + GPI_INT_EN_0 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPS + } + } + }) + /* only bank/group in community 4: GPP_S */ + Name (GPPS, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_S_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_S_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_S_START_OFFSET + } + } + }) + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* GPIO Community 5: GPP_B, GPP_V, VGPIO */ +Device (GPI5) +{ + Name (_HID, ACPI_GPIO_HID) + Name (_CID, ACPI_GPIO_CID) + Name (_UID, GPP_COMM5_ID) + Name (_DDN, "GPIO Controller 4") + + Method (_CRS, 0, NotSerialized) + { + Return (^^GCRS (PID_GPIOCOM5)) + } + + Name (_DSD, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x08) + { + Package (0x02) + { + "intc-gpio-sw-revision", + GPIO_SW_REVISION + }, + + Package (0x02) + { + "intc-gpio-community-name", + GPP_COMM5_NAME + }, + + Package (0x02) + { + "intc-gpio-group-count", + NUM_COM5_GROUPS + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + // 0xD0 + PAD_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + PAD_CFG_LOCK_REG_0 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + HOSTSW_OWN_REG_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + GPI_INT_STS_0 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + GPI_INT_EN_0 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPB + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPV + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + VGP0 + } + } + }) + /* first bank/group in community 5: GPP_B */ + Name (GPPB, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_B_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_B_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_B_START_OFFSET + } + } + }) + /* 2nd bank/group in community 5: GPP_V */ + Name (GPPV, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_V_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_V_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_V_START_OFFSET + } + } + }) + /* 3rd bank/group in community 5: VGPIO */ + Name (VGP0, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + GPP_VGPIO_NAME + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_VGPIO_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_VGPIO_START_OFFSET + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} diff --git a/src/soc/intel/novalake/acpi/hda.asl b/src/soc/intel/novalake/acpi/hda.asl new file mode 100644 index 00000000000..fc6cb4e505c --- /dev/null +++ b/src/soc/intel/novalake/acpi/hda.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) +} diff --git a/src/soc/intel/novalake/acpi/pcie.asl b/src/soc/intel/novalake/acpi/pcie.asl new file mode 100644 index 00000000000..638e8b93ed3 --- /dev/null +++ b/src/soc/intel/novalake/acpi/pcie.asl @@ -0,0 +1,335 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x00060000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x00060001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x00060002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x00060003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP13) +{ + Name (_ADR, 0x00060004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x00060005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/novalake/acpi/serialio.asl b/src/soc/intel/novalake/acpi/serialio.asl new file mode 100644 index 00000000000..1571f5ecd25 --- /dev/null +++ b/src/soc/intel/novalake/acpi/serialio.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (FSPI) +{ + Name (_ADR, 0x001f0005) + Name (_DDN, "Fast SPI") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/novalake/acpi/southbridge.asl b/src/soc/intel/novalake/acpi/southbridge.asl new file mode 100644 index 00000000000..3619967098c --- /dev/null +++ b/src/soc/intel/novalake/acpi/southbridge.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* PCR access */ +#include + +/* PCIE src clock control */ +#include + +/* PCH clock */ +#include "camera_clock_ctl.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include + +/* PCH HDA */ +#include "hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* ISH 0:1a.0 */ +#if CONFIG(DRIVERS_INTEL_ISH) +#include +#endif + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PMC Shared SRAM 0:14.2 */ +#include + +/* CSE/HECI #1 0:16.0 */ +#include + +/* PCI _OSC */ +#include + +/* GbE 0:1f.6 */ +#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION) +#include +#endif + +/* UFS 0:17:0 */ +#include + +/* P2B access for IOST */ +#include diff --git a/src/soc/intel/novalake/acpi/tcss.asl b/src/soc/intel/novalake/acpi/tcss.asl new file mode 100644 index 00000000000..ddc103709d5 --- /dev/null +++ b/src/soc/intel/novalake/acpi/tcss.asl @@ -0,0 +1,702 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* + * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), + * USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers. + * PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1. + */ +#define TCSS_TBT_PCIE0_RP0 0 +#define TCSS_TBT_PCIE0_RP1 1 +#define TCSS_TBT_PCIE0_RP2 2 +#define TCSS_TBT_PCIE0_RP3 3 +#define TCSS_XHCI 4 +#define TCSS_XDCI 5 +#define TCSS_DMA0 6 +#define TCSS_DMA1 7 + +/* + * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + * Command code 0x15 + * Description: Gateway command for handling TCSS DEVEN clear/restore. + * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from + * a pre-defined set of subcommands. + */ +#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015 +#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */ +#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */ +#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100 + +#define MCHBAR_TCSS_DEVEN_OFFSET 0x73a8 +#define MCHBAR_TCSS_PCODE_MAILBOX 0x5da0 + +#define REVISION_ID 1 +#define UNRECOGNIZED_UUID 0x4 +#define UNRECOGNIZED_REVISION 0x8 + +#define USB_TUNNELING 0x1 +#define DISPLAY_PORT_TUNNELING 0x2 +#define PCIE_TUNNELING 0x4 +#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8 + +Scope (\_SB) +{ + /* + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be + * found in Device 31, Function 2, Offset 40h. + */ + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) + Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset(0x6c), /* 0x6C, General Purpose Event 0 Status [127:96] */ + , 19, + CPWS, 1, /* CPU WAKE STATUS */ + Offset(0x7c), /* 0x7C, General Purpose Event 0 Enable [127:96] */ + , 19, + CPWE, 1 /* CPU WAKE EN */ + } + + Name (C2PW, 0) /* Set default value to 0. */ + + /* + * C2PM (CPU to PCH Method) + * + * This object is Enable/Disable GPE_CPU_WAKE_EN. + * Arguments: (4) + * Arg0 - An Integer containing the device wake capability + * Arg1 - An Integer containing the target system state + * Arg2 - An Integer containing the target device state + * Arg3 - An Integer containing the request device type + * Return Value: + * return 0 + */ + Method (C2PM, 4, NotSerialized) + { + Local0 = 1 << Arg3 + /* This method is used to enable/disable wake from Tcss Device (WKEN). */ + If (Arg0 && Arg1) + { /* If entering Sx and enabling wake, need to enable WAKE capability. */ + If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */ + If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */ + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { /* If Staying in S0 or Disabling Wake. */ + If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */ + /* If CPU WAKE EN is not set, Set it. */ + If (CPWE == 0) { + /* If CPU WAKE STATUS is set, Clear it. */ + If (CPWS) { + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { + /* + * Disable runtime PME, either because staying in D0 or + * disabling wake. + */ + If ((C2PW & Local0) != 0) { + /* + * Clear Corresponding Device En BIT in C2PW. + */ + C2PW &= ~Local0 + } + If ((CPWE != 0) && (C2PW == 0)) { + /* + * If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN + * by writing 0. + */ + CPWE = 0 + } + } + } + Return (0) + } + + Method (_OSC, 4, Serialized) + { + CreateDWordField (Arg3, 0, CDW1) + If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) { + /* Platform-Wide _OSC Capabilities + * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities + * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4 + * support. The OS sets this bit to indicate support for an OSPM-native + * USB4 Connection Manager which handles USB4 connection events and + * link management. + */ + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + } + Return (Arg3) +#if CONFIG(SOFTWARE_CONNECTION_MANAGER) + /* + * Software Connection Manager doesn't work with Linux 5.13 or later and + * results in TBT ports timing out. Not advertising this results in + * Firmware Connection Manager being used and TBT works correctly. + */ + } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { + /* + * Operating System Capabilities for USB4 + * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. + * Third DWORD: OSPM control field for USB4. + * bit 0: USB tunneling + * bit 1: DisplayPort tunneling + * bit 2: PCIe tunneling + * bit 3: Inter-domain USB4 internet protocol + * bit 31:4: reserved + * Return: The platform acknowledges the capabilities buffer by + * returning a buffer of DWORD of the same length. Masked/Cleared bits + * in the control field indicate that the platform does not permit OSPM + * control of the respectively capabilities or features. + */ + CreateDWordField (Arg3, 8, CDW3) + Local0 = CDW3 + + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + Return (Arg3) + } + Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | + INTER_DOMAIN_USB4_INTERNET_PROTOCOL + CDW3 = Local0 + Return (Arg3) +#endif + } Else { + CDW1 |= UNRECOGNIZED_UUID + Return (Arg3) + } + } +} + +Scope (_GPE) +{ + /* TCSS PCI Express Hot-Plug wake event */ + Method (_L77, 0, NotSerialized) + { + /* + * Delay for 100ms to meet the timing requirements of the PCI Express Base + * Specification, Revision 1.0A, Section 6.6 ("...software must wait at least + * 100ms from the end of reset of one or more device before it is permitted + * to issue Configuration Requests to those devices"). + */ + Sleep (100) + + If (CondRefOf (\_SB.PCI0.TXHC)) { + /* Invoke PCIe root ports wake event handler */ + \_SB.PCI0.TRP0.HPEV() + \_SB.PCI0.TRP1.HPEV() + \_SB.PCI0.TRP2.HPEV() + } + + /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { + If (\_SB.PCI0.TRP0.PDCX) { + /* Clear all status bits */ + \_SB.PCI0.TRP0.PDCX = 1 + \_SB.PCI0.TRP0.HPSX = 1 + /* + * Intercept Presence Detect Changed interrupt and make sure + * the L0s is disabled on empty slots. + */ + If (!\_SB.PCI0.TRP0.PDSX) { + /* + * The PCIe slot is empty, so disable L0s on hot unplug. + */ + \_SB.PCI0.TRP0.L0SE = 0 + } + /* Performs proper notification to the OS. */ + Notify (\_SB.PCI0.TRP0, 0) + } Else { + /* False event. Clear Hot-Plug status, then exit. */ + \_SB.PCI0.TRP0.HPSX = 1 + } + } + + /* Check Root Port 1 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) { + If (\_SB.PCI0.TRP1.PDCX) { + \_SB.PCI0.TRP1.PDCX = 1 + \_SB.PCI0.TRP1.HPSX = 1 + If (!\_SB.PCI0.TRP1.PDSX) { + \_SB.PCI0.TRP1.L0SE = 0 + } + Notify (\_SB.PCI0.TRP1, 0) + } Else { + \_SB.PCI0.TRP1.HPSX = 1 + } + } + + /* Check Root Port 2 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) { + If (\_SB.PCI0.TRP2.PDCX) { + \_SB.PCI0.TRP2.PDCX = 1 + \_SB.PCI0.TRP2.HPSX = 1 + If (!\_SB.PCI0.TRP2.PDSX) { + \_SB.PCI0.TRP2.L0SE = 0 + } + Notify (\_SB.PCI0.TRP2, 0) + } Else { + \_SB.PCI0.TRP2.HPSX = 1 + } + } + } + + /* TCSS PCI Express power management event */ + Method (_L76, 0, Serialized) + { + If (CondRefOf (\_SB.PCI0.TXHC)) { + If (\_SB.PCI0.TRP0.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP0, 0x2) + } + + If (\_SB.PCI0.TRP1.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP1, 0x2) + } + + If (\_SB.PCI0.TRP2.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP2, 0x2) + } + } + + /* Invoke PCIe root ports power management status handler */ + \_SB.PCI0.TRP0.HPME() + \_SB.PCI0.TRP1.HPME() + \_SB.PCI0.TRP2.HPME() + } +} + +Scope (\_SB.PCI0) +{ + Device (IOM) + { + Name (_HID, "INTC107A") + Name (_DDN, "Intel(R) Nova Lake Input Output Manager(IOM) driver") + /* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */ + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, 0x0, + IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0, + IOM_BASE_SIZE,,,) + }) +#if CONFIG(IOM_ACPI_DEVICE_VISIBLE) + /* ACPI_STATUS_DEVICE_ALL_ON */ + Name (_STA, 0xF) +#else + /* ACPI_STATUS_DEVICE_HIDDEN_ON */ + Name (_STA, 0xB) +#endif + } + + OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4) + Field (TDEN, ByteAcc, NoLock, Preserve) + { + TRE0, 1, /* PCIE0_EN */ + TRE1, 1, /* PCIE1_EN */ + TRE2, 1, /* PCIE2_EN */ + TRE3, 1, /* PCIE3_EN */ + , 4, + THCE, 1, /* XHCI_EN */ + TDCE, 1, /* XDCI_EN */ + DME0, 1, /* TBT_DMA0_EN */ + DME1, 1, /* TBT_DMA1_EN */ + , 20 + } + + OperationRegion (PBAR, SystemMemory, (GMHB() + MCHBAR_TCSS_PCODE_MAILBOX), 0x08) + Field (PBAR, DWordAcc, NoLock, Preserve) + { + PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */ + PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */ + PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */ + , 15, /* Reserved */ + PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */ + } + + /* + * Poll pCode MailBox Ready + * + * Return 0xFF - Timeout + * 0x00 - Ready + */ + Method (PMBY, 0) + { + Local0 = 0 + While (PMBR && (Local0 < 1000)) { + Local0++ + Stall (1) + } + If (Local0 == 1000) { + Printf("Timeout occurred.") + Return (0xFF) + } + Return (0) + } + + + /* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */ + OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100) + Field (IOMR, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 15, + TD3C, 1, /* [15:15] Type C D3 cold bit */ + TACK, 1, /* [16:16] IOM Acknowledge bit */ + DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ + /* display is OFF, clear otherwise */ + Offset(0x44), /* SW_CONFIG_2 */ + DPHD, 1, /* [0:0] DP_ALT and DP Tunneling HPD assertion */ + Offset(0x48), /* SW_CONFIG_3 */ + , 12, + INDP, 1, /* [12:12] The capability of monitoring the DP_ALT and DP tunneling */ + Offset(0x70), /* Physical addr is offset 0x70. */ + IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ + IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ + } + + /* + * TBT Group0 ON method + */ + Method (TG0N, 0) + { + If (DME0 == 1) { + If (\_SB.PCI0.TDM0.STAT == 0) { + /* DMA0 is in D3Cold early. */ + Printf("TG0N: TDM0 D3 cold exit") + \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* RP0 D3 cold exit. */ + Printf("TG0N: RP0 D3 cold exit") + \_SB.PCI0.TRP0.D3CX() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* RP1 D3 cold exit. */ + Printf("TG0N: RP1 D3 cold exit") + \_SB.PCI0.TRP1.D3CX() + } + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* RP2 D3 cold exit. */ + Printf("TG0N: RP2 D3 cold exit") + \_SB.PCI0.TRP2.D3CX() + } + } Else { + Printf("Drop TG0N due to it is already exit D3 cold.") + } + + } + } + + /* + * TBT Group0 OFF method + */ + Method (TG0F, 0) + { + If (DME0 == 1) { + If (\_SB.PCI0.TDM0.STAT == 1) { + /* DMA0 is not in D3Cold now. */ + Printf("TG0F: TDM0 D3 cold enter") + \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* Put RP0 to D3 cold. */ + Printf("TG0F: RP0 D3 cold enter") + \_SB.PCI0.TRP0.D3CE() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* Put RP1 to D3 cold. */ + Printf("TG0F: RP1 D3 cold enter") + \_SB.PCI0.TRP1.D3CE() + } + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* Put RP2 to D3 cold. */ + Printf("TG0F: RP2 D3 cold enter") + \_SB.PCI0.TRP2.D3CE() + } + } + } + } + + + PowerResource (TBT0, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } + } + + +#if CONFIG(D3COLD_SUPPORT) + Method (TCON, 0) + { + /* Reset IOM D3 cold bit if it is in D3 cold now. */ + If (TD3C == 1) /* It was in D3 cold before. */ + { + /* Reset IOM D3 cold bit. */ + TD3C = 0 /* Request IOM for D3 cold exit sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ + Local0++ + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: TCON TACK Timeout occurred.") + TD3C = 1 /* Failed, revert back. */ + } + Else + { + Printf("TCON: TCSS D3 exit."); + } + } + Else { + Printf("Drop TCON due to it is already exit D3 cold.") + } + } + + Method (TCOF, 0) + { + If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0)) + { + Printf("TCOF: Skip D3C entry.") + Return + } + + /* Set IOM D3 cold bit if it is in D0 now. */ + If (TD3C == 0) /* It was in D3 cold exit (D0) before. */ + { + /* Set IOM D3 cold bit. */ + TD3C = 1 /* Request IOM for D3 cold enter sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK == 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 1 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ + Local0++ + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: TCOF TACK Timeout occurred.") + TD3C = 0 /* Failed, revert back. */ + } + Else + { + Printf("PowerResource D3C => TCOF TACK=1 TCSS D3 Cold Enter."); + } + } + Else { + Printf("Drop TCOF as it is already in D3 Cold.") + } + } + + PowerResource (D3C, 5, 0) + { + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } + } +#endif // D3COLD_SUPPORT + + /* + * TCSS xHCI device + */ + Device (TXHC) + { + Name (_ADR, 0x000D0000) + Name (_DDN, "North XHCI controller") + Name (_STR, Unicode ("North XHCI controller")) + Name (DCPM, TCSS_XHCI) + + Method (_STA, 0x0, NotSerialized) + { + If (THCE == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_xhci.asl" + } + + /* + * TCSS DMA0 device + */ + Device (TDM0) + { + Name (_ADR, 0x000D0002) + Name (_DDN, "TBT DMA0 controller") + Name (_STR, Unicode ("TBT DMA0 controller")) + Name (DUID, 0) /* TBT DMA number */ + Name (DCPM, TCSS_DMA0) + + Method (_STA, 0x0, NotSerialized) + { + Printf ("TDM0._STA: DME0:%o", ToHexString(DME0)) + If (DME0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_dma.asl" + } + + /* + * TCSS PCIE Root Port #00 + */ + Device (TRP0) + { + Name (_ADR, 0x00070000) + Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP0) + + Method (_STA, 0x0, NotSerialized) + { + If (VDID != 0xFFFFFFFF) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #01 + */ + Device (TRP1) + { + Name (_ADR, 0x00070001) + Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP1) + + Method (_STA, 0x0, NotSerialized) + { + If (VDID != 0xFFFFFFFF) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #02 + */ + Device (TRP2) + { + Name (_ADR, 0x00070002) + Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP2) + + Method (_STA, 0x0, NotSerialized) + { + If (VDID != 0xFFFFFFFF) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + +} diff --git a/src/soc/intel/novalake/acpi/tcss_dma.asl b/src/soc/intel/novalake/acpi/tcss_dma.asl new file mode 100644 index 00000000000..f119a6e83e6 --- /dev/null +++ b/src/soc/intel/novalake/acpi/tcss_dma.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) +Field (DPME, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x84), /* 0x84, DMA CFG PM CAP */ + PMST, 2, /* 1:0, PM_STATE */ + , 6, + PMEE, 1, /* 8, PME_EN */ + , 6, + PMES, 1, /* 15, PME_STATUS */ + Offset(0xc8), /* 0xC8, TBT NVM FW Revision */ + , 31, + INFR, 1, /* TBT NVM FW Ready */ + Offset(0xec), /* 0xEC, TBT TO PCIE Register */ + TB2P, 32, /* TBT to PCIe */ + P2TB, 32, /* PCIe to TBT */ + Offset(0xfc), /* 0xFC, DMA RTD3 Force Power */ + DD3E, 1, /* 0:0 DMA RTD3 Enable */ + DFPE, 1, /* 1:1 DMA Force Power */ + Offset (0xff), + DMAD, 8 /* 31:24 DMA Active Delay */ +} + +/* IUHR: IOM USB4 Host Router */ +OperationRegion (IUHR, SystemMemory, IOM_BASE_ADDR, 0x600) +Field (IUHR, DWordAcc, NoLock, Preserve) +{ + Offset(0x594), /* USB4HR_MISC_CONFIG */ + U0D3, 1 /* [0:0] USB4HR0_RTD3_PWR_EN */ +} + +OperationRegion (DPEE, SystemMemory, BASE(_ADR), 0x100) +Field (DPEE, AnyAcc, NoLock, Preserve) +{ + Offset (0x00), + Offset (0x84), + XPME, 16 +} + +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ +Name (PMCS, Zero) + +Method (_S0W, 0x0) +{ +#if CONFIG(D3COLD_SUPPORT) + Printf("TDM0 _S0W: 0x04") + Return (0x04) +#else + Printf("TDM0 _S0W: 0x03") + Return (0x03) +#endif // D3COLD_SUPPORT +} + +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ +Method (_PR0) +{ +#if CONFIG(D3COLD_SUPPORT) + Printf("TDM0 _PR0: D3C") + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) +#else + Printf("TDM0 _PR0: D3Hot") + Return (Package() { \_SB.PCI0.TBT0 }) +#endif // D3COLD_SUPPORT +} + +Method (_PR3) +{ +#if CONFIG(D3COLD_SUPPORT) + Printf("TDM0 _PR3: D3C") + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + +#else + Printf("TDM0 _PR3: D3Hot") + Return (Package() { \_SB.PCI0.TBT0 }) +#endif // D3COLD_SUPPORT +} + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + + U0D3 = 0x01 /* Disable RTD3, power on USB4 HR */ + STAT = 0x01 + + If (CondRefOf (VDID)) + { + Local0 = 0xC8 + Local1 = Zero + While (((STAT == One) && (VDID == 0xFFFFFFFF))) + { + If ((Local1 == 0x001E8480)) + { + Printf("TDM0 D3CX Timeout. ") + Break + } + Else + { + Stall (Local0) + Local1 += 0xC8 + } + } + } + + Local2 = XPME + If ((PMCS == Zero)) + { + Printf("TDM0 D3CX PMCS is 0x0, not restoring PMCSR") + } + Else + { + If (((Local2 & 0x03) != (PMCS & 0x03))) + { + Local3 = (PMCS & 0x7FFF) + XPME = Local3 + PMCS = Zero + } + } +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + U0D3 = 0x0 /* Enable RTD3, power off USB4 HR */ + STAT = 0x00 + PMCS = XPME +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x65, 4 }) +} diff --git a/src/soc/intel/novalake/acpi/tcss_pcierp.asl b/src/soc/intel/novalake/acpi/tcss_pcierp.asl new file mode 100644 index 00000000000..427b214df2f --- /dev/null +++ b/src/soc/intel/novalake/acpi/tcss_pcierp.asl @@ -0,0 +1,314 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * TCSS PCIE RP Channel Configuration (CCFG) Config Space register offsets + * MPC - Miscellaneous Port Configuration Register + * RPPGEN - Root Port Power Gating Enable Register + * SMSCS - SMI/SCI Status Register + */ +#define PXCS_OPREGION_SIZE 0xc00 +#define TCSS_CFG_MPC_FROM_CCFG 0xba8 +#define TCSS_CFG_SMSCS_FROM_CCFG 0xbac +#define TCSS_CFG_RPPGEN_FROM_CCFG 0xbb2 + +OperationRegion (PXCS, SystemMemory, BASE(_ADR), PXCS_OPREGION_SIZE) +Field (PXCS, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x50), /* LCTL - Link Control Register */ + L0SE, 1, /* 0, L0s Entry Enabled */ + , 3, + LDIS, 1, /* 1, Link Disable */ + , 4, + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + Offset(0x5a), /* SLSTS[7:0] - Slot Status Register */ + ABPX, 1, /* 0, Attention Button Pressed */ + , 2, + PDCX, 1, /* 3, Presence Detect Changed */ + , 2, + PDSX, 1, /* 6, Presence Detect State */ + , 1, + DLSC, 1, /* 8, Data Link Layer State Changed */ + Offset(0x60), /* RSTS - Root Status Register */ + Offset(0x62), + PSPX, 1, /* 16, PME Status */ + Offset (0x68), + , 10, + LNRE, 1, /* LTR Mechanism Enable */ + Offset(0xA4), + D3HT, 2, /* Power State */ + Offset (0x404), + LSOE, 1, + LNSE, 1, + Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */ + , 30, + DPGE, 1, /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */ + /* Power Gating Enable (DLSULPPGE) */ + Offset(0x5bc), /* 0x5bc, PCIE ADVMCTRL */ + , 3, + RPER, 1, /* RTD3PERST[3] */ + RPFE, 1, /* RTD3PFETDIS[4] */ + Offset(TCSS_CFG_MPC_FROM_CCFG), /* 0xba8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + Offset(TCSS_CFG_RPPGEN_FROM_CCFG), /* 0xbb2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ +} + +Field (PXCS, AnyAcc, NoLock, WriteAsZeros) +{ + Offset(TCSS_CFG_SMSCS_FROM_CCFG), /* 0xbac, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +/* + * _DSM Device Specific Method + * + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0x00 }) +} + +/* + * A bitmask of functions support + */ +Name(OPTS, Buffer(2) {0, 0}) + +Device (PXSX) +{ + Name (_ADR, 0x00000000) + + /* + * _DSM Device Specific Method + * + * Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + * Arg1: Revision ID: 3 + * Arg2: Function index: 0, 9 + * Arg3: Empty package + */ + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + If (Arg1 >= 3) { + If (Arg2 == 0) { + /* + * Function index: 0 + * Standard query - A bitmask of functions supported + */ + CreateBitField(OPTS, 9, FUN9) + FUN9 = 1 + Return (OPTS) + } ElseIf (Arg2 == 9) { + /* + * Function index: 9 + * Specifying device readiness durations + */ + Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME, + FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME, + FW_VF_ENABLE_TIME }) + } + } + } + Return (Buffer() { 0x0 }) + } + + Method (_PRW, 0) + { + Return (Package() { 0x76, 4 }) + } +} + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + \_SB.PCI0.TDM0.SD3C = Arg1 + C2PM (Arg0, Arg1, Arg2, DCPM) +} + +Method (_PRW, 0) +{ + Return (Package() { 0x76, 4 }) +} + +/* + * Sub-Method of _L61 Hot-Plug event + * _L61 event handler should invoke this method to support HotPlug wake event from TBT RP. + */ +Method (HPEV, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && HPSX) { + If ((PDCX == 1) && (DLSC == 1)) { + /* Clear all status bits first. */ + PDCX = 1 + HPSX = 1 + + /* Perform proper notification to the OS. */ + Notify (^, 0) + } Else { + /* False event. Clear Hot-Plug Status, then exit. */ + HPSX = 1 + } + } +} + +/* + * Power Management routine for D3 + */ +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + If (STAT == 0x1) { + Return + } + + RPFE = 0 /* Set RTD3PFETDIS = 0 */ + RPER = 0 /* Set RTD3PERST = 0 */ + L23R = 1 /* Set L23r2dt = 1 */ + + /* + * Poll for L23r2dt == 0. Wait for transition to Detect. + */ + Local0 = 0 + Local1 = L23R + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23R + } + STAT = 0x1 +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + If (STAT == 0x0) { + Return + } + + If ((LNSE == 1) || (LSOE == 1)) { + If ((LASX == 1) && (LNRE == 0)) { + LNRE = 1 + Sleep(1) + LNRE = 0 + } + } + + L23E = 1 /* Set L23er = 1 */ + + /* Poll until L23er == 0 */ + Local0 = 0 + Local1 = L23E + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23E + } + + STAT = 0 /* D3Cold */ + RPFE = 1 /* Set RTD3PFETDIS = 1 */ + RPER = 1 /* Set RTD3PERST = 1 */ +} + +Method (_PS0, 0, Serialized) +{ + HPEV () /* Check and handle Hot Plug SCI status. */ + If (HPEX == 1) { + HPEX = 0 /* Disable Hot Plug SCI */ + } + HPME () /* Check and handle PME SCI status */ + If (PMEX == 1) { + PMEX = 0 /* Disable Power Management SCI */ + } +} + +Method (_PS3, 0, Serialized) +{ + /* Check it is hotplug SCI or not, then clear PDC accordingly */ + If (PDCX == 1) { + If (DLSC == 0) { + /* Clear PDC since it is not a hotplug. */ + PDCX = 1 + } + } + + If (HPEX == 0) { + HPEX = 1 /* Enable Hot Plug SCI. */ + HPEV () /* Check and handle Hot Plug SCI status. */ + } + If (PMEX == 0) { + PMEX = 1 /* Enable Power Management SCI. */ + HPME () /* Check and handle PME SCI status. */ + } +} + +Method (_S0W, 0x0, NotSerialized) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT +} + +Method (_PR0) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) +#else + Return (Package() { \_SB.PCI0.TBT0 }) +#endif // D3COLD_SUPPORT +} + +Method (_PR3) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) +#else + Return (Package() { \_SB.PCI0.TBT0 }) +#endif // D3COLD_SUPPORT +} + +/* + * PCI_EXP_STS Handler for PCIE Root Port + */ +Method (HPME, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && (PMSX == 1)) { /* if port exists and PME SCI Status set */ + /* + * Notify child device; this will cause its driver to clear PME_Status from + * device. + */ + Notify (PXSX, 0x2) + PMSX = 1 /* clear rootport's PME SCI status */ + /* + * Consume one pending PME notification to prevent it from blocking the queue. + */ + PSPX = 1 + Return (0x01) + } + Return (0x00) +} diff --git a/src/soc/intel/novalake/acpi/tcss_xhci.asl b/src/soc/intel/novalake/acpi/tcss_xhci.asl new file mode 100644 index 00000000000..006ba69c212 --- /dev/null +++ b/src/soc/intel/novalake/acpi/tcss_xhci.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100) +Field (XPRT, ByteAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x74), /* 0x74, XHCI CFG Power Control And Status */ + D0D3, 2, /* 0x74 BIT[1:0] */ + , 6, + PMEE, 1, /* PME Enable */ + , 6, + PMES, 1, /* PME Status */ +} + +Method (_PS0, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 1) { + /* Clear PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 0 + } +} + +Method (_PS3, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 0) { + /* Set PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 1 + } +} + +Method (_S0W, 0x0, NotSerialized) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (0x4) +#else + Return (0x3) +#endif +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +#if CONFIG(D3COLD_SUPPORT) +Method (_PR0) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +Method (_PR3) +{ + Return (Package () { \_SB.PCI0.D3C }) +} +#endif + +/* + * XHCI controller _DSM method + */ +Method (_DSM, 4, serialized) +{ + Return (Buffer() { 0 }) +} + +/* + * _SXD and _SXW methods + */ +Method (_S3D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S3W, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4W, 0, NotSerialized) +{ + Return (3) +} + +/* + * Power resource for wake + */ +Method (_PRW, 0) +{ + Return (Package() { 0x65, 4 }) +} + +/* + * Device sleep wake + */ +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +/* + * xHCI Root Hub Device + */ +Device (RHUB) +{ + Name (_ADR, 0) + + /* High Speed Ports */ + Device (HS01) + { + Name (_ADR, 0x01) + } + + /* Super Speed Ports */ + Device (SS01) + { + Name (_ADR, 0x02) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 0 } + } + }) + } + } + + Device (SS02) + { + Name (_ADR, 0x03) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 1 } + } + }) + } + } + + Device (SS03) + { + Name (_ADR, 0x04) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 2 } + } + }) + } + } +} diff --git a/src/soc/intel/novalake/acpi/xhci.asl b/src/soc/intel/novalake/acpi/xhci.asl new file mode 100644 index 00000000000..cd3b9f22feb --- /dev/null +++ b/src/soc/intel/novalake/acpi/xhci.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + /* Disable Clock Gating */ + ^^PCRA (PID_XHCI, 0x0, ~(1 << 3)) + } + + Method (_PS3, 0, Serialized) + { + /* Enable Clock Gating */ + ^^PCRO (PID_XHCI, 0x0, 1 << 3) + } + + Device (RHUB) + { + Name (_ADR, 0) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + /* USB3 */ + Device (SS01) { Name (_ADR, 11) } + Device (SS02) { Name (_ADR, 12) } + } +} diff --git a/src/soc/intel/novalake/bootblock/bootblock.c b/src/soc/intel/novalake/bootblock/bootblock.c new file mode 100644 index 00000000000..4228afeeaab --- /dev/null +++ b/src/soc/intel/novalake/bootblock/bootblock.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_pcd_die_early_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + bootblock_pcd_die_init(); +} diff --git a/src/soc/intel/novalake/bootblock/pcd.c b/src/soc/intel/novalake/bootblock/pcd.c new file mode 100644 index 00000000000..e40f15b5d2f --- /dev/null +++ b/src/soc/intel/novalake/bootblock/pcd.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xA80 +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_TO_SHDW_PCIEN 0x1C + +/* DMI3DP registers */ +#define DMI3DP_DECODE_CTRL_IOC_MCHBAR_REG 0x7978 +#define DMI3BAR_IOC_MCHBAR_REG 0x7938 +#define DMI_DECODE_EN 0x1 + +static void pcd_die_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +static void pcd_die_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + lpc_enable_fixed_io_ranges(io_enables); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +static void pcd_die_early_ip_init(void) +{ + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ + p2sb_enable_bar(); + p2sb2_enable_bar(); + p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + + /* + * Enabling PCD PMC PWRM Base for accessing + * Global Reset Cause Register. + */ + pcd_die_config_pwrmbase(); + + /* Disable DMI Decode */ + clrbits32((void *)MCH_BASE_ADDRESS + DMI3DP_DECODE_CTRL_IOC_MCHBAR_REG, DMI_DECODE_EN); + /* Disable DMI RCRB */ + clrbits32((void *)MCH_BASE_ADDRESS + DMI3BAR_IOC_MCHBAR_REG, DMI_DECODE_EN); +} + +static void pcd_die_early_sa_init(void) +{ + const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { NOHOMBASE, NOHOM_BASE_ADDRESS, NOHOM_SIZE, "NOHOMBASE" }, + { NOHOMLIMIT, NOHOM_LIMIT_ADDRESS, NOHOM_SIZE, "NOHOMLIMIT" }, + }; + + bootblock_systemagent_early_init(); + + /* Enable MCHBAR early, needed by IOC driver */ + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); +} + +void bootblock_pcd_die_early_init(void) +{ + /* + * Ensure performing SA related programming including MCHBAR prior to accessing + * IOC driver. + */ + pcd_die_early_sa_init(); + + pcd_die_early_ip_init(); + + fast_spi_cache_bios_region(); + pcd_die_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +static void pcd_die_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value == 0xffffffff) { + printk(BIOS_WARNING, "PCR_PSFX_TO_SHDW_BAR4 has not been programmed.\n"); + return; + } else { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF8 PMC space BAR4 */ + pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +void bootblock_pcd_die_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + pcd_die_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/novalake/bootblock/report_platform.c b/src/soc/intel/novalake/bootblock/report_platform.c new file mode 100644 index 00000000000..e16cb39f82d --- /dev/null +++ b/src/soc/intel/novalake/bootblock/report_platform.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_NOVALAKE, "Nova Lake" }, +}; + +struct device_name_map { + u16 id; + const char *name; +}; + +static struct device_name_map mch_table[] = { + { PCI_DID_INTEL_NVL_ID_1, "Nova Lake" }, + { PCI_DID_INTEL_NVL_ID_2, "Nova Lake" }, + { PCI_DID_INTEL_NVL_ID_3, "Nova Lake" }, + { PCI_DID_INTEL_NVL_ID_4, "Nova Lake" }, +}; + +static struct device_name_map pch_table[] = { + { PCI_DID_INTEL_NVL_ESPI_0, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_1, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_2, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_3, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_4, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_5, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_6, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_7, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_8, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_9, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_10, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_11, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_12, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_13, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_14, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_15, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_16, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_17, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_18, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_19, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_20, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_21, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_22, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_23, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_24, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_25, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_26, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_27, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_28, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_29, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_30, "Nova Lake SOC" }, + { PCI_DID_INTEL_NVL_ESPI_31, "Nova Lake SOC" }, +}; + +static struct device_name_map igd_table[] = { + { PCI_DID_INTEL_NVL_GT2_1, "Nova Lake GT2" }, + { PCI_DID_INTEL_NVL_GT2_2, "Nova Lake GT2" }, + { PCI_DID_INTEL_NVL_GT2_3, "Nova Lake GT2" }, + { PCI_DID_INTEL_NVL_GT2_4, "Nova Lake GT2" }, + { PCI_DID_INTEL_NVL_GT2_5, "Nova Lake GT2" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpuid_match(cpu_table[i].cpuid, cpu_id, CPUID_ALL_STEPPINGS_MASK)) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = !!(cpu_feature_flag & CPUID_AES); + txt = !!(cpu_feature_flag & CPUID_SMX); + vt = !!(cpu_feature_flag & CPUID_VMX); + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); + + car_report_cache_info(); + pmc_dump_soc_qdf_info(); +} + +static const char *find_device_name(const struct device_name_map *table, + size_t count, u16 id) +{ + for (size_t i = 0; i < count; i++) { + if (table[i].id == id) + return table[i].name; + } + return "Unknown"; +} + +static void report_dev_info(const char *prefix, pci_devfn_t dev, + const struct device_name_map *table, size_t count) +{ + uint16_t devid = get_dev_id(dev); + printk(BIOS_DEBUG, "%s: device id %04x (rev %02x) is %s\n", + prefix, devid, get_dev_revision(dev), + find_device_name(table, count, devid)); +} + +static void report_mch_info(void) +{ + report_dev_info("MCH", PCI_DEV_ROOT, mch_table, ARRAY_SIZE(mch_table)); +} + +static void report_pch_info(void) +{ + report_dev_info("PCH", PCI_DEV_ESPI, pch_table, ARRAY_SIZE(pch_table)); +} + +static void report_igd_info(void) +{ + report_dev_info("IGD", PCI_DEV_IGD, igd_table, ARRAY_SIZE(igd_table)); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/novalake/chip.c b/src/soc/intel/novalake/chip.c new file mode 100644 index 00000000000..6704a7167d4 --- /dev/null +++ b/src/soc/intel/novalake/chip.c @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + printk(BIOS_ERR, "Missing ACPI Name for USB port_type=0x%x\n", + dev->path.usb.port_type); + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "Missing ACPI Name for USB path_type=0x%x\n", + dev->path.type); + return NULL; + } + + switch (dev->path.pci.devfn) { + case PCI_DEVFN_ROOT: return "MCHC"; + case PCI_DEVFN_IGD: return "GFX0"; + case PCI_DEVFN_TCSS_XHCI: return "TXHC"; + case PCI_DEVFN_TCSS_XDCI: return "TXDC"; + case PCI_DEVFN_TCSS_DMA0: return "TDM0"; + case PCI_DEVFN_TBT0: return "TRP0"; + case PCI_DEVFN_TBT1: return "TRP1"; + case PCI_DEVFN_TBT2: return "TRP2"; + case PCI_DEVFN_THC0: return "THC0"; + case PCI_DEVFN_THC1: return "THC1"; + case PCI_DEVFN_NPU: return "NPU"; + case PCI_DEVFN_IPU: return "IPU0"; + case PCI_DEVFN_I3C1: return "I3C1"; + case PCI_DEVFN_I3C2: return "I3C2"; + case PCI_DEVFN_ISH: return "ISHB"; + case PCI_DEVFN_GSPI2: return "SPI2"; + case PCI_DEVFN_XHCI: return "XHCI"; + case PCI_DEVFN_SRAM: return "SRAM"; + case PCI_DEVFN_I2C0: return "I2C0"; + case PCI_DEVFN_I2C1: return "I2C1"; + case PCI_DEVFN_I2C2: return "I2C2"; + case PCI_DEVFN_I2C3: return "I2C3"; + case PCI_DEVFN_I2C4: return "I2C4"; + case PCI_DEVFN_I2C5: return "I2C5"; + case PCI_DEVFN_CSE: return "HECI"; + case PCI_DEVFN_PCIE1: return "RP01"; + case PCI_DEVFN_PCIE2: return "RP02"; + case PCI_DEVFN_PCIE3: return "RP03"; + case PCI_DEVFN_PCIE4: return "RP04"; + case PCI_DEVFN_PCIE5: return "RP05"; + case PCI_DEVFN_PCIE6: return "RP06"; + case PCI_DEVFN_PCIE7: return "RP07"; + case PCI_DEVFN_PCIE8: return "RP08"; + case PCI_DEVFN_PCIE9: return "RP09"; + case PCI_DEVFN_PCIE10: return "RP10"; + case PCI_DEVFN_PCIE11: return "RP11"; + case PCI_DEVFN_PCIE12: return "RP12"; + case PCI_DEVFN_PCIE13: return "RP13"; + case PCI_DEVFN_PCIE14: return "RP14"; + case PCI_DEVFN_PMC: return "PMC"; + case PCI_DEVFN_UART0: return "UAR0"; + case PCI_DEVFN_UART1: return "UAR1"; + case PCI_DEVFN_UART2: return "UAR2"; + case PCI_DEVFN_GSPI0: return "SPI0"; + case PCI_DEVFN_GSPI1: return "SPI1"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCI_DEVFN_ESPI: return "LPCB"; + case PCI_DEVFN_SPI: return "FSPI"; + case PCI_DEVFN_HDA: return "HDAS"; + case PCI_DEVFN_GBE: return "GLAN"; + } + printk(BIOS_ERR, "Missing ACPI Name for PCI: 00:%02x.%01x\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; +} +#endif + +#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) +/* SoC override API to identify if ISH Firmware existed inside CSE FPT */ +bool soc_is_ish_partition_enabled(void) +{ + struct device *ish = pcidev_path_on_root(PCI_DEVFN_ISH); + uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF; + + if (ish_pci_id == 0xFFFF) + return false; + + return true; +} +#endif + +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct soc_intel_novalake_config *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(value)); + else + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + +/* Enable tracehub in device tree */ +static void soc_enable_tracehub(void) +{ + struct device *dev; + + dev = pcidev_path_on_root(PCI_DEVFN_NPK); + if (dev) { + dev->enabled = 1; + printk(BIOS_DEBUG, "Tracehub is enabled.\n"); + } +} + +void soc_init_pre_device(void *chip_info) +{ + config_t *config = config_of_soc(); + if (config == NULL) { + printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); + return; + } + /* Validate TBT image authentication */ + config->tbt_authentication = p2sb2_sbi_read(PID_IOM, + IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) + soc_enable_tracehub(); + + /* Perform silicon specific init. */ + fsp_silicon_init(); + + /* Display FIRMWARE_VERSION_INFO_HOB */ + fsp_display_fvi_version_hob(); + + soc_fill_gpio_pm_configuration(); + + /* Swap enabled PCI ports in device tree if needed. */ + pcie_rp_update_devicetree(get_pcie_rp_table()); + + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); + + /* + * Earlier when coreboot used to send EOP at late as possible caused + * issue of delayed response from CSE since CSE was busy loading payload. + * To resolve the issue, EOP should be sent earlier than current sequence + * in the boot sequence at BS_DEV_INIT. + * + * Intel CSE team recommends to send EOP close to FW init (between FSP-S + * exit and current boot sequence) to reduce message response time from + * CSE hence moving sending EOP to earlier stage. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { + printk(BIOS_INFO, "Sending EOP early from SoC\n"); + cse_send_end_of_post(); + } +} + +static void cpu_fill_ssdt(const struct device *dev) +{ + if (!generate_pin_irq_map()) + printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); + + generate_cpu_entries(dev); +} + +/* + * This implements SoC-specific function used in common P2SB code to generate + * additional P2SB-related ACPI code. + */ +void soc_fill_p2sb_ssdt(const struct device *dev) +{ + /* + * Enable IOST for debug via P2SB at OS level. The associated IOST ASL file + * (i.e., src/soc/intel/common/acpi/iost.asl) is included in the SoC's + * southbridge.asl. The CBFS option "iost_enable" is used to expose this + * IOST interface to the OS. + * Use cbfstool command to add this option to the image. + */ + if (!get_uint_option("iost_enable", 0)) + return; + + printk(BIOS_INFO, "IOST is enabled\n"); + /* + * The following generates: + * Scope (\_SB.PCI0.IOST) + * { + * If (CondRefOf (IOSE)) + * { + * IOSE = 0x0F + * } + * } + */ + acpigen_write_scope("\\_SB.PCI0.IOST"); + acpigen_write_if_cond_ref_of("IOSE"); + acpigen_write_store_int_to_namestr(0xf, "IOSE"); + acpigen_write_if_end(); + acpigen_write_scope_end(); +} + +static void cpu_set_north_irqs(struct device *dev) +{ + irq_program_non_pch(); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, + .acpi_fill_ssdt = ssdt_set_above_4g_pci, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .enable_resources = cpu_set_north_irqs, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = cpu_fill_ssdt, +#endif +}; + +static void soc_enable(struct device *dev) +{ + struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops; + struct device_operations *soc_p2sb2_ops = (struct device_operations *)&p2sb2_ops; + + /* + * Set the operations if it is a special bus type or a hidden PCI + * device. + */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCI_DEVFN_PMC) + dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCI_DEVFN_P2SB) + dev->ops = soc_p2sb_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCI_DEVFN_P2SB2) + dev->ops = soc_p2sb2_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); +} + +static void soc_init_final_device(void *chip_info) +{ + efi_return_status_t reset_status = fsp_get_pch_reset_status(); + + if (reset_status == FSP_SUCCESS) + return; + + /* Handle any pending reset request from previously executed FSP APIs */ + fsp_handle_reset(reset_status); + + /* Control shouldn't return here */ + fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE, + "Failed to handle the FSP reset request with error"); +} + +struct chip_operations soc_intel_novalake_ops = { + .name = "Intel Nova Lake", + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, + .final = &soc_init_final_device, +}; diff --git a/src/soc/intel/novalake/chip.h b/src/soc/intel/novalake/chip.h new file mode 100644 index 00000000000..fc4556824be --- /dev/null +++ b/src/soc/intel/novalake/chip.h @@ -0,0 +1,626 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_CHIP_H_ +#define _SOC_NOVALAKE_CHIP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Define config parameters for In-Band ECC (IBECC). */ +#define MAX_IBECC_REGIONS 8 + +#define MAX_SAGV_POINTS 4 +#define MAX_HD_AUDIO_SDI_LINKS 2 + +#define NUM_THC 2 + +/* In-Band ECC Operation Mode */ +enum ibecc_mode { + IBECC_MODE_PER_REGION, + IBECC_MODE_NONE, + IBECC_MODE_ALL, +}; + +struct ibecc_config { + bool enable; + bool parity_en; + enum ibecc_mode mode; + bool region_enable[MAX_IBECC_REGIONS]; + uint16_t region_base[MAX_IBECC_REGIONS]; + uint16_t region_mask[MAX_IBECC_REGIONS]; +}; + +/* SaGv gears */ +enum soc_intel_novalake_sagv_gears { + GEAR_AUTO = 0, + GEAR_1 = 1, + GEAR_2 = 2, + GEAR_4 = 4, +}; + +/* Types of display ports */ +enum ddi_ports { + DDI_PORT_A, + DDI_PORT_B, + DDI_PORT_C, + DDI_PORT_1, + DDI_PORT_2, + DDI_PORT_3, + DDI_PORT_4, + DDI_PORT_COUNT, +}; + +enum ddi_port_flags { + DDI_ENABLE_DDC = BIT(0), /* Display Data Channel */ + DDI_ENABLE_HPD = BIT(1), /* Hot Plug Detect */ +}; + +/* + * The Max Pkg Cstate + * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, + * 254 - CPU Default , 255 - Auto. + */ +enum pkgcstate_limit { + LIMIT_C0_C1 = 0, + LIMIT_C2 = 1, + LIMIT_C3 = 2, + LIMIT_C6 = 3, + LIMIT_C7 = 4, + LIMIT_C7S = 5, + LIMIT_C8 = 6, + LIMIT_C9 = 7, + LIMIT_C10 = 8, + LIMIT_CPUDEFAULT = 254, + LIMIT_AUTO = 255, +}; + +/* Bit values for use in LpmStateEnableMask. */ +enum lpm_state_mask { + LPM_S0i2_0 = BIT(0), + LPM_S0i2_1 = BIT(1), + LPM_S0i2_2 = BIT(2), + LPM_S0i3_0 = BIT(3), + LPM_S0i3_1 = BIT(4), + LPM_S0i3_2 = BIT(5), + LPM_S0i3_3 = BIT(6), + LPM_S0i3_4 = BIT(7), + LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 + | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, +}; + +/* Platform Debug Option using HW interface + * + * 0: Disabled, + * 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix, + * 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix, + * 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional + * low power state, + * 7: User needs to configure Advanced Debug Settings manually. (only applicable for devices + * with BIOS Setup Menu option present. + */ +enum platform_hw_debug_option { + HW_DEBUG_DISABLE = 0, + HW_DEBUG_TRACEHUB_ACTIVE = BIT(1), + HW_DEBUG_TRACEHUB_READY = BIT(2), + HW_DEBUG_TRACEHUB_POWEROFF = BIT(2) | BIT(1), +}; + +/* + * As per definition from FSP header: + * - [0] for IA + * - [1] for GT + * - [2] for SA + * - [3] through [5] are reserved + */ +enum vr_domain { + VR_DOMAIN_IA, + VR_DOMAIN_GT, + VR_DOMAIN_SA, + VR_DOMAIN_ATOM, + NUM_VR_DOMAINS, +}; + +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16, + SLEW_IGNORE = 0xff, +}; + +enum tdc_mode { + TDC_IPL2, + TDC_IRMS, +}; + +struct soc_intel_novalake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + bool s0ix_enable; + /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ + bool tcss_d3_cold_disable; + /* Enable DPTF support */ + bool dptf_enable; + + /* Deep SX enable for both AC and DC */ + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin + */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + /* In-Band ECC (IBECC) configuration */ + struct ibecc_config ibecc; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:Enabled + */ + enum { + SAGV_DISABLED, + SAGV_ENABLED, + } sagv; + + /* System Agent dynamic frequency work points that memory will be training + * at the enabled frequencies. Possible work points are: + * 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 + */ + enum { + SAGV_POINTS_0_1 = 0x03, + SAGV_POINTS_0_1_2 = 0x07, + SAGV_POINTS_0_1_2_3 = 0x0f, + } sagv_wp_bitmap; + + /* Rank Margin Tool. true:Enable, false:Disable */ + bool rmt; + + /* USB related */ + struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX]; + struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX]; + /* true: this USB2 port is for integrated camera */ + uint8_t usb2_camera_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX]; + + uint8_t usb2_port_reset_msg_en[CONFIG_SOC_INTEL_USB2_DEV_MAX]; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + /* Program OC pins for TCSS */ + struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; + uint8_t tbt_pcie_port_disable[4]; + uint8_t tcss_cap_policy[4]; + /* Validate TBT firmware authenticated and loaded into IMR */ + bool tbt_authentication; + + /* Audio related */ + bool pch_hda_audio_link_hda_enable; + bool pch_hda_dsp_enable; + bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS]; + + /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ + enum { + HDA_TMODE_2T = 0, + HDA_TMODE_4T = 2, + HDA_TMODE_8T = 3, + HDA_TMODE_16T = 4, + } pch_hda_idisp_link_tmode; + + /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ + enum { + HDA_LINKFREQ_48MHZ = 3, + HDA_LINKFREQ_96MHZ = 4, + } pch_hda_idisp_link_frequency; + + /* iDisp-Link Interface 0: Disabled, 1: HD-Audio, 2: SoundWire. */ + enum { + IDISP_LINK_DISABLED, + IDISP_LINK_HDA, + IDISP_LINK_SNDW, + } pch_hda_idisp_link_interface; + + struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS]; + uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; + + /* Gfx related */ + enum { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, + IGD_SM_160MB = 0x05, + IGD_SM_4MB = 0xF0, + IGD_SM_8MB = 0xF1, + IGD_SM_12MB = 0xF2, + IGD_SM_16MB = 0xF3, + IGD_SM_20MB = 0xF4, + IGD_SM_24MB = 0xF5, + IGD_SM_28MB = 0xF6, + IGD_SM_36MB = 0xF8, + IGD_SM_40MB = 0xF9, + IGD_SM_44MB = 0xFA, + IGD_SM_48MB = 0xFB, + IGD_SM_52MB = 0xFC, + IGD_SM_56MB = 0xFD, + IGD_SM_60MB = 0xFE, + } igd_dvmt50_pre_alloc; + + bool skip_ext_gfx_scan; + + /* Enable/Disable EIST. true:Enabled, false:Disabled */ + bool eist_enable; + + /* + * When enabled, this feature makes the SoC throttle when the power + * consumption exceeds the I_TRIP threshold. + * + * FSPs sets a by default I_TRIP threshold adapted to the current SoC + * and assuming a Voltage Regulator error accuracy of 6.5%. + */ + bool enable_fast_vmode[NUM_VR_DOMAINS]; + + /* + * Current Excursion Protection needs to be set for each VR domain + * in order to be able to enable fast Vmode. + */ + bool cep_enable[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 1. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 2. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 3. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS]; + + /* + * Thermal Design Current (TDC) mode for each Voltage Regulator (VR) domain. + * + * The mode indicates the method used for managing thermal constraints and power + * consumption based on current measurement techniques. + * + * Possible values: + * - 0: iPL2 + * - 1: Irms + */ + uint8_t tdc_mode[NUM_VR_DOMAINS]; + + /* + * Time Window for Thermal Design Current (TDC) for each Voltage Regulator (VR) + * domain. + * + * This array specifies the time window for TDC measurement for each VR + * domain. The TDC time window determines the duration over which the current is + * averaged. + * + * Units are milliseconds. + */ + uint32_t tdc_time_window_ms[NUM_VR_DOMAINS]; + + /* + * Power State Current Thresholds for VR Domains. + * + * These arrays define the current thresholds for different power states (PS1, + * PS2, PS3) for each Voltage Regulator (VR) domain. + * + * Each value is defined in 1/4 A increments. For example, a value of 400 + * corresponds to 100A. The valid range is 0-512 (0-128A). A value of 0 + * indicates AUTO (use default). + */ + uint16_t ps1_threshold[NUM_VR_DOMAINS]; + uint16_t ps2_threshold[NUM_VR_DOMAINS]; + uint16_t ps3_threshold[NUM_VR_DOMAINS]; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + bool heci_enable; + + /* Enable C6 DRAM */ + bool enable_c6dram; + uint8_t PmTimerDisabled; + + /* SATA related */ + uint8_t SataEnable; + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[8]; + + /* SataPortsDmVal is the DITO multiplier. Default is 15. */ + uint8_t SataPortsDmVal[8]; + /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ + uint16_t SataPortsDitoVal[8]; + + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t serial_io_i3c_mode[CONFIG_SOC_INTEL_I3C_DEV_MAX]; + uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + + /* + * SerialIO DMA/PIO mode: + * 0: Disable (PIO) + * 1: Enable (DMA) + */ + uint8_t serial_io_uart_dma_enable[CONFIG_SOC_INTEL_UART_DEV_MAX]; + + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* CNVi WiFi Core Enable/Disable */ + bool cnvi_wifi_core; + + /* CNVi BT Core Enable/Disable */ + bool cnvi_bt_core; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + bool cnvi_bt_audio_offload; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = BIT(0), + DEBUG_INTERFACE_UART_8250IO = BIT(1), + DEBUG_INTERFACE_USB3 = BIT(3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = BIT(4), + DEBUG_INTERFACE_TRACEHUB = BIT(5), + } debug_interface_flag; + + /* + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). + */ + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; + + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports on NVL. + * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. + * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines + * on the motherboard. + */ + uint16_t tcss_aux_ori; + + /* Connect Topology Command timeout value */ + uint16_t itbt_connect_topology_timeout_in_ms; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t ddi_port_A_config; + uint8_t ddi_port_B_config; + + /* Enable(1)/Disable(0) HPD/DDC */ + uint8_t ddi_ports_config[DDI_PORT_COUNT]; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * + * Only override CPU flex ratio if don't want to boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + + /* + * Enable(true)/Disable(false) CPU Replacement check. + * Default false. Setting this to true to check CPU replacement. + */ + bool cpu_replacement_check; + + /* ISA Serial Base selection. */ + enum { + ISA_SERIAL_BASE_ADDR_3F8, + ISA_SERIAL_BASE_ADDR_2F8, + } isa_serial_uart_base; + + /* + * Enable or Disable C1 C-state Auto Demotion & un-demotion + * The algorithm looks at the behavior of the wake up tracker, how + * often it is waking up, and based on that it demote the c-state. + * Default false. Set this to true in order to disable C1-state auto + * demotion. + * NOTE: Un-Demotion from Demoted C1 needs to be disabled when + * C1 C-state Auto Demotion is disabled. + */ + bool disable_c1_state_auto_demotion; + + /* + * Enable or Disable Package C-state Demotion. + * Default is set to false. + * Set this to true in order to disable Package C-state demotion. + * NOTE: Un-Demotion from demoted Package C-state needs to be disabled + * when auto demotion is disabled. + */ + bool disable_package_c_state_demotion; + + /* Enable PCH to CPU energy report feature. */ + bool pch_pm_energy_report_enable; + + /* Energy-Performance Preference (HWP feature) */ + bool enable_energy_perf_pref; + uint8_t energy_perf_pref_value; + + bool disable_vmx; + + /* + * SAGV Frequency per point in Mhz. 0 is Auto, otherwise holds the + * frequency value expressed as an integer. For example: 1867 + */ + uint16_t sagv_freq_mhz[MAX_SAGV_POINTS]; + + /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */ + uint8_t sagv_gear[MAX_SAGV_POINTS]; + + /* + * Enable or Disable Reduced BasicMemoryTest size. + * Default is set to false. + * Set this to true in order to reduce BasicMemoryTest size + */ + bool lower_basic_mem_test_size; + + /* Platform Power Pmax in Watts. Zero means automatic. */ + uint16_t psys_pmax_watts; + + /* Platform Power Limit 2 in Watts. */ + uint16_t psys_pl2_watts; + + /* Enable or Disable Acoustic Noise Mitigation feature */ + bool enable_acoustic_noise_mitigation; + /* Disable Fast Slew Rate for Deep Package C States for VR domains */ + bool disable_fast_pkgc_ramp[NUM_VR_DOMAINS]; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * as per `enum slew_rate` data type. + */ + uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + /* P-cores Hysteresis time window ranges from 1 to 50 ms. */ + uint8_t pcore_hysteresis_window_ms; + /* E-cores Hysteresis time window ranges from 1 to 50 ms. */ + uint8_t ecore_hysteresis_window_ms; + + uint16_t max_dram_speed_mts; + + /* + * Touch Host Controller Mode + * Switch between Intel THC protocol and Industry standard HID protocols. + * 0x0:Thc, 0x1:HID over SPI, 0x2:HID over I2C + */ + uint8_t thc_mode[NUM_THC]; + + /* + * Touch Host Controller Wake On Touch + * Based on this setting vGPIO for given THC will be in native mode, and additional _CRS + * for wake will be exposed in ACPI + */ + bool thc_wake_on_touch[NUM_THC]; + + /* Disable the progress bar during MRC training operations. */ + bool disable_progress_bar; + + /* USB overcurrent pin mapping */ + uint8_t pch_usb_oc_enable; +}; + +typedef struct soc_intel_novalake_config config_t; + +#endif /* _SOC_NOVALAKE_CHIP_H_ */ diff --git a/src/soc/intel/novalake/chipset.cb b/src/soc/intel/novalake/chipset.cb new file mode 100644 index 00000000000..1a0f3ed38c9 --- /dev/null +++ b/src/soc/intel/novalake/chipset.cb @@ -0,0 +1,149 @@ +chip soc/intel/novalake + + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu on end + device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end + device pci 06.0 alias pcie_rp9 off ops pcie_rp_ops end + device pci 06.1 alias pcie_rp10 off ops pcie_rp_ops end + device pci 06.2 alias pcie_rp11 off ops pcie_rp_ops end + device pci 06.3 alias pcie_rp12 off ops pcie_rp_ops end + device pci 06.4 alias pcie_rp13 off ops pcie_rp_ops end + device pci 06.5 alias pcie_rp14 off ops pcie_rp_ops end + + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 2 on end + end + end + device pci 08.0 alias thc1 off end + device pci 0a.0 alias crashlog on end + device pci 0b.0 alias npu off end + device pci 0c.0 alias iaa on end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port2 off end + end + end + end + end + device pci 0d.1 alias tcss_xdci off ops usb_xdci_ops end + device pci 0d.2 alias tcss_dma0 off end + device pci 0e.0 alias vmd off end + + device pci 10.0 alias thc0 off end + device pci 11.0 alias i3c1 off end + device pci 11.2 alias i3c2 off end + device pci 12.0 alias ieh1 off end + device pci 12.1 alias p2sb2 hidden end + device pci 12.6 alias gspi2 off ops spi_dev_ops end + device pci 13.0 alias osse_heci_1 off end + device pci 13.1 alias osse_heci_2 off end + device pci 13.2 alias osse_heci_3 off end + device pci 14.0 alias xhci on ops usb_xhci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + end + end + end + device pci 14.1 alias usb_otg off ops usb_xdci_ops end + device pci 14.2 alias pmc_shared_sram on end + device pci 14.3 alias cnvi_wifi on ops cnvi_wifi_ops end + device pci 14.5 alias ieh off end + device pci 14.7 alias cnvi_bluetooth on end + device pci 15.0 alias i2c0 off ops i2c_dev_ops end + device pci 15.1 alias i2c1 off ops i2c_dev_ops end + device pci 15.2 alias i2c2 off ops i2c_dev_ops end + device pci 15.3 alias i2c3 off ops i2c_dev_ops end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias ufs off end + device pci 18.0 alias ese_heci1 off end + device pci 18.1 alias ese_heci2 off end + device pci 18.2 alias ese_eheci3 off end + device pci 19.0 alias i2c4 off ops i2c_dev_ops end + device pci 19.1 alias i2c5 off ops i2c_dev_ops end + device pci 19.2 alias uart2 off ops uart_ops end + device pci 1a.0 alias ish off end + device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end + device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end + device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end + device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end + device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end + device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end + device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end + device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end + device pci 1d.0 alias tsn_gbe1 off end + device pci 1d.1 alias tsn_gbe2 off end + device pci 1e.0 alias uart0 off ops uart_ops end + device pci 1e.1 alias uart1 off ops uart_ops end + device pci 1e.2 alias gspi0 off ops spi_dev_ops end + device pci 1e.3 alias gspi1 off ops spi_dev_ops end + device pci 1f.0 alias soc_espi on end + device pci 1f.1 alias p2sb hidden end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off ops hda_ops end + device pci 1f.4 alias smbus off ops smbus_ops end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias npk off end + end +end diff --git a/src/soc/intel/novalake/cpu.c b/src/soc/intel/novalake/cpu.c new file mode 100644 index 00000000000..2524ed5a38d --- /dev/null +++ b/src/soc/intel/novalake/cpu.c @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +bool cpu_soc_is_in_untrusted_mode(void) +{ + msr_t msr; + + msr = rdmsr(MSR_BIOS_DONE); + return !!(msr.lo & ENABLE_IA_UNTRUSTED); +} + +void cpu_soc_bios_done(void) +{ + msr_t msr; + + msr = rdmsr(MSR_BIOS_DONE); + msr.lo |= ENABLE_IA_UNTRUSTED; + wrmsr(MSR_BIOS_DONE, msr); +} + +uint8_t get_supported_lpm_mask(void) +{ + const config_t *conf = config_of_soc(); + if (!conf->s0ix_enable) + return 0; + + return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2; +} + +static void soc_fsp_load(void) +{ + fsps_load(); +} + +static void configure_misc(void) +{ + msr_t msr; + + const struct soc_intel_novalake_config *conf = config_of_soc(); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + msr.lo |= TM1_TM2_EMTTM_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = CRITICAL_TEMP_INTERRUPT_ENABLE; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT and Power Performance Platform Override */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= ENABLE_BIDIR_PROCHOT; + msr.lo |= VR_THERM_ALERT_DISABLE_LOCK; + msr.lo |= PWR_PERF_PLATFORM_OVR; + wrmsr(MSR_POWER_CTL, msr); +} + +enum core_type get_soc_cpu_type(void) +{ + if (cpu_is_hybrid_supported()) + return cpu_get_cpu_type(); + + return CPUID_CORE_TYPE_INTEL_CORE; +} + +bool soc_is_nominal_freq_supported(void) +{ + return true; +} + +static void enable_x2apic(void) +{ + if (!CONFIG(X2APIC_LATE_WORKAROUND)) + return; + + enable_lapic_mode(true); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(struct device *cpu) +{ + /* Clear out pending MCEs */ + mca_configure(); + + enable_x2apic(); + + enable_lapic_tpr(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + enable_pm_timer_emulation(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + const struct soc_intel_novalake_config *conf = config_of_soc(); + /* Set energy-performance preference */ + if (conf != NULL && conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) + set_energy_perf_pref(conf->energy_perf_pref_value); + } + + /* Enable Turbo */ + enable_turbo(); + + /* Set core type in struct cpu_info */ + set_dev_core_type(); + + if (get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported()) + set_tme_core_activate(); + + if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) { + /* Disable 3-strike error */ + disable_signaling_three_strike_event(); + + set_aesni_lock(); + + /* Enable VMX */ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx); + + /* Feature control lock configure */ + set_feature_ctrl_lock(); + } +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void pre_mp_init(void) +{ + soc_fsp_load(); + + const struct soc_intel_novalake_config *conf = config_of_soc(); + if (conf == NULL) { + printk(BIOS_ERR, "Configuration could not be retrieved.\n"); + return; + } + if (conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) + enable_energy_perf_pref(); + else + printk(BIOS_WARNING, "Energy Performance Preference not supported!\n"); + } +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * 1. Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT + * to avoid shutdown hang due to lack of init on certain IP in FSP-S. + */ + global_smi_enable_no_pwrbtn(); +} + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); +} + +int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) +{ + if (!CONFIG(CHROMEOS)) + return 0; + /* + * Locked RO Descriptor Implications: + * + * - A locked descriptor signals the RO binary is fixed; the FIT will load the + * RO's microcode during system reset. + * - Attempts to load newer microcode from the RW CBFS will cause a boot-time + * delay (~60ms, core-dependent), as the microcode must be reloaded on BSP+APs. + * - The kernel can load microcode updates without impacting AP FW boot time. + * - Skipping RW CBFS microcode loading is low-risk when the RO is locked, + * prioritizing fast boot times. + */ + if (CONFIG(LOCK_MANAGEMENT_ENGINE) && current_patch_id) + return 1; + + return 0; +} + +/* Override SMBIOS type 4 processor serial numbers */ +const char *smbios_processor_serial_number(void) +{ + char *qdf = retrieve_soc_qdf_info_via_pmc_ipc(); + + if (qdf != NULL) + return qdf; + else + return ""; +} diff --git a/src/soc/intel/novalake/crashlog.c b/src/soc/intel/novalake/crashlog.c new file mode 100644 index 00000000000..471608f21a9 --- /dev/null +++ b/src/soc/intel/novalake/crashlog.c @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CONTROL_INTERFACE_OFFSET 0x5 +#define CRASHLOG_NODES_COUNT 0x1 +#define CRASHLOG_PUNIT_STORAGE_OFF_MASK BIT(24) +#define CRASHLOG_RE_ARM_STATUS_MASK BIT(25) +#define CRASHLOG_CONSUMED_BIOS_MASK BIT(27) +#define CRASHLOG_SET_CLEAR_TRIGGER_MASK BIT(30) +#define CRASHLOG_SET_CONSUMED_MASK BIT(18) +#define CRASHLOG_REARM_TRIGGER_MASK BIT(28) + +/* Global crashLog info */ +static bool m_pmc_crash_log_support; +static bool m_pmc_crash_log_present; +static bool m_cpu_crash_log_support; +static bool m_cpu_crash_log_present; +static u32 m_pmc_crash_log_size; +static u32 m_cpu_crash_log_size; +static u32 cpu_crash_version; +static pmc_ipc_discovery_buf_t discovery_buf; +static pmc_crashlog_desc_table_t descriptor_table; +static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; +static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; +static uintptr_t disc_tab_addr; + +static u64 get_disc_tab_header(void) +{ + return read64p(disc_tab_addr); +} + +/* Get the SRAM BAR. */ +static uintptr_t get_sram_bar(pci_devfn_t sram_devfn) +{ + const struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(sram_devfn); + if (!dev) { + printk(BIOS_ERR, "device: 0x%x not found!\n", sram_devfn); + return 0; + } + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "SOC SRAM device not found!\n"); + return 0; + } + + /* Return the base address of the resource */ + return res->base; +} + +static void configure_sram(const struct device *sram_dev, uintptr_t base_addr) +{ + pci_update_config16(sram_dev, PCI_COMMAND, ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY), 0); + + /* Program BAR 0 and enable command register memory space decoding */ + pci_write_config32(sram_dev, PCI_BASE_ADDRESS_0, base_addr); + pci_or_config16(sram_dev, PCI_COMMAND, PCI_COMMAND_MEMORY); +} + +void cl_get_pmc_sram_data(cl_node_t *head) +{ + uintptr_t pmc_sram_base = cl_get_cpu_tmp_bar(); + u32 pmc_crashLog_size = cl_get_pmc_record_size(); + cl_node_t *cl_cur = head; + + if (!pmc_crashLog_size) { + printk(BIOS_ERR, "No PMC crashlog records\n"); + return; + } + + if (!pmc_sram_base) { + printk(BIOS_ERR, "PMC SRAM base not valid\n"); + return; + } + + if (!cl_pmc_sram_has_mmio_access()) + return; + + printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size); + + /* Goto tail node */ + while (cl_cur && cl_cur->next) { + cl_cur = cl_cur->next; + } + + /* Process crashlog records */ + for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + uintptr_t sram_base = 0; + bool pmc_sram = true; + printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", + i, + descriptor_table.regions[i].bits.assign_tag, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size); + + if (!descriptor_table.regions[i].bits.size) + continue; + + /* + * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM + * and IOE SRAM. We don't need to parse this as we already define BDFs in + * soc/pci_devs.h for these SRAMs. Also we need to skip this region as it does not + * contain any crashlog data. + */ + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_META) { + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "Found metadata tag. PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + continue; + } else { + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) + sram_base = pmc_sram_base; + else + continue; + + cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size); + + if (!cl_node) { + printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i); + goto pmc_send_re_arm_after_reset; + } + + if (cl_copy_data_from_sram(sram_base, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + cl_node->data, + i, + pmc_sram)) { + cl_cur->next = cl_node; + cl_cur = cl_cur->next; + } else { + /* Coping data from sram failed */ + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + /* Free cl_node */ + free_cl_node(cl_node); + } + } + } + + update_new_pmc_crashlog_size(&pmc_crashLog_size); + +pmc_send_re_arm_after_reset: + /* Re-arm and clear only if crashlog is present and valid*/ + if (!pmc_crashLog_size) { + printk(BIOS_DEBUG, "No valid crashlog data found in PMC SRAM\n"); + return; + } else { + /* When bit 7 of discov cmd resp is set -> bit 2 of size field */ + cl_pmc_re_arm_after_reset(); + /* Clear the SSRAM region after copying the error log */ + cl_pmc_clear(); + } +} + +bool pmc_cl_discovery(void) +{ + uintptr_t bar_addr = 0, desc_table_addr = 0; + + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY, + PMC_IPC_CMD_SIZE_SHIFT); + printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d in %s\n", cmd_reg, __func__); + + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return false; + } + discovery_buf.conv_val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0]; + + if ((discovery_buf.conv_bits64.supported != 1) || + (discovery_buf.conv_bits64.discov_mechanism == 0) || + (discovery_buf.conv_bits64.crash_dis_sts == 1)) { + printk(BIOS_INFO, "PCH crashlog feature not supported.\n"); + m_pmc_crash_log_support = false; + m_pmc_crash_log_size = 0; + printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n", + discovery_buf.conv_bits64.supported, + discovery_buf.conv_bits64.discov_mechanism, + discovery_buf.conv_bits64.crash_dis_sts); + return false; + } + + printk(BIOS_INFO, "PMC crashlog feature is supported.\n"); + m_pmc_crash_log_support = true; + + /* Program BAR 0 and enable command register memory space decoding */ + bar_addr = get_sram_bar(PCI_DEVFN_SRAM); + if (bar_addr == 0) { + printk(BIOS_ERR, "PCH SRAM not available, crashlog feature can't be enabled.\n"); + return false; + } + + configure_sram(PCI_DEV_SRAM, bar_addr); + + desc_table_addr = bar_addr + discovery_buf.conv_bits64.desc_tabl_offset; + m_pmc_crash_log_size = pmc_cl_gen_descriptor_table(desc_table_addr, + &descriptor_table); + printk(BIOS_DEBUG, "PMC CrashLog size in discovery mode: 0x%X\n", + m_pmc_crash_log_size); + m_pmc_crash_log_present = m_pmc_crash_log_size > 0; + + return true; +} + +uintptr_t cl_get_cpu_bar_addr(void) +{ + uintptr_t base_addr = 0; + if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { + base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { + base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_1) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else { + printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d, discovery failure expected.\n", + cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); + } + + return base_addr; +} + +uintptr_t cl_get_cpu_tmp_bar(void) +{ + return get_sram_bar(PCI_DEVFN_SRAM); +} + +bool cl_pmc_sram_has_mmio_access(void) +{ + if (pci_read_config16(PCI_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "PMC SSRAM PCI device disabled. Can be enabled in device tree.\n"); + return false; + } + + return true; +} + +static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap) +{ + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY, + TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID); + if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) { + printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID); + return false; + } + + /* Walk through the entries until crashLog entry */ + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, TEL_DVSEV_ID); + int new_offset = 0; + while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) { + if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0 + || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) { + printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id); + return false; + } + new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset; + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY, + new_offset + TEL_DVSEC_PCIE_CAP_ID); + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, + new_offset + TEL_DVSEV_ID); + } + cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver; + + cl_devsc_cap->discovery_data.data = pci_read_config32(PCI_DEV_TELEMETRY, new_offset + + TEL_DVSEV_DISCOVERY_TABLE_OFFSET); + + return true; +} + +static u32 get_disc_table_offset(void) +{ + u32 offset = cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + + return offset; +} + +static bool is_crashlog_data_valid(u32 dw0) +{ + return (dw0 != 0x0 && dw0 != INVALID_CRASHLOG_RECORD); +} + +static bool cpu_cl_gen_discovery_table(void) +{ + uintptr_t bar_addr = cl_get_cpu_bar_addr(); + + if (!bar_addr) + return false; + + disc_tab_addr = bar_addr + get_disc_table_offset(); + memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); + cpu_cl_disc_tab.header.data = get_disc_tab_header(); + /* Check both 32 bit header data and status register for non-zero values */ + if ((!is_crashlog_data_valid(cpu_cl_disc_tab.header.data & 0xFFFFFFFF)) && + (!is_crashlog_data_valid((cpu_cl_disc_tab.header.data) >> 32))) + return false; + + u32 cur_offset = 0; + cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT; + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n", + cpu_cl_disc_tab.header.fields.count); + for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { + cur_offset = 8 + 24 * i; + u32 cl_buffer_size = read32p(disc_tab_addr + cur_offset + 4); + /* Check for buffer size */ + if (!(is_crashlog_data_valid(cl_buffer_size))) + continue; + + u32 dw0 = read32p(disc_tab_addr + cur_offset); + if (dw0 & CRASHLOG_CONSUMED_BIOS_MASK) { + printk(BIOS_DEBUG, "cpu crashlog records already consumed." + "id: 0x%x dw0: 0x%x\n", i, dw0); + break; + } + + cpu_cl_disc_tab.buffers[i].data = read64p(disc_tab_addr + cur_offset); + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " + "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, + cpu_cl_disc_tab.buffers[i].fields.offset); + m_cpu_crash_log_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32); + } + + if (m_cpu_crash_log_size > 0) + m_cpu_crash_log_present = true; + else + m_cpu_crash_log_present = false; + + return true; +} + +bool cpu_cl_discovery(void) +{ + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); + + if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) { + printk(BIOS_ERR, "CPU crashlog capability not found.\n"); + m_cpu_crash_log_support = false; + return false; + } + + m_cpu_crash_log_support = true; + + if (!cpu_cl_gen_discovery_table()) { + printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); + m_cpu_crash_log_present = false; + return false; + } + + return true; +} + +void reset_discovery_buffers(void) +{ + memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t)); + memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t)); + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); +} + +int cl_get_total_data_size(void) +{ + printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, cpu-0x%x\n", + m_pmc_crash_log_size, m_cpu_crash_log_size); + return m_pmc_crash_log_size + m_cpu_crash_log_size; +} + +int cpu_cl_clear_data(void) +{ + /* Clear all crashlog data and CRASHLOG_SET_CONSUMED = 1 -> sets CONSUMED_BIOS bit */ + setbits64p(cl_get_cpu_bar_addr() + CRASHLOG_WATCHER_CONTROL_OFFSET, + CRASHLOG_SET_CLEAR_TRIGGER_MASK | CRASHLOG_SET_CONSUMED_MASK); + + return 0; +} + +static bool wait_and_check(u32 bit_mask) +{ + u32 stall_cnt = 0; + + do { + cpu_cl_disc_tab.header.data = get_disc_tab_header(); + udelay(CPU_CRASHLOG_WAIT_STALL); + stall_cnt++; + } while (((cpu_cl_disc_tab.header.data & bit_mask) == 0) && + ((stall_cnt * CPU_CRASHLOG_WAIT_STALL) < CPU_CRASHLOG_WAIT_TIMEOUT)); + + return (cpu_cl_disc_tab.header.data & bit_mask); +} + +void cpu_cl_rearm(void) +{ + setbits64p(cl_get_cpu_bar_addr() + CRASHLOG_WATCHER_CONTROL_OFFSET, + CRASHLOG_REARM_TRIGGER_MASK); + + if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK)) + printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n"); + else + printk(BIOS_DEBUG, "CPU crashlog re_arm asserted\n"); +} + +void cpu_cl_cleanup(void) +{ + /* + * Crashlog storage and power management in PTL is changed to a unified + * and persistent model,removing the need for manual SRAM power-down + * commands after crashlog extraction. + */ + /* Does nothing. */ +} + +pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void) +{ + return discovery_buf; +} + +pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void) +{ + return descriptor_table; +} + +int cl_get_pmc_record_size(void) +{ + return m_pmc_crash_log_size; +} + +int cl_get_cpu_record_size(void) +{ + return m_cpu_crash_log_size; +} + +bool cl_cpu_data_present(void) +{ + return m_cpu_crash_log_present; +} + +bool cl_pmc_data_present(void) +{ + return m_pmc_crash_log_present; +} + +bool cpu_crashlog_support(void) +{ + return m_cpu_crash_log_support; +} + +bool pmc_crashlog_support(void) +{ + return m_pmc_crash_log_support; +} + +void update_new_pmc_crashlog_size(u32 *pmc_crash_size) +{ + m_pmc_crash_log_size = *pmc_crash_size; +} + +cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void) +{ + return cpu_cl_disc_tab; +} + +void update_new_cpu_crashlog_size(u32 *cpu_crash_size) +{ + m_cpu_crash_log_size = *cpu_crash_size; +} diff --git a/src/soc/intel/novalake/cse_telemetry.c b/src/soc/intel/novalake/cse_telemetry.c new file mode 100644 index 00000000000..c24810556f6 --- /dev/null +++ b/src/soc/intel/novalake/cse_telemetry.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + + +/* TODO: b/510835894 - Consolidate cse_telemetry.c with PTL/ADL/MTL common timestamps. + * Move shared CSE timestamps to a common cse_telemetry.c with a weak override for + * SoC-specific telemetry data. */ + +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) +{ + s64 start_stamp; + + if (!ts) { + printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__); + return; + } + + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + timestamp_add(TS_DMU_LOAD_END, + start_stamp + ts[PERF_DATA_ESE_LOAD_DMU_COMPLETED]); + timestamp_add(TS_AUNIT_LOAD_END, + start_stamp + ts[PERF_DATA_ESE_LOAD_AUNIT_COMPLETED]); +} diff --git a/src/soc/intel/novalake/fsp_params.c b/src/soc/intel/novalake/fsp_params.c new file mode 100644 index 00000000000..41cfd8ba229 --- /dev/null +++ b/src/soc/intel/novalake/fsp_params.c @@ -0,0 +1,755 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_ONBOARD_PCIE_DEVICES 256 + +/* THC assignment definition */ +enum { + THC_NONE, + THC_0, + THC_1 +}; + +/* LPSS UART Power Gating mode */ +enum { + LPSS_UART_PG_DISABLED, + LPSS_UART_PG_ENABLED, + LPSS_UART_PG_AUTO +}; + +static const pci_devfn_t i2c_dev[] = { + PCI_DEVFN_I2C0, + PCI_DEVFN_I2C1, + PCI_DEVFN_I2C2, + PCI_DEVFN_I2C3, + PCI_DEVFN_I2C4, + PCI_DEVFN_I2C5, +}; + +static const pci_devfn_t i3c_dev[] = { + PCI_DEVFN_I3C1, + PCI_DEVFN_I3C2, +}; + +static const pci_devfn_t gspi_dev[] = { + PCI_DEVFN_GSPI0, + PCI_DEVFN_GSPI1 +}; + +static const pci_devfn_t uart_dev[] = { + PCI_DEVFN_UART0, + PCI_DEVFN_UART1, + PCI_DEVFN_UART2 +}; + +__weak void mainboard_update_soc_chip_config(struct soc_intel_novalake_config *config) +{ + /* Override settings per board. */ +} + +static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = PCI_DEV_SLOT_IGD, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_DPTF, + .fns = { + /* Dynamic Tuning Technology (DTT) device IRQ is not + programmable and is INT_A/PIRQ_A (IRQ 16) */ + FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_IPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, + but S0ix fails when not set to 16 (b/193434192) */ + FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCI_DEV_SLOT_TBT, + .fns = { + ANY_PIRQ(PCI_DEVFN_TBT0), + ANY_PIRQ(PCI_DEVFN_TBT1), + ANY_PIRQ(PCI_DEVFN_TBT2), + }, + }, + { + .slot = PCI_DEV_SLOT_THC1, + .fns = { + ANY_PIRQ(PCI_DEVFN_THC1), + }, + }, + { + .slot = PCI_DEV_SLOT_NPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPU, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_TCSS, + .fns = { + ANY_PIRQ(PCI_DEVFN_TCSS_XHCI), + }, + }, + { + .slot = PCI_DEV_SLOT_THC0, + .fns = { + ANY_PIRQ(PCI_DEVFN_THC0), + }, + }, + { + .slot = PCI_DEV_SLOT_ISH, + .fns = { + DIRECT_IRQ(PCI_DEVFN_ISH), + }, + }, + { + .slot = PCI_DEV_SLOT_XHCI, + .fns = { + ANY_PIRQ(PCI_DEVFN_XHCI), + DIRECT_IRQ(PCI_DEVFN_USBOTG), + ANY_PIRQ(PCI_DEVFN_CNVI_WIFI), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO0, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C0), + DIRECT_IRQ(PCI_DEVFN_I2C1), + DIRECT_IRQ(PCI_DEVFN_I2C2), + DIRECT_IRQ(PCI_DEVFN_I2C3), + }, + }, + { + .slot = PCI_DEV_SLOT_CSE, + .fns = { + ANY_PIRQ(PCI_DEVFN_CSE), + ANY_PIRQ(PCI_DEVFN_CSE_2), + ANY_PIRQ(PCI_DEVFN_CSE_IDER), + ANY_PIRQ(PCI_DEVFN_CSE_KT), + ANY_PIRQ(PCI_DEVFN_CSE_3), + ANY_PIRQ(PCI_DEVFN_CSE_4), + }, + }, + { + .slot = PCI_DEV_SLOT_UFS, + .fns = { + ANY_PIRQ(PCI_DEVFN_UFS), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO1, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C4), + DIRECT_IRQ(PCI_DEVFN_I2C5), + DIRECT_IRQ(PCI_DEVFN_UART2), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_1, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO2, + .fns = { + /* UART0 shares an interrupt line with TSN0, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A), + /* UART1 shares an interrupt line with TSN1, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B), + DIRECT_IRQ(PCI_DEVFN_GSPI0), + DIRECT_IRQ(PCI_DEVFN_GSPI1), + }, + }, + { + .slot = PCI_DEV_SLOT_ESPI, + .fns = { + ANY_PIRQ(PCI_DEVFN_HDA), + ANY_PIRQ(PCI_DEVFN(PCI_DEV_SLOT_ESPI, 4)), + ANY_PIRQ(PCI_DEVFN_GBE), + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A), + }, + }, +}; + +static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + size_t i; + + for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + s_cfg->SerialIoI2cMode[i] = + is_devfn_enabled(i2c_dev[i]) ? config->serial_io_i2c_mode[i] : 0; + + for (i = 0; i < CONFIG_SOC_INTEL_I3C_DEV_MAX; i++) + s_cfg->SerialIoI3cMode[i] = + is_devfn_enabled(i3c_dev[i]) ? config->serial_io_i3c_mode[i] : 0; + + for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + s_cfg->SerialIoLpssSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; + s_cfg->SerialIoLpssSpiCsState[i] = config->serial_io_gspi_cs_state[i]; + s_cfg->SerialIoLpssSpiMode[i] = + is_devfn_enabled(gspi_dev[i]) ? config->serial_io_gspi_mode[i] : 0; + } + + for (i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) { + s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ? + config->serial_io_uart_mode[i] : 0; + s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ? + LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO; + s_cfg->SerialIoUartDmaEnable[i] = is_devfn_enabled(uart_dev[i]) ? + config->serial_io_uart_dma_enable[i] : 0; + } +} + +static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + if (!CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + return; + + s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); +} + +static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + const struct microcode *microcode; + size_t length; + + if (!CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) + return; + + /* Locate microcode and pass to FSP-S for 2nd microcode loading */ + microcode = intel_microcode_find(); + if (!microcode) + return; + + length = get_microcode_size(microcode); + if (!length) + return; + + /* Update CPU Microcode patch base address/size */ + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode; + s_cfg->MicrocodeRegionSize = (uint32_t)length; +} + +static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + size_t vbt_len; + + /* Load VBT before devicetree-specific config. */ + s_cfg->GraphicsConfigPtr = (uintptr_t)locate_vbt(&vbt_len); + s_cfg->VbtSize = vbt_len; + + /* Check if IGD is present and fill Graphics init param accordingly */ + s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); + s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + s_cfg->PavpEnable = CONFIG(PAVP); +} + +static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + /* D3Cold for TCSS */ + s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; + s_cfg->TcCstateLimit = 8; + s_cfg->UsbTcPortEn = 0; + + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) + if (config->tcss_ports[i].enable) + s_cfg->UsbTcPortEn |= BIT(i); +} + +static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + /* Chipset Lockdown */ + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + + s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; + s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; + s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; + s_cfg->RtcMemoryLock = lockdown_by_fsp; + s_cfg->SkipPamLock = !lockdown_by_fsp; + + /* coreboot will send EOP before loading payload */ + s_cfg->EndOfPostMessage = 0; /* EOP disable */ + + s_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); +} + +static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + size_t i; + + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { + s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; + s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; + + s_cfg->PortResetMessageEnable[i] = config->usb2_ports[i].type_c; + s_cfg->PortUsb20IntegratedCamera[i] = config->usb2_camera_ports[i]; + } + + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { + s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].enable) + s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + else + s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; + + } + + for (i = 0; i < MAX_TYPE_C_PORTS; i++) + if (config->tcss_ports[i].enable) + s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; +} + +static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG); +} + +static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); +} + +static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) +{ + const struct pci_irq_entry *entry = get_cached_pci_irqs(); + SI_PCH_DEVICE_INTERRUPT_CONFIG *config; + size_t pch_total = 0, cfg_count = 0; + + if (!entry) + return NULL; + + /* Count PCH devices */ + while (entry) { + if (is_pch_slot(entry->devfn)) + pch_total++; + entry = entry->next; + } + + /* Convert PCH device entries to FSP format */ + config = calloc(pch_total, sizeof(*config)); + entry = get_cached_pci_irqs(); + while (entry) { + if (!is_pch_slot(entry->devfn)) { + entry = entry->next; + continue; + } + + config[cfg_count].Device = PCI_SLOT(entry->devfn); + config[cfg_count].Function = PCI_FUNC(entry->devfn); + config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; + config[cfg_count].Irq = entry->irq; + cfg_count++; + + entry = entry->next; + } + + *out_count = cfg_count; + + return config; +} + +static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) + die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); + + size_t pch_count = 0; + const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); + + s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); + s_cfg->NumOfDevIntConfig = pch_count; + printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); +} + +static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid) +{ + if (!(dev && svid && ssid)) + return; + + *svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086); + *ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe); +} + +/* + * Programming SSID before FSP-S is important because SSID registers of a few PCIE + * devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence + * provide a custom SSID (same as DID by default) value via UPD. + */ +static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t ignore1:4; + uint64_t segment:16; + uint64_t ignore2:16; + }; + uint64_t data; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t ignore3; + }; + + static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES]; + const struct device *dev; + size_t i = 0; + + for (dev = all_devices; dev; dev = dev->next) { + if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI && + dev->upstream->secondary == 0)) + continue; + + if (dev->path.pci.devfn == PCI_DEVFN_ROOT) { + evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid); + } else { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn); + ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn); + evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid); + i++; + } + } + + s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; + s_cfg->SiNumberOfSsidTableEntry = i; + + /* Ensure FSP will program the registers */ + s_cfg->SiSkipSsidProgramming = 0; +} + +static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE); +} + +static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI); + s_cfg->CnviWifiCore = config->cnvi_wifi_core; + s_cfg->CnviBtCore = config->cnvi_bt_core; + s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; + + if (!s_cfg->CnviMode && s_cfg->CnviWifiCore) { + printk(BIOS_ERR, "CNVi WiFi is enabled without CNVi being enabled\n"); + s_cfg->CnviWifiCore = 0; + } + if (!s_cfg->CnviBtCore && s_cfg->CnviBtAudioOffload) { + printk(BIOS_ERR, "BT offload is enabled without CNVi BT being enabled\n"); + s_cfg->CnviBtAudioOffload = 0; + } + if (!s_cfg->CnviMode && s_cfg->CnviBtCore) { + printk(BIOS_ERR, "CNVi BT is enabled without CNVi being enabled\n"); + s_cfg->CnviBtCore = 0; + s_cfg->CnviBtAudioOffload = 0; + } + +} + +static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD); +} + +static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->PmcPdEnable = 1; +} + +static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + if (is_devfn_enabled(PCI_DEVFN_THC0)) { + s_cfg->ThcAssignment[0] = THC_0; + s_cfg->ThcMode[0] = config->thc_mode[0]; + s_cfg->ThcWakeOnTouch[0] = config->thc_wake_on_touch[0]; + } else + s_cfg->ThcAssignment[0] = THC_NONE; + + if (is_devfn_enabled(PCI_DEVFN_THC1)) { + s_cfg->ThcAssignment[1] = THC_1; + s_cfg->ThcMode[1] = config->thc_mode[1]; + s_cfg->ThcWakeOnTouch[1] = config->thc_wake_on_touch[1]; + } else + s_cfg->ThcAssignment[1] = THC_NONE; +} + +static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + s_cfg->Enable8254ClockGating = !use_8254; + s_cfg->Enable8254ClockGatingOnS3 = !use_8254; +} + +static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + s_cfg->EnableTcoTimer = 1; +} + +static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table()); + + for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (!(enable_mask & BIT(i))) + continue; + const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i]; + s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); + s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); + s_cfg->PcieRpHotPlug[i] = + !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); + s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; + configure_pch_rp_power_management(s_cfg, rp_cfg, i); + } + + s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); +} + +static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + /* Skip setting D0I3 bit for all HECI devices */ + s_cfg->DisableD0I3SettingForHeci = 1; + + /* Disable SSE from PCI config space */ + s_cfg->SseCommunication = 2; + + s_cfg->Hwp = 1; + s_cfg->Cx = 1; + /* Enable the energy efficient turbo mode */ + s_cfg->EnergyEfficientTurbo = 1; + s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); + /* Un-Demotion from Demoted C1 need to be disable when + C1 auto demotion is disabled. */ + s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion; + s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; + s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion; + s_cfg->PmcV1p05PhyExtFetControlEn = 1; + + /* Enable/Disable PCH to CPU energy report feature. */ + s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable; +} + +static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->NpuEnable = is_devfn_enabled(PCI_DEVFN_NPU); +} + +static void fill_fsps_audio_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + if (!is_devfn_enabled(PCI_DEVFN_HDA)) + return; + + /* Fill MIC privacy settings */ + s_cfg->PchHdaMicPrivacyHwModeSoundWire0 = 1; + s_cfg->PchHdaMicPrivacyHwModeSoundWire1 = 1; + s_cfg->PchHdaMicPrivacyHwModeSoundWire2 = 1; + s_cfg->PchHdaMicPrivacyHwModeSoundWire3 = 1; + s_cfg->PchHdaMicPrivacyHwModeSoundWire4 = 1; + s_cfg->PchHdaMicPrivacyHwModeDmic = 1; + s_cfg->PchHdaMicPrivacyMode = 1; +} + +static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA); +} + +static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + /* Setting FSP UPD (1,0) to enable controller 0 */ + s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS); + s_cfg->UfsEnable[1] = 0; +} + +static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg) +{ + /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) + && CONFIG(CONSOLE_SERIAL) + && CONFIG(FSP_ENABLE_SERIAL_DEBUG) && fsp_get_pcd_debug_log_level()) + s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + +} + +static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, const config_t *config) +{ + void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, const config_t *config) = { + fill_fsps_lpss_params, + fill_fsps_cpu_params, + fill_fsps_microcode_params, + fill_fsps_igd_params, + fill_fsps_tcss_params, + fill_fsps_chipset_lockdown_params, + fill_fsps_xhci_params, + fill_fsps_xdci_params, + fill_fsps_thermal_params, + fill_fsps_irq_params, + fill_fsps_pci_ssid_params, + fill_fsps_lan_params, + fill_fsps_cnvi_params, + fill_fsps_vmd_params, + fill_fsps_pmcpd_params, + fill_fsps_thc_params, + fill_fsps_8254_params, + fill_fsps_pm_timer_params, + fill_fsps_pcie_params, + fill_fsps_misc_power_params, + fill_fsps_npu_params, + fill_fsps_audio_params, + fill_fsps_iax_params, + fill_fsps_ufs_params, + }; + + for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) + fill_fsps_params[i](s_cfg, config); +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + config_t *config; + FSP_S_CONFIG *s_cfg = &supd->FspsConfig; + FSPS_ARCH2_UPD *s_arch_cfg = &supd->FspsArchUpd; + + config = config_of_soc(); + arch_silicon_init_params(s_arch_cfg); + /* Override settings per board if required. */ + mainboard_update_soc_chip_config(config); + soc_silicon_init_params(s_cfg, config); + mainboard_silicon_init_params(s_cfg); +} + +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + * This platform supports below MultiPhaseSIInit Phase(s): + * + * Phase | FSP return point | Purpose + * ----- + -------------------------------------+ ------------------------ + * 1 | After TCSS initialization completed | for TCSS specific init + */ +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: + /* TCSS specific initialization here */ + printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", + __FILE__, __func__); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } + + /* Allow CBFS preload transfers to complete before FSP-S locks SPI DMA. */ + struct soc_intel_common_config *config = chip_get_common_soc_structure(); + if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP) + cbfs_preload_wait_for_all(); + break; + default: + break; + } +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Handle FSP logo params */ +void soc_load_logo_by_fsp(FSPS_UPD *supd) +{ + efi_uintn_t logo, blt_size; + uint32_t logo_size; + struct soc_intel_common_config *config = chip_get_common_soc_structure(); + FSP_S_CONFIG *s_cfg = &supd->FspsConfig; + + /* + * Adjusts panel orientation for external display when the lid is closed. + * + * When the lid is closed (LidStatus == 0), indicating the onboard display is inactive, + * this function forces the panel orientation to normal. This ensures proper display + * on an external monitor, as rotated orientations are typically not suitable in + * such state. + */ + if (s_cfg->LidStatus == 0) + config->panel_orientation = LB_FB_ORIENTATION_NORMAL; + + fsp_load_and_convert_bmp_to_gop_blt(&logo, &logo_size, + &supd->FspsConfig.BltBufferAddress, + &blt_size, + &supd->FspsConfig.LogoPixelHeight, + &supd->FspsConfig.LogoPixelWidth, + config->panel_orientation); +} diff --git a/src/soc/intel/novalake/gpio.c b/src/soc/intel/novalake/gpio.c new file mode 100644 index 00000000000..d832291260e --- /dev/null +++ b/src/soc/intel/novalake/gpio.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, + { .logical = PAD_RESET(GLBRST), .chipset = 3U << 30 }, +}; + +/* + * Nova Lake adopts new pinctrl schema, where each GPIO community has its own + * pinctrl instance and a group is not required to be aligned with 32 boundary. + * SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES must be selected and + * the offset from its GPIO's community is used as the ACPI GPIO number directly. + * Therefore, the .acpi_pad_base field in 'pad_group' structure is not used for + * constructing APIC gpio number and INTEL_GPP() is used for all GPIO groups + * instead. Please see function gpio_acpi_pin() in + * src/soc/intel/common/block/gpio/gpio.c for more details. + */ +static const struct pad_group nvl_community0_groups[] = { + INTEL_GPP(GPP_D00, GPP_D00, GPP_I3C_CLK_LPBK), /* GPP_D */ + INTEL_GPP(GPP_D00, GPP_C00, GPP_C23), /* GPP_C */ +}; + +static const struct pad_group nvl_community1_groups[] = { + INTEL_GPP(GPP_F00, GPP_F00, GPP_GSPI0_CLK_LOOPBK), /* GPP_F */ + INTEL_GPP(GPP_F00, GPP_E00, GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK), /* GPP_E */ +}; + +static const struct pad_group nvl_community3_groups[] = { + INTEL_GPP(GPP_EPD_ON, GPP_EPD_ON, GPP_VDD2_PWRGD), /* GPP_CPUJTAG1 */ + INTEL_GPP(GPP_EPD_ON, GPP_JTAG_MBPB0, GPP_DDSP_HPDALV), /* GPP_CPUJTAG */ + INTEL_GPP(GPP_EPD_ON, GPP_H00, GPP_LPI3C3_CLK_LPBK), /* GPP_H */ + INTEL_GPP(GPP_EPD_ON, GPP_A00, GPP_SPI0_CLK_LOOPBK), /* GPP_A */ + INTEL_GPP(GPP_EPD_ON, GPP_VGPIO3_USB_OCB_RX_0, GPP_VGPIO3_EC_SCI1), /* GPP_VGPIO3 */ +}; + +static const struct pad_group nvl_community4_groups[] = { + INTEL_GPP(GPP_S00, GPP_S00, GPP_S07), /* GPP_S */ +}; + +static const struct pad_group nvl_community5_groups[] = { + INTEL_GPP(GPP_B00, GPP_B00, GPP_GSPI2_CLK_LPBK), /* GPP_B */ + INTEL_GPP(GPP_B00, GPP_V00, GPP_V17), /* GPP_V */ + INTEL_GPP(GPP_B00, GPP_VGPIO0, GPP_VGPIO47), /* GPP_VGPIO */ +}; + +static const struct pad_community nvl_communities[] = { + [COMM_0] = { /* GPP: D, C */ + .port = PID_GPIOCOM0, + .first_pad = COM0_GRP_PAD_START, + .last_pad = COM0_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_D_C", + .acpi_path = "\\_SB.PCI0.GPI0", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = nvl_community0_groups, + .num_groups = ARRAY_SIZE(nvl_community0_groups), + }, + [COMM_1] = { /* GPP: F, E */ + .port = PID_GPIOCOM1, + .first_pad = COM1_GRP_PAD_START, + .last_pad = COM1_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_F_E", + .acpi_path = "\\_SB.PCI0.GPI1", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = nvl_community1_groups, + .num_groups = ARRAY_SIZE(nvl_community1_groups), + }, + [COMM_3] = { /* GPP: CPUJTAG1, CPUJTAG, H, A, VGPIO3 */ + .port = PID_GPIOCOM3, + .first_pad = COM3_GRP_PAD_START, + .last_pad = COM3_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPUJTAG1_CPUJTAG_H_A_VGPIO3", + .acpi_path = "\\_SB.PCI0.GPI3", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = nvl_community3_groups, + .num_groups = ARRAY_SIZE(nvl_community3_groups), + }, + [COMM_4] = { /* GPP: S */ + .port = PID_GPIOCOM4, + .first_pad = COM4_GRP_PAD_START, + .last_pad = COM4_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_S", + .acpi_path = "\\_SB.PCI0.GPI4", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = nvl_community4_groups, + .num_groups = ARRAY_SIZE(nvl_community4_groups), + }, + [COMM_5] = { /* GPP: B, V, VGPIO */ + .port = PID_GPIOCOM5, + .first_pad = COM5_GRP_PAD_START, + .last_pad = COM5_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_B_V_VGPIO", + .acpi_path = "\\_SB.PCI0.GPI5", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = nvl_community5_groups, + .num_groups = ARRAY_SIZE(nvl_community5_groups), + }, +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(nvl_communities); + return nvl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_V, GPP_V }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_VGPIO3, GPP_VGPIO3 }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/novalake/include/soc/bootblock.h b/src/soc/intel/novalake/include/soc/bootblock.h new file mode 100644 index 00000000000..c6190c6685e --- /dev/null +++ b/src/soc/intel/novalake/include/soc/bootblock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_BOOTBLOCK_H_ +#define _SOC_NOVALAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_pcd_die_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pcd_die_init(void); +void report_platform_info(void); + +#endif /* _SOC_NOVALAKE_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/novalake/include/soc/cnvi.h b/src/soc/intel/novalake/include/soc/cnvi.h new file mode 100644 index 00000000000..2b78306c43f --- /dev/null +++ b/src/soc/intel/novalake/include/soc/cnvi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_CNVI_H_ +#define _SOC_NOVALAKE_CNVI_H_ + +#define CNVI_ABORT_PLDR 0x80 + +#endif /* _SOC_NOVALAKE_CNVI_H_ */ diff --git a/src/soc/intel/novalake/include/soc/cpu.h b/src/soc/intel/novalake/include/soc/cpu.h new file mode 100644 index 00000000000..cfe0d72544e --- /dev/null +++ b/src/soc/intel/novalake/include/soc/cpu.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_CPU_H_ +#define _SOC_NOVALAKE_CPU_H_ + +#include + +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Get a bitmask of supported LPM states */ +uint8_t get_supported_lpm_mask(void); + +#endif diff --git a/src/soc/intel/novalake/include/soc/crashlog.h b/src/soc/intel/novalake/include/soc/crashlog.h new file mode 100644 index 00000000000..fb22cbc18c9 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/crashlog.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_CRASHLOG_H_ +#define _SOC_NOVALAKE_CRASHLOG_H_ + +#include + +/* DVSEC capability Registers */ +#define TEL_DVSEC_OFFSET 0x100 +#define TEL_DVSEC_PCIE_CAP_ID 0x0 +#define TEL_DVSEV_ID 0x8 +#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC +#define TELEMETRY_EXTENDED_CAP_ID 0x23 +#define CRASHLOG_DVSEC_ID 0x04 +#define TEL_DVSEC_TBIR_BAR0 0 +#define TEL_DVSEC_TBIR_BAR1 1 +#define CRASHLOG_WATCHER_CONTROL_OFFSET 0x10 + +typedef union { + struct { + u32 reserved1 :27; + u32 set_storage_off :1; + u32 set_re_arm :1; + u32 reserved2 :1; + u32 set_clr :1; + u32 reserved3 :1; + } fields; + u32 data; +} __packed cl_punit_control_interface_t; + +#endif /* _SOC_NOVALAKE_CRASHLOG_H_ */ diff --git a/src/soc/intel/novalake/include/soc/dptf.h b/src/soc/intel/novalake/include/soc/dptf.h new file mode 100644 index 00000000000..6359da2f51f --- /dev/null +++ b/src/soc/intel/novalake/include/soc/dptf.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_DPTF_H_ +#define _SOC_NOVALAKE_DPTF_H_ + +/* + * Below is a list of unique ACPI Device IDs for thermal and DPTF + * (Dynamic Platform and Thermal Framework) + */ +/* DPTF ACPI Device ID */ +#define DPTF_DPTF_DEVICE "INTC10D4" +/* Generic ACPI Device ID for TSR0/1/2/3 and charger */ +#define DPTF_GEN_DEVICE "INTC10D5" +/* Fan ACPI Device ID */ +#define DPTF_FAN_DEVICE "INTC10D6" +/* TPCH ACPI Device ID */ +#define DPTF_TPCH_DEVICE "INTC10D7" +/* TPWR ACPI Device ID */ +#define DPTF_TPWR_DEVICE "INTC10D8" +/* BAT1 ACPI Device ID */ +#define DPTF_BAT1_DEVICE "INTC10D9" + +#endif diff --git a/src/soc/intel/novalake/include/soc/gpe.h b/src/soc/intel/novalake/include/soc/gpe.h new file mode 100644 index 00000000000..5a013aa6ba0 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/gpe.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_GPE_H_ +#define _SOC_NOVALAKE_GPE_H_ + +#include + +#endif /* _SOC_NOVALAKE_GPE_H_ */ diff --git a/src/soc/intel/novalake/include/soc/gpio.h b/src/soc/intel/novalake/include/soc/gpio.h new file mode 100644 index 00000000000..8bccf6b371d --- /dev/null +++ b/src/soc/intel/novalake/include/soc/gpio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_GPIO_H_ +#define _SOC_NOVALAKE_GPIO_H_ + +#include +#include + +#define CROS_GPIO_NAME "INTC10DC" +#define CROS_GPIO_DEVICE0_NAME "INTC10DC:00" +#define CROS_GPIO_DEVICE1_NAME "INTC10DC:01" +#define CROS_GPIO_DEVICE2_NAME "INTC10DC:02" +#define CROS_GPIO_DEVICE3_NAME "INTC10DC:03" +#define CROS_GPIO_DEVICE4_NAME "INTC10DC:04" + +#define ACPI_GPIO_CID "INTC105F" +#define ACPI_GPIO_HID CROS_GPIO_NAME + +#define GPP_COMM0_NAME "Community 0" +#define GPP_COMM1_NAME "Community 1" +#define GPP_COMM3_NAME "Community 3" +#define GPP_COMM4_NAME "Community 4" +#define GPP_COMM5_NAME "Community 5" + +/* Enable GPIO community power management configuration */ +#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \ + MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | \ + MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + +#endif /* _SOC_NOVALAKE_GPIO_H_ */ diff --git a/src/soc/intel/novalake/include/soc/gpio_defs.h b/src/soc/intel/novalake/include/soc/gpio_defs.h new file mode 100644 index 00000000000..8dbb0617260 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/gpio_defs.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_GPIO_DEFS_H_ +#define _SOC_NOVALAKE_GPIO_DEFS_H_ + +#include + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM0_GRP_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM1_GRP_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM3_GRP_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM4_GRP_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM5_GRP_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group D */ +#define GPP_D00_IRQ 0x18 +#define GPP_D01_IRQ 0x19 +#define GPP_D02_IRQ 0x1A +#define GPP_D03_IRQ 0x1B +#define GPP_D04_IRQ 0x1C +#define GPP_D05_IRQ 0x1D +#define GPP_D06_IRQ 0x1E +#define GPP_D07_IRQ 0x1F +#define GPP_D08_IRQ 0x20 +#define GPP_D09_IRQ 0x21 +#define GPP_D10_IRQ 0x22 +#define GPP_D11_IRQ 0x23 +#define GPP_D12_IRQ 0x24 +#define GPP_D13_IRQ 0x25 +#define GPP_D14_IRQ 0x26 +#define GPP_D15_IRQ 0x27 +#define GPP_D16_IRQ 0x28 +#define GPP_D17_IRQ 0x29 +#define GPP_D18_IRQ 0x2A +#define GPP_D19_IRQ 0x2B +#define GPP_D20_IRQ 0x2C +#define GPP_D21_IRQ 0x2D +#define GPP_D22_IRQ 0x2E +#define GPP_D23_IRQ 0x2F +#define GPP_D24_IRQ 0x30 +#define GPP_D25_IRQ 0x31 + +/* Group C */ +#define GPP_C00_IRQ 0x32 +#define GPP_C01_IRQ 0x33 +#define GPP_C02_IRQ 0x34 +#define GPP_C03_IRQ 0x35 +#define GPP_C04_IRQ 0x36 +#define GPP_C05_IRQ 0x37 +#define GPP_C06_IRQ 0x38 +#define GPP_C07_IRQ 0x39 +#define GPP_C08_IRQ 0x3A +#define GPP_C09_IRQ 0x3B +#define GPP_C10_IRQ 0x3C +#define GPP_C11_IRQ 0x3D +#define GPP_C12_IRQ 0x3E +#define GPP_C13_IRQ 0x3F +#define GPP_C14_IRQ 0x40 +#define GPP_C15_IRQ 0x41 +#define GPP_C16_IRQ 0x42 +#define GPP_C17_IRQ 0x43 +#define GPP_C18_IRQ 0x44 +#define GPP_C19_IRQ 0x45 +#define GPP_C20_IRQ 0x46 +#define GPP_C21_IRQ 0x47 +#define GPP_C22_IRQ 0x48 +#define GPP_C23_IRQ 0x49 + +/* Group F */ +#define GPP_F00_IRQ 0x4A +#define GPP_F01_IRQ 0x4B +#define GPP_F02_IRQ 0x4C +#define GPP_F03_IRQ 0x4D +#define GPP_F04_IRQ 0x4E +#define GPP_F05_IRQ 0x4F +#define GPP_F06_IRQ 0x50 +#define GPP_F07_IRQ 0x51 +#define GPP_F08_IRQ 0x52 +#define GPP_F09_IRQ 0x53 +#define GPP_F10_IRQ 0x54 +#define GPP_F11_IRQ 0x55 +#define GPP_F12_IRQ 0x56 +#define GPP_F13_IRQ 0x57 +#define GPP_F14_IRQ 0x58 +#define GPP_F15_IRQ 0x59 +#define GPP_F16_IRQ 0x5A +#define GPP_F17_IRQ 0x5B +#define GPP_F18_IRQ 0x5C +#define GPP_F19_IRQ 0x5D +#define GPP_F20_IRQ 0x5E +#define GPP_F21_IRQ 0x5F +#define GPP_F22_IRQ 0x60 +#define GPP_F23_IRQ 0x61 + +/* Group E */ +#define GPP_E00_IRQ 0x62 +#define GPP_E01_IRQ 0x63 +#define GPP_E02_IRQ 0x64 +#define GPP_E03_IRQ 0x65 +#define GPP_E04_IRQ 0x66 +#define GPP_E05_IRQ 0x67 +#define GPP_E06_IRQ 0x68 +#define GPP_E07_IRQ 0x69 +#define GPP_E08_IRQ 0x6A +#define GPP_E09_IRQ 0x6B +#define GPP_E10_IRQ 0x6C +#define GPP_E11_IRQ 0x6D +#define GPP_E12_IRQ 0x6E +#define GPP_E13_IRQ 0x6F +#define GPP_E14_IRQ 0x70 +#define GPP_E15_IRQ 0x71 +#define GPP_E16_IRQ 0x72 +#define GPP_E17_IRQ 0x73 +#define GPP_E18_IRQ 0x74 +#define GPP_E19_IRQ 0x75 +#define GPP_E20_IRQ 0x76 +#define GPP_E21_IRQ 0x77 +#define GPP_E22_IRQ 0x18 + +/* Group H */ +#define GPP_H00_IRQ 0x19 +#define GPP_H01_IRQ 0x1A +#define GPP_H02_IRQ 0x1B +#define GPP_H03_IRQ 0x1C +#define GPP_H04_IRQ 0x1D +#define GPP_H05_IRQ 0x1E +#define GPP_H06_IRQ 0x1F +#define GPP_H07_IRQ 0x20 +#define GPP_H08_IRQ 0x21 +#define GPP_H09_IRQ 0x22 +#define GPP_H10_IRQ 0x23 +#define GPP_H11_IRQ 0x24 +#define GPP_H12_IRQ 0x25 +#define GPP_H13_IRQ 0x26 +#define GPP_H14_IRQ 0x27 +#define GPP_H15_IRQ 0x28 +#define GPP_H16_IRQ 0x29 +#define GPP_H17_IRQ 0x2A +#define GPP_H18_IRQ 0x2B +#define GPP_H19_IRQ 0x2C +#define GPP_H20_IRQ 0x2D +#define GPP_H21_IRQ 0x2E +#define GPP_H22_IRQ 0x2F +#define GPP_H23_IRQ 0x30 +#define GPP_H24_IRQ 0x31 + +/* Group A */ +#define GPP_A00_IRQ 0x32 +#define GPP_A01_IRQ 0x33 +#define GPP_A02_IRQ 0x34 +#define GPP_A03_IRQ 0x35 +#define GPP_A04_IRQ 0x36 +#define GPP_A05_IRQ 0x37 +#define GPP_A06_IRQ 0x38 +#define GPP_A07_IRQ 0x39 +#define GPP_A08_IRQ 0x3A +#define GPP_A09_IRQ 0x3B +#define GPP_A10_IRQ 0x3C +#define GPP_A11_IRQ 0x3D +#define GPP_A12_IRQ 0x3E +#define GPP_A13_IRQ 0x3F +#define GPP_A14_IRQ 0x40 +#define GPP_A15_IRQ 0x41 +#define GPP_A16_IRQ 0x42 +#define GPP_A17_IRQ 0x43 + +/* Group VGPIO3 */ + +#define GPP_VGPIO3_TS0_IRQ 0x44 +#define GPP_VGPIO3_TS1_IRQ 0x45 +#define GPP_VGPIO3_THC0_IRQ 0x46 +#define GPP_VGPIO3_THC1_IRQ 0x47 +#define GPP_VGPIO3_THC2_IRQ 0x48 +#define GPP_VGPIO3_THC3_IRQ 0x49 +#define GPP_VGPIO3_ESPI_4_IRQ 0x4A +#define GPP_VGPIO3_ESPI_5_IRQ 0x4B +#define GPP_VGPIO3_ESPI_6_IRQ 0x4C +#define GPP_VGPIO3_ESPI_7_IRQ 0x4D +#define GPP_VGPIO3_EC_SCI1_IRQ 0x4E + +/* Group B */ +#define GPP_B00_IRQ 0x4F +#define GPP_B01_IRQ 0x50 +#define GPP_B02_IRQ 0x51 +#define GPP_B03_IRQ 0x52 +#define GPP_B04_IRQ 0x53 +#define GPP_B05_IRQ 0x54 +#define GPP_B06_IRQ 0x55 +#define GPP_B07_IRQ 0x56 +#define GPP_B08_IRQ 0x57 +#define GPP_B09_IRQ 0x58 +#define GPP_B10_IRQ 0x59 +#define GPP_B11_IRQ 0x5A +#define GPP_B12_IRQ 0x5B +#define GPP_B13_IRQ 0x5C +#define GPP_B14_IRQ 0x5D +#define GPP_B15_IRQ 0x5E +#define GPP_B16_IRQ 0x5F +#define GPP_B17_IRQ 0x60 +#define GPP_B18_IRQ 0x61 +#define GPP_B19_IRQ 0x62 +#define GPP_B20_IRQ 0x63 +#define GPP_B21_IRQ 0x64 +#define GPP_B22_IRQ 0x65 +#define GPP_B23_IRQ 0x66 +#define GPP_B24_IRQ 0x67 +#define GPP_B25_IRQ 0x68 + +/* Group V */ +#define GPP_V00_IRQ 0x69 +#define GPP_V01_IRQ 0x6A +#define GPP_V02_IRQ 0x6B +#define GPP_V03_IRQ 0x6C +#define GPP_V04_IRQ 0x6D +#define GPP_V05_IRQ 0x6E +#define GPP_V06_IRQ 0x6F +#define GPP_V07_IRQ 0x70 +#define GPP_V08_IRQ 0x71 +#define GPP_V09_IRQ 0x72 +#define GPP_V10_IRQ 0x73 +#define GPP_V11_IRQ 0x74 +#define GPP_V12_IRQ 0x75 +#define GPP_V13_IRQ 0x76 +#define GPP_V14_IRQ 0x77 +#define GPP_V15_IRQ 0x18 +#define GPP_V16_IRQ 0x19 +#define GPP_V17_IRQ 0x1A + +/* Group S */ +#define GPP_S00_IRQ 0x1B +#define GPP_S01_IRQ 0x1C +#define GPP_S02_IRQ 0x1D +#define GPP_S03_IRQ 0x1E +#define GPP_S04_IRQ 0x1F +#define GPP_S05_IRQ 0x20 +#define GPP_S06_IRQ 0x21 +#define GPP_S07_IRQ 0x22 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define PAD_OWN_REG_0 0x130 +#define PAD_CFG_LOCK_REG_0 0x2e0 +#define HOSTSW_OWN_REG_0 0x310 +#define GPI_INT_STS_0 0x400 +#define GPI_INT_EN_0 0x420 +#define GPI_GPE_STS_0 0x440 +#define GPI_GPE_EN_0 0x460 +#define GPI_SMI_STS_0 0x480 +#define GPI_SMI_EN_0 0x4a0 +#define GPI_NMI_STS_0 0x4c0 +#define GPI_NMI_EN_0 0x4e0 +#define PAD_CFG_BASE 0x900 + +#define GPP_D_START_OFFSET 0x900 +#define GPP_C_START_OFFSET 0xab0 +#define GPP_F_START_OFFSET 0x900 +#define GPP_E_START_OFFSET 0xaa0 +#define GPP_RSVD1_START_OFFSET 0x900 +#define GPP_RSVD2_START_OFFSET 0x920 +#define GPP_H_START_OFFSET 0x9e0 +#define GPP_A_START_OFFSET 0xbc0 +#define GPP_VGPIO3_START_OFFSET 0xd80 +#define GPP_S_START_OFFSET 0x900 +#define GPP_B_START_OFFSET 0x900 +#define GPP_V_START_OFFSET 0xad0 +#define GPP_VGPIO_START_OFFSET 0xc50 + +#endif /* _SOC_NOVALAKE_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/gpio_soc_defs.h b/src/soc/intel/novalake/include/soc/gpio_soc_defs.h new file mode 100644 index 00000000000..cba2126d01c --- /dev/null +++ b/src/soc/intel/novalake/include/soc/gpio_soc_defs.h @@ -0,0 +1,611 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_GPIO_SOC_DEFS_H_ +#define _SOC_NOVALAKE_GPIO_SOC_DEFS_H_ + +#include + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +/* + * NOTE: The following GPP group value comes from GPIO_MISC registers and they + * also need to map to PMC GPIO_CFG register. + */ +/* GPIO COMM 0 */ +#define GPP_D 0x8 +#define GPP_C 0x1 +/* GPIO COMM 1 */ +#define GPP_F 0x2 +#define GPP_E 0x3 +/* GPIO COMM 3 */ +#define GPP_H 0x5 +#define GPP_A 0x4 +#define GPP_VGPIO3 0x6 +/* GPIO COMM 4 */ +#define GPP_S 0x9 +/* GPIO COMM 5 */ +#define GPP_B 0x7 +#define GPP_V 0x0 + +/* for ACPI _UID */ +#define GPP_COMM0_ID 0 +#define GPP_COMM1_ID 1 +#define GPP_COMM3_ID 3 +#define GPP_COMM4_ID 4 +#define GPP_COMM5_ID 5 + +#define GPP_D_NAME "GPP_D" +#define GPP_C_NAME "GPP_C" +#define GPP_F_NAME "GPP_F" +#define GPP_E_NAME "GPP_E" +#define GPP_H_NAME "GPP_H" +#define GPP_A_NAME "GPP_A" +#define GPP_VGPIO3_NAME "vGPIO_3" +#define GPP_S_NAME "GPP_S" +#define GPP_B_NAME "GPP_B" +#define GPP_V_NAME "GPP_V" +#define GPP_VGPIO_NAME "vGPIO" + +#define GPIO_MAX_NUM_PER_GROUP 28 + +#define COMM_0 0 +#define COMM_1 INC(COMM_0) +#define COMM_3 INC(COMM_1) +#define COMM_4 INC(COMM_3) +#define COMM_5 INC(COMM_4) + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* + * +----------------------------+ + * | Community 0 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group D | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 0 | + * +------------------+---------+ + * | Pad End Number | 26 | + * +------------------+---------+ + */ +#define GPP_D00 0 +#define GPP_D01 INC(GPP_D00) +#define GPP_D02 INC(GPP_D01) +#define GPP_D03 INC(GPP_D02) +#define GPP_D04 INC(GPP_D03) +#define GPP_D05 INC(GPP_D04) +#define GPP_D06 INC(GPP_D05) +#define GPP_D07 INC(GPP_D06) +#define GPP_D08 INC(GPP_D07) +#define GPP_D09 INC(GPP_D08) +#define GPP_D10 INC(GPP_D09) /* 10 */ +#define GPP_D11 INC(GPP_D10) +#define GPP_D12 INC(GPP_D11) +#define GPP_D13 INC(GPP_D12) +#define GPP_D14 INC(GPP_D13) +#define GPP_D15 INC(GPP_D14) +#define GPP_D16 INC(GPP_D15) +#define GPP_D17 INC(GPP_D16) +#define GPP_D18 INC(GPP_D17) +#define GPP_D19 INC(GPP_D18) +#define GPP_D20 INC(GPP_D19) /* 20 */ +#define GPP_D21 INC(GPP_D20) +#define GPP_D22 INC(GPP_D21) +#define GPP_D23 INC(GPP_D22) +#define GPP_D24 INC(GPP_D23) +#define GPP_D25 INC(GPP_D24) +#define GPP_I3C_CLK_LPBK INC(GPP_D25) + +#define NUM_GRP_D_PADS (GPP_I3C_CLK_LPBK - GPP_D00 + 1) +#define NUM_GPP_D_PADS (GPP_D25 - GPP_D00 + 1) + +/* + * +----------------------------+ + * | Group C | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 27 | + * +------------------+---------+ + * | Pad End Number | 50 | + * +------------------+---------+ + */ +#define GPP_C00 INC(GPP_I3C_CLK_LPBK) +#define GPP_C01 INC(GPP_C00) +#define GPP_C02 INC(GPP_C01) +#define GPP_C03 INC(GPP_C02) /* 30 */ +#define GPP_C04 INC(GPP_C03) +#define GPP_C05 INC(GPP_C04) +#define GPP_C06 INC(GPP_C05) +#define GPP_C07 INC(GPP_C06) +#define GPP_C08 INC(GPP_C07) +#define GPP_C09 INC(GPP_C08) +#define GPP_C10 INC(GPP_C09) +#define GPP_C11 INC(GPP_C10) +#define GPP_C12 INC(GPP_C11) +#define GPP_C13 INC(GPP_C12) /* 40 */ +#define GPP_C14 INC(GPP_C13) +#define GPP_C15 INC(GPP_C14) +#define GPP_C16 INC(GPP_C15) +#define GPP_C17 INC(GPP_C16) +#define GPP_C18 INC(GPP_C17) +#define GPP_C19 INC(GPP_C18) +#define GPP_C20 INC(GPP_C19) +#define GPP_C21 INC(GPP_C20) +#define GPP_C22 INC(GPP_C21) +#define GPP_C23 INC(GPP_C22) /* 50 */ + +#define NUM_GRP_C_PADS (GPP_C23 - GPP_C00 + 1) +#define NUM_GPP_C_PADS (GPP_C23 - GPP_C00 + 1) + +#define COM0_GRP_PAD_START GPP_D00 +#define COM0_GRP_PAD_END GPP_C23 +#define NUM_COM0_GRP_PADS (GPP_C23 - GPP_D00 + 1) +#define NUM_COM0_GPP_PADS (NUM_GPP_D_PADS + NUM_GPP_C_PADS) +#define NUM_COM0_GROUPS 2 + +/* + * +----------------------------+ + * | Community 1 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group F | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 51 | + * +------------------+---------+ + * | Pad End Number | 76 | + * +------------------+---------+ + */ +#define GPP_F00 INC(GPP_C23) +#define GPP_F01 INC(GPP_F00) +#define GPP_F02 INC(GPP_F01) +#define GPP_F03 INC(GPP_F02) +#define GPP_F04 INC(GPP_F03) +#define GPP_F05 INC(GPP_F04) +#define GPP_F06 INC(GPP_F05) +#define GPP_F07 INC(GPP_F06) +#define GPP_F08 INC(GPP_F07) +#define GPP_F09 INC(GPP_F08) /* 60 */ +#define GPP_F10 INC(GPP_F09) +#define GPP_F11 INC(GPP_F10) +#define GPP_F12 INC(GPP_F11) +#define GPP_F13 INC(GPP_F12) +#define GPP_F14 INC(GPP_F13) +#define GPP_F15 INC(GPP_F14) +#define GPP_F16 INC(GPP_F15) +#define GPP_F17 INC(GPP_F16) +#define GPP_F18 INC(GPP_F17) +#define GPP_F19 INC(GPP_F18) /* 70 */ +#define GPP_F20 INC(GPP_F19) +#define GPP_F21 INC(GPP_F20) +#define GPP_F22 INC(GPP_F21) +#define GPP_F23 INC(GPP_F22) +#define GPP_THC1_GSPI1_I3C1_CLK_LPBK INC(GPP_F23) +#define GPP_GSPI0_CLK_LOOPBK INC(GPP_THC1_GSPI1_I3C1_CLK_LPBK) + +#define NUM_GRP_F_PADS (GPP_GSPI0_CLK_LOOPBK - GPP_F00 + 1) +#define NUM_GPP_F_PADS (GPP_F23 - GPP_F00 + 1) + +/* + * +----------------------------+ + * | Group E | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 77 | + * +------------------+---------+ + * | Pad End Number | 101 | + * +------------------+---------+ + * + * NOTE: GPP_E00 is not a connected PAD in NVL and should be treated + * as other internal used only PADs. It is not meant to be used. + * ref doc: Nova Lake H GPIO Implementation Summary (#817954) + */ +#define GPP_E00 INC(GPP_GSPI0_CLK_LOOPBK) +#define GPP_E01 INC(GPP_E00) +#define GPP_E02 INC(GPP_E01) +#define GPP_E03 INC(GPP_E02) /* 80 */ +#define GPP_E04 INC(GPP_E03) +#define GPP_E05 INC(GPP_E04) +#define GPP_E06 INC(GPP_E05) +#define GPP_E07 INC(GPP_E06) +#define GPP_E08 INC(GPP_E07) +#define GPP_E09 INC(GPP_E08) +#define GPP_E10 INC(GPP_E09) +#define GPP_E11 INC(GPP_E10) +#define GPP_E12 INC(GPP_E11) +#define GPP_E13 INC(GPP_E12) /* 90 */ +#define GPP_E14 INC(GPP_E13) +#define GPP_E15 INC(GPP_E14) +#define GPP_E16 INC(GPP_E15) +#define GPP_E17 INC(GPP_E16) +#define GPP_E18 INC(GPP_E17) +#define GPP_E19 INC(GPP_E18) +#define GPP_E20 INC(GPP_E19) +#define GPP_E21 INC(GPP_E20) +#define GPP_E22 INC(GPP_E21) +#define GPP_BOOTHALT_B INC(GPP_E22) /* 100 */ +#define GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK INC(GPP_BOOTHALT_B) + +#define NUM_GRP_E_PADS (GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK - GPP_E00 + 1) +#define NUM_GPP_E_PADS (GPP_E22 - GPP_E00 + 1) + +#define COM1_GRP_PAD_START GPP_F00 +#define COM1_GRP_PAD_END GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK +#define NUM_COM1_GRP_PADS (GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK - GPP_F00 + 1) +#define NUM_COM1_GPP_PADS (NUM_GPP_F_PADS + NUM_GPP_E_PADS) +#define NUM_COM1_GROUPS 2 + +/* + * +----------------------------+ + * | Community 3 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group CPUJTAG1 | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 102 | + * +------------------+---------+ + * | Pad End Number | 103 | + * +------------------+---------+ + */ +#define GPP_EPD_ON INC(GPP_THC0_GSPI0_I3C0_I3C3_CLK_LPBK) +#define GPP_VDD2_PWRGD INC(GPP_EPD_ON) + +#define NUM_GRP_RSVD1_PADS (GPP_VDD2_PWRGD - GPP_EPD_ON + 1) +#define NUM_GPP_RSVD1_PADS 0 + +/* + * +----------------------------+ + * | Group CPUJTAG | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 104 | + * +------------------+---------+ + * | Pad End Number | 115 | + * +------------------+---------+ + */ +#define GPP_JTAG_MBPB0 INC(GPP_VDD2_PWRGD) +#define GPP_JTAG_MBPB1 INC(GPP_JTAG_MBPB0) +#define GPP_JTAG_TDO INC(GPP_JTAG_MBPB1) +#define GPP_JTAGX INC(GPP_JTAG_TDO) +#define GPP_PRDY_B INC(GPP_JTAGX) +#define GPP_PREQ_B INC(GPP_PRDY_B) +#define GPP_JTAG_TDI INC(GPP_PREQ_B) /* 110 */ +#define GPP_JTAG_TMS INC(GPP_JTAG_TDI) +#define GPP_JTAG_TCK INC(GPP_JTAG_TMS) +#define GPP_DBG_PMODE INC(GPP_JTAG_TCK) +#define GPP_JTAG_TRST_B INC(GPP_DBG_PMODE) +#define GPP_DDSP_HPDALV INC(GPP_JTAG_TRST_B) + +#define NUM_GRP_RSVD2_PADS (GPP_DDSP_HPDALV - GPP_JTAG_MBPB0 + 1) +#define NUM_GPP_RSVD2_PADS 0 + +/* + * +----------------------------+ + * | Group H | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 116 | + * +------------------+---------+ + * | Pad End Number | 145 | + * +------------------+---------+ + */ +#define GPP_H00 INC(GPP_DDSP_HPDALV) +#define GPP_H01 INC(GPP_H00) +#define GPP_H02 INC(GPP_H01) +#define GPP_H03 INC(GPP_H02) +#define GPP_H04 INC(GPP_H03) /* 120 */ +#define GPP_H05 INC(GPP_H04) +#define GPP_H06 INC(GPP_H05) +#define GPP_H07 INC(GPP_H06) +#define GPP_H08 INC(GPP_H07) +#define GPP_H09 INC(GPP_H08) +#define GPP_H10 INC(GPP_H09) +#define GPP_H11 INC(GPP_H10) +#define GPP_H12 INC(GPP_H11) +#define GPP_H13 INC(GPP_H12) +#define GPP_H14 INC(GPP_H13) /* 130 */ +#define GPP_H15 INC(GPP_H14) +#define GPP_H16 INC(GPP_H15) +#define GPP_H17 INC(GPP_H16) +#define GPP_H18 INC(GPP_H17) +#define GPP_H19 INC(GPP_H18) +#define GPP_H20 INC(GPP_H19) +#define GPP_H21 INC(GPP_H20) +#define GPP_H22 INC(GPP_H21) +#define GPP_H23 INC(GPP_H22) +#define GPP_H24 INC(GPP_H23) /* 140 */ +#define GPP_LPI3C1_CLK_LPBK INC(GPP_H24) +#define GPP_LPI3C0_CLK_LPBK INC(GPP_LPI3C1_CLK_LPBK) +#define GPP_ISHI3C1_CLK_LPBK INC(GPP_LPI3C0_CLK_LPBK) +#define GPP_LPI3C2_CLK_LPBK INC(GPP_ISHI3C1_CLK_LPBK) +#define GPP_LPI3C3_CLK_LPBK INC(GPP_LPI3C2_CLK_LPBK) + +#define NUM_GRP_H_PADS (GPP_LPI3C3_CLK_LPBK - GPP_H00 + 1) +#define NUM_GPP_H_PADS (GPP_H24 - GPP_H00 + 1) + +/* + * +----------------------------+ + * | Group A | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 146 | + * +------------------+---------+ + * | Pad End Number | 173 | + * +------------------+---------+ + */ +#define GPP_A00 INC(GPP_LPI3C3_CLK_LPBK) +#define GPP_A01 INC(GPP_A00) +#define GPP_A02 INC(GPP_A01) +#define GPP_A03 INC(GPP_A02) +#define GPP_A04 INC(GPP_A03) /* 150 */ +#define GPP_A05 INC(GPP_A04) +#define GPP_A06 INC(GPP_A05) +#define GPP_A07 INC(GPP_A06) +#define GPP_A08 INC(GPP_A07) +#define GPP_A09 INC(GPP_A08) +#define GPP_A10 INC(GPP_A09) +#define GPP_A11 INC(GPP_A10) +#define GPP_A12 INC(GPP_A11) +#define GPP_A13 INC(GPP_A12) +#define GPP_A14 INC(GPP_A13) /* 160 */ +#define GPP_A15 INC(GPP_A14) +#define GPP_A16 INC(GPP_A15) +#define GPP_A17 INC(GPP_A16) +/* SPI0 PADs */ +#define GPP_SPI0_IO_2 INC(GPP_A17) +#define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2) +#define GPP_SPI0_MOSI_IO_0 INC(GPP_SPI0_IO_3) +#define GPP_SPI0_MOSI_IO_1 INC(GPP_SPI0_MOSI_IO_0) +#define GPP_SPI0_TPM_CS_B INC(GPP_SPI0_MOSI_IO_1) +#define GPP_SPI0_FLASH_0_CS_B INC(GPP_SPI0_TPM_CS_B) +#define GPP_SPI0_FLASH_1_CS_B INC(GPP_SPI0_FLASH_0_CS_B) /* 170 */ +#define GPP_SPI0_CLK INC(GPP_SPI0_FLASH_1_CS_B) +#define GPP_ESPI_CLK_LPBK INC(GPP_SPI0_CLK) +#define GPP_SPI0_CLK_LOOPBK INC(GPP_ESPI_CLK_LPBK) + +#define NUM_GRP_A_PADS (GPP_SPI0_CLK_LOOPBK - GPP_A00 + 1) +#define NUM_GPP_A_PADS (GPP_A17 - GPP_A00 + 1) + +/* + * +----------------------------+ + * | Group vGPIO3 | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 174 | + * +------------------+---------+ + * | Pad End Number | 205 | + * +------------------+---------+ + */ +#define GPP_VGPIO3_USB_OCB_RX_0 INC(GPP_SPI0_CLK_LOOPBK) +#define GPP_VGPIO3_USB_OCB_RX_1 INC(GPP_VGPIO3_USB_OCB_RX_0) +#define GPP_VGPIO3_USB_OCB_RX_2 INC(GPP_VGPIO3_USB_OCB_RX_1) +#define GPP_VGPIO3_USB_OCB_RX_3 INC(GPP_VGPIO3_USB_OCB_RX_2) +#define GPP_VGPIO3_USB_OCB_TX_0 INC(GPP_VGPIO3_USB_OCB_RX_3) +#define GPP_VGPIO3_USB_OCB_TX_1 INC(GPP_VGPIO3_USB_OCB_TX_0) +#define GPP_VGPIO3_USB_OCB_TX_2 INC(GPP_VGPIO3_USB_OCB_TX_1) /* 180 */ +#define GPP_VGPIO3_USB_OCB_TX_3 INC(GPP_VGPIO3_USB_OCB_TX_2) +#define GPP_VGPIO3_TS0 INC(GPP_VGPIO3_USB_OCB_TX_3) +#define GPP_VGPIO3_TS1 INC(GPP_VGPIO3_TS0) +#define GPP_VGPIO3_THC0 INC(GPP_VGPIO3_TS1) +#define GPP_VGPIO3_THC1 INC(GPP_VGPIO3_THC0) +#define GPP_VGPIO3_THC2 INC(GPP_VGPIO3_THC1) +#define GPP_VGPIO3_THC3 INC(GPP_VGPIO3_THC2) +#define GPP_VGPIO3_ESPI_0 INC(GPP_VGPIO3_THC3) +#define GPP_VGPIO3_ESPI_1 INC(GPP_VGPIO3_ESPI_0) +#define GPP_VGPIO3_ESPI_2 INC(GPP_VGPIO3_ESPI_1) /* 190 */ +#define GPP_VGPIO3_ESPI_3 INC(GPP_VGPIO3_ESPI_2) +#define GPP_VGPIO3_ESPI_4 INC(GPP_VGPIO3_ESPI_3) +#define GPP_VGPIO3_ESPI_5 INC(GPP_VGPIO3_ESPI_4) +#define GPP_VGPIO3_ESPI_6 INC(GPP_VGPIO3_ESPI_5) +#define GPP_VGPIO3_ESPI_7 INC(GPP_VGPIO3_ESPI_6) +#define GPP_VGPIO3_ESPI_8 INC(GPP_VGPIO3_ESPI_7) +#define GPP_VGPIO3_ESPI_9 INC(GPP_VGPIO3_ESPI_8) +#define GPP_VGPIO3_ESPI_10 INC(GPP_VGPIO3_ESPI_9) +#define GPP_VGPIO3_ESPI_11 INC(GPP_VGPIO3_ESPI_10) +#define GPP_VGPIO3_ESPI_12 INC(GPP_VGPIO3_ESPI_11) /* 200 */ +#define GPP_VGPIO3_ESPI_13 INC(GPP_VGPIO3_ESPI_12) +#define GPP_VGPIO3_ESPI_14 INC(GPP_VGPIO3_ESPI_13) +#define GPP_VGPIO3_ESPI_15 INC(GPP_VGPIO3_ESPI_14) +#define GPP_VGPIO3_EC_SCI INC(GPP_VGPIO3_ESPI_15) +#define GPP_VGPIO3_EC_SCI1 INC(GPP_VGPIO3_EC_SCI) + +#define NUM_GRP_VGPIO3_PADS (GPP_VGPIO3_EC_SCI1 - GPP_VGPIO3_USB_OCB_RX_0 + 1) +#define NUM_GPP_VGPIO3_PADS 0 + +#define COM3_GRP_PAD_START GPP_EPD_ON +#define COM3_GRP_PAD_END GPP_VGPIO3_EC_SCI1 +#define NUM_COM3_GRP_PADS (GPP_VGPIO3_EC_SCI1 - GPP_EPD_ON + 1) +#define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) +#define NUM_COM3_GROUPS 5 + +/* + * +----------------------------+ + * | Community 4 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group S | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 206 | + * +------------------+---------+ + * | Pad End Number | 213 | + * +------------------+---------+ + */ +#define GPP_S00 INC(GPP_VGPIO3_EC_SCI1) +#define GPP_S01 INC(GPP_S00) +#define GPP_S02 INC(GPP_S01) +#define GPP_S03 INC(GPP_S02) +#define GPP_S04 INC(GPP_S03) /* 210 */ +#define GPP_S05 INC(GPP_S04) +#define GPP_S06 INC(GPP_S05) +#define GPP_S07 INC(GPP_S06) + +#define NUM_GRP_S_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_GPP_S_PADS (GPP_S07 - GPP_S00 + 1) + +#define COM4_GRP_PAD_START GPP_S00 +#define COM4_GRP_PAD_END GPP_S07 +#define NUM_COM4_GRP_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_COM4_GPP_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_COM4_GROUPS 1 + +/* + * +----------------------------+ + * | Community 5 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group B | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 214 | + * +------------------+---------+ + * | Pad End Number | 242 | + * +------------------+---------+ + */ +#define GPP_B00 INC(GPP_S07) +#define GPP_B01 INC(GPP_B00) +#define GPP_B02 INC(GPP_B01) +#define GPP_B03 INC(GPP_B02) +#define GPP_B04 INC(GPP_B03) +#define GPP_B05 INC(GPP_B04) +#define GPP_B06 INC(GPP_B05) /* 220 */ +#define GPP_B07 INC(GPP_B06) +#define GPP_B08 INC(GPP_B07) +#define GPP_B09 INC(GPP_B08) +#define GPP_B10 INC(GPP_B09) +#define GPP_B11 INC(GPP_B10) +#define GPP_B12 INC(GPP_B11) +#define GPP_B13 INC(GPP_B12) +#define GPP_B14 INC(GPP_B13) +#define GPP_B15 INC(GPP_B14) +#define GPP_B16 INC(GPP_B15) /* 230 */ +#define GPP_B17 INC(GPP_B16) +#define GPP_B18 INC(GPP_B17) +#define GPP_B19 INC(GPP_B18) +#define GPP_B20 INC(GPP_B19) +#define GPP_B21 INC(GPP_B20) +#define GPP_B22 INC(GPP_B21) +#define GPP_B23 INC(GPP_B22) +#define GPP_B24 INC(GPP_B23) +#define GPP_B25 INC(GPP_B24) +#define GPP_ISHI3C0_CLK_LPBK INC(GPP_B25) /* 240 */ +#define GPP_A_GSPI1_CLK_LPBK INC(GPP_ISHI3C0_CLK_LPBK) +#define GPP_GSPI2_CLK_LPBK INC(GPP_A_GSPI1_CLK_LPBK) + +#define NUM_GRP_B_PADS (GPP_GSPI2_CLK_LPBK - GPP_B00 + 1) +#define NUM_GPP_B_PADS (GPP_B25 - GPP_B00 + 1) + +/* + * +----------------------------+ + * | Group V | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 243 | + * +------------------+---------+ + * | Pad End Number | 266 | + * +------------------+---------+ + */ +#define GPP_V00 INC(GPP_GSPI2_CLK_LPBK) +#define GPP_V01 INC(GPP_V00) +#define GPP_V02 INC(GPP_V01) +#define GPP_V03 INC(GPP_V02) +#define GPP_V04 INC(GPP_V03) +#define GPP_V05 INC(GPP_V04) +#define GPP_V06 INC(GPP_V05) +#define GPP_V07 INC(GPP_V06) /* 250 */ +#define GPP_V08 INC(GPP_V07) +#define GPP_V09 INC(GPP_V08) +#define GPP_V10 INC(GPP_V09) +#define GPP_V11 INC(GPP_V10) +#define GPP_V12 INC(GPP_V11) +#define GPP_V13 INC(GPP_V12) +#define GPP_V14 INC(GPP_V13) +#define GPP_V15 INC(GPP_V14) +#define GPP_V16 INC(GPP_V15) +#define GPP_V17 INC(GPP_V16) /* 260 */ +#define GPP_RESET_SYNC_B INC(GPP_V17) +#define GPP_SYS_RESET_B INC(GPP_RESET_SYNC_B) +#define GPP_BKLTEN INC(GPP_SYS_RESET_B) +#define GPP_BKLTCTL INC(GPP_BKLTEN) +#define GPP_VDDEN INC(GPP_BKLTCTL) +#define GPP_MLK_RST_B INC(GPP_VDDEN) + +#define NUM_GRP_V_PADS (GPP_MLK_RST_B - GPP_V00 + 1) +#define NUM_GPP_V_PADS (GPP_V17 - GPP_V00 + 1) + +/* + * +----------------------------+ + * | Group vGPIO | + * +------------------+---------+ + * | | NVL-H | + * +------------------+---------+ + * | Pad Start Number | 267 | + * +------------------+---------+ + * | Pad End Number | 284 | + * +------------------+---------+ + */ +#define GPP_VGPIO0 INC(GPP_MLK_RST_B) +#define GPP_VGPIO5 INC(GPP_VGPIO0) +#define GPP_VGPIO30 INC(GPP_VGPIO5) +#define GPP_VGPIO31 INC(GPP_VGPIO30) /* 270 */ +#define GPP_VGPIO32 INC(GPP_VGPIO31) +#define GPP_VGPIO33 INC(GPP_VGPIO32) +#define GPP_VGPIO34 INC(GPP_VGPIO33) +#define GPP_VGPIO35 INC(GPP_VGPIO34) +#define GPP_VGPIO36 INC(GPP_VGPIO35) +#define GPP_VGPIO37 INC(GPP_VGPIO36) +#define GPP_VGPIO40 INC(GPP_VGPIO37) +#define GPP_VGPIO41 INC(GPP_VGPIO40) +#define GPP_VGPIO42 INC(GPP_VGPIO41) +#define GPP_VGPIO43 INC(GPP_VGPIO42) /* 280 */ +#define GPP_VGPIO44 INC(GPP_VGPIO43) +#define GPP_VGPIO45 INC(GPP_VGPIO44) +#define GPP_VGPIO46 INC(GPP_VGPIO45) +#define GPP_VGPIO47 INC(GPP_VGPIO46) + +#define NUM_GRP_VGPIO_PADS (GPP_VGPIO47 - GPP_VGPIO0 + 1) + +#define COM5_GRP_PAD_START GPP_B00 +#define COM5_GRP_PAD_END GPP_VGPIO47 +#define NUM_COM5_GRP_PADS (GPP_VGPIO47 - GPP_B00 + 1) +#define NUM_COM5_GPP_PADS (NUM_GPP_B_PADS + NUM_GPP_V_PADS) +#define NUM_COM5_GROUPS 3 + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (COM5_GRP_PAD_END + 1) + +#endif /* _SOC_NOVALAKE_GPIO_SOC_DEFS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/iomap.h b/src/soc/intel/novalake/include/soc/iomap.h new file mode 100644 index 00000000000..43d325e7f19 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/iomap.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_IOMAP_H_ +#define _SOC_NOVALAKE_IOMAP_H_ + +#include + +/* + * Memory-mapped I/O registers. + */ +#define PCH_PRESERVED_BASE_ADDRESS 0xfd800000 +#define PCH_PRESERVED_BASE_SIZE 0x01000000 + +#define MCH_BASE_ADDRESS 0x4152000000 +#define MCH_BASE_SIZE 0x40000 + +#define NOHOM_BASE_ADDRESS 0x4140000000 + +#define NOHOM_LIMIT_ADDRESS 0x4180000000 +#define NOHOM_SIZE 0x40000000 + +/* System Agent Fabric (SAF) */ +#define SAF_BASE_ADDRESS 0x4150000000 +#define SAF_BASE_SIZE (32 * MiB) + +/* Add dummy entry to cater common/block/acpi/acpi/northbridge.asl */ +#define DMI_BASE_SIZE 0 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +/* VT-d 512KB */ +#define VTD_BASE_ADDRESS 0xfc800000 +#define VTD_BASE_SIZE 0x80000 + +/* GFX VT-d 64KB */ +#define GFXVT_BASE_ADDRESS 0xfc800000 +#define GFXVT_BASE_SIZE 0x10000 + +/* Non-GFX VT-d 64KB */ +#define VTVC0_BASE_ADDRESS 0xfc810000 +#define VTVC0_BASE_SIZE 0x10000 + +/* IOC VT-d 64KB */ +#define IOCVTD_BASE_ADDRESS 0xfc820000 +#define IOCVTD_BASE_SIZE 0x10000 + +#define UART_BASE_SIZE 0x1000 +#define UART_BASE_0_ADDRESS CONFIG_CONSOLE_UART_BASE_ADDRESS +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define SPI_BASE_ADDRESS 0xfe010000 + +/* REGBAR 128MB */ +#define REG_BASE_ADDRESS 0x4148000000 +#define REG_BASE_SIZE (128 * MiB) + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (256 * MiB) + +/* PCH P2SB2 256MB */ +#define P2SB2_BAR CONFIG_P2SB_2_PCR_BASE_ADDRESS +#define P2SB2_SIZE (256 * MiB) + +#define IOM_BASE_ADDR 0x4110800000 /* P2SB2_BAR + (PID_IOM << 16) */ +#define IOM_BASE_SIZE 0x10000 +#define IOM_BASE_ADDR_MAX 0x411080ffff /* IOM_BASE_ADDR + IOM_BASE_SIZE - 1 */ + +/* Temporary MMIO address for GMADR (aka LMEMBAR) with 256MB */ +#define GMADR_BASE 0x4180000000 +#define GMADR_SIZE 0x10000000 + +/* I/O port address space */ +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#endif /* _SOC_NOVALAKE_IOMAP_H_ */ diff --git a/src/soc/intel/novalake/include/soc/irq.h b/src/soc/intel/novalake/include/soc/irq.h new file mode 100644 index 00000000000..a16cda74faf --- /dev/null +++ b/src/soc/intel/novalake/include/soc/irq.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_IRQ_H_ +#define _SOC_NOVALAKE_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 31 + +#endif diff --git a/src/soc/intel/novalake/include/soc/meminit.h b/src/soc/intel/novalake/include/soc/meminit.h new file mode 100644 index 00000000000..a87f2d1211e --- /dev/null +++ b/src/soc/intel/novalake/include/soc/meminit.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_MEMINIT_H_ +#define _SOC_NOVALAKE_MEMINIT_H_ + +#include +#include +#include +#include + +enum mem_type { + MEM_TYPE_DDR4, + MEM_TYPE_DDR5, + MEM_TYPE_LP4X, + MEM_TYPE_LP5X, +}; + +struct mem_ddr_config { + /* Dqs Pins Interleaved Setting. Enable/Disable Control */ + bool dq_pins_interleaved; +}; + +struct lpx_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; +}; + +struct lpx_dqs { + uint8_t dqs0; + uint8_t dqs1; +}; + +struct lpx_dq_map { + struct lpx_dq ddr0; + struct lpx_dq ddr1; + struct lpx_dq ddr2; + struct lpx_dq ddr3; + struct lpx_dq ddr4; + struct lpx_dq ddr5; + struct lpx_dq ddr6; + struct lpx_dq ddr7; +}; + +struct lpx_dqs_map { + struct lpx_dqs ddr0; + struct lpx_dqs ddr1; + struct lpx_dqs ddr2; + struct lpx_dqs ddr3; + struct lpx_dqs ddr4; + struct lpx_dqs ddr5; + struct lpx_dqs ddr6; + struct lpx_dqs ddr7; +}; + +struct mem_lp5x_config { + uint8_t ccc_config; +}; + +struct rcomp { + /* + * Rcomp resistor value. This values represents the resistance in + * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC. + * + * Note: If mainboard users don't want to override rcomp related settings + * then associated rcomp UPDs will have its default value. + */ + uint16_t resistor; + /* Rcomp target values. */ + uint16_t targets[5]; +}; + +struct mb_cfg { + enum mem_type type; + struct rcomp rcomp; + union { + /* + * DQ CPU<>DRAM map: + * Index of the array represents DQ# on the CPU and the value represents DQ# on + * the DRAM part. + */ + uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]; + struct lpx_dq_map lpx_dq_map; + }; + + union { + /* + * DQS CPU<>DRAM map: + * Index of the array represents DQS# on the CPU and the value represents DQS# + * on the DRAM part. + */ + uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]; + struct lpx_dqs_map lpx_dqs_map; + }; + + union { + struct mem_lp5x_config lp5x_config; + struct mem_ddr_config ddr_config; + }; + + /* Early Command Training Enable/Disable Control */ + bool ect; + + /* Board type */ + uint8_t user_bd; +}; + +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated); + +#endif /* _SOC_NOVALAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/novalake/include/soc/msr.h b/src/soc/intel/novalake/include/soc/msr.h new file mode 100644 index 00000000000..b0249f2a5db --- /dev/null +++ b/src/soc/intel/novalake/include/soc/msr.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_MSR_H_ +#define _SOC_NOVALAKE_MSR_H_ + +#include + +#define MSR_BIOS_DONE 0x151 +#define ENABLE_IA_UNTRUSTED BIT(0) +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif /* _SOC_NOVALAKE_MSR_H_ */ diff --git a/src/soc/intel/novalake/include/soc/nvs.h b/src/soc/intel/novalake/include/soc/nvs.h new file mode 100644 index 00000000000..3c3b4edaa4c --- /dev/null +++ b/src/soc/intel/novalake/include/soc/nvs.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_NVS_H_ +#define _SOC_NOVALAKE_NVS_H_ + +#include + +#endif diff --git a/src/soc/intel/novalake/include/soc/p2sb.h b/src/soc/intel/novalake/include/soc/p2sb.h new file mode 100644 index 00000000000..d5ab70a6599 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/p2sb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_P2SB_H_ +#define _SOC_NOVALAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT BIT(7) + +#define PCH_P2SB_EPMASK0 0x220 + +extern const struct device_operations p2sb_ops; +extern const struct device_operations p2sb2_ops; + +#endif /* _SOC_NOVALAKE_P2SB_H_ */ diff --git a/src/soc/intel/novalake/include/soc/pci_devs.h b/src/soc/intel/novalake/include/soc/pci_devs.h new file mode 100644 index 00000000000..e33be4456b2 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/pci_devs.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_PCI_DEVS_H_ +#define _SOC_NOVALAKE_PCI_DEVS_H_ + +#include + +#define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func) +#if !defined(__SIMPLE_DEVICE__) +#include +#define _PCI_DEV(slot, func) pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__) +#else +#define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define PCI_DEV_SLOT_ROOT 0x00 +#define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define PCI_DEV_ROOT _PCI_DEV(ROOT, 0) +#endif + +#define PCI_DEV_SLOT_IGD 0x02 +#define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0) +#define PCI_DEV_IGD _PCI_DEV(IGD, 0) + +#define PCI_DEV_SLOT_DPTF 0x04 +#define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0) +#define PCI_DEV_DPTF _PCI_DEV(DPTF, 0) + +#define PCI_DEV_SLOT_IPU 0x05 +#define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0) +#define PCI_DEV_IPU _PCI_DEV(IPU, 0) + +#define PCI_DEV_SLOT_PCIE_2 0x06 +#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) +#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_2, 3) +#define PCI_DEVFN_PCIE13 _PCI_DEVFN(PCIE_2, 4) +#define PCI_DEVFN_PCIE14 _PCI_DEVFN(PCIE_2, 5) +#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) +#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) +#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_2, 3) +#define PCI_DEV_PCIE13 _PCI_DEV(PCIE_2, 4) +#define PCI_DEV_PCIE14 _PCI_DEV(PCIE_2, 5) + +#define PCI_DEV_SLOT_TBT 0x07 +#define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) +#define NUM_TBT_FUNCTIONS 3 +#define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) +#define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) +#define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) +#define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) +#define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) +#define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) + +#define PCI_DEV_SLOT_THC1 0x08 +#define PCI_DEVFN_THC1 _PCI_DEVFN(THC1, 0) +#define PCI_DEV_THC1 _PCI_DEV(THC1, 0) + +#define PCI_DEV_SLOT_TELEMETRY 0x0a +#define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) +#define PCI_DEV_TELEMETRY _PCI_DEV(TELEMETRY, 0) + +#define PCI_DEV_SLOT_NPU 0x0b +#define PCI_DEVFN_NPU _PCI_DEVFN(NPU, 0) +#define PCI_DEV_NPU _PCI_DEV(NPU, 0) + +#define PCI_DEV_SLOT_IAA 0x0c +#define PCI_DEVFN_IAA _PCI_DEVFN(IAA, 0) +#define PCI_DEV_IAA _PCI_DEV(IAA, 0) + +#define PCI_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 1 +#define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) +#define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) +#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) +#define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) +#define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) +#define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) +#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) +#define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) + +#define PCI_DEV_SLOT_VMD 0x0e +#define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0) +#define PCI_DEV_VMD _PCI_DEV(VMD, 0) + +#define PCI_DEV_SLOT_THC0 0x10 +#define PCI_DEVFN_THC0 _PCI_DEVFN(THC0, 0) +#define PCI_DEV_THC0 _PCI_DEV(THC0, 0) + +#define PCI_DEV_SLOT_I3C 0x11 +#define PCI_DEVFN_I3C1 _PCI_DEVFN(I3C, 0) +#define PCI_DEVFN_I3C2 _PCI_DEVFN(I3C, 2) +#define PCI_DEV_I3C1 _PCI_DEV(I3C, 0) +#define PCI_DEV_I3C2 _PCI_DEV(I3C, 2) + +#define PCI_DEV_SLOT_IEH1 0x12 +#define PCI_DEVFN_IEH1 _PCI_DEVFN(IEH1, 0) +#define PCI_DEVFN_P2SB2 _PCI_DEVFN(IEH1, 1) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(IEH1, 6) +#define PCI_DEV_IEH1 _PCI_DEV(IEH1, 0) +#define PCI_DEV_P2SB2 _PCI_DEV(IEH1, 1) +#define PCI_DEV_GSPI2 _PCI_DEV(IEH1, 6) + +#define PCI_DEV_SLOT_OSSE 0x13 +#define PCI_DEVFN_OSSE1 _PCI_DEVFN(OSSE, 0) +#define PCI_DEVFN_OSSE2 _PCI_DEVFN(OSSE, 1) +#define PCI_DEVFN_OSSE3 _PCI_DEVFN(OSSE, 2) +#define PCI_DEV_OSSE1 _PCI_DEV(OSSE, 0) +#define PCI_DEV_OSSE2 _PCI_DEV(OSSE, 1) +#define PCI_DEV_OSSE3 _PCI_DEV(OSSE, 2) + +#define PCI_DEV_SLOT_XHCI 0x14 +#define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0) +#define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) +#define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) +#define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) +#define PCI_DEVFN_IEH _PCI_DEVFN(XHCI, 5) +#define PCI_DEVFN_CNVI_BT _PCI_DEVFN(XHCI, 7) +#define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) +#define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) +#define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) +#define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3) +#define PCI_DEV_IEH _PCI_DEV(XHCI, 5) +#define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7) + +#define PCI_DEV_SLOT_SIO0 0x15 +#define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0) +#define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1) +#define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2) +#define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3) +#define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0) +#define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1) +#define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2) +#define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3) + +#define PCI_DEV_SLOT_CSE 0x16 +#define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0) +#define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1) +#define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) +#define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) +#define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4) +#define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5) +#define PCI_DEV_CSE _PCI_DEV(CSE, 0) +#define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1) +#define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2) +#define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) +#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) +#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) +#define PCI_DEV_CSE_WLAN _PCI_DEV(CSE, 7) + +#define PCI_DEV_SLOT_UFS 0x17 +#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) +#define PCI_DEV_UFS _PCI_DEV(UFS, 0) + +#define PCI_DEV_SLOT_ESE 0x18 +#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) +#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) +#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) +#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) +#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) +#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) + +#define PCI_DEV_SLOT_SIO1 0x19 +#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) +#define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1) +#define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2) +#define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0) +#define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1) +#define PCI_DEV_UART2 _PCI_DEV(SIO1, 2) + +#define PCI_DEV_SLOT_ISH 0x1a +#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) +#define PCI_DEV_ISH _PCI_DEV(ISH, 0) + +#define PCI_DEV_SLOT_PCIE_1 0x1c +#define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0) +#define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) +#define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) +#define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) +#define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6) +#define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7) +#define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) +#define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) +#define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) +#define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) +#define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6) +#define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7) + +#define PCI_DEV_SLOT_SIO2 0x1e +#define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) +#define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) +#define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2) +#define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3) +#define PCI_DEV_UART0 _PCI_DEV(SIO2, 0) +#define PCI_DEV_UART1 _PCI_DEV(SIO2, 1) +#define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2) +#define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3) + +#define PCI_DEV_SLOT_ESPI 0x1f +#define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0) +#define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1) +#define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2) +#define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3) +#define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5) +#define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6) +#define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7) +#define PCI_DEV_ESPI _PCI_DEV(ESPI, 0) +#define PCI_DEV_P2SB _PCI_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCI_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCI_DEV_PMC _PCI_DEV(ESPI, 2) +#endif + +#define PCI_DEV_HDA _PCI_DEV(ESPI, 3) +#define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4) +#define PCI_DEV_SPI _PCI_DEV(ESPI, 5) +#define PCI_DEV_GBE _PCI_DEV(ESPI, 6) +#define PCI_DEV_NPK _PCI_DEV(ESPI, 7) + +/* for common code */ +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC0 +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define PCH_DEVFN_CSE PCI_DEVFN_CSE +#define PCH_DEV_CSE PCI_DEV_CSE +#define PCH_DEV_SPI PCI_DEV_SPI +#define PCH_DEV_LPC PCI_DEV_ESPI +#define PCH_DEV_P2SB PCI_DEV_P2SB +#define PCH_DEV_P2SB2 PCI_DEV_P2SB2 +#define PCH_DEV_SMBUS PCI_DEV_SMBUS +#define PCH_DEV_XHCI PCI_DEV_XHCI +#define PCH_DEVFN_XHCI PCI_DEVFN_XHCI +#define PCH_DEVFN_PMC PCI_DEVFN_PMC +#define PCI_DEV_IOE_P2SB PCH_DEV_P2SB2 +#define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH +#define SA_DEV_ROOT PCI_DEV_ROOT +#define SA_DEVFN_ROOT PCI_DEVFN_ROOT +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 +#define SA_DEV_IGD PCI_DEV_IGD +#define SA_DEVFN_IGD PCI_DEVFN_IGD +#define SOC_I2C_DEVFN(n) PCI_DEVFN_I2C##n +#define SOC_GSPI_DEVFN(n) PCI_DEVFN_GSPI##n +#define SOC_PMC_DEV PCI_DEV_PMC + +#endif /* _SOC_NOVALAKE_PCI_DEVS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/pcie.h b/src/soc/intel/novalake/include/soc/pcie.h new file mode 100644 index 00000000000..008a16486af --- /dev/null +++ b/src/soc/intel/novalake/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_NOVALAKE_PCIE_H__ +#define __SOC_NOVALAKE_PCIE_H__ + +#include + +const struct pcie_rp_group *get_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); + +#endif /* __SOC_NOVALAKE_PCIE_H__ */ diff --git a/src/soc/intel/novalake/include/soc/pcr_ids.h b/src/soc/intel/novalake/include/soc/pcr_ids.h new file mode 100644 index 00000000000..473815b4946 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/pcr_ids.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_PCR_IDS_H_ +#define _SOC_NOVALAKE_PCR_IDS_H_ + +/* Port IDs */ + +#define PID_XHCI 0x09 +#define PID_DMI 0x56 +#define PID_CSME0 0x40 +#define PID_CNVI 0x51 +#define PID_GPIOCOM0 0x59 +#define PID_GPIOCOM1 0x5A +#define PID_GPIOCOM3 0x5B +#define PID_GPIOCOM4 0x5C +#define PID_GPIOCOM5 0x5D +#define PID_ITSS 0x69 +#define PID_PSTH 0x6A +#define PID_RTC 0x6C +#define PID_ISCLK 0x72 +#define PID_IOM 0x80 +#define PID_NPK 0x8C +#define PID_PSF4 0xB0 +#define PID_PSF6 0xB1 +#define PID_PSF8 0xB2 +#define PID_PSF14 0xB3 +#define PID_PSF15 0xB4 +#define PID_PSF0 0xB5 + +#endif /* _SOC_NOVALAKE_PCR_IDS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/pm.h b/src/soc/intel/novalake/include/soc/pm.h new file mode 100644 index 00000000000..fbdcc338096 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/pm.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_PM_H_ +#define _SOC_NOVALAKE_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS BIT(15) +#define PCIEXPWAK_STS BIT(14) +#define PRBTNOR_STS BIT(11) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TMROF_STS BIT(0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS BIT(14) +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TMROF_EN BIT(0) +#define PM1_CNT 0x04 +#define GBL_RLS BIT(2) +#define BM_RLD BIT(1) +#define SCI_EN BIT(0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN BIT(31) +#define ME_SMI_EN BIT(30) +#define ESPI_SMI_EN BIT(28) +#define GPIO_UNLOCK_SMI_EN BIT(27) +#define INTEL_USB2_EN BIT(18) +#define LEGACY_USB2_EN BIT(17) +#define PERIODIC_EN BIT(14) +#define TCO_SMI_EN BIT(13) +#define MCSMI_EN BIT(11) +#define BIOS_RLS BIT(7) +#define SWSMI_TMR_EN BIT(6) +#define APMC_EN BIT(5) +#define SLP_SMI_EN BIT(4) +#define LEGACY_USB_EN BIT(3) +#define BIOS_EN BIT(2) +#define EOS BIT(1) +#define GBL_SMI_EN BIT(0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL BIT(1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS BIT(18) +#define GPIO_T2_STS BIT(15) +#define ESPI_STS BIT(14) +#define PME_B0_STS BIT(13) +#define ME_SCI_STS BIT(12) +#define PME_STS BIT(11) +#define BATLOW_STS BIT(10) +#define PCI_EXP_STS BIT(9) +#define SMB_WAK_STS BIT(7) +#define TCOSCI_STS BIT(6) +#define SWGPE_STS BIT(2) +#define HOT_PLUG_STS BIT(1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN BIT(18) +#define GPIO_T2_EN BIT(15) +#define ESPI_EN BIT(14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN BIT(PME_B0_EN_BIT) +#define ME_SCI_EN BIT(12) +#define PME_EN BIT(11) +#define BATLOW_EN BIT(10) +#define PCI_EXP_EN BIT(9) +#define TCOSCI_EN BIT(6) +#define SWGPE_EN BIT(2) +#define HOT_PLUG_EN BIT(1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include +#include +#include +#include +#include + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ + +#endif /* _SOC_NOVALAKE_PM_H_ */ diff --git a/src/soc/intel/novalake/include/soc/pmc.h b/src/soc/intel/novalake/include/soc/pmc.h new file mode 100644 index 00000000000..f1f9a793c78 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/pmc.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_PMC_H_ +#define _SOC_NOVALAKE_PMC_H_ + +#include + +extern struct device_operations pmc_ops; + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* General PM Configuration A */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS BIT(30) +#define DSX_PP_DIS BIT(29) +#define AG3_PP_EN BIT(28) +#define SX_PP_EN BIT(27) +#define ALLOW_ICLK_PLL_SD_INC0 BIT(26) +#define GBL_RST_STS BIT(24) +#define DISB BIT(23) +#define ALLOW_OPI_PLL_SD_INC0 BIT(22) +#define MEM_SR BIT(21) +#define ALLOW_SPXB_CG_INC0 BIT(20) +#define ALLOW_L1LOW_C0 BIT(19) +#define MS4V BIT_FLAG_32(18) +#define ALLOW_L1LOW_OPI_ON BIT(17) +#define SUS_PWR_FLR BIT(16) +#define PME_B0_S5_DIS BIT(15) +#define PWR_FLR BIT(14) +#define ALLOW_L1LOW_BCLKREQ_ON BIT(13) +#define DIS_SLP_X_STRCH_SUS_UP BIT(12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS BIT(10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS BIT(9) +#define ESPI_SMI_LOCK BIT(8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S BIT(4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE BIT(3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S BIT(1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL BIT(0) + +/* General PM Configuration B */ +#define GEN_PMCON_B 0x1024 +#define ST_FDIS_LOCK BIT(21) +/* Alias used by common lockdown driver */ +#define PMC_FDIS_LOCK_REG GEN_PMCON_B +#define SLP_STR_POL_LOCK BIT(18) +#define ACPI_BASE_LOCK BIT(17) +#define PM_DATA_BAR_DIS BIT(16) +#define WOL_EN_OVRD BIT(13) +#define BIOS_PCI_EXP_EN BIT(10) +#define PWRBTN_LVL BIT(9) +#define SMI_LOCK BIT(4) +#define RTC_BATTERY_DEAD BIT(2) + +/* Extended Test Mode Register */ +#define ETR 0x1048 +#define CF9_LOCK BIT(31) +#define CF9_GLB_RST BIT(20) + +/* Set strap message lock */ +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN BIT(0) + +/* Set strap msg control */ +#define SSMC 0x1050 +#define SSMC_SSMS BIT(0) + +/* Set strap message data */ +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +/* Power and Reset Status */ +#define PRSTS 0x1810 + +/* Power Management Configuration */ +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK BIT(27) +#define PM_CFG_XRAM_READ_DISABLE BIT(22) + +/* S3 Power Gating Policies */ +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS BIT(1) +#define S3AC_GATE_SUS BIT(0) + +/* S4 power gating policies */ +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS BIT(1) +#define S4AC_GATE_SUS BIT(0) + +/* S5 power gating policies */ +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS BIT(15) +#define S5AC_GATE_SUS BIT(14) + +/* Deep Sx configuration */ +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX BIT(4) +#define REQ_BATLOW_DSX BIT(3) +#define DSX_EN_WAKE_PIN BIT(2) +#define DSX_DIS_AC_PRESENT_PD BIT(1) +#define DSX_EN_LAN_WAKE_PIN BIT(0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK BIT(31) +#define PCH2CPU_TT_EN BIT(26) + +/* ACPI Timer Control */ +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS BIT(1) +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#define PMC_GPP_V 0x0 +#define PMC_GPP_C 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_E 0x3 +#define PMC_GPP_H 0x4 +#define PMC_GPP_F 0x5 +#define PMC_GPP_VGPIO3 0x6 +#define PMC_GPP_B 0x7 +#define PMC_GPP_D 0x8 +#define PMC_GPP_S 0x9 + +/* Global reset causes 0 */ +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP BIT(5) + +/* Global reset causes 1 */ +#define GBLRST_CAUSE1 0x1928 + +/* Host partition reset causes */ +#define HPR_CAUSE0 0x192C +#define HPR_CAUSE0_MI_HRPD BIT(10) +#define HPR_CAUSE0_MI_HRPC BIT(9) +#define HPR_CAUSE0_MI_HR BIT(8) + +/* Sleep S0 residency */ +#define SLP_S0_RES 0x193c + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS BIT(22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 + +/* ACPI Control */ +#define ACTL 0x1BD8 +#define PWRM_EN BIT(8) +#define ACPI_EN BIT(7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 + +#endif /* _SOC_NOVALAKE_PMC_H_ */ diff --git a/src/soc/intel/novalake/include/soc/ramstage.h b/src/soc/intel/novalake/include/soc/ramstage.h new file mode 100644 index 00000000000..fb2bc2e81b9 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/ramstage.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_RAMSTAGE_H_ +#define _SOC_NOVALAKE_RAMSTAGE_H_ + +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_novalake_config *config); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/novalake/include/soc/romstage.h b/src/soc/intel/novalake/include/soc/romstage.h new file mode 100644 index 00000000000..572afa915ae --- /dev/null +++ b/src/soc/intel/novalake/include/soc/romstage.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_ROMSTAGE_H_ +#define _SOC_NOVALAKE_ROMSTAGE_H_ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *memupd); +void systemagent_early_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_NOVALAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/novalake/include/soc/serialio.h b/src/soc/intel/novalake/include/soc/serialio.h new file mode 100644 index 00000000000..a7cb81fc618 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/serialio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_SERIALIO_H_ +#define _SOC_NOVALAKE_SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialPio, + PchSerialDma +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexI3C0, + PchSerialIoIndexI3C1 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2, +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2 +}; + +#endif /* _SOC_NOVALAKE_SERIALIO_H_ */ diff --git a/src/soc/intel/novalake/include/soc/smbus.h b/src/soc/intel/novalake/include/soc/smbus.h new file mode 100644 index 00000000000..fa8676d7c86 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/smbus.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_SMBUS_H_ +#define _SOC_NOVALAKE_SMBUS_H_ + +#include + +#endif /* _SOC_NOVALAKE_SMBUS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/soc_chip.h b/src/soc/intel/novalake/include/soc/soc_chip.h new file mode 100644 index 00000000000..5266250edfc --- /dev/null +++ b/src/soc/intel/novalake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_SOC_CHIP_H_ +#define _SOC_NOVALAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_NOVALAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/novalake/include/soc/systemagent.h b/src/soc/intel/novalake/include/soc/systemagent.h new file mode 100644 index 00000000000..8493fe5784b --- /dev/null +++ b/src/soc/intel/novalake/include/soc/systemagent.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_SYSTEMAGENT_H_ +#define _SOC_NOVALAKE_SYSTEMAGENT_H_ + +#include + +/* Device 0:0.0 PCI configuration space */ + +#define SAFBAR 0x68 +#define EPBAR 0x40 +#define NOHOMBASE 0x90 +#define NOHOMLIMIT 0x98 +#define CAPID0_A 0xe4 +#define VTD_DISABLE BIT(23) + +/* MCHBAR offsets */ +#define REGBAR 0x5400 +#define VTDBAR 0x5410 +#define GFXVTBAR VTDBAR +#define GFXVT_ENABLED BIT(0) +#define NONGFXVT_ENABLED BIT(1) +#define IOCVT_ENABLED BIT(2) + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define PCODE_MAILBOX_DATA 0x5da0 +#define PCODE_MAILBOX_INTERFACE 0x5da4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6a40 +#define IMRLIMIT 0x6a48 +#define IPUVTBAR 0x7880 +#define TBTxBAR(x) (0x7888 + (x) * 8) + +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { VTDBAR, VTD_BASE_ADDRESS, VTD_BASE_SIZE, "VTDBAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#define CRAB_ABORT_BASE_ADDR 0xFEB00000 +#define CRAB_ABORT_SIZE (512 * KiB) +#define TPM_BASE_ADDRESS 0xFED40000 +#define TPM_SIZE (64 * KiB) +#define LT_SECURITY_BASE_ADDR 0xFED20000 +#define LT_SECURITY_SIZE (384 * KiB) +#define APIC_SIZE (1 * MiB) + +uint64_t get_mmcfg_size(const struct device *dev); +uint64_t get_dsm_size(const struct device *dev); +uint64_t get_gsm_size(const struct device *dev); +uint64_t get_dpr_size(const struct device *dev); + +#endif /* _SOC_NOVALAKE_SYSTEMAGENT_H_ */ diff --git a/src/soc/intel/novalake/include/soc/tcss.h b/src/soc/intel/novalake/include/soc/tcss.h new file mode 100644 index 00000000000..d10b4a47d6d --- /dev/null +++ b/src/soc/intel/novalake/include/soc/tcss.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_NOVALAKE_TCSS_H_ +#define _SOC_NOVALAKE_TCSS_H_ + +/* Thunderbolt firmware IMR status */ +#define IOM_CSME_IMR_TBT_STATUS 0x14 +#define TBT_VALID_AUTHENTICATION BIT(30) + +/* IOM aux bias control registers in REGBAR MMIO space */ +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) + +#define BIAS_CTRL_VW_INDEX_SHIFT 16 +#define BIAS_CTRL_BIT_POS_SHIFT 8 + +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 + +enum { + TCSS_TYPE_C_PORT_USBC = 0x0, + TCSS_TYPE_C_PORT_HDMI = 0x1, + TCSS_TYPE_C_PORT_EDP = 0x2, + TCSS_TYPE_C_PORT_USBA = 0x3, + TCSS_TYPE_C_PORT_DISABLE = 0xF, + TCSS_TYPE_C_PORT_DP_ONLY = 0x10, + TCSS_TYPE_C_PORT_NO_PCIE = 0x11, + TCSS_TYPE_C_PORT_FULL_FUN = 0x12 +}; + +#endif /* _SOC_NOVALAKE_TCSS_H_ */ diff --git a/src/soc/intel/novalake/include/soc/touch.h b/src/soc/intel/novalake/include/soc/touch.h new file mode 100644 index 00000000000..7646e1279b7 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/touch.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_TOUCH_H_ +#define _SOC_NOVALAKE_TOUCH_H_ + +#include + +/* For THC-I2C: */ + +/* + * I2C Standard Mode (100Kbps): + * Requested Connection Speed: 186A0 + * I2C Speed Mode: Standard (100Kbps) = 0x186A0 + * + * I2C Fast Mode (400Kbps): + * Requested Connection Speed: 61A80 + * I2C Speed Mode: Fast (400Kbps) = 0x612B0 + * + * I2C Fast-Plus Mode (1Mbps): + * Requested Connection Speed: F4240 + * I2C Speed Mode: Fast-Plus (1Mbps) = 0xF4240 + * FM SCL HIGH Period: 34 Fast Mode (FM) CLK Signal HIGH Period + * FM SCL LOW Period: 3E Fast Mode (FM) CLK Signal LOW Period + */ +#define SOC_NVL_THC_I2C_CONNECTION_SPEED_SM 0x186a0 +#define SOC_NVL_THC_I2C_CONNECTION_SPEED_FM 0x61a80 +#define SOC_NVL_THC_I2C_CONNECTION_SPEED_FMP 0xf4240 + +/* + * 0 = 7-bit Addressing Mode for HID-I2C (Default) + * 1 = 10-bit Addressing Mode for HID-I2C + */ +#define SOC_NVL_THC_I2C_ADDR_MODE 0 +#define SOC_NVL_THC_I2C_SM_SCL_HIGH_PERIOD 0x267 +#define SOC_NVL_THC_I2C_SM_SCL_LOW_PERIOD 0x271 +#define SOC_NVL_THC_I2C_SM_SDA_HOLD_TX_PERIOD 0 +#define SOC_NVL_THC_I2C_SM_SDA_HOLD_RX_PERIOD 0 +#define SOC_NVL_THC_I2C_FM_SCL_HIGH_PERIOD 0x92 +#define SOC_NVL_THC_I2C_FM_SCL_LOW_PERIOD 0x9c +#define SOC_NVL_THC_I2C_FM_SDA_HOLD_TX_PERIOD 0 +#define SOC_NVL_THC_I2C_FM_SDA_HOLD_RX_PERIOD 0 +#define SOC_NVL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP 0 +#define SOC_NVL_THC_I2C_FMP_SCL_HIGH_PERIOD 0x34 +#define SOC_NVL_THC_I2C_FMP_SCL_LOW_PERIOD 0x3e +#define SOC_NVL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD 0 +#define SOC_NVL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD 0 +#define SOC_NVL_THC_I2C_HM_SCL_HIGH_PERIOD 0 +#define SOC_NVL_THC_I2C_HM_SCL_LOW_PERIOD 0 +#define SOC_NVL_THC_I2C_HM_SDA_HOLD_TX_PERIOD 0 +#define SOC_NVL_THC_I2C_HM_SDA_HOLD_RX_PERIOD 0 +#define SOC_NVL_THC_I2C_SUPPRESSED_SPIKES_H_FP 0 + + +/* For THC-SPI: */ + +/* unit: ms */ +#define SOC_NVL_THC_RST_SEQ_DLY 300 + +/* The initial default speed is 17 MHz. */ +#define SOC_NVL_THC_SPI_CONNECTION_SPEED (17 * MHz) + +/* 0 = no limit */ +#define SOC_NVL_THC_HIDSPI_LIMIT_PKT_SZ 0 +#define SOC_NVL_THC_PERFORMANCE_LIMIT 0 + +#endif /* _SOC_NOVALAKE_TOUCH_H_ */ diff --git a/src/soc/intel/novalake/include/soc/ufs.h b/src/soc/intel/novalake/include/soc/ufs.h new file mode 100644 index 00000000000..c991034db78 --- /dev/null +++ b/src/soc/intel/novalake/include/soc/ufs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NOVALAKE_UFS_H_ +#define _SOC_NOVALAKE_UFS_H_ + +#include + +/* Calculate _ADR for Intel UFS Controller */ +#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16) + +#define R_SCS_CFG_PCS 0x84 +#define R_SCS_CFG_PG_CONFIG 0xA2 + +#endif diff --git a/src/soc/intel/novalake/meminit.c b/src/soc/intel/novalake/meminit.c new file mode 100644 index 00000000000..2736e8868c1 --- /dev/null +++ b/src/soc/intel/novalake/meminit.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +#define LP5_PHYSICAL_CH_WIDTH 16 +#define LP5_CHANNELS CHANNEL_COUNT(LP5_PHYSICAL_CH_WIDTH) + +static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) +{ + if (mb_cfg->rcomp.resistor) + mem_cfg->RcompResistor = mb_cfg->rcomp.resistor; + + for (size_t i = 0; i < ARRAY_SIZE(mem_cfg->RcompTarget); i++) + if (mb_cfg->rcomp.targets[i]) + mem_cfg->RcompTarget[i] = mb_cfg->rcomp.targets[i]; +} + +static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config) +{ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->Lp5CccConfig = lp5x_config->ccc_config; +} + +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_LP5X] = { + .num_phys_channels = LP5_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case + * of half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP5x does not support mixed topology. */ + }, + }, +}; + +#define SPD_PTR_IDX(mc, ch, dimm) \ + ((mc) * (MRC_CHANNELS / 2) * CONFIG_DIMMS_PER_CHANNEL + \ + (ch) * CONFIG_DIMMS_PER_CHANNEL + \ + (dimm)) + +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +{ + uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { + [0] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 0, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 0, 1)], }, + [1] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 1, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 1, 1)], }, + [2] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 2, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 2, 1)], }, + [3] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 3, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(0, 3, 1)], }, + [4] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 0, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 0, 1)], }, + [5] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 1, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 1, 1)], }, + [6] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 2, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 2, 1)], }, + [7] = { &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 3, 0)], &mem_cfg->MemorySpdPtr[SPD_PTR_IDX(1, 3, 1)], }, + }; + uint8_t *disable_channel_upds[MRC_CHANNELS] = { + &mem_cfg->DisableMc0Ch0, + &mem_cfg->DisableMc0Ch1, + &mem_cfg->DisableMc0Ch2, + &mem_cfg->DisableMc0Ch3, + &mem_cfg->DisableMc1Ch0, + &mem_cfg->DisableMc1Ch1, + &mem_cfg->DisableMc1Ch2, + &mem_cfg->DisableMc1Ch3, + }; + size_t ch, dimm; + + mem_cfg->MemorySpdDataLen = data->spd_len; + + for (ch = 0; ch < MRC_CHANNELS; ch++) { + uint8_t *disable_channel_ptr = disable_channel_upds[ch]; + bool enable_channel = false; + + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + uint64_t *spd_ptr = spd_upds[ch][dimm]; + + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) + enable_channel = true; + } + *disable_channel_ptr = !enable_channel; + } +} + +static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, + const struct mem_channel_data *data, bool auto_detect) +{ + for (size_t i = 0; i < MRC_CHANNELS; i++, map += upd_size) { + if (auto_detect || !channel_is_populated(i, MRC_CHANNELS, + data->ch_population_flags)) + memset(upds[i], 0, upd_size); + else + memcpy(upds[i], map, upd_size); + } +} + +static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); + void *dq_upds[MRC_CHANNELS] = { + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc1Ch0, + &mem_cfg->DqMapCpu2DramMc1Ch1, + &mem_cfg->DqMapCpu2DramMc1Ch2, + &mem_cfg->DqMapCpu2DramMc1Ch3, + }; + + _Static_assert(sizeof(mem_cfg->DqMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH, + "Incorrect DQ UPD size!"); + + mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect); +} + +static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); + void *dqs_upds[MRC_CHANNELS] = { + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc1Ch0, + &mem_cfg->DqsMapCpu2DramMc1Ch1, + &mem_cfg->DqsMapCpu2DramMc1Ch2, + &mem_cfg->DqsMapCpu2DramMc1Ch3, + }; + + _Static_assert(sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH / 8, + "Incorrect DQS UPD size!"); + + mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); +} + +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) +{ + struct mem_channel_data data; + bool dq_dqs_auto_detect = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + mem_cfg->ECT = mb_cfg->ect; + mem_cfg->UserBd = mb_cfg->user_bd; + set_rcomp_config(mem_cfg, mb_cfg); + + if (mb_cfg->type == MEM_TYPE_LP5X) + meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); + else + die("Unsupported memory type %d\n", mb_cfg->type); + + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, + half_populated, &data); + mem_init_spd_upds(mem_cfg, &data); + mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); + mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); +} diff --git a/src/soc/intel/novalake/p2sb.c b/src/soc/intel/novalake/p2sb.c new file mode 100644 index 00000000000..3b86bb07e80 --- /dev/null +++ b/src/soc/intel/novalake/p2sb.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = BIT(29) | BIT(28) | BIT(27) | BIT(26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = BIT(31) | BIT(30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/novalake/pcie_rp.c b/src/soc/intel/novalake/pcie_rp.c new file mode 100644 index 00000000000..edad696b7f7 --- /dev/null +++ b/src/soc/intel/novalake/pcie_rp.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 21 }, + { 0 } +}; + +static const struct pcie_rp_group nvlp_rp_groups[] = { + { .slot = PCI_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCI_DEV_SLOT_PCIE_2, .count = 6, .lcap_port_base = 1 }, + { 0 } +}; + + +const struct pcie_rp_group *get_pcie_rp_table(void) +{ + return nvlp_rp_groups; +} + +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + return PCIE_RP_PCH; +} + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + return -1; +} diff --git a/src/soc/intel/novalake/pmc.c b/src/soc/intel/novalake/pmc.c new file mode 100644 index 00000000000..f265903682c --- /dev/null +++ b/src/soc/intel/novalake/pmc.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMC_HID "INTC1026" + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + if (pmcbase == NULL) { + printk(BIOS_ERR, "PMC MMIO regs could not be retrieved.\n"); + return; + } + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void soc_pmc_enable(struct device *dev) +{ + const struct soc_intel_novalake_config *config = config_of_soc(); + + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + /* Add the fixed MMIO resource */ + mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); + + /* Add the fixed I/O resource */ + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_pmc_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_name_string("_HID", PMC_HID); + acpigen_write_name_string("_DDN", "Intel(R) Nova Lake IPC Controller"); + /* Hide the device so that Windows does not complain on missing driver */ + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + + /* + * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). + * The PMC gets 0xFE000000 - 0xFE00FFFF. + */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); + acpigen_write_resourcetemplate_footer(); + + /* Define IPC Write Method */ + if (CONFIG(PMC_IPC_ACPI_INTERFACE)) + pmc_ipc_acpi_fill_ssdt(); + + acpigen_pop_len(); /* PMC Device */ + acpigen_pop_len(); /* Scope */ + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) { + const struct soc_pmc_lpm nvl_pmc_lpm = { + .num_substates = 8, + .num_req_regs = 6, + .lpm_ipc_offset = 0x1000, + .req_reg_stride = 0x30, + .lpm_enable_mask = get_supported_lpm_mask(), + }; + + generate_acpi_power_engine_with_lpm(&nvl_pmc_lpm); + } + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static void soc_pmc_init(struct device *dev) +{ + /* + * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order + * to ensure the ordering does not break the assumptions that other + * drivers make about ACPI mode (e.g. Chrome EC). Since it disables + * ACPI mode, other drivers may take different actions based on this + * (e.g. Chrome EC will flush any pending hostevent bits). Because + * NVL has its PMC device available for device_operations, it can be + * done from the "ops->init" callback. + */ + pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); +} + +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); + +/* + * `pmc_final` function is native implementation of equivalent events performed by + * each FSP NotifyPhase() API invocations. + * + * + * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits) + * + * Perform the PMCON status bit clear operation from `.final` + * to cover any such chances where later boot stage requested a global + * reset and PMCON status bit remains set. + */ +static void pmc_final(struct device *dev) +{ + pmc_clear_pmcon_sts(); +} + +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .init = soc_pmc_init, + .enable = soc_pmc_enable, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = soc_pmc_fill_ssdt, +#endif + .scan_bus = scan_static_bus, + .final = pmc_final, +}; diff --git a/src/soc/intel/novalake/reset.c b/src/soc/intel/novalake/reset.c new file mode 100644 index 00000000000..3c13f6dfe56 --- /dev/null +++ b/src/soc/intel/novalake/reset.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (cse_request_global_reset() == CSE_TX_RX_SUCCESS) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} diff --git a/src/soc/intel/novalake/retimer.c b/src/soc/intel/novalake/retimer.c new file mode 100644 index 00000000000..fcea6f0259b --- /dev/null +++ b/src/soc/intel/novalake/retimer.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +int retimer_get_index_for_typec(uint8_t typec_port) +{ + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port0), + DEV_PTR(tcss_usb3_port1), +#if CONFIG_MAX_TCSS_PORTS > 2 + DEV_PTR(tcss_usb3_port2), +#endif +#if CONFIG_MAX_TCSS_PORTS > 3 + DEV_PTR(tcss_usb3_port2), +#endif + }; + + int max_port = ARRAY_SIZE(tcss_port_arr); + + for (int i = 0, ec_port = 0; i < max_port; i++) { + if (i == typec_port) { + printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, + ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + /* Code should not come here if typec_port input is correct */ + return -1; +} diff --git a/src/soc/intel/novalake/romstage/Makefile.mk b/src/soc/intel/novalake/romstage/Makefile.mk new file mode 100644 index 00000000000..999241c7383 --- /dev/null +++ b/src/soc/intel/novalake/romstage/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += systemagent.c +romstage-y += ux.c diff --git a/src/soc/intel/novalake/romstage/fsp_params.c b/src/soc/intel/novalake/romstage/fsp_params.c new file mode 100644 index 00000000000..48d692ed630 --- /dev/null +++ b/src/soc/intel/novalake/romstage/fsp_params.c @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ux.h" + +#define FSP_CLK_NOTUSED 0xff +#define FSP_CLK_LAN 0x70 +#define FSP_CLK_FREE_RUNNING 0x80 + +static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + const struct ddi_port_upds { + uint8_t *ddc; + uint8_t *hpd; + } ddi_port_upds[] = { + [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, + [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, + [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, + [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, + [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, + [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, + [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, + }; + m_cfg->InternalGraphics = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); + if (m_cfg->InternalGraphics) { + /* IGD is enabled, set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; + /* DP port config */ + m_cfg->DdiPortAConfig = config->ddi_port_A_config; + m_cfg->DdiPortBConfig = config->ddi_port_B_config; + for (size_t i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & + DDI_ENABLE_DDC); + *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & + DDI_ENABLE_HPD); + } + /* Enable memory bandwidth compression */ + m_cfg->MemoryBandwidthCompression = 1; + } else { + /* IGD is disabled, skip IGD init in FSP. */ + m_cfg->IgdDvmt50PreAlloc = 0; + /* DP port config */ + m_cfg->DdiPortAConfig = 0; + m_cfg->DdiPortBConfig = 0; + for (size_t i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = 0; + *ddi_port_upds[i].hpd = 0; + } + } +} + +static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->SaGv = config->sagv; + if (m_cfg->SaGv) { + /* + * Set SaGv work points after reviewing the power and performance impact + * with SaGv set to 1 (Enabled) and various work points between 0-3 being + * enabled. + */ + if (config->sagv_wp_bitmap) + m_cfg->SaGvWpMask = config->sagv_wp_bitmap; + else + m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; + + for (size_t i = 0; i < HOB_MAX_SAGV_POINTS; i++) { + m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; + m_cfg->SaGvGear[i] = config->sagv_gear[i]; + } + } + + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + + m_cfg->RMT = config->rmt; + m_cfg->MrcFastBoot = 1; + m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; + + /* TODO: Temporary workaround - remove once FSP enables WRT retrain correctly. */ + m_cfg->WRTRETRAIN = 0; +} + +static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + m_cfg->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + m_cfg->PrmrrSize = get_valid_prmrr_size(); + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->SmmRelocationEnable = 0; +} + +static void fill_tme_params(FSP_M_CONFIG *m_cfg) +{ + m_cfg->TmeEnable = get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported(); + if (!m_cfg->TmeEnable || acpi_is_wakeup_s3()) + return; + m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT); + if (m_cfg->GenerateNewTmeKey) { + uint32_t ram_top = get_ramtop_addr(); + if (!ram_top) { + printk(BIOS_WARNING, "Invalid exclusion range start address. " + "Full memory encryption is enabled.\n"); + return; + } + m_cfg->TmeExcludeBase = (ram_top - CACHE_TMP_RAMTOP); + m_cfg->TmeExcludeSize = CACHE_TMP_RAMTOP; + } +} + +static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->BiosGuard = 0; + fill_tme_params(m_cfg); +} + +static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +} + +static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* IPU */ + m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); +} + +static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 1; + + /* Skip MBP HOB */ + m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); + + m_cfg->SkipExtGfxScan = config->skip_ext_gfx_scan; + + m_cfg->DlvrRfiEnable = 1; +} + +static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); + if (m_cfg->PchHdaEnable) { + m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; + m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; + m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; + m_cfg->IDispInterfaceSelect = config->pch_hda_idisp_link_interface; + + for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) + m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; + m_cfg->PchHdaAudioLinkHdaEnable = 1; + } + + /* + * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP + * only to configure GPIO pads for audio. Mainboard is expected to + * perform all GPIO configuration in coreboot and hence these UPDs are + * set to 0 to skip FSP GPIO configuration for audio pads. + */ + memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + + /* + * Get HDA Subsystem Vendor ID and Device ID from devicetree + * and set it in FSPM UPD. + */ + const struct device_path path = { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_HDA }; + const struct device *dev = find_dev_path(pci_root_bus(), &path); + if (is_dev_enabled(dev) && dev->subsystem_vendor && dev->subsystem_device) + m_cfg->PchHdaSubSystemIds = dev->subsystem_vendor | (dev->subsystem_device << 16); +} + +static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, + const struct pcie_rp_config *cfg, size_t cfg_count) +{ + unsigned int clk_req_mapping = 0; + for (size_t i = 0; i < cfg_count; i++) { + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + continue; + } + if (!(en_mask & BIT(i))) + continue; + if (!cfg[i].flags && !cfg[i].clk_src && !cfg[i].clk_req) { + printk(BIOS_WARNING, "Missing root port clock structure definition\n"); + continue; + } + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n", + cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { + m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + clk_req_mapping |= 1 << cfg[i].clk_req; + } + + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; + } +} + +static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + for (size_t i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { + if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; + else + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; + m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; + } + + /* PCIE ports */ + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, + CONFIG_MAX_ROOT_PORTS); +} + +static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH); +} + +static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + /* Tcss USB */ + m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI); + + /* Enable TCSS port */ + for (size_t i = 0; i < CONFIG_MAX_TCSS_PORTS; i++) { + m_cfg->TcssCapPolicy[i] = config->tcss_cap_policy[i]; + m_cfg->Usb4v2Enable[i] = 0; + } +} + +static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[2] = IOCVTD_BASE_ADDRESS; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); +} + +static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); + + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) + return; + + if (is_devfn_enabled(PCI_DEVFN_NPK)) + m_cfg->PlatformDebugOption = HW_DEBUG_TRACEHUB_READY; + + switch (m_cfg->PlatformDebugOption) { + case HW_DEBUG_TRACEHUB_ACTIVE: + case HW_DEBUG_TRACEHUB_READY: + case HW_DEBUG_TRACEHUB_POWEROFF: + m_cfg->DciEn = 1; + break; + case HW_DEBUG_DISABLE: + m_cfg->DciEn = 0; + break; + } +} + +static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->TccActivationOffset = config->tcc_offset; + m_cfg->TccOffsetLock = 0; +} + +static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) { + if (!config->cep_enable[i]) + continue; + m_cfg->CepEnable[i] = config->cep_enable[i]; + if (config->enable_fast_vmode[i]) + m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; + } + + for (size_t i = 0; i < ARRAY_SIZE(config->tdc_mode); i++) { + m_cfg->TdcMode[i] = config->tdc_mode[i]; + m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i]; + } + + for (size_t i = 0; i < ARRAY_SIZE(config->ps1_threshold); i++) { + if (config->ps1_threshold[i]) + m_cfg->Ps1Threshold[i] = config->ps1_threshold[i]; + if (config->ps2_threshold[i]) + m_cfg->Ps2Threshold[i] = config->ps2_threshold[i]; + if (config->ps3_threshold[i]) + m_cfg->Ps3Threshold[i] = config->ps3_threshold[i]; + } +} + +#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) +void platform_display_early_shutdown_notification(void *arg) +{ + FSPM_UPD *mupd = arg; + ux_inform_user_of_poweroff_operation("low-battery shutdown", mupd); +} +#endif + +static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg, + const config_t *config) +{ + if (!config->enable_acoustic_noise_mitigation) + return; + + m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation; + m_cfg->PcoreHysteresisWindow = config->pcore_hysteresis_window_ms; + m_cfg->EcoreHysteresisWindow = config->ecore_hysteresis_window_ms; + + for (size_t i = 0; i < ARRAY_SIZE(config->disable_fast_pkgc_ramp); i++) { + m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i]; + m_cfg->SlowSlewRate[i] = config->slow_slew_rate_config[i]; + } +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, const config_t *config) = { + fill_fspm_igd_params, + fill_fspm_mrc_params, + fill_fspm_cpu_params, + fill_fspm_security_params, + fill_fspm_uart_params, + fill_fspm_ipu_params, + fill_fspm_misc_params, + fill_fspm_audio_params, + fill_fspm_pcie_rp_params, + fill_fspm_ish_params, + fill_fspm_tcss_params, + fill_fspm_vtd_params, + fill_fspm_trace_params, + fill_fspm_thermal_params, + fill_fspm_vr_config_params, + fill_fspm_acoustic_params, + }; + + for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) + fill_fspm_params[i](m_cfg, config); +} + +static void fsp_set_debug_level(FSP_M_CONFIG *m_cfg, + enum fsp_log_level fsp_pcd_log_level, + enum fsp_log_level fsp_mrc_log_level) +{ + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = fsp_pcd_log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = fsp_mrc_log_level; +} + +static void fsp_control_log_level(FSPM_UPD *mupd, bool is_enabled) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; + + enum fsp_log_level fsp_log_level = is_enabled ? fsp_get_pcd_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + enum fsp_log_level mrc_log_level = is_enabled ? fsp_get_mrc_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + + fsp_set_debug_level(m_cfg, fsp_log_level, mrc_log_level); + + if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) || + (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) { + printk(BIOS_ERR, "Invalid FSP log level\n"); + return; + } + + /* Set Event Handler if log-level is non-zero */ + if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel) { + arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); + /* Override SerialIo Uart default MMIO resource if log-level is non-zero */ + m_cfg->SerialIoUartDebugMmioBase = UART_BASE(CONFIG_UART_FOR_CONSOLE); + } +} + +static void fill_fsp_event_handler(FSPM_UPD *mupd) +{ + fsp_control_log_level(mupd, CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)); +} + +static void fill_fspm_sign_of_life(FSPM_UPD *mupd) +{ + FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; + + if (arch_upd->NvsBufferPtr) + return; + + /* + * To enhance the user experience, let's display on-screen guidance + * during memory training, acknowledging that the process may require + * patience. + */ + printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); + ux_inform_user_of_update_operation("memory training", mupd); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) + fill_fsp_event_handler(mupd); + + soc_memory_init_params(&mupd->FspmConfig, config); + + if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE)) + fill_fspm_sign_of_life(mupd); + + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/novalake/romstage/romstage.c b/src/soc/intel/novalake/romstage/romstage.c new file mode 100644 index 00000000000..fa4d941b2d0 --- /dev/null +++ b/src/soc/intel/novalake/romstage/romstage.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void platform_fill_dimm_info_args(const DIMM_INFO *src_dimm, + const MEMORY_INFO_DATA_HOB *meminfo_hob, + struct dimm_fill_args *args) +{ + args->data_width = src_dimm->DataWidth; + args->mfg_id_arg = src_dimm->MfgId.Data; +} + +void mainboard_romstage_entry(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + /* Initialize HECI interface */ + cse_init(HECI1_BASE_ADDRESS); + + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + cse_fill_bp_info(); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE)) + cse_fw_sync(); + } + + /* Update coreboot timestamp table with CSE timestamps */ + if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) + cse_get_telemetry_data(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); + + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. + */ + pch_thermal_configuration(); + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + fsp_save_dimm_info(); +} diff --git a/src/soc/intel/novalake/romstage/systemagent.c b/src/soc/intel/novalake/romstage/systemagent.c new file mode 100644 index 00000000000..951f92083e8 --- /dev/null +++ b/src/soc/intel/novalake/romstage/systemagent.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { SAFBAR, SAF_BASE_ADDRESS, SAF_BASE_SIZE, "SAFBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/novalake/romstage/ux.c b/src/soc/intel/novalake/romstage/ux.c new file mode 100644 index 00000000000..8f5e4b25d24 --- /dev/null +++ b/src/soc/intel/novalake/romstage/ux.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: b/509920220 - Consolidate this file with src/soc/intel/pantherlake/romstage/ux.c + * as they are currently identical. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ux.h" + +#if CONFIG(FSP_VGA_MODE12) +void soc_set_vga_mode12_buffer(FSPM_UPD *fspm_upd, uintptr_t buffer) +{ + fspm_upd->FspmConfig.VgaGraphicsMode12ImagePtr = buffer; +} +#endif + +static void setup_vga_mode12_params(FSP_M_CONFIG *m_cfg, enum ux_locale_msg id) +{ + struct soc_intel_common_config *common_config = chip_get_common_soc_structure(); + unsigned char *vga_bitmap_buffer = (unsigned char *)(uintptr_t)m_cfg->VgaGraphicsMode12ImagePtr; + enum lb_fb_orientation current_orientation = common_config->panel_orientation; + if (!vga_bitmap_buffer) { + return; + } + int img_width = VGA12_WIDTH; + int img_height = VGA12_HEIGHT; + if (!m_cfg->LidStatus) + current_orientation = LB_FB_ORIENTATION_NORMAL; + render_text_to_bitmap_buffer(vga_bitmap_buffer, + current_orientation, + ux_locales_get_text(id), + &img_width, &img_height); + int img_size = img_width * img_height / 8; /* Image is a bitmap */ + /* Duplicate the first plane data to all other planes */ + for (int i = 1; i < CONFIG_FSP_VGA_MODE12_BPP; i++) + memcpy(vga_bitmap_buffer + (i * img_size), + vga_bitmap_buffer, + img_size); + + m_cfg->LogoPixelHeight = img_height; + m_cfg->LogoPixelWidth = img_width; + m_cfg->LogoXPosition = (VGA12_WIDTH - img_width) / 2; + m_cfg->LogoYPosition = (VGA12_HEIGHT - img_height) / 2; + m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12; + if (CONFIG(FSP_VGA_MODE12_MONOCHROME)) + m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12_MONOCHROME; +} + +static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id, + FSPM_UPD *mupd) +{ + const config_t *config = config_of_soc(); + timestamp_add_now(TS_ESOL_START); + + if (!CONFIG(CHROMEOS_ENABLE_ESOL)) { + timestamp_add_now(TS_ESOL_END); + return false; + } + + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *vbt; + size_t vbt_size; + static bool ux_done = false; + + /* + * Prevents multiple VGA text messages from being rendered during the boot process. + * + * This function is designed to be called only once. Subsequent calls are intentionally + * ignored to avoid overwriting previously displayed messages. For example, if a + * low-battery shutdown notification is scheduled, a later call with a firmware + * update notification could result in the low-battery message being lost. + */ + if (ux_done) { + timestamp_add_now(TS_ESOL_END); + return true; + } + + printk(BIOS_INFO, "Informing user on-display of %s.\n", name); + + vbt = cbfs_map("vbt.bin", &vbt_size); + if (!vbt) { + printk(BIOS_ERR, "Could not load vbt.bin\n"); + return false; + } + + m_cfg->VgaInitControl = VGA_INIT_CONTROL_ENABLE; + if (config->disable_progress_bar) + m_cfg->VgaInitControl |= VGA_INIT_DISABLE_ANIMATION; + m_cfg->VbtPtr = (efi_uintn_t)vbt; + m_cfg->VbtSize = vbt_size; + m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(id); + + if (CONFIG(FSP_VGA_MODE12)) + setup_vga_mode12_params(m_cfg, id); + + ux_done = true; + + timestamp_add_now(TS_ESOL_END); + return true; +} + +bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd) +{ + return ux_inform_user_of_operation(name, UX_LOCALE_MSG_MEMORY_TRAINING, mupd); +} + +bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd) +{ + return ux_inform_user_of_operation(name, UX_LOCALE_MSG_LOW_BATTERY, mupd); +} diff --git a/src/soc/intel/novalake/romstage/ux.h b/src/soc/intel/novalake/romstage/ux.h new file mode 100644 index 00000000000..e3aa31799f4 --- /dev/null +++ b/src/soc/intel/novalake/romstage/ux.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: b/509920220 - Consolidate this file with src/soc/intel/pantherlake/romstage/ux.h + * as they are currently identical. */ + +#ifndef _SOC_INTEL_NOVALAKE_ROMSTAGE_UX_H_ +#define _SOC_INTEL_NOVALAKE_ROMSTAGE_UX_H_ + +#include + +bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd); +bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd); + +/* VGA initialization configuration */ +#define VGA_INIT_CONTROL_ENABLE BIT(0) +#define VGA_INIT_CONTROL_MODE12 BIT(1) +#define VGA_INIT_DISABLE_ANIMATION BIT(4) +#define VGA_INIT_CONTROL_MODE12_MONOCHROME BIT(5) + +#endif /* _SOC_INTEL_NOVALAKE_ROMSTAGE_UX_H_ */ diff --git a/src/soc/intel/novalake/systemagent.c b/src/soc/intel/novalake/systemagent.c new file mode 100644 index 00000000000..486fa93f0b1 --- /dev/null +++ b/src/soc/intel/novalake/systemagent.c @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { SAFBAR, SAF_BASE_ADDRESS, SAF_BASE_SIZE, "SAFBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + /* First field (sa_mmio_descriptor.index) is not used, setting to 0: */ + { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" }, + { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" }, + { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" }, + { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); +} + +/* + * Set MMIO resource's fields + */ +static void set_mmio_resource( + struct sa_mmio_descriptor *resource, + uint64_t base, + uint64_t size, + const char *description) +{ + if (resource == NULL) { + printk(BIOS_ERR, "%s: argument resource is NULL for %s\n", + __func__, description); + return; + } + resource->base = base; + resource->size = size; + resource->description = description; +} + +int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, + uint64_t *prmrr_mask) +{ + msr_t msr; + msr = rdmsr(MSR_PRMRR_BASE_0); + *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; + msr = rdmsr(MSR_PRMRR_PHYS_MASK); + *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; + return 0; +} + +/* + * SoC implementation + * + * Add all known configurable memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt) +{ + uint64_t size, base, tseg_base; + int count = 0; + struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */ + + /* MMCONF */ + size = sa_get_mmcfg_size(); + if (size > 0) + set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS, + size, "MMCONF"); + + /* DSM */ + size = sa_get_dsm_size(); + if (size > 0) { + base = pci_read_config32(dev, BDSM) & 0xFFF00000; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM"); + } + + /* TSEG */ + size = CONFIG_SMM_TSEG_SIZE; + tseg_base = sa_get_tseg_base(); + if (size > 0) + set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG"); + + /* PMRR */ + size = get_valid_prmrr_size(); + if (size > 0) { + uint64_t mask; + if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) { + base &= mask; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR"); + } else { + printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n"); + } + } + + /* GSM */ + size = sa_get_gsm_size(); + if (size > 0) { + base = sa_get_gsm_base(); + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM"); + } + + /* DPR */ + size = sa_get_dpr_size(); + if (size > 0) { + /* DPR just below TSEG: */ + base = tseg_base - size; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR"); + } + + /* Add all the above */ + sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count); +} + +union pcode_mailbox_command { + struct { + uint32_t command: 8; + uint32_t param1: 8; + uint32_t param2: 13; + uint32_t reserved: 2; + /* + * Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is + * ready. pcode will clear this bit after the message is + * consumed. + */ + uint32_t runbusy: 1; + } fields; + uint32_t data; +}; + +union pcode_scaling_factor { + struct { + /* Core scaling factor */ + uint32_t scaling_factor: 16; + /* + * Number of modules with consecutive module id sharing the same scaling + * factor + */ + uint32_t num_equivalent_module: 8; + uint32_t reserved: 8; + } fields; + uint32_t data; +}; + +#define MAILBOX_WAIT_TIMEOUT_US 1000 +#define PCODE_READ_CORE_SCALING_FACTOR_CMD 0x21 + +static bool poll_mailbox_ready(void) +{ + union pcode_mailbox_command cmd; + size_t i; + + for (i = 0; i < MAILBOX_WAIT_TIMEOUT_US; i++) { + cmd.data = MCHBAR32(PCODE_MAILBOX_INTERFACE); + if (!cmd.fields.runbusy) + return true; + udelay(1); + } + return false; +} + +static u16 u88_to_scaling_factor(u16 u88) +{ + unsigned int tmp = (u88 & 0xff) * 100; + unsigned int fraction = tmp / (1 << 8); + + /* Rounding */ + if (((tmp & 0xff) << 1) >= (1 << 8)) + fraction++; + return ((u88 >> 8) * 100) + fraction; +} + +/* + * The following function sends commands to the pcode mailbox interface to read the core scaling + * factors for performance and efficient cores. + * + * The READ_CORE_SCALING_FACTOR command takes a module ID as a parameter. The function iterates + * over all the CPU devices to identify module IDs of different core types (efficient and + * performance). + * + * If no efficient cores are present, no efficient factor is returned. + * + * Return values: + * - CB_ERR_ARG: If any of the input pointers were NULL. + * - CB_ERR: If there was a generic error while reading the scaling factors. + * - CB_SUCCESS: If the scaling factors were read successfully. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient) +{ + extern struct cpu_info cpu_infos[]; + union pcode_mailbox_command cmd = { + .fields = { + .command = PCODE_READ_CORE_SCALING_FACTOR_CMD, + .runbusy = 1 + } + }; + union pcode_scaling_factor res; + bool has_efficient_core = false; + + if (!performance || !efficient) + return CB_ERR_ARG; + + for (size_t i = 0; i < CONFIG_MAX_CPUS; i++) { + struct device *cpu = cpu_infos[i].cpu; + + if (!cpu) + continue; + + if (cpu->path.apic.core_type != CPU_TYPE_PERF) + has_efficient_core = true; + + if (cpu->path.apic.core_type == CPU_TYPE_PERF && *performance) + continue; + + cmd.fields.param1 = cpu->path.apic.module_id; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode mailbox is busy\n"); + return CB_ERR; + } + + MCHBAR32(PCODE_MAILBOX_INTERFACE) = cmd.data; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode command mailbox not completing in time\n"); + return CB_ERR; + } + + res.data = MCHBAR32(PCODE_MAILBOX_DATA); + + if (cpu->path.apic.core_type == CPU_TYPE_PERF) + *performance = u88_to_scaling_factor(res.fields.scaling_factor); + else + *efficient = u88_to_scaling_factor(res.fields.scaling_factor); + + if (*performance && *efficient) + break; + } + + if (!*performance) { + printk(BIOS_ERR, "Could not read performance scaling factor\n"); + return CB_ERR; + } + if (has_efficient_core && !*efficient) { + printk(BIOS_ERR, "Could not read efficient scaling factor\n"); + return CB_ERR; + } + return CB_SUCCESS; +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); +} + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 65536; + } +} diff --git a/src/soc/intel/novalake/tcss.c b/src/soc/intel/novalake/tcss.c new file mode 100644 index 00000000000..1b7a34acc9b --- /dev/null +++ b/src/soc/intel/novalake/tcss.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static bool soc_tcss_valid_tbt_auth(void) +{ + const config_t *config = config_of_soc(); + return config->tbt_authentication; +} + +const struct soc_tcss_ops tcss_ops = { + .configure_aux_bias_pads = NULL, + .valid_tbt_auth = soc_tcss_valid_tbt_auth, +}; diff --git a/src/soc/intel/novalake/touch.c b/src/soc/intel/novalake/touch.c new file mode 100644 index 00000000000..8aba299571e --- /dev/null +++ b/src/soc/intel/novalake/touch.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Convert I2C speed into value for the register in SoC */ +static uint64_t get_soc_thc_i2c_bus_freq_val(enum i2c_speed speed) +{ + switch (speed) { + case I2C_SPEED_FAST_PLUS: + return SOC_NVL_THC_I2C_CONNECTION_SPEED_FMP; + case I2C_SPEED_FAST: + return SOC_NVL_THC_I2C_CONNECTION_SPEED_FM; + case I2C_SPEED_STANDARD: + return SOC_NVL_THC_I2C_CONNECTION_SPEED_SM; + default: + die("Fail to map %d Hz to proper I2C speed.\n", speed); + } +} + +/* SoC-specific THC-I2C config */ +const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void) +{ + static const struct intel_thc_hidi2c_info soc_thc_hidi2c_info = { + .connection_speed = I2C_SPEED_FAST, /* 400KHz */ + .get_soc_i2c_bus_speed_val_func = get_soc_thc_i2c_bus_freq_val, + .addr_mode = SOC_NVL_THC_I2C_ADDR_MODE, + .sm_scl_high_period = SOC_NVL_THC_I2C_SM_SCL_HIGH_PERIOD, + .sm_scl_low_period = SOC_NVL_THC_I2C_SM_SCL_LOW_PERIOD, + .sm_sda_hold_tx_period = SOC_NVL_THC_I2C_SM_SDA_HOLD_TX_PERIOD, + .sm_sda_hold_rx_period = SOC_NVL_THC_I2C_SM_SDA_HOLD_RX_PERIOD, + .fm_scl_high_period = SOC_NVL_THC_I2C_FM_SCL_HIGH_PERIOD, + .fm_scl_low_period = SOC_NVL_THC_I2C_FM_SCL_LOW_PERIOD, + .fm_sda_hold_tx_period = SOC_NVL_THC_I2C_FM_SDA_HOLD_TX_PERIOD, + .fm_sda_hold_rx_period = SOC_NVL_THC_I2C_FM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_s_f_fp = SOC_NVL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP, + .fmp_scl_high_period = SOC_NVL_THC_I2C_FMP_SCL_HIGH_PERIOD, + .fmp_scl_low_period = SOC_NVL_THC_I2C_FMP_SCL_LOW_PERIOD, + .fmp_sda_hold_tx_period = SOC_NVL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD, + .fmp_sda_hold_rx_period = SOC_NVL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD, + .hm_scl_high_period = SOC_NVL_THC_I2C_HM_SCL_HIGH_PERIOD, + .hm_scl_low_period = SOC_NVL_THC_I2C_HM_SCL_LOW_PERIOD, + .hm_sda_hold_tx_period = SOC_NVL_THC_I2C_HM_SDA_HOLD_TX_PERIOD, + .hm_sda_hold_rx_period = SOC_NVL_THC_I2C_HM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_h_fp = SOC_NVL_THC_I2C_SUPPRESSED_SPIKES_H_FP, + }; + return &soc_thc_hidi2c_info; +} + +/* SoC-specific THC-SPI config */ +const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void) +{ + static const struct intel_thc_hidspi_info soc_thc_hidspi_info = { + .connection_speed = SOC_NVL_THC_SPI_CONNECTION_SPEED, + .write_mode = HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI, + .limit_packet_size = SOC_NVL_THC_HIDSPI_LIMIT_PKT_SZ, + .performance_limit = SOC_NVL_THC_PERFORMANCE_LIMIT, + .reset_sequencing_delay = SOC_NVL_THC_RST_SEQ_DLY, + }; + return &soc_thc_hidspi_info; +} diff --git a/src/soc/intel/novalake/xhci.c b/src/soc/intel/novalake/xhci.c new file mode 100644 index 00000000000..ed265d8251d --- /dev/null +++ b/src/soc/intel/novalake/xhci.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM CONFIG_SOC_INTEL_USB2_DEV_MAX +#define XHCI_USB3_PORT_NUM CONFIG_SOC_INTEL_USB3_DEV_MAX + +#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480 +#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490 +#define TCSS_XHCI_USB2_PORT_NUM 0 +#define TCSS_XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +static const struct xhci_usb_info tcss_usb_info = { + .usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev) +{ + if (xhci_dev == PCI_DEVFN_XHCI) + return &usb_info; + else if (xhci_dev == PCI_DEVFN_TCSS_XHCI) + return &tcss_usb_info; + + return NULL; +} diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 00616f14a57..2258ef31194 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -31,6 +31,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR if CHROMEOS_ENABLE_ESOL select HAVE_FSP_GOP select HAVE_HYPERTHREADING + select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT select HAVE_INTEL_COMPLIANCE_TEST_MODE select HAVE_SMI_HANDLER select HAVE_X86_64_SUPPORT @@ -42,7 +43,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select INTEL_GMA_VERSION_2 select INTEL_KEYLOCKER select IOAPIC - select MICROCODE_BLOB_UNDISCLOSED + select MICROCODE_BLOB_UNDISCLOSED if !SOC_INTEL_PANTHERLAKE_U_H select MP_SERVICES_PPI_V2 select MRC_CACHE_USING_MRC_VERSION select MRC_SETTINGS_PROTECT @@ -64,6 +65,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CAR_ENHANCED_NEM select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU @@ -97,6 +99,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FEATURE + select SOC_INTEL_COMMON_FEATURE_CBFS_PRELOAD select SOC_INTEL_COMMON_FEATURE_ESPI select SOC_INTEL_COMMON_FEATURE_FINALIZE select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC @@ -127,7 +130,6 @@ config SOC_INTEL_PANTHERLAKE_BASE select UDK_202302_BINDING select USE_COREBOOT_FOR_BMP_RENDERING select USE_X86_64_SUPPORT - select X86_INIT_NEED_1_SIPI help Intel Pantherlake support. Mainboards should specify the SoC type using the `SOC_INTEL_PANTHERLAKE_*` options instead @@ -176,15 +178,6 @@ config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI -config CAR_ENHANCED_NEM - bool - default y if !INTEL_CAR_NEM - select INTEL_CAR_NEM_ENHANCED - select CAR_HAS_SF_MASKS - select COS_MAPPED_TO_MSB - select CAR_HAS_L3_PROTECTED_WAYS - select INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE - config MAX_CPUS int default 16 @@ -378,10 +371,22 @@ config CONSOLE_CBMEM_BUFFER_SIZE default 0x100000 if BUILDING_WITH_DEBUG_FSP default 0x40000 +config FSP_TYPE_IOT + bool + default n + help + This option allows to select FSP IOT type from 3rdparty/fsp repo + config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/wildcatlake" if SOC_INTEL_WILDCATLAKE - default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/" + default "src/vendorcode/intel/fsp/fsp2_0/wildcatlake" if !FSP_USE_REPO && SOC_INTEL_WILDCATLAKE + default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/" if !FSP_USE_REPO + default "3rdparty/fsp/PantherLakeFspBinPkg/IoT/PantherLake/Include/" if FSP_TYPE_IOT && SOC_INTEL_PANTHERLAKE + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/PantherLakeFspBinPkg/IoT/PantherLake/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_PANTHERLAKE # Override platform debug consent value: # 0: Disabled, diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index 24ef2e9d273..4f70045100e 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -6,6 +6,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +ifeq ($(CONFIG_SOC_INTEL_PANTHERLAKE_U_H),y) +cpu_microcode_bins += \ + 3rdparty/intel-microcode/intel-ucode/06-cc-02 \ + 3rdparty/intel-microcode/intel-ucode/06-cc-03 +endif + # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gpio.c all-y += isclk.c @@ -20,7 +26,6 @@ romstage-y += pcie_rp.c romstage-y += tdp.c ramstage-y += acpi.c -ramstage-y += cbfs_preload.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c @@ -43,4 +48,10 @@ smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/pantherlake CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include +# FSP repo is missing some PTL headers, so add the vendorcode headers as a +# fallback. See: https://github.com/intel/FSP/issues/129 +ifeq ($(CONFIG_FSP_TYPE_IOT),y) +CPPFLAGS_common += -idirafter $(top)/src/vendorcode/intel/fsp/fsp2_0/pantherlake +endif + endif diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index 70d644ff527..d5320c58f5c 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -157,6 +157,9 @@ static struct { { PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_4, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_PTL_H_GT2_5, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_PTL_H_GT2_6, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_PTL_H_GT2_7, "Pantherlake-H GT2" }, { PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" }, { PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" }, }; diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index f3058faf33d..5aae0193901 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -529,6 +529,12 @@ struct soc_intel_pantherlake_config { /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ bool cnvi_bt_audio_offload; + /* UFS Inline Encryption Enable/Disable */ + bool ufs_inline_encryption; + + /* CNVi WWAN Coexistence Enable/Disable */ + bool cnvi_wwan_coex; + /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = BIT(0), @@ -767,6 +773,9 @@ struct soc_intel_pantherlake_config { CD_CLK_461MHZ, MAX_CD_CLOCK = CD_CLK_461MHZ } vga_cd_clk_freq_sel; + + /* Enable or Disable VCCSA Shutdown */ + bool vccsa_shutdown; }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c index 471608f21a9..dc5636c2fa8 100644 --- a/src/soc/intel/pantherlake/crashlog.c +++ b/src/soc/intel/pantherlake/crashlog.c @@ -111,6 +111,11 @@ void cl_get_pmc_sram_data(cl_node_t *head) if (!descriptor_table.regions[i].bits.size) continue; + if (descriptor_table.regions[i].bits.size * sizeof(u32) > pmc_crashLog_size) { + printk(BIOS_ERR, "Region size exceeds remaining crashlog size\n"); + goto pmc_send_re_arm_after_reset; + } + /* * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM * and IOE SRAM. We don't need to parse this as we already define BDFs in diff --git a/src/soc/intel/pantherlake/cse_telemetry.c b/src/soc/intel/pantherlake/cse_telemetry.c index 60faeb2b317..7ead0f28f34 100644 --- a/src/soc/intel/pantherlake/cse_telemetry.c +++ b/src/soc/intel/pantherlake/cse_telemetry.c @@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); - timestamp_add(TS_ESE_LOAD_AUNIT_END, + timestamp_add(TS_AUNIT_LOAD_END, start_stamp + ts[PERF_DATA_ESE_LOAD_AUNIT_COMPLETED]); } diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index e5fb8965137..494bfe987e4 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -289,13 +290,27 @@ static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_pantherlake_config *config) { - /* Load VBT before devicetree-specific config. */ - s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); + struct soc_intel_common_config *common_config; + bool lid_is_open; - /* Check if IGD is present and fill Graphics init param accordingly */ + /* Basic Graphics & VBT Configuration */ + s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); - s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); s_cfg->PavpEnable = CONFIG(PAVP); + + /* Determine LID Status */ + lid_is_open = CONFIG(VBOOT_LID_SWITCH) ? !!get_lid_switch() : !!CONFIG(RUN_FSP_GOP); + s_cfg->LidStatus = lid_is_open; + + /* + * Display Constraints + * Only restrict to a single display if the LID is open and the + * internal panel is in a non-standard (portrait) orientation. + */ + common_config = chip_get_common_soc_structure(); + if (common_config && lid_is_open && + (common_config->panel_orientation != LB_FB_ORIENTATION_NORMAL)) + s_cfg->MaxActiveDisplays = 1; } static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, @@ -518,6 +533,7 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, s_cfg->CnviWifiCore = config->cnvi_wifi_core; s_cfg->CnviBtCore = config->cnvi_bt_core; s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; + s_cfg->CnviWwanCoex = config->cnvi_wwan_coex; if (!s_cfg->CnviMode && s_cfg->CnviWifiCore) { printk(BIOS_ERR, "CNVi WiFi is enabled without CNVi being enabled\n"); @@ -532,6 +548,10 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, s_cfg->CnviBtCore = 0; s_cfg->CnviBtAudioOffload = 0; } + if (!s_cfg->CnviMode && s_cfg->CnviWwanCoex) { + printk(BIOS_ERR, "CNVi WWAN Coex enabled without CNVi being enabled\n"); + s_cfg->CnviWwanCoex = 0; + } s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1; } @@ -713,6 +733,9 @@ static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg, /* Setting FSP UPD (1,0) to enable controller 0 */ s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS); s_cfg->UfsEnable[1] = 0; + s_cfg->UfsInlineEncryption[0] = is_devfn_enabled(PCI_DEVFN_UFS) + && config->ufs_inline_encryption; + s_cfg->UfsInlineEncryption[1] = 0; #else /* Setting FSP UPD (0,0) to keep both controllers disabled */ s_cfg->UfsEnable[0] = 0; diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h index 352df92b6ee..cd6c836f717 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -3,7 +3,7 @@ #ifndef _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ -#define INC(x) ((x) + 1) +#include /* * Most of the fixed numbers and macros are based on the GPP groups. diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h index d9506500ef3..890612faf23 100644 --- a/src/soc/intel/pantherlake/include/soc/meminit.h +++ b/src/soc/intel/pantherlake/include/soc/meminit.h @@ -100,9 +100,6 @@ struct mb_cfg { /* Board type */ uint8_t user_bd; - - /* Command Mirror */ - uint8_t cmd_mirror; }; void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 5e652da1874..2bc61ce4c4d 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -342,14 +342,21 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, if (!map) return; + for (size_t i = 0; i < ARRAY_SIZE(config->cep_enable); i++) { + if (config->cep_enable[i]) + m_cfg->CepEnable[i] = config->cep_enable[i]; + } + + /* + * Only enable Fast Vmode when a valid IccLimit threshold exists + */ for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) { - if (!config->cep_enable[i]) + if (!config->enable_fast_vmode[i]) continue; - m_cfg->CepEnable[i] = config->cep_enable[i]; - if (config->enable_fast_vmode[i]) { - m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; - m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->sku][i]; - } + if (!config->fast_vmode_i_trip[map->sku][i]) + continue; + m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; + m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->sku][i]; } for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) { @@ -380,6 +387,8 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, if (config->ps3_threshold[i]) m_cfg->Ps3Threshold[i] = config->ps3_threshold[i]; } + + m_cfg->VccsaShutdown = config->vccsa_shutdown; } #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e0d2c4d2220..c76239936a3 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_INTEL_OC_MAILBOX select DRAM_SUPPORT_DDR3 select DRAM_SUPPORT_DDR4 select DRIVERS_USB_ACPI diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index df00bb85a98..797abd6e84d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 964c1264aa7..2d58e2b42a7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -396,7 +397,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); + tconfig->PchSbAccessUnlock = soc_disable_heci1_at_pre_boot(); const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; tconfig->PchLockDownBiosInterface = lockdown_by_fsp; diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index dfb81d496ec..31b625ca26d 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -4,9 +4,9 @@ chip soc/intel/skylake ops pci_domain_ops device gpio 0 alias pch_gpio on ops block_gpio_ops end device pci 00.0 alias system_agent on ops systemagent_ops end - device pci 01.0 alias peg0 off end - device pci 01.1 alias peg1 off end - device pci 01.2 alias peg2 off end + device pci 01.0 alias peg0 off ops pcie_rp_ops end + device pci 01.1 alias peg1 off ops pcie_rp_ops end + device pci 01.2 alias peg2 off ops pcie_rp_ops end device pci 02.0 alias igpu off ops graphics_ops end device pci 04.0 alias sa_thermal off end device pci 05.0 alias imgu off end # Imaging Unit diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index fd80aeac1a0..a6a451364de 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -59,8 +59,7 @@ static void pch_finalize_script(struct device *dev) */ pch_thermal_configuration(); - /* we should disable Heci1 based on the config */ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); /* Hide p2sb device as the OS must not change BAR0. */ diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 8a9ec813cd6..4d8997b07dd 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index e91719f00ca..6b6cdfb349e 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 3708f057fc4..20772f73e7c 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,9 @@ void soc_systemagent_init(struct device *dev) config = config_of_soc(); soc_config = &config->power_limits_config; set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + + /* Apply OC mailbox settings (e.g. undervolt) after power limits. */ + program_oc_mailbox(); } int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, diff --git a/src/soc/intel/snowridge/chip.h b/src/soc/intel/snowridge/chip.h index 27d792a7beb..81e17b87ac3 100644 --- a/src/soc/intel/snowridge/chip.h +++ b/src/soc/intel/snowridge/chip.h @@ -14,7 +14,7 @@ #define MAX_DOMAIN (BL_MAX_SOCKET * BL_MAX_LOGIC_IIO_STACK + 2) struct snr_domain { - uint8_t enabled; + bool enabled; uint8_t personality; uint8_t bus_base; uint8_t bus_limit; @@ -31,7 +31,7 @@ struct soc_intel_snowridge_config { struct soc_intel_common_config common_soc_config; uint32_t tcc_offset; /**< Needed by `common/block/cpulib.c`. */ - uint8_t eist_enable; + bool eist_enable; struct snr_domain domain[MAX_DOMAIN]; }; diff --git a/src/soc/intel/snowridge/chipset.cb b/src/soc/intel/snowridge/chipset.cb index 7632b33eacb..9b2d872e7bd 100644 --- a/src/soc/intel/snowridge/chipset.cb +++ b/src/soc/intel/snowridge/chipset.cb @@ -7,7 +7,7 @@ chip soc/intel/snowridge }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" device cpu_cluster 0 alias cpu_bus on end diff --git a/src/soc/intel/snowridge/romstage/romstage.c b/src/soc/intel/snowridge/romstage/romstage.c index d615da6e925..23615aa61a6 100644 --- a/src/soc/intel/snowridge/romstage/romstage.c +++ b/src/soc/intel/snowridge/romstage/romstage.c @@ -5,8 +5,6 @@ #include #include #include -#include -#include #include #include #include @@ -16,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/snowridge/sata.c b/src/soc/intel/snowridge/sata.c index bdd881d996f..824fdd5e715 100644 --- a/src/soc/intel/snowridge/sata.c +++ b/src/soc/intel/snowridge/sata.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 19fa050da41..0aa56da87d5 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -49,4 +49,6 @@ #include /* GbE 0:1f.6 */ +#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION) #include +#endif diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 725f8296a3b..18c5dee0221 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -7,7 +7,7 @@ chip soc/intel/tigerlake device pci 02.0 alias igpu off end device pci 04.0 alias dptf off end device pci 05.0 alias ipu off end - device pci 06.0 alias peg off end + device pci 06.0 alias peg off ops pcie_rp_ops end device pci 07.0 alias tbt_pcie_rp0 off chip soc/intel/common/block/usb4 use tbt_dma0 as usb4_port diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb index 28adb940e4f..a5f4706c4d3 100644 --- a/src/soc/intel/tigerlake/chipset_pch_h.cb +++ b/src/soc/intel/tigerlake/chipset_pch_h.cb @@ -3,13 +3,13 @@ chip soc/intel/tigerlake device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end - device pci 01.0 alias peg1 off end - device pci 01.1 alias peg2 off end - device pci 01.2 alias peg3 off end + device pci 01.0 alias peg1 off ops pcie_rp_ops end + device pci 01.1 alias peg2 off ops pcie_rp_ops end + device pci 01.2 alias peg3 off ops pcie_rp_ops end device pci 02.0 alias igpu off end device pci 04.0 alias dptf off end device pci 05.0 alias ipu off end - device pci 06.0 alias peg0 off end + device pci 06.0 alias peg0 off ops pcie_rp_ops end device pci 07.0 alias tbt_pcie_rp0 off chip soc/intel/common/block/usb4 use tbt_dma0 as usb4_port diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index cd02745a9e6..63a46ac02e8 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -57,7 +57,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); tbt_finalize(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (soc_disable_heci1_at_pre_boot()) heci1_disable(); /* Indicate finalize step with post code */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 35562d1a697..4102f724200 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 6f8c5eb9e66..42e48cc0904 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -227,8 +227,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = !!config->ibecc.enable; + if (get_uint_option("ibecc_enable", config->ibecc.enable)) { + m_cfg->Ibecc = true; m_cfg->IbeccParity = !!config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) { diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 808a0db266d..cd26290c5a8 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -32,6 +32,7 @@ /* Bus: B0, Device: 8, Function: 1 */ #define SMM_FEATURE_CONTROL 0x7c #define SMM_CODE_CHK_EN BIT(2) +#define SMM_FC_CPU_SAVE_EN BIT(1) #define SMM_FEATURE_CONTROL_LOCK BIT(0) #define UBOX_DFX_DEVID 0x2015 diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h index bddca8a111e..88a82a62f19 100644 --- a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h @@ -26,6 +26,7 @@ /* UBOX Registers [U(1), D:0, F:1] */ #define SMM_FEATURE_CONTROL 0x8c #define SMM_CODE_CHK_EN BIT(2) +#define SMM_FC_CPU_SAVE_EN BIT(1) #define SMM_FEATURE_CONTROL_LOCK BIT(0) #define UBOX_DFX_DEVID 0x3251 diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 8ce49818e94..9088502248d 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5f480d6ea8e..60a4dc51a9c 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index 6a784e0d12f..951442fbf02 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index b6414ad62fb..0218536b4f1 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -33,6 +33,7 @@ /* Bus: B0, Device: 8, Function: 1 */ #define SMM_FEATURE_CONTROL 0x7c #define SMM_CODE_CHK_EN BIT(2) +#define SMM_FC_CPU_SAVE_EN BIT(1) #define SMM_FEATURE_CONTROL_LOCK BIT(0) #define UBOX_DFX_DEVID 0x2015 diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 0825260ac5e..d83c3fc5a47 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -11,6 +11,7 @@ /* UBOX Registers [U(1), D:0, F:1] */ #define SMM_FEATURE_CONTROL 0x8c #define SMM_CODE_CHK_EN BIT(2) +#define SMM_FC_CPU_SAVE_EN BIT(1) #define SMM_FEATURE_CONTROL_LOCK BIT(0) #define UBOX_DFX_DEVID 0x3251 diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index c52f8ed407d..20f772c1756 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -54,6 +54,13 @@ config MEDIATEK_DRAM_SCRAMBLE This option enables DRAM data scramble, which can prevent DRAM data from being hacked. +config MEDIATEK_DRAM_HIGH_FREQ + bool "Enable DRAM high frequency mode" + default n + help + This option enables DRAM high frequency mode to run DRAM at higher + operating frequencies for improved performance. + config MEDIATEK_DSI_CPHY bool default n diff --git a/src/soc/mediatek/common/clkbuf.c b/src/soc/mediatek/common/clkbuf.c index 60f53a77b0c..f79dfa60b9c 100644 --- a/src/soc/mediatek/common/clkbuf.c +++ b/src/soc/mediatek/common/clkbuf.c @@ -28,20 +28,20 @@ static struct pmif *pmif_arb; static u32 buf_read(u32 addr) { - u32 rdata; + u16 rdata; if (!pmif_arb) pmif_arb = get_pmif_controller(PMIF_SPI, 0); - pmif_arb->read(pmif_arb, 0, addr, &rdata); + pmif_arb->read16(pmif_arb, 0, addr, &rdata); - return rdata; + return (u32)rdata; } static void buf_write(u32 addr, u32 wdata) { if (!pmif_arb) pmif_arb = get_pmif_controller(PMIF_SPI, 0); - pmif_arb->write(pmif_arb, 0, addr, wdata); + pmif_arb->write16(pmif_arb, 0, addr, (u16)wdata); } static void dump_clkbuf_log(void) diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index d1fce217a69..39079f96c80 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -50,14 +51,15 @@ __weak int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid) return -1; } -__weak int mtk_edp_enable(struct mtk_dp *mtk_dp) +__weak int mtk_edp_enable(const struct mtk_dp *mtk_dp) { printk(BIOS_WARNING, "%s: Not supported\n", __func__); return -1; } __weak int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, - const struct edid *edid, const u8 *init_commands) + const struct edid *edid, const u8 *init_commands, + struct thread_mutex *ready_mutex) { printk(BIOS_WARNING, "%s: Not supported\n", __func__); return -1; @@ -100,9 +102,11 @@ static void display_logo(struct panel_description *panel, panel_configure_backlight(panel, true); timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED); + printk(BIOS_DEBUG, "Firmware Splash Screen: Enabled\n"); + elog_add_event_byte(ELOG_TYPE_FW_SPLASH_SCREEN, 1); } -int mtk_display_init(void) +int mtk_display_init(struct thread_mutex *ready_mutex) { struct edid edid = {0}; struct mtk_dp mtk_edp = {0}; @@ -176,7 +180,7 @@ int mtk_display_init(void) dsi_mode_flags = mipi_dsi_flags; if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, lanes, &edid, - mipi_data ? mipi_data->init : NULL) < 0) { + mipi_data ? mipi_data->init : NULL, ready_mutex) < 0) { printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); return -1; } diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c index 342f742a2c1..82d30b366df 100644 --- a/src/soc/mediatek/common/dp/dptx_common.c +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -13,8 +13,8 @@ #include #include -static bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, - size_t length, u8 *data) +static bool dptx_auxwrite_bytes(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, const u8 *data) { if (retry(7, dptx_hal_auxwrite_bytes(mtk_dp, cmd, dpcd_addr, length, data), mdelay(1))) @@ -26,8 +26,8 @@ static bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, return false; } -bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, - size_t length, u8 *data) +bool dptx_auxwrite_dpcd(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, const u8 *data) { bool ret = true; size_t offset = 0; @@ -42,7 +42,7 @@ bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, return ret; } -static bool dptx_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, +static bool dptx_auxread_bytes(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *data) { if (retry(7, dptx_hal_auxread_bytes(mtk_dp, cmd, dpcd_addr, length, data), @@ -55,7 +55,7 @@ static bool dptx_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, return false; } -bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, +bool dptx_auxread_dpcd(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rxbuf) { bool ret = true; @@ -202,7 +202,7 @@ bool dptx_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], return true; } -static void dptx_videomute(struct mtk_dp *mtk_dp, bool enable) +static void dptx_videomute(const struct mtk_dp *mtk_dp, bool enable) { dptx_hal_videomute(mtk_dp, enable); } @@ -239,7 +239,7 @@ static void dptx_fec_ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel) } } -void dptx_init_variable(struct mtk_dp *mtk_dp) +static void dptx_init_variable(struct mtk_dp *mtk_dp) { mtk_dp->regs = (void *)EDP_BASE; mtk_dp->phy_regs = (void *)EDP_PHY_BASE; @@ -267,7 +267,7 @@ static inline bool dptx_check_res_sample_rate(const struct edid *edid) return edid->mode.va + edid->mode.vbl <= 525; } -static void dptx_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 sram_read_start) +static void dptx_setsdp_downcnt_init(const struct mtk_dp *mtk_dp, u16 sram_read_start) { u32 count = 0; /* count: sdp_down_cnt_init */ u8 offset; @@ -299,7 +299,7 @@ static void dptx_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 sram_read_start) dptx_hal_setsdp_downcnt_init(mtk_dp, count); } -static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp) +static void dptx_setsdp_downcnt_init_inhblanking(const struct mtk_dp *mtk_dp) { int pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; u8 offset; @@ -330,7 +330,7 @@ static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp) dptx_hal_setsdp_downcnt_init_inhblanking(mtk_dp, count); } -static void dptx_set_tu(struct mtk_dp *mtk_dp) +static void dptx_set_tu(const struct mtk_dp *mtk_dp) { u8 bpp; u16 sram_read_start = DPTX_TBC_BUF_READSTARTADRTHRD; @@ -359,7 +359,7 @@ static void dptx_set_tu(struct mtk_dp *mtk_dp) dptx_setsdp_downcnt_init(mtk_dp, sram_read_start); } -static void dptx_set_misc(struct mtk_dp *mtk_dp) +static void dptx_set_misc(const struct mtk_dp *mtk_dp) { u8 format, depth; union misc_t dptx_misc = { .cmisc = {} }; @@ -401,7 +401,7 @@ static void dptx_set_misc(struct mtk_dp *mtk_dp) dptx_hal_setmisc(mtk_dp, dptx_misc.cmisc); } -static void dptx_set_dptxout(struct mtk_dp *mtk_dp) +static void dptx_set_dptxout(const struct mtk_dp *mtk_dp) { dptx_hal_bypassmsa_en(mtk_dp, false); dptx_set_tu(mtk_dp); @@ -485,7 +485,7 @@ static void dptx_check_sinkcap(struct mtk_dp *mtk_dp) stopwatch_duration_msecs(&sw)); } -void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable) +void dptx_video_enable(const struct mtk_dp *mtk_dp, bool enable) { printk(BIOS_INFO, "Output Video %s!\n", enable ? "enable" : "disable"); @@ -498,17 +498,17 @@ void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable) dptx_videomute(mtk_dp, true); } -static void dptx_set_color_format(struct mtk_dp *mtk_dp, u8 color_format) +static void dptx_set_color_format(const struct mtk_dp *mtk_dp, u8 color_format) { dptx_hal_set_color_format(mtk_dp, color_format); } -static void dptx_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) +static void dptx_set_color_depth(const struct mtk_dp *mtk_dp, u8 color_depth) { dptx_hal_set_color_depth(mtk_dp, color_depth); } -void dptx_video_config(struct mtk_dp *mtk_dp) +void dptx_video_config(const struct mtk_dp *mtk_dp) { u32 mvid = 0; bool overwrite = false; @@ -522,7 +522,7 @@ void dptx_video_config(struct mtk_dp *mtk_dp) dptx_set_color_format(mtk_dp, mtk_dp->info.format); } -static void dptx_init_port(struct mtk_dp *mtk_dp) +static void dptx_init_port(const struct mtk_dp *mtk_dp) { dptx_hal_phy_setidlepattern(mtk_dp, true); dptx_hal_init_setting(mtk_dp); @@ -575,7 +575,7 @@ int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid) return 0; } -int mtk_edp_enable(struct mtk_dp *mtk_dp) +int mtk_edp_enable(const struct mtk_dp *mtk_dp) { if (!mtk_dp) { printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__); diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 42208a14b23..f86c1cc348a 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -12,7 +12,7 @@ #define REG_OFFSET_LIMIT 0x8000 -u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) +u32 mtk_dp_read(const struct mtk_dp *mtk_dp, u32 offset) { void *addr = mtk_dp->regs + offset; @@ -21,7 +21,7 @@ u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) return read32(addr); } -void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +void mtk_dp_write(const struct mtk_dp *mtk_dp, u32 offset, u32 val) { void *addr = mtk_dp->regs + offset; @@ -31,7 +31,7 @@ void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) write32(addr, val); } -void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +void mtk_dp_mask(const struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) { void *addr = mtk_dp->regs + offset; @@ -42,7 +42,7 @@ void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) clrsetbits32(addr, mask, val); } -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) +void mtk_dp_write_byte(const struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) { if (addr % 2) { mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); @@ -55,7 +55,7 @@ void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); } -u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset) +u32 mtk_dp_phy_read(const struct mtk_dp *mtk_dp, u32 offset) { void *addr = mtk_dp->phy_regs + offset; @@ -65,7 +65,7 @@ u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset) return read32(addr); } -void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +void mtk_dp_phy_write(const struct mtk_dp *mtk_dp, u32 offset, u32 val) { void *addr = mtk_dp->phy_regs + offset; @@ -75,7 +75,7 @@ void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) write32(addr, val); } -void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +void mtk_dp_phy_mask(const struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) { void *addr = mtk_dp->phy_regs + offset; @@ -86,7 +86,7 @@ void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) clrsetbits32(addr, mask, val); } -void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) +void dptx_hal_verify_clock(const struct mtk_dp *mtk_dp) { u32 m, n, ls_clk, pix_clk; @@ -100,12 +100,12 @@ void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) pix_clk / 4); } -void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_bypassmsa_en(const struct mtk_dp *mtk_dp, bool enable) { mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, enable ? 0 : 0x3ff, 0x3ff); } -void dptx_hal_set_msa(struct mtk_dp *mtk_dp) +void dptx_hal_set_msa(const struct mtk_dp *mtk_dp) { u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal, val; struct edid *edid = mtk_dp->edid; @@ -166,7 +166,7 @@ void dptx_hal_set_msa(struct mtk_dp *mtk_dp) edid->mode.pixel_clock * 1000 / htotal / vtotal); } -void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) +void dptx_hal_set_color_depth(const struct mtk_dp *mtk_dp, u8 color_depth) { u8 val; @@ -194,13 +194,13 @@ void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); } -void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]) +void dptx_hal_setmisc(const struct mtk_dp *mtk_dp, u8 cmisc[2]) { mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe); mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff); } -void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, bool enable, u32 video_m, u32 video_n) +void dptx_hal_overwrite_mn(const struct mtk_dp *mtk_dp, bool enable, u32 video_m, u32 video_n) { if (enable) { /* Turn on overwrite MN */ @@ -219,7 +219,7 @@ void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, bool enable, u32 video_m, u32 } } -u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) +u8 dptx_hal_get_colorbpp(const struct mtk_dp *mtk_dp) { u8 color_bpp; u8 color_depth = mtk_dp->info.depth; @@ -275,7 +275,7 @@ u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) return color_bpp; } -void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) +void dptx_hal_settu_sramrd_start(const struct mtk_dp *mtk_dp, u16 value) { /* * [5:0] video sram start address @@ -284,17 +284,17 @@ void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f); } -void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) +void dptx_hal_setsdp_downcnt_init_inhblanking(const struct mtk_dp *mtk_dp, u16 value) { DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, value); } -void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) +void dptx_hal_setsdp_downcnt_init(const struct mtk_dp *mtk_dp, u16 value) { DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, value); } -bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, +bool dptx_hal_auxread_bytes(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rx_buf) { bool valid_cmd = false; @@ -357,15 +357,19 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t } reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; + if (wait_reply_count == 0x0 || reply_cmd != DP_AUX_NATIVE_REPLY_ACK) { + if (wait_reply_count == 0) + printk(BIOS_ERR, "AUX Read timeout\n"); + else if (reply_cmd == DP_AUX_NATIVE_REPLY_DEFER || + reply_cmd == DP_AUX_I2C_REPLY_DEFER) + printk(BIOS_DEBUG, "reply_cmd(%#x), Defer\n", reply_cmd); + else + printk(BIOS_ERR, "reply_cmd(%#x), NACK\n", reply_cmd); - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + u8 phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); if (phy_status != 0x1) - printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n"); + printk(BIOS_ERR, "AUX Read hanging, need SW reset\n"); mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, @@ -373,7 +377,6 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); mdelay(1); - printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n", wait_reply_count); return false; } @@ -406,8 +409,8 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t return valid_cmd; } -bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, - u8 *data) +bool dptx_hal_auxwrite_bytes(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, + const u8 *data) { bool valid_cmd = false; u8 reply_cmd; @@ -461,23 +464,24 @@ bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_ } reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; + if (wait_reply_count == 0x0 || reply_cmd != DP_AUX_NATIVE_REPLY_ACK) { + if (wait_reply_count == 0) + printk(BIOS_ERR, "AUX Write timeout\n"); + else if (reply_cmd == DP_AUX_NATIVE_REPLY_DEFER || + reply_cmd == DP_AUX_I2C_REPLY_DEFER) + printk(BIOS_DEBUG, "reply_cmd(%#x), Defer\n", reply_cmd); + else + printk(BIOS_ERR, "reply_cmd(%#x), NACK\n", reply_cmd); - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + u8 phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); if (phy_status != 0x1) - printk(BIOS_ERR, "Aux write: aux hang, need SW reset!\n"); + printk(BIOS_ERR, "AUX Write hanging, need SW reset\n"); DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); mdelay(1); - - printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n", reply_cmd, - wait_reply_count); return false; } @@ -493,14 +497,14 @@ bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_ return valid_cmd; } -void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_hpd_int_en(const struct mtk_dp *mtk_dp, bool enable) { /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0, enable ? 0 : GENMASK(7, 5), GENMASK(7, 5)); } -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, u8 value) +void dptx_hal_set_txtrainingpattern(const struct mtk_dp *mtk_dp, u8 value) { /* if Set TPS1. */ if (value == BIT(4)) @@ -509,13 +513,13 @@ void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, u8 value) mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1, value, GENMASK(7, 4)); } -void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_phy_setidlepattern(const struct mtk_dp *mtk_dp, bool enable) { mtk_dp_write_byte(mtk_dp, REG_3580_DP_TRANS_P0 + 1, enable ? 0xf : 0x0, 0xf); } -void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_set_ef_mode(const struct mtk_dp *mtk_dp, bool enable) { /* * [4]: REG_enhanced_frame_mode @@ -527,7 +531,7 @@ void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, 0, BIT(4)); } -void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_setscramble(const struct mtk_dp *mtk_dp, bool enable) { /* [0]: dp tx transmitter scramble enable. */ if (enable) @@ -536,7 +540,7 @@ void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, 0, BIT(0)); } -void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_videomute(const struct mtk_dp *mtk_dp, bool enable) { if (enable) { mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(3) | BIT(2), @@ -549,7 +553,7 @@ void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c)); } -void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_analog_power_en(const struct mtk_dp *mtk_dp, bool enable) { if (enable) { mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, 0, BIT(4)); @@ -564,4 +568,4 @@ void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) } } -__weak void dptx_hal_phy_init(struct mtk_dp *mtk_dp) { /* do nothing */ } +__weak void dptx_hal_phy_init(const struct mtk_dp *mtk_dp) { /* do nothing */ } diff --git a/src/soc/mediatek/common/dp/dptx_hal_v1.c b/src/soc/mediatek/common/dp/dptx_hal_v1.c index 1bf9b71bb45..68d053ba76f 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_v1.c +++ b/src/soc/mediatek/common/dp/dptx_hal_v1.c @@ -27,7 +27,7 @@ static const struct shift_mask volt_preemphasis[DPTX_LANE_MAX] = { [DPTX_LANE3] = { DP_TX3_PRE_EMPH_FLDMASK_POS, DP_TX3_PRE_EMPH_FLDMASK }, }; -void dptx_hal_init_setting(struct mtk_dp *mtk_dp) +void dptx_hal_init_setting(const struct mtk_dp *mtk_dp) { DP_WRITE1BYTE(mtk_dp, REG_342C_DP_TRANS_P0, 0x69); mtk_dp_mask(mtk_dp, REG_3540_DP_TRANS_P0, BIT(3), BIT(3)); @@ -36,7 +36,7 @@ void dptx_hal_init_setting(struct mtk_dp *mtk_dp) mtk_dp_mask(mtk_dp, DP_TX_TOP_IRQ_MASK, BIT(2), BIT(2)); } -void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format) +void dptx_hal_set_color_format(const struct mtk_dp *mtk_dp, u8 out_format) { /* MISC0 */ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, @@ -61,7 +61,7 @@ void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format) } } -void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) +void dptx_hal_settu_setencoder(const struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, BIT(7), BIT(7)); @@ -74,13 +74,13 @@ void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) DP_WRITE2BYTE(mtk_dp, REG_3368_DP_ENCODER1_P0, 0x1111); } -bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp) +bool dptx_hal_hpd_high(const struct mtk_dp *mtk_dp) { return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2); } -void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, - u8 *swing_value, u8 *preemphasis) +void dptx_hal_set_swing_preemphasis(const struct mtk_dp *mtk_dp, size_t lane_count, + const u8 *swing_value, const u8 *preemphasis) { assert(lane_count <= DPTX_LANE_MAX); @@ -96,7 +96,7 @@ void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, } } -void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) +void dptx_hal_reset_swing_preemphasis(const struct mtk_dp *mtk_dp) { int lane; @@ -108,7 +108,7 @@ void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) 0, volt_preemphasis[lane].mask); } -void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) +void dptx_hal_hpd_detect_setting(const struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0, 0x8, GENMASK(3, 0)); @@ -119,7 +119,7 @@ void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) DP_WRITE1BYTE(mtk_dp, REG_3430_DP_TRANS_P0, 0x2); } -void dptx_hal_phy_setting(struct mtk_dp *mtk_dp) +void dptx_hal_phy_setting(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, DP_TX_TOP_PWR_STATE, 0x3 << DP_PWR_STATE_FLDMASK_POS, DP_PWR_STATE_FLDMASK); @@ -154,7 +154,7 @@ void dptx_hal_phy_setting(struct mtk_dp *mtk_dp) mtk_dp_mask(mtk_dp, 0x3690, BIT(8), BIT(8)); } -void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_ssc_en(const struct mtk_dp *mtk_dp, bool enable) { mtk_dp_mask(mtk_dp, 0x2000, BIT(0), GENMASK(1, 0)); @@ -168,7 +168,7 @@ void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable) mdelay(1); } -void dptx_hal_aux_setting(struct mtk_dp *mtk_dp) +void dptx_hal_aux_setting(const struct mtk_dp *mtk_dp) { /* [12 : 8]: modify timeout threshold = 1595 */ mtk_dp_mask(mtk_dp, REG_360C_AUX_TX_P0, @@ -185,7 +185,7 @@ void dptx_hal_aux_setting(struct mtk_dp *mtk_dp) MTK_ATOP_EN_AUX_TX_P0_FLDMASK); } -void dptx_hal_digital_setting(struct mtk_dp *mtk_dp) +void dptx_hal_digital_setting(const struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK); @@ -204,21 +204,21 @@ void dptx_hal_digital_setting(struct mtk_dp *mtk_dp) mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, 0, BIT(1)); } -void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp) +void dptx_hal_digital_swreset(const struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_340C_DP_TRANS_P0 + 1, BIT(5), BIT(5)); mdelay(1); mtk_dp_write_byte(mtk_dp, REG_340C_DP_TRANS_P0 + 1, 0, BIT(5)); } -void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) +void dptx_hal_phyd_reset(const struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, 0x1038, 0, BIT(0)); mdelay(1); mtk_dp_write_byte(mtk_dp, 0x1038, BIT(0), BIT(0)); } -void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) +void dptx_hal_set_txlane(const struct mtk_dp *mtk_dp, u8 value) { if (value == 0) mtk_dp_write_byte(mtk_dp, REG_35F0_DP_TRANS_P0, @@ -237,7 +237,7 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) } } -void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value) +void dptx_hal_set_txrate(const struct mtk_dp *mtk_dp, u8 value) { /* Power off TPLL and lane */ mtk_dp_write(mtk_dp, 0x2000, 0x00000001); diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c index 4de941fa618..bf0ac710bd8 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_v2.c +++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c @@ -19,7 +19,7 @@ const int dptx_hal_driving_offset[] = { const int dptx_hal_driving_offset_size = ARRAY_SIZE(dptx_hal_driving_offset); -void dptx_hal_init_setting(struct mtk_dp *mtk_dp) +void dptx_hal_init_setting(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0)); @@ -45,7 +45,7 @@ void dptx_hal_init_setting(struct mtk_dp *mtk_dp) ENCODER_IRQ_MSK | TRANS_IRQ_MSK); } -void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format) +void dptx_hal_set_color_format(const struct mtk_dp *mtk_dp, u8 out_format) { u32 val; @@ -72,7 +72,7 @@ void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format) mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val << 12, 0x7 << 12); } -void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) +void dptx_hal_settu_setencoder(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, BIT(15), BIT(15)); DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020); @@ -81,13 +81,14 @@ void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x40 << 8, 0x70 << 8); } -bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp) +bool dptx_hal_hpd_high(const struct mtk_dp *mtk_dp) { return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15); } -void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, - u8 *swing_value, u8 *preemphasis) +void dptx_hal_set_swing_preemphasis(const struct mtk_dp *mtk_dp, size_t lane_count, + const u8 *swing_value, const u8 *preemphasis) + { assert(lane_count <= DPTX_LANE_MAX); @@ -101,13 +102,13 @@ void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, } } -void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) +void dptx_hal_hpd_detect_setting(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, REG_364C_AUX_TX_P0, HPD_INT_THD_FLDMASK_VAL << 4, HPD_INT_THD_FLDMASK); } -void dptx_hal_phy_init(struct mtk_dp *mtk_dp) +void dptx_hal_phy_init(const struct mtk_dp *mtk_dp) { mtk_dp_phy_mask(mtk_dp, IPMUX_CONTROL, 0 << EDPTX_DSI_PHYD_SEL_FLDMASK_POS, EDPTX_DSI_PHYD_SEL_FLDMASK); @@ -116,7 +117,7 @@ void dptx_hal_phy_init(struct mtk_dp *mtk_dp) dptx_hal_ssc_en(mtk_dp, false); } -void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value) +void dptx_hal_set_txrate(const struct mtk_dp *mtk_dp, u8 value) { printk(BIOS_INFO, "Link rate = 0x%x\n", value); switch (value) { @@ -138,7 +139,7 @@ void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value) } } -void dptx_hal_phy_setting(struct mtk_dp *mtk_dp) +void dptx_hal_phy_setting(const struct mtk_dp *mtk_dp) { u8 link_rate = mtk_dp->train_info.linkrate; u8 lane_count = mtk_dp->train_info.linklane_count; @@ -154,7 +155,7 @@ void dptx_hal_phy_setting(struct mtk_dp *mtk_dp) mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_PLL_CTL_1)); } -void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable) +void dptx_hal_ssc_en(const struct mtk_dp *mtk_dp, bool enable) { if (enable) { printk(BIOS_DEBUG, "[eDPTX] enable ssc\n"); @@ -169,7 +170,7 @@ void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable) mdelay(1); } -void dptx_hal_aux_setting(struct mtk_dp *mtk_dp) +void dptx_hal_aux_setting(const struct mtk_dp *mtk_dp) { /* Modify timeout threshold = 1595 [12 : 8] */ mtk_dp_mask(mtk_dp, REG_360C_AUX_TX_P0, 0x1D0C, 0x1FFF); @@ -201,7 +202,7 @@ void dptx_hal_aux_setting(struct mtk_dp *mtk_dp) XTAL_FREQ_DP_TX_AUX_366C_MASK); } -void dptx_hal_digital_setting(struct mtk_dp *mtk_dp) +void dptx_hal_digital_setting(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, VBID_VIDEO_MUTE_DP_ENC0_4P_MASK); mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, BS2BS_MODE_DP_ENC1_4P_VAL << 12, @@ -261,7 +262,7 @@ void dptx_hal_digital_setting(struct mtk_dp *mtk_dp) mdelay(1); } -void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp) +void dptx_hal_digital_swreset(const struct mtk_dp *mtk_dp) { printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0)); @@ -274,7 +275,7 @@ void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp) mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0)); } -void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp) +void dptx_hal_swing_emp_reset(const struct mtk_dp *mtk_dp) { mtk_dp_mask(mtk_dp, REG_2004_TOP_SWING_EMP, 0, DP_TX0_VOLT_SWING_MASK | DP_TX1_VOLT_SWING_MASK | DP_TX2_VOLT_SWING_MASK | @@ -282,7 +283,7 @@ void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp) DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK); } -static void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp) +static void dptx_hal_phy_wait_aux_ldo_ready(const struct mtk_dp *mtk_dp) { u32 mask = RGS_BG_CORE_EN_READY_MASK | RGS_AUX_LDO_EN_READY_MASK; @@ -293,7 +294,7 @@ static void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp) } } -void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) +void dptx_hal_set_txlane(const struct mtk_dp *mtk_dp, u8 value) { /* Turn off phy power before phy configure */ mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, PHY_PWR_STATE_OW_EN_DP_ENC_4P_3, @@ -313,7 +314,7 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2)); } -void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable) +void dptx_hal_phy_set_idle_pattern(const struct mtk_dp *mtk_dp, u8 lane_count, bool enable) { u32 val = 0x0; @@ -340,7 +341,7 @@ void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool en POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK); } -void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) +void dptx_hal_phyd_reset(const struct mtk_dp *mtk_dp) { mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0)); udelay(10); diff --git a/src/soc/mediatek/common/dp/dptx_v1.c b/src/soc/mediatek/common/dp/dptx_v1.c index 76a324a9bb5..d427dc66804 100644 --- a/src/soc/mediatek/common/dp/dptx_v1.c +++ b/src/soc/mediatek/common/dp/dptx_v1.c @@ -14,7 +14,7 @@ #include #include -static void dptx_training_checkswingpre(struct mtk_dp *mtk_dp, +static void dptx_training_checkswingpre(const struct mtk_dp *mtk_dp, u8 target_lane_count, const u8 *dpcp202_x, u8 *dpcp_buf) { @@ -349,7 +349,7 @@ static int dptx_trainingflow(struct mtk_dp *mtk_dp, return DPTX_PASS; } -static void dptx_training_changemode(struct mtk_dp *mtk_dp) +static void dptx_training_changemode(const struct mtk_dp *mtk_dp) { dptx_hal_phyd_reset(mtk_dp); dptx_hal_reset_swing_preemphasis(mtk_dp); diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c index 81cfa766819..013d720a775 100644 --- a/src/soc/mediatek/common/dp/dptx_v2.c +++ b/src/soc/mediatek/common/dp/dptx_v2.c @@ -13,7 +13,7 @@ #include #include -static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern) +static void mtk_edp_pattern(const struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern) { u8 aux_offset; @@ -49,7 +49,7 @@ static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern) dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &aux_offset); } -static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, +static void update_swing_preemphasis(const struct mtk_dp *mtk_dp, u8 lane_count, u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE]) { u8 swing_val[MAX_LANECOUNT]; @@ -85,7 +85,7 @@ static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, dptx_hal_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis); } -static void dptx_training_changemode(struct mtk_dp *mtk_dp) +static void dptx_training_changemode(const struct mtk_dp *mtk_dp) { dptx_hal_phyd_reset(mtk_dp); dptx_hal_swing_emp_reset(mtk_dp); @@ -93,7 +93,7 @@ static void dptx_training_changemode(struct mtk_dp *mtk_dp) mdelay(2); } -static void mtk_edp_train_setting(struct mtk_dp *mtk_dp, +static void mtk_edp_train_setting(const struct mtk_dp *mtk_dp, u8 linkrate, u8 lanecount) { u8 lanecount_enhanced_frame; @@ -120,12 +120,12 @@ static void mtk_edp_train_setting(struct mtk_dp *mtk_dp, linkrate, lanecount); } -static void drm_dp_dpcd_read_link_status(struct mtk_dp *mtk_dp, u8 status[DP_LINK_STATUS_SIZE]) +static void drm_dp_dpcd_read_link_status(const struct mtk_dp *mtk_dp, u8 status[DP_LINK_STATUS_SIZE]) { dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00202, DP_LINK_STATUS_SIZE, status); } -static int mtk_edp_train_cr(struct mtk_dp *mtk_dp, u8 lane_count) +static int mtk_edp_train_cr(const struct mtk_dp *mtk_dp, u8 lane_count) { u8 lane_adjust[DP_LANSE_ADJUST_SIZE]; u8 link_status[DP_LINK_STATUS_SIZE]; @@ -197,7 +197,7 @@ static int mtk_edp_train_cr(struct mtk_dp *mtk_dp, u8 lane_count) return DPTX_TRANING_FAIL; } -static int mtk_edp_train_eq(struct mtk_dp *mtk_dp, u8 lane_count) +static int mtk_edp_train_eq(const struct mtk_dp *mtk_dp, u8 lane_count) { u8 lane_adjust[2]; u8 link_status[DP_LINK_STATUS_SIZE]; diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index fb3c1daf57a..7b6a12c8b52 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -222,24 +222,23 @@ struct mtk_dp { }; int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid); -int mtk_edp_enable(struct mtk_dp *mtk_dp); +int mtk_edp_enable(const struct mtk_dp *mtk_dp); void dptx_set_tx_power_con(void); void dptx_set_26mhz_clock(void); int dptx_set_trainingstart(struct mtk_dp *mtk_dp); -bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, +bool dptx_auxread_dpcd(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rxbuf); -bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, - size_t length, u8 *data); +bool dptx_auxwrite_dpcd(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, const u8 *data); bool dptx_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count); bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count); -void dptx_init_variable(struct mtk_dp *mtk_dp); void dptx_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void dptx_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void dptx_power_on(void); -void dptx_video_config(struct mtk_dp *mtk_dp); -void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable); +void dptx_video_config(const struct mtk_dp *mtk_dp); +void dptx_video_enable(const struct mtk_dp *mtk_dp, bool enable); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index daece24e20b..bc585ce2f29 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -15,6 +15,12 @@ #define DP_AUX_NATIVE_WRITE 0x8 #define DP_AUX_NATIVE_READ 0x9 +#define DP_AUX_NATIVE_REPLY_ACK 0x0 +#define DP_AUX_NATIVE_REPLY_NACK 0x1 +#define DP_AUX_NATIVE_REPLY_DEFER 0x2 +#define DP_AUX_I2C_REPLY_NACK 0x4 +#define DP_AUX_I2C_REPLY_DEFER 0x8 + #define DP_WRITE1BYTE(mtk_dp, reg, u8_val) \ mtk_dp_write_byte(mtk_dp, reg, u8_val, 0xff) #define DP_WRITE2BYTE(mtk_dp, reg, u16_val) \ @@ -57,51 +63,51 @@ enum { DP_COLOR_DEPTH_UNKNOWN = 5, }; -bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp); -bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, +bool dptx_hal_hpd_high(const struct mtk_dp *mtk_dp); +bool dptx_hal_auxread_bytes(const struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rx_buf); -bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data); -void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, - u8 *swing_value, u8 *preemphasis); -void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp); -u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp); -u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset); -void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); -void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); -u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset); -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask); -void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); -void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); -void dptx_hal_verify_clock(struct mtk_dp *mtk_dp); -void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp); -void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp); -void dptx_hal_phy_setting(struct mtk_dp *mtk_dp); -void dptx_hal_aux_setting(struct mtk_dp *mtk_dp); -void dptx_hal_digital_setting(struct mtk_dp *mtk_dp); -void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value); -void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp); -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, u8 value); -void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_init_setting(struct mtk_dp *mtk_dp); -void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, bool enable, +bool dptx_hal_auxwrite_bytes(const struct mtk_dp *mtk_dp, u8 cmd, + u32 dpcd_addr, size_t length, const u8 *data); +void dptx_hal_set_swing_preemphasis(const struct mtk_dp *mtk_dp, size_t lane_count, + const u8 *swing_value, const u8 *preemphasis); +void dptx_hal_reset_swing_preemphasis(const struct mtk_dp *mtk_dp); +u8 dptx_hal_get_colorbpp(const struct mtk_dp *mtk_dp); +u32 mtk_dp_phy_read(const struct mtk_dp *mtk_dp, u32 offset); +void mtk_dp_phy_mask(const struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); +void mtk_dp_phy_write(const struct mtk_dp *mtk_dp, u32 offset, u32 val); +u32 mtk_dp_read(const struct mtk_dp *mtk_dp, u32 offset); +void mtk_dp_write_byte(const struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask); +void mtk_dp_mask(const struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); +void mtk_dp_write(const struct mtk_dp *mtk_dp, u32 offset, u32 val); +void dptx_hal_verify_clock(const struct mtk_dp *mtk_dp); +void dptx_hal_digital_swreset(const struct mtk_dp *mtk_dp); +void dptx_hal_ssc_en(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_hpd_int_en(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_hpd_detect_setting(const struct mtk_dp *mtk_dp); +void dptx_hal_phy_setting(const struct mtk_dp *mtk_dp); +void dptx_hal_aux_setting(const struct mtk_dp *mtk_dp); +void dptx_hal_digital_setting(const struct mtk_dp *mtk_dp); +void dptx_hal_set_txlane(const struct mtk_dp *mtk_dp, u8 value); +void dptx_hal_phy_setidlepattern(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_phyd_reset(const struct mtk_dp *mtk_dp); +void dptx_hal_set_txtrainingpattern(const struct mtk_dp *mtk_dp, u8 value); +void dptx_hal_set_ef_mode(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_setscramble(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_init_setting(const struct mtk_dp *mtk_dp); +void dptx_hal_videomute(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_bypassmsa_en(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_overwrite_mn(const struct mtk_dp *mtk_dp, bool enable, u32 video_m, u32 video_n); -void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value); -void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value); -void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value); -void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp); -void dptx_hal_set_msa(struct mtk_dp *mtk_dp); -void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]); -void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth); -void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 color_format); -void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value); -void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable); -void dptx_hal_phy_init(struct mtk_dp *mtk_dp); +void dptx_hal_settu_sramrd_start(const struct mtk_dp *mtk_dp, u16 value); +void dptx_hal_setsdp_downcnt_init_inhblanking(const struct mtk_dp *mtk_dp, u16 value); +void dptx_hal_setsdp_downcnt_init(const struct mtk_dp *mtk_dp, u16 value); +void dptx_hal_settu_setencoder(const struct mtk_dp *mtk_dp); +void dptx_hal_set_msa(const struct mtk_dp *mtk_dp); +void dptx_hal_setmisc(const struct mtk_dp *mtk_dp, u8 cmisc[2]); +void dptx_hal_set_color_depth(const struct mtk_dp *mtk_dp, u8 color_depth); +void dptx_hal_set_color_format(const struct mtk_dp *mtk_dp, u8 color_format); +void dptx_hal_set_txrate(const struct mtk_dp *mtk_dp, u8 value); +void dptx_hal_analog_power_en(const struct mtk_dp *mtk_dp, bool enable); +void dptx_hal_phy_init(const struct mtk_dp *mtk_dp); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h index b5149b812b4..b80180eba37 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h @@ -19,8 +19,8 @@ enum { extern const int dptx_hal_driving_offset[]; extern const int dptx_hal_driving_offset_size; -void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp); -void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable); -void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count); +void dptx_hal_swing_emp_reset(const struct mtk_dp *mtk_dp); +void dptx_hal_phy_set_idle_pattern(const struct mtk_dp *mtk_dp, u8 lane_count, bool enable); +void dptx_hal_phy_set_lanes(const struct mtk_dp *mtk_dp, u8 lane_count); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H */ diff --git a/src/soc/mediatek/common/dramc_param.c b/src/soc/mediatek/common/dramc_param.c index 4e05bc2e738..f81ff0fe176 100644 --- a/src/soc/mediatek/common/dramc_param.c +++ b/src/soc/mediatek/common/dramc_param.c @@ -44,14 +44,3 @@ void dump_param_header(const void *blob) header->size, sizeof(*dparam)); print("header.flags = %#x\n", header->flags); } - -int initialize_dramc_param(void *blob) -{ - struct dramc_param *param = blob; - struct dramc_param_header *hdr = ¶m->header; - - memset(hdr, 0, sizeof(*hdr)); - hdr->version = DRAMC_PARAM_HEADER_VERSION; - hdr->size = sizeof(*param); - return 0; -} diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c index 4071cee41a3..9126c541f07 100644 --- a/src/soc/mediatek/common/dsi_common.c +++ b/src/soc/mediatek/common/dsi_common.c @@ -454,7 +454,7 @@ static void mtk_dsi_stop(struct dsi_regs *dsi) } int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, - const u8 *init_commands) + const u8 *init_commands, struct thread_mutex *ready_mutex) { u32 data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); @@ -501,6 +501,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, mtk_dsi_clk_hs_mode_enable(dsi); } + if (ready_mutex) + thread_mutex_unlock(ready_mutex); if (init_commands) mipi_panel_parse_commands(init_commands, mtk_dsi_cmdq, &mode_flags); diff --git a/src/soc/mediatek/common/flash_controller.c b/src/soc/mediatek/common/flash_controller.c index 4f0d4b0dfac..1e829e97c49 100644 --- a/src/soc/mediatek/common/flash_controller.c +++ b/src/soc/mediatek/common/flash_controller.c @@ -3,16 +3,19 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include static struct mtk_nor_regs *const mtk_nor = (void *)SFLASH_REG_BASE; +struct thread_mutex mtk_dma_mutex; #define GET_NTH_BYTE(d, n) ((d >> (8 * n)) & 0xff) @@ -150,8 +153,14 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, /* DMA: start [ skip | len | drop ] = total end */ for (done = 0; done < total; dest += copy_len) { read_len = MIN(dma_buf_len, total - done); - if (dma_read(start + done, dma_buf, read_len)) + + /* Protect shared SPI controller and dma_buf during transfer AND copy */ + thread_mutex_lock(&mtk_dma_mutex); + + if (dma_read(start + done, dma_buf, read_len)) { + thread_mutex_unlock(&mtk_dma_mutex); return -1; + } done += read_len; /* decide the range to copy into buffer */ @@ -160,8 +169,12 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, copy_len = read_len - skip; memcpy(dest, (uint8_t *)dma_buf + skip, copy_len); + if (skip) skip = 0; /* Only apply skip in first iteration. */ + + /* Release bus immediately after data is safely copied out of shared buffer */ + thread_mutex_unlock(&mtk_dma_mutex); } return 0; } diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 886fb2a6628..1fc5bd6075d 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -7,9 +7,11 @@ #include #include #include +#include #include #include #include +#include const struct i2c_spec_values standard_mode_spec = { .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, @@ -167,6 +169,8 @@ static int mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP); + thread_mutex_lock(&mtk_dma_mutex); + switch (mode) { case I2C_WRITE_MODE: memcpy(_dma_coherent, write_buffer, write_len); @@ -269,6 +273,8 @@ static int mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, } } + thread_mutex_unlock(&mtk_dma_mutex); + write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | I2C_HS_NACKERR); diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h index 87a6a04d9db..6b663aaf215 100644 --- a/src/soc/mediatek/common/include/soc/display.h +++ b/src/soc/mediatek/common/include/soc/display.h @@ -7,6 +7,7 @@ #include #include #include +#include enum disp_path_sel { DISP_PATH_NONE = 0, @@ -31,7 +32,7 @@ struct panel_description { struct panel_description *get_active_panel(void); void mtk_display_disable_secure_mode(void); -int mtk_display_init(void); +int mtk_display_init(struct thread_mutex *ready_mutex); int mtk_mipi_panel_poweroff(void); void mtk_ddp_init(void); diff --git a/src/soc/mediatek/common/include/soc/display_dsi.h b/src/soc/mediatek/common/include/soc/display_dsi.h index 6a51dca55a4..0f540aa0683 100644 --- a/src/soc/mediatek/common/include/soc/display_dsi.h +++ b/src/soc/mediatek/common/include/soc/display_dsi.h @@ -5,6 +5,7 @@ #include #include +#include enum mipi_dsi_pixel_format { MIPI_DSI_FMT_RGB888, @@ -50,7 +51,7 @@ enum { /* Public API for common display code (display.c). */ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, - const u8 *init_commands); + const u8 *init_commands, struct thread_mutex *ready_mutex); int mtk_dsi_panel_poweroff(u32 mode_flags, const u8 *poweroff_cmds); #endif /* SOC_MEDIATEK_DISPLAY_DSI_H */ diff --git a/src/soc/mediatek/common/include/soc/dma_mutex.h b/src/soc/mediatek/common/include/soc/dma_mutex.h new file mode 100644 index 00000000000..97dcbc638a3 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dma_mutex.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DMA_MUTEX_H__ +#define __SOC_MEDIATEK_COMMON_DMA_MUTEX_H__ + +#include + +extern struct thread_mutex mtk_dma_mutex; + +#endif /* __SOC_MEDIATEK_COMMON_DMA_MUTEX_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h index 57ee16d7e53..e691fd257b1 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param_common.h +++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h @@ -31,6 +31,7 @@ enum DRAMC_PARAM_CONFIG { DRAMC_CONFIG_EMCP = 0x0001, DRAMC_CONFIG_DVFS = 0x0002, DRAMC_CONFIG_FAST_K = 0x0004, + DRAMC_CONFIG_HIGH_FREQ = 0x0008, /* Security configs */ DRAMC_CONFIG_SCRAMBLE = 0x0100, }; @@ -109,6 +110,5 @@ const char *get_status_string(u16 status); void dump_param_header(const void *blob); int validate_dramc_param(const void *blob); int is_valid_dramc_param(const void *blob); -int initialize_dramc_param(void *blob); #endif diff --git a/src/soc/mediatek/common/include/soc/mt6685.h b/src/soc/mediatek/common/include/soc/mt6685.h index 5590a1b6763..0b4f1ff7f1d 100644 --- a/src/soc/mediatek/common/include/soc/mt6685.h +++ b/src/soc/mediatek/common/include/soc/mt6685.h @@ -19,7 +19,6 @@ struct mt6685_key_setting { }; void mt6685_init(void); -void mt6685_init_pmif_arb(void); void mt6685_write_field(u32 reg, u32 val, u32 mask, u32 shift); u32 mt6685_read_field(u32 reg, u32 mask, u32 shift); u8 mt6685_read8(u32 reg); diff --git a/src/soc/mediatek/common/include/soc/pmif_common.h b/src/soc/mediatek/common/include/soc/pmif_common.h index b9cee916760..5af8e5d90c6 100644 --- a/src/soc/mediatek/common/include/soc/pmif_common.h +++ b/src/soc/mediatek/common/include/soc/pmif_common.h @@ -28,8 +28,8 @@ struct pmif { u32 swinf_no; u32 mstid; u32 pmifid; - void (*read)(struct pmif *arb, u32 slvid, u32 reg, u32 *data); - void (*write)(struct pmif *arb, u32 slvid, u32 reg, u32 data); + void (*read8)(struct pmif *arb, u32 slvid, u32 reg, u8 *data); + void (*write8)(struct pmif *arb, u32 slvid, u32 reg, u8 data); void (*read16)(struct pmif *arb, u32 slvid, u32 reg, u16 *data); void (*write16)(struct pmif *arb, u32 slvid, u32 reg, u16 data); u32 (*read_field)(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift); @@ -86,15 +86,15 @@ DEFINE_BIT(PMIFSPMI_MD_CTL_SRVOL_EN, 11) struct pmif *get_pmif_controller(int inf, int mstid); void pmwrap_interface_init(void); int mtk_pmif_init(void); -void pmif_spmi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data); -void pmif_spmi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data); +void pmif_spmi_read8(struct pmif *arb, u32 slvid, u32 reg, u8 *data); +void pmif_spmi_write8(struct pmif *arb, u32 slvid, u32 reg, u8 data); void pmif_spmi_read16(struct pmif *arb, u32 slvid, u32 reg, u16 *data); void pmif_spmi_write16(struct pmif *arb, u32 slvid, u32 reg, u16 data); u32 pmif_spmi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift); void pmif_spmi_write_field(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift); -void pmif_spi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data); -void pmif_spi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data); +void pmif_spi_read16(struct pmif *arb, u32 slvid, u32 reg, u16 *data); +void pmif_spi_write16(struct pmif *arb, u32 slvid, u32 reg, u16 data); u32 pmif_spi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift); void pmif_spi_write_field(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift); diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 4e3d7110ef7..8b50c0840c6 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -97,6 +97,7 @@ enum { /* external API */ bool rtc_write_trigger(void); bool rtc_writeif_unlock(void); +bool rtc_clrset_trigger(u16 addr, u16 clr_bits, u16 set_bits); bool rtc_xosc_write(u16 val); bool rtc_lpen(u16 con); bool rtc_reg_init(void); diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 6408ac03e8f..31efdb7b110 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -17,8 +17,6 @@ _Static_assert(sizeof(struct dramc_param) <= FMAP_SECTION_RW_MRC_CACHE_SIZE, "sizeof(struct dramc_param) exceeds RW_MRC_CACHE size"); -const char *get_dram_geometry_str(u32 ddr_geometry); -const char *get_dram_type_str(u32 ddr_type); static const struct ddr_base_info *curr_ddr_info; @@ -45,7 +43,7 @@ static int mt_mem_test(const struct dramc_data *dparam) return 0; } -const char *get_dram_geometry_str(u32 ddr_geometry) +static const char *get_dram_geometry_str(u32 ddr_geometry) { const char *s; @@ -76,7 +74,7 @@ const char *get_dram_geometry_str(u32 ddr_geometry) return s; } -const char *get_dram_type_str(u32 ddr_type) +static const char *get_dram_type_str(u32 ddr_type) { const char *s; @@ -191,22 +189,44 @@ static int run_dram_blob(struct dramc_param *dparam) return 0; } -static int dram_run_fast_calibration(struct dramc_param *dparam) +static u16 get_expected_config(void) { - const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; + u16 config = 0; + + if (CONFIG(MEDIATEK_DRAM_DVFS)) + config |= DRAMC_CONFIG_DVFS; + + if (CONFIG(MEDIATEK_DRAM_HIGH_FREQ)) + config |= DRAMC_CONFIG_HIGH_FREQ; + + if (CONFIG(MEDIATEK_DRAM_SCRAMBLE)) + config |= DRAMC_CONFIG_SCRAMBLE; - if (dparam->dramc_datas.ddr_info.config_dvfs != config) { - printk(BIOS_WARNING, + return config; +} + +static int dram_run_fast_calibration(struct dramc_param *dparam) +{ + /* + * Sync old config_dvfs setting to header.config to support backward + * compatibility for validation. + */ + if (dparam->dramc_datas.ddr_info.config_dvfs == DRAMC_ENABLE_DVFS) + dparam->header.config |= DRAMC_CONFIG_DVFS; + + /* Validate config flags (scramble, DVFS, etc.) except FAST_K */ + const u16 expected_config = get_expected_config(); + const u16 mask = (u16)~DRAMC_CONFIG_FAST_K; + if ((dparam->header.config & mask) != (expected_config & mask)) { + printk(BIOS_INFO, "DRAM-K: Incompatible config for calibration data from flash " "(expected: %#x, saved: %#x)\n", - config, dparam->dramc_datas.ddr_info.config_dvfs); - return -1; + expected_config & mask, dparam->header.config & mask); + return -DRAMC_ERR_RECALIBRATE; } printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); - if (CONFIG(MEDIATEK_DRAM_SCRAMBLE)) - dparam->header.config |= DRAMC_CONFIG_SCRAMBLE; if (CONFIG(MEDIATEK_DRAM_BLOB_FAST_INIT)) { printk(BIOS_INFO, "DRAM-K: Run fast calibration run in blob mode\n"); @@ -218,46 +238,41 @@ static int dram_run_fast_calibration(struct dramc_param *dparam) dparam->header.config |= DRAMC_CONFIG_FAST_K; if (run_dram_blob(dparam) < 0) - return -3; + return -DRAMC_ERR_FAST_CALIBRATION; } else { init_dram_by_params(dparam); } if (mt_mem_test(&dparam->dramc_datas) < 0) - return -4; + return -DRAMC_ERR_COMPLEX_RW_MEM_TEST; return 0; } -static int dram_run_full_calibration(struct dramc_param *dparam) -{ - initialize_dramc_param(dparam); - - return run_dram_blob(dparam); -} - -static void mem_init_set_default_config(struct dramc_param *dparam, - const struct sdram_info *dram_info) +static int dram_run_full_calibration(struct dramc_param *dparam, + const struct sdram_info *dram_info) { - u32 type, geometry; memset(dparam, 0, sizeof(*dparam)); - type = dram_info->ddr_type; - geometry = dram_info->ddr_geometry; + dparam->dramc_datas.ddr_info.sdram.ddr_type = dram_info->ddr_type; + dparam->dramc_datas.ddr_info.sdram.ddr_geometry = dram_info->ddr_geometry; - dparam->dramc_datas.ddr_info.sdram.ddr_type = type; + /* Initialize header version and size */ + dparam->header.version = DRAMC_PARAM_HEADER_VERSION; + dparam->header.size = sizeof(*dparam); - if (CONFIG(MEDIATEK_DRAM_DVFS)) - dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS; - if (CONFIG(MEDIATEK_DRAM_SCRAMBLE)) - dparam->header.config |= DRAMC_CONFIG_SCRAMBLE; + dparam->header.config = get_expected_config(); + /* Sync config_dvfs from header.config for backward compatibility. */ + dparam->dramc_datas.ddr_info.config_dvfs = + (dparam->header.config & DRAMC_CONFIG_DVFS) ? + DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; - dparam->dramc_datas.ddr_info.sdram.ddr_geometry = geometry; + printk(BIOS_INFO, "DRAM-K: config: %#x, ddr_type: %s, ddr_geometry: %s\n", + dparam->header.config, + get_dram_type_str(dram_info->ddr_type), + get_dram_geometry_str(dram_info->ddr_geometry)); - printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n", - get_dram_type_str(type), - dparam->dramc_datas.ddr_info.config_dvfs, - get_dram_geometry_str(geometry)); + return run_dram_blob(dparam); } static void mt_mem_init_run(struct dramc_param *dparam, @@ -278,9 +293,14 @@ static void mt_mem_init_run(struct dramc_param *dparam, ret = dram_run_fast_calibration(dparam); if (ret != 0) { - printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " - "in %lld msecs, error: %d\n", - stopwatch_duration_msecs(&sw), ret); + if (ret == -DRAMC_ERR_RECALIBRATE) { + printk(BIOS_INFO, "DRAM-K: Fast calibration cache incompatible, " + "re-calibration needed\n"); + } else { + printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " + "in %lld msecs, error: %d\n", + stopwatch_duration_msecs(&sw), ret); + } /* Erase flash data after fast calibration failed */ memset(dparam, 0xa5, mrc_cache_size); @@ -299,10 +319,8 @@ static void mt_mem_init_run(struct dramc_param *dparam, /* Run full calibration */ printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); - mem_init_set_default_config(dparam, dram_info); - stopwatch_init(&sw); - int err = dram_run_full_calibration(dparam); + int err = dram_run_full_calibration(dparam, dram_info); if (err == 0) { printk(BIOS_INFO, "DRAM-K: Full calibration passed in %lld msecs\n", stopwatch_duration_msecs(&sw)); diff --git a/src/soc/mediatek/common/mt6315.c b/src/soc/mediatek/common/mt6315.c index a9efb0c9755..a7a3e471332 100644 --- a/src/soc/mediatek/common/mt6315.c +++ b/src/soc/mediatek/common/mt6315.c @@ -9,14 +9,14 @@ static struct pmif *pmif_arb = NULL; -static void mt6315_read(u32 slvid, u32 reg, u32 *data) +static void mt6315_read(u32 slvid, u32 reg, u8 *data) { - pmif_arb->read(pmif_arb, slvid, reg, data); + pmif_arb->read8(pmif_arb, slvid, reg, data); } -static void mt6315_write(u32 slvid, u32 reg, u32 data) +static void mt6315_write(u32 slvid, u32 reg, u8 data) { - pmif_arb->write(pmif_arb, slvid, reg, data); + pmif_arb->write8(pmif_arb, slvid, reg, data); } void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) @@ -62,7 +62,8 @@ void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv) u32 mt6315_buck_get_voltage(u32 slvid, u32 buck_id) { - u32 vol_reg, vol; + u32 vol_reg; + u8 vol; if (!pmif_arb) die("ERROR: pmif_arb not initialized"); @@ -80,7 +81,7 @@ u32 mt6315_buck_get_voltage(u32 slvid, u32 buck_id) }; mt6315_read(slvid, vol_reg, &vol); - return vol * 6250; + return (u32)vol * 6250; } static void init_pmif_arb(void) diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c index 9ed5d29c219..44394a17526 100644 --- a/src/soc/mediatek/common/mt6316.c +++ b/src/soc/mediatek/common/mt6316.c @@ -14,18 +14,18 @@ static const u32 mt6316_slave_id[] = { static u8 mt6316_read8(enum spmi_slave slvid, u32 reg) { - u32 rdata = 0; + u8 rdata = 0; assert(pmif_arb); - pmif_arb->read(pmif_arb, slvid, reg, &rdata); + pmif_arb->read8(pmif_arb, slvid, reg, &rdata); - return (u8)rdata; + return rdata; } static void mt6316_write8(enum spmi_slave slvid, u32 reg, u8 data) { assert(pmif_arb); - pmif_arb->write(pmif_arb, slvid, reg, data); + pmif_arb->write8(pmif_arb, slvid, reg, data); } void mt6316_write_field(enum spmi_slave slvid, u32 reg, u32 val, u32 mask, u32 shift) diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c index 5dad6a44cb4..26cc224de49 100644 --- a/src/soc/mediatek/common/mt6359p.c +++ b/src/soc/mediatek/common/mt6359p.c @@ -45,9 +45,9 @@ static const struct pmic_efuse efuse_setting[] = { }; static struct pmif *pmif_arb = NULL; -static void mt6359p_write(u32 reg, u32 data) +static void mt6359p_write(u32 reg, u16 data) { - pmif_arb->write(pmif_arb, 0, reg, data); + pmif_arb->write16(pmif_arb, 0, reg, data); } u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift) diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index e675ef2c9cb..5a4e6ff532b 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -36,18 +36,18 @@ u16 mt6363_read16(u32 reg) u8 mt6363_read8(u32 reg) { - u32 rdata = 0; + u8 rdata = 0; assert(pmif_arb); - pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &rdata); + pmif_arb->read8(pmif_arb, SPMI_SLAVE_4, reg, &rdata); - return (u8)rdata; + return rdata; } void mt6363_write8(u32 reg, u8 data) { assert(pmif_arb); - pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, data); + pmif_arb->write8(pmif_arb, SPMI_SLAVE_4, reg, data); } static u32 mt6363_read_field(u32 reg, u32 mask, u32 shift) diff --git a/src/soc/mediatek/common/mt6373.c b/src/soc/mediatek/common/mt6373.c index 315f19b8fa7..92deac99d24 100644 --- a/src/soc/mediatek/common/mt6373.c +++ b/src/soc/mediatek/common/mt6373.c @@ -24,7 +24,7 @@ static struct pmif *pmif_arb; static void mt6373_write8(u32 reg, u8 data) { assert(pmif_arb); - pmif_arb->write(pmif_arb, SPMI_SLAVE_5, reg, data); + pmif_arb->write8(pmif_arb, SPMI_SLAVE_5, reg, data); } static u32 mt6373_read_field(u32 reg, u32 mask, u32 shift) diff --git a/src/soc/mediatek/common/mt6685.c b/src/soc/mediatek/common/mt6685.c index 0d43c7badea..9db6310dfe8 100644 --- a/src/soc/mediatek/common/mt6685.c +++ b/src/soc/mediatek/common/mt6685.c @@ -11,46 +11,57 @@ #define MT6685_TOP_RST_MISC_SET 0x128 static struct pmif *pmif_arb; + +static void mt6685_init_pmif_arb(void) +{ + if (pmif_arb) + return; + + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); + if (pmif_arb->check_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi"); +} + u32 mt6685_read_field(u32 reg, u32 mask, u32 shift) { - assert(pmif_arb); + mt6685_init_pmif_arb(); return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_9, reg, mask, shift); } void mt6685_write_field(u32 reg, u32 val, u32 mask, u32 shift) { - assert(pmif_arb); + mt6685_init_pmif_arb(); pmif_arb->write_field(pmif_arb, SPMI_SLAVE_9, reg, val, mask, shift); } u8 mt6685_read8(u32 reg) { - u32 rdata = 0; + u8 rdata = 0; - assert(pmif_arb); - pmif_arb->read(pmif_arb, SPMI_SLAVE_9, reg, &rdata); + mt6685_init_pmif_arb(); + pmif_arb->read8(pmif_arb, SPMI_SLAVE_9, reg, &rdata); - return (u8)rdata; + return rdata; } void mt6685_write8(u32 reg, u8 reg_val) { - assert(pmif_arb); - pmif_arb->write(pmif_arb, SPMI_SLAVE_9, reg, reg_val); + mt6685_init_pmif_arb(); + pmif_arb->write8(pmif_arb, SPMI_SLAVE_9, reg, reg_val); } u16 mt6685_read16(u32 reg) { u16 rdata = 0; - assert(pmif_arb); + mt6685_init_pmif_arb(); pmif_arb->read16(pmif_arb, SPMI_SLAVE_9, reg, &rdata); return rdata; } void mt6685_write16(u32 reg, u16 reg_val) { - assert(pmif_arb); + mt6685_init_pmif_arb(); pmif_arb->write16(pmif_arb, SPMI_SLAVE_9, reg, reg_val); } @@ -78,23 +89,10 @@ static void mt6685_unlock(bool unlock) unlock ? key_protect_setting[i].val : 0); } -void mt6685_init_pmif_arb(void) -{ - if (pmif_arb) - return; - - pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); - assert(pmif_arb); - - if (pmif_arb->check_init_done(pmif_arb)) - die("ERROR - Failed to initialize pmif spi"); - - printk(BIOS_INFO, "[%s]CHIP ID = %#x\n", __func__, mt6685_read_field(0xb, 0xFF, 0)); -} - void mt6685_init(void) { mt6685_init_pmif_arb(); + printk(BIOS_INFO, "[%s]CHIP ID = %#x\n", __func__, mt6685_read_field(0xb, 0xFF, 0)); mt6685_unlock(true); mt6685_wdt_set(); mt6685_init_setting(); diff --git a/src/soc/mediatek/common/pmif.c b/src/soc/mediatek/common/pmif.c index 97da4157f11..5c36d52f5f0 100644 --- a/src/soc/mediatek/common/pmif.c +++ b/src/soc/mediatek/common/pmif.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -8,6 +9,8 @@ #include #include #include +#include +#include #include static int pmif_check_swinf(struct pmif *arb, long timeout_us, u32 expected_status) @@ -25,11 +28,11 @@ static int pmif_check_swinf(struct pmif *arb, long timeout_us, u32 expected_stat return 0; } -static void pmif_send_cmd(struct pmif *arb, int write, u32 opc, u32 slvid, - u32 addr, u32 *rdata, u32 wdata, u32 len) +static void send_cmd(struct pmif *arb, bool write, u32 opc, u32 slvid, + u32 bc, u32 addr, u32 *rdata, u32 wdata) { int ret; - u32 data, bc = len - 1; + u32 cmd = (opc << 30) | ((u32)write << 29) | (slvid << 24) | (bc << 16) | addr; /* Wait for Software Interface FSM state to be IDLE. */ ret = pmif_check_swinf(arb, PMIF_WAIT_IDLE_US, SWINF_FSM_IDLE); @@ -43,8 +46,7 @@ static void pmif_send_cmd(struct pmif *arb, int write, u32 opc, u32 slvid, write32(&arb->ch->wdata, wdata); /* Send the command. */ - write32(&arb->ch->ch_send, - (opc << 30) | (write << 29) | (slvid << 24) | (bc << 16) | addr); + write32(&arb->ch->ch_send, cmd); if (!write) { /* @@ -57,88 +59,107 @@ static void pmif_send_cmd(struct pmif *arb, int write, u32 opc, u32 slvid, return; } - data = read32(&arb->ch->rdata); - *rdata = data; + *rdata = read32(&arb->ch->rdata); write32(&arb->ch->ch_rdy, 0x1); } } -void pmif_spmi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data) +static void pmif_send_cmd(struct pmif *arb, bool write, u32 opc, u32 slvid, + u32 addr, u32 *rdata, u32 wdata, u32 len) +{ + assert(len >= 1); + send_cmd(arb, write, opc, slvid, len - 1, addr, rdata, wdata); +} + +/* Data type is always u16 for PWRAP interface. */ +static void pwrap_send_cmd(struct pmif *arb, bool write, u32 addr, + u16 *rdata, u16 wdata) +{ + u32 rdata32 = 0; + + /* opc, slvid, bc are not used for PWRAP interface. */ + send_cmd(arb, write, 0, 0, 0, addr, &rdata32, wdata); + + if (!write) { + *rdata = (u16)rdata32; + assert(*rdata == rdata32); + } +} + +void pmif_spmi_read8(struct pmif *arb, u32 slvid, u32 reg, u8 *data) { - *data = 0; - pmif_send_cmd(arb, 0, PMIF_CMD_EXT_REG_LONG, slvid, reg, data, 0, 1); + u32 rdata = 0; + pmif_send_cmd(arb, false, PMIF_CMD_EXT_REG_LONG, slvid, reg, &rdata, 0, 1); + assert(rdata <= UINT8_MAX); + *data = (u8)rdata; } -void pmif_spmi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data) +void pmif_spmi_write8(struct pmif *arb, u32 slvid, u32 reg, u8 data) { - pmif_send_cmd(arb, 1, PMIF_CMD_EXT_REG_LONG, slvid, reg, NULL, data, 1); + pmif_send_cmd(arb, true, PMIF_CMD_EXT_REG_LONG, slvid, reg, NULL, data, 1); } void pmif_spmi_read16(struct pmif *arb, u32 slvid, u32 reg, u16 *data) { u32 rdata = 0; - pmif_send_cmd(arb, 0, PMIF_CMD_EXT_REG_LONG, slvid, reg, &rdata, 0, 2); + pmif_send_cmd(arb, false, PMIF_CMD_EXT_REG_LONG, slvid, reg, &rdata, 0, 2); + assert(rdata <= UINT16_MAX); *data = (u16)rdata; } void pmif_spmi_write16(struct pmif *arb, u32 slvid, u32 reg, u16 data) { - pmif_send_cmd(arb, 1, PMIF_CMD_EXT_REG_LONG, slvid, reg, NULL, data, 2); + pmif_send_cmd(arb, true, PMIF_CMD_EXT_REG_LONG, slvid, reg, NULL, data, 2); } u32 pmif_spmi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift) { - u32 data; - - pmif_spmi_read(arb, slvid, reg, &data); - data &= (mask << shift); - data >>= shift; + u8 data; - return data; + pmif_spmi_read8(arb, slvid, reg, &data); + return ((u32)data >> shift) & mask; } void pmif_spmi_write_field(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) { - u32 old, new; + u8 old, new; - pmif_spmi_read(arb, slvid, reg, &old); + pmif_spmi_read8(arb, slvid, reg, &old); new = old & ~(mask << shift); - new |= (val << shift); - pmif_spmi_write(arb, slvid, reg, new); + new |= (u8)((val & mask) << shift); + pmif_spmi_write8(arb, slvid, reg, new); } -void pmif_spi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data) +void pmif_spi_read16(struct pmif *arb, u32 slvid, u32 reg, u16 *data) { - *data = 0; - pmif_send_cmd(arb, 0, PMIF_CMD_REG_0, slvid, reg, data, 0, 1); + pwrap_send_cmd(arb, false, reg, data, 0); } -void pmif_spi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data) +void pmif_spi_write16(struct pmif *arb, u32 slvid, u32 reg, u16 data) { - pmif_send_cmd(arb, 1, PMIF_CMD_REG_0, slvid, reg, NULL, data, 1); + pwrap_send_cmd(arb, true, reg, NULL, data); } u32 pmif_spi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift) { - u32 data; + u16 data; - pmif_spi_read(arb, slvid, reg, &data); - data &= (mask << shift); - data >>= shift; - - return data; + pmif_spi_read16(arb, slvid, reg, &data); + return ((u32)data >> shift) & mask; } void pmif_spi_write_field(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) { - u32 old, new; + u16 old, new; + + assert(((val & mask) << shift) <= UINT16_MAX); - pmif_spi_read(arb, slvid, reg, &old); + pmif_spi_read16(arb, slvid, reg, &old); new = old & ~(mask << shift); - new |= (val << shift); - pmif_spi_write(arb, slvid, reg, new); + new |= (u16)((val & mask) << shift); + pmif_spi_write16(arb, slvid, reg, new); } int pmif_check_init_done(struct pmif *arb) diff --git a/src/soc/mediatek/common/pmif_init.c b/src/soc/mediatek/common/pmif_init.c index 14250817c57..fc5e135868a 100644 --- a/src/soc/mediatek/common/pmif_init.c +++ b/src/soc/mediatek/common/pmif_init.c @@ -13,8 +13,8 @@ const struct pmif pmif_spmi_arb[] = { .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN, .mstid = SPMI_MASTER_0, .pmifid = PMIF_SPMI, - .write = pmif_spmi_write, - .read = pmif_spmi_read, + .write8 = pmif_spmi_write8, + .read8 = pmif_spmi_read8, .write_field = pmif_spmi_write_field, .read_field = pmif_spmi_read_field, .check_init_done = pmif_check_init_done, @@ -28,8 +28,8 @@ const struct pmif pmif_spi_arb[] = { .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, .ch = (struct chan_regs *)PMIF_SPI_AP_CHAN, .pmifid = PMIF_SPI, - .write = pmif_spi_write, - .read = pmif_spi_read, + .write16 = pmif_spi_write16, + .read16 = pmif_spi_read16, .write_field = pmif_spi_write_field, .read_field = pmif_spi_read_field, .check_init_done = pmif_check_init_done, diff --git a/src/soc/mediatek/common/pmif_spi.c b/src/soc/mediatek/common/pmif_spi.c index ed01c0d9a62..4baab5e4a58 100644 --- a/src/soc/mediatek/common/pmif_spi.c +++ b/src/soc/mediatek/common/pmif_spi.c @@ -125,11 +125,11 @@ static void init_reg_clock(struct pmif *arb) write32(&mtk_pmicspi_mst->cslext_read, 0x100); /* Set Read Dummy Cycle Number (Slave Clock is 18MHz) */ - arb->write(arb, DEFAULT_SLVID, PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + arb->write16(arb, DEFAULT_SLVID, PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); write32(&mtk_pmicspi_mst->rddmy, DUMMY_READ_CYCLES); /* Enable DIO mode */ - arb->write(arb, DEFAULT_SLVID, PMIC_DEW_DIO_EN, 0x1); + arb->write16(arb, DEFAULT_SLVID, PMIC_DEW_DIO_EN, 0x1); /* Wait for completion of sending the commands */ if (check_idle(&arb->mtk_pmif->inf_busy_sta, PMIF_SPI_AP)) { @@ -153,23 +153,23 @@ static void init_reg_clock(struct pmif *arb) static void init_spislv(struct pmif *arb) { /* Turn on SPI IO filter function */ - arb->write(arb, DEFAULT_SLVID, PMIC_FILTER_CON0, SPI_FILTER); + arb->write16(arb, DEFAULT_SLVID, PMIC_FILTER_CON0, SPI_FILTER); /* Turn on SPI IO SMT function to improve noise immunity */ - arb->write(arb, DEFAULT_SLVID, PMIC_SMT_CON1, SPI_SMT); + arb->write16(arb, DEFAULT_SLVID, PMIC_SMT_CON1, SPI_SMT); /* Turn off SPI IO pull function for power saving */ - arb->write(arb, DEFAULT_SLVID, PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + arb->write16(arb, DEFAULT_SLVID, PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); /* Enable SPI access in SODI-3.0 and Suspend modes */ - arb->write(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON0, 0x2); + arb->write16(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON0, 0x2); /* Set SPI IO driving strength to 4 mA */ - arb->write(arb, DEFAULT_SLVID, PMIC_DRV_CON1, SPI_DRIVING); + arb->write16(arb, DEFAULT_SLVID, PMIC_DRV_CON1, SPI_DRIVING); } static int init_sistrobe(struct pmif *arb) { - u32 rdata = 0; + u16 rdata = 0; int si_sample_ctrl; /* Random data for testing */ - const u32 test_data[30] = { + const u16 test_data[30] = { 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, @@ -180,7 +180,7 @@ static int init_sistrobe(struct pmif *arb) for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { write32(&mtk_pmicspi_mst->si_sampling_ctrl, si_sample_ctrl << 5); - arb->read(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + arb->read16(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); if (rdata == DEFAULT_VALUE_READ_TEST) break; } @@ -196,12 +196,12 @@ static int init_sistrobe(struct pmif *arb) * to current sampling clock edge. */ for (int si_dly = 0; si_dly < 10; si_dly++) { - arb->write(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON2, si_dly); + arb->write16(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON2, si_dly); int start_boundary_found = 0; for (int i = 0; i < ARRAY_SIZE(test_data); i++) { - arb->write(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, test_data[i]); - arb->read(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, &rdata); + arb->write16(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, test_data[i]); + arb->read16(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, &rdata); if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { start_boundary_found = 1; break; @@ -218,7 +218,7 @@ static int init_sistrobe(struct pmif *arb) write32(&mtk_pmicspi_mst->si_sampling_ctrl, ++si_sample_ctrl << 5); /* Read Test */ - arb->read(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + arb->read16(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); if (rdata != DEFAULT_VALUE_READ_TEST) { printk(BIOS_ERR, "[%s] Failed for read test, data = %#x.\n", __func__, rdata); @@ -231,10 +231,10 @@ static int init_sistrobe(struct pmif *arb) static void init_staupd(struct pmif *arb) { /* Unlock SPI Slave registers */ - arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0xbade); + arb->write16(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0xbade); /* Enable CRC of PMIC 0 */ - arb->write(arb, DEFAULT_SLVID, PMIC_DEW_CRC_EN, 0x1); + arb->write16(arb, DEFAULT_SLVID, PMIC_DEW_CRC_EN, 0x1); /* Wait for completion of sending the commands */ if (check_idle(&arb->mtk_pmif->inf_busy_sta, PMIF_SPI_AP)) { @@ -257,7 +257,7 @@ static void init_staupd(struct pmif *arb) write32(&arb->mtk_pmif->sig_mode, 0x0); /* Lock SPI Slave registers */ - arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + arb->write16(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); /* Set up PMIC Siganature */ write32(&arb->mtk_pmif->pmic_sig_addr, PMIC_DEW_CRC_VAL); @@ -300,7 +300,7 @@ int pmif_spi_init(struct pmif *arb) } /* Lock SPISLV Registers */ - arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + arb->write16(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); /* * Status update function initialization diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c index 6bc3e315242..7dec5877314 100644 --- a/src/soc/mediatek/common/pmif_spmi.c +++ b/src/soc/mediatek/common/pmif_spmi.c @@ -19,16 +19,16 @@ __weak void pmif_spmi_config(struct pmif *arb) static int spmi_read_check(struct pmif *pmif_arb, int slvid) { - u32 rdata = 0; + u8 rdata = 0; - pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST, &rdata); + pmif_arb->read8(pmif_arb, slvid, MT6315_READ_TEST, &rdata); if (rdata != MT6315_DEFAULT_VALUE_READ) { printk(BIOS_INFO, "%s next, slvid:%d rdata = 0x%x.\n", __func__, slvid, rdata); return -E_NODEV; } - pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST_1, &rdata); + pmif_arb->read8(pmif_arb, slvid, MT6315_READ_TEST_1, &rdata); if (rdata != MT6315_DEFAULT_VALUE_READ) { printk(BIOS_INFO, "%s next, slvid:%d rdata = 0x%x.\n", __func__, slvid, rdata); diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index f36bbc57e47..a7104a54dfb 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -43,6 +43,20 @@ bool rtc_writeif_unlock(void) return true; } +bool rtc_clrset_trigger(u16 addr, u16 clr_bits, u16 set_bits) +{ + u16 rdata; + + rtc_read(addr, &rdata); + + rdata &= ~clr_bits; + rdata |= set_bits; + + rtc_write(addr, rdata); + + return rtc_write_trigger(); +} + /* set rtc time */ int rtc_set(const struct rtc_time *time) { @@ -195,9 +209,7 @@ void rtc_boot_common(void) switch (rtc_check_state()) { case RTC_STATE_REBOOT: - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_osc_init(); rtc_info("RTC_STATE_REBOOT\n"); break; diff --git a/src/soc/mediatek/common/rtc_mt6359p.c b/src/soc/mediatek/common/rtc_mt6359p.c index 7ea23b0e794..9feb9c5d5e3 100644 --- a/src/soc/mediatek/common/rtc_mt6359p.c +++ b/src/soc/mediatek/common/rtc_mt6359p.c @@ -13,20 +13,16 @@ static struct pmif *pmif_arb = NULL; void rtc_read(u16 addr, u16 *rdata) { - u32 data; - if (!pmif_arb) pmif_arb = get_pmif_controller(PMIF_SPI, 0); - pmif_arb->read(pmif_arb, 0, (u32)addr, &data); - - *rdata = (u16)data; + pmif_arb->read16(pmif_arb, 0, (u32)addr, rdata); } void rtc_write(u16 addr, u16 wdata) { if (!pmif_arb) pmif_arb = get_pmif_controller(PMIF_SPI, 0); - pmif_arb->write(pmif_arb, 0, (unsigned int)addr, (unsigned int)wdata); + pmif_arb->write16(pmif_arb, 0, (u32)addr, wdata); } static void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift) @@ -47,10 +43,8 @@ static bool rtc_enable_dcxo(void) return false; } - u16 bbpu, con, osc32con, sec; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + u16 con, osc32con, sec; + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_OSC32CON, &osc32con); osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK); osc32con |= (OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB); @@ -70,30 +64,22 @@ static bool rtc_enable_dcxo(void) /* initialize rtc related gpio */ bool rtc_gpio_init(void) { - u16 con; - /* GPI mode and pull down */ - rtc_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN - | RTC_CON_XOSC32_LPEN); - con |= (RTC_CON_GPEN | RTC_CON_GOE); - con &= ~(RTC_CON_F32KOB); - con &= ~RTC_CON_GPU; - rtc_write(RTC_CON, con); - - return rtc_write_trigger(); + u16 mask = (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN | + RTC_CON_XOSC32_LPEN); + return rtc_clrset_trigger(RTC_CON, + (u16)(~mask) | RTC_CON_F32KOB | RTC_CON_GPU, + RTC_CON_GPEN | RTC_CON_GOE); } u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { - u16 bbpu, osc32con; + u16 osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_tcksel; struct stopwatch sw; if (val) { - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_OSC32CON, &osc32con); rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | (val & RTC_XOSCCALI_MASK)); @@ -163,14 +149,10 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) /* low power detect setting */ static bool rtc_lpd_init(void) { - u16 con, sec; + u16 con; /* enable both XOSC & EOSC LPD */ - rtc_read(RTC_AL_SEC, &sec); - sec &= ~RTC_LPD_OPT_F32K_CK_ALIVE; - rtc_write(RTC_AL_SEC, sec); - - if (!rtc_write_trigger()) + if (!rtc_clrset_trigger(RTC_AL_SEC, RTC_LPD_OPT_F32K_CK_ALIVE, 0)) return false; /* init XOSC32 to detect 32k clock stop */ @@ -197,21 +179,18 @@ static bool rtc_hw_init(void) { u16 bbpu; - rtc_read(RTC_BBPU, &bbpu); - bbpu |= RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR; - rtc_write(RTC_BBPU, bbpu & (~RTC_BBPU_SPAR_SW)); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, RTC_BBPU_SPAR_SW, + RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR); udelay(500); - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); - rtc_read(RTC_BBPU, &bbpu); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_read(RTC_BBPU, &bbpu); if (bbpu & RTC_BBPU_RESET_ALARM || bbpu & RTC_BBPU_RESET_SPAR) { rtc_info("timeout\n"); return false; } + return true; } @@ -219,8 +198,6 @@ static bool rtc_hw_init(void) int rtc_init(int recover) { int ret; - u16 year; - u16 al_dow; rtc_info("recovery: %d\n", recover); @@ -258,14 +235,10 @@ int rtc_init(int recover) } /* RTC EOSC calibration period setting and day-of-week value of alarm counter setting */ - rtc_read(RTC_AL_DOW, &al_dow); - rtc_write(RTC_AL_DOW, al_dow | RTC_EOSC_CALI_TD_DEFAULT); + rtc_clrset_trigger(RTC_AL_DOW, 0, RTC_EOSC_CALI_TD_DEFAULT); /* solution1 for EOSC cali*/ - rtc_read(RTC_AL_YEA, &year); - rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1) - & (~RTC_K_EOSC_RSV_2)); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_AL_YEA, RTC_K_EOSC_RSV_1 | RTC_K_EOSC_RSV_2, RTC_K_EOSC_RSV_0); if (!rtc_lpd_init()) { ret = -RTC_STATUS_LPD_INIT_FAIL; diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 8d86e1520a0..b3ba1d50ab0 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -10,18 +10,14 @@ /* initialize rtc related gpio */ bool rtc_gpio_init(void) { - u16 con; - mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE, - MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */ + MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */ /* Export 32K clock RTC_32K2V8 */ - rtc_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN); - con |= (RTC_CON_GPEN | RTC_CON_GOE); - con &= ~(RTC_CON_F32KOB); - rtc_write(RTC_CON, con); - return rtc_write_trigger(); + u16 mask = RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN; + return rtc_clrset_trigger(RTC_CON, + (u16)(~mask) | RTC_CON_F32KOB, + RTC_CON_GPEN | RTC_CON_GOE); } /* set xosc mode */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 23a3ea3d5c1..f215212fa7d 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -11,11 +11,9 @@ /* initialize rtc setting of using dcxo clock */ static bool rtc_enable_dcxo(void) { - u16 bbpu, con, osc32con, sec; + u16 con, osc32con, sec; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); mdelay(1); if (!rtc_writeif_unlock()) { @@ -44,8 +42,6 @@ static bool rtc_enable_dcxo(void) /* initialize rtc related gpio */ bool rtc_gpio_init(void) { - u16 con; - /* RTC_32K1V8 clock change from 128k div 4 source * to RTC 32k source */ @@ -55,26 +51,21 @@ bool rtc_gpio_init(void) pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); /* Export 32K clock RTC_32K2V8 */ - rtc_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN - | RTC_CON_XOSC32_LPEN); - con |= (RTC_CON_GPEN | RTC_CON_GOE); - con &= ~(RTC_CON_F32KOB); - rtc_write(RTC_CON, con); - - return rtc_write_trigger(); + u16 mask = (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN | + RTC_CON_XOSC32_LPEN); + return rtc_clrset_trigger(RTC_CON, + (u16)(~mask) | RTC_CON_F32KOB, + RTC_CON_GPEN | RTC_CON_GOE); } u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { - u16 bbpu, osc32con; + u16 osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; struct stopwatch sw; if (val) { - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_OSC32CON, &osc32con); rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | (val & RTC_XOSCCALI_MASK)); @@ -143,13 +134,10 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) /* low power detect setting */ static bool rtc_lpd_init(void) { - u16 con, sec; + u16 con; /* set RTC_LPD_OPT */ - rtc_read(RTC_AL_SEC, &sec); - sec |= RTC_LPD_OPT_F32K_CK_ALIVE; - rtc_write(RTC_AL_SEC, sec); - if (!rtc_write_trigger()) + if (!rtc_clrset_trigger(RTC_AL_SEC, 0, RTC_LPD_OPT_F32K_CK_ALIVE)) return false; /* init XOSC32 to detect 32k clock stop */ @@ -169,11 +157,7 @@ static bool rtc_lpd_init(void) rtc_write(RTC_CON, con); /* set RTC_LPD_OPT */ - rtc_read(RTC_AL_SEC, &sec); - sec &= ~RTC_LPD_OPT_MASK; - sec |= RTC_LPD_OPT_EOSC_LPD; - rtc_write(RTC_AL_SEC, sec); - if (!rtc_write_trigger()) + if (!rtc_clrset_trigger(RTC_AL_SEC, RTC_LPD_OPT_MASK, RTC_LPD_OPT_EOSC_LPD)) return false; return true; @@ -183,15 +167,11 @@ static bool rtc_hw_init(void) { u16 bbpu; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_INIT); udelay(500); - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_BBPU, &bbpu); if (bbpu & RTC_BBPU_INIT) { diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 54b2f2d5a35..7811eb5063f 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -17,12 +17,9 @@ /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) { - u16 bbpu, con, osc32con, sec; + u16 con, osc32con, sec; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD)) { rtc_info("rtc_write_trigger() failed\n"); return false; } @@ -54,8 +51,6 @@ static bool rtc_enable_dcxo(void) /* Initialize RTC related gpio */ bool rtc_gpio_init(void) { - u16 con; - /* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */ pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3); @@ -63,24 +58,19 @@ bool rtc_gpio_init(void) pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); /* Export 32K clock RTC_32K2V8 */ - rtc_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN - | RTC_CON_XOSC32_LPEN); - con |= (RTC_CON_GPEN | RTC_CON_GOE); - con &= ~RTC_CON_F32KOB; - rtc_write(RTC_CON, con); - - return rtc_write_trigger(); + u16 mask = (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN | + RTC_CON_XOSC32_LPEN); + return rtc_clrset_trigger(RTC_CON, + (u16)(~mask) | RTC_CON_F32KOB, + RTC_CON_GPEN | RTC_CON_GOE); } u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { - u16 bbpu, osc32con; + u16 osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD)) { rtc_info("rtc_write_trigger() failed\n"); return false; } @@ -153,13 +143,10 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) /* Low power detect setting */ static bool rtc_lpd_init(void) { - u16 con, sec; + u16 con; /* Set RTC_LPD_OPT */ - rtc_read(RTC_AL_SEC, &sec); - sec |= RTC_LPD_OPT_F32K_CK_ALIVE; - rtc_write(RTC_AL_SEC, sec); - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_AL_SEC, 0, RTC_LPD_OPT_F32K_CK_ALIVE)) { rtc_info("rtc_write_trigger() failed\n"); return false; } @@ -181,11 +168,7 @@ static bool rtc_lpd_init(void) rtc_write(RTC_CON, con); /* Set RTC_LPD_OPT */ - rtc_read(RTC_AL_SEC, &sec); - sec &= ~RTC_LPD_OPT_MASK; - sec |= RTC_LPD_OPT_EOSC_LPD; - rtc_write(RTC_AL_SEC, sec); - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_AL_SEC, RTC_LPD_OPT_MASK, RTC_LPD_OPT_EOSC_LPD)) { rtc_info("rtc_write_trigger() failed\n"); return false; } @@ -197,18 +180,14 @@ static bool rtc_hw_init(void) { u16 bbpu; - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_INIT)) { rtc_info("rtc_write_trigger() failed\n"); return false; } udelay(500); - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD)) { rtc_info("rtc_write_trigger() failed\n"); return false; } diff --git a/src/soc/mediatek/mt8189/dptx_hal.c b/src/soc/mediatek/mt8189/dptx_hal.c index 3fa3955f558..c079be94552 100644 --- a/src/soc/mediatek/mt8189/dptx_hal.c +++ b/src/soc/mediatek/mt8189/dptx_hal.c @@ -11,7 +11,7 @@ #include #include -void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) +void dptx_hal_reset_swing_preemphasis(const struct mtk_dp *mtk_dp) { u32 mask = EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK | EDP_TX_LN_VOLT_SWING_EN_MASK | EDP_TX_LN_PRE_EMPH_EN_MASK; @@ -21,7 +21,7 @@ void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], value, mask); } -void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count) +void dptx_hal_phy_set_lanes(const struct mtk_dp *mtk_dp, u8 lane_count) { mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x44, GENMASK(4 + lane_count - 1, 4), GENMASK(7, 4)); diff --git a/src/soc/mediatek/mt8192/srclken_rc.c b/src/soc/mediatek/mt8192/srclken_rc.c index 0c5b8896d97..0d419936334 100644 --- a/src/soc/mediatek/mt8192/srclken_rc.c +++ b/src/soc/mediatek/mt8192/srclken_rc.c @@ -114,14 +114,14 @@ static struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = { [CHN_RESERVE] = SUB_CTRL_CON(0x0, 0x0, 0x1, DXCO_SETTLE_BLK_DIS), }; -static void pmic_read(u32 addr, u32 *rdata) +static void pmic_read(u32 addr, u16 *rdata) { static struct pmif *pmif_arb; if (!pmif_arb) pmif_arb = get_pmif_controller(PMIF_SPI, 0); - pmif_arb->read(pmif_arb, 0, addr, rdata); + pmif_arb->read16(pmif_arb, 0, addr, rdata); } static void rc_dump_reg_info(void) @@ -352,7 +352,6 @@ int srclken_rc_init(void) for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { unsigned int chk_sta, shift_chn_n = 0; int retry; - u32 temp; /* Fix RC_MXX_REQ_STA_0 register shift */ if (chn_n > 0) @@ -365,6 +364,7 @@ int srclken_rc_init(void) != chk_sta && retry-- > 0) udelay(10); if (retry < 0) { + u16 temp; pmic_read(PMIC_PMRC_CON0, &temp); rc_info("polling M%02d failed.(R:%#x)(C:%#x)(PMRC:%#x)\n", chn_n, diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c index 9fe85712311..9f98d42b4e8 100644 --- a/src/soc/mediatek/mt8196/dptx_hal.c +++ b/src/soc/mediatek/mt8196/dptx_hal.c @@ -6,14 +6,14 @@ #include #include -void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) +void dptx_hal_reset_swing_preemphasis(const struct mtk_dp *mtk_dp) { for (int i = 0; i < dptx_hal_driving_offset_size; i++) mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], 0, EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK); } -void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count) +void dptx_hal_phy_set_lanes(const struct mtk_dp *mtk_dp, u8 lane_count) { for (int i = 0; i < lane_count; i++) mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x74, BIT(i), BIT(i)); diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 48f4dc77ce2..6d66fce4b10 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -69,6 +69,7 @@ SECTIONS RAMSTAGE(0x80300000, 2M) OPTEE_BUF(0x80500000, 70M) FSP_RAMSTAGE_INIT_CODE(0x90000000, 2M) + FRAMEBUFFER(0x90200000, 32M) BL31(0x94600000, 0x200000) @@ -76,5 +77,4 @@ SECTIONS RESV_MEMORY_GPUEB(0xA0000000, 2M) /* Reserved memory for the dedicated secured memory allocator of GPU Mali firmware */ GPU_SEC_BUF(0xA2000000, 16M) - FRAMEBUFFER(0xBEC00000, 32M) } diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c index 9837df4e59b..a030eadaedc 100644 --- a/src/soc/mediatek/mt8196/mt6685_rtc.c +++ b/src/soc/mediatek/mt8196/mt6685_rtc.c @@ -78,11 +78,9 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) u16 fqmtr_data; if (val != 0) { - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_OSC32CON, &rdata); - osc32con = rdata & 0xFFE0; + osc32con = rdata & ~RTC_XOSCCALI_MASK; rtc_xosc_write(osc32con | (val & RTC_XOSCCALI_MASK)); } @@ -195,30 +193,14 @@ static bool rtc_frequency_meter_check(void) return true; } -static bool rtc_clrset_trigger(u16 addr, u16 clr_bits, u16 set_bits) -{ - u16 rdata; - - rtc_read(addr, &rdata); - - rdata &= ~clr_bits; - rdata |= set_bits; - - rtc_write(addr, rdata); - - return rtc_write_trigger(); -} - bool rtc_gpio_init(void) { /* GPI mode and pull enable + pull down */ - rtc_clrset_trigger(RTC_CON, - (u16)(~(RTC_CON_LPSTA_RAW | RTC_CON_LPRST | - RTC_XOSC32_LPEN | RTC_EOSC32_LPEN) | - RTC_CON_GPU | RTC_CON_F32KOB), - RTC_CON_GPEN | RTC_CON_GOE); - - return rtc_write_trigger(); + u16 mask = (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_XOSC32_LPEN | + RTC_EOSC32_LPEN); + return rtc_clrset_trigger(RTC_CON, + (u16)(~mask) | RTC_CON_GPU | RTC_CON_F32KOB, + RTC_CON_GPEN | RTC_CON_GOE); } static bool rtc_hw_init(void) @@ -228,18 +210,14 @@ static bool rtc_hw_init(void) stopwatch_init_usecs_expire(&sw, BBPU_RELOAD_TIMEOUT_US); - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, - rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | - (RTC_BBPU_RESET_SPAR & (~RTC_BBPU_SPAR_SW))); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, + RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | + (RTC_BBPU_RESET_SPAR & (~RTC_BBPU_SPAR_SW))); do { - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); - rtc_read(RTC_BBPU, &rdata); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_read(RTC_BBPU, &rdata); if (!(rdata & (RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR))) return true; @@ -282,9 +260,7 @@ static bool rtc_lpd_init(void) printk(BIOS_INFO, "%s: RTC_CON=%#x\n", __func__, rdata); /* bit 7 for low power detected in preloader */ - rtc_read(RTC_CON, &rdata); - rtc_write(RTC_SPAR0, rdata | RTC_PDN1_PWRON_TIME); - if (!rtc_write_trigger()) + if (!rtc_clrset_trigger(RTC_SPAR0, 0, RTC_PDN1_PWRON_TIME)) return false; return true; @@ -389,9 +365,7 @@ static bool rtc_first_boot_init(void) u16 rdata; printk(BIOS_INFO, "%s: Enter\n", __func__); - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR); - if (!rtc_write_trigger()) + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR)) return false; if (!mt6685_writeif_unlock()) { @@ -421,10 +395,7 @@ static bool rtc_first_boot_init(void) return false; } - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR); - - if (!rtc_write_trigger()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR)) { printk(BIOS_ERR, "%s rtc_write_trigger failed after BBPU written\n", __func__); return false; @@ -475,26 +446,17 @@ static void rtc_enable_dcxo(void) if (!mt6685_writeif_unlock()) printk(BIOS_ERR, "mt6685_writeif_unlock() failed\n"); - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); - rtc_read(RTC_OSC32CON, &rdata); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_read(RTC_OSC32CON, &rdata); /* 0: f32k_ck src = dcxo_ck */ rtc_xosc_write(rdata & ~RTC_EMBCK_SRC_SEL); - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); - - rtc_read(RTC_CON, &rdata); - con = rdata; - - rtc_read(RTC_OSC32CON, &rdata); - osc32con = rdata; + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_read(RTC_AL_SEC, &rdata); - sec = rdata; + rtc_read(RTC_CON, &con); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_read(RTC_AL_SEC, &sec); printk(BIOS_INFO, "%s con = %#x, osc32con = %#x, sec = %#x\n", __func__, con, osc32con, sec); @@ -550,10 +512,8 @@ void rtc_boot(void) rtc_bbpu, rtc_con, rtc_osc32con, rtc_al_sec, rtc_al_yea); - rtc_read(RTC_BBPU, &rtc_bbpu); - rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - - if (!rtc_write_trigger() || !mt6685_writeif_unlock()) { + if (!rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD) || + !mt6685_writeif_unlock()) { rtc_recovery_flow(); } else { rtc_read(RTC_POWERKEY1, &rtc_pwrkey1); @@ -571,14 +531,10 @@ void rtc_boot(void) } /* Set RTC EOSC calibration period = 8sec */ - rtc_read(RTC_AL_DOW, &rdata); - rtc_write(RTC_AL_DOW, rdata | RTC_EOSC_CALI_TD_8SEC); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_AL_DOW, 0, RTC_EOSC_CALI_TD_8SEC); /* Make sure RTC get the latest register info. */ - rtc_read(RTC_BBPU, &rtc_bbpu); - rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); /* HW K EOSC mode whatever power off (including plug out battery) */ rtc_read(RTC_AL_YEA, &rtc_al_yea); @@ -612,21 +568,16 @@ void rtc_boot(void) RG_RTC_EOSC32_CK_PDN_MASK, RG_RTC_EOSC32_CK_PDN_SHIFT); /* Set register to let MD know 32k status */ - rtc_read(RTC_SPAR0, &rdata); - rtc_write(RTC_SPAR0, (rdata & ~RTC_SPAR0_32K_LESS)); - printk(BIOS_INFO, "32k-less mode\n"); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_SPAR0, RTC_SPAR0_32K_LESS, 0); - rtc_read(RTC_BBPU, &rtc_bbpu); - rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); /* Clear ONESHOT bit to solve alarm issue */ + rtc_clrset_trigger(RTC_IRQ_EN, RTC_IRQ_EN_ONESHOT, 0); + rtc_read(RTC_IRQ_EN, &rdata); - rtc_write(RTC_IRQ_EN, rdata & ~RTC_IRQ_EN_ONESHOT); - rtc_write_trigger(); - rtc_read(RTC_IRQ_EN, &rdata); + printk(BIOS_INFO, "check RTC_IRQ_EN = %#x\n", rdata); if (need_secure_rtc_set_ck) @@ -636,9 +587,7 @@ void rtc_boot(void) static void rtc_get_tick(struct rtc_time *tm) { u16 rdata; - rtc_read(RTC_BBPU, &rdata); - rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); + rtc_clrset_trigger(RTC_BBPU, 0, RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_read(RTC_TC_SEC, &rdata); tm->sec = rdata; diff --git a/src/soc/mediatek/mt8196/pmif_init.c b/src/soc/mediatek/mt8196/pmif_init.c index a6151bba23e..8d37056ac16 100644 --- a/src/soc/mediatek/mt8196/pmif_init.c +++ b/src/soc/mediatek/mt8196/pmif_init.c @@ -18,8 +18,8 @@ const struct pmif pmif_spmi_arb[] = { .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN_P, .mstid = SPMI_MASTER_0, .pmifid = PMIF_SPMI, - .write = pmif_spmi_write, - .read = pmif_spmi_read, + .write8 = pmif_spmi_write8, + .read8 = pmif_spmi_read8, .write16 = pmif_spmi_write16, .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, @@ -30,8 +30,8 @@ const struct pmif pmif_spmi_arb[] = { .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN, .mstid = SPMI_MASTER_1, .pmifid = PMIF_SPMI, - .write = pmif_spmi_write, - .read = pmif_spmi_read, + .write8 = pmif_spmi_write8, + .read8 = pmif_spmi_read8, .write16 = pmif_spmi_write16, .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, @@ -42,8 +42,8 @@ const struct pmif pmif_spmi_arb[] = { .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN_P, .mstid = SPMI_MASTER_2, .pmifid = PMIF_SPMI, - .write = pmif_spmi_write, - .read = pmif_spmi_read, + .write8 = pmif_spmi_write8, + .read8 = pmif_spmi_read8, .write16 = pmif_spmi_write16, .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, @@ -59,8 +59,8 @@ const struct pmif pmif_spi_arb[] = { .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, .ch = (struct chan_regs *)PMIF_SPI_AP_CHAN, .pmifid = PMIF_SPI, - .write = pmif_spi_write, - .read = pmif_spi_read, + .write16 = pmif_spi_write16, + .read16 = pmif_spi_read16, .write_field = pmif_spi_write_field, .read_field = pmif_spi_read_field, .check_init_done = pmif_check_init_done, diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index 5b395e3c233..f7fe4c28551 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include #include #include #include @@ -163,9 +164,9 @@ void pmif_spmi_iocfg(void) static int spmi_read_check(struct pmif *arb, const struct spmi_device *dev) { - u32 rdata = 0; + u8 rdata = 0; - arb->read(arb, dev->slvid, dev->hwcid_addr, &rdata); + arb->read8(arb, dev->slvid, dev->hwcid_addr, &rdata); if ((rdata & dev->hwcid_mask) != (dev->hwcid_val & dev->hwcid_mask)) { printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x\n", __func__, dev->slvid, rdata); @@ -216,15 +217,16 @@ static int spmi_cali_rd_clock_polarity(struct pmif *arb, const struct spmi_devic static int spmi_config_slave(struct pmif *arb, const struct spmi_device *dev) { - u32 wdata; + u8 wdata; /* set RG_RCS_ADDR=slave id */ - wdata = dev->slvid; - arb->write(arb, dev->slvid, 0x419, wdata); /* rcs_slvid_addr: 0x419 */ + wdata = (u8)dev->slvid; + arb->write8(arb, dev->slvid, 0x419, wdata); /* rcs_slvid_addr: 0x419 */ /* set RG_RCS_ENABLE=1, RG_RCS_ID=Master ID */ - wdata = 0x5 | (dev->mstid << 4); - arb->write(arb, dev->slvid, 0x418, wdata); /* rcs_slvid_en: 0x418 */ + assert(dev->mstid <= 1); + wdata = 0x5 | (u8)(dev->mstid << 4); + arb->write8(arb, dev->slvid, 0x418, wdata); /* rcs_slvid_en: 0x418 */ return 0; } diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 1e228c8a54b..345a3096448 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -87,7 +86,6 @@ static void soc_init(struct device *dev) sspm_init(); gpueb_init(); mcupm_init(); - mt6685_init_pmif_arb(); /* * According to CI-700 documentation: * Registers are only accessible by Secure accesses. Writes to them must occur prior to @@ -124,6 +122,7 @@ static void enable_soc_dev(struct device *dev) } else { printk(BIOS_DEBUG, "Skip setting PCIe ops\n"); dev->ops = &noop_domain_ops; + dev->enabled = 0; } } } diff --git a/src/soc/qualcomm/calypso/Kconfig b/src/soc/qualcomm/calypso/Kconfig new file mode 100644 index 00000000000..fdfe4e62e05 --- /dev/null +++ b/src/soc/qualcomm/calypso/Kconfig @@ -0,0 +1,94 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_QUALCOMM_CALYPSO_BASE + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select ARM64_USE_ARM_TRUSTED_FIRMWARE + select CACHE_MRC_SETTINGS + select CBFS_PRELOAD + select COOP_MULTITASKING + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_SD + select FIXED_UART_FOR_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAS_RECOVERY_MRC_CACHE + select HAVE_LINEAR_FRAMEBUFFER + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select NO_ECAM_MMCONF_SUPPORT + select PCI + select SOC_QUALCOMM_COMMON + select SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE + +config SOC_QUALCOMM_CALYPSO + bool + select SOC_QUALCOMM_CALYPSO_BASE + select QMP_PHY_PCIE5_1X4 + default n + help + Choose this option if the mainboard is built using Calypso system-on-a-chip SoC. + +if SOC_QUALCOMM_CALYPSO_BASE + +config QC_BLOBS_UPSTREAM + bool "QC blobs are available in upstream repository" + select USE_QC_BLOBS + default n + help + Select based on availability of QC blobs in upstream coreboot `3rdparty/qc_blobs`. + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/calypso/memlayout.ld" + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 26 + +config UART_FOR_CONSOLE + int + default 21 # QUP2_SE5 + help + Select the QUP instance to be used for UART console output. + +config UART_BITBANG_TX_DELAY_MS + int + default 1 + +config SPI_FREQ_25MHZ + def_bool n + +config SPI_FREQ_50MHZ + def_bool n + +config SPI_FREQ_75MHZ + def_bool n + +config SPI_FREQ_100MHZ + def_bool n + +config SOC_SPI_FREQ_MHZ + int + default 25 if SPI_FREQ_25MHZ + default 50 if SPI_FREQ_50MHZ + default 75 if SPI_FREQ_75MHZ + default 100 if SPI_FREQ_100MHZ + default 50 + help + Supported SPI Frequency for Hamoa/X1P42100 Platforms + +endif diff --git a/src/soc/qualcomm/calypso/Makefile.mk b/src/soc/qualcomm/calypso/Makefile.mk new file mode 100644 index 00000000000..23b29e2df28 --- /dev/null +++ b/src/soc/qualcomm/calypso/Makefile.mk @@ -0,0 +1,409 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y) + +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += ../common/timer.c +all-y += ../common/timer.c +all-y += ../common/gpio.c +all-y += ../common/clock.c +all-y += clock.c +all-y += ../common/spi.c +all-y += ../common/qspi.c +all-y += ../common/qupv3_config.c +all-y += qcom_qup_se.c +all-y += ../common/qup_se_handler.c +all-y += ../common/qupv3_spi.c +all-y += ../common/qupv3_i2c.c +all-y += ../common/qupv3_spi.c + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c + +################################################################################ +verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += ../common/shrm_load_reset.c +romstage-y += cpucp_load_reset.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += ../common/watchdog.c +romstage-y += mmu.c +romstage-y += ../common/aop_load_reset.c +romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +romstage-$(CONFIG_SOC_QUALCOMM_CDT) += ../common/cdt.c +romstage-y += ../common/spmi.c +romstage-y += ../common/pmic_gpio.c +romstage-$(CONFIG_PCI) += pcie.c +ifeq ($(CONFIG_SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT),y) +romstage-$(CONFIG_PCI) += ../common/pcie_common.c +endif + +################################################################################ + +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += ../common/mmu.c +ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-$(CONFIG_PCI) += pcie.c +ramstage-$(CONFIG_PCI) += ../common/pcie_common.c +ramstage-y += cpucp_load_reset.c +ramstage-y += ../common/spmi.c +ramstage-y += ../common/pmic_gpio.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/calypso/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ +# look for QC blobs if QC SoC blobs are only available in upstream else ignore +ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y) +ifeq ($(CONFIG_USE_QC_BLOBS),y) +CALYPSO_BLOB := $(top)/3rdparty/qc_blobs/calypso + +ifeq ($(CONFIG_QC_SECURE_BOOT_BLOBS),y) +BLOB_VARIANT := secure +else +BLOB_VARIANT := non_secure +endif + +DTB_DCB_BLOB_PATH := calypso + +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +BL31_MAKEARGS += QTI_SDI_BUILD=1 +BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec_dbg.a +else +BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec.a +endif # CONFIG_QC_SDI_ENABLE + +ifeq ($(CONFIG_QC_QDUTT_ENABLE),y) +QCLIB_FILE := $(CALYPSO_BLOB)/QDUTT/boot/QcDdi.elf +DCB_FILE := $(CALYPSO_BLOB)/QDUTT/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin +SHRM_FILE := $(CALYPSO_BLOB)/QDUTT/$(BLOB_VARIANT)/shrm/shrm.elf +else +QCLIB_FILE := $(CALYPSO_BLOB)/boot/QcLib.elf +DCB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin +SHRM_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf +endif # CONFIG_QC_QDUTT_ENABLE + +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(CALYPSO_BLOB)/boot/QcSdi.elf +QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi +$(QCSDI_CBFS)-file := $(QCSDI_FILE) +$(QCSDI_CBFS)-type := stage +$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(QCSDI_CBFS) +endif + +################################################################################ +QC_SEC_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/qc_sec/qc_sec.mbn +TME_SEQ_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/sequencer_ram.elf +TME_FW_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/signed_firmware_soc_view.elf + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 7 -f $(objcbfs)/bootblock.raw.elf \ + -o $(objcbfs)/bootblock.mbn \ + -a 64 -c 64 + @util/qualcomm/create_multielf.py -f $(TME_SEQ_FILE),$(TME_FW_FILE),$(QC_SEC_FILE),$(objcbfs)/bootblock.mbn \ + -o $(objcbfs)/merged_bb.melf + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb.melf \ + $(objcbfs)/bootblock.bin + +################################################################################ +QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib +$(QCLIB_CBFS)-file := $(QCLIB_FILE) +$(QCLIB_CBFS)-type := stage +# FIXME: b/511898023 +$(QCLIB_CBFS)-compression := none +cbfs-files-y += $(QCLIB_CBFS) + +################################################################################ +DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb +$(DCB_CBFS)-file := $(DCB_FILE) +$(DCB_CBFS)-type := raw +$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS) + +################################################################################ +DELTA_DCB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/delta_dcb.bin +DELTA_DCB_CBFS := $(CONFIG_CBFS_PREFIX)/delta_dcb +$(DELTA_DCB_CBFS)-file := $(DELTA_DCB_FILE) +$(DELTA_DCB_CBFS)-type := raw +$(DELTA_DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DELTA_DCB_CBFS) + +################################################################################ +DTB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/pre-ddr.dtb +DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb +$(DTB_CBFS)-file := $(DTB_FILE) +$(DTB_CBFS)-type := raw +$(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DTB_CBFS) + +################################################################################ +CPR_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin +CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr +$(CPR_CBFS)-file := $(CPR_FILE) +$(CPR_CBFS)-type := raw +$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(CPR_CBFS) + +################################################################################ +UART_FW_FILE := $(CALYPSO_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := none +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := none +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(CALYPSO_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := none +cbfs-files-y += $(I2C_FW_CBFS) + +################################################################################ +AOP_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn +AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop +$(AOP_CBFS)-file := $(AOP_FILE) +$(AOP_CBFS)-type := payload +$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CBFS) + +################################################################################ +# Rule to create aop_meta from aop.mbn +# This rule depends on aop.mbn built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +AOP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_meta +AOP_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_meta +$(AOP_META_CBFS)-file := $(AOP_META_FILE) +$(AOP_META_CBFS)-type := raw +$(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_META_CBFS) + +################################################################################ +AOP_CFG_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn +AOP_CFG_CBFS := $(CONFIG_CBFS_PREFIX)/aop_cfg +$(AOP_CFG_CBFS)-file := $(AOP_CFG_FILE) +$(AOP_CFG_CBFS)-type := payload +$(AOP_CFG_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CFG_CBFS) + +################################################################################ +# Rule to create aop_meta from aop_devcfg.mbn +# This rule depends on aop_devcfg.mbn built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +AOP_DEVCFG_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta +AOP_DEVCFG_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_devcfg_meta +$(AOP_DEVCFG_META_CBFS)-file := $(AOP_DEVCFG_META_FILE) +$(AOP_DEVCFG_META_CBFS)-type := raw +$(AOP_DEVCFG_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_DEVCFG_META_CBFS) + +################################################################################ +CPUCP_FILE := $(CALYPSO_BLOB)/cpucp/cpucp.elf + +CPUCP_CBFS_RW := $(CONFIG_CBFS_PREFIX)/cpucp_rw +regions-for-file-$(CPUCP_CBFS_RW) = FW_MAIN_A,FW_MAIN_B +$(CPUCP_CBFS_RW)-file := $(CPUCP_FILE) +$(CPUCP_CBFS_RW)-type := payload +$(CPUCP_CBFS_RW)-compression := none +cbfs-files-y += $(CPUCP_CBFS_RW) + +CPUCP_CBFS_RO := $(CONFIG_CBFS_PREFIX)/cpucp_ro +regions-for-file-$(CPUCP_CBFS_RO) = COREBOOT +$(CPUCP_CBFS_RO)-file := $(CPUCP_FILE) +$(CPUCP_CBFS_RO)-type := payload +$(CPUCP_CBFS_RO)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_CBFS_RO) + +################################################################################ +# Rule to create cpucp_meta from cpucp.elf +# This rule depends on cpucp.elf being built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta: $(CALYPSO_BLOB)/cpucp/cpucp.elf util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +CPUCP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta +CPUCP_META_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_meta +$(CPUCP_META_CBFS)-file := $(CPUCP_META_FILE) +$(CPUCP_META_CBFS)-type := raw +$(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_META_CBFS) + +################################################################################ +CPUCP_DTBS_FILE := $(CALYPSO_BLOB)/cpucp/cpucp_dtbs.elf +CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs +$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE) +$(CPUCP_DTBS_CBFS)-type := payload +$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_DTBS_CBFS) + +################################################################################ +PDP_FILE := $(CALYPSO_BLOB)/pdp/pdp.elf + +PDP_CBFS_RW := $(CONFIG_CBFS_PREFIX)/pdp_rw +regions-for-file-$(PDP_CBFS_RW) = FW_MAIN_A,FW_MAIN_B +$(PDP_CBFS_RW)-file := $(PDP_FILE) +$(PDP_CBFS_RW)-type := payload +$(PDP_CBFS_RW)-compression := none +cbfs-files-y += $(PDP_CBFS_RW) + +PDP_CBFS_RO := $(CONFIG_CBFS_PREFIX)/pdp_ro +regions-for-file-$(PDP_CBFS_RO) = COREBOOT +$(PDP_CBFS_RO)-file := $(PDP_FILE) +$(PDP_CBFS_RO)-type := payload +$(PDP_CBFS_RO)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(PDP_CBFS_RO) + +################################################################################ +PDP_CDB_FILE := $(CALYPSO_BLOB)/pdp/pdp_cdb.elf +PDP_CDB_CBFS := $(CONFIG_CBFS_PREFIX)/pdp_cdb +$(PDP_CDB_CBFS)-file := $(PDP_CDB_FILE) +$(PDP_CDB_CBFS)-type := payload +$(PDP_CDB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(PDP_CDB_CBFS) + +################################################################################ +SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm +$(SHRM_CBFS)-file := $(SHRM_FILE) +$(SHRM_CBFS)-type := payload +$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(SHRM_CBFS) + +################################################################################ +# Rule to create shrm_meta from shrm.elf +# This rule depends on shrm.elf being built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(SHRM_FILE) util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +SHRM_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta +SHRM_META_CBFS := $(CONFIG_CBFS_PREFIX)/shrm_meta +$(SHRM_META_CBFS)-file := $(SHRM_META_FILE) +$(SHRM_META_CBFS)-type := raw +$(SHRM_META_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(SHRM_META_CBFS) + +################################################################################ +GSI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/gsi_fw.bin +GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw +$(GSI_FW_CBFS)-file := $(GSI_FW_FILE) +$(GSI_FW_CBFS)-type := raw +$(GSI_FW_CBFS)-compression := none +cbfs-files-y += $(GSI_FW_CBFS) + +################################################################################ +ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y) + +DEVCFG_TZ_FILE := $(CALYPSO_BLOB)/qtee/tz_oem_config.mbn +DEVCFG_TZ_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzoem_cfg +$(DEVCFG_TZ_FILE_CBFS)-file := $(DEVCFG_TZ_FILE) +$(DEVCFG_TZ_FILE_CBFS)-type := payload +$(DEVCFG_TZ_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DEVCFG_TZ_FILE_CBFS) + +################################################################################ +TZQTI_CFG_FILE := $(CALYPSO_BLOB)/qtee/tz_qti_config.mbn +TZQTI_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzqti_cfg +$(TZQTI_CFG_FILE_CBFS)-file := $(TZQTI_CFG_FILE) +$(TZQTI_CFG_FILE_CBFS)-type := payload +$(TZQTI_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(TZQTI_CFG_FILE_CBFS) + +################################################################################ +TZAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/tz_ac_config.elf +TZAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzac_cfg +$(TZAC_CFG_FILE_CBFS)-file := $(TZAC_CFG_FILE) +$(TZAC_CFG_FILE_CBFS)-type := payload +$(TZAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(TZAC_CFG_FILE_CBFS) + +################################################################################ +HYPAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/hyp_ac_config.elf +HYPAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/hypac_cfg +$(HYPAC_CFG_FILE_CBFS)-file := $(HYPAC_CFG_FILE) +$(HYPAC_CFG_FILE_CBFS)-type := payload +$(HYPAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(HYPAC_CFG_FILE_CBFS) + +endif # ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y) +################################################################################ +ifeq ($(CONFIG_QC_APDP_ENABLE),y) + +APDP_FILE := $(CALYPSO_BLOB)/qtee/apdp.mbn +APDP_CBFS := $(CONFIG_CBFS_PREFIX)/apdp +$(APDP_CBFS)-file := $(APDP_FILE) +$(APDP_CBFS)-type := payload +$(APDP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(APDP_CBFS) + +################################################################################ +# Rule to create apdp_meta from apdp.mbn +# This rule depends on apdp.mbn being built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/apdp/apdp.mbn util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +APDP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta +APDP_META_CBFS := $(CONFIG_CBFS_PREFIX)/apdp_meta +$(APDP_META_CBFS)-file := $(APDP_META_FILE) +$(APDP_META_CBFS)-type := raw +$(APDP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(APDP_META_CBFS) + +endif # ifeq ($(CONFIG_QC_APDP_ENABLE),y) +################################################################################ +ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y) + +RAMDUMP_FILE := $(CALYPSO_BLOB)/boot/XblRamdump.elf +RAMDUMP_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump +$(RAMDUMP_CBFS)-file := $(RAMDUMP_FILE) +$(RAMDUMP_CBFS)-type := stage +$(RAMDUMP_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(RAMDUMP_CBFS) + +################################################################################ +# Rule to create ramdump_meta from XblRamdump.elf +# This rule depends on XblRamdump.elf being built and the extractor script existing. +$(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta: $(CALYPSO_BLOB)/boot/XblRamdump.elf util/qualcomm/elf_segment_extractor.py + @echo "Extracting ELF headers and hash table segment from $< to $@" + @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ + +RAMDUMP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta +RAMDUMP_META_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump_meta +$(RAMDUMP_META_CBFS)-file := $(RAMDUMP_META_FILE) +$(RAMDUMP_META_CBFS)-type := raw +$(RAMDUMP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(RAMDUMP_META_CBFS) + +endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y) + +endif # ifeq ($(CONFIG_USE_QC_BLOBS),y) + +endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y) +endif # ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y) diff --git a/src/soc/qualcomm/calypso/bootblock.c b/src/soc/qualcomm/calypso/bootblock.c new file mode 100644 index 00000000000..b87066967db --- /dev/null +++ b/src/soc/qualcomm/calypso/bootblock.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define SPI_BUS_CLOCK_FREQ (CONFIG_SOC_SPI_FREQ_MHZ * MHz) + +void bootblock_soc_early_init(void) +{ + if (!CONFIG(COMPRESS_BOOTBLOCK)) + soc_mmu_init(); +} + +void bootblock_soc_init(void) +{ + clock_init(); + + quadspi_init(SPI_BUS_CLOCK_FREQ); + qupv3_fw_init(); +} diff --git a/src/soc/qualcomm/calypso/cbmem.c b/src/soc/qualcomm/calypso/cbmem.c new file mode 100644 index 00000000000..c2fb7838589 --- /dev/null +++ b/src/soc/qualcomm/calypso/cbmem.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)_dram_pil; +} diff --git a/src/soc/qualcomm/calypso/clock.c b/src/soc/qualcomm/calypso/clock.c new file mode 100644 index 00000000000..797222d39ff --- /dev/null +++ b/src/soc/qualcomm/calypso/clock.c @@ -0,0 +1,488 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static struct clock_freq_config qspi_core_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2MHz */ + .src = SRC_XO_19_2MHZ, + .div = QCOM_CLOCK_DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(6), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(4), + }, + { + .hz = 200 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(3), + }, + { + .hz = 300 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(2), + }, + { + .hz = 400 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(1.5), + }, +}; + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +/* Helper function to get SE index within a wrap */ +static inline int get_qup_se_index(int qup) +{ + return qup % QUP_WRAP1_S0; +} + +/* Helper function to get pointer to QUP SE clock structure */ +static void *get_qup_se_clk(int qup, int s) +{ + struct calypso_qupv3_wrap *wrap = NULL; + void *se_clk_array[8]; + + /* Determine which wrap based on qup value */ + if (qup <= QUP_WRAP0_S7) + wrap = qup_wrap0_clk; + else if (qup <= QUP_WRAP1_S7) + wrap = qup_wrap1_clk; + else if (qup <= QUP_WRAP2_S7) + wrap = qup_wrap2_clk; + else if (qup <= QUP_WRAP3_S1) + wrap = qup_oob_clk; + + if (!wrap) { + printk(BIOS_ERR, "%s: invalid QUP index %d\n", __func__, qup); + return NULL; + } + + /* Build array of pointers to SE clock structures */ + se_clk_array[0] = &wrap->qupv3_s0; + se_clk_array[1] = &wrap->qupv3_s1; + se_clk_array[2] = &wrap->qupv3_s2; + se_clk_array[3] = &wrap->qupv3_s3; + se_clk_array[4] = &wrap->qupv3_s4; + se_clk_array[5] = &wrap->qupv3_s5; + se_clk_array[6] = &wrap->qupv3_s6; + se_clk_array[7] = &wrap->qupv3_s7; + return se_clk_array[s]; +} + +void clock_enable_qup(int qup) +{ + int s = get_qup_se_index(qup), clk_en_off; + void *clk_br_en_ptr = NULL; + void *se_clk; + u32 *cbcr; + + if (qup <= QUP_WRAP0_S7) { + clk_en_off = QUPV3_WRAP0_CLK_ENA_S(s); + clk_br_en_ptr = &gcc->apcs_clk_br_en4; + } else if (qup <= QUP_WRAP1_S7) { + clk_en_off = QUPV3_WRAP1_CLK_ENA_S(s); + clk_br_en_ptr = &gcc->apcs_clk_br_en3; + } else if (qup <= QUP_WRAP2_S7) { + if (qup <= QUP_WRAP2_S1) { + clk_en_off = (qup == QUP_WRAP2_S0) ? + QUPV3_WRAP2_SE0_CLK_ENA : + QUPV3_WRAP2_SE1_CLK_ENA; + clk_br_en_ptr = &gcc->apcs_clk_br_en3; + } else { + clk_en_off = QUPV3_WRAP2_CLK_ENA_S(s); + clk_br_en_ptr = &gcc->apcs_clk_br_en4; + } + } else if (qup <= QUP_WRAP3_S1) { + clk_en_off = QUPV3_OOB_CLK_ENA_S(s); + clk_br_en_ptr = &gcc->apcs_clk_br_en3; + } + + se_clk = get_qup_se_clk(qup, s); + if (!se_clk) + return; + + if (s == 2 || s == 3) + cbcr = &((struct qupv3_clock_v2 *)se_clk)->cbcr; + else + cbcr = &((struct qupv3_clock *)se_clk)->cbcr; + + /* Only call if a valid pointer was assigned */ + if (clk_br_en_ptr) + clock_enable_vote(cbcr, clk_br_en_ptr, clk_en_off); +} + +void clock_configure_dfsr(int qup) +{ + /* placeholder */ +} + +enum cb_err pll_init_and_set(struct calypso_ncc0_clock *ncc0, u32 l_val) +{ + int ret; + struct alpha_pll_reg_val_config ncc0_pll_cfg = {0}; + + setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, + BIT(PLLSWCTL) | BIT(OVRCKMUXPLLFASTCLK)); + + setbits64p(NCC0_NCC_CMU_NCC_PLL_CFG, + ((uint64_t)(LOCKTMOUTCNT_VAL & LOCKTMOUTCNT_BMSK) + << LOCKTMOUTCNT) | + ((uint64_t)(LOCKDEASSERTTMOUTCNT_VAL & LOCKDEASSERTTMOUTCNT_BMSK) + << LOCKDEASSERTTMOUTCNT)); + + ncc0_pll_cfg.reg_config_ctl = &ncc0->pll0_config_ctl; + ncc0_pll_cfg.config_ctl_val = read32(ncc0_pll_cfg.reg_config_ctl) | + PFA_MSB_VAL << PFA_MSB | + RON_DEGEN_MULTIPLY_VAL << RON_DEGEN_MULTIPLY | + FBC_ALPHA_CAL_VAL << FBC_ALPHA_CAL | + PLL_COUNTER_ENABLE_VAL << PLL_COUNTER_ENABLE; + + ncc0_pll_cfg.reg_config_ctl_hi = &ncc0->pll0_config_ctl_u; + ncc0_pll_cfg.config_ctl_hi_val = read32(ncc0_pll_cfg.reg_config_ctl_hi) | + CHP_REF_CUR_TRIM_VAL << CHP_REF_CUR_TRIM | + ADC_KLSB_VALUE_VAL << ADC_KLSB_VALUE | + ADC_KMSB_VALUE_VAL << ADC_KMSB_VALUE; + + ncc0_pll_cfg.reg_l = &ncc0->pll0_l; + ncc0_pll_cfg.l_val = l_val; + + ncc0_pll_cfg.reg_alpha = &ncc0->pll0_alpha; + ncc0_pll_cfg.alpha_val = 0x00; + ncc0_pll_cfg.reg_user_ctl = &ncc0->pll0_user_ctl; + ncc0_pll_cfg.user_ctl_val = (1 << PLL_PLLOUT_EVEN_SHFT | + 1 << PLL_PLLOUT_MAIN_SHFT); + + if (clock_configure_enable_gpll(&ncc0_pll_cfg, false, 0) != CB_SUCCESS) + return CB_ERR; + + ncc0_pll_cfg.reg_mode = &ncc0->pll0_mode; + ncc0_pll_cfg.reg_opmode = &ncc0->pll0_opmode; + ret = zondaole_pll_enable(&ncc0_pll_cfg); + if (ret != CB_SUCCESS) + return CB_ERR; + + setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, BIT(SELCKMUXPLLFASTCLK)); + + return CB_SUCCESS; +} + +static enum cb_err clock_configure_gpll0(void) +{ + struct alpha_pll_reg_val_config gpll0_cfg = {0}; + + gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl; + gpll0_cfg.user_ctl_val = read32(gpll0_cfg.reg_user_ctl) | + BIT(PLL_PLLOUT_MAIN_SHFT_CALYPSO) | + BIT(PLL_PLLOUT_EVEN_SHFT_CALYPSO) | + BIT(PLL_PLLOUT_ODD_SHFT_CALYPSO) | + 1 << PLL_POST_DIV_EVEN_SHFT_CALYPSO | + 2 << PLL_POST_DIV_ODD_SHFT_CALYPSO; + + return clock_configure_enable_gpll(&gpll0_cfg, false, 0); +} + +static void speed_up_boot_cpu(void) +{ + /* 1363.2 MHz */ + if (pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz) == CB_SUCCESS) + printk(BIOS_DEBUG, "NCC frequency bumped to 1363.2 MHz\n"); + else + printk(BIOS_ERR, "NCC PLL initialization failed\n"); +} + +void clock_init(void) +{ + if (clock_configure_gpll0() != CB_SUCCESS) + printk(BIOS_ERR, "GPLL0 configuration failed\n"); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en4, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en4, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en4, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en4, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP_1_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap2_core_2x_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP2_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap2_core_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP2_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap2_m_ahb_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP_2_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap2_s_ahb_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_WRAP_2_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_oob_core_2x_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_OOB_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_oob_core_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_OOB_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_oob_s_ahb_cbcr, + &gcc->apcs_clk_br_en3, + QUPV3_OOB_S_AHB_CLK_ENA); + + speed_up_boot_cpu(); +} + +static struct pcie pcie_cfg[] = { + [GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK] = { + .clk = &gcc->pcie_5.aggre_noc_pcie_5_east_sf_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK_ENA, + }, + [GCC_AGGRE_NOC_PCIE_EAST_TUNNEL_AXI_CLK] = { + .clk = &gcc->pcie_noc.aggre_noc_pcie_east_tunnel_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en2, + .vote_bit = AGGRE_NOC_PCIE_EAST_TUNNEL_AXI_CLK_ENA, + }, + [GCC_AGGRE_NOC_PCIE_WEST_TUNNEL_AXI_CLK] = { + .clk = &gcc->pcie_noc.aggre_noc_pcie_west_tunnel_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en2, + .vote_bit = AGGRE_NOC_PCIE_WEST_TUNNEL_AXI_CLK_ENA, + }, + [GCC_ANOC_PCIE_PWRCTL_CLK] = { + .clk = &gcc->anoc_pcie_pwrctl_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = ANOC_PCIE_PWRCTL_CLK_ENA, + }, + [GCC_CNOC_PCIE_EAST_TUNNEL_CLK] = { + .clk = &gcc->pcie_noc.cnoc_pcie_east_tunnel_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = CNOC_PCIE_EAST_TUNNEL_CLK_ENA, + }, + [GCC_CNOC_PCIE_WEST_TUNNEL_CLK] = { + .clk = &gcc->pcie_noc.cnoc_pcie_west_tunnel_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = CNOC_PCIE_WEST_TUNNEL_CLK_ENA, + }, + [GCC_PCIE_LINK_XO_CLK] = { + .clk = &gcc->pcie_noc.pcie_link_xo_cbcr, + .vote_bit = NO_VOTE_BIT, + }, + [GCC_HSCNOC_PCIE_SF_QTC_CLK] = { + .clk = &gcc->pcie_noc.hscnoc_pcie_sf_qtc_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = HSCNOC_PCIE_SF_QTC_CLK_ENA, + }, + [GCC_HSCNOC_PCIE_SLAVE_SF_EAST_CLK] = { + .clk = &gcc->pcie_noc.hscnoc_pcie_slave_sf_east_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = HSCNOC_PCIE_SLAVE_SF_EAST_CLK_ENA, + }, + [GCC_HSCNOC_PCIE_SLAVE_SF_WEST_CLK] = { + .clk = &gcc->pcie_noc.hscnoc_pcie_slave_sf_west_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = HSCNOC_PCIE_SLAVE_SF_WEST_CLK_ENA, + }, + [GCC_PCIE_NOC_PWRCTL_CLK] = { + .clk = &gcc->pcie_noc.pcie_noc_pwrctl_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = PCIE_NOC_PWRCTL_CLK_ENA, + }, + [GCC_PCIE_NOC_SF_CENTER_CLK] = { + .clk = &gcc->pcie_noc.pcie_noc_sf_center_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = PCIE_NOC_SF_CENTER_CLK_ENA, + }, + [GCC_PCIE_NOC_SLAVE_SF_EAST_CLK] = { + .clk = &gcc->pcie_noc.pcie_noc_slave_sf_east_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = PCIE_NOC_SLAVE_SF_EAST_CLK_ENA, + }, + [GCC_PCIE_NOC_SLAVE_SF_WEST_CLK] = { + .clk = &gcc->pcie_noc.pcie_noc_slave_sf_west_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = PCIE_NOC_SLAVE_SF_WEST_CLK_ENA, + }, + [GCC_SMMU_PCIE_QTC_AT_CLK] = { + .clk = &gcc->smmu_pcie_qtc_at_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = SMMU_PCIE_QTC_AT_CLK_ENA, + }, + [GCC_TCU_PCIE_SF_QTC_CLK] = { + .clk = &gcc->pcie_noc.tcu_pcie_sf_qtc_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = TCU_PCIE_SF_QTC_CLK_ENA, + }, + [GCC_TRACE_NOC_PCIE_3B_AT_CLK] = { + .clk = &gcc->pcie_noc.trace_noc_pcie_3b_at_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en2, + .vote_bit = TRACE_NOC_PCIE_3B_AT_CLK_ENA, + }, + [GCC_TRACE_NOC_PCIE_5_AT_CLK] = { + .clk = &gcc->pcie_noc.trace_noc_pcie_5_at_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en2, + .vote_bit = TRACE_NOC_PCIE_5_AT_CLK_ENA, + }, + [GCC_TRACE_NOC_TCU_PCIE_QTC_AT_CLK] = { + .clk = &gcc->trace_noc_tcu_pcie_qtc_at_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en2, + .vote_bit = TRACE_NOC_TCU_PCIE_QTC_AT_CLK_ENA, + }, + [GCC_PCIE_5_AT_CLK] = { + .clk = &gcc->pcie_5.at_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_AT_CLK_ENA, + }, + [GCC_PCIE_5_AUX_CLK] = { + .clk = &gcc->pcie_5.aux_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_AUX_CLK_ENA, + }, + [GCC_PCIE_5_CFG_AHB_CLK] = { + .clk = &gcc->pcie_5_cfg_ahb_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_CFG_AHB_CLK_ENA, + }, + [GCC_PCIE_5_MSTR_AXI_CLK] = { + .clk = &gcc->pcie_5.mstr_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_MSTR_AXI_CLK_ENA, + }, + [GCC_PCIE_5_PHY_RCHNG_CLK] = { + .clk = &gcc->pcie_5.phy_rchng_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_PHY_RCHNG_CLK_ENA, + }, + [GCC_PCIE_5_PIPE_DIV2_CLK] = { + .clk = &gcc->pcie_5.pipe_div2_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_PIPE_DIV2_CLK_ENA, + }, + [GCC_PCIE_5_SLV_AXI_CLK] = { + .clk = &gcc->pcie_5.slv_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_SLV_AXI_CLK_ENA, + }, + [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = { + .clk = &gcc->pcie_5.slv_q2a_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_SLV_Q2A_AXI_CLK_ENA, + }, + [GCC_PCIE_PHY_5_AUX_CLK] = { + .clk = &gcc->pcie_phy_5_aux_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_PHY_5_AUX_CLK_ENA, + }, + [GCC_PCIE_5_PIPE_CLK] = { + .clk = &gcc->pcie_5.pipe_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = PCIE_5_PIPE_CLK_ENA, + }, + [GCC_PCIE_5_PIPE_MUXR] = { + .clk = &gcc->pcie_5.pipe_muxr, + .vote_bit = NO_VOTE_BIT, + }, + [GCC_QMIP_PCIE_5_AHB_CLK] = { + .clk = &gcc->pcie_5.qmip_pcie_5_ahb_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en6, + .vote_bit = QMIP_PCIE_5_AHB_CLK_ENA, + }, +}; + +static u32 *gdsc_regs[MAX_GDSC] = { + [PCIE_5_GDSC] = &gcc->pcie_5.gdscr, + [PCIE_5_PHY_GDSC] = &gcc->pcie_phy_5_gdscr, +}; + +enum cb_err clock_enable_pcie(enum clk_pcie clk_type) +{ + int clk_vote_bit; + + if (clk_type >= PCIE_CLK_COUNT) { + printk(BIOS_ERR, "%s: invalid PCIe clock %d\n", __func__, clk_type); + return CB_ERR; + } + + clk_vote_bit = pcie_cfg[clk_type].vote_bit; + if (clk_vote_bit < 0) + return clock_enable(pcie_cfg[clk_type].clk); + + return clock_enable_vote(pcie_cfg[clk_type].clk, + pcie_cfg[clk_type].clk_br_en, pcie_cfg[clk_type].vote_bit); +} + +enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type) +{ + if (clk_type >= PCIE_CLK_COUNT) + return CB_ERR; + + /* Set clock src */ + write32(pcie_cfg[clk_type].clk, src_type); + + return CB_SUCCESS; +} + +enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type) +{ + if (gdsc_type >= MAX_GDSC) { + printk(BIOS_ERR, "%s: invalid GDSC %d\n", __func__, gdsc_type); + return CB_ERR; + } + + return enable_and_poll_gdsc_status(gdsc_regs[gdsc_type]); +} + +/* Configure gcc_pcie_5_phy_rchng_clk to 100 MHz */ +static struct clock_freq_config pcie5_phy_rchng_cfg[] = { + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(6), + }, +}; + +enum cb_err clock_configure_pcie(void) +{ + enum cb_err ret; + + /* Configure the RCG to 100 MHz */ + ret = clock_configure(&gcc->pcie_5.phy_rchng_rcg, pcie5_phy_rchng_cfg, + 100 * MHz, ARRAY_SIZE(pcie5_phy_rchng_cfg)); + if (ret != CB_SUCCESS) { + printk(BIOS_ERR, "%s: failed to configure PCIE5 PHY RCHNG clock\n", + __func__); + } + + return ret; +} diff --git a/src/soc/qualcomm/calypso/cpucp_load_reset.c b/src/soc/qualcomm/calypso/cpucp_load_reset.c new file mode 100644 index 00000000000..1baa99c8b2f --- /dev/null +++ b/src/soc/qualcomm/calypso/cpucp_load_reset.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void pdp_fw_load(void) +{ + const char *pdp_name = (CONFIG(VBOOT) && !vboot_recovery_mode_enabled()) + ? CONFIG_CBFS_PREFIX "/pdp_rw" + : CONFIG_CBFS_PREFIX "/pdp_ro"; + + struct prog pdp_fw_prog = PROG_INIT(PROG_PAYLOAD, pdp_name); + + if (!selfload(&pdp_fw_prog)) + die("SOC image: 'pdp' load failed"); + printk(BIOS_DEBUG, "SOC image: 'pdp' loaded successfully.\n"); + + struct prog pdp_cdb_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/pdp_cdb"); + + if (!selfload(&pdp_cdb_fw_prog)) + die("SOC image: 'pdp_cdb' load failed"); + printk(BIOS_DEBUG, "SOC image: 'pdp_cdb' loaded successfully.\n"); +} + +static void cpucp_fw_load(void) +{ + /* map to cached region to force address to be 4 byte aligned */ + mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), CACHED_RAM); + + struct prog cpucp_dtbs_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs"); + + if (!selfload(&cpucp_dtbs_prog)) + die("SOC image: 'cpucp dtbs' load failed"); + printk(BIOS_DEBUG, "SOC image: 'cpucp dtbs' image loaded successfully.\n"); + + const char *cpucp_name = (CONFIG(VBOOT) && !vboot_recovery_mode_enabled()) + ? CONFIG_CBFS_PREFIX "/cpucp_rw" + : CONFIG_CBFS_PREFIX "/cpucp_ro"; + + struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, cpucp_name); + + if (!selfload(&cpucp_fw_prog)) + die("SOC image: 'cpucp' load failed"); + printk(BIOS_DEBUG, "SOC image: 'cpucp' image loaded successfully.\n"); + + /* flush cached region */ + dcache_clean_by_mva(_cpucp, REGION_SIZE(cpucp)); + /* remap back to device memory */ + mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), DEV_MEM); +} + + +void cpucp_pdp_fw_load_reset(void) +{ + cpucp_fw_load(); + pdp_fw_load(); + + /* Debug scripts may have set Wakeup Mask. Clear it */ + write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0); + + /* Zero out SEQ_SLEEP_REQ to have a clean state */ + write32((void *) HWIO_APSS_CPUCP_LPMBFSM_CPUCP_SW_SLEEP_REQ, 0x0); + + /* Trigger CPUCP boot */ + write32((void *) APSS_GLUE_BOOT_REG_BASE_SW_TRIGGER, 0x1); +} diff --git a/src/soc/qualcomm/calypso/decompressor.c b/src/soc/qualcomm/calypso/decompressor.c new file mode 100644 index 00000000000..12a3bac50bc --- /dev/null +++ b/src/soc/qualcomm/calypso/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void decompressor_soc_init(void) +{ + soc_mmu_init(); +} diff --git a/src/soc/qualcomm/calypso/include/soc/addressmap.h b/src/soc/qualcomm/calypso/include/soc/addressmap.h new file mode 100644 index 00000000000..c66aba8cd49 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/addressmap.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ + +#include +#include + +#define TCSR_BASE 0x01FC0000 +#define AOSS_CC_BASE 0x0C2A0000 +#define QSPI_BASE 0x088DC000 +#define TLMM_TILE_BASE 0x0F100000 +#define GCC_BASE 0x00100000 +#define NCC0_BASE 0x19A30000 +#define GCC_QUPV3_WRAP0_BASE 0x128004 +#define GCC_QUPV3_WRAP1_BASE 0x1B3004 +#define GCC_QUPV3_WRAP2_BASE 0x1B4004 +#define GCC_QUPV3_OOB_BASE 0x1E7014 + +/* CALPYSO QSPI GPIO PINS */ +#define QSPI_CS GPIO(132) +#define QSPI_DATA_0 GPIO(128) +#define QSPI_DATA_1 GPIO(129) +#define QSPI_CLK GPIO(127) + +#define GPIO_FUNC_QSPI_DATA_0 GPIO128_FUNC_QSPI0_DATA_0 +#define GPIO_FUNC_QSPI_DATA_1 GPIO129_FUNC_QSPI0_DATA_1 +#define GPIO_FUNC_QSPI_CLK GPIO127_FUNC_QSPI0_CLK + +/* CALYPSO NCC0 PLL CONFIG ADDRESSES */ +#define NCC0_NCC_CMU_NCC_PLL_CFG 0x199A2010 +#define NCC0_NCC_CMU_NCC_CLK_CFG 0x199A2030 + +/* CPUCP */ +#define APSS_HM_BASE 0x17000000 +#define APSS_CPUCP_LPM_BFSM_REG_BASE (APSS_HM_BASE + 0x01876000) +#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR (APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161C) +#define HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR (APSS_CPUCP_LPM_BFSM_REG_BASE + 0x1688) + +#define HWIO_APSS_CPUCP_LPMBFSM_CPUCP_SW_SLEEP_REQ (APSS_CPUCP_LPM_BFSM_REG_BASE + 0x168C) +#define APSS_GLUE_BOOT_REG_BASE 0x17F40000 +#define APSS_GLUE_BOOT_REG_BASE_SW_TRIGGER (APSS_GLUE_BOOT_REG_BASE + 0x2000) + + + +/* QUP SERIAL ENGINE BASE ADDRESSES */ +/* QUPV3_0 */ +#define QUP_SERIAL0_BASE 0x00B80000 +#define QUP_SERIAL1_BASE 0x00B84000 +#define QUP_SERIAL2_BASE 0x00B88000 +#define QUP_SERIAL3_BASE 0x00B8C000 +#define QUP_SERIAL4_BASE 0x00B90000 +#define QUP_SERIAL5_BASE 0x00B94000 +#define QUP_SERIAL6_BASE 0x00B98000 +#define QUP_SERIAL7_BASE 0x00B9C000 +#define QUP_WRAP0_BASE 0x00BC0000 +#define QUP_0_GSI_BASE 0x00B04000 + +/* QUPV3_1 */ +#define QUP_SERIAL8_BASE 0x00A80000 +#define QUP_SERIAL9_BASE 0x00A84000 +#define QUP_SERIAL10_BASE 0x00A88000 +#define QUP_SERIAL11_BASE 0x00A8C000 +#define QUP_SERIAL12_BASE 0x00A90000 +#define QUP_SERIAL13_BASE 0x00A94000 +#define QUP_SERIAL14_BASE 0x00A98000 +#define QUP_SERIAL15_BASE 0x00A9C000 +#define QUP_WRAP1_BASE 0x00AC0000 +#define QUP_1_GSI_BASE 0x00A04000 + +/* QUPV3_2 */ +#define QUP_SERIAL16_BASE 0x00880000 +#define QUP_SERIAL17_BASE 0x00884000 +#define QUP_SERIAL18_BASE 0x00888000 +#define QUP_SERIAL19_BASE 0x0088C000 +#define QUP_SERIAL20_BASE 0x00890000 +#define QUP_SERIAL21_BASE 0x00894000 +#define QUP_SERIAL22_BASE 0x00898000 +#define QUP_SERIAL23_BASE 0x0089C000 +#define QUP_WRAP2_BASE 0x008C0000 +#define QUP_2_GSI_BASE 0x00804000 + +/* QUPV3_3 */ +#define QUP_SERIAL24_BASE 0x00780000 +#define QUP_SERIAL25_BASE 0x00784000 +#define QUP_WRAP3_BASE 0x009C0000 +#define QUP_3_GSI_BASE 0x00904000 + +/* SPMI PMIC ARB */ +#define SPMI_PMIC_ARB_CORE_BASE 0x0C400000 +#define FIRST_APID_MAP_OFFSET 0x3000 +#define LAST_APID_MAP_OFFSET 0x5800 +#define SPMI_PMIC_ARB_APID_COUNT ((LAST_APID_MAP_OFFSET - FIRST_APID_MAP_OFFSET) / 4) +#define SPMI_PMIC_ARB_APID_MAP_BASE (SPMI_PMIC_ARB_CORE_BASE + FIRST_APID_MAP_OFFSET) +#define SPMI_PMIC_ARB_CHANNEL_BASE 0x0C900000 +#define SPMI_PMIC_ARB_CHANNEL_SIZE 0x200 + +/* + * APID map entry format (PMIC_ARB_REG_ADDRp) for Calypso: + * bit 31 : IRQ_OWN + * bits 12:8 : DEVID_SID (5-bit slave ID) + * bits 7:0 : ADDRESS (PPID) + */ +/* ADDR.PPID is 13 bits: SID (20:16) + Periph (15:8) */ +#define SPMI_PPID_FROM_ADDR(a) (((a) >> 8) & 0x1fffU) +/* REG.PPID is 13 bits: SID (12:8) + Periph (7:0) */ +#define SPMI_PPID_FROM_REG(r) ((r) & 0x1fffU) + +/* PCIe5 controller addresses */ +#define PCIE5_PCIE_PARF 0x01B40000 +#define PCIE5_GEN1X4_PCIE_DBI 0x7A000000 +#define PCIE5_GEN1X4_PCIE_ELBI 0x7A000F40 +#define PCIE5_GEN1X4_DWC_PCIE_DM_IATU 0x7A001000 +#define PCIE5_SPACE_END_ADDR 0x7E000000 +#define PCIE5_BCR 0x1C3000 +#define GCC_PCIE_5_PHY_BCR 0x1D2000 + +/* PCIe5 QMP PHY (5x4) base addresses */ +#define PCIE5_QMP_PHY_WRAPPER_BASE 0x01B50000 +#define PCIE5_QMP_PHY_TXRX0 (PCIE5_QMP_PHY_WRAPPER_BASE + 0x0000) +#define PCIE5_QMP_PHY_TXRX1 (PCIE5_QMP_PHY_WRAPPER_BASE + 0x1000) +#define PCIE5_QMP_PHY_TXRX2 (PCIE5_QMP_PHY_WRAPPER_BASE + 0x2000) +#define PCIE5_QMP_PHY_TXRX3 (PCIE5_QMP_PHY_WRAPPER_BASE + 0x3000) +#define PCIE5_QMP_PHY_SERDES (PCIE5_QMP_PHY_WRAPPER_BASE + 0x8000) +#define PCIE5_QMP_PHY_PCS_COM (PCIE5_QMP_PHY_WRAPPER_BASE + 0x9000) +#define PCIE5_QMP_PHY_PCS_LANE0 (PCIE5_QMP_PHY_WRAPPER_BASE + 0xA000) +#define PCIE5_QMP_PHY_PCS_LANE1 (PCIE5_QMP_PHY_WRAPPER_BASE + 0xA400) +#define PCIE5_QMP_PHY_PCS_LANE2 (PCIE5_QMP_PHY_WRAPPER_BASE + 0xA800) +#define PCIE5_QMP_PHY_PCS_LANE3 (PCIE5_QMP_PHY_WRAPPER_BASE + 0xAC00) +#define PCIE5_QMP_PHY_TXRXZ (PCIE5_QMP_PHY_WRAPPER_BASE + 0xD000) +#define PCIE5_QMP_PHY_PCS_LANEZ (PCIE5_QMP_PHY_WRAPPER_BASE + 0xE800) + +/* TCSR PCIe clkref enable */ +#define TCSR_PCIE_1_CLKREF_EN_OFF 0x95048 +#define TCSR_PCIE_1_CLKREF_EN__PCIE_ENABLE ((void *)(TCSR_BASE + TCSR_PCIE_1_CLKREF_EN_OFF)) + +#endif /* __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/clock.h b/src/soc/qualcomm/calypso/include/soc/clock.h new file mode 100644 index 00000000000..c9679145ad5 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/clock.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#ifndef __SOC_QUALCOMM_CALYPSO_CLOCK_H__ +#define __SOC_QUALCOMM_CALYPSO_CLOCK_H__ + +#define SRC_XO_HZ (19200 * KHz) + +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) +#define CLK_100MHZ (100 * MHz) +#define CLK_200MHZ (200 * MHz) +#define CLK_400MHZ (400 * MHz) +#define CLK_75MHZ (75 * MHz) +#define CLK_575MHZ (575 * MHz) +#define CLK_37_5MHZ (37500 * KHz) + +/* CPU PLL*/ +#define L_VAL_1363P2MHz 0x47 +#define L_VAL_710P4MHz 0x25 + +#define QUPV3_WRAP0_CLK_ENA_S(idx) (13 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (15 + idx) +#define QUPV3_WRAP2_CLK_ENA_S(idx) (idx) +#define QUPV3_OOB_CLK_ENA_S(idx) (6 + idx) + +#define QUPV3_WRAP2_SE0_CLK_ENA 30 +#define QUPV3_WRAP2_SE1_CLK_ENA 31 + +#define LOCKDEASSERTTMOUTCNT_BMSK 0xFFF +#define LOCKTMOUTCNT_BMSK 0xFFFF + +#define LOCKDEASSERTTMOUTCNT_VAL 960LL +#define LOCKTMOUTCNT_VAL 960LL + +#define PFA_MSB_VAL 2 +#define RON_DEGEN_MULTIPLY_VAL 1 +#define FBC_ALPHA_CAL_VAL 2 +#define PLL_COUNTER_ENABLE_VAL 1 + +#define CHP_REF_CUR_TRIM_VAL 1 +#define ADC_KLSB_VALUE_VAL 4 +#define ADC_KMSB_VALUE_VAL 10 + +/* TODO: update as per datasheet */ +void clock_init(void); +void clock_configure_qspi(uint32_t hz); +void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); + +/* Does nothing */ +#define clock_reset_aop() do {} while (0) +/* Does nothing */ +#define clock_reset_shrm() do {} while (0) + +enum apcs_branch_en_vote { + QUPV3_OOB_S_AHB_CLK_ENA = 3, + QUPV3_OOB_CORE_CLK_ENA = 4, + QUPV3_OOB_CORE_2X_CLK_ENA = 5, + QUPV3_WRAP_0_M_AHB_CLK_ENA = 9, + QUPV3_WRAP_0_S_AHB_CLK_ENA = 10, + QUPV3_WRAP0_CORE_CLK_ENA = 11, + QUPV3_WRAP0_CORE_2X_CLK_ENA = 12, + QUPV3_WRAP1_CORE_2X_CLK_ENA = 14, + QUPV3_WRAP1_CORE_CLK_ENA = 13, + QUPV3_WRAP_1_M_AHB_CLK_ENA = 11, + QUPV3_WRAP_1_S_AHB_CLK_ENA = 12, + QUPV3_WRAP2_CORE_2X_CLK_ENA = 29, + QUPV3_WRAP2_CORE_CLK_ENA = 28, + QUPV3_WRAP_2_M_AHB_CLK_ENA = 26, + QUPV3_WRAP_2_S_AHB_CLK_ENA = 27, + /* VOTE_0 (apcs_clk_br_en) - SMMU/TCU/HSCNOC PCIe */ + HSCNOC_PCIE_SF_QTC_CLK_ENA = 24, + HSCNOC_PCIE_SLAVE_SF_EAST_CLK_ENA = 25, + HSCNOC_PCIE_SLAVE_SF_WEST_CLK_ENA = 26, + TCU_PCIE_SF_QTC_CLK_ENA = 27, + SMMU_PCIE_QTC_AT_CLK_ENA = 30, + /* VOTE_1 (apcs_clk_br_en1) - AGGRE_NOC/ANOC/CNOC/PCIE_NOC */ + PCIE_NOC_PWRCTL_CLK_ENA = 7, + PCIE_NOC_SF_CENTER_CLK_ENA = 8, + PCIE_NOC_SLAVE_SF_EAST_CLK_ENA = 9, + PCIE_NOC_SLAVE_SF_WEST_CLK_ENA = 10, + CNOC_PCIE_WEST_TUNNEL_CLK_ENA = 14, + CNOC_PCIE_EAST_TUNNEL_CLK_ENA = 15, + ANOC_PCIE_PWRCTL_CLK_ENA = 26, + AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK_ENA = 30, + /* VOTE_2 (apcs_clk_br_en2) - TRACE_NOC/AGGRE_NOC_TUNNEL */ + AGGRE_NOC_PCIE_EAST_TUNNEL_AXI_CLK_ENA = 0, + AGGRE_NOC_PCIE_WEST_TUNNEL_AXI_CLK_ENA = 1, + TRACE_NOC_TCU_PCIE_QTC_AT_CLK_ENA = 8, + TRACE_NOC_PCIE_3B_AT_CLK_ENA = 9, + TRACE_NOC_PCIE_5_AT_CLK_ENA = 10, + /* VOTE_6 (apcs_clk_br_en6) - PCIE_5 specific */ + QMIP_PCIE_5_AHB_CLK_ENA = 0, + PCIE_5_SLV_Q2A_AXI_CLK_ENA = 1, + PCIE_5_SLV_AXI_CLK_ENA = 2, + PCIE_5_MSTR_AXI_CLK_ENA = 3, + PCIE_5_AUX_CLK_ENA = 5, + PCIE_5_PIPE_CLK_ENA = 6, + PCIE_5_PIPE_DIV2_CLK_ENA = 7, + PCIE_5_PHY_RCHNG_CLK_ENA = 8, + PCIE_5_AT_CLK_ENA = 9, + PCIE_PHY_5_AUX_CLK_ENA = 11, + PCIE_5_CFG_AHB_CLK_ENA = 4, + /* Direct CBCR enable (no vote register) */ + NO_VOTE_BIT = -1, +}; + +enum clk_pll_src { + SRC_XO_19_2MHZ = 0, + SRC_GPLL0_MAIN_600MHZ = 1, + SRC_GPLL9_MAIN_808MHZ = 2, + SRC_GCC_DISP_GPLL0_CLK = 4, + SRC_GPLL10_MAIN_384MHZ = 5, + SRC_GPLL0_EVEN_300MHZ = 6, +}; + +struct calypso_gpll { + u32 mode; + u32 opmode; + u32 state; + u32 status; + u32 l; + u32 alpha; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 config_ctl_u; + u32 config_ctl_u1; + u32 test_ctl; + u32 test_ctl_u; + u32 ssc; +}; + +enum ncc0_cmu_clk_cfg_calypso { + OVRCKMUXPLLFASTCLK = 2, + SELCKMUXPLLFASTCLK = 3, + PLLSWCTL = 25, +}; + +enum ncc0_cmu_pll_cfg_calypso { + LOCKTMOUTCNT = 0, + LOCKDEASSERTTMOUTCNT = 32, +}; + +enum ncc0_pll0_config_ctl { + PFA_MSB = 10, + RON_DEGEN_MULTIPLY = 18, + FBC_ALPHA_CAL = 20, + PLL_COUNTER_ENABLE = 27, +}; + +enum ncc0_pll0_config_ctl_u { + CHP_REF_CUR_TRIM = 0, + ADC_KLSB_VALUE = 13, + ADC_KMSB_VALUE = 23, +}; + +struct calypso_ncc0_clock { + u32 pll0_mode; + u32 pll0_l; + u32 pll0_alpha; + u32 pll0_user_ctl; + u32 pll0_user_ctl_u; + u32 pll0_config_ctl; + u32 pll0_config_ctl_u; + u32 pll0_config_ctl_u1; + u32 pll0_config_ctl_u2; + u32 pll0_test_ctl; + u32 pll0_test_ctl_u; + u32 pll0_test_ctl_u1; + u32 pll0_opmode; +}; + +enum clk_ctl_gpll_user_ctl_calypso { + PLL_PLLOUT_MAIN_SHFT_CALYPSO = 0, + PLL_PLLOUT_EVEN_SHFT_CALYPSO = 1, + PLL_PLLOUT_ODD_SHFT_CALYPSO = 2, + PLL_POST_DIV_EVEN_SHFT_CALYPSO = 10, + PLL_POST_DIV_ODD_SHFT_CALYPSO = 14, +}; + +/* + * PCIE NOC register block + */ +struct calypso_pcie_noc { + u8 _res0[0x268]; + u32 hscnoc_pcie_sf_qtc_cbcr; + u8 _res1[0x270 - 0x26C]; + u32 hscnoc_pcie_slave_sf_east_cbcr; + u8 _res2[0x278 - 0x274]; + u32 hscnoc_pcie_slave_sf_west_cbcr; + u8 _res3[0x280 - 0x27C]; + u32 tcu_pcie_sf_qtc_cbcr; + u8 _res4[0x2AC - 0x284]; + u32 pcie_noc_pwrctl_cbcr; + u32 pcie_noc_sf_center_cbcr; + u8 _res5[0x2B8 - 0x2B4]; + u32 pcie_noc_slave_sf_east_cbcr; + u8 _res6[0x2C0 - 0x2BC]; + u32 pcie_noc_slave_sf_west_cbcr; + u8 _res7[0x2DC - 0x2C4]; + u32 cnoc_pcie_west_tunnel_cbcr; + u8 _res8[0x2E4 - 0x2E0]; + u32 cnoc_pcie_east_tunnel_cbcr; + u8 _res9[0x300 - 0x2E8]; + u32 aggre_noc_pcie_east_tunnel_axi_cbcr; + u32 aggre_noc_pcie_west_tunnel_axi_cbcr; + u8 _res10[0x448 - 0x308]; + u32 trace_noc_pcie_3b_at_cbcr; + u32 trace_noc_pcie_5_at_cbcr; + u8 _res11[0x4E4 - 0x450]; + u32 pcie_link_xo_cbcr; +}; +check_member(calypso_pcie_noc, hscnoc_pcie_sf_qtc_cbcr, 0x268); +check_member(calypso_pcie_noc, hscnoc_pcie_slave_sf_east_cbcr, 0x270); +check_member(calypso_pcie_noc, hscnoc_pcie_slave_sf_west_cbcr, 0x278); +check_member(calypso_pcie_noc, tcu_pcie_sf_qtc_cbcr, 0x280); +check_member(calypso_pcie_noc, pcie_noc_pwrctl_cbcr, 0x2AC); +check_member(calypso_pcie_noc, pcie_noc_sf_center_cbcr, 0x2B0); +check_member(calypso_pcie_noc, pcie_noc_slave_sf_east_cbcr, 0x2B8); +check_member(calypso_pcie_noc, pcie_noc_slave_sf_west_cbcr, 0x2C0); +check_member(calypso_pcie_noc, cnoc_pcie_west_tunnel_cbcr, 0x2DC); +check_member(calypso_pcie_noc, cnoc_pcie_east_tunnel_cbcr, 0x2E4); +check_member(calypso_pcie_noc, aggre_noc_pcie_east_tunnel_axi_cbcr, 0x300); +check_member(calypso_pcie_noc, aggre_noc_pcie_west_tunnel_axi_cbcr, 0x304); +check_member(calypso_pcie_noc, trace_noc_pcie_3b_at_cbcr, 0x448); +check_member(calypso_pcie_noc, trace_noc_pcie_5_at_cbcr, 0x44C); +check_member(calypso_pcie_noc, pcie_link_xo_cbcr, 0x4E4); + +/* + * PCIE5 register block + * Embedded in calypso_gcc at offset 0xC3000 (absolute: GCC_BASE + 0xC3000) + */ +struct calypso_pcie_5 { + u32 bcr; + u32 gdscr; + u8 _res0[0x18 - 0x8]; + u32 qmip_pcie_5_ahb_cbcr; + u32 slv_q2a_axi_cbcr; + u8 _res1[0x24 - 0x20]; + u32 slv_axi_cbcr; + u8 _res2[0x38 - 0x28]; + u32 mstr_axi_cbcr; + u8 _res3[0x4C - 0x3C]; + u32 aux_cbcr; + u8 _res4[0x5C - 0x50]; + u32 pipe_cbcr; + u8 _res5[0x70 - 0x60]; + u32 pipe_div2_cbcr; + u8 _res6[0x80 - 0x74]; + u32 phy_rchng_cbcr; + struct clock_rcg phy_rchng_rcg; + u8 _res7a[0x9C - 0x8C]; + u32 pipe_muxr; + u8 _res7b[0xC0 - 0xA0]; + u32 at_cbcr; + u8 _res8[0xD0 - 0xC4]; + u32 aggre_noc_pcie_5_east_sf_axi_cbcr; +}; +check_member(calypso_pcie_5, gdscr, 0x004); +check_member(calypso_pcie_5, qmip_pcie_5_ahb_cbcr, 0x018); +check_member(calypso_pcie_5, slv_q2a_axi_cbcr, 0x01C); +check_member(calypso_pcie_5, slv_axi_cbcr, 0x024); +check_member(calypso_pcie_5, mstr_axi_cbcr, 0x038); +check_member(calypso_pcie_5, aux_cbcr, 0x04C); +check_member(calypso_pcie_5, pipe_cbcr, 0x05C); +check_member(calypso_pcie_5, pipe_div2_cbcr, 0x070); +check_member(calypso_pcie_5, phy_rchng_cbcr, 0x080); +check_member(calypso_pcie_5, phy_rchng_rcg, 0x084); +check_member(calypso_pcie_5, pipe_muxr, 0x09C); +check_member(calypso_pcie_5, at_cbcr, 0x0C0); +check_member(calypso_pcie_5, aggre_noc_pcie_5_east_sf_axi_cbcr, 0x0D0); + +struct calypso_gcc { + struct calypso_gpll gpll0; + u8 _res0[0x28004 - 0x3A]; + struct qupv3_clock qup_wrap0_s[8]; + u8 _res1[0x50000 - 0x28984]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct clock_rcg qspi_core; + u8 _res2[0x62000 - 0x50014]; + u32 apcs_clk_br_en; + u8 _res3[0x62008 - 0x62004]; + u32 apcs_clk_br_en1; + u8 _res4[0x62010 - 0x6200C]; + u32 apcs_clk_br_en2; + u8 _res5[0x62018 - 0x62014]; + u32 apcs_clk_br_en3; + u8 _res6[0x62020 - 0x6201C]; + u32 apcs_clk_br_en4; + u8 _res7[0x62028 - 0x62024]; + u32 apcs_clk_br_en5; + u8 _res8a[0x62030 - 0x6202C]; + u32 apcs_clk_br_en6; + u8 _res8b[0x62040 - 0x62034]; + u32 apcs_pll_br_en; + u8 _res9a[0x82064 - 0x62044]; + u32 anoc_pcie_pwrctl_cbcr; + u8 _res9b[0x9C030 - 0x82068]; + u32 trace_noc_tcu_pcie_qtc_at_cbcr; + u8 _res9c[0xB3004 - 0x9C034]; + struct qupv3_clock qup_wrap1_s[8]; + u8 _res10[0xB4004 - 0xB3984]; + struct qupv3_clock qup_wrap2_s[8]; + u8 _res11[0xB8008 - 0xB4984]; + u32 pcie_rscc_xo_cbcr; + u8 _res11b[0xB9048 - 0xB800C]; + u32 smmu_pcie_qtc_at_cbcr; + u8 _res11c[0xBA000 - 0xB904C]; + struct calypso_pcie_noc pcie_noc; + u8 _res11da[0xBA4F8 - 0xBA4E8]; + u32 pcie_5_cfg_ahb_cbcr; + u8 _res11db[0xC3000 - 0xBA4FC]; + struct calypso_pcie_5 pcie_5; + u8 _res11e[0xC5028 - 0xC30D4]; + u32 qup_oob_s_ahb_cbcr; + u32 qup_oob_core_cbcr; + u8 _res12[0xC503C - 0xC5030]; + u32 qup_oob_core_cdivr; + u32 qup_oob_core_2x_cbcr; + u8 _res13[0xC517C - 0xc5044]; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + u32 qup_wrap1_core_cbcr; + u8 _res14[0xC5194 - 0xC5188]; + u32 qup_wrap1_core_cdivr; + u32 qup_wrap1_core_2x_cbcr; + u8 _res15[0xC51A8 - 0xC519C]; + struct clock_rcg qup_wrap1_core_2x; + u8 _res16[0xC52D4 - 0xC51B0]; + u32 qup_wrap2_m_ahb_cbcr; + u32 qup_wrap2_s_ahb_cbcr; + u32 qup_wrap2_core_cbcr; + u8 _res17[0xC52EC - 0xC52E0]; + u32 qup_wrap2_core_cdivr; + u32 qup_wrap2_core_2x_cbcr; + u8 _res18[0xC5300 - 0xC52F4]; + struct clock_rcg qup_wrap2_core_2x; + u8 _res19[0xC542C - 0xC5308]; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + u32 qup_wrap0_core_cbcr; + u8 _res20[0xC5444 - 0xC5438]; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + u8 _res21[0xC5458 - 0xC544C]; + struct clock_rcg qup_wrap0_core_2x; + u8 _res20a[0xD2004 - 0xC5460]; + u32 pcie_phy_5_gdscr; + u8 _res20b[0xD2030 - 0xD2008]; + u32 pcie_phy_5_aux_cbcr; + u8 _res20c[0xE7004 - 0xD2034]; + u32 qup_oob_m_ahb_cbcr; + u8 _res23[0xE7014 - 0xE7008]; + struct qupv3_clock qup_wrap3_s[2]; +}; + +check_member(calypso_gcc, qup_wrap0_s, 0x28004); +check_member(calypso_gcc, qspi_bcr, 0x50000); +check_member(calypso_gcc, apcs_clk_br_en, 0x62000); +check_member(calypso_gcc, apcs_clk_br_en1, 0x62008); +check_member(calypso_gcc, apcs_clk_br_en2, 0x62010); +check_member(calypso_gcc, apcs_clk_br_en3, 0x62018); +check_member(calypso_gcc, apcs_clk_br_en4, 0x62020); +check_member(calypso_gcc, apcs_clk_br_en5, 0x62028); +check_member(calypso_gcc, apcs_pll_br_en, 0x62040); +check_member(calypso_gcc, qup_wrap1_s, 0xB3004); +check_member(calypso_gcc, qup_wrap2_s, 0xB4004); +check_member(calypso_gcc, pcie_rscc_xo_cbcr, 0xB8008); +check_member(calypso_gcc, smmu_pcie_qtc_at_cbcr, 0xB9048); +check_member(calypso_gcc, pcie_noc, 0xBA000); +check_member(calypso_gcc, pcie_5_cfg_ahb_cbcr, 0xBA4F8); +check_member(calypso_gcc, pcie_5, 0xC3000); +check_member(calypso_gcc, qup_oob_s_ahb_cbcr, 0xC5028); +check_member(calypso_gcc, qup_oob_core_cbcr, 0xC502C); +check_member(calypso_gcc, qup_oob_core_cdivr, 0xC503C); +check_member(calypso_gcc, qup_oob_core_2x_cbcr, 0xC5040); +check_member(calypso_gcc, qup_wrap1_m_ahb_cbcr, 0xC517C); +check_member(calypso_gcc, qup_wrap1_core_2x, 0xC51A8); +check_member(calypso_gcc, qup_wrap2_m_ahb_cbcr, 0xC52D4); +check_member(calypso_gcc, qup_wrap2_core_2x, 0xC5300); +check_member(calypso_gcc, qup_wrap0_m_ahb_cbcr, 0xC542C); +check_member(calypso_gcc, qup_wrap0_core_2x, 0xC5458); +check_member(calypso_gcc, pcie_phy_5_gdscr, 0xD2004); +check_member(calypso_gcc, pcie_phy_5_aux_cbcr, 0xD2030); +check_member(calypso_gcc, qup_oob_m_ahb_cbcr, 0xE7004); +check_member(calypso_gcc, qup_wrap3_s, 0xE7014); + +/* Generic QUPV3 wrapper structure - all wrappers have identical layout */ +struct calypso_qupv3_wrap { + struct qupv3_clock qupv3_s0; + struct qupv3_clock qupv3_s1; + struct qupv3_clock_v2 qupv3_s2; + struct qupv3_clock_v2 qupv3_s3; + struct qupv3_clock qupv3_s4; + struct qupv3_clock qupv3_s5; + struct qupv3_clock qupv3_s6; + struct qupv3_clock qupv3_s7; +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP0_S6, + QUP_WRAP0_S7, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, + QUP_WRAP1_S6, + QUP_WRAP1_S7, + QUP_WRAP2_S0, + QUP_WRAP2_S1, + QUP_WRAP2_S2, + QUP_WRAP2_S3, + QUP_WRAP2_S4, + QUP_WRAP2_S5, + QUP_WRAP2_S6, + QUP_WRAP2_S7, + QUP_WRAP3_S0, + QUP_WRAP3_S1, +}; + +/* PCIe clock indices - each maps to a CBCR register in pcie_cfg[]. */ +enum clk_pcie { + GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK, + GCC_AGGRE_NOC_PCIE_EAST_TUNNEL_AXI_CLK, + GCC_AGGRE_NOC_PCIE_WEST_TUNNEL_AXI_CLK, + GCC_ANOC_PCIE_PWRCTL_CLK, + GCC_CNOC_PCIE_EAST_TUNNEL_CLK, + GCC_CNOC_PCIE_WEST_TUNNEL_CLK, + GCC_PCIE_LINK_XO_CLK, + GCC_HSCNOC_PCIE_SF_QTC_CLK, + GCC_HSCNOC_PCIE_SLAVE_SF_EAST_CLK, + GCC_HSCNOC_PCIE_SLAVE_SF_WEST_CLK, + GCC_PCIE_NOC_PWRCTL_CLK, + GCC_PCIE_NOC_SF_CENTER_CLK, + GCC_PCIE_NOC_SLAVE_SF_EAST_CLK, + GCC_PCIE_NOC_SLAVE_SF_WEST_CLK, + GCC_SMMU_PCIE_QTC_AT_CLK, + GCC_TCU_PCIE_SF_QTC_CLK, + GCC_TRACE_NOC_PCIE_3B_AT_CLK, + GCC_TRACE_NOC_PCIE_5_AT_CLK, + GCC_TRACE_NOC_TCU_PCIE_QTC_AT_CLK, + GCC_PCIE_5_AT_CLK, + GCC_PCIE_5_AUX_CLK, + GCC_PCIE_5_CFG_AHB_CLK, + GCC_PCIE_5_MSTR_AXI_CLK, + GCC_PCIE_5_PHY_RCHNG_CLK, + GCC_PCIE_5_PIPE_DIV2_CLK, + GCC_PCIE_5_SLV_AXI_CLK, + GCC_PCIE_5_SLV_Q2A_AXI_CLK, + GCC_PCIE_PHY_5_AUX_CLK, + GCC_PCIE_5_PIPE_CLK, + GCC_PCIE_5_PIPE_MUXR, + GCC_QMIP_PCIE_5_AHB_CLK, + PCIE_CLK_COUNT, +}; + +struct pcie { + uint32_t *gdscr; + uint32_t *clk; + uint32_t *clk_br_en; + int vote_bit; +}; + +enum clk_gdsc { + PCIE_5_GDSC, + PCIE_5_PHY_GDSC, + MAX_GDSC, +}; + +/* Pipe clock source select: 0 = PHY pipe clock (post-PHY init) */ +#define GCC_PCIE_5_PIPE_SRC_SEL 0 + +enum cb_err clock_enable_pcie(enum clk_pcie clk_type); +enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type); +enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type); +enum cb_err clock_configure_pcie(void); + +/* Subsystem Reset */ +static struct aoss *const aoss = (void *)AOSS_CC_BASE; +static struct calypso_gcc *const gcc = (void *)GCC_BASE; +static struct calypso_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE; +static struct calypso_qupv3_wrap *const qup_wrap0_clk = (void *)GCC_QUPV3_WRAP0_BASE; +static struct calypso_qupv3_wrap *const qup_wrap1_clk = (void *)GCC_QUPV3_WRAP1_BASE; +static struct calypso_qupv3_wrap *const qup_wrap2_clk = (void *)GCC_QUPV3_WRAP2_BASE; +static struct calypso_qupv3_wrap *const qup_oob_clk = (void *)GCC_QUPV3_OOB_BASE; + +enum cb_err pll_init_and_set(struct calypso_ncc0_clock *ncc0, u32 l_val); + +#endif // __SOC_QUALCOMM_CALYPSO_CLOCK_H__ diff --git a/src/soc/qualcomm/calypso/include/soc/cpucp.h b/src/soc/qualcomm/calypso/include/soc/cpucp.h new file mode 100644 index 00000000000..5978818a0e6 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/cpucp.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_CPUCP_H__ +#define __SOC_QUALCOMM_CALYPSO_CPUCP_H__ + +void cpucp_pdp_fw_load_reset(void); + +#endif // __SOC_QUALCOMM_CALYPSO_CPUCP_H__ diff --git a/src/soc/qualcomm/calypso/include/soc/gpio.h b/src/soc/qualcomm/calypso/include/soc/gpio.h new file mode 100644 index 00000000000..bec2f01604b --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/gpio.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_GPIO_H__ +#define __SOC_QUALCOMM_CALYPSO_GPIO_H__ + +#include +#include +#include + +#define PIN(index, func1, func2, func3, func4, func5, func6) \ + GPIO##index##_ADDR = (TLMM_TILE_BASE + ((index) * TLMM_GPIO_OFF_DELTA)), \ + GPIO##index##_FUNC_##func1 = (1), \ + GPIO##index##_FUNC_##func2 = (2), \ + GPIO##index##_FUNC_##func3 = (3), \ + GPIO##index##_FUNC_##func4 = (4), \ + GPIO##index##_FUNC_##func5 = (5), \ + GPIO##index##_FUNC_##func6 = (6) + +enum { + PIN(0, QUP0_SE0_L0, IBI_I3C_QUP0_SE0_SDA, RES_3, RES_4, RES_5, RES_6), + PIN(1, QUP0_SE0_L1, IBI_I3C_QUP0_SE0_SCL, RES_3, RES_4, RES_5, RES_6), + PIN(2, QUP0_SE0_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(3, QUP0_SE0_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(4, QUP0_SE1_L0, QUP0_SE6_L2, IBI_I3C_QUP0_SE1_SDA, RES_4, RES_5, RES_6), + PIN(5, QUP0_SE1_L1, QUP0_SE6_L3, IBI_I3C_QUP0_SE1_SCL, RES_4, RES_5, RES_6), + PIN(6, QUP0_SE1_L2, QUP0_SE6_L0, I2C0_S_SDA, RES_4, RES_5, RES_6), + PIN(7, QUP0_SE1_L3, QUP0_SE6_L1, I2C0_S_SCL, RES_4, RES_5, RES_6), + PIN(8, QUP0_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(9, QUP0_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(10, QUP0_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(11, QUP0_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(12, QUP0_SE3_L0, QUP0_SE7_L2, RES_3, RES_4, RES_5, RES_6), + PIN(13, QUP0_SE3_L1, QUP0_SE7_L3, RES_3, RES_4, RES_5, RES_6), + PIN(14, QUP0_SE3_L2, QUP0_SE7_L0, RES_3, RES_4, RES_5, RES_6), + PIN(15, QUP0_SE3_L3, QUP0_SE7_L1, RES_3, RES_4, RES_5, RES_6), + PIN(16, QUP0_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(17, QUP0_SE4_L1, QUP0_SE2_L4, RES_3, RES_4, RES_5, RES_6), + PIN(18, QUP0_SE4_L2, QUP0_SE2_L5, RES_3, RES_4, QDSS_CTI_TRIG0_OUT_MIRB, RES_6), + PIN(19, QUP0_SE4_L3, QUP0_SE2_L6, RES_3, RES_4, QDSS_CTI_TRIG1_OUT_MIRB, RES_6), + PIN(20, QUP0_SE5_L0, GP_PDM_MIRB_2, RES_3, RES_4, RES_5, RES_6), + PIN(21, QUP0_SE5_L1, QUP0_SE3_L4, GP_PDM_MIRB_1, RES_4, RES_5, RES_6), + PIN(22, QUP0_SE5_L2, QUP0_SE3_L5, GP_PDM_MIRB_0, RES_4, RES_5, RES_6), + PIN(23, QUP0_SE5_L3, QUP0_SE3_L6, RES_3, RES_4, QDSS_CTI_TRIG0_IN_MIRA, RES_6), + PIN(24, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(25, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(26, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(27, RES_1, RES_2, QDSS_CTI_TRIG1_IN_MIRA, RES_4, RES_5, RES_6), + PIN(28, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(29, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(30, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(31, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(32, QUP1_SE0_L0, IBI_I3C_QUP1_SE0_SDA, RES_3, RES_4, RES_5, RES_6), + PIN(33, QUP1_SE0_L1, IBI_I3C_QUP1_SE0_SCL, QUP1_SE3_L4, RES_4, RES_5, RES_6), + PIN(34, QUP1_SE0_L2, QUP1_SE3_L5, RES_3, RES_4, RES_5, RES_6), + PIN(35, QUP1_SE0_L3, QUP1_SE3_L6, RES_3, RES_4, RES_5, RES_6), + PIN(36, QUP1_SE1_L0, IBI_I3C_QUP1_SE1_SDA, RES_3, RES_4, RES_5, RES_6), + PIN(37, QUP1_SE1_L1, IBI_I3C_QUP1_SE1_SCL, RES_3, RES_4, RES_5, RES_6), + PIN(38, QUP1_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(39, QUP1_SE1_L3, SYS_THROTTLE_N_MIRA, RES_3, RES_4, RES_5, RES_6), + PIN(40, QUP1_SE2_L0, QUP3_SE1_L0, RES_3, RES_4, RES_5, RES_6), + PIN(41, QUP1_SE2_L1, QUP3_SE1_L1, RES_3, RES_4, RES_5, RES_6), + PIN(42, QUP1_SE2_L2, QUP3_SE1_L2, RES_3, RES_4, RES_5, RES_6), + PIN(43, QUP1_SE2_L3, QUP3_SE1_L3, RES_3, RES_4, RES_5, RES_6), + PIN(44, QUP1_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(45, QUP1_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(46, QUP1_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(47, QUP1_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(48, QUP1_SE4_L0, QUP3_SE1_L7, RES_3, RES_4, RES_5, RES_6), + PIN(49, QUP1_SE4_L1, QUP1_SE2_L4, QUP3_SE1_L4, RES_4, RES_5, RES_6), + PIN(50, QUP1_SE4_L2, QUP1_SE2_L5, QUP3_SE1_L5, RES_4, RES_5, RES_6), + PIN(51, QUP1_SE4_L3, QUP1_SE4_L4, QUP1_SE4_L5, RES_4, RES_5, RES_6), + PIN(52, QUP1_SE5_L0, QUP1_SE7_L2, RES_3, RES_4, RES_5, RES_6), + PIN(53, QUP1_SE5_L1, QUP1_SE7_L3, GP_MN, RES_4, RES_5, RES_6), + PIN(54, QUP1_SE5_L2, QUP1_SE7_L0, RES_3, RES_4, RES_5, RES_6), + PIN(55, QUP1_SE5_L3, QUP1_SE7_L1, RES_3, RES_4, RES_5, RES_6), + PIN(56, QUP1_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(57, QUP1_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(58, QUP1_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(59, QUP1_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(60, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(61, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(62, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(63, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(64, QUP2_SE0_L0, IBI_I3C_QUP2_SE0_SDA, GCC_GP2_CLK_MIRB, RES_4, RES_5, RES_6), + PIN(65, QUP2_SE0_L1, QUP2_SE3_L4, IBI_I3C_QUP2_SE0_SCL, RES_4, RES_5, RES_6), + PIN(66, QUP2_SE0_L2, QUP2_SE3_L5, RES_3, RES_4, RES_5, RES_6), + PIN(67, QUP2_SE0_L3, QUP2_SE3_L6, RES_3, RES_4, RES_5, RES_6), + PIN(68, QUP2_SE1_L0, IBI_I3C_QUP2_SE1_SDA, RES_3, RES_4, RES_5, RES_6), + PIN(69, QUP2_SE1_L1, IBI_I3C_QUP2_SE1_SCL, RES_3, RES_4, RES_5, RES_6), + PIN(70, QUP2_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(71, QUP2_SE1_L3, GCC_GP1_CLK_MIRB, RES_3, RES_4, RES_5, RES_6), + PIN(72, QUP2_SE2_L0, GCC_GP1_CLK_MIRA, RES_3, RES_4, RES_5, RES_6), + PIN(73, QUP2_SE2_L1, GCC_GP2_CLK_MIRA, RES_3, RES_4, RES_5, RES_6), + PIN(74, QUP2_SE2_L2, GCC_GP3_CLK_MIRA, RES_3, RES_4, RES_5, RES_6), + PIN(75, QUP2_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(76, QUP2_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(77, QUP2_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(78, QUP2_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(79, QUP2_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(80, QUP2_SE4_L0, QUP2_SE7_L0, RES_3, RES_4, RES_5, RES_6), + PIN(81, QUP2_SE4_L1, QUP2_SE2_L4, QUP2_SE7_L1, RES_4, RES_5, RES_6), + PIN(82, QUP2_SE4_L2, QUP2_SE2_L5, QUP2_SE7_L2, GCC_GP3_CLK_MIRB, RES_5, RES_6), + PIN(83, QUP2_SE4_L3, QUP2_SE2_L6, QUP2_SE7_L3, RES_4, RES_5, RES_6), + PIN(84, QUP2_SE5_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(85, QUP2_SE5_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(86, QUP2_SE5_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(87, QUP2_SE5_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(88, QUP2_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(89, QUP2_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(90, QUP2_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(91, QUP2_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(92, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(93, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(94, SYS_THROTTLE_N_MIRB, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(95, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(96, CAM_MCLK0, QDSS_GPIO_TRACEDATA_LOCA_0, RES_3, RES_4, RES_5, RES_6), + PIN(97, CAM_MCLK1, QDSS_GPIO_TRACEDATA_LOCA_1, RES_3, RES_4, RES_5, RES_6), + PIN(98, CAM_MCLK2, MDP_VSYNC_P, USB0_TMU_CLK_OUT, USB1_TMU_CLK_OUT, USB2_TMU_CLK_OUT, RES_6), + PIN(99, CAM_MCLK3, QDSS_GPIO_TRACEDATA_LOCA_3, RES_3, RES_4, RES_5, RES_6), + PIN(100, CAM_ASC_MCLK4, QDSS_GPIO_TRACEDATA_LOCA_4, RES_3, RES_4, RES_5, RES_6), + PIN(101, CCI_I2C_SDA0, QDSS_GPIO_TRACEDATA_LOCA_5, RES_3, RES_4, RES_5, RES_6), + PIN(102, CCI_I2C_SCL0, QDSS_GPIO_TRACEDATA_LOCA_6, RES_3, RES_4, RES_5, RES_6), + PIN(103, CCI_I2C_SDA1, QDSS_GPIO_TRACEDATA_LOCA_7, RES_3, RES_4, RES_5, RES_6), + PIN(104, CCI_I2C_SCL1, QDSS_GPIO_TRACECTL_LOCA, RES_3, RES_4, RES_5, RES_6), + PIN(105, CCI_I2C_SDA2, MDP_VSYNC_S, RES_3, RES_4, RES_5, RES_6), + PIN(106, CCI_I2C_SCL2, MDP_VSYNC_E, RES_3, RES_4, RES_5, RES_6), + PIN(107, QDSS_GPIO_TRACEDATA_LOCA_9, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(108, QDSS_GPIO_TRACEDATA_LOCA_10, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(109, CCI_TIMER0, MDP_VSYNC4_OUT, QDSS_GPIO_TRACEDATA_LOCA_11, RES_4, RES_5, RES_6), + PIN(110, CCI_TIMER1, MDP_VSYNC5_OUT, QDSS_GPIO_TRACEDATA_LOCA_12, RES_4, RES_5, RES_6), + PIN(111, CCI_TIMER2, CCI_ASYNC_IN2, MDP_VSYNC6_OUT, QDSS_GPIO_TRACEDATA_LOCA_13, RES_5, RES_6), + PIN(112, CCI_TIMER3, CCI_ASYNC_IN1, MDP_VSYNC7_OUT, QDSS_GPIO_TRACEDATA_LOCA_14, RES_5, RES_6), + PIN(113, CCI_TIMER4, CCI_ASYNC_IN0, MDP_VSYNC8_OUT, QDSS_GPIO_TRACEDATA_LOCA_15, RES_5, RES_6), + PIN(114, MDP_VSYNC0_OUT, MDP_VSYNC1_OUT, RES_3, RES_4, RES_5, RES_6), + PIN(115, MDP_VSYNC3_OUT, MDP_VSYNC2_OUT, RES_3, RES_4, RES_5, RES_6), + PIN(116, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(117, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(118, HOST2WLAN_SOL, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(119, EDP0_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(120, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(121, USB0_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(122, USB0_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(123, USB1_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(124, USB1_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(125, USB2_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(126, USB2_DP_HOT_PLUG_DETECT, GP_PDM_MIRA_0, RES_3, RES_4, RES_5, RES_6), + PIN(127, QSPI0_CLK, SDC4_CLK, QUP3_SE0_L2, GP_PDM_MIRA_1, RES_5, RES_6), + PIN(128, QSPI0_DATA_0, SDC4_DATA_0, QUP3_SE0_L1, GP_PDM_MIRA_2, RES_5, RES_6), + PIN(129, QSPI0_DATA_1, SDC4_DATA_1, QUP3_SE0_L0, RES_4, RES_5, RES_6), + PIN(130, QSPI0_DATA_2, SDC4_DATA_2, QUP3_SE0_L4, RES_4, RES_5, RES_6), + PIN(131, QSPI0_DATA_3, SDC4_DATA_3, QUP3_SE0_L5, RES_4, RES_5, RES_6), + PIN(132, QSPI0_CS0_N, SDC4_CMD, QUP3_SE0_L3, RES_4, RES_5, RES_6), + PIN(133, QSPI0_CS1_N, RES_2, QUP3_SE0_L6, RES_4, RES_5, RES_6), + PIN(134, AUDIO_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(135, I2S0_SCK, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(136, I2S0_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(137, I2S0_DATA1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(138, I2S0_WS, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(139, I2S1_SCK, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(140, I2S1_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(141, I2S1_WS, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(142, I2S1_DATA1, AUDIO_EXT_MCLK1, AUDIO_REF_CLK, RES_4, RES_5, RES_6), + PIN(143, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(144, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(145, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(146, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(147, PCIE4_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(148, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(149, QDSS_GPIO_TRACEDATA_LOCA_2, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(150, PCIE6_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(151, QDSS_GPIO_TRACECLK_LOCA, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(152, QDSS_GPIO_TRACEDATA_LOCA_8, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(153, PCIE5_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(154, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(155, PCIE3_RST_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(156, PCIE3_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(157, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(158, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(159, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(160, RESOUT_GPIO_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(161, QDSS_CTI_TRIG0_OUT_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(162, SD_WRITE_PROTECT, QDSS_CTI_TRIG1_OUT_MIRA, RES_3, RES_4, RES_5, RES_6), + PIN(163, USB0_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(164, USB0_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(165, USB0_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(166, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(167, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(168, EUSB0_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(169, EUSB3_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(170, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(171, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(172, USB1_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(173, USB1_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(174, USB1_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(175, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(176, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(177, EUSB1_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(178, EUSB6_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(179, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(180, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(181, USB2_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(182, USB2_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(183, USB2_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(184, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(185, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(186, EUSB2_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(187, EUSB5_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(188, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(189, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(190, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(191, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(192, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(193, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(194, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(195, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(196, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(197, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(198, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(199, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(200, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(201, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(202, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(203, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(204, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(205, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(206, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(207, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(208, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(209, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(210, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(211, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(212, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(213, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(214, WCN_SW_CTRL, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(215, RES_1, QDSS_CTI_TRIG1_IN_MIRB, RES_3, RES_4, RES_5, RES_6), + PIN(216, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(217, RES_1, QDSS_CTI_TRIG0_IN_MIRB, RES_3, RES_4, RES_5, RES_6), + PIN(218, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(219, RES_1, QDSS_GPIO_TRACEDATA_LOCB_0, RES_3, RES_4, RES_5, RES_6), + PIN(220, RES_1, QDSS_GPIO_TRACEDATA_LOCB_1, RES_3, RES_4, RES_5, RES_6), + PIN(221, WCN_SW_CTRL_WL_CX, RES_2, QDSS_GPIO_TRACEDATA_LOCB_2, RES_4, RES_5, RES_6), + PIN(222, RES_1, QDSS_GPIO_TRACEDATA_LOCB_3, RES_3, RES_4, RES_5, RES_6), + PIN(223, RES_1, QDSS_GPIO_TRACEDATA_LOCB_4, RES_3, RES_4, RES_5, RES_6), + PIN(224, RES_1, QDSS_GPIO_TRACEDATA_LOCB_5, RES_3, RES_4, RES_5, RES_6), + PIN(225, RES_1, QDSS_GPIO_TRACEDATA_LOCB_6, RES_3, RES_4, RES_5, RES_6), + PIN(226, RES_1, QDSS_GPIO_TRACEDATA_LOCB_7, RES_3, RES_4, RES_5, RES_6), + PIN(227, RES_1, QDSS_GPIO_TRACECLK_LOCB, RES_3, RES_4, RES_5, RES_6), + PIN(228, RES_1, QDSS_GPIO_TRACECTL_LOCB, RES_3, RES_4, RES_5, RES_6), + PIN(229, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(230, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(231, QDSS_GPIO_TRACEDATA_LOCB_10, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(232, QDSS_GPIO_TRACEDATA_LOCB_11, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(233, QDSS_GPIO_TRACEDATA_LOCB_12, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(234, QDSS_GPIO_TRACEDATA_LOCB_13, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(235, ASC_CCI_I2C_SDA3, QDSS_GPIO_TRACEDATA_LOCB_14, RES_3, RES_4, RES_5, RES_6), + PIN(236, ASC_CCI_I2C_SCL3, QDSS_GPIO_TRACEDATA_LOCB_15, RES_3, RES_4, RES_5, RES_6), + PIN(237, QDSS_GPIO_TRACEDATA_LOCB_8, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(238, QDSS_GPIO_TRACEDATA_LOCB_9, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(239, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(240, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(241, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(242, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(243, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(244, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(245, SMB_ACOK_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(246, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(247, QUP3_SE0_L7, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(248, PMC_UVA_N, RES_2, RES_3, RES_4, RES_5, RES_6), + PIN(249, PMC_OCA_N, RES_2, RES_3, RES_4, RES_5, RES_6), +}; + +#endif /* __SOC_QUALCOMM_CALYPSO_GPIO_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/mmu.h b/src/soc/qualcomm/calypso/include/soc/mmu.h new file mode 100644 index 00000000000..115fdafe133 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_MMU_H__ +#define __SOC_QUALCOMM_CALYPSO_MMU_H__ + +void soc_mmu_init(void); + +#endif /* __SOC_QUALCOMM_CALYPSO_MMU_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/qcom_qmp_phy.h b/src/soc/qualcomm/calypso/include/soc/qcom_qmp_phy.h new file mode 100644 index 00000000000..7b6b6a2b188 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/qcom_qmp_phy.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * QMP PHY register definitions for Qualcomm Calypso SoC + * PCIe5 4-lane (5x4) PHY + */ + +#ifndef __SOC_QUALCOMM_CALYPSO_QMP_PHY_H__ +#define __SOC_QUALCOMM_CALYPSO_QMP_PHY_H__ + +/* QMP V5 4L PHY - PLL registers (offsets from PLL base) */ +#define QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V5_PLL_CLK_EP_DIV_MODE1 0x0c +#define QSERDES_V5_PLL_CP_CTRL_MODE1 0x10 +#define QSERDES_V5_PLL_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V5_PLL_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V5_PLL_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V5_PLL_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V5_PLL_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V5_PLL_DEC_START_MODE1 0x28 +#define QSERDES_V5_PLL_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V5_PLL_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V5_PLL_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V5_PLL_HSCLK_SEL_1 0x3c +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x54 +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x58 +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c +#define QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V5_PLL_CLK_EP_DIV_MODE0 0x6c +#define QSERDES_V5_PLL_CP_CTRL_MODE0 0x70 +#define QSERDES_V5_PLL_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V5_PLL_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V5_PLL_CORECLK_DIV_MODE0 0x7c +#define QSERDES_V5_PLL_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V5_PLL_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V5_PLL_DEC_START_MODE0 0x88 +#define QSERDES_V5_PLL_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V5_PLL_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V5_PLL_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V5_PLL_HSCLK_HS_SWITCH_SEL_1 0x9c +#define QSERDES_V5_PLL_BG_TIMER 0xbc +#define QSERDES_V5_PLL_SSC_EN_CENTER 0xc0 +#define QSERDES_V5_PLL_SSC_PER1 0xcc +#define QSERDES_V5_PLL_SSC_PER2 0xd0 +#define QSERDES_V5_PLL_POST_DIV_MUX 0xd8 +#define QSERDES_V5_PLL_BIAS_EN_CLKBUFLR_EN 0xdc +#define QSERDES_V5_PLL_CLK_ENABLE1 0xe0 +#define QSERDES_V5_PLL_SYS_CLK_CTRL 0xe4 +#define QSERDES_V5_PLL_PLL_IVCO 0xf4 +#define QSERDES_V5_PLL_CMN_IETRIM 0xfc +#define QSERDES_V5_PLL_SYSCLK_EN_SEL 0x110 +#define QSERDES_V5_PLL_LOCK_CMP_EN 0x120 +#define QSERDES_V5_PLL_LOCK_CMP_CFG 0x124 +#define QSERDES_V5_PLL_VCO_TUNE_CTRL 0x13c +#define QSERDES_V5_PLL_VCO_TUNE_MAP 0x140 +#define QSERDES_V5_PLL_CLK_SELECT 0x164 +#define QSERDES_V5_PLL_CORE_CLK_EN 0x170 +#define QSERDES_V5_PLL_CMN_CONFIG_1 0x174 +#define QSERDES_V5_PLL_CMN_MISC1 0x188 +#define QSERDES_V5_PLL_CMN_MODE 0x18c +#define QSERDES_V5_PLL_VCO_DC_LEVEL_CTRL 0x19c +#define QSERDES_V5_PLL_BIN_VCOCAL_HSCLK_SEL_1 0x1a0 +#define QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE2 0x1cc +#define QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE2 0x1d0 +#define QSERDES_V5_PLL_CP_CTRL_MODE2 0x1dc +#define QSERDES_V5_PLL_PLL_RCTRL_MODE2 0x1e0 +#define QSERDES_V5_PLL_PLL_CCTRL_MODE2 0x1e4 +#define QSERDES_V5_PLL_CORECLK_DIV_MODE2 0x1e8 +#define QSERDES_V5_PLL_LOCK_CMP1_MODE2 0x1ec +#define QSERDES_V5_PLL_LOCK_CMP2_MODE2 0x1f0 +#define QSERDES_V5_PLL_DEC_START_MODE2 0x1f4 +#define QSERDES_V5_PLL_DIV_FRAC_START1_MODE2 0x1fc +#define QSERDES_V5_PLL_DIV_FRAC_START2_MODE2 0x200 +#define QSERDES_V5_PLL_DIV_FRAC_START3_MODE2 0x204 +#define QSERDES_V5_PLL_HSCLK_SEL_2 0x21c +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE2 0x220 +#define QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE2 0x224 +#define QSERDES_V5_PLL_HSCLK_HS_SWITCH_SEL_2 0x228 +#define QSERDES_V5_PLL_CMN_CONFIG_2 0x22c +#define QSERDES_V5_PLL_BIN_VCOCAL_HSCLK_SEL_2 0x230 +#define QSERDES_V5_PLL_PLL_SPARE_FOR_ECO 0x2b8 +#define QSERDES_V5_PLL_DCC_CAL_1 0x2d8 +#define QSERDES_V5_PLL_DCC_CAL_2 0x2dc +#define QSERDES_V5_PLL_DCC_CAL_3 0x2e0 +#define QSERDES_V5_PLL_PSM_CAL_EN 0x2f0 +#define QSERDES_V5_PLL_CLK_FWD_CONFIG_1 0x2f4 +#define QSERDES_V5_PLL_IP_CTRL_AND_DP_SEL 0x2fc +#define QSERDES_V5_PLL_DCC_CAL_7 0x300 +#define QSERDES_V5_PLL_DCC_CAL_8 0x304 +#define QSERDES_V5_PLL_DCC_CAL_9 0x308 + +/* QMP V5 4L PHY - TXRXZ broadcast registers (offsets from TXRXZ base) */ +#define QSERDES_V5_TXRX_CLKBUF_ENABLE 0x4c +#define QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL1 0x70 +#define QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL2 0x74 +#define QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL3 0x78 +#define QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL4 0x7c +#define QSERDES_V5_TXRX_LANE_MODE_1 0x94 +#define QSERDES_V5_TXRX_LANE_MODE_2 0x98 +#define QSERDES_V5_TXRX_LANE_MODE_3 0x9c +#define QSERDES_V5_TXRX_LANE_MODE_4 0xa0 +#define QSERDES_V5_TXRX_RESTRIM_CAL_CTRL 0xb0 +#define QSERDES_V5_TXRX_RESTRIM_POST_CAL_OFFSET 0xb8 +#define QSERDES_V5_TXRX_RESTRIM_VREF_SEL 0xbc +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B0 0xf4 +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B1 0xf8 +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B2 0xfc +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B3 0x100 +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B4 0x104 +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B5 0x108 +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B6 0x10c +#define QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B7 0x110 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B0 0x114 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B1 0x118 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B2 0x11c +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B3 0x120 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B4 0x124 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B5 0x128 +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B6 0x12c +#define QSERDES_V5_TXRX_RX_MODE_RATE2_B7 0x130 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B0 0x134 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B1 0x138 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B2 0x13c +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B3 0x140 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B4 0x144 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B5 0x148 +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B6 0x14c +#define QSERDES_V5_TXRX_RX_MODE_RATE3_B7 0x150 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B0 0x154 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B1 0x158 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B2 0x15c +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B3 0x160 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B4 0x164 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B5 0x168 +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B6 0x16c +#define QSERDES_V5_TXRX_RX_MODE_RATE4_B7 0x170 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE0 0x1b4 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE0 0x1b8 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE1 0x1bc +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE1 0x1c0 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE2 0x1c4 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE2 0x1c8 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE3 0x1cc +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE3 0x1d0 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE4 0x1d4 +#define QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE4 0x1d8 +#define QSERDES_V5_TXRX_CDR_VCTRL_RATE_0_1 0x1dc +#define QSERDES_V5_TXRX_CDR_VCTRL_RATE_2_3 0x1e0 +#define QSERDES_V5_TXRX_CDR_VCTRL_RATE_4 0x1e4 +#define QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL2 0x2c8 +#define QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL3 0x2cc +#define QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL4 0x2d0 +#define QSERDES_V5_TXRX_KVCO_CODE_OVRD_RATE2 0x1fc +#define QSERDES_V5_TXRX_KVCO_CODE_OVRD_RATE4 0x204 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE0 0x220 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE0 0x224 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE1 0x228 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE1 0x22c +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE2 0x230 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE2 0x234 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE3 0x238 +#define QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE4 0x240 +#define QSERDES_V5_TXRX_KP_CODE_OVRD_RATE4 0x254 +#define QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0 0x258 +#define QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1 0x260 +#define QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2 0x268 +#define QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3 0x270 +#define QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4 0x278 +#define QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0 0x280 +#define QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1 0x284 +#define QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2 0x288 +#define QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3 0x28c +#define QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4 0x290 +#define QSERDES_V5_TXRX_RX_SUMMER_CAL_SPD_MODE_RATE_0123 0x2a8 +#define QSERDES_V5_TXRX_RX_IDAC_ENABLES 0x310 +#define QSERDES_V5_TXRX_SIGDET_ENABLES 0x31c +#define QSERDES_V5_TXRX_SIGDET_CNTRL 0x320 +#define QSERDES_V5_TXRX_SIGDET_LVL 0x324 +#define QSERDES_V5_TXRX_SIGDET_CAL_TRIM 0x334 +#define QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE0 0x33c +#define QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE1 0x340 +#define QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE2 0x344 +#define QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE3 0x348 +#define QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE4 0x34c +#define QSERDES_V5_TXRX_CDR_PHASE_LOCK_CNT_RATE4 0x360 +#define QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE0 0x368 +#define QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE1 0x36c +#define QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE2 0x370 +#define QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE3 0x374 +#define QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE4 0x378 +#define QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE0 0x37c +#define QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE1 0x380 +#define QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE2 0x384 +#define QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE3 0x388 +#define QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE4 0x38c +#define QSERDES_V5_TXRX_CDR_FLL_DIV_RATIO_RATE_0123 0x390 +#define QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE_01 0x398 +#define QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE_23 0x39c +#define QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE4 0x3a0 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE_0_1 0x3a4 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE_2_3 0x3a8 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE4 0x3ac +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE_0_1 0x3b0 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE_2_3 0x3b4 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE4 0x3b8 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE_0_1 0x3bc +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE_2_3 0x3c0 +#define QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE4 0x3c4 +#define QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_RATE_0123 0x3c8 +#define QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_RATE4 0x3cc +#define QSERDES_V5_TXRX_CDR_VCO_TYPE_CONFIG 0x3d0 +#define QSERDES_V5_TXRX_CDR_VCO_EN_LOWFREQ 0x3d4 +#define QSERDES_V5_TXRX_CDR_LOOP_FUNC_CTRL 0x3dc +#define QSERDES_V5_TXRX_CDR_FAST_LOCK_EN_CTRL 0x3e0 +#define QSERDES_V5_TXRX_RX_RCVR_EN 0x3e4 +#define QSERDES_V5_TXRX_RES_CODE_LANE_OFFSET_RX 0x3f4 +#define QSERDES_V5_TXRX_GM_CAL_RES_RATE0_1 0x404 +#define QSERDES_V5_TXRX_GM_CAL_RES_RATE2_3 0x408 +#define QSERDES_V5_TXRX_GM_CAL_RES_RATE4 0x40c +#define QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL3 0x454 +#define QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL4 0x458 +#define QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL5 0x45c +#define QSERDES_V5_TXRX_CTLE_POST_CAL_OFFSET_RATE_3_4 0x47c +#define QSERDES_V5_TXRX_VGA_CAL_CNTRL1 0x488 +#define QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE0_1 0x490 +#define QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE2_3 0x494 +#define QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE4 0x498 +#define QSERDES_V5_TXRX_VTHRESH_CAL_CNTRL1 0x4a4 +#define QSERDES_V5_TXRX_VTHRESH_CAL_MAN_VAL_RATE4 0x4bc +#define QSERDES_V5_TXRX_DFE_TAP1_DAC_ENABLE 0x50c +#define QSERDES_V5_TXRX_DFE_TAP2_DAC_ENABLE 0x510 +#define QSERDES_V5_TXRX_DFE_TAP345_DAC_ENABLE 0x514 +#define QSERDES_V5_TXRX_DFE_TAP67_DAC_ENABLE 0x518 +#define QSERDES_V5_TXRX_PHPRE_CTRL 0x51c +#define QSERDES_V5_TXRX_TX_ADAPT_POST_THRESH1 0x52c +#define QSERDES_V5_TXRX_TX_ADAPT_POST_THRESH2 0x530 +#define QSERDES_V5_TXRX_TX_ADPT_CTRL 0x53c +#define QSERDES_V5_TXRX_CDR_IQTUNE_CTRL 0x548 +#define QSERDES_V5_TXRX_CDR_IQTUNE_MAN_INDEX 0x550 +#define QSERDES_V5_TXRX_CDR_IQTUNE_CLK0_CAL_CODE_RATE4 0x56c +#define QSERDES_V5_TXRX_CDR_IQTUNE_ANA_CTRL 0x584 +#define QSERDES_V5_TXRX_CDR_IQTUNE_DIV2_CTRL_RATE0123 0x58c +#define QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_OVRD_MUXES 0x5ac +#define QSERDES_V5_TXRX_VCO_CTUNE_LOWER_BND_RATE2 0x5b8 +#define QSERDES_V5_TXRX_VCO_CTUNE_LOWER_BND_RATE3 0x5bc +#define QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE0 0x5c4 +#define QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE1 0x5c8 +#define QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE2 0x5cc +#define QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE3 0x5d0 +#define QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE4 0x5d4 +#define QSERDES_V5_TXRX_CDR_LOCK_KP_OFFSET_RATE4 0x5fc +#define QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE0 0x600 +#define QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE1 0x604 +#define QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE2 0x608 +#define QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE3 0x60c +#define QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE4 0x610 +#define QSERDES_V5_TXRX_DIG_BKUP_CTRL16 0x7ec +#define QSERDES_V5_TXRX_KVCO_INIT_RATE_0_1 0x1e8 +#define QSERDES_V5_TXRX_KVCO_INIT_RATE_2_3 0x1ec +#define QSERDES_V5_TXRX_KVCO_INIT_RATE_4 0x1f0 + +/* QMP V5 4L PHY - PCS COM registers (offsets from PCS_COM base) */ +#define QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG2 0x6c +#define QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG5 0x78 +#define QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG6 0x7c +#define QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG7 0x80 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG2 0xa0 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG3 0xa4 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG5 0xac +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG6 0xb0 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG7 0xb4 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG8 0xb8 +#define QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG10 0xc0 +#define QPHY_PCIE5_PCS_COM_ENDPOINT_REFCLK_DRIVE 0xc8 +#define QPHY_PCIE5_PCS_COM_RX_SIGDET_LVL 0xec +#define QPHY_PCIE5_PCS_COM_OSC_DTCT_ACTIONS 0x194 +#define QPHY_PCIE5_PCS_COM_LOCK_DETECT_CONFIG2 0x1c0 +#define QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG1 0x1dc +#define QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG2 0x1e0 +#define QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG3 0x1e4 +#define QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG7 0x1f4 +#define QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG8 0x1f8 +#define QPHY_PCIE5_PCS_COM_EQ_CONFIG1 0x380 +#define QPHY_PCIE5_PCS_COM_EQ_CONFIG2 0x384 +#define QPHY_PCIE5_PCS_COM_G345_EQ_CONFIG1 0x38c +#define QPHY_PCIE5_PCS_COM_G345_EQ_CONFIG3 0x394 +#define QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG1 0x3a4 +#define QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG5 0x3b4 +#define QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG7 0x3bc +#define QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG1 0x3c8 +#define QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG5 0x3d8 +#define QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG7 0x3e0 +#define QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG1 0x3ec +#define QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG5 0x3fc +#define QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG7 0x404 + +/* QMP V5 4L PHY - PCS LANEZ broadcast registers (offsets from PCS_LANEZ base) */ +#define QPHY_PCIE5_PCS_LANEZ_OUTSIG_MX_CTRL2 0xe0 +#define QPHY_PCIE5_PCS_LANEZ_OUTSIG_MX_CTRL5 0xf8 + +#endif /* __SOC_QUALCOMM_CALYPSO_QMP_PHY_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h new file mode 100644 index 00000000000..6e5711d3ba6 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_QUP_SE_H__ +#define __SOC_QUALCOMM_CALYPSO_QUP_SE_H__ + +#include +#include +#include +#include +#include +#include + +enum qup_se { + QUPV3_0_SE0, + QUPV3_0_SE1, + QUPV3_0_SE2, + QUPV3_0_SE3, + QUPV3_0_SE4, + QUPV3_0_SE5, + QUPV3_0_SE6, + QUPV3_0_SE7, + QUPV3_1_SE0, + QUPV3_1_SE1, + QUPV3_1_SE2, + QUPV3_1_SE3, + QUPV3_1_SE4, + QUPV3_1_SE5, + QUPV3_1_SE6, + QUPV3_1_SE7, + QUPV3_2_SE0, + QUPV3_2_SE1, + QUPV3_2_SE2, + QUPV3_2_SE3, + QUPV3_2_SE4, + QUPV3_2_SE5, + QUPV3_2_SE6, + QUPV3_2_SE7, + QUPV3_3_SE0, + QUPV3_3_SE1, + QUPV3_SE_MAX, +}; + +struct qup { + struct qup_regs *regs; + gpio_t pin[4]; + u8 func[4]; +}; + +extern struct qup qup[QUPV3_SE_MAX]; + +/* TODO: update MAX_OFFSET_CFG_REG as per datasheet */ +#define MAX_OFFSET_CFG_REG 0x000001c4 + +#endif /* __SOC_QUALCOMM_CALYPSO_QUP_SE_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/shrm.h b/src/soc/qualcomm/calypso/include/soc/shrm.h new file mode 100644 index 00000000000..8e3f7102ebf --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/shrm.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_SHRM_H__ +#define __SOC_QUALCOMM_CALYPSO_SHRM_H__ + +void shrm_fw_load_reset(void); + +#endif // __SOC_QUALCOMM_CALYPSO_SHRM_H__ diff --git a/src/soc/qualcomm/calypso/include/soc/uart.h b/src/soc/qualcomm/calypso/include/soc/uart.h new file mode 100644 index 00000000000..1684b9ba12a --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/uart.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_CALYPSO_UART_TX_H__ +#define __SOC_QUALCOMM_CALYPSO_UART_TX_H__ + +/* TODO: update as per datasheet */ +#define UART_TX_PIN GPIO(86) + +#endif /* __SOC_QUALCOMM_CALYPSO_UART_TX_H__ */ diff --git a/src/soc/qualcomm/calypso/include/soc/variant.h b/src/soc/qualcomm/calypso/include/soc/variant.h new file mode 100644 index 00000000000..924c34d6474 --- /dev/null +++ b/src/soc/qualcomm/calypso/include/soc/variant.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_VARIANT_H_ +#define _SOC_QUALCOMM_X1P42100_VARIANT_H_ + +void mainboard_soc_init(void); + +#endif /* _SOC_QUALCOMM_X1P42100_VARIANT_H_ */ diff --git a/src/soc/qualcomm/calypso/memlayout.ld b/src/soc/qualcomm/calypso/memlayout.ld new file mode 100644 index 00000000000..7041a9b4ee6 --- /dev/null +++ b/src/soc/qualcomm/calypso/memlayout.ld @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + * The linker script below configures the memory layout for the Qualcomm Calypso SoC. + * + * The memory map and addressing scheme are implemented according to the official Qualcomm + * Hardware Reference Document (HRD) for this specific SoC. + * + * 0x10000000000 +----------------------------------------------------------+ <-------------- + * | dram_space_2 | DRAM Space 2 ^ + * 0x8800000000 +----------------------------------------------------------+ <--------- | + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX | + * 0x1000000000 +----------------------------------------------------------+ <--------- | + * | dram_space_1 | DRAM Space 1 | + * 0x880000000 +----------------------------------------------------------+ <--------- | + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX | + * 0x100000000 +----------------------------------------------------------+ <--------- | + * | dram_smem (Shared Memory) | ^ | + * 0xFFE00000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0xE6900000 +----------------------------------------------------------+ | | + * | dram_display | | | + * 0xE4800000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0xD9632000 +----------------------------------------------------------+ | | + * | dram_ta | | | + * 0xD7800000 +----------------------------------------------------------+ | | + * | dram_tz (TrustZone) | | | + * 0xD7180000 +----------------------------------------------------------+ | | + * | BL31 (ARM Trusted Firmware) | | | + * 0xD7029000 +----------------------------------------------------------+ | DRAM + * | dram_tz_ac | | | + * 0xD7019000 +----------------------------------------------------------+ | | + * | dram_hyp_ac | | | + * 0xD7000000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0xA1800000 +----------------------------------------------------------+ | | + * | RAMSTAGE | DRAM Space 0 | + * 0x94F00000 +----------------------------------------------------------+ | | + * | POSTRAM_CBFS_CACHE | | | + * 0x93F00000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x91380000 +----------------------------------------------------------+ | | + * | dram_pil | | | + * 0x86E10000 +----------------------------------------------------------+ | | + * | CBMEM | | | + * +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x85F80000 +----------------------------------------------------------+ | | + * | dram_wlan | | | + * 0x85300000 +----------------------------------------------------------+ | | + * | dram_adsp_rpc_heap | | | + * 0x84A00000 +----------------------------------------------------------+ | | + * 0x85380000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x84400000 +----------------------------------------------------------+ | | + * | dram_ncc | | | + * 0x84000000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x82800000 +----------------------------------------------------------+ | | + * | dram_tz_static | | | + * 0x82700000 +----------------------------------------------------------+ | | + * | dram_pdp_ns | | | + * 0x81E00000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x81CF4000 +----------------------------------------------------------+ | | + * | dram_dc_log | | | + * 0x81CF0000 +----------------------------------------------------------+ | | + * | dram_tme_log | | | + * 0x81CE0000 +----------------------------------------------------------+ | | + * | dram_tme_crashdump | | | + * 0x81CA0000 +----------------------------------------------------------+ | | + * | dram_aop_config | | | + * 0x81C80000 +----------------------------------------------------------+ | | + * | dram_aop_cmd_db | | | + * 0x81C60000 +----------------------------------------------------------+ | | + * | dram_aop | | | + * 0x81C00000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | + * 0x81C00000 +----------------------------------------------------------+ | | + * | dram_ramdump | | | + * 0x81A40000 +----------------------------------------------------------+ | | + * | dram_xbl_log | | | + * 0x81A00000 +----------------------------------------------------------+ | | + * | POSTRAM_DMA_COHERENT | | | + * 0x81860000 +----------------------------------------------------------+ | | + * | POSTRAM_STACK | | | + * 0x81860000 +----------------------------------------------------------+ | | + * | dram_pdp_cdb | | | + * 0x814CC000 +----------------------------------------------------------+ | | + * | dram_pdp | | | + * 0x81400000 +----------------------------------------------------------+ | | + * | dram_cpucp | | | + * 0x80900000 +----------------------------------------------------------+ | | + * | dram_llcc_lpi | v v + * 0x80000000 +----------------------------------------------------------+ <-------------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x20260000 +----------------------------------------------------------+ <--------- + * | shrm | SHRM + * 0x20220000 +----------------------------------------------------------+ <--------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x1DB80000 +----------------------------------------------------------+ <--------- + * | cpucp | CPUCP + * 0x1DB00000 +----------------------------------------------------------+ <--------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x14A80000 +----------------------------------------------------------+ <--------- + * | auth_metadata | ^ + * 0x14A7F000 +----------------------------------------------------------+ | + * | debug_policy | | + * 0x14A7E000 +----------------------------------------------------------+ | + * | OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE | | + * 0x14A60000 +----------------------------------------------------------+ | + * | PRERAM_CBMEM_CONSOLE | | + * 0x14A5A000 +----------------------------------------------------------+ | + * | qclib | | + * 0x148A0000 +----------------------------------------------------------+ | + * | PRERAM_CBFS_CACHE | | + * 0x14870000 +----------------------------------------------------------+ | + * | cdt_data (optional) | | + * 0x1486F000 +----------------------------------------------------------+ | + * | cpr_settings | | + * 0x1486E000 +----------------------------------------------------------+ | + * | apdp_ramdump_meta | | + * 0x1486D000 +----------------------------------------------------------+ | + * | aop_blob_meta | | + * 0x14869000 +----------------------------------------------------------+ | + * | qc_blob_meta | | + * 0x14865000 +----------------------------------------------------------+ | + * | ddr_training | | + * 0x14855000 +----------------------------------------------------------+ | + * | dcb (DDR Config Block) | | + * 0x14847000 +----------------------------------------------------------+ | + * | FMAP_CACHE | | + * 0x14846800 +----------------------------------------------------------+ BSRAM + * | CBFS_MCACHE | | + * 0x14841000 +----------------------------------------------------------+ | + * | qclib_serial_log | | + * 0x14840000 +----------------------------------------------------------+ | + * | PRERAM_DMA_COHERENT | | + * 0x1483E000 +----------------------------------------------------------+ | + * | VBOOT2_WORK | | + * 0x1483B000 +----------------------------------------------------------+ | + * | PRERAM_STACK | | + * 0x14837000 +----------------------------------------------------------+ | + * | TTB (Translation Table Base) | | + * 0x14829000 +----------------------------------------------------------+ | + * | TIMESTAMP | | + * 0x14828000 +----------------------------------------------------------+ | + * | BOOTBLOCK | | + * 0x14819000 +----------------------------------------------------------+ | + * | pbl_timestamps | v + * 0x14800000 +----------------------------------------------------------+ <--------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x146AC000 +----------------------------------------------------------+ <--------- + * | WATCHDOG_TOMBSTONE | ^ + * 0x146ABFFC +----------------------------------------------------------+ | + * | ddr_information | | + * 0x146ABFE8 +----------------------------------------------------------+ | + * | shared_imem | | + * 0x146AA000 +----------------------------------------------------------+ | + * | aop_imem | | + * 0x146A8000 +----------------------------------------------------------+ SSRAM + * | qdss_usb_trace | | + * 0x146A6000 +----------------------------------------------------------+ | + * | delta_dcb | | + * 0x146A2000 +----------------------------------------------------------+ | + * | dtb (Device Tree Blob) | | + * 0x14692000 +----------------------------------------------------------+ | + * | aop_sdi | | + * 0x14686000 +----------------------------------------------------------+ | + * | Reserved for QSEE | v + * 0x14680000 +----------------------------------------------------------+ <--------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x0EF30000 +----------------------------------------------------------+ <--------- + * | spel_rvss_dram | ^ + * 0x0EF24000 +----------------------------------------------------------+ | + * | spel_rvss_iram | | + * 0x0EF20000 +----------------------------------------------------------+ | + * | ... Usable memory ... | | + * 0x0B128000 +----------------------------------------------------------+ | + * | aop_data_ram | | + * 0x0B100000 +----------------------------------------------------------+ AOP SRAM + * | ... Usable memory ... | | + * 0x0B0D8000 +----------------------------------------------------------+ | + * | aop_code_ram | | + * 0x0B080000 +----------------------------------------------------------+ | + * | ... Usable memory ... | | + * 0x0B000000 +----------------------------------------------------------+ v + * +----------------------------------------------------------+ <--------- + * + */ + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop_code_ram, 0x0B080000, 0x58000, 4K) + REGION(aop_data_ram, 0x0B100000, 0x28000, 4K) + REGION(spel_rvss_iram, 0x0EF20000, 16K, 4k) + REGION(spel_rvss_dram, 0x0EF24000, 8k, 4k) + AOPSRAM_END(0x0EF30000) + + + SSRAM_START(0x14680000) + REGION(qsee, 0x14680000, 24K, 4K) + REGION(aop_sdi, 0x14686000, 48K, 4K) + REGION(dtb, 0x14692000, 64K, 4K) + REGION(delta_dcb, 0x146A2000, 16K, 4K) + REGION(qdss_usb_trace, 0x146A6000, 8K, 4K) + REGION(aop_imem, 0x146A8000, 8K, 4K) + REGION(shared_imem, 0x146AA000, 0x1000, 4K) + REGION(ddr_information, 0x146ABFE8, 16, 8) + WATCHDOG_TOMBSTONE(0x146ABFFC, 4) + SSRAM_END(0x146AC000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14819000, 60K) + TIMESTAMP(0x14828000, 4K) + TTB(0x14829000, 56K) + PRERAM_STACK(0x14837000, 16K) + VBOOT2_WORK(0x1483B000, 12K) + PRERAM_DMA_COHERENT(0x1483E000, 8K) + REGION(qclib_serial_log, 0x14840000, 4K, 4K) + CBFS_MCACHE(0x14841000,22K) + FMAP_CACHE(0x14846800, 2K) + REGION(dcb, 0x14847000, 56K, 4K) + REGION(ddr_training, 0x14855000, 64K, 4K) + REGION(qc_blob_meta, 0x14865000, 16K, 4K) + REGION(aop_blob_meta, 0x14869000, 16K, 4K) + REGION(apdp_ramdump_meta, 0x1486D000, 4K, 4K) + REGION(cpr_settings, 0x1486E000, 4K, 4K) +#if CONFIG(SOC_QUALCOMM_CDT) + REGION(cdt_data, 0x1486F000, 4K, 4K) +#endif + PRERAM_CBFS_CACHE(0x14870000, 192K) + REGION(qclib, 0x148A0000, 1728K, 4K) + PRERAM_CBMEM_CONSOLE(0x14A50000, 24K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A56000, 160K) + REGION(debug_policy, 0x14A7E000, 4K, 4K) + REGION(auth_metadata, 0x14A7F000, 4K, 4K) + BSRAM_END(0x14A80000) + + REGION(cpucp, 0x1DB00000, 512K , 4K) + + REGION(shrm, 0x20220000, 256k , 4K) + + DRAM_START(0x80000000) + REGION(dram_llcc_lpi, 0x80000000, 0x900000, 4K) + REGION(dram_cpucp, 0x80900000, 0xB00000, 4K) + REGION(dram_pdp, 0x81400000, 0xCC000, 4K) + REGION(dram_pdp_cdb, 0x814CC000, 0x394000, 4K) + POSTRAM_STACK(0x81860000, 32K) + POSTRAM_DMA_COHERENT(0x81868000, 16K) + REGION(dram_xbl_log, 0x81A00000, 0x40000, 4K) + REGION(dram_ramdump, 0x81A40000, 0x1C0000, 4K) + REGION(dram_aop, 0x81C00000, 0x60000, 4K) + REGION(dram_aop_cmd_db, 0x81C60000, 0x20000, 4K) + REGION(dram_aop_config, 0x81C80000, 0x20000, 4K) + REGION(dram_tme_crashdump, 0x81CA0000, 0x40000, 4K) + REGION(dram_tme_log, 0x81CE0000, 0x10000, 4K) + REGION(dram_dc_log, 0x81CF0000, 0x10000, 4K) + REGION(dram_pdp_ns, 0x81E00000, 0x200000, 4K) + REGION(dram_tz_static, 0x82700000, 0x100000, 4K) + REGION(dram_ncc, 0x84000000, 0x400000, 4K) + REGION(dram_adsp_rpc_heap, 0x84A00000, 0x900000, 4K) + REGION(dram_pil, 0x86E10000, 0xD0F0000, 4K) + POSTRAM_CBFS_CACHE(0x93F00000, 16M) + RAMSTAGE(0x94F00000, 16M) + + REGION(dram_hyp_ac, 0xD7000000, 0x19000, 4K) + REGION(dram_tz_ac, 0xD7019000, 0x10000, 4K) + BL31(0xD7029000, 800K) + REGION(dram_tz, 0xD7180000, 0x680000, 4K) + REGION(dram_ta, 0xD7800000, 0x1C00000, 4K) + REGION(dram_display, 0xE4800000, 0x2100000, 4K) + REGION(dram_smem, 0xFFE00000, 0x200000, 4K) + DRAM_END(0x100000000) + + /* + * Define the address range limits for fragmented DRAM regions. + * + * These regions, `dram_space_1` and `dram_space_2`, are used to map physical + * memory beyond the initial `_dram` region. The MMU configuration logic in + * `mmu.c` uses `REGION_SIZE()` to dynamically size these ranges based on the + * total system DRAM capacity, which is determined by the QCLib. + * + * Example for a 16GB DRAM system: + * - `_dram` (2GB): 0x80000000 - 0x100000000 + * - `_dram_space_1` (14GB): 0x880000000 - 0x440000000 (0x880000000 + 14GB) + * + * Note: The example memory addresses are for illustration and depend on the + * platform's specific memory map. + */ + REGION(dram_space_1, 0x880000000, 0x780000000, 4K) + REGION(dram_space_2, 0x8800000000, 0x7800000000, 4K) +} diff --git a/src/soc/qualcomm/calypso/mmu.c b/src/soc/qualcomm/calypso/mmu.c new file mode 100644 index 00000000000..9279d8e1a00 --- /dev/null +++ b/src/soc/qualcomm/calypso/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void soc_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/calypso/pcie.c b/src/soc/qualcomm/calypso/pcie.c new file mode 100644 index 00000000000..e8ee595eacd --- /dev/null +++ b/src/soc/qualcomm/calypso/pcie.c @@ -0,0 +1,593 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* PMIC B SPMI slave ID */ +#define PMIC_B_SID 1 +#define NVME_REG_EN 14 + +/* PCIe5 4-lane (5x4) QMP PHY init sequence */ + +/* PLL (serdes) registers */ +static const struct qcom_qmp_phy_init_tbl calypso_qmp_pcie5_serdes_tbl[] = { + /* Enable L and R bias */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CLK_FWD_CONFIG_1, 0x0F), + /* Gen5 PLL charge pump adjustment */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE2, 0xAB), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CP_CTRL_MODE2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_RCTRL_MODE2, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_CCTRL_MODE2, 0x36), + /* Set gen5 coreclk divider */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CORECLK_DIV_MODE2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP1_MODE2, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP2_MODE2, 0x1A), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DEC_START_MODE2, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START1_MODE2, 0xAB), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START2_MODE2, 0xAA), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START3_MODE2, 0x02), + /* Set binary VCO cal comp value Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE2, 0xA4), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18), + /* Gen3/4 PLL settings */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_CCTRL_MODE1, 0x36), + /* Set gen3 coreclk divider */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP1_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP2_MODE1, 0x0D), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START1_MODE1, 0xAB), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START2_MODE1, 0xAA), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START3_MODE1, 0x02), + /* Set binary VCO cal comp value Gen3/4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0C), + /* Set HSCLK divider for Gen1 and Gen3 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_HSCLK_SEL_1, 0x3C), + /* Set HSCLK divider for Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_HSCLK_SEL_2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_HSCLK_SEL_1, 0x3C), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_HSCLK_SEL_2, 0x01), + /* Gen1/2 PLL settings */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE1_MODE0, 0xE0), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_CCTRL_MODE0, 0x36), + /* Set gen1 coreclk divider */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CORECLK_DIV_MODE0, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP1_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP2_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START1_MODE0, 0xAB), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START2_MODE0, 0xAA), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DIV_FRAC_START3_MODE0, 0x01), + /* Set binary VCO cal comp value Gen1/2 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE1_MODE0, 0xD4), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03), + /* Set HSCLK divider for Gen2 and Gen4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_HSCLK_HS_SWITCH_SEL_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_HSCLK_HS_SWITCH_SEL_2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BG_TIMER, 0x0A), + /* Phase-based vs binary VCO calibration */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_VCO_TUNE_CTRL, 0x40), + /* Downspread SSC enabled */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SSC_PER2, 0x02), + /* Set HSCLK divider for gen1/2, gen3/4, gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_POST_DIV_MUX, 0xC0), + /* Enable right and left side clock buffers and bias */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_BIAS_EN_CLKBUFLR_EN, 0x1F), + /* Enable endpoint clock drive with pulldown when off */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CLK_ENABLE1, 0x90), + /* Select SW endpoint enable */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SYS_CLK_CTRL, 0x82), + /* Adjust VCO current */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_IVCO, 0x0F), + /* Select SE cmos clock input */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_SYSCLK_EN_SEL, 0x08), + /* Lock count = 512, lock range = +/-64 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP_EN, 0x46), + /* Use same range values for all lock iterations */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_LOCK_CMP_CFG, 0x04), + /* Set mode0 as gen1/2, mode1 as gen3/4, mode2 as gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_VCO_TUNE_MAP, 0x24), + /* Set rchng clock as endpoint refclk source during relock */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CLK_SELECT, 0x34), + /* Set PLL lock clock divider. Enable automatic div2 in hs_switch */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CORE_CLK_EN, 0xE0), + /* Set gen1/2 PLL feedback divide to 6 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CMN_CONFIG_1, 0x86), + /* Set hs_switch as part of rate change */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CMN_MISC1, 0x88), + /* VCCA selected as input to Vreg */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CMN_MODE, 0x14), + /* Increase Vreg */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_VCO_DC_LEVEL_CTRL, 0x0F), + /* Enable VCO div3 before Epclk div circuit in Gen12 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CMN_CONFIG_2, 0x10), + /* Set EP divider in Gen3/4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CLK_EP_DIV_MODE1, 0x14), + /* Set EP divider in Gen1/2 */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CLK_EP_DIV_MODE0, 0x32), + /* Enable DCC calibration */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PSM_CAL_EN, 0x05), + /* Enable PCS control of SSC_EN */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_PLL_SPARE_FOR_ECO, 0x40), + /* Invert analog comp sign */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_1, 0x40), + /* Skip PLL digital DCC cal */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_2, 0x07), + /* Increase cal wait-time to 65 cycles */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_3, 0x60), + /* Zero DCC code for right driver stage */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_7, 0x20), + /* Force DCC code for VCO stage */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_8, 0x36), + /* Zero DCC code for left driver stage */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_DCC_CAL_9, 0x20), + /* Enable ip50/ie50 to lanes */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_IP_CTRL_AND_DP_SEL, 0xAF), + /* Adjust IE trim */ + QMP_PHY_INIT_CFG(QSERDES_V5_PLL_CMN_IETRIM, 0x1B), +}; + +/* + * TXRXZ broadcast registers (applied to all 4 lanes simultaneously) + * Contains RX mode, CDR, sigdet, and TX adaptation settings + */ +static const struct qcom_qmp_phy_init_tbl calypso_qmp_pcie5_txrxz_tbl[] = { + /* Force use of local bias, bypass pulse width filter */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_SIGDET_ENABLES, 0x1C), + /* Rx setting adjustment for G3 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B0, 0xCF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B1, 0xA1), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B2, 0x7C), + /* 0x71: PCIE5/PCIE3A instance */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B3, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B5, 0x5E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B6, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE2_B7, 0x23), + /* Rx setting adjustment for G4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B0, 0xCE), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B1, 0xB3), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B2, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B3, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B4, 0x2C), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B5, 0x5D), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B6, 0x2D), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE3_B7, 0x3B), + /* Rx setting adjustment for G5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B0, 0xAF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B1, 0xC6), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B2, 0xC3), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B3, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B4, 0x8C), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B5, 0x5E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE4_B7, 0x7A), + /* Adjust Gen4 summer speed */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x6F), + /* Adjust txadpt post thresholds */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_TX_ADAPT_POST_THRESH2, 0x0D), + /* Use QSRV pre-adapt algorithm */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_PHPRE_CTRL, 0x20), + /* Use CTLE code for TX post adaption */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_TX_ADPT_CTRL, 0x30), + /* Rx setting adjustment for G1/G2 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B0, 0xEF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B1, 0x48), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B2, 0x5C), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B4, 0x2A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B5, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B6, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_MODE_RATE_0_1_B7, 0x1D), + /* Si adjustment */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_LANE_MODE_2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_LANE_MODE_3, 0x41), + /* Update BLW cap */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_LANE_MODE_4, 0x00), + /* LDO control */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL3, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_PCIE5_TOP_LDO_CODE_CTRL4, 0x8D), + /* DFE Tap control per rate */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_DFE_TAP1_DAC_ENABLE, 0x1C), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_DFE_TAP2_DAC_ENABLE, 0x1C), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_DFE_TAP345_DAC_ENABLE, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_DFE_TAP67_DAC_ENABLE, 0x10), + /* Adjust charge pump current per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE2, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE3, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_FLL_RATE4, 0x0A), + /* 0x01: PCIE5/PCIE3A instance */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE3, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_CP_CUR_PLL_RATE4, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FLL_DIV_RATIO_RATE_0123, 0x94), + /* Adjust filter RC code */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE_01, 0x66), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE_23, 0x57), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_CCODE_RATE4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x22), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FAST_RATE4, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_FLL_RATE4, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_RCODE_PLL_RATE4, 0x02), + /* Adjust Fastlock charge pump current per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE2, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE3, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FASTLOCK_CP_CUR_PLL_RATE4, 0x03), + /* Use Iqtune bypass code */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_IQTUNE_CTRL, 0x5A), + /* Upper band adjustment per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4, 0xFF), + /* Lower band adjustment per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4, 0x08), + /* Iqtune adjustment */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_IQTUNE_MAN_INDEX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_IQTUNE_CLK0_CAL_CODE_RATE4, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_IQTUNE_ANA_CTRL, 0x00), + /* 0x5F: PCIE5/PCIE3A instance. Adjust div2/div4 path setting in Gen1/2/3/4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x5F), + /* Adjust VCO measure count per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE0, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE0, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26), + /* 0x85: PCIE5/PCIE3A instance. Adjust VCO measure count */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x85), + /* 0x1E: PCIE5/PCIE3A instance. Adjust VCO measure count */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE3, 0xCC), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE3, 0x3D), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT1_RATE4, 0xCC), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CTUNE_MEAS_CNT2_RATE4, 0x3D), + /* Adjust summer cal ref source per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL2, 0x83), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL3, 0x44), + /* 0x02: std/med channel. 0x03: long channel. 0x02: short channel */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_IVCM_CAL_CTRL4, 0x02), + /* CTLE adaptor force control per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL3, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL4, 0xAA), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_EQU_ADAPTOR_CNTRL5, 0x0A), + /* VGA adaptor force value per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE0_1, 0xDD), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE2_3, 0xDB), + /* 0x04: std/med channel. 0x08: long channel. 0x00: short channel */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VGA_CAL_MAN_VAL_RATE4, 0x04), + /* 0x15: PCIE5/PCIE3A instance. Enable override for all rates */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x15), + /* 0x7F: PCIE5/PCIE3A instance. Force VCO cap code values Gen1-4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_RATE_0123, 0x7F), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_CAP_CODE_RATE4, 0x01), + /* Adjust KVCO freq target per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE0, 0x2B), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00), + /* 0x35: PCIE5/PCIE3A instance. Adjust KVCO freq target Gen3 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE3, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_IDEAL_FREQ_DIFF1_RATE4, 0x20), + /* Adjust KVCO init */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_INIT_RATE_0_1, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_INIT_RATE_2_3, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_INIT_RATE_4, 0x01), + /* Adjust delay for freq_lock_detect per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE0, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE1, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE2, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE3, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_FREQ_LOCK_DET_DLY_RATE4, 0xFF), + /* Adjust common mode voltage input per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCTRL_RATE_0_1, 0x34), + /* 0x43: PCIE5/PCIE3A instance. Adjust common mode voltage input Gen3/4 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCTRL_RATE_2_3, 0x43), + /* Adjust common mode voltage input Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCTRL_RATE_4, 0x03), + /* 0x07: PCIE5/PCIE3A instance. Enable slow VCO in Gen1/2/3 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_TYPE_CONFIG, 0x07), + /* Override KP/KVCO code for Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KP_CODE_OVRD_RATE4, 0x03), + /* 0x03: PCIE5/PCIE3A instance. Override KVCO code, Gen3 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_CODE_OVRD_RATE2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_KVCO_CODE_OVRD_RATE4, 0x04), + /* Enable LD-6bit and VCO boost prop gain */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOOP_FUNC_CTRL, 0xD0), + /* GM Cal resistor setting per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_GM_CAL_RES_RATE0_1, 0xCC), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_GM_CAL_RES_RATE2_3, 0x8A), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_GM_CAL_RES_RATE4, 0x09), + /* VCO lowfreq enable Gen1-5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_VCO_EN_LOWFREQ, 0x1F), + /* Resistor trim Vref sel */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RESTRIM_VREF_SEL, 0x16), + /* Force pd_iq low */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_RCVR_EN, 0x08), + /* RX resistor code offset */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RES_CODE_LANE_OFFSET_RX, 0x17), + /* Bypass restrim calibration and use one from refgen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RESTRIM_CAL_CTRL, 0x08), + /* Resistor trim postcal offset */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RESTRIM_POST_CAL_OFFSET, 0x10), + /* Adjust CTLE post cal offset Gen4/5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CTLE_POST_CAL_OFFSET_RATE_3_4, 0x67), + /* Manual VGA mode and update Gen5 KVGA gain control */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VGA_CAL_CNTRL1, 0x00), + /* Manual Vthresh mode */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VTHRESH_CAL_CNTRL1, 0x04), + /* Enable cdr_refclk clock gate */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CLKBUF_ENABLE, 0x40), + /* Adjust VCO coarse lower band per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_LOWER_BND_RATE2, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_LOWER_BND_RATE3, 0x11), + /* Adjust upper coarse tune band per Gen */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE0, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE1, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE2, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE3, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VCO_CTUNE_UPPER_BND_RATE4, 0x1E), + /* Use smaller sigdet threshold step size */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_SIGDET_CNTRL, 0x2F), + /* Adjust sigdet level */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_SIGDET_LVL, 0x84), + /* Adjust sigdet cal trim */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_SIGDET_CAL_TRIM, 0x66), + /* Set R2 analog controls through reserved interface */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_DIG_BKUP_CTRL16, 0x6E), + /* Enable all samplers */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_RX_IDAC_ENABLES, 0xFF), + /* Vthresh cal manual value (long channel: use 0x70) */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_VTHRESH_CAL_MAN_VAL_RATE4, 0x56), + /* Adjust phase lock count Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_PHASE_LOCK_CNT_RATE4, 0x80), + /* Enhance PLL locking range during FLL-PLL transition Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_FAST_LOCK_EN_CTRL, 0x10), + /* Adjust KP offset Gen5 */ + QMP_PHY_INIT_CFG(QSERDES_V5_TXRX_CDR_LOCK_KP_OFFSET_RATE4, 0x20), +}; + +/* PCS COM registers */ +static const struct qcom_qmp_phy_init_tbl calypso_qmp_pcie5_pcs_tbl[] = { + /* + * Maxpclk handshake enabled and l1p12 to l1p0 disabled. + * Keep PLL/EP clock on in P2 until CLKREQ# goes high. + */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG2, 0x3D), + /* Enable PCLK 32khz toggle in L1SS/P2 for DCD aging */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG5, 0xE4), + /* Extend pipe clk toggles during L1SS/P2 entry */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG6, 0x1F), + /* Enable SSC control by PCS and mask during CDR cal */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_POWER_STATE_CONFIG7, 0x0D), + /* Adjust Pinf RTB depth */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG2, 0xE4), + /* Adjust local blockalign and holdoff-only features */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG3, 0x30), + /* G12 Rxvalid asserted by snoop comma lock */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG5, 0x05), + /* Zero rxvalid extend cycles, eight rxclk extend cycles */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG6, 0x08), + /* P0 rxvalid assert wait count 1 microsecond */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG7, 0x20), + /* P0s rxvalid assert wait count 1 microsecond */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG8, 0x20), + /* G345 Rxvalid asserted by snoop block align */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_PCS_TX_RX_CONFIG10, 0x40), + /* Enable endpoint refclk drive */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ENDPOINT_REFCLK_DRIVE, 0xC1), + /* Adjust sigdet level */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_RX_SIGDET_LVL, 0x66), + /* Disable osc detect */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_OSC_DTCT_ACTIONS, 0x00), + /* Disable doubling of P0 holdoff time in G2 */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_LOCK_DETECT_CONFIG2, 0x00), + /* Set 4us holdoff time */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG2, 0x04), + /* Detect 2 EIEOS for alignment, WDT increment 8us steps */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG3, 0x1F), + /* Enable WDT Gen4/5 */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG7, 0x35), + /* Wait for cdr_lock indication to start alignment holdoff */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_ALIGN_DETECT_CONFIG8, 0x3E), + /* Flip post inc/dec mappings */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_EQ_CONFIG1, 0x06), + /* Select DFE freeze release w/o align */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_EQ_CONFIG2, 0x1C), + /* Disable background BLW */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G345_EQ_CONFIG1, 0x07), + /* Disable early training G3/G4/G5 */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G345_EQ_CONFIG3, 0x00), + /* Disable Vth adaptation, run CTLE only during G3 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG1, 0x00), + /* Enable Pass2 during G3 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG5, 0x90), + /* Run CTLE only during G3 Pass2 Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G3_EQ_CONFIG7, 0x0D), + /* Disable Vth adaptation, run CTLE only during G4 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG1, 0x00), + /* Enable Pass2 during G4 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG5, 0x90), + /* Run CTLE only during G4 Pass2 Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G4_EQ_CONFIG7, 0x0D), + /* Disable Vth adaptation, run CTLE only during G5 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG1, 0x00), + /* Enable Pass2 during G5 DC Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG5, 0x90), + /* Run CTLE only during G5 Pass2 Rxeq */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_COM_G5_EQ_CONFIG7, 0x0D), +}; + +/* PCS LANEZ broadcast registers */ +static const struct qcom_qmp_phy_init_tbl calypso_qmp_pcie5_pcs_lanez_tbl[] = { + /* + * 0x00: Link partner Tx Preset adjusted during G34 RxEq training + * 0x55: Link partner Tx Preset fixed + */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_LANEZ_OUTSIG_MX_CTRL2, 0x00), + /* + * 0x00: Link partner Tx Preset adjusted during G5 RxEq training + * 0x05: Link partner Tx Preset fixed + */ + QMP_PHY_INIT_CFG(QPHY_PCIE5_PCS_LANEZ_OUTSIG_MX_CTRL5, 0x00), +}; + +static pcie_cntlr_cfg_t pcie_host = { + .parf = (void *)PCIE5_PCIE_PARF, + .dbi_base = (void *)PCIE5_GEN1X4_PCIE_DBI, + .elbi = (void *)PCIE5_GEN1X4_PCIE_ELBI, + .atu_base = (void *)PCIE5_GEN1X4_DWC_PCIE_DM_IATU, + .cfg_base = (void *)(PCIE5_GEN1X4_PCIE_DBI + PCIE_EP_CONF_OFFSET), + .pcie_bcr = (void *)PCIE5_BCR, + .qmp_phy_bcr = (void *)GCC_PCIE_5_PHY_BCR, + .lanes = PCIE_1x4_NUM_LANES, + .cfg_size = PCIE_EP_CONF_SIZE, + .perst = GPIO(152), + + /* Store the IO and MEM space settings for future use by the ATU */ + .io.phys_start = PCIE5_GEN1X4_PCIE_DBI + PCIE_IO_SPACE_OFFSET, + .io.size = PCIE_IO_SPACE_SIZE, + .mem.phys_start = PCIE5_GEN1X4_PCIE_DBI + PCIE_MMIO_SPACE_OFFSET, + .mem.size = PCIE5_SPACE_END_ADDR, +}; + +static pcie_qmp_phy_cfg_t pcie5_qmp_phy_1x4 = { + .qserdes_pll = (void *)PCIE5_QMP_PHY_SERDES, + .qserdes_txrx0 = (void *)PCIE5_QMP_PHY_TXRX0, + .qserdes_txrx1 = (void *)PCIE5_QMP_PHY_TXRX1, + .qserdes_txrx2 = (void *)PCIE5_QMP_PHY_TXRX2, + .qserdes_txrx3 = (void *)PCIE5_QMP_PHY_TXRX3, + .qserdes_txrxz = (void *)PCIE5_QMP_PHY_TXRXZ, + .pcs_com = (void *)PCIE5_QMP_PHY_PCS_COM, + .pcs_lane0 = (void *)PCIE5_QMP_PHY_PCS_LANE0, + .pcs_lane1 = (void *)PCIE5_QMP_PHY_PCS_LANE1, + .pcs_lane2 = (void *)PCIE5_QMP_PHY_PCS_LANE2, + .pcs_lane3 = (void *)PCIE5_QMP_PHY_PCS_LANE3, + .pcs_lanez = (void *)PCIE5_QMP_PHY_PCS_LANEZ, + + .serdes_tbl = calypso_qmp_pcie5_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(calypso_qmp_pcie5_serdes_tbl), + .txrxz_tbl = calypso_qmp_pcie5_txrxz_tbl, + .txrxz_tbl_num = ARRAY_SIZE(calypso_qmp_pcie5_txrxz_tbl), + .pcs_tbl = calypso_qmp_pcie5_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(calypso_qmp_pcie5_pcs_tbl), + .pcs_lanez_tbl = calypso_qmp_pcie5_pcs_lanez_tbl, + .pcs_lanez_tbl_num = ARRAY_SIZE(calypso_qmp_pcie5_pcs_lanez_tbl), +}; + +/* Enable PIPE clock */ +int qcom_dw_pcie_enable_pipe_clock(void) +{ + /* Keep memory and peripheral core powered during clock halt */ + clock_configure_force_mem_core_on(&gcc->pcie_5.pipe_cbcr, true); + clock_configure_force_mem_periph_on(&gcc->pcie_5.pipe_cbcr, true); + + /* Set pipe clock source */ + if (clock_configure_mux(GCC_PCIE_5_PIPE_MUXR, GCC_PCIE_5_PIPE_SRC_SEL)) { + printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__); + return -1; + } + + return 0; +} + +/* Enable controller specific clocks */ +int32_t qcom_dw_pcie_enable_clock(void) +{ + int32_t ret, clk, gdsc; + + /* Enable GDSCs */ + for (gdsc = PCIE_5_GDSC; gdsc < MAX_GDSC; gdsc++) { + ret = clock_enable_gdsc(gdsc); + if (ret) { + printk(BIOS_ERR, "%s: failed to enable GDSC %d\n", + __func__, gdsc); + return ret; + } + } + + /* Disable HW_CTL */ + clock_configure_hw_ctl(&gcc->pcie_5_cfg_ahb_cbcr, false); + clock_configure_hw_ctl(&gcc->pcie_5.slv_axi_cbcr, false); + clock_configure_hw_ctl(&gcc->pcie_5.qmip_pcie_5_ahb_cbcr, false); + clock_configure_hw_ctl(&gcc->anoc_pcie_pwrctl_cbcr, false); + clock_configure_hw_ctl(&gcc->pcie_noc.hscnoc_pcie_sf_qtc_cbcr, false); + + /* Configure PHY RCHNG clock to 100 MHz */ + ret = clock_configure_pcie(); + if (ret) { + printk(BIOS_ERR, "%s: failed to configure PCIE5 PHY RCHNG clock\n", + __func__); + return ret; + } + + /* Enable PCIe clocks */ + for (clk = GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK; clk < PCIE_CLK_COUNT; clk++) { + if (clk == GCC_PCIE_5_PIPE_MUXR) + continue; + + ret = clock_enable_pcie(clk); + if (ret) + printk(BIOS_WARNING, "%s: failed to enable PCIe clock %d (skipping)\n", + __func__, clk); + } + + write32(TCSR_PCIE_1_CLKREF_EN__PCIE_ENABLE, 0x1); + + return 0; +} + +/* Turn on NVMe */ +void gcom_pcie_power_on_ep(void) +{ + pmic_gpio_output(PMIC_B_SID, NVME_REG_EN, true); +} + +/* Turn off NVMe */ +void gcom_pcie_power_off_ep(void) +{ + pmic_gpio_output(PMIC_B_SID, NVME_REG_EN, false); +} + +void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg) +{ + host_cfg->cntlr_cfg = &pcie_host; + host_cfg->qmp_phy_cfg = &pcie5_qmp_phy_1x4; +} diff --git a/src/soc/qualcomm/calypso/qclib.c b/src/soc/qualcomm/calypso/qclib.c new file mode 100644 index 00000000000..506221a7672 --- /dev/null +++ b/src/soc/qualcomm/calypso/qclib.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +__weak int qclib_mainboard_override(struct qclib_cb_if_table *table) { return 0; } + +int qclib_soc_override(struct qclib_cb_if_table *table) +{ + size_t data_size; + + /* Attempt to load DCB Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_DCB), _dcb, REGION_SIZE(dcb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /dcb failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0); + + /* Attempt to load DTB Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_DTB), _dtb, REGION_SIZE(dtb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /dtb failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_DTB_SETTINGS, _dtb, data_size, 0); + + /* Attempt to load CPR Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_CPR), _cpr_settings, REGION_SIZE(cpr_settings)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /cpr failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_CPR_SETTINGS, _cpr_settings, data_size, 0); + + if (!qclib_check_dload_mode()) { + /* Attempt to load shrm_meta Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META), + _qc_blob_meta, REGION_SIZE(qc_blob_meta)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /shrm_meta failed\n", __func__); + return -1; + } + + qclib_add_if_table_entry(QCLIB_TE_SHRM_META_SETTINGS, _qc_blob_meta, data_size, 0); + } + + /* hook for platform specific policy configuration */ + if (qclib_mainboard_override(table)) { + printk(BIOS_ERR, "qclib_mainboard_override failed\n"); + return -1; + } + + return 0; +} diff --git a/src/soc/qualcomm/calypso/qcom_qup_se.c b/src/soc/qualcomm/calypso/qcom_qup_se.c new file mode 100644 index 00000000000..53ae41f5fdf --- /dev/null +++ b/src/soc/qualcomm/calypso/qcom_qup_se.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct qup qup[QUPV3_SE_MAX] = { + [QUPV3_0_SE0] = { .regs = (void *)QUP_SERIAL0_BASE, + .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) }, + .func = { GPIO0_FUNC_QUP0_SE0_L0, GPIO1_FUNC_QUP0_SE0_L1, + GPIO2_FUNC_QUP0_SE0_L2, GPIO3_FUNC_QUP0_SE0_L3 } + }, + [QUPV3_0_SE1] = { .regs = (void *)QUP_SERIAL1_BASE, + .pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) }, + .func = { GPIO4_FUNC_QUP0_SE1_L0, GPIO5_FUNC_QUP0_SE1_L1, + GPIO6_FUNC_QUP0_SE1_L2, GPIO7_FUNC_QUP0_SE1_L3 } + }, + [QUPV3_0_SE2] = { .regs = (void *)QUP_SERIAL2_BASE, + .pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) }, + .func = { GPIO8_FUNC_QUP0_SE2_L0, GPIO9_FUNC_QUP0_SE2_L1, + GPIO10_FUNC_QUP0_SE2_L2, GPIO11_FUNC_QUP0_SE2_L3 } + }, + [QUPV3_0_SE3] = { .regs = (void *)QUP_SERIAL3_BASE, + .pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) }, + .func = { GPIO12_FUNC_QUP0_SE3_L0, GPIO13_FUNC_QUP0_SE3_L1, + GPIO14_FUNC_QUP0_SE3_L2, GPIO15_FUNC_QUP0_SE3_L3 } + }, + [QUPV3_0_SE4] = { .regs = (void *)QUP_SERIAL4_BASE, + .pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) }, + .func = { GPIO16_FUNC_QUP0_SE4_L0, GPIO17_FUNC_QUP0_SE4_L1, + GPIO18_FUNC_QUP0_SE4_L2, GPIO19_FUNC_QUP0_SE4_L3 } + }, + [QUPV3_0_SE5] = { .regs = (void *)QUP_SERIAL5_BASE, + .pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) }, + .func = { GPIO20_FUNC_QUP0_SE5_L0, GPIO21_FUNC_QUP0_SE5_L1, + GPIO22_FUNC_QUP0_SE5_L2, GPIO23_FUNC_QUP0_SE5_L3 } + }, + [QUPV3_0_SE6] = { .regs = (void *)QUP_SERIAL6_BASE, + .pin = { GPIO(6), GPIO(7), GPIO(4), GPIO(5) }, + .func = { GPIO6_FUNC_QUP0_SE6_L0, GPIO7_FUNC_QUP0_SE6_L1, + GPIO4_FUNC_QUP0_SE6_L2, GPIO5_FUNC_QUP0_SE6_L3 } + }, + [QUPV3_0_SE7] = { .regs = (void *)QUP_SERIAL7_BASE, + .pin = { GPIO(14), GPIO(15), GPIO(12), GPIO(13) }, + .func = { GPIO14_FUNC_QUP0_SE7_L0, GPIO15_FUNC_QUP0_SE7_L1, + GPIO12_FUNC_QUP0_SE7_L2, GPIO13_FUNC_QUP0_SE7_L3 } + }, + [QUPV3_1_SE0] = { .regs = (void *)QUP_SERIAL8_BASE, + .pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) }, + .func = { GPIO32_FUNC_QUP1_SE0_L0, GPIO33_FUNC_QUP1_SE0_L1, + GPIO34_FUNC_QUP1_SE0_L2, GPIO35_FUNC_QUP1_SE0_L3 } + }, + [QUPV3_1_SE1] = { .regs = (void *)QUP_SERIAL9_BASE, + .pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) }, + .func = { GPIO36_FUNC_QUP1_SE1_L0, GPIO37_FUNC_QUP1_SE1_L1, + GPIO38_FUNC_QUP1_SE1_L2, GPIO39_FUNC_QUP1_SE1_L3 } + }, + [QUPV3_1_SE2] = { .regs = (void *)QUP_SERIAL10_BASE, + .pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) }, + .func = { GPIO40_FUNC_QUP1_SE2_L0, GPIO41_FUNC_QUP1_SE2_L1, + GPIO42_FUNC_QUP1_SE2_L2, GPIO43_FUNC_QUP1_SE2_L3 } + }, + [QUPV3_1_SE3] = { .regs = (void *)QUP_SERIAL11_BASE, + .pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) }, + .func = { GPIO44_FUNC_QUP1_SE3_L0, GPIO45_FUNC_QUP1_SE3_L1, + GPIO46_FUNC_QUP1_SE3_L2, GPIO47_FUNC_QUP1_SE3_L3 } + }, + [QUPV3_1_SE4] = { .regs = (void *)QUP_SERIAL12_BASE, + .pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) }, + .func = { GPIO48_FUNC_QUP1_SE4_L0, GPIO49_FUNC_QUP1_SE4_L1, + GPIO50_FUNC_QUP1_SE4_L2, GPIO51_FUNC_QUP1_SE4_L3 } + }, + [QUPV3_1_SE5] = { .regs = (void *)QUP_SERIAL13_BASE, + .pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) }, + .func = { GPIO52_FUNC_QUP1_SE5_L0, GPIO53_FUNC_QUP1_SE5_L1, + GPIO54_FUNC_QUP1_SE5_L2, GPIO55_FUNC_QUP1_SE5_L3 } + }, + [QUPV3_1_SE6] = { .regs = (void *)QUP_SERIAL14_BASE, + .pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) }, + .func = { GPIO56_FUNC_QUP1_SE6_L0, GPIO57_FUNC_QUP1_SE6_L1, + GPIO58_FUNC_QUP1_SE6_L2, GPIO59_FUNC_QUP1_SE6_L3 } + }, + [QUPV3_1_SE7] = { .regs = (void *)QUP_SERIAL15_BASE, + .pin = { GPIO(54), GPIO(55), GPIO(52), GPIO(53) }, + .func = { GPIO54_FUNC_QUP1_SE7_L0, GPIO55_FUNC_QUP1_SE7_L1, + GPIO52_FUNC_QUP1_SE7_L2, GPIO53_FUNC_QUP1_SE7_L3 } + }, + [QUPV3_2_SE0] = { .regs = (void *)QUP_SERIAL16_BASE, + .pin = { GPIO(64), GPIO(65), GPIO(66), GPIO(67) }, + .func = { GPIO64_FUNC_QUP2_SE0_L0, GPIO65_FUNC_QUP2_SE0_L1, + GPIO66_FUNC_QUP2_SE0_L2, GPIO67_FUNC_QUP2_SE0_L3 } + }, + [QUPV3_2_SE1] = { .regs = (void *)QUP_SERIAL17_BASE, + .pin = { GPIO(68), GPIO(69), GPIO(70), GPIO(71) }, + .func = { GPIO68_FUNC_QUP2_SE1_L0, GPIO69_FUNC_QUP2_SE1_L1, + GPIO70_FUNC_QUP2_SE1_L2, GPIO71_FUNC_QUP2_SE1_L3 } + }, + [QUPV3_2_SE2] = { .regs = (void *)QUP_SERIAL18_BASE, + .pin = { GPIO(72), GPIO(73), GPIO(74), GPIO(75) }, + .func = { GPIO72_FUNC_QUP2_SE2_L0, GPIO73_FUNC_QUP2_SE2_L1, + GPIO74_FUNC_QUP2_SE2_L2, GPIO75_FUNC_QUP2_SE2_L3 } + }, + [QUPV3_2_SE3] = { .regs = (void *)QUP_SERIAL19_BASE, + .pin = { GPIO(76), GPIO(77), GPIO(78), GPIO(79) }, + .func = { GPIO76_FUNC_QUP2_SE3_L0, GPIO77_FUNC_QUP2_SE3_L1, + GPIO78_FUNC_QUP2_SE3_L2, GPIO79_FUNC_QUP2_SE3_L3 } + }, + [QUPV3_2_SE4] = { .regs = (void *)QUP_SERIAL20_BASE, + .pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) }, + .func = { GPIO80_FUNC_QUP2_SE4_L0, GPIO81_FUNC_QUP2_SE4_L1, + GPIO82_FUNC_QUP2_SE4_L2, GPIO83_FUNC_QUP2_SE4_L3 } + }, + [QUPV3_2_SE5] = { .regs = (void *)QUP_SERIAL21_BASE, + .pin = { GPIO(84), GPIO(85), GPIO(86), GPIO(87) }, + .func = { GPIO84_FUNC_QUP2_SE5_L0, GPIO85_FUNC_QUP2_SE5_L1, + GPIO86_FUNC_QUP2_SE5_L2, GPIO87_FUNC_QUP2_SE5_L3 } + }, + [QUPV3_2_SE6] = { .regs = (void *)QUP_SERIAL22_BASE, + .pin = { GPIO(88), GPIO(89), GPIO(90), GPIO(91) }, + .func = { GPIO88_FUNC_QUP2_SE6_L0, GPIO89_FUNC_QUP2_SE6_L1, + GPIO90_FUNC_QUP2_SE6_L2, GPIO91_FUNC_QUP2_SE6_L3 } + }, + [QUPV3_2_SE7] = { .regs = (void *)QUP_SERIAL23_BASE, + .pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) }, + .func = { GPIO80_FUNC_QUP2_SE7_L0, GPIO81_FUNC_QUP2_SE7_L1, + GPIO82_FUNC_QUP2_SE7_L2, GPIO83_FUNC_QUP2_SE7_L3 } + }, + [QUPV3_3_SE0] = { .regs = (void *)QUP_SERIAL24_BASE, + .pin = { GPIO(129), GPIO(128), GPIO(127), GPIO(132) }, + .func = { GPIO129_FUNC_QUP3_SE0_L0, GPIO128_FUNC_QUP3_SE0_L1, + GPIO127_FUNC_QUP3_SE0_L2, GPIO132_FUNC_QUP3_SE0_L3 } + }, + [QUPV3_3_SE1] = { .regs = (void *)QUP_SERIAL25_BASE, + .pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) }, + .func = { GPIO40_FUNC_QUP3_SE1_L0, GPIO41_FUNC_QUP3_SE1_L1, + GPIO42_FUNC_QUP3_SE1_L2, GPIO43_FUNC_QUP3_SE1_L3 } + }, +}; diff --git a/src/soc/qualcomm/calypso/soc.c b/src/soc/qualcomm/calypso/soc.c new file mode 100644 index 00000000000..2f8bb75197b --- /dev/null +++ b/src/soc/qualcomm/calypso/soc.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TODO: Add any housekeeping stuffs before handing over to the BL31 */ +void soc_prepare_bl31_handoff(void) +{ + printk(BIOS_WARNING, "Inside %s:\n", __func__); +} + +static void preload_bl31(void) +{ + if (!CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE) || !CONFIG(CBFS_PRELOAD)) + return; + + cbfs_preload(CONFIG_CBFS_PREFIX"/bl31"); +} + +static void preload_bl32(void) +{ + if (!CONFIG(ARM64_USE_SECURE_OS) || !CONFIG(CBFS_PRELOAD)) + return; + + cbfs_preload(CONFIG_CBFS_PREFIX"/secure_os"); +} + +/* + * Weak implementation of mainboard-specific display initialization. + * This can be overridden by mainboard-specific code. + */ +__weak void mainboard_soc_init(void) +{ + /* Default implementation: do nothing */ +} + +static struct device_operations pci_domain_ops = { + .read_resources = &qcom_pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_host_bridge_scan_bus, + .enable = &qcom_setup_pcie_host, +}; + +static void soc_read_resources(struct device *dev) +{ + int index = 0; + int count; + struct region *config = qc_get_soc_dram_space_config(region_sz(ddr_region), &count); + + for (int i = 0; i < count; i++) + ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size); + + mmio_range(dev, index++, (uintptr_t)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db)); + + reserved_ram_range(dev, index++, (uintptr_t)_dram_ncc, REGION_SIZE(dram_ncc)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_xbl_log, REGION_SIZE(dram_xbl_log)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_ramdump, REGION_SIZE(dram_ramdump)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_aop_config, REGION_SIZE(dram_aop_config)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_crashdump, REGION_SIZE(dram_tme_crashdump)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_log, REGION_SIZE(dram_tme_log)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_dc_log, REGION_SIZE(dram_dc_log)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pdp, REGION_SIZE(dram_pdp)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pdp_cdb, REGION_SIZE(dram_pdp_cdb)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pdp_ns, REGION_SIZE(dram_pdp_ns)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_static, REGION_SIZE(dram_tz_static)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_adsp_rpc_heap, REGION_SIZE(dram_adsp_rpc_heap)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem)); +} + +static void qtee_fw_config_load(void) +{ + if (!CONFIG(ARM64_USE_SECURE_OS)) + return; + + struct prog devcfg_tz = PROG_INIT(PROG_PAYLOAD, + CONFIG_CBFS_PREFIX"/tzoem_cfg"); + if (!selfload(&devcfg_tz)) + die("devcfg_tz load failed"); + + struct prog tzqti_cfg = PROG_INIT(PROG_PAYLOAD, + CONFIG_CBFS_PREFIX"/tzqti_cfg"); + if (!selfload(&tzqti_cfg)) + die("tzqti_cfg load failed"); + + struct prog tzac_cfg = PROG_INIT(PROG_PAYLOAD, + CONFIG_CBFS_PREFIX"/tzac_cfg"); + if (!selfload(&tzac_cfg)) + die("tzac_cfg load failed"); + + struct prog hypac_cfg = PROG_INIT(PROG_PAYLOAD, + CONFIG_CBFS_PREFIX"/hypac_cfg"); + if (!selfload(&hypac_cfg)) + die("hypac_cfg load failed"); +} + +static void soc_init(struct device *dev) +{ + cpucp_pdp_fw_load_reset(); + qtee_fw_config_load(); + preload_bl31(); + preload_bl32(); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = noop_set_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + if (mainboard_needs_pcie_init()) + dev->ops = &pci_domain_ops; + else + printk(BIOS_DEBUG, "Skip setting PCIe ops\n"); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_calypso_ops = { + .name = "Calypso", + .enable_dev = enable_soc_dev, +}; + +static void soc_late_init(void *unused) +{ + /* placeholder code in sync w/ x1p42100 SoC */ + mainboard_soc_init(); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, soc_late_init, NULL); diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig index 98760cec63f..56b1eab787d 100644 --- a/src/soc/qualcomm/common/Kconfig +++ b/src/soc/qualcomm/common/Kconfig @@ -18,6 +18,15 @@ config QMP_PHY_2X2_1X4 help Selected by chipsets that have PCIE QMP PHY 2X2/1X4 +config QMP_PHY_PCIE5_1X4 + bool + default n + help + Selected by chipsets that have the PCIe5 5x4 QMP PHY. + This PHY uses a unified TXRXZ broadcast register (all 4 lanes), + PCS_LANEZ broadcast, and has different PCS_COM control register + offsets. + if SOC_QUALCOMM_COMMON config QC_SDI_ENABLE @@ -41,6 +50,24 @@ config QC_RAMDUMP_ENABLE Ramdump is a debug image that is loaded during a system crash to capture memory contents for post-crash analysis. +config QC_SKIP_SOC_DEBUG_FEATURES_IN_RECOVERY + bool + default n + help + Skip Qualcomm SoC debug features in the recovery mode. + + Select this option if the platform's recovery partition is not + sufficient to store binaries required to support Qualcomm SoC + debug features such as ramdump. + +config SOC_QUALCOMM_CDT + bool + default n + help + When enabled, the CDT data from RW_CDT partition is passed to QcLib, + which populates the platform information in SMEM. This information is + later used by depthcharge to select the platform-specific DTBO. + config SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE bool default n @@ -54,4 +81,69 @@ config SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE flushes and TLB invalidations associated with mmu_disable() and mmu_enable() calls. +config SOC_QUALCOMM_DEBUG_TSENS + bool + default n + help + When enabled, a call to monitor TSENS will dump the sensor data on + the debug console. + +config SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT + bool + default n + help + When enabled, qcom_setup_pcie_host will initiate the PCIe + hardware power-up sequence but will not block the boot flow + to wait for the link-up status. This can reduce overall + boot time, but requires late-stage drivers to verify link + readiness before access. + +config QC_DUMP_MEMCHIP_INFO + bool + default n + help + When enabled, coreboot will print detailed memory chip attributes + to the console during the boot process. This includes + Manufacturer IDs, Revision IDs, and Serial IDs for each rank. + + Note: Enabling this feature increases the size of the romstage + binary. If your platform is near its ROM size limit, this may + cause a build failure. Only enable this for memory bring-up or + debugging. + +config QC_SANITIZE_MEMCHIP_INFO + bool + default n + help + Enable this option to filter out MEM_CHIP_UNDEFINED entries from the + memory chip information table provided by the Qualcomm library (QCLib). + + When enabled, the table is collapsed in-place to remove empty slots, + ensuring that logs and downstream data consumers only see valid + memory hardware information. + + If unsure, say N. + +config QC_QDUTT_ENABLE + bool + default n + prompt "Enable QDUTT for DRAM Eye Diagram Testing" + help + QDUTT provides specialized utilities for DDR PHY training and + margin analysis. + + Enable this option to allow the collection of DRAM eye diagram + data during the bootloader training phase. This is essential for + validating signal integrity and optimizing DRAM performance + on new hardware iterations. + +config QC_SPI_DRIVE_STRENGTH_MA + int + default 3 + help + Sets the drive strength for the QSPI GPIO lines (CLK, DATA_0, DATA_1). + Lower frequencies default to 8mA (GPIO_8MA aka 3). + Allow SoC/mainboard to override the SPI drive strength as applicable. + Refer to `GPIO TLMM: Drive Strength` enum inside gpio_common.h + endif diff --git a/src/soc/qualcomm/common/aop_load_reset.c b/src/soc/qualcomm/common/aop_load_reset.c index f7465308910..1283920ab94 100644 --- a/src/soc/qualcomm/common/aop_load_reset.c +++ b/src/soc/qualcomm/common/aop_load_reset.c @@ -1,18 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include #include +#include +#include +#include void aop_fw_load_reset(void) { + /* map to cached region to force address to be 4 byte aligned */ + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); + struct prog aop_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); if (!selfload(&aop_fw_prog)) die("SOC image: AOP load failed"); + /* flush cached region */ + dcache_clean_by_mva(_aop_code_ram, REGION_SIZE(aop_code_ram)); + /* remap back to device memory */ + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), DEV_MEM); + clock_reset_aop(); } diff --git a/src/soc/qualcomm/common/cdt.c b/src/soc/qualcomm/common/cdt.c new file mode 100644 index 00000000000..757725a7f5c --- /dev/null +++ b/src/soc/qualcomm/common/cdt.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct platform_id_cdt *plat_id; +static bool cdt_initialized; + +static void cdt_init_platform_id(void) +{ + const struct cdt_header *hdr = (const struct cdt_header *)_cdt_data; + const struct cdb_meta *meta; + + cdt_initialized = true; + + if (hdr->magic != CDT_MAGIC) { + printk(BIOS_ERR, "CDT: Invalid magic 0x%08x\n", hdr->magic); + return; + } + + meta = (const struct cdb_meta *)(_cdt_data + sizeof(struct cdt_header)); + plat_id = (const struct platform_id_cdt *) + (_cdt_data + meta[CDT_BLOCK_INDEX_PLATFORM_ID].offset); +} + +ssize_t cdt_read(void *buffer, size_t buffer_size) +{ + struct region_device rdev; + ssize_t bytes_read; + size_t read_size; + + if (!buffer || buffer_size == 0) { + printk(BIOS_ERR, "CDT: Invalid buffer parameters\n"); + return 0; + } + + if (fmap_locate_area_as_rdev(CDT_REGION_NAME, &rdev) < 0) { + printk(BIOS_ERR, "CDT: Could not locate '%s' region\n", CDT_REGION_NAME); + return 0; + } + + read_size = MIN(buffer_size, region_device_sz(&rdev)); + + bytes_read = rdev_readat(&rdev, buffer, 0, read_size); + if (bytes_read < 0) { + printk(BIOS_ERR, "CDT: Failed to read data from flash\n"); + return 0; + } + + printk(BIOS_INFO, "CDT: Read %zd bytes from '%s'\n", bytes_read, CDT_REGION_NAME); + + return bytes_read; +} + +uint8_t cdt_get_platform_id(void) +{ + if (!cdt_initialized) + cdt_init_platform_id(); + + return plat_id ? plat_id->platform : 0; +} + +uint32_t cdt_get_hw_version(void) +{ + if (!cdt_initialized) + cdt_init_platform_id(); + + return plat_id ? plat_id->hw_version_major : 0; +} diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index ede523e2988..266c0f6c201 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -17,7 +17,7 @@ static bool clock_is_off(u32 *cbcr_addr) enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, uint32_t vote_bit) { - int count = 100; + int count = CLK_POLL_COUNT; setbits32(vote_addr, BIT(vote_bit)); @@ -34,7 +34,7 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, enum cb_err clock_enable(void *cbcr_addr) { - int count = 100; + int count = CLK_POLL_COUNT; /* Set clock enable bit */ setbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT)); @@ -50,6 +50,86 @@ enum cb_err clock_enable(void *cbcr_addr) return CB_ERR; } +enum cb_err clock_disable(void *cbcr_addr) +{ + int count = CLK_POLL_COUNT; + + if (!cbcr_addr) + return CB_ERR; + + /* Clear clock enable bit */ + clrbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT)); + + /* Ensure clock is disabled */ + while (count-- > 0) { + if (clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + + printk(BIOS_ERR, "Failed to disable clock, register val: 0x%x\n", + read32(cbcr_addr)); + return CB_ERR; +} + +void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable) +{ + if (!cbcr_addr) + return; + + if (enable) + setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT)); + else + clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT)); +} + +void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable) +{ + if (!cbcr_addr) + return; + + if (enable) + setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT)); + else + clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT)); +} + +void clock_configure_hw_ctl(void *cbcr_addr, bool enable) +{ + if (!cbcr_addr) + return; + + /* Enable or disable hardware-controlled clock gating */ + if (enable) + setbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT)); + else + clrbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT)); +} + +void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable) +{ + if (!cbcr_addr) + return; + + /* Forces core-on signal to stay active during clk halt */ + if (enable) + setbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT)); + else + clrbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT)); +} + +void clock_configure_force_mem_periph_on(void *cbcr_addr, bool enable) +{ + if (!cbcr_addr) + return; + + /* Forces peripheral core-on signal to stay active during clk halt */ + if (enable) + setbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_PERIPH_ON_SHFT)); + else + clrbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_PERIPH_ON_SHFT)); +} + /* Clock Block Reset Operations */ void clock_reset_bcr(void *bcr_addr, bool assert) { @@ -77,7 +157,7 @@ enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr) clrbits32(gdscr_addr, BIT(GDSC_ENABLE_BIT)); /* Ensure gdsc is enabled */ - if (!wait_us(100, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK))) + if (!wait_us(CLK_WAIT_US_TIMEOUT, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK))) return CB_ERR; return CB_SUCCESS; @@ -137,6 +217,11 @@ void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg, unsigned int idx, s = qup % QUP_WRAP1_S0; uint32_t reg_val; +#if QUP_WRAP3_BASE + if (qup >= QUP_WRAP3_S0) + qup_clk = &gcc->qup_wrap3_s[s]; + else +#endif #if QUP_WRAP2_BASE if (qup >= QUP_WRAP2_S0) qup_clk = &gcc->qup_wrap2_s[s]; @@ -227,7 +312,7 @@ enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, setbits32(cfg->reg_apcs_pll_br_en, BIT(br_enable)); /* Wait for Lock Detection */ - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { printk(BIOS_ERR, "PLL did not lock!\n"); return CB_ERR; } @@ -247,7 +332,7 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg) udelay(5); setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } @@ -269,7 +354,7 @@ enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); setbits32(cfg->reg_opmode, PLL_RUN_MODE); - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } @@ -292,7 +377,7 @@ enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg) setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); setbits32(cfg->reg_opmode, PLL_RUN_MODE); - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } @@ -312,7 +397,7 @@ enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg) setbits32(cfg->reg_opmode, PLL_RUN_MODE); setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } diff --git a/src/soc/qualcomm/common/cmd_db.c b/src/soc/qualcomm/common/cmd_db.c index fbe3acd96f4..993f873049b 100644 --- a/src/soc/qualcomm/common/cmd_db.c +++ b/src/soc/qualcomm/common/cmd_db.c @@ -5,7 +5,6 @@ #include #include #include -#include #include /** diff --git a/src/soc/qualcomm/common/include/soc/cdt.h b/src/soc/qualcomm/common/include/soc/cdt.h new file mode 100644 index 00000000000..f7d5804f75a --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/cdt.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_CDT_H_ +#define _SOC_QUALCOMM_CDT_H_ + +#include +#include +#include + +#define CDT_REGION_NAME "RW_CDT" +#define CDT_MAGIC 0x00544443 + +struct cdt_header { + uint32_t magic; + uint16_t version; + uint32_t reserved1; + uint32_t reserved2; +} __packed; + +struct cdb_meta { + uint16_t offset; + uint16_t size; +}; + +#define CDT_BLOCK_INDEX_PLATFORM_ID 0 +#define CDT_BLOCK_INDEX_DDR 1 + +struct platform_id_cdt { + uint8_t version; + uint8_t platform; + uint8_t hw_version_major; + uint8_t hw_version_minor; + uint8_t subtype; + uint8_t num_kvps; +}; + +ssize_t cdt_read(void *buffer, size_t buffer_size); +uint8_t cdt_get_platform_id(void); +uint32_t cdt_get_hw_version(void); + +#endif /* _SOC_QUALCOMM_CDT_H_ */ diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h index fd3a073d016..acd15e3671b 100644 --- a/src/soc/qualcomm/common/include/soc/clock_common.h +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -4,6 +4,8 @@ #define __SOC_QUALCOMM_COMMON_CLOCK_H__ #define QCOM_CLOCK_DIV(div) (2 * div - 1) +#define CLK_POLL_COUNT 100 +#define CLK_WAIT_US_TIMEOUT 100 /* Root Clock Generator */ struct clock_rcg { @@ -124,11 +126,20 @@ enum clk_ctl_cmd_rcgr { enum clk_ctl_cbcr { CLK_CTL_EN_SHFT = 0, + CLK_CTL_HW_CTL_SHFT = 1, CLK_CTL_ARES_SHFT = 2, + CLK_CTL_FORCE_MEM_PERIPH_ON_SHFT = 13, + CLK_CTL_FORCE_MEM_CORE_ON_SHFT = 14, + CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT = 20, + CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT = 21, CLK_CTL_OFF_SHFT = 31, CLK_CTL_EN_BMSK = 0x1, + CLK_CTL_HW_CTL_BMSK = 0x1 << CLK_CTL_HW_CTL_SHFT, CLK_CTL_ARES_BMSK = 0x1 << CLK_CTL_ARES_SHFT, - CLK_CTL_OFF_BMSK = 0x80000000, + CLK_CTL_FORCE_MEM_CORE_ON_BMSK = 0x1 << CLK_CTL_FORCE_MEM_CORE_ON_SHFT, + CLK_CTL_IGNORE_RPMH_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT, + CLK_CTL_IGNORE_PMU_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT, + CLK_CTL_OFF_BMSK = 0x1 << CLK_CTL_OFF_SHFT, }; enum clk_ctl_rcg_mnd { @@ -155,6 +166,17 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, enum cb_err clock_enable(void *cbcr_addr); +enum cb_err clock_disable(void *cbcr_addr); + +void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable); + +void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable); + +void clock_configure_hw_ctl(void *cbcr_addr, bool enable); + +void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable); +void clock_configure_force_mem_periph_on(void *cbcr_addr, bool enable); + enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr); void clock_reset_bcr(void *bcr_addr, bool assert); diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index fa1e603f085..c33660af1f7 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -32,6 +32,18 @@ #define PCIE_PARF_LTSSM 0x1B0 #define LTSSM_EN BIT(8) #define PCIE_PARF_DBI_BASE_ADDR 0x350 +#define PCIE_PARF_DBI_BASE_ADDR_HI 0x354 +#define PCIE_PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PCIE_PARF_SLV_ADDR_SPACE_SIZE_HI 0x35C +#define PCIE_PARF_ATU_BASE_ADDR_LO 0x634 +#define PCIE_PARF_ATU_BASE_ADDR_HI 0x638 +#define PCIE_PARF_DMA_BASE_ADDR_LO 0x64C +#define PCIE_PARF_DMA_BASE_ADDR_HI 0x650 +#define PCIE_PARF_L1SUB_AHB_CLK_MAX_TIMER 0x180 +#define AUX_PWR_DET BIT(4) /* PCIE_PARF_SYS_CTRL */ +#define L1SUB_CNT_MAX 0x7FFFFFFF +/* L1SS timeout: 19.2 MHz * 20 ms = 384000 cycles */ +#define L1SS_TIMEOUT_20MS (19200 * 20) #define PCIE_PARF_DEVICE_TYPE 0x1000 #define DEVICE_TYPE_RC 0x4 #define PCIE_PARF_BDF_TO_SID_CFG 0x2C00 @@ -49,8 +61,10 @@ /* ELBI */ #define PCIE3X2_ELBI_SYS_STTS 0x08 #define XMLH_LINK_UP 0x400 +#define PCIE_ELBI_LTSSM_STATE_MASK 0x3f /* bits 5:0 = LTSSM state */ /* DBI Registers */ +#define PCIE_LINK_STATUS_REG 0x80 #define PCIE_LINK_CAPABILITY 0x7c #define PCIE_LINK_CTL_2 0xa0 #define TARGET_LINK_SPEED_MASK 0xf @@ -58,6 +72,7 @@ #define LINK_SPEED_GEN_2 0x2 #define LINK_SPEED_GEN_3 0x3 #define LINK_SPEED_GEN_4 0x4 +#define LINK_SPEED_GEN_5 0x5 #define PCIE_LINK_UP_MS 100 #define PCIE_PHY_POLL_US 1000 #define LINK_WAIT_MAX_RETRIES 10 @@ -66,16 +81,113 @@ #define PCIE_SPCIE_CAP_OFF_0CH_REG 0x154 #define PCIE_SPCIE_CAP_OFF_10H_REG 0x158 #define PCIE_PL16G_CAP_OFF_20H_REG 0x188 +#define PCIE_PL32G_CAP_OFF_20H_REG 0x1C4 #define PCIE_GEN3_EQ_CONTROL_OFF 0x8A8 #define GEN3_EQ_PSET_REQ_VEC 0x00FFFF00 #define PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC -#define GEN3_EQ_FMDC_T_MIN_PHASE23 0xF +#define GEN3_EQ_FMDC_T_MIN_PHASE23 0x1F #define PCIE_GEN3_RELATED_OFF 0x890 #define RATE_SHADOW_SEL_MASK (BIT(25)|BIT(24)) #define RATE_SHADOW_SEL_VAL (BIT(24)) #define PCIE_CAP_HOT_PLUG_CAPABLE BIT(6) +#define PCIE_CAP_PHY_SLOT_NUM_MASK (0x1FFFU << 19) +#define PCIE_CAP_PHY_SLOT_NUM(n) ((u32)(n) << 19) #define PCIE_SLOT_CAPABILITIES_REG 0x84 +/* Gen5 DBI post-PHY init registers */ +#define PCIE_TYPE1_STATUS_COMMAND_REG 0x4 +#define PCIE_BME BIT(2) /* Bus Master Enable */ +#define PCIE_MSE BIT(1) /* Memory Space Enable */ +#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG 0x8 +#define BASE_CLASS_CODE_MASK 0xFF000000 +#define BASE_CLASS_CODE_BRIDGE (0x6 << 24) +#define SUBCLASS_CODE_MASK 0x00FF0000 +#define SUBCLASS_CODE_PCI_BRIDGE (0x4 << 16) +#define PCIE_TYPE1_BAR0_REG 0x10 +#define PCIE_TYPE1_BAR1_REG 0x14 +#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG 0x8C +#define PCIE_CAP_CRS_SW_VISIBILITY BIT(16) +#define PCIE_CAP_CRS_SW_VISIBILITY_EN BIT(4) +#define PCIE_ACK_F_ASPM_CTRL_OFF 0x70C +#define COMMON_CLK_N_FTS_MASK 0xFF0000 +#define COMMON_CLK_N_FTS_VAL (0x80 << 16) +#define ACK_N_FTS_MASK 0xFF00 +#define ACK_N_FTS_VAL (0x80 << 8) +#define PCIE_GEN2_CTRL_OFF 0x80C +#define NUM_OF_LANES_MASK PORT_LOGIC_LINK_WIDTH_MASK +#define NUM_OF_LANES_1 PORT_LOGIC_LINK_WIDTH_1_LANES +#define NUM_OF_LANES_4 PORT_LOGIC_LINK_WIDTH_4_LANES +#define GEN3_ZRXDC_NONCOMPL BIT(0) /* PCIE_GEN3_RELATED_OFF bit 0 */ +#define RATE_SHADOW_SEL_GEN5 BIT(25) +/* GEN3_EQ_FB_MODE_DIR_CHANGE_OFF field masks */ +#define GEN3_EQ_FMDC_T_MIN_PHASE23_MASK 0x1F +#define GEN3_EQ_FMDC_N_EVALS_MASK 0x3E0 +#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA_MASK 0x3C00 +#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA_MASK 0x3C000 +#define GEN3_EQ_FMDC_ALL_MASK (GEN3_EQ_FMDC_T_MIN_PHASE23_MASK | \ + GEN3_EQ_FMDC_N_EVALS_MASK | \ + GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA_MASK | \ + GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA_MASK) +/* Named field values for GEN3_EQ_FB_MODE_DIR_CHANGE_OFF */ +#define GEN3_EQ_FMDC_T_MIN_PHASE23_VAL 0x1 +#define GEN3_EQ_FMDC_N_EVALS_VAL (0xD << 5) +#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA_VAL (0x5 << 10) +#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA_VAL (0x5 << 14) +#define GEN3_EQ_FMDC_ALL_VAL (GEN3_EQ_FMDC_T_MIN_PHASE23_VAL | \ + GEN3_EQ_FMDC_N_EVALS_VAL | \ + GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA_VAL | \ + GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA_VAL) +/* GEN3_EQ_CONTROL_OFF additional fields */ +#define GEN3_EQ_PHASE23_EXIT_MODE BIT(4) +#define GEN3_EQ_FB_MODE_MASK 0xF +#define PCIE_L1SUB_CAP_HEADER_REG 0x1DC +#define L1SUB_NEXT_OFFSET_MASK 0xFFF00000 +#define PCIE_RAS_DES_CAP_HDR_OFFSET 0x230 /* offset to skip DPC */ +#define PCIE_QUEUE_STATUS_OFF 0x73C +#define TIMER_MOD_FLOW_CONTROL_EN BIT(31) +#define TIMER_MOD_FLOW_CONTROL_MASK 0x1FFF0000 +#define TIMER_MOD_FLOW_CONTROL_VAL (64 << 16) +/* Gen4/5 lane margining register 1 (0xB80) field masks and values */ +#define PCIE_GEN4_LANE_MARGINING_1_OFF 0xB80 +#define GEN4_MARG1_MAX_VOLT_OFF_MASK 0x3F000000 +#define GEN4_MARG1_NUM_VOLT_STEPS_MASK 0x7F0000 +#define GEN4_MARG1_MAX_TIMING_OFF_MASK 0x3F00 +#define GEN4_MARG1_NUM_TIMING_STEPS_MASK 0x3F +#define GEN4_MARG1_ALL_MASK (GEN4_MARG1_MAX_VOLT_OFF_MASK | \ + GEN4_MARG1_NUM_VOLT_STEPS_MASK | \ + GEN4_MARG1_MAX_TIMING_OFF_MASK | \ + GEN4_MARG1_NUM_TIMING_STEPS_MASK) +#define GEN4_MARG1_ALL_VAL ((0x24 << 24) | (0x78 << 16) | \ + (0x32 << 8) | 0x10) + +/* Gen4/5 lane margining register 2 (0xB84) field masks and values */ +#define PCIE_GEN4_LANE_MARGINING_2_OFF 0xB84 +#define GEN4_MARG2_IND_ERR_SAMPLER BIT(28) +#define GEN4_MARG2_SAMPLE_RPT_METHOD BIT(27) +#define GEN4_MARG2_IND_LR_TIMING BIT(26) +#define GEN4_MARG2_IND_UD_VOLTAGE BIT(25) +#define GEN4_MARG2_VOLTAGE_SUPPORTED BIT(24) +#define GEN4_MARG2_MAXLANES_MASK 0x1F0000 +#define GEN4_MARG2_SAMPLE_RATE_TIMING_MASK 0x3F00 +#define GEN4_MARG2_SAMPLE_RATE_VOLTAGE_MASK 0x3F +#define GEN4_MARG2_ALL_MASK (GEN4_MARG2_IND_ERR_SAMPLER | \ + GEN4_MARG2_SAMPLE_RPT_METHOD | \ + GEN4_MARG2_IND_LR_TIMING | \ + GEN4_MARG2_IND_UD_VOLTAGE | \ + GEN4_MARG2_VOLTAGE_SUPPORTED | \ + GEN4_MARG2_MAXLANES_MASK | \ + GEN4_MARG2_SAMPLE_RATE_TIMING_MASK | \ + GEN4_MARG2_SAMPLE_RATE_VOLTAGE_MASK) +#define GEN4_MARG2_ALL_VAL (GEN4_MARG2_IND_ERR_SAMPLER | \ + GEN4_MARG2_SAMPLE_RPT_METHOD | \ + GEN4_MARG2_IND_LR_TIMING | \ + GEN4_MARG2_VOLTAGE_SUPPORTED | \ + (0x3 << 16) | (0x3F << 8) | 0x3F) +#define PCIE_AUX_CLK_FREQ_OFF 0xB40 +#define PCIE_AUX_CLK_FREQ_19_2MHZ 0x13 +#define PCIE_PL32G_CONTROL_REG 0x1AC +#define EQ_BYPASS_HIGHEST_RATE_DISABLE BIT(0) + #define COMMAND_MASK 0xffff #define TYPE1_HDR_BUS_NUM_MASK 0xffffff @@ -144,6 +256,18 @@ #define SERDES_START BIT(0) #define PCS_START BIT(1) +/* + * PCIe5 5x4 QMP PHY PCS_COM control register offsets (from PCS_COM base). + * Bit macros SW_RESET, SW_PWRDN, REFCLK_DRV_DSBL, SERDES_START and PCS_START + * are shared with the existing PHY; only the register offsets differ. + */ +#define QPHY5_PCS_POWER_DOWN_CTRL 0x64 /* PCS_COM_POWER_DOWN_CONTROL */ +#define QPHY5_SW_RESET 0x60 /* PCS_COM_SW_RESET */ +#define QPHY5_START_CONTROL 0x5c /* PCS_COM_START_CONTROL */ +#define QPHY5_PCS_STATUS1 0x10 /* PCS_COM_PCS_STATUS1 */ +#define QPHY_PHYSTATUS BIT(7) /* PHYSTATUS in PCS_STATUS1 */ +#define QPHY5_PHY_DELAY_US 2000 /* 2ms delay before polling PCS_STATUS1 */ + /* Register address builder */ #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) #define lower_32_bits(n) ((u32)(n)) @@ -222,7 +346,27 @@ typedef struct { #endif typedef struct { -#if !CONFIG(QMP_PHY_2X2_1X4) +#if CONFIG(QMP_PHY_PCIE5_1X4) + /* Gen5 5x4 QMP PHY block base addresses */ + void *qserdes_txrx0; + void *qserdes_txrx1; + void *qserdes_txrx2; + void *qserdes_txrx3; + void *qserdes_pll; + void *pcs_com; + void *pcs_lane0; + void *pcs_lane1; + void *pcs_lane2; + void *pcs_lane3; + void *qserdes_txrxz; + void *pcs_lanez; + + /* Init tables for the TXRXZ and PCS_LANEZ broadcast blocks */ + const struct qcom_qmp_phy_init_tbl *txrxz_tbl; + unsigned int txrxz_tbl_num; + const struct qcom_qmp_phy_init_tbl *pcs_lanez_tbl; + unsigned int pcs_lanez_tbl_num; +#elif !CONFIG(QMP_PHY_2X2_1X4) void *qmp_phy_base; void *serdes; void *tx0; @@ -239,7 +383,7 @@ typedef struct { pcie_qmp_phy_base_t porta; pcie_qmp_phy_base_t portb; #endif - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + /* Init sequence table pointers shared across all PHY variants */ const struct qcom_qmp_phy_init_tbl *serdes_tbl; unsigned int serdes_tbl_num; const struct qcom_qmp_phy_init_tbl *serdes_tbl_sec; @@ -277,9 +421,14 @@ struct qcom_pcie_cntlr_t { pcie_qmp_phy_cfg_t *qmp_phy_cfg; }; +/* TCSR PCIe clkref enable (TCSR_BASE defined in soc/addressmap.h) */ +#define TCSR_PCIE_1_CLKREF_EN_OFF 0x95048 +#define TCSR_PCIE_1_CLKREF_EN__PCIE_ENABLE ((void *)(TCSR_BASE + TCSR_PCIE_1_CLKREF_EN_OFF)) + int qcom_dw_pcie_enable_clock(void); int qcom_dw_pcie_enable_pipe_clock(void); void gcom_pcie_power_on_ep(void); +void gcom_pcie_power_off_ep(void); void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg); void qcom_pci_domain_read_resources(struct device *dev); void qcom_setup_pcie_host(struct device *dev); diff --git a/src/soc/qualcomm/common/include/soc/pmic_gpio.h b/src/soc/qualcomm/common/include/soc/pmic_gpio.h new file mode 100644 index 00000000000..18a1f296866 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/pmic_gpio.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_PMIC_GPIO_H_ +#define _SOC_QUALCOMM_PMIC_GPIO_H_ + +#include +#include +#include + +#define PMIC_GPIO_BASE(num) (0x8800 + ((num - 1) * 0x100)) +#define PMIC_GPIO_NUMBER_MIN 1 +#define PMIC_GPIO_NUMBER_MAX 14 +#define PMIC_PMK_GPIO_OFFSET 0x3000 + +#define PMIC_GPIO_MODE_CTL 0x40 + #define PMIC_GPIO_MODE_OUTPUT 0x01 + #define PMIC_GPIO_MODE_INPUT 0x00 + +#define PMIC_GPIO_DIG_VIN_CTL 0x41 + #define PMIC_GPIO_DIG_VIN_VIN0 0x00 + +#define PMIC_GPIO_DIG_PULL_CTL 0x42 + +#define PMIC_GPIO_DIG_OUT_SOURCE_CTL 0x44 + #define PMIC_GPIO_DIG_OUT_SOURCE_HIGH 0x80 + #define PMIC_GPIO_DIG_OUT_SOURCE_LOW 0x00 + +#define PMIC_GPIO_DIG_OUT_CTL 0x45 + +#define PMIC_GPIO_EN_CTL 0x46 + #define PMIC_GPIO_EN_PERPH_EN 0x80 + +void pmic_gpio_configure(uint8_t sid, uint8_t gpio_num, + uint8_t source, uint8_t enable, + uint8_t mode); + +void pmic_gpio_output(uint8_t sid, uint8_t gpio_num, bool high); + +#endif // _SOC_QUALCOMM_PMIC_GPIO_H_ diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index 8ce24f2b35a..547b6d131c9 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -19,6 +19,7 @@ #define QCLIB_TE_DDR_INFORMATION "ddr_information" #define QCLIB_TE_QCLIB_LOG_BUFFER "qclib_log_buffer" #define QCLIB_TE_DCB_SETTINGS "dcb_settings" +#define QCLIB_TE_DELTA_DCB_SETTINGS "delta_dcb_settings" #define QCLIB_TE_CDT_SETTINGS "cdt_settings" #define QCLIB_TE_PMIC_SETTINGS "pmic_settings" #define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" @@ -41,6 +42,7 @@ enum qclib_cbfs_file { QCLIB_CBFS_QCSDI, QCLIB_CBFS_QCLIB, QCLIB_CBFS_DCB, + QCLIB_CBFS_DELTA_DCB, QCLIB_CBFS_DTB, QCLIB_CBFS_CPR, QCLIB_CBFS_SHRM_META, @@ -87,6 +89,7 @@ void qclib_add_if_table_entry(const char *name, void *base, void qclib_load_and_run(void); void qclib_rerun(void); int qclib_soc_override(struct qclib_cb_if_table *table); +const char *qclib_override_soc_file(enum qclib_cbfs_file file); int qclib_mainboard_override(struct qclib_cb_if_table *table); bool qclib_check_dload_mode(void); diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h index 65d2e17bbaf..bbf45b7a0b8 100644 --- a/src/soc/qualcomm/common/include/soc/qcom_spmi.h +++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h @@ -12,5 +12,7 @@ int spmi_read8(uint32_t addr); int spmi_write8(uint32_t addr, uint8_t data); int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes); +int spmi_read8_safe(uint32_t reg); +int spmi_rmw8(uint32_t addr, uint8_t mask, uint8_t value); #endif // __SOC_QCOM_SPMI_H__ diff --git a/src/soc/qualcomm/common/include/soc/qcom_tsens.h b/src/soc/qualcomm/common/include/soc/qcom_tsens.h new file mode 100644 index 00000000000..6bb82a5e30d --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/qcom_tsens.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_TSENS_H_ +#define _SOC_QUALCOMM_TSENS_H_ + +#include +#include +#include + +#define TM_SN_STATUS_OFF 0x00a0 +#define SN_STATUS_VALID (1 << 21) +#define SN_STATUS_TEMP_MASK 0xFFF + +struct tsens_controller { + const char *name; + uintptr_t tm_base; + uintptr_t srot_base; + uint32_t sensor_count; +}; + +enum sensor_type { + TYPE_TSENS +}; + +struct thermal_zone_map { + const char *label; + enum sensor_type type; + const void *ctrl; + int hw_id; + int threshold; +}; + +/* + * Iterates through all defined zones and checks thresholds. + */ +void qcom_tsens_monitor_all(bool *has_crossed_threshold); + +/* External Data (Defined in SoC file) */ +extern const struct thermal_zone_map qcom_thermal_zones[]; + +#endif /* _SOC_QUALCOMM_TSENS_H_ */ diff --git a/src/soc/qualcomm/common/include/soc/qspi_common.h b/src/soc/qualcomm/common/include/soc/qspi_common.h index 6e4b779aee1..f3140fe97f7 100644 --- a/src/soc/qualcomm/common/include/soc/qspi_common.h +++ b/src/soc/qualcomm/common/include/soc/qspi_common.h @@ -97,6 +97,7 @@ static struct qcom_qspi_regs * const qcom_qspi = (void *)QSPI_BASE; #define QSPI_MAX_PACKET_COUNT 0xFFC0 +void qspi_set_bus_clock(uint32_t hz); void quadspi_init(uint32_t hz); int qspi_claim_bus(const struct spi_slave *slave); int qspi_setup_bus(const struct spi_slave *slave); @@ -105,4 +106,7 @@ int qspi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes); int qspi_xfer_dual(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes); + +/* SoC override */ +void qspi_configure_gpios(void); #endif /* __SOC_QUALCOMM_QSPI_H__ */ diff --git a/src/soc/qualcomm/common/include/soc/qupv3_config_common.h b/src/soc/qualcomm/common/include/soc/qupv3_config_common.h index 0993d860f46..8ef1b74f436 100644 --- a/src/soc/qualcomm/common/include/soc/qupv3_config_common.h +++ b/src/soc/qualcomm/common/include/soc/qupv3_config_common.h @@ -39,7 +39,7 @@ #define GSI_FW_MAGIC_HEADER 0x20495351 #define GSI_REG_BASE_SIZE 0x5000 -#define GSI_INST_RAM_n_MAX_n 4095 +#define GSI_INST_RAM_n_MAX_n 5800 #define GSI_FW_BYTES_PER_LINE 8 #define GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 #define GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 847225216ab..eca0eb2b15c 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -15,22 +15,28 @@ DECLARE_OPTIONAL_REGION(dram_aop_cmd_db) DECLARE_REGION(dram_aop_config) DECLARE_REGION(dram_soc) DECLARE_REGION(dcb) +DECLARE_OPTIONAL_REGION(delta_dcb) DECLARE_REGION(dtb) DECLARE_REGION(cpr_settings) DECLARE_REGION(qc_blob_meta) DECLARE_REGION(aop_blob_meta) DECLARE_REGION(apdp_ramdump_meta) +DECLARE_OPTIONAL_REGION(cdt_data) DECLARE_OPTIONAL_REGION(pmic) DECLARE_REGION(limits_cfg) DECLARE_REGION(aop) DECLARE_REGION(modem_id) DECLARE_REGION(aop_code_ram) DECLARE_REGION(aop_data_ram) +DECLARE_OPTIONAL_REGION(spel_rvss_iram) +DECLARE_OPTIONAL_REGION(spel_rvss_dram) DECLARE_REGION(dram_modem_wifi_only) DECLARE_REGION(dram_modem_extra) DECLARE_REGION(dram_wlan) DECLARE_REGION(dram_wpss) DECLARE_REGION(shrm) +DECLARE_REGION(cpucp) +DECLARE_REGION(pdp) DECLARE_REGION(dram_cpucp_dtbs) DECLARE_REGION(dram_cpucp) DECLARE_REGION(dram_modem) @@ -47,7 +53,14 @@ DECLARE_REGION(dram_adsp_rpc_heap) DECLARE_REGION(dram_llcc_lpi) DECLARE_REGION(dram_ta) DECLARE_REGION(dram_pdp) +DECLARE_REGION(dram_pdp_cdb) +DECLARE_REGION(dram_pdp_ns) DECLARE_REGION(dram_pil) +DECLARE_REGION(shared_imem) +DECLARE_REGION(dram_pld_pep) +DECLARE_REGION(dram_pld_gmu) +DECLARE_REGION(dram_pld_pdp) +DECLARE_OPTIONAL_REGION(pcie) /* * DDR_SPACE (2 GB) aka `_dram`: 0x80000000 - 0x100000000 diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index c3f89a24c16..44fb53ff5d7 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -77,9 +77,19 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size) mmu_config_range((void *)_postram_dma_coherent, REGION_SIZE(postram_dma_coherent), UNCACHED_RAM); + if (REGION_SIZE(spel_rvss_iram) != 0) + mmu_config_range((void *)_spel_rvss_iram, REGION_SIZE(spel_rvss_iram), CACHED_RAM); + + if (REGION_SIZE(spel_rvss_dram) != 0) + mmu_config_range((void *)_spel_rvss_dram, REGION_SIZE(spel_rvss_dram), CACHED_RAM); + if (REGION_SIZE(dram_aop_cmd_db) != 0) mmu_config_range((void *)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db), UNCACHED_RAM); if (REGION_SIZE(framebuffer)) mmu_config_range((void *)_framebuffer, REGION_SIZE(framebuffer), UNCACHED_RAM); + + /* Do not call mmu_config_range() after this point. */ + if (_preram_ttb != _postram_ttb) + mmu_relocate_ttb(); } diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index ab8af642d15..754dd34e2d9 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -16,7 +16,10 @@ #define ROOT_PORT_BDF 0x0 #define ATU_CTRL2 PCIE_ATU_UNR_REGION_CTRL2 -#if CONFIG(QMP_PHY_2X2_1X4) +#if CONFIG(QMP_PHY_PCIE5_1X4) +#define LINK_SPEED_DEFAULT LINK_SPEED_GEN_4 +#define PCIE_PHY_SLOT_NUM 6 +#elif CONFIG(QMP_PHY_2X2_1X4) #define LINK_SPEED_DEFAULT LINK_SPEED_GEN_4 #else #define LINK_SPEED_DEFAULT LINK_SPEED_GEN_2 @@ -102,6 +105,186 @@ static void qcom_dw_pcie_configure(uint32_t cap_speed) printk(BIOS_INFO, "PCIe Link speed configured in Gen %d\n", cap_speed); } +#if CONFIG(QMP_PHY_PCIE5_1X4) +/* + * post_phy_pwr_up_init() - Gen5 post-PHY PARF init + * + * Re-assert RC mode and program PARF address windows after PHY BCR reset. + * The PHY BCR reset clears PARF_DEVICE_TYPE on Calypso; writing it here + * guarantees RC mode is set after all resets have completed. + */ +static void post_phy_pwr_up_init(struct qcom_pcie_cntlr_t *pcie) +{ + pcie_cntlr_cfg_t *pcierc = pcie->cntlr_cfg; + + write32(pcierc->parf + PCIE_PARF_DEVICE_TYPE, DEVICE_TYPE_RC); + + /* Program DBI base address window in PARF */ + write32(pcierc->parf + PCIE_PARF_DBI_BASE_ADDR, + lower_32_bits((uintptr_t)pcierc->dbi_base)); + write32(pcierc->parf + PCIE_PARF_DBI_BASE_ADDR_HI, + upper_32_bits((uintptr_t)pcierc->dbi_base)); + + /* Program ATU base address window in PARF */ + write32(pcierc->parf + PCIE_PARF_ATU_BASE_ADDR_LO, + lower_32_bits((uintptr_t)pcierc->atu_base)); + write32(pcierc->parf + PCIE_PARF_ATU_BASE_ADDR_HI, + upper_32_bits((uintptr_t)pcierc->atu_base)); + + /* Disable DMA window (set to invalid address) */ + write32(pcierc->parf + PCIE_PARF_DMA_BASE_ADDR_LO, 0xFFFFFFFF); + write32(pcierc->parf + PCIE_PARF_DMA_BASE_ADDR_HI, 0xFFFFFFFF); + + /* Slave address space size: 0x200_0000_0000 (2 TB) */ + write32(pcierc->parf + PCIE_PARF_SLV_ADDR_SPACE_SIZE, 0x0); + write32(pcierc->parf + PCIE_PARF_SLV_ADDR_SPACE_SIZE_HI, 0x200); + dsb(); + + /* Disable SRIS mode */ + write32(pcierc->parf + PCIE_SRIS_MODE, 0x0); + + /* Detect auxiliary power */ + setbits32(pcierc->parf + PCIE_PARF_SYS_CTRL, AUX_PWR_DET); + + /* Disable AXI master write address halt */ + write32(pcierc->parf + PCIE_PARF_AXI_MSTR_WR_ADDR_HALT, 0x0); + + /* Disable AXI slave error CRS BRESP */ + clrbits32(pcierc->parf + PCIE_PARF_SLAVE_AXI_ERR_REPORT, + AXI_SLAVE_ERR_CRS_BRESP_EN); + + /* L1SS AHB clock max timer: 20 ms at 19.2 MHz */ + clrsetbits32(pcierc->parf + PCIE_PARF_L1SUB_AHB_CLK_MAX_TIMER, + L1SUB_CNT_MAX, L1SS_TIMEOUT_20MS); + + /* Assert app margining ready signals */ + setbits32(pcierc->parf + PCIE_APP_MARGINING_CTRL, + APP_MARGINING_SW_READY | APP_MARGINING_READY); + dsb(); +} + +/* post_phy_pwr_up_dbi_init() - Gen5 post-PHY DBI init */ +static void post_phy_pwr_up_dbi_init(struct qcom_pcie_cntlr_t *pcie) +{ + pcie_cntlr_cfg_t *pcierc = pcie->cntlr_cfg; + + /* Set AUX clock frequency to 19.2 MHz */ + write32(pcierc->dbi_base + PCIE_AUX_CLK_FREQ_OFF, PCIE_AUX_CLK_FREQ_19_2MHZ); + + /* AMBA error response: set CRS field to 0x2 (bits [4:3]) */ + clrsetbits32(pcierc->dbi_base + PCIE_AMBA_ERR_RESP_DEFLT_OFF, + AMBA_ERR_RESP_CRS_MASK, 0x2 << 3); + + /* Clear GEN3_ZRXDC_NONCOMPL */ + clrbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, GEN3_ZRXDC_NONCOMPL); + + /* Unlock DBI read-only registers */ + dw_pcie_dbi_rd_wr(true); + dsb(); + write32(pcierc->dbi_base + PCIE_SPCIE_CAP_OFF_0CH_REG, 0x55555555); + write32(pcierc->dbi_base + PCIE_SPCIE_CAP_OFF_10H_REG, 0x55555555); + write32(pcierc->dbi_base + PCIE_PL16G_CAP_OFF_20H_REG, 0x55555555); + write32(pcierc->dbi_base + PCIE_PL32G_CAP_OFF_20H_REG, 0x55555555); + clrbits32(pcierc->dbi_base + PCIE_SLOT_CAPABILITIES_REG, PCIE_CAP_HOT_PLUG_CAPABLE); + clrsetbits32(pcierc->dbi_base + PCIE_SLOT_CAPABILITIES_REG, + PCIE_CAP_PHY_SLOT_NUM_MASK, + PCIE_CAP_PHY_SLOT_NUM(PCIE_PHY_SLOT_NUM)); + /* Enable CRS Software Visibility in root control/capabilities */ + setbits32(pcierc->dbi_base + PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG, + PCIE_CAP_CRS_SW_VISIBILITY | PCIE_CAP_CRS_SW_VISIBILITY_EN); + + /* Set class code: Base=0x6 (Bridge), Sub=0x4 (PCI-to-PCI) */ + clrsetbits32(pcierc->dbi_base + PCIE_TYPE1_CLASS_CODE_REV_ID_REG, + BASE_CLASS_CODE_MASK | SUBCLASS_CODE_MASK, + BASE_CLASS_CODE_BRIDGE | SUBCLASS_CODE_PCI_BRIDGE); + + /* Disable hot-plug capable */ + clrbits32(pcierc->dbi_base + PCIE_SLOT_CAPABILITIES_REG, + PCIE_CAP_HOT_PLUG_CAPABLE); + + /* + * Remove DPC from capabilities list: set L1SS NEXT_OFFSET to point + * directly to RAS DES (skipping DPC at 0x1EC). + */ + clrsetbits32(pcierc->dbi_base + PCIE_L1SUB_CAP_HEADER_REG, + L1SUB_NEXT_OFFSET_MASK, + (uint32_t)PCIE_RAS_DES_CAP_HDR_OFFSET << 20); + dsb(); + + /* Lock DBI read-only registers */ + dw_pcie_dbi_rd_wr(false); + + /* Flow control timer: enable with 64-cycle update interval */ + clrsetbits32(pcierc->dbi_base + PCIE_QUEUE_STATUS_OFF, + TIMER_MOD_FLOW_CONTROL_EN | TIMER_MOD_FLOW_CONTROL_MASK, + TIMER_MOD_FLOW_CONTROL_EN | TIMER_MOD_FLOW_CONTROL_VAL); + + /* ACK/ASPM: set COMMON_CLK_N_FTS=0x80, ACK_N_FTS=0x80 */ + clrsetbits32(pcierc->dbi_base + PCIE_ACK_F_ASPM_CTRL_OFF, + COMMON_CLK_N_FTS_MASK | ACK_N_FTS_MASK, + COMMON_CLK_N_FTS_VAL | ACK_N_FTS_VAL); + + /* GEN3 EQ settings (RATE_SHADOW_SEL=0) */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, + RATE_SHADOW_SEL_MASK, 0x0); + dsb(); + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, + GEN3_EQ_FMDC_ALL_MASK, GEN3_EQ_FMDC_ALL_VAL); + clrbits32(pcierc->dbi_base + PCIE_GEN3_EQ_CONTROL_OFF, + GEN3_EQ_PHASE23_EXIT_MODE | GEN3_EQ_PSET_REQ_VEC | GEN3_EQ_FB_MODE_MASK); + dsb(); + + /* GEN4 EQ settings (RATE_SHADOW_SEL=1) */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, + RATE_SHADOW_SEL_MASK, RATE_SHADOW_SEL_VAL); + dsb(); + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, + GEN3_EQ_FMDC_ALL_MASK, GEN3_EQ_FMDC_ALL_VAL); + clrbits32(pcierc->dbi_base + PCIE_GEN3_EQ_CONTROL_OFF, + GEN3_EQ_PHASE23_EXIT_MODE | GEN3_EQ_PSET_REQ_VEC | GEN3_EQ_FB_MODE_MASK); + dsb(); + + /* GEN5 EQ settings (RATE_SHADOW_SEL=2) */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, + RATE_SHADOW_SEL_MASK, RATE_SHADOW_SEL_GEN5); + dsb(); + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, + GEN3_EQ_FMDC_ALL_MASK, GEN3_EQ_FMDC_ALL_VAL); + clrbits32(pcierc->dbi_base + PCIE_GEN3_EQ_CONTROL_OFF, + GEN3_EQ_PHASE23_EXIT_MODE | GEN3_EQ_PSET_REQ_VEC | GEN3_EQ_FB_MODE_MASK); + dsb(); + + /* Restore RATE_SHADOW_SEL=0 */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, + RATE_SHADOW_SEL_MASK, 0x0); + + /* Gen4/5 lane margining capabilities */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN4_LANE_MARGINING_1_OFF, + GEN4_MARG1_ALL_MASK, GEN4_MARG1_ALL_VAL); + + /* Gen4/5 lane margining control */ + clrsetbits32(pcierc->dbi_base + PCIE_GEN4_LANE_MARGINING_2_OFF, + GEN4_MARG2_ALL_MASK, GEN4_MARG2_ALL_VAL); + + /* Disable root port BARs using DBI write enable */ + dsb(); + dw_pcie_dbi_rd_wr(true); + dsb(); + write32(pcierc->dbi_base + PCIE_TYPE1_BAR0_REG, 0x0); + write32(pcierc->dbi_base + PCIE_TYPE1_BAR1_REG, 0x0); + dsb(); + dw_pcie_dbi_rd_wr(false); + + /* Enable Bus Master and Memory Space */ + setbits32(pcierc->dbi_base + PCIE_TYPE1_STATUS_COMMAND_REG, + PCIE_BME | PCIE_MSE); + + /* Disable EQ bypass for highest rate (Gen5) */ + setbits32(pcierc->dbi_base + PCIE_PL32G_CONTROL_REG, + EQ_BYPASS_HIGHEST_RATE_DISABLE); +} +#endif + #if CONFIG(QMP_PHY_2X2_1X4) static void post_phy_pwr_up_init(struct qcom_pcie_cntlr_t *pcie) { @@ -110,7 +293,9 @@ static void post_phy_pwr_up_init(struct qcom_pcie_cntlr_t *pcie) write32(pcierc->parf + PCIE_PARF_DEVICE_TYPE, DEVICE_TYPE_RC); dsb(); clrbits32(pcierc->parf + PCIE_PARF_SLAVE_AXI_ERR_REPORT, AXI_SLAVE_ERR_CRS_BRESP_EN); - clrsetbits32(pcierc->dbi_base + PCIE_AMBA_ERR_RESP_DEFLT_OFF, AMBA_ERR_RESP_CRS_MASK, 0x2); + /* AMBA_ERROR_RESPONSE_CRS field is bits [4:3]; value 0x2 must be shifted */ + clrsetbits32(pcierc->dbi_base + PCIE_AMBA_ERR_RESP_DEFLT_OFF, + AMBA_ERR_RESP_CRS_MASK, 0x2 << 3); dsb(); write32(pcierc->parf + PCIE_PARF_AXI_MSTR_WR_ADDR_HALT, 0x0); write32(pcierc->parf + PCIE_SRIS_MODE, 0x0); @@ -161,7 +346,8 @@ static bool wait_link_up(struct qcom_pcie_cntlr_t *pci) if (retry(LINK_WAIT_MAX_RETRIES, is_pcie_link_up(pci), mdelay(PCIE_LINK_UP_MS))) return true; - printk(BIOS_ERR, "PCIe link is not up even after 1sec\n"); + printk(BIOS_ERR, "PCIe link is not up even after 1sec (LTSSM=0x%02x)\n", + read32(pci->cntlr_cfg->parf + PCIE_PARF_LTSSM) & 0x3f); return false; } @@ -178,6 +364,9 @@ static enum cb_err qcom_pcie_dw_link_up(struct qcom_pcie_cntlr_t *pcie) /* enable link training */ setbits32(pcie->cntlr_cfg->parf + PCIE_PARF_LTSSM, LTSSM_EN); + if (CONFIG(SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT)) + return CB_SUCCESS; + /* Check that link was established */ if (wait_link_up(pcie)) { printk(BIOS_INFO, "PCIe link is up\n"); @@ -325,7 +514,41 @@ static void qcom_qmp_phy_configure(void *base, const struct qcom_qmp_phy_init_tb { qcom_qmp_phy_config_lane(base, tbl, num, 0xff); } -#if !CONFIG(QMP_PHY_2X2_1X4) +#if CONFIG(QMP_PHY_PCIE5_1X4) +/* qcom_qmp_phy_power_on - PCIe5 5x4 QMP PHY power-on sequence */ +static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy) +{ + uint64_t lock_us; + + /* Release power-down, enable refclk */ + write32(qphy->pcs_com + QPHY5_PCS_POWER_DOWN_CTRL, SW_PWRDN | REFCLK_DRV_DSBL); + + /* Configure PLL, TXRXZ broadcast, PCS_COM, and PCS_LANEZ */ + qcom_qmp_phy_configure(qphy->qserdes_txrxz, qphy->txrxz_tbl, qphy->txrxz_tbl_num); + qcom_qmp_phy_configure(qphy->qserdes_pll, qphy->serdes_tbl, qphy->serdes_tbl_num); + qcom_qmp_phy_configure(qphy->pcs_com, qphy->pcs_tbl, qphy->pcs_tbl_num); + qcom_qmp_phy_configure(qphy->pcs_lanez, qphy->pcs_lanez_tbl, qphy->pcs_lanez_tbl_num); + + /* Release SW reset and start PCS/serdes */ + write32(qphy->pcs_com + QPHY5_SW_RESET, 0x0); + write32(qphy->pcs_com + QPHY5_START_CONTROL, PCS_START | SERDES_START); + + /* Wait 2ms then poll PCS_STATUS1.PHYSTATUS until clear (PHY ready) */ + udelay(QPHY5_PHY_DELAY_US); + lock_us = wait_us(PCIE_PHY_POLL_US, + !(read32(qphy->pcs_com + QPHY5_PCS_STATUS1) & QPHY_PHYSTATUS)); + if (!lock_us) { + printk(BIOS_ERR, "PCIe5 QMP PHY PLL failed to lock\n"); + return CB_ERR; + } + + printk(BIOS_DEBUG, "PCIe5 QPHY Initialized\n"); + + qcom_dw_pcie_enable_pipe_clock(); + + return CB_SUCCESS; +} +#elif !CONFIG(QMP_PHY_2X2_1X4) static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy) { uint64_t lock_us; @@ -360,7 +583,7 @@ static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy) * Wait for PHY initialization to be done * PCS_STATUS: wait for 1ms for PHY STATUS bit to be set */ - lock_us = wait_us(PCIE_PHY_POLL_US, !(read32(qphy->qmp_phy_base + QPHY_PCS_STATUS) & PHY_STATUS)); + lock_us = wait_us(PCIE_PHY_POLL_US, !(read32(qphy->qmp_phy_base + QPHY_PCS_STATUS) & QPHY_PHYSTATUS)); if (!lock_us) { printk(BIOS_ERR, "PCIe QMP PHY PLL failed to lock in 1ms\n"); return CB_ERR; @@ -503,10 +726,15 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie) } qcom_dw_pcie_setup_rc(pcie); -#if CONFIG(QMP_PHY_2X2_1X4) +#if CONFIG(QMP_PHY_PCIE5_1X4) || CONFIG(QMP_PHY_2X2_1X4) post_phy_pwr_up_init(pcie); post_phy_pwr_up_dbi_init(pcie); #endif + /* T_perst-clk: REFCLK must be stable for at least 100us before + * de-asserting PERST#. A 8ms delay ensures ample margin for + * the clock to stabilize across all operating conditions. + */ + mdelay(8); /* de-assert PCIe reset link to bring EP out of reset */ gpio_set(pcierc->perst, 1); @@ -562,21 +790,68 @@ void qcom_pci_domain_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } -/* PCI domain ops enable callback */ -void qcom_setup_pcie_host(struct device *dev) +static enum cb_err pcie_initiate_link(void) { gcom_pcie_get_config(&qcom_pcie_cfg); - /* Ensure PCIe endpoints are powered-on before initiating PCIe link training */ - gcom_pcie_power_on_ep(); - printk(BIOS_INFO, "Setup PCIe in RC mode\n"); /* Configure PERST gpio */ qcom_pcie_configure_gpios(qcom_pcie_cfg.cntlr_cfg); if (!qcom_dw_pcie_enable(&qcom_pcie_cfg)) - printk(BIOS_NOTICE, "PCIe enumerated succussfully..\n"); + return CB_SUCCESS; + else + return CB_ERR; +} + +static enum cb_err pcie_verify_link_status(void) +{ + gcom_pcie_get_config(&qcom_pcie_cfg); + + if (is_pcie_link_up(&qcom_pcie_cfg)) { + printk(BIOS_INFO, "PCIe Link is already up\n"); + return CB_SUCCESS; + } + + /* Check that link was established */ + if (wait_link_up(&qcom_pcie_cfg)) { + printk(BIOS_INFO, "PCIe link is up\n"); + return CB_SUCCESS; + } + + /* + * Link can be established in Gen 1 as it failed to establish in Gen2. + * So allow some time to do it. + */ + udelay(100); + + return is_pcie_link_up(&qcom_pcie_cfg) ? CB_SUCCESS : CB_ERR; +} + +/* PCI domain ops enable callback */ +void qcom_setup_pcie_host(struct device *dev) +{ + /* STAGE 1: Initiate Hardware (Sync or Async) + * In Romstage (or if Async is disabled), we always start the hardware. + */ + if (ENV_SEPARATE_ROMSTAGE || !CONFIG(SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT)) { + if (pcie_initiate_link() != CB_SUCCESS) { + printk(BIOS_EMERG, "Failed to enable PCIe\n"); + return; + } + + /* Async in Romstage */ + if (ENV_SEPARATE_ROMSTAGE) + return; + } + + /* STAGE 2: Late Check (Async only) + * If we are in Ramstage and Async is enabled, the hardware was already + * kicked off in Romstage. Now we just verify the result. + */ + if (pcie_verify_link_status() == CB_SUCCESS) + printk(BIOS_NOTICE, "PCIe enumerated successfully\n"); else printk(BIOS_EMERG, "Failed to enable PCIe\n"); } diff --git a/src/soc/qualcomm/common/pmic_gpio.c b/src/soc/qualcomm/common/pmic_gpio.c new file mode 100644 index 00000000000..230573657e3 --- /dev/null +++ b/src/soc/qualcomm/common/pmic_gpio.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include + +void pmic_gpio_configure(uint8_t sid, uint8_t gpio_num, + uint8_t source, uint8_t enable, + uint8_t mode) +{ + if (gpio_num < PMIC_GPIO_NUMBER_MIN || gpio_num > PMIC_GPIO_NUMBER_MAX) { + printk(BIOS_ERR, "Invalid PMIC GPIO (%d:%d)", sid, gpio_num); + return; + } + + uint32_t spmi_base = SPMI_ADDR(sid, PMIC_GPIO_BASE(gpio_num)); + if (!sid) + spmi_base += PMIC_PMK_GPIO_OFFSET; + + spmi_write8(spmi_base + PMIC_GPIO_DIG_OUT_SOURCE_CTL, source); + spmi_write8(spmi_base + PMIC_GPIO_EN_CTL, enable); + spmi_write8(spmi_base + PMIC_GPIO_MODE_CTL, mode); +} + +void pmic_gpio_output(uint8_t sid, uint8_t gpio_num, bool high) +{ + uint8_t state = high ? PMIC_GPIO_DIG_OUT_SOURCE_HIGH : PMIC_GPIO_DIG_OUT_SOURCE_LOW; + pmic_gpio_configure(sid, gpio_num, state, PMIC_GPIO_EN_PERPH_EN, PMIC_GPIO_MODE_OUTPUT); +} diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 8b7843540bc..7651a7013cc 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,11 +27,71 @@ /* store QcLib return data until CBMEM_CREATION_HOOK runs */ static struct mem_chip_info *mem_chip_info; +static void dump_mem_chip_info(const struct mem_chip_info *info) +{ + if (!CONFIG(QC_DUMP_MEMCHIP_INFO)) + return; + + printk(BIOS_DEBUG, "MEM Chip Info: version=%d, entries=%d\n", + info->struct_version, info->num_entries); + + for (int i = 0; i < info->num_entries; i++) { + const struct mem_chip_entry *e = &info->entries[i]; + + printk(BIOS_DEBUG, " Entry [%d]:\n", i); + printk(BIOS_DEBUG, " Channel: %d, Rank: %d\n", e->channel, e->rank); + printk(BIOS_DEBUG, " Type: %d, Channel I/O Width: %d\n", + e->type, e->channel_io_width); + printk(BIOS_DEBUG, " Density: %u Mbits, Chip I/O Width: %d\n", + e->density_mbits, e->io_width); + printk(BIOS_DEBUG, " Manufacturer ID: 0x%02x\n", + e->manufacturer_id); + printk(BIOS_DEBUG, " Revision ID: 0x%02x 0x%02x\n", + e->revision_id[0], e->revision_id[1]); + printk(BIOS_DEBUG, " Serial ID: "); + for (int j = 0; j < 8; j++) + printk(BIOS_DEBUG, "%02x", e->serial_id[j]); + + printk(BIOS_DEBUG, "\n"); + } +} + +/* + * Filter out undefined memory chip entries. + * + * This function performs an in-place "collapse" of the entries array by + * removing all entries marked as MEM_CHIP_UNDEFINED. It maintains the + * relative order of valid entries and updates the total count (num_entries) + * once the filtering is complete. + */ +static void process_mem_chip_information(struct mem_chip_info *info) +{ + if (!CONFIG(QC_SANITIZE_MEMCHIP_INFO)) + return; + + int next_valid = 0; + + for (int i = 0; i < info->num_entries; i++) { + /* Check if the entry is valid/non-empty */ + if (info->entries[i].type != MEM_CHIP_UNDEFINED) { + if (next_valid != i) + info->entries[next_valid] = info->entries[i]; + + next_valid++; + } + } + + info->num_entries = next_valid; +} + static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) { struct mem_chip_info *info = (void *)te->blob_address; if (te->size > sizeof(struct mem_chip_info) && te->size == mem_chip_info_size(info->num_entries)) { + process_mem_chip_information(info); + dump_mem_chip_info(info); + /* Save mem_chip_info in global variable ahead of hook running */ mem_chip_info = info; } @@ -58,6 +120,26 @@ static void add_mem_chip_info(int unused) CBMEM_CREATION_HOOK(add_mem_chip_info); +static int qdutt_find_flash(size_t *offset, size_t *size) +{ + const char *name = "RW_QDUTT"; + struct region_device rdev; + + /* Find the region in FMAP */ + if (fmap_locate_area_as_rdev_rw(name, &rdev)) { + printk(BIOS_ERR, "Unable to find FMAP region %s\n", name); + return -1; + } + + *offset = region_device_offset(&rdev); + *size = region_device_sz(&rdev); + + printk(BIOS_INFO, "QDUTT found at offset 0x%zx size 0x%zx\n", + *offset, *size); + + return 0; +} + struct qclib_cb_if_table qclib_cb_if_table; static inline void init_qclib_cb_if_table(struct qclib_cb_if_table *tbl) @@ -84,6 +166,8 @@ const char *qclib_file_default(enum qclib_cbfs_file file) return CONFIG_CBFS_PREFIX "/qclib"; case QCLIB_CBFS_DCB: return CONFIG_CBFS_PREFIX "/dcb"; + case QCLIB_CBFS_DELTA_DCB: + return CONFIG_CBFS_PREFIX "/delta_dcb"; case QCLIB_CBFS_DTB: return CONFIG_CBFS_PREFIX "/dtb"; case QCLIB_CBFS_CPR: @@ -103,8 +187,16 @@ const char *qclib_file_default(enum qclib_cbfs_file file) } } +__weak const char *qclib_override_soc_file(enum qclib_cbfs_file file) +{ + return NULL; +} + const char *qclib_file(enum qclib_cbfs_file file) - __attribute__((weak, alias("qclib_file_default"))); +{ + const char *name = qclib_override_soc_file(file); + return name ?: qclib_file_default(file); +} void qclib_add_if_table_entry(const char *name, void *base, uint32_t size, uint32_t attrs) @@ -186,7 +278,20 @@ static void dump_te_table(void) } } -__weak int qclib_soc_override(struct qclib_cb_if_table *table) { return 0; } +__weak int qclib_soc_override(struct qclib_cb_if_table *table) +{ + ssize_t data_size; + + /* Attempt to load DCB Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_DCB), _dcb, REGION_SIZE(dcb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /dcb failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0); + + return 0; +} __weak bool qclib_check_dload_mode(void) { @@ -198,6 +303,12 @@ static bool qclib_debug_log_level(void) return get_uint_option("qclib_debug_level", 1); } +static bool qc_soc_debug_enabled(void) +{ + return !(CONFIG(QC_SKIP_SOC_DEBUG_FEATURES_IN_RECOVERY) && CONFIG(VBOOT) && + vboot_recovery_mode_enabled()); +} + struct prog qclib; /* This will be re-used by qclib_rerun() */ static void qclib_prepare_and_run(void) @@ -236,6 +347,13 @@ static void qclib_prepare_and_run(void) prog_run(&qclib); + if (qclib_cb_if_table.num_entries > QCLIB_MAX_NUMBER_OF_ENTRIES) { + printk(BIOS_ERR, "QcLib returned invalid num_entries=%u,", + qclib_cb_if_table.num_entries); + printk(BIOS_ERR, " clamping to %d\n", QCLIB_MAX_NUMBER_OF_ENTRIES); + qclib_cb_if_table.num_entries = QCLIB_MAX_NUMBER_OF_ENTRIES; + } + /* * Post-QCLib execution: If the MMU was toggled off, ensure it is * cleanly disabled (flushed/invalidated) before restoring the @@ -267,6 +385,12 @@ void qclib_load_and_run(void) timestamp_add_now(TS_QUALCOMM_QCLIB_INIT_START); + if (CONFIG(QC_QDUTT_ENABLE)) { + size_t qdutt_offset, qdutt_size; + if (qdutt_find_flash(&qdutt_offset, &qdutt_size) < 0) + return; + } + /* zero ddr_information SRAM region, needs new data each boot */ memset(ddr_region, 0, sizeof(struct region)); @@ -301,14 +425,16 @@ void qclib_load_and_run(void) qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, data_size, 0); } - /* Attempt to load DCB Blob */ - data_size = cbfs_load(qclib_file(QCLIB_CBFS_DCB), - _dcb, REGION_SIZE(dcb)); - if (!data_size) { - printk(BIOS_ERR, "[%s] /dcb failed\n", __func__); - goto fail; + if (_delta_dcb) { + /* Attempt to load DELTA_DCB Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_DELTA_DCB), + _delta_dcb, REGION_SIZE(delta_dcb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /delta_dcb failed\n", __func__); + goto fail; + } + qclib_add_if_table_entry(QCLIB_TE_DELTA_DCB_SETTINGS, _delta_dcb, data_size, 0); } - qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0); if (CONFIG(QC_SDI_ENABLE) && (!CONFIG(VBOOT) || !vboot_is_gbb_flag_set(VB2_GBB_FLAG_RUNNING_FAFT))) { @@ -332,7 +458,7 @@ void qclib_load_and_run(void) } /* Load APDP image */ - if (CONFIG(QC_APDP_ENABLE)) { + if (CONFIG(QC_APDP_ENABLE) && qc_soc_debug_enabled()) { struct prog apdp_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/apdp"); @@ -353,6 +479,12 @@ void qclib_load_and_run(void) qclib_add_if_table_entry(QCLIB_TE_APDP_META_SETTINGS, _apdp_ramdump_meta, data_size, 0); } + if (CONFIG(SOC_QUALCOMM_CDT)) { + data_size = cdt_read(_cdt_data, REGION_SIZE(cdt_data)); + if (data_size > 0) + qclib_add_if_table_entry(QCLIB_TE_CDT_SETTINGS, _cdt_data, data_size, 0); + } + /* Attempt to load QCLib elf */ qclib = (struct prog) PROG_INIT(PROG_REFCODE, qclib_file(QCLIB_CBFS_QCLIB)); @@ -387,33 +519,35 @@ void qclib_rerun(void) init_qclib_cb_if_table(&qclib_cb_if_table); - struct prog aop_cfg_fw_prog = - PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop_cfg"); + if(!qclib_check_dload_mode()){ + struct prog aop_cfg_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop_cfg"); - if (!selfload(&aop_cfg_fw_prog)) - die("SOC image: AOP load failed"); + if (!selfload(&aop_cfg_fw_prog)) + die("SOC image: AOP load failed"); - /* Attempt to load aop_meta Blob (reuse the qc_blob_meta region). */ - data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_META), - _qc_blob_meta, REGION_SIZE(qc_blob_meta)); - if (!data_size) { - printk(BIOS_ERR, "[%s] /aop_meta failed\n", __func__); - goto fail; - } + /* Attempt to load aop_meta Blob (reuse the qc_blob_meta region). */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_META), + _qc_blob_meta, REGION_SIZE(qc_blob_meta)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /aop_meta failed\n", __func__); + goto fail; + } - qclib_add_if_table_entry(QCLIB_TE_AOP_META_SETTINGS, _qc_blob_meta, data_size, 0); + qclib_add_if_table_entry(QCLIB_TE_AOP_META_SETTINGS, _qc_blob_meta, data_size, 0); - /* Attempt to load aop_devcfg_meta Blob. */ - data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_DEVCFG_META), - _aop_blob_meta, REGION_SIZE(aop_blob_meta)); - if (!data_size) { - printk(BIOS_ERR, "[%s] /aop_devcfg_meta failed\n", __func__); - goto fail; - } + /* Attempt to load aop_devcfg_meta Blob. */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_DEVCFG_META), + _aop_blob_meta, REGION_SIZE(aop_blob_meta)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /aop_devcfg_meta failed\n", __func__); + goto fail; + } - qclib_add_if_table_entry(QCLIB_TE_AOP_DEVCFG_META_SETTINGS, _aop_blob_meta, data_size, 0); + qclib_add_if_table_entry(QCLIB_TE_AOP_DEVCFG_META_SETTINGS, _aop_blob_meta, data_size, 0); + } - if (CONFIG(QC_RAMDUMP_ENABLE) && qclib_check_dload_mode()) { + if (CONFIG(QC_RAMDUMP_ENABLE) && qc_soc_debug_enabled() && qclib_check_dload_mode()) { struct prog ramdump_prog = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/ramdump"); diff --git a/src/soc/qualcomm/common/qspi.c b/src/soc/qualcomm/common/qspi.c index 088c79d6f3b..528e52c446a 100644 --- a/src/soc/qualcomm/common/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -140,18 +140,25 @@ static void cs_change(enum cs_state state) gpio_set(QSPI_CS, state == CS_DEASSERT); } -static void configure_gpios(void) +/* + * Weak implementation for SoC-specific QSPI initialization. + * SoC layer might wish to increase the drive strength depending upon + * the SPI flash operating frequency. + */ +__weak void qspi_configure_gpios(void) { + uint32_t drive_str = CONFIG_QC_SPI_DRIVE_STRENGTH_MA; + gpio_output(QSPI_CS, 1); gpio_configure(QSPI_DATA_0, GPIO_FUNC_QSPI_DATA_0, - GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, drive_str, GPIO_OUTPUT); gpio_configure(QSPI_DATA_1, GPIO_FUNC_QSPI_DATA_1, - GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, drive_str, GPIO_OUTPUT); gpio_configure(QSPI_CLK, GPIO_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, drive_str, GPIO_OUTPUT); } static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, @@ -247,11 +254,16 @@ static void reg_init(void) write32(&qcom_qspi->rd_fifo_rst, RESET_FIFO); } +void qspi_set_bus_clock(uint32_t hz) +{ + clock_configure_qspi(hz * 4); +} + void quadspi_init(uint32_t hz) { assert(dcache_line_bytes() == CACHE_LINE_SIZE); - clock_configure_qspi(hz * 4); - configure_gpios(); + qspi_set_bus_clock(hz); + qspi_configure_gpios(); reg_init(); } diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index 0b4d17ceb19..cb1591a4f85 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -264,4 +264,6 @@ void qupv3_fw_init(void) qup_common_init(QUP_WRAP1_BASE); if (QUP_WRAP2_BASE) qup_common_init(QUP_WRAP2_BASE); + if (QUP_WRAP3_BASE) + qup_common_init(QUP_WRAP3_BASE); } diff --git a/src/soc/qualcomm/common/qupv3_spi.c b/src/soc/qualcomm/common/qupv3_spi.c index 5e05d573ff2..891c83caec3 100644 --- a/src/soc/qualcomm/common/qupv3_spi.c +++ b/src/soc/qualcomm/common/qupv3_spi.c @@ -34,7 +34,6 @@ /* If fragmentation bit is set then CS will not toggle after each transfer */ #define M_CMD_FRAGMENTATION BIT(2) -#define BITS_PER_BYTE 8 #define BITS_PER_WORD 8 #define TX_WATERMARK 1 diff --git a/src/soc/qualcomm/common/spmi.c b/src/soc/qualcomm/common/spmi.c index 2409cbbf23b..8f896264cab 100644 --- a/src/soc/qualcomm/common/spmi.c +++ b/src/soc/qualcomm/common/spmi.c @@ -2,12 +2,11 @@ #include #include +#include #include #include #include -#define PPID_MASK (0xfffU << 8) - /* These are opcodes specific to this SPMI arbitrator, *not* SPMI commands. */ #define OPC_EXT_WRITEL 0 #define OPC_EXT_READL 1 @@ -19,9 +18,14 @@ #define ERROR_APID_NOT_FOUND (-(int)BIT(8)) #define ERROR_TIMEOUT (-(int)BIT(9)) +/* Add this for your specific SPMI read error (-9) */ +#define ERROR_SPMI_READ_FAILED (-9) #define ARB_COMMAND_TIMEOUT_MS 100 +#define MAX_SPMI_RETRIES 6 +#define SPMI_RETRY_DELAY_MS 50 + // Individual register block per APID struct qcom_spmi_regs { uint32_t cmd; @@ -53,10 +57,11 @@ struct qcom_spmi qcom_spmi = { static struct qcom_spmi_regs *find_apid(uint32_t addr) { size_t i; + uint32_t target_ppid = SPMI_PPID_FROM_ADDR(addr); for (i = 0U; i < qcom_spmi.num_apid; i++) { uint32_t reg = read32(&qcom_spmi.apid_map[i]); - if ((reg != 0U) && ((addr & PPID_MASK) == (reg & PPID_MASK))) + if ((reg != 0U) && (target_ppid == SPMI_PPID_FROM_REG(reg))) return &qcom_spmi.regs_per_apid[i]; } @@ -101,7 +106,7 @@ int spmi_read8(uint32_t addr) int ret = wait_for_done(regs); if (ret != 0) { printk(BIOS_ERR, "ERROR: SPMI_ARB read error [0x%x]: 0x%x\n", addr, ret); - return ret; + return ERROR_SPMI_READ_FAILED; } return read32(®s->rdata0) & 0xff; @@ -141,3 +146,40 @@ int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes) } return 0; } + +/* Helper to handle transient SPMI bus errors with retries */ +int spmi_read8_safe(uint32_t reg) +{ + int val; + int retries = 0; + + do { + val = spmi_read8(reg); + if (val != ERROR_SPMI_READ_FAILED) + return val; + + printk(BIOS_WARNING, "SPMI read error at 0x%x. Retry %d/%d in %dms\n", + reg, retries + 1, MAX_SPMI_RETRIES, SPMI_RETRY_DELAY_MS); + + mdelay(SPMI_RETRY_DELAY_MS); + retries++; + } while (retries < MAX_SPMI_RETRIES); + + return ERROR_SPMI_READ_FAILED; +} + +int spmi_rmw8(uint32_t addr, uint8_t mask, uint8_t value) +{ + int spmi_result; + uint8_t data; + + spmi_result = spmi_read8(addr); + if (spmi_result < 0) + return -1; + data = spmi_result & 0xff; + + data &= ~mask; + data |= value; + spmi_result = spmi_write8(addr, data); + return (spmi_result < 0) ? -1 : 0; +} diff --git a/src/soc/qualcomm/common/tsens.c b/src/soc/qualcomm/common/tsens.c new file mode 100644 index 00000000000..12f5ecdc5b0 --- /dev/null +++ b/src/soc/qualcomm/common/tsens.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#if CONFIG(SOC_QUALCOMM_DEBUG_TSENS) +#define thermal_printk(fmt, ...) printk(BIOS_INFO, fmt, ##__VA_ARGS__) +#else +#define thermal_printk(fmt, ...) do { (void)(fmt); } while (0) +#endif + +static int read_tsens(const struct thermal_zone_map *zone, int *out) +{ + if (!zone) + return -1; + + const struct tsens_controller *ctrl = (const struct tsens_controller *)zone->ctrl; + if (!ctrl || (zone->hw_id >= (int)ctrl->sensor_count)) + return -1; + + uintptr_t status_addr = ctrl->tm_base + TM_SN_STATUS_OFF + (zone->hw_id * 4); + + uint32_t status = read32p(status_addr); + if (!(status & SN_STATUS_VALID)) + return -2; + + /* Sign extend 12-bit temperature and scale to milli C */ + *out = ((int32_t)((status & SN_STATUS_TEMP_MASK) << 20) >> 20) * 100; + return 0; +} + +void qcom_tsens_monitor_all(bool *has_crossed_threshold) +{ + if (!has_crossed_threshold) + return; + + *has_crossed_threshold = false; + + thermal_printk("\n------------------ Thermal Sensor State --------------------\n"); + thermal_printk("%-15s | %-10s | %-8s | %-10s\n", "Zone", "Type", "Temp (C)", "Status"); + thermal_printk("------------------------------------------------------------\n"); + + for (const struct thermal_zone_map *zone = qcom_thermal_zones; zone->label != NULL; zone++) { + int data = 0, status = -1; + const char *type_str = "UNK"; + (void)type_str; + + if (zone->type == TYPE_TSENS) { + type_str = "SoC"; + status = read_tsens(zone, &data); + } + + if (status == 0) { + thermal_printk("%-15s | %-10s | %3d.%1d | ", + zone->label, type_str, data / 1000, (data % 1000) / 100); + + if (data >= zone->threshold) { + *has_crossed_threshold = true; + thermal_printk("EXCEEDED\n"); + if (!CONFIG(SOC_QUALCOMM_DEBUG_TSENS)) + return; + } else { + thermal_printk("OK\n"); + } + } else { + thermal_printk("%-15s | %-10s | [ERR %d] | -\n", zone->label, type_str, status); + } + } +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index e4453922740..f5438722c01 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -37,6 +37,9 @@ /* QUPV3_2 - Dummy Entry */ #define QUP_WRAP2_BASE 0x00000000 +/* QUPV3_3 - Dummy Entry */ +#define QUP_WRAP3_BASE 0x00000000 + /* * USB BASE ADDRESSES */ diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index b9f5d370a30..f84750b32dc 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -15,13 +15,13 @@ static int dcb_fuse_longsys1p8(void) return bit_value; } -const char *qclib_file(enum qclib_cbfs_file file) +const char *qclib_override_soc_file(enum qclib_cbfs_file file) { if ((file == QCLIB_CBFS_DCB) && dcb_fuse_longsys1p8()) { printk(BIOS_INFO, "Using DCB for Longsys 1.8V memory based on fuse setting\n"); return CONFIG_CBFS_PREFIX "/dcb_longsys1p8"; } else { - return qclib_file_default(file); + return NULL; } } diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index fb5bf6f0d5f..74a0bb85fce 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -58,6 +58,9 @@ /* QUPV3_2 - Dummy Entry */ #define QUP_WRAP2_BASE 0x00000000 +/* QUPV3_3 - Dummy Entry */ +#define QUP_WRAP3_BASE 0x00000000 + #define EPSSTOP_EPSS_TOP 0x18598000 #define EPSSFAST_BASE_ADDR 0x18580000 diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 731761c0291..adf2f2985dc 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -4,6 +4,10 @@ #include #include +#if CONFIG(QC_SDI_ENABLE) +#error "sc7280 cannot support QC_SDI for SRAM space reasons" +#endif + SECTIONS { REGION(shrm, 0x09060000, 64K , 4K) @@ -14,8 +18,7 @@ SECTIONS AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 112K) - REGION(qcsdi, 0x1469C000, 39K + 256, 4K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 140K) REGION(modem_id, 0x146A5D00, 4, 4) SSRAM_END(0x146AB000) diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig index b2244358aaa..12fdf124651 100644 --- a/src/soc/qualcomm/x1p42100/Kconfig +++ b/src/soc/qualcomm/x1p42100/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -config SOC_QUALCOMM_BASE +config SOC_QUALCOMM_X1P42100_BASE bool default n select ARCH_BOOTBLOCK_ARMV8_64 @@ -10,6 +10,8 @@ config SOC_QUALCOMM_BASE select ARM64_USE_ARCH_TIMER select ARM64_USE_ARM_TRUSTED_FIRMWARE select CACHE_MRC_SETTINGS + select CBFS_PRELOAD + select COOP_MULTITASKING select COMMONLIB_STORAGE select COMMONLIB_STORAGE_SD select COMPRESS_BOOTBLOCK @@ -17,14 +19,16 @@ config SOC_QUALCOMM_BASE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAS_RECOVERY_MRC_CACHE - select HAVE_CBFS_FILE_OPTION_BACKEND select HAVE_LINEAR_FRAMEBUFFER select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select PCI + select QC_APDP_ENABLE select QC_COMMON_QUPV3_2 + select QC_RAMDUMP_ENABLE + select QC_SANITIZE_MEMCHIP_INFO select QMP_PHY_2X2_1X4 select NO_ECAM_MMCONF_SUPPORT select SDHCI_CONTROLLER @@ -33,7 +37,9 @@ config SOC_QUALCOMM_BASE config SOC_QUALCOMM_X1P42100 bool - select SOC_QUALCOMM_BASE + select ARM64_USE_SECURE_OS + select ARM64_USE_SECURE_OS_PAYLOAD + select SOC_QUALCOMM_X1P42100_BASE default n help Choose this option if the mainboard is built using Qualcomm X1P42100 system-on-a-chip SoC. @@ -42,12 +48,12 @@ config SOC_QUALCOMM_HAMOA bool select ARM64_USE_SECURE_OS select ARM64_USE_SECURE_OS_PAYLOAD - select SOC_QUALCOMM_BASE + select SOC_QUALCOMM_X1P42100_BASE default n help Choose this option if the mainboard is built using Qualcomm Hamoa system-on-a-chip SoC. -if SOC_QUALCOMM_BASE +if SOC_QUALCOMM_X1P42100_BASE config QC_BLOBS_UPSTREAM bool "QC blobs are available in upstream repository" @@ -80,4 +86,26 @@ config UART_BITBANG_TX_DELAY_MS int default 1 +config SPI_FREQ_25MHZ + def_bool n + +config SPI_FREQ_50MHZ + def_bool n + +config SPI_FREQ_75MHZ + def_bool n + +config SPI_FREQ_100MHZ + def_bool n + +config SOC_SPI_FREQ_MHZ + int + default 25 if SPI_FREQ_25MHZ + default 50 if SPI_FREQ_50MHZ + default 75 if SPI_FREQ_75MHZ + default 100 if SPI_FREQ_100MHZ + default 50 + help + Supported SPI Frequency for Hamoa/X1P42100 Platforms + endif diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk index 68eff9a46b5..7947890c2f0 100644 --- a/src/soc/qualcomm/x1p42100/Makefile.mk +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y) +ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100_BASE),y) decompressor-y += decompressor.c decompressor-y += mmu.c @@ -38,6 +38,12 @@ romstage-y += ../common/aop_load_reset.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c romstage-y += ../common/spmi.c romstage-y += pmic.c +romstage-$(CONFIG_SOC_QUALCOMM_CDT) += ../common/cdt.c +ifeq ($(CONFIG_SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT),y) +romstage-$(CONFIG_PCI) += ../common/pcie_common.c +romstage-$(CONFIG_PCI) += pcie.c +endif +romstage-y += platform_info.c ################################################################################ ramstage-y += soc.c @@ -52,11 +58,25 @@ ramstage-$(CONFIG_PCI) += ../common/pcie_common.c ramstage-y += ../common/spmi.c ramstage-$(CONFIG_PCI) += pcie.c ramstage-y += cpucp_load_reset.c +ramstage-y += adsp_load_reset.c ramstage-y += ../common/cmd_db.c ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c ramstage-y += rpmh_rsc_init.c ramstage-y += display/disp.c +ramstage-y += display/edp_ctrl.c +ramstage-y += display/edp_aux.c +ramstage-y += display/edp_phy_4nm.c +ramstage-y += display/edp_link_train.c +ramstage-y += display/mdp_intf_TG.c +ramstage-y += display/vbif.c +ramstage-y += display/sspp.c +ramstage-y += display/edp_panel_tu.c ramstage-y += lpass.c +ramstage-y += ../common/tsens.c +ramstage-y += tsens_map.c +ramstage-y += ../common/pmic_gpio.c +ramstage-y += platform_info.c +ramstage-$(CONFIG_SOC_QUALCOMM_CDT) += ../common/cdt.c ################################################################################ @@ -75,12 +95,6 @@ else BLOB_VARIANT := non_secure endif -ifeq ($(CONFIG_SOC_QUALCOMM_HAMOA),y) -DTB_DCB_BLOB_PATH := hamoa -else -DTB_DCB_BLOB_PATH := x1p42100 -endif - ifeq ($(CONFIG_QC_SDI_ENABLE),y) BL31_MAKEARGS += QTI_SDI_BUILD=1 BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec_dbg.a @@ -88,6 +102,18 @@ else BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec.a endif # CONFIG_QC_SDI_ENABLE +ifeq ($(CONFIG_QC_QDUTT_ENABLE),y) +QCLIB_FILE := $(X1P42100_BLOB)/QDUTT/boot/QcDdi.elf +DCB_FILE_HAMOA := $(X1P42100_BLOB)/QDUTT/boot/hamoa/dcb.bin +DCB_FILE_X1P42100 := $(X1P42100_BLOB)/QDUTT/boot/x1p42100/dcb.bin +SHRM_FILE := $(X1P42100_BLOB)/QDUTT/$(BLOB_VARIANT)/shrm/shrm.elf +else +QCLIB_FILE := $(X1P42100_BLOB)/boot/QcLib.elf +DCB_FILE_HAMOA := $(X1P42100_BLOB)/boot/hamoa/dcb.bin +DCB_FILE_X1P42100 := $(X1P42100_BLOB)/boot/x1p42100/dcb.bin +SHRM_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf +endif # CONFIG_QC_QDUTT_ENABLE + ################################################################################ ifeq ($(CONFIG_QC_SDI_ENABLE),y) QCSDI_FILE := $(X1P42100_BLOB)/boot/QcSdi.elf @@ -114,7 +140,6 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf $(objcbfs)/bootblock.bin ################################################################################ -QCLIB_FILE := $(X1P42100_BLOB)/boot/QcLib.elf QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib $(QCLIB_CBFS)-file := $(QCLIB_FILE) $(QCLIB_CBFS)-type := stage @@ -122,28 +147,47 @@ $(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(QCLIB_CBFS) ################################################################################ -DCB_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin -DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb -$(DCB_CBFS)-file := $(DCB_FILE) -$(DCB_CBFS)-type := raw -$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) -cbfs-files-y += $(DCB_CBFS) +DCB_CBFS_HAMOA := $(CONFIG_CBFS_PREFIX)/dcb_hamoa +$(DCB_CBFS_HAMOA)-file := $(DCB_FILE_HAMOA) +$(DCB_CBFS_HAMOA)-type := raw +$(DCB_CBFS_HAMOA)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS_HAMOA) + +DCB_CBFS_X1P42100 := $(CONFIG_CBFS_PREFIX)/dcb_x1p42100 +$(DCB_CBFS_X1P42100)-file := $(DCB_FILE_X1P42100) +$(DCB_CBFS_X1P42100)-type := raw +$(DCB_CBFS_X1P42100)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS_X1P42100) ################################################################################ -DTB_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/pre-ddr.dtb -DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb -$(DTB_CBFS)-file := $(DTB_FILE) -$(DTB_CBFS)-type := raw -$(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) -cbfs-files-y += $(DTB_CBFS) +DTB_FILE_HAMOA := $(X1P42100_BLOB)/boot/hamoa/pre-ddr.dtb +DTB_CBFS_HAMOA := $(CONFIG_CBFS_PREFIX)/dtb_hamoa +$(DTB_CBFS_HAMOA)-file := $(DTB_FILE_HAMOA) +$(DTB_CBFS_HAMOA)-type := raw +$(DTB_CBFS_HAMOA)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DTB_CBFS_HAMOA) + +DTB_FILE_X1P42100 := $(X1P42100_BLOB)/boot/x1p42100/pre-ddr.dtb +DTB_CBFS_X1P42100 := $(CONFIG_CBFS_PREFIX)/dtb_x1p42100 +$(DTB_CBFS_X1P42100)-file := $(DTB_FILE_X1P42100) +$(DTB_CBFS_X1P42100)-type := raw +$(DTB_CBFS_X1P42100)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DTB_CBFS_X1P42100) ################################################################################ -CPR_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin -CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr -$(CPR_CBFS)-file := $(CPR_FILE) -$(CPR_CBFS)-type := raw -$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -cbfs-files-y += $(CPR_CBFS) +CPR_FILE_HAMOA := $(X1P42100_BLOB)/boot/hamoa/cpr.bin +CPR_CBFS_HAMOA := $(CONFIG_CBFS_PREFIX)/cpr_hamoa +$(CPR_CBFS_HAMOA)-file := $(CPR_FILE_HAMOA) +$(CPR_CBFS_HAMOA)-type := raw +$(CPR_CBFS_HAMOA)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(CPR_CBFS_HAMOA) + +CPR_FILE_X1P42100 := $(X1P42100_BLOB)/boot/x1p42100/cpr.bin +CPR_CBFS_X1P42100 := $(CONFIG_CBFS_PREFIX)/cpr_x1p42100 +$(CPR_CBFS_X1P42100)-file := $(CPR_FILE_X1P42100) +$(CPR_CBFS_X1P42100)-type := raw +$(CPR_CBFS_X1P42100)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(CPR_CBFS_X1P42100) ################################################################################ UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin @@ -215,11 +259,20 @@ cbfs-files-y += $(AOP_DEVCFG_META_CBFS) ################################################################################ CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf -CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp -$(CPUCP_CBFS)-file := $(CPUCP_FILE) -$(CPUCP_CBFS)-type := payload -$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) -cbfs-files-y += $(CPUCP_CBFS) + +CPUCP_CBFS_RW := $(CONFIG_CBFS_PREFIX)/cpucp_rw +regions-for-file-$(CPUCP_CBFS_RW) = FW_MAIN_A,FW_MAIN_B +$(CPUCP_CBFS_RW)-file := $(CPUCP_FILE) +$(CPUCP_CBFS_RW)-type := payload +$(CPUCP_CBFS_RW)-compression := none +cbfs-files-y += $(CPUCP_CBFS_RW) + +CPUCP_CBFS_RO := $(CONFIG_CBFS_PREFIX)/cpucp_ro +regions-for-file-$(CPUCP_CBFS_RO) = COREBOOT +$(CPUCP_CBFS_RO)-file := $(CPUCP_FILE) +$(CPUCP_CBFS_RO)-type := payload +$(CPUCP_CBFS_RO)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_CBFS_RO) ################################################################################ # Rule to create cpucp_meta from cpucp.elf @@ -244,7 +297,23 @@ $(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(CPUCP_DTBS_CBFS) ################################################################################ -SHRM_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf +# ADSP (Audio DSP) Lite Firmware for Off-mode charging +################################################################################ +ADSP_LITE_FILE := $(X1P42100_BLOB)/adsp/mainboard/$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))/adsp.mbn +ADSP_LITE_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_lite +$(ADSP_LITE_CBFS)-file := $(ADSP_LITE_FILE) +$(ADSP_LITE_CBFS)-type := payload +$(ADSP_LITE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(ADSP_LITE_CBFS) + +################################################################################ +ADSP_DTBS_FILE := $(X1P42100_BLOB)/adsp/mainboard/$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))/adsp_dtbs.elf +ADSP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_dtbs +$(ADSP_DTBS_CBFS)-file := $(ADSP_DTBS_FILE) +$(ADSP_DTBS_CBFS)-type := payload +cbfs-files-y += $(ADSP_DTBS_CBFS) + +################################################################################ SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm $(SHRM_CBFS)-file := $(SHRM_FILE) $(SHRM_CBFS)-type := payload @@ -254,7 +323,7 @@ cbfs-files-y += $(SHRM_CBFS) ################################################################################ # Rule to create shrm_meta from shrm.elf # This rule depends on shrm.elf being built and the extractor script existing. -$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py +$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(SHRM_FILE) util/qualcomm/elf_segment_extractor.py @echo "Extracting ELF headers and hash table segment from $< to $@" @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ @@ -308,7 +377,7 @@ cbfs-files-y += $(HYPAC_CFG_FILE_CBFS) ################################################################################ ifeq ($(CONFIG_QC_APDP_ENABLE),y) -APDP_FILE := $(X1P42100_BLOB)/qtee/apdp.mbn +APDP_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/apdp/apdp.mbn APDP_CBFS := $(CONFIG_CBFS_PREFIX)/apdp $(APDP_CBFS)-file := $(APDP_FILE) $(APDP_CBFS)-type := payload @@ -318,7 +387,7 @@ cbfs-files-y += $(APDP_CBFS) ################################################################################ # Rule to create apdp_meta from apdp.mbn # This rule depends on apdp.mbn being built and the extractor script existing. -$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(X1P42100_BLOB)/qtee/apdp.mbn util/qualcomm/elf_segment_extractor.py +$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(X1P42100_BLOB)/$(BLOB_VARIANT)/apdp/apdp.mbn util/qualcomm/elf_segment_extractor.py @echo "Extracting ELF headers and hash table segment from $< to $@" @util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@ @@ -359,4 +428,4 @@ endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y) endif # ifeq ($(CONFIG_USE_QC_BLOBS),y) endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y) -endif # ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y) +endif # ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100_BASE),y) diff --git a/src/soc/qualcomm/x1p42100/adsp_load_reset.c b/src/soc/qualcomm/x1p42100/adsp_load_reset.c new file mode 100644 index 00000000000..e7bfbcd34a4 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/adsp_load_reset.c @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * lpass_program_boot_addr() - Program ADSP boot address override + * @addr: ADSP firmware entry address + * + * Program EVB address/select so Q6 boots from @addr. + */ +static void lpass_program_boot_addr(uintptr_t addr) +{ + write32(&lpass_efuse_q6ss->evb_addr, (addr>>4)); + write32(&lpass_efuse_q6ss->evb_sel, EVB_ENABLE); + dsb(); +} + +/** + * lpass_dtb_bring_up() - Configure ADSP Device Tree Boot parameters + * @dtb_entry_addr: Physical address where Device Tree image is loaded + * @dtb_size: Size of Device Tree image in bytes + * + * Configure the QDSP6SS boot parameter registers with: + * - Device Tree blob location and size + * - Chip identification (family and ID) + * - Chip version information + * - Platform type and version + * + * Boot Parameter Register Layout: + * BOOT_PARAMS[0]: DTB address (lower 32 bits) + * BOOT_PARAMS[1]: DTB address (upper 32 bits) + * BOOT_PARAMS[2]: Chip family (bits 31:16) | Chip ID (bits 15:0) + * BOOT_PARAMS[3]: Chip version - Major (bits 15:8) | Minor (bits 7:0) + * BOOT_PARAMS[4]: Platform type (bits 31:24) | Subtype (bits 23:16) | + * Version major (bits 15:8) | Version minor (bits 7:0) not programmed + * BOOT_PARAMS[5]: DTB size + * + * Return: CB_SUCCESS on success, CB_ERR on failure + */ +static enum cb_err lpass_dtb_bring_up(uintptr_t dtb_entry_addr, size_t dtb_size) +{ + uint32_t chip_family, chip_id; + uint32_t chip_major, chip_minor; + uint32_t boot_params2, boot_params3; + + write32(&lpass_qdsp6ss->boot_params[0], (uint32_t)(dtb_entry_addr & 0xFFFFFFFF)); + write32(&lpass_qdsp6ss->boot_params[1], (uint32_t)(dtb_entry_addr >> 32)); + + /* x1p42100 uses fixed SoC boot args; do not depend on SMEM init ordering. */ + if (platform_get_soc_id() == SOC_ID_HAMOA) { + chip_family = HAMOA_FAMILY & CHIP_FAMILY_MASK; + chip_id = HAMOA_ID_SCP & CHIP_ID_MASK; + } else { + chip_family = X1P42100_FAMILY & CHIP_FAMILY_MASK; + chip_id = X1P42100_ID_SCP & CHIP_ID_MASK; + } + boot_params2 = (chip_family << CHIP_FAMILY_SHIFT) | chip_id; + + chip_major = CHIPINFO_CHIP_VERSION_MAJOR; + chip_minor = CHIPINFO_CHIP_VERSION_MINOR; + boot_params3 = ((chip_major & CHIP_VERSION_MASK) << CHIP_VERSION_MAJOR_SHIFT) | + (chip_minor & CHIP_VERSION_MASK); + + write32(&lpass_qdsp6ss->boot_params[2], boot_params2); + write32(&lpass_qdsp6ss->boot_params[3], boot_params3); + write32(&lpass_qdsp6ss->boot_params[5], (uint32_t)dtb_size); + dsb(); + + return CB_SUCCESS; +} + +/** + * adsp_fw_load() - Main entry point for ADSP firmware loading + * + * Orchestrate the complete ADSP firmware loading sequence: + * 1. Load ADSP Device Tree Blob from CBFS + * 2. Configure QDSP6SS boot parameters with DTB location and platform info + * 3. Load ADSP firmware from CBFS + * 4. Program ADSP boot address via EFUSE EVB registers + */ +void adsp_fw_load(void) +{ + struct prog adsp_dtbs_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_DTBS); + struct prog adsp_fw_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_FIRMWARE); + uintptr_t dtb_entry_addr; + uintptr_t fw_entry_addr; + size_t dtb_size; + + dtb_size = cbfs_get_size(ADSP_CBFS_DTBS); + if (dtb_size == 0) { + printk(BIOS_ERR, "ADSP: Failed to get DTBS size from CBFS\n"); + return; + } + + if (!selfload(&adsp_dtbs_prog)) { + printk(BIOS_ERR, "ADSP: DTBS load failed\n"); + return; + } + + dtb_entry_addr = (uintptr_t)prog_entry(&adsp_dtbs_prog); + + if (lpass_dtb_bring_up(dtb_entry_addr, dtb_size) != CB_SUCCESS) { + printk(BIOS_ERR, "ADSP: DTB bring up failed\n"); + return; + } + + if (!selfload(&adsp_fw_prog)) { + printk(BIOS_ERR, "ADSP: Firmware load failed\n"); + return; + } + + fw_entry_addr = (uintptr_t)prog_entry(&adsp_fw_prog); + + lpass_program_boot_addr(fw_entry_addr); + + printk(BIOS_INFO, "SOC: LPASS/ADSP image loaded successfully\n"); +} diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c index 44641397d2b..b87066967db 100644 --- a/src/soc/qualcomm/x1p42100/bootblock.c +++ b/src/soc/qualcomm/x1p42100/bootblock.c @@ -5,7 +5,7 @@ #include #include -#define SPI_BUS_CLOCK_FREQ (75 * MHz) +#define SPI_BUS_CLOCK_FREQ (CONFIG_SOC_SPI_FREQ_MHZ * MHz) void bootblock_soc_early_init(void) { diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c index eba4987217e..9adbe230d14 100644 --- a/src/soc/qualcomm/x1p42100/clock.c +++ b/src/soc/qualcomm/x1p42100/clock.c @@ -612,7 +612,7 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type) return CB_SUCCESS; } -static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val) +enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val) { int ret; struct alpha_pll_reg_val_config ncc0_pll_cfg = {0}; @@ -697,9 +697,9 @@ void enable_disp_clock_tcsr(void) static void speed_up_boot_cpu(void) { - /* 1363.2 MHz */ - if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz)) - printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n"); + /* 3 GHz */ + if (!pll_init_and_set(apss_ncc0, L_VAL_2995P2MHz)) + printk(BIOS_DEBUG, "NCC Frequency bumped to 3.0(GHz)\n"); } void clock_init(void) diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c index 804c9924254..80e3a392832 100644 --- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c +++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c @@ -1,13 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include +#include #include +#include +#include +#include void cpucp_fw_load_reset(void) { + /* map to cached region to force address to be 4 byte aligned */ + mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), CACHED_RAM); + struct prog cpucp_dtbs_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs"); @@ -16,12 +25,20 @@ void cpucp_fw_load_reset(void) printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n"); - struct prog cpucp_fw_prog = - PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); + const char *cpucp_name = (CONFIG(VBOOT) && !vboot_recovery_mode_enabled()) + ? CONFIG_CBFS_PREFIX "/cpucp_rw" + : CONFIG_CBFS_PREFIX "/cpucp_ro"; + + struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, cpucp_name); if (!selfload(&cpucp_fw_prog)) die("SOC image: CPUCP load failed"); + /* flush cached region */ + dcache_clean_by_mva(_cpucp, REGION_SIZE(cpucp)); + /* remap back to device memory */ + mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), DEV_MEM); + printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n"); write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0); diff --git a/src/soc/qualcomm/x1p42100/display/disp.c b/src/soc/qualcomm/x1p42100/display/disp.c index f4a999ec80c..6a111b3f766 100644 --- a/src/soc/qualcomm/x1p42100/display/disp.c +++ b/src/soc/qualcomm/x1p42100/display/disp.c @@ -57,7 +57,7 @@ void enable_mdss_clk(void) disp_pll_init_and_set(apss_disp_pll0, L_VAL_1725MHz, DISP_PLL0_ALPHA_VAL); disp_pll_init_and_set(apss_disp_pll1, L_VAL_600MHz, DISP_PLL1_ALPHA_VAL); clock_configure(&disp_cc->mdss_ahb_rcg, - disp_cc_mdss_ahb_cfg, CLK_75MHZ, ARRAY_SIZE(disp_cc_mdss_ahb_cfg)); + disp_cc_mdss_ahb_cfg, SRC_XO_HZ, ARRAY_SIZE(disp_cc_mdss_ahb_cfg)); mdss_clock_enable(DISP_CC_MDSS_AHB_CBCR); clock_configure(&disp_cc->mdss_mdp_rcg, disp_cc_mdss_mdp_cfg, CLK_575MHZ, ARRAY_SIZE(disp_cc_mdss_mdp_cfg)); @@ -112,7 +112,7 @@ enum cb_err display_rpmh_init(void) printk(BIOS_INFO, "ARC regulator initialized successfully\n"); - rc = rpmh_regulator_arc_set_level(&arc_reg, RPMH_REGULATOR_LEVEL_MIN_MM0, true, false); + rc = rpmh_regulator_arc_set_level(&arc_reg, RPMH_REGULATOR_LEVEL_NOM_L1, true, false); if (rc) { printk(BIOS_ERR, "Failed to set ARC level\n"); return CB_ERR; diff --git a/src/soc/qualcomm/x1p42100/display/edp_aux.c b/src/soc/qualcomm/x1p42100/display/edp_aux.c new file mode 100644 index 00000000000..26574e3e688 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/edp_aux.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AUX_CMD_FIFO_LEN 144 +#define AUX_CMD_NATIVE_MAX 16 +#define AUX_CMD_I2C_MAX 128 +#define AUX_INTR_I2C_DONE BIT(0) +#define AUX_INTR_WRONG_ADDR BIT(1) +#define AUX_INTR_CONSECUTIVE_TIMEOUT BIT(2) +#define AUX_INTR_CONSECUTIVE_NACK_DEFER BIT(3) +#define AUX_INTR_WRONG_RD_DATA_CNT BIT(4) +#define AUX_INTR_NACK_I2C BIT(5) +#define AUX_INTR_DEFER_I2C BIT(6) +#define AUX_INTR_DPPHY_AUX_ERR BIT(7) +#define EDP_AUX_INTERRUPT \ + (AUX_INTR_I2C_DONE | AUX_INTR_WRONG_ADDR | AUX_INTR_CONSECUTIVE_TIMEOUT | \ + AUX_INTR_CONSECUTIVE_NACK_DEFER | AUX_INTR_WRONG_RD_DATA_CNT | AUX_INTR_DEFER_I2C | \ + AUX_INTR_NACK_I2C | AUX_INTR_DPPHY_AUX_ERR) + +static void edp_wait_for_aux_done(void) +{ + u32 intr_status = 0; + + if (!wait_ms(100, read32(&edp_auxclk->status) & EDP_AUX_INTERRUPT)) { + printk(BIOS_ERR, "AUX SEND not acknowledged\n"); + return; + } + + intr_status = read32(&edp_auxclk->status); + if (!(intr_status & AUX_INTR_I2C_DONE)) { + printk(BIOS_ERR, "AUX command failed, status = %#x\n", intr_status); + return; + } + + write32(&edp_ahbclk->interrupt_status, 0x0); +} + +static int edp_msg_fifo_tx(unsigned int address, u8 request, void *buffer, size_t size) +{ + u32 data[4]; + u32 reg, len; + bool native = (request == DP_AUX_NATIVE_WRITE) || (request == DP_AUX_NATIVE_READ); + bool read = (request == DP_AUX_I2C_READ) || (request == DP_AUX_NATIVE_READ); + u8 *msgdata = buffer; + int i; + + if (read) + len = 4; + else + len = size + 4; + + /* + * cmd fifo only has depth of 144 bytes + */ + if (len > AUX_CMD_FIFO_LEN) + return -1; + + /* Pack cmd and write to HW */ + data[0] = (address >> 16) & 0xf; /* addr[19:16] */ + if (read) + data[0] |= AUX_CMD_READ; /* R/W */ + + data[1] = (address >> 8) & 0xff; /* addr[15:8] */ + data[2] = address & 0xff; /* addr[7:0] */ + data[3] = (size - 1) & 0xff; /* len[7:0] */ + + for (i = 0; i < len; i++) { + reg = (i < 4) ? data[i] : msgdata[i - 4]; + reg = EDP_AUX_DATA_DATA(reg); /* index = 0, write */ + if (i == 0) + reg |= EDP_AUX_DATA_INDEX_WRITE; + write32(&edp_auxclk->aux_data, reg); + } + + /* clear old aux transaction control */ + write32(&edp_auxclk->aux_trans_ctrl, 0); + reg = RX_STOP_ERR | RX_DEC_ERR | RX_SYNC_ERR | RX_ALIGN_ERR | TX_REQ_ERR; + write32(&edp_phy->aux_interrupt_clr, reg); + write32(&edp_phy->aux_interrupt_clr, reg | GLOBE_REQ_CLR); + write32(&edp_phy->aux_interrupt_clr, 0x0); + + reg = 0; /* Transaction number is always 1 */ + if (!native) { /* i2c */ + reg |= EDP_AUX_TRANS_CTRL_I2C | EDP_AUX_TRANS_CTRL_NO_SEND_ADDR; + /* EDP_AUX_TRANS_CTRL_NO_SEND_STOP should be set ONLY if DP_AUX_I2C_MOT is used. */ + if (request & DP_AUX_I2C_MOT) { + reg |= EDP_AUX_TRANS_CTRL_NO_SEND_STOP; + } + } + + reg |= EDP_AUX_TRANS_CTRL_GO; + write32(&edp_auxclk->aux_trans_ctrl, reg); + edp_wait_for_aux_done(); + + return 0; +} + +static int edp_msg_fifo_rx(void *buffer, size_t size) +{ + u32 data; + u8 *dp; + int i; + u32 len = size; + + clrbits32(&edp_auxclk->aux_trans_ctrl, EDP_AUX_TRANS_CTRL_GO); + + write32(&edp_auxclk->aux_data, + EDP_AUX_DATA_INDEX_WRITE | EDP_AUX_DATA_READ); /* index = 0 */ + + dp = buffer; + + /* discard first byte */ + data = read32(&edp_auxclk->aux_data); + /* printk(BIOS_DEBUG, "AUX RX dummy = 0x%08x\n", data); + + if (len == 1) { + + dp[0] = (u8)((data >> 8) & 0xff); + return 0; + } + */ + + for (i = 0; i < len; i++) { + data = read32(&edp_auxclk->aux_data); + // printk(BIOS_DEBUG, "AUX RX word[%d] = 0x%08x\n", i, data); + dp[i] = (u8)((data >> 8) & 0xff); + } + + return 0; +} + +ssize_t edp_aux_transfer(unsigned int address, u8 request, void *buffer, size_t size) +{ + ssize_t ret; + bool native = (request == DP_AUX_NATIVE_WRITE) || (request == DP_AUX_NATIVE_READ); + bool read = (request == DP_AUX_I2C_READ) || (request == DP_AUX_NATIVE_READ); + + /* Ignore address only message */ + if ((size == 0) || (buffer == NULL)) { + printk(BIOS_ERR, "%s: invalid size or buffer\n", __func__); + return size; + } + + /* msg sanity check */ + if ((native && (size > AUX_CMD_NATIVE_MAX)) || (size > AUX_CMD_I2C_MAX)) { + printk(BIOS_ERR, "%s: invalid msg: size(%zu), request(%x)\n", __func__, size, + request); + return -1; + } + + ret = edp_msg_fifo_tx(address, request, buffer, size); + if (ret < 0) { + printk(BIOS_ERR, "edp aux transfer tx failed\n"); + return ret; + } + + if (read) { + ret = edp_msg_fifo_rx(buffer, size); + if (ret < 0) { + printk(BIOS_ERR, "edp aux transfer rx failed\n"); + return ret; + } + } + + /* Return requested size for success or retry */ + ret = size; + + printk(BIOS_INFO, "DP AUX %s done: status=%d type=%u addr=0x%06x %s=%zu %s=%zd\n", + read ? "READ" : "WRITE", 0, /* status: 0 = success */ + request, address, read ? "req_size" : "size", size, + read ? "bytes_read" : "bytes_written", ret); + + /* Dump data bytes */ + if (buffer && size) { + size_t i; + printk(BIOS_INFO, ":"); + for (i = 0; i < size; i++) + printk(BIOS_INFO, "%02x%s", ((u8 *)buffer)[i], + (i == size - 1) ? "]\n" : ":"); + } + + return ret; +} + +int edp_read_edid(struct edid *out) +{ + int err; + u8 edid[EDID_LENGTH * 2]; + int edid_size = EDID_LENGTH; + + uint8_t reg_addr = 0; + err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_WRITE, ®_addr, 1); + if (err > 0) + err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ, edid, EDID_LENGTH); + + if (err < EDID_LENGTH) { + printk(BIOS_ERR, "Failed to read EDID. :%d\n", err); + return err; + } + + if (edid[EDID_EXTENSION_FLAG]) { + printk(BIOS_INFO, " read EDID ext block.\n"); + edid_size += EDID_LENGTH; + reg_addr = EDID_LENGTH; + err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_WRITE, ®_addr, 1); + if (err > 0) + err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ, + &edid[EDID_LENGTH], EDID_LENGTH); + + if (err < EDID_LENGTH) { + printk(BIOS_ERR, "Failed to read EDID ext block.\n"); + return err; + } + } + + if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { + printk(BIOS_ERR, "Failed to decode EDID.\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +void edp_aux_ctrl(int enable) +{ + u32 data; + data = read32(&edp_auxclk->aux_ctrl); + + if (!enable) { + data &= ~EDP_AUX_CTRL_ENABLE; + write32(&edp_auxclk->aux_ctrl, data); + return; + } + + data |= EDP_AUX_CTRL_RESET; + write32(&edp_auxclk->aux_ctrl, data); + + data &= ~EDP_AUX_CTRL_RESET; + write32(&edp_auxclk->aux_ctrl, data); + + write32(&edp_auxclk->timeout_count, 0xffff); + write32(&edp_auxclk->aux_limits, 0xffff); + + data |= EDP_AUX_CTRL_ENABLE; + write32(&edp_auxclk->aux_ctrl, data); +} diff --git a/src/soc/qualcomm/x1p42100/display/edp_ctrl.c b/src/soc/qualcomm/x1p42100/display/edp_ctrl.c new file mode 100644 index 00000000000..b7e44bf3dff --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/edp_ctrl.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static void edp_ctrl_phy_enable(int enable) +{ + write32(&edp_ahbclk->sw_reset, 1); + write32(&edp_ahbclk->sw_reset, 0); + + write32(&edp_ahbclk->phy_ctrl, 0x4); + write32(&edp_ahbclk->phy_ctrl, 0x0); + + uint32_t active_status = read32(&edp_ahbclk->clk_active); + + printk(BIOS_INFO, "edp_ahbclk->phy_ctrl active = %d\n", active_status); + + early_phy_enable(); + + /* early link-side initialization */ + write32(&edp_auxclk->hpd_int_ack, EDP_HPD_INT_ACK_CLEAR_ALL); + write32(&edp_auxclk->aux_ctrl, EDP_AUX_CTRL_ENABLE_BASIC); + write32(&edp_auxclk->hpd_reftimer, EDP_HPD_REFTIMER_ENABLE_0013); + write32(&edp_auxclk->hpd_int_ack, EDP_HPD_INT_ACK_CLEAR_ALL); + write32(&edp_auxclk->hpd_ctrl, EDP_HPD_CTRL_ENABLE); + write32(&mdp_periph_top1->dp_hpd_select, MDP_DP_HPD_SELECT_HPDDPT3); + write32(&mdp_periph_top1->hdmi_dp_core_select, MDP_HDMI_DP_CORE_SELECT_DP); + write32(&edp_auxclk->aux_ctrl, EDP_AUX_CTRL_ENABLE_RST); + write32(&edp_auxclk->aux_ctrl, EDP_AUX_CTRL_ENABLE_BASIC); + write32(&edp_auxclk->timeout_count, EDP_AUX_TIMEOUT_COUNT_FFFF); + write32(&edp_auxclk->aux_limits, EDP_AUX_LIMITS_FFFF); + write32((uint32_t *)AHB2EDPPHY_AHB2PHY_AHB2PHY_TOP_CFG, READ_WAIT2_WR_WAIT1); +} + +static void edp_ctrl_irq_enable(int enable) +{ + if (enable) { + write32(&edp_ahbclk->interrupt_status, EDP_INTERRUPT_STATUS1_MASK); + write32(&edp_ahbclk->interrupt_status2, EDP_INTERRUPT_STATUS2_MASK); + } else { + write32(&edp_ahbclk->interrupt_status, EDP_INTERRUPT_STATUS1_ACK); + write32(&edp_ahbclk->interrupt_status2, EDP_INTERRUPT_STATUS2_ACK); + } +} + +enum cb_err edp_ctrl_init(struct edid *edid) +{ + uint8_t value; + + uint32_t ver = edp_ahbclk->hw_version; + + printk(BIOS_DEBUG, " eDP HW_VERSION = 0x%08x\n", ver); + + uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; + int ret; + + mdss_clock_enable(DISP_CC_MDSS_DPTX3_AUX_CBCR); + + edp_ctrl_phy_enable(1); + + edp_ctrl_irq_enable(1); + + ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_READ, &value, 1); + printk(BIOS_DEBUG, "DPCD power read address=%x\n", DP_SET_POWER); + if (ret < 0) { + printk(BIOS_ERR, "edp native read failure\n"); + return -1; + } + + value &= ~DP_SET_POWER_MASK; + value |= DP_SET_POWER_D0; + + ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_WRITE, &value, 1); + printk(BIOS_DEBUG, "DPCD power Set address=%x : %x\n", DP_SET_POWER, value); + if (ret < 0) { + printk(BIOS_ERR, "edp native read failure\n"); + return -1; + } + + udelay(1000); + + ret = edp_aux_transfer(DP_DPCD_REV, DP_AUX_NATIVE_READ, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) { + printk(BIOS_ERR, " DPCD[0x00000] read failed : ret=%d\n", ret); + } else { + int dump_len = ret; + if (dump_len > 16) + dump_len = 16; + + printk(BIOS_DEBUG, "[DPCD] 0000..000F: "); + + for (int i = 0; i <= dump_len; i++) { + printk(BIOS_INFO, "%02x ", (uint32_t)dpcd[i]); + } + } + + edp_read_edid(edid); + + u8 v[5]; + ret = edp_aux_transfer(0xF0000, DP_AUX_NATIVE_READ, v, 5); + u8 bright[3]; + ret = edp_aux_transfer(0x724, DP_AUX_NATIVE_READ, bright, 3); + u8 br2[1]; + br2[0] = bright[2]; + edp_aux_transfer(0x724, DP_AUX_NATIVE_WRITE, br2, 1); + + printk(BIOS_INFO, "LTTPR probe: addr=0x%05x ret=%d val=0x%02x", 0xF0000, ret, v[0]); + printk(BIOS_INFO, ":%02x", v[1]); + printk(BIOS_INFO, ":%02x", v[2]); + printk(BIOS_INFO, ":%02x", v[3]); + printk(BIOS_INFO, ":%02x", v[4]); + + struct edp_ctrl ctrl; + edp_ctrl_on(&ctrl, edid, dpcd); + + return CB_SUCCESS; +} + +void edp_backlight_aux(void) +{ + /* eDP DPCD AUX transactions: enable backlight control and set brightness */ + uint8_t rx_buf[4], tx_buf[4]; + int ret; + + ret = edp_aux_transfer(0x721, DP_AUX_NATIVE_READ, rx_buf, 1); + if (ret < 0) + printk(BIOS_DEBUG, " Error\n"); + + tx_buf[0] = 0x02; /* Set DPCD 0x721 bits (per original logic) */ + ret = edp_aux_transfer(0x721, DP_AUX_NATIVE_WRITE, tx_buf, 1); + if (ret < 0) + printk(BIOS_DEBUG, " Error\n"); + + ret = edp_aux_transfer(0x720, DP_AUX_NATIVE_READ, rx_buf, 1); + if (ret < 0) + printk(BIOS_DEBUG, " Error\n"); + + tx_buf[0] = 0x01; /* Enable backlight via DPCD 0x720 */ + ret = edp_aux_transfer(0x720, DP_AUX_NATIVE_WRITE, tx_buf, 1); + if (ret < 0) + printk(BIOS_DEBUG, " Error\n"); + + /* Brightness: MSB @ 0x722, LSB @ 0x723 (0x0400) */ + tx_buf[0] = 0x04; + tx_buf[1] = 0x00; + ret = edp_aux_transfer(0x722, DP_AUX_NATIVE_WRITE, tx_buf, 2); + if (ret < 0) + printk(BIOS_DEBUG, " Error\n"); + + mdelay(50); +} diff --git a/src/soc/qualcomm/x1p42100/display/edp_link_train.c b/src/soc/qualcomm/x1p42100/display/edp_link_train.c new file mode 100644 index 00000000000..0d1ef539201 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/edp_link_train.c @@ -0,0 +1,957 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BPC_TO_ENUM(bpc) ((enum edp_color_depth)((bpc / 2) - 3)) + +static uint8_t dp_get_lane_status(const uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) +{ + int i = DP_LANE0_1_STATUS + (lane >> 1); + int s = (lane & 1) * 4; + uint8_t l = link_status[i - DP_LANE0_1_STATUS]; + return (l >> s) & 0xf; +} + +static uint8_t edp_get_adjust_request_voltage(const uint8_t link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : + DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); + uint8_t l = link_status[i - DP_LANE0_1_STATUS]; + + return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; +} + +static uint8_t +edp_get_adjust_request_pre_emphasis(const uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : + DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); + uint8_t l = link_status[i - DP_LANE0_1_STATUS]; + + return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; +} + +static void edp_link_train_clock_recovery_delay(const uint8_t dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + printk(BIOS_ERR, "AUX interval %d, out of range (max 4)\n", rd_interval); + + udelay(100); +} + +static bool edp_clock_recovery_ok(const uint8_t link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + for (int lane = 0; lane < lane_count; lane++) { + uint8_t lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) { + printk(BIOS_ERR, "clock recovery ok failed : %x\n", lane_status); + return false; + } else { + printk(BIOS_DEBUG, "Lane status if not failed 0x%08x\n", lane_status); + } + } + return true; +} + +static void edp_link_train_channel_eq_delay(const uint8_t dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + printk(BIOS_INFO, "AUX interval %d, out of range (max 4)\n", rd_interval); + + /* + * The DPCD stores the AUX read interval in units of 4 ms. + * If the TRAINING_AUX_RD_INTERVAL field is 0, the channel equalization + * should use 400 us AUX read intervals. + */ + printk(BIOS_INFO, "AUX interval %d\n", rd_interval); + if (rd_interval == 0) + udelay(400); + else { + mdelay(rd_interval * 4); + mdelay(rd_interval); + } +} + +static bool edp_channel_eq_ok(const uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) +{ + uint8_t lane_align = link_status[DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS]; + if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) + return false; + + for (int lane = 0; lane < lane_count; lane++) { + uint8_t lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) + return false; + } + return true; +} + +static void edp_ctrl_irq_enable(int enable) +{ + if (enable) { + write32(&edp_ahbclk->interrupt_status, EDP_INTERRUPT_STATUS1_MASK); + write32(&edp_ahbclk->interrupt_status2, EDP_INTERRUPT_STATUS2_MASK); + } else { + write32(&edp_ahbclk->interrupt_status, EDP_INTERRUPT_STATUS1_ACK); + write32(&edp_ahbclk->interrupt_status2, EDP_INTERRUPT_STATUS2_ACK); + } +} + +static void edp_state_ctrl(uint32_t state) +{ + write32(&edp_lclk->state_ctrl, state); + printk(BIOS_DEBUG, "State = 0x%x\n", state); +} + +static int edp_lane_set_write(uint8_t voltage_level, uint8_t pre_emphasis_level) +{ + uint8_t buf[4]; + + if (voltage_level >= DPCD_LINK_VOLTAGE_MAX) + voltage_level |= 0x04; + + if (pre_emphasis_level >= DPCD_LINK_PRE_EMPHASIS_MAX) + pre_emphasis_level |= 0x20; + + for (int i = 0; i < 4; i++) + buf[i] = voltage_level | (pre_emphasis_level << 3); + + printk(BIOS_DEBUG, "VP:perlane =0x%x:0x%x:0x%x:0x%x\n", buf[0], buf[1], buf[2], buf[3]); + if (edp_aux_transfer(DP_TRAINING_LANE0_SET, DP_AUX_NATIVE_WRITE, buf, 4) < 4) { + printk(BIOS_ERR, "%s: Set sw/pe to panel failed\n", __func__); + return -1; + } + return 0; +} + +static int edp_train_pattern_set_write(uint8_t pattern) +{ + uint8_t p = pattern; + + printk(BIOS_INFO, "pattern=%x\n", p); + if (edp_aux_transfer(DP_TRAINING_PATTERN_SET, DP_AUX_NATIVE_WRITE, &p, 1) < 1) { + printk(BIOS_ERR, "%s: Set training pattern to panel failed\n", __func__); + return -1; + } + return 0; +} + +static void edp_sink_train_set_adjust(struct edp_ctrl *ctrl, const uint8_t *link_status) +{ + uint8_t max = 0; + + /* use the max level across lanes */ + for (int i = 0; i < ctrl->lane_cnt; i++) { + uint8_t data = edp_get_adjust_request_voltage(link_status, i); + if (max < data) + max = data; + } + ctrl->v_level = max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; + + /* use the max level across lanes */ + max = 0; + for (int i = 0; i < ctrl->lane_cnt; i++) { + uint8_t data = edp_get_adjust_request_pre_emphasis(link_status, i); + + if (max < data) + max = data; + } + ctrl->p_level = max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; + + printk(BIOS_INFO, "Requested_max_all lanes v_level=%d, p_level=%d\n", ctrl->v_level, + ctrl->p_level); +} + +static void edp_host_train_set(uint32_t train) +{ + int cnt = 10; + uint32_t shift = train - 1; + + printk(BIOS_INFO, "train=%d\n", train); + + edp_state_ctrl(SW_LINK_TRAINING_PATTERN1 << shift); + while (--cnt) { + uint32_t data = read32(&edp_lclk->mainlink_ready); + if (data & (EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY << shift)) + break; + } + if (cnt == 0) + printk(BIOS_INFO, "%s: set link_train failed\n", __func__); +} + +static int edp_voltage_pre_emphasis_set(struct edp_ctrl *ctrl) +{ + printk(BIOS_INFO, "v=%d p=%d\n", ctrl->v_level, ctrl->p_level); + edp_phy_config(ctrl->v_level, ctrl->p_level, ctrl->link_rate_khz); + return edp_lane_set_write(ctrl->v_level, ctrl->p_level); +} + +static int edp_start_link_train_1(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + uint8_t link_status[DP_LINK_STATUS_SIZE]; + uint8_t old_v_level; + int tries; + int ret, rlen; + + edp_state_ctrl(0); + edp_host_train_set(DP_TRAINING_PATTERN_1); + + ret = edp_train_pattern_set_write(DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE); + if (ret) + return ret; + + ret = edp_voltage_pre_emphasis_set(ctrl); + if (ret) + return ret; + + tries = 0; + old_v_level = ctrl->v_level; + while (1) { + edp_link_train_clock_recovery_delay(dpcd); + + rlen = edp_aux_transfer(DP_LANE0_1_STATUS, DP_AUX_NATIVE_READ, &link_status, + DP_LINK_STATUS_SIZE); + if (rlen < DP_LINK_STATUS_SIZE) { + printk(BIOS_ERR, "%s: read link status failed\n", __func__); + return -1; + } + + if (edp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { + ret = 0; + break; + } + + if (ctrl->v_level == DPCD_LINK_VOLTAGE_MAX) { + ret = -1; + break; + } + + if (old_v_level != ctrl->v_level) { + tries++; + if (tries >= 5) { + ret = -1; + break; + } + } else { + tries = 0; + old_v_level = ctrl->v_level; + } + + edp_sink_train_set_adjust(ctrl, link_status); + ret = edp_voltage_pre_emphasis_set(ctrl); + if (ret) + return ret; + } + return ret; +} + +static int edp_start_link_train_2(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + uint8_t link_status[DP_LINK_STATUS_SIZE]; + int tries = 0; + int ret, rlen; + + edp_host_train_set(DP_TRAINING_PATTERN_3); + + ret = edp_train_pattern_set_write(DP_TRAINING_PATTERN_3 | DP_LINK_SCRAMBLING_DISABLE); + if (ret) + return ret; + + edp_link_train_channel_eq_delay(dpcd); + + ret = edp_voltage_pre_emphasis_set(ctrl); + if (ret) + return ret; + + while (1) { + edp_link_train_channel_eq_delay(dpcd); + + rlen = edp_aux_transfer(DP_LANE0_1_STATUS, DP_AUX_NATIVE_READ, &link_status, + DP_LINK_STATUS_SIZE); + printk(BIOS_DEBUG, "Lane status =0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n\n", + link_status[0], link_status[1], link_status[2], link_status[3], + link_status[4], link_status[5]); + + if (rlen < DP_LINK_STATUS_SIZE) { + printk(BIOS_ERR, "%s: read link status failed\n", __func__); + return -1; + } + + if (edp_channel_eq_ok(link_status, ctrl->lane_cnt)) { + ret = 0; + break; + } + + tries++; + if (tries > 10) { + ret = -1; + break; + } + + edp_sink_train_set_adjust(ctrl, link_status); + ret = edp_voltage_pre_emphasis_set(ctrl); + if (ret) + return ret; + } + return ret; +} + +static int edp_link_rate_down_shift(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + int ret = 0; + int link_rate = ctrl->link_rate_khz; + + switch (link_rate) { + case 810000: + link_rate = 540000; + break; + case 540000: + link_rate = 270000; + break; + case 270000: + link_rate = 162000; + break; + case 162000: + default: + ret = -1; + break; + } + + if (!ret) { + ctrl->link_rate_khz = link_rate; + ctrl->link_rate = link_rate / DP_LINK_RATE_UNIT_KHZ; + printk(BIOS_INFO, "new rate=%d\n", ctrl->link_rate_khz); + } + return ret; +} + +static bool edp_clock_recovery_reduced_lanes(const uint8_t link_status[DP_LINK_STATUS_SIZE], + uint32_t lane_cnt) +{ + if (lane_cnt <= 1) + return false; + + int reduced_lanes = lane_cnt >> 1; + return edp_clock_recovery_ok(link_status, reduced_lanes); +} + +static int edp_link_lane_down_shift(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + if (ctrl->lane_cnt <= 1) + return -1; + + ctrl->lane_cnt = ctrl->lane_cnt >> 1; + ctrl->link_rate_khz = dpcd[DP_MAX_LINK_RATE] * DP_LINK_RATE_UNIT_KHZ; + ctrl->link_rate = dpcd[DP_MAX_LINK_RATE]; + ctrl->p_level = 0; + ctrl->v_level = 0; + return 0; +} + +static int edp_clear_training_pattern(uint8_t *dpcd) +{ + int ret = edp_train_pattern_set_write(0); + edp_link_train_channel_eq_delay(dpcd); + return ret; +} + +static int edp_do_link_train(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + uint8_t values[2], edp_config = 0; + int ret; + int rlen; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + + /* + * Set the current link rate and lane cnt to panel. They may have been + * adjusted and the values are different from them in DPCD CAP + */ + values[0] = ctrl->link_rate; + values[1] = ctrl->lane_cnt; + + if (dpcd[DP_DPCD_REV] >= 0x11 && (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) + values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + + if (ctrl->use_rate_select) { + ret = edp_aux_transfer(DP_LANE_COUNT_SET, DP_AUX_NATIVE_WRITE, &values[1], 1); + if (ret < 1) { + printk(BIOS_ERR, "failed to write lane count, ret:%d\n", ret); + return EDP_TRAIN_FAIL; + } + + /* write link rate index (DPCD 0x0115) */ + ret = edp_aux_transfer(DP_LINK_RATE_SET, DP_AUX_NATIVE_WRITE, + &ctrl->rate_select_idx, 1); + if (ret < 1) { + printk(BIOS_ERR, "failed to write link rate, ret:%d\n", ret); + return EDP_TRAIN_FAIL; + } + } else { + if (edp_aux_transfer(DP_LINK_BW_SET, DP_AUX_NATIVE_WRITE, &values[0], 1) < 0) + return EDP_TRAIN_FAIL; + + printk(BIOS_DEBUG, "Setting %8x : %x\n", DP_LINK_BW_SET, values[0]); + + edp_aux_transfer(DP_LANE_COUNT_SET, DP_AUX_NATIVE_WRITE, &values[1], 1); + ctrl->v_level = 0; /* start from default level */ + ctrl->p_level = 0; + + printk(BIOS_DEBUG, "Setting %8x : %x\n", DP_LANE_COUNT_SET, values[1]); + } + + edp_config = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; + edp_aux_transfer(DP_EDP_CONFIGURATION_SET, DP_AUX_NATIVE_WRITE, &edp_config, 1); + printk(BIOS_DEBUG, "Setting %8x : %x\n", DP_EDP_CONFIGURATION_SET, edp_config); + + write32(&edp_p0clk->intf_config, 0x10); /* Databus Widen, 2 Pixel / Pixels per clock */ + + values[0] = 0x10; + if (dpcd[DP_MAX_DOWNSPREAD] & 1) + values[0] = DP_SPREAD_AMP_0_5; + + values[1] = 1; + + ret = edp_start_link_train_1(ctrl, dpcd); + if (ret < 0) { + rlen = edp_aux_transfer(DP_LANE0_1_STATUS, DP_AUX_NATIVE_READ, &link_status, + DP_LINK_STATUS_SIZE); + if (rlen < DP_LINK_STATUS_SIZE) { + printk(BIOS_ERR, "%s: read link status failed\n", __func__); + return -1; + } + + ret = edp_link_rate_down_shift(ctrl, dpcd); + if (!ret) { + printk(BIOS_ERR, "link reconfig\n"); + ret = EDP_TRAIN_RECONFIG; + } else if (ret < 0) { + if (edp_clock_recovery_reduced_lanes(link_status, ctrl->lane_cnt) == + 0) { + if (edp_link_lane_down_shift(ctrl, dpcd) < 0) { + printk(BIOS_ERR, "%s: Training 1 failed\n", __func__); + ret = EDP_TRAIN_FAIL; + } else { + printk(BIOS_ERR, "link reconfig\n"); + ret = EDP_TRAIN_RECONFIG; + } + } else { + printk(BIOS_ERR, "%s: Training 1 failed\n", __func__); + ret = EDP_TRAIN_FAIL; + } + } + edp_clear_training_pattern(dpcd); + return ret; + } + + printk(BIOS_INFO, "Training 1 completed successfully\n"); + edp_state_ctrl(0); + + ret = edp_start_link_train_2(ctrl, dpcd); + if (ret < 0) { + rlen = edp_aux_transfer(DP_LANE0_1_STATUS, DP_AUX_NATIVE_READ, &link_status, + DP_LINK_STATUS_SIZE); + if (rlen < DP_LINK_STATUS_SIZE) { + printk(BIOS_ERR, "%s: read link status failed\n", __func__); + return -1; + } + + if (edp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { + if (edp_link_rate_down_shift(ctrl, dpcd) == 0) { + printk(BIOS_ERR, "link reconfig\n"); + ret = EDP_TRAIN_RECONFIG; + } else { + printk(BIOS_ERR, "%s: Training 2 failed\n", __func__); + ret = EDP_TRAIN_FAIL; + } + } else { + if (edp_link_lane_down_shift(ctrl, dpcd) < 0) { + printk(BIOS_ERR, "%s: Training 1 failed\n", __func__); + ret = EDP_TRAIN_FAIL; + } else { + printk(BIOS_ERR, "link reconfig\n"); + ret = EDP_TRAIN_RECONFIG; + } + } + edp_clear_training_pattern(dpcd); + return ret; + } + + printk(BIOS_INFO, "Training 2 completed successfully\n"); + edp_config = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; + edp_aux_transfer(DP_EDP_CONFIGURATION_SET, DP_AUX_NATIVE_WRITE, &edp_config, 1); + return ret; +} + +static int edp_ctrl_pixel_clock_dividers(struct edp_ctrl *ctrl, uint32_t *pixel_m, + uint32_t *pixel_n) +{ + uint32_t pixel_div = 0, dispcc_input_rate; + unsigned long den, num; + uint8_t rate = (ctrl->link_rate); + + uint32_t stream_rate_khz = + (ctrl->pixel_rate) / + 2; /* Databus Widen, 2 Pixel / Pixels per clock settings in edp_do_link_train() */ + + if (rate == DP_LINK_BW_8_1) + pixel_div = 6; + else if (rate == DP_LINK_BW_1_62 || rate == DP_LINK_BW_2_7) + pixel_div = 2; + else if (rate == DP_LINK_BW_5_4) + pixel_div = 4; + else { + printk(BIOS_ERR, "Invalid pixel mux divider\n"); + return -1; + } + + dispcc_input_rate = (ctrl->link_rate_khz * 10) / pixel_div; + + rational_best_approximation(dispcc_input_rate, stream_rate_khz, + (uint64_t)(1 << 16) - 1, (uint64_t)(1 << 16) - 1, + &den, &num); + + printk(BIOS_INFO, "M = %lu , N= %lu\n", num, den); + *pixel_m = num; + *pixel_n = den; + return 0; +} + +static int edp_check_link_bandwidth(uint32_t pixel_clock_khz, uint32_t link_rate_khz, + uint32_t lane_count, uint32_t bits_per_color) +{ + uint32_t bpp = bits_per_color * 3; + + uint64_t pixel_data_rate_bps = (uint64_t)pixel_clock_khz * 1000ULL * bpp; + + uint64_t raw_link_bps = (uint64_t)link_rate_khz * 1000ULL * 10ULL * lane_count; + + /* payload shrink */ + uint64_t effective_link_bps = (raw_link_bps * 8ULL) / 10ULL; + + return pixel_data_rate_bps <= effective_link_bps; +} + +static uint32_t choose_best_color_depth(struct edid *edid, uint32_t link_rate_khz, + uint32_t lane_count) +{ + uint32_t clk = edid->mode.pixel_clock; + + printk(BIOS_DEBUG, "%d %d %d\n", clk, link_rate_khz, lane_count); + + if ((edid->panel_bits_per_color >= COLOR_DEPTH_10BPC) && + (edp_check_link_bandwidth(clk, link_rate_khz, lane_count, 10))) + return COLOR_DEPTH_10BPC; + + if ((edid->panel_bits_per_color >= COLOR_DEPTH_8BPC) && + (edp_check_link_bandwidth(clk, link_rate_khz, lane_count, 8))) + return COLOR_DEPTH_8BPC; + + if ((edid->panel_bits_per_color >= COLOR_DEPTH_6BPC) && + (edp_check_link_bandwidth(clk, link_rate_khz, lane_count, 6))) + return COLOR_DEPTH_6BPC; + + printk(BIOS_ERR, "Searching for suitable color width failed\n"); + return 0; +} + +static void edp_config_ctrl(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + uint32_t config = 0, depth = BPC_TO_ENUM(ctrl->color_depth); + + /* Default-> LSCLK DIV: 1/4 LCLK */ + config |= (2 << EDP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); + + /* Scrambler reset enable */ + if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) + config |= EDP_CONFIGURATION_CTRL_ASSR; + + config |= depth << EDP_CONFIGURATION_CTRL_BPC_SHIFT; + + /* Num of Lanes */ + config |= ((ctrl->lane_cnt - 1) << EDP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); + + if (dpcd[DP_DPCD_REV] >= 0x11 && (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) + config |= EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING; + + config |= EDP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ + + /* sync clock & static Mvid */ + config |= EDP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; + config |= EDP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; + + write32(&edp_lclk->configuration_ctrl, config); +} + +static void edp_ctrl_config_misc(struct edp_ctrl *ctrl) +{ + uint32_t misc_val; + enum edp_color_depth depth = BPC_TO_ENUM(ctrl->color_depth); + + misc_val = read32(&edp_lclk->misc1_misc0); + + /* clear bpp bits */ + misc_val &= ~(0x07 << EDP_MISC0_TEST_BITS_DEPTH_SHIFT); + misc_val |= depth << EDP_MISC0_TEST_BITS_DEPTH_SHIFT; + + /* Configure clock to synchronous mode */ + misc_val |= EDP_MISC0_SYNCHRONOUS_CLK; + write32(&edp_lclk->misc1_misc0, misc_val); +} + +static int edp_ctrl_config_msa(struct edp_ctrl *ctrl) +{ + uint32_t pixel_m, pixel_n; + uint32_t mvid, nvid; + const u32 nvid_fixed = 0x8000; + uint8_t rate = ctrl->link_rate; + + if (edp_ctrl_pixel_clock_dividers(ctrl, &pixel_m, &pixel_n) < 0) + return -1; + + mvid = (pixel_m & 0xFFFF) * 5; + + nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + + if (nvid < nvid_fixed) { + printk(BIOS_INFO, "nvid is< nvid_fixed\n"); + u32 temp; + + temp = (nvid_fixed / nvid) * nvid; + mvid = (nvid_fixed / nvid) * mvid; + nvid = temp; + } + + mvid = mvid * 2; /* Databus Widen, 2 Pixel / Pixels clock */ + + /* Link Rate scaling */ + if (rate == DP_LINK_BW_5_4) + nvid *= 2; + + if (rate == DP_LINK_BW_8_1) + nvid *= 3; + + printk(BIOS_INFO, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); + + write32(&edp_lclk->software_mvid, mvid); + write32(&edp_lclk->software_nvid, nvid); + + write32(&edp_p0clk->dsc_dto, 0x0); + return 0; +} + +static void edp_ctrl_timing_cfg(struct edid *edid) +{ + uint32_t hpolarity = (edid->mode.phsync == '+'); + + /* This has to be plus "+", since there is bug in EDID parsing, + which fills + if vsyns is not present in EDID, + we are keeping it minus "-"for missing override. */ + uint32_t vpolarity = (edid->mode.pvsync == '-'); + + printk(BIOS_DEBUG, + "Confirm Parsing phsync=%c pvsync=%c hpol=%u vpol=%u hspw=0x%x vspw=0x%x\n", + edid->mode.phsync, edid->mode.pvsync, hpolarity, vpolarity, edid->mode.hspw, + edid->mode.vspw); + + /* Configure eDP timing to HW */ + write32(&edp_lclk->total_hor_ver, + (edid->mode.ha + edid->mode.hbl) | + (((edid->mode.va + edid->mode.vbl) << 16) & 0xffff0000)); + + write32(&edp_lclk->start_hor_ver_from_sync, + (edid->mode.hbl - edid->mode.hso) | + (((edid->mode.vbl - edid->mode.vso) << 16) & 0xffff0000)); + + write32(&edp_lclk->hysnc_vsync_width_polarity, + (edid->mode.hspw & 0x7fff) | /* HSW[14:0] */ + (hpolarity << 15) | /* HSP[15] */ + ((edid->mode.vspw & 0x7fff) << 16) | /* VSW[30:16] */ + (vpolarity << 31)); + + write32(&edp_lclk->active_hor_ver, + (edid->mode.ha) | ((edid->mode.va << 16) & 0xffff0000)); +} + +static void edp_mainlink_ctrl(int enable) +{ + uint32_t data = 0; + + write32(&edp_lclk->mainlink_ctrl, 0x2); + if (enable) + data |= 0x1; + write32(&edp_lclk->mainlink_ctrl, data); +} + +static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, struct edid *edid, uint8_t *dpcd, + int enable) +{ + int ret = 0; + uint32_t m = 0, n = 0; + + if (enable) { + uint64_t link_hz; + + edp_phy_power_on(ctrl->link_rate_khz, ctrl->lane_cnt); + + /* link_rate_khz is in kHz -> convert to Hz */ + link_hz = (uint64_t)ctrl->link_rate_khz * 1000ULL; + + struct clock_freq_config link_cfg[] = { + { + .hz = link_hz, + .src = 4, + .div = QCOM_CLOCK_DIV(1), + }, + }; + + printk(BIOS_DEBUG, "[ Starting mdss_dptx3_link_rcg @ %llu Hz ]\n", link_hz); + + clock_configure(&disp_cc->mdss_dptx3_link_rcg, link_cfg, link_hz, + ARRAY_SIZE(link_cfg)); + + ret = mdss_clock_enable(DISP_CC_MDSS_DPTX3_LINK_CBCR); + if (ret) + printk(BIOS_ERR, "failed to enable link clk\n"); + + ret = mdss_clock_enable(DISP_CC_MDSS_DPTX3_LINK_INTF_CBCR); + if (ret) + printk(BIOS_ERR, "failed to enable link intf clk\n"); + + /* Get pixel clock divider values for the current mode/link */ + edp_ctrl_pixel_clock_dividers(ctrl, &m, &n); + + /* divide by 2 because of Databus widen. + 2 pixels per clock. 326 for pixel clock from DPCD */ + uint64_t pixel_hz = (ctrl->pixel_rate / 1000) / 2 * MHz; + + struct clock_freq_config pixel0_cfg[] = { + { + .hz = pixel_hz, + .src = 3, + .div = QCOM_CLOCK_DIV(1), + .m = m, + .n = n, + .d_2 = n, + }, + }; + + printk(BIOS_DEBUG, "[ pixel0: hz=%llu m=%u n=%u ]\n", pixel_hz, m, n); + + clock_configure(&disp_cc->mdss_dptx3_pixel0_rcg, pixel0_cfg, pixel_hz, + ARRAY_SIZE(pixel0_cfg)); + clock_enable(&disp_cc->mdss_dptx3_pixel0_cbcr); + + printk(BIOS_DEBUG, "[ Setting Mainlink control as 1 ]\n"); + + /* mainlink_levels */ + uint32_t safe_to_exit_level = eDP_SAFE_EXIT_LVL_LANE1; + switch (ctrl->lane_cnt) { + case 1: + safe_to_exit_level = eDP_SAFE_EXIT_LVL_LANE1; + break; + case 2: + safe_to_exit_level = eDP_SAFE_EXIT_LVL_LANE2; + break; + case 4: + safe_to_exit_level = eDP_SAFE_EXIT_LVL_LANE4; + break; + default: + printk(BIOS_DEBUG, "setting the default safe_to_exit_level = %u\n", + safe_to_exit_level); + break; + } + + write32(&edp_lclk->mainlink_levels, safe_to_exit_level); + + edp_mainlink_ctrl(1); + } else { + edp_mainlink_ctrl(0); + /* disable clocks here if your flow expects it */ + } +} + +static int edp_ctrl_training(struct edp_ctrl *ctrl, struct edid *edid, uint8_t *dpcd) +{ + /* Do link training only when power is on */ + int ret = edp_do_link_train(ctrl, dpcd); + + /* Re-configure main link */ + while (ret == EDP_TRAIN_RECONFIG) { + edp_ctrl_irq_enable(0); + edp_ctrl_link_enable(ctrl, edid, dpcd, 0); + + /* edp Phy enable */ + write32(&edp_ahbclk->phy_ctrl, 0x4 | 0x1); + write32(&edp_ahbclk->phy_ctrl, 0x0); + edp_phy_enable(ctrl->link_rate_khz); + + edp_ctrl_irq_enable(1); + edp_ctrl_link_enable(ctrl, edid, dpcd, 1); + + ret = edp_do_link_train(ctrl, dpcd); + } + return ret; +} + +static void edp_get_best_rate_from_table(struct edp_ctrl *ctrl, uint8_t *dpcd) +{ + uint8_t tbl[DP_EDP_RATE_TABLE_SIZE] = {0}; + int ret; + int best_idx = -1; + uint32_t best_rate_khz = 0; + + ret = edp_aux_transfer(DP_SUPPORTED_LINK_RATES, DP_AUX_NATIVE_READ, tbl, sizeof(tbl)); + if (ret < 0) { + printk(BIOS_ERR, "SUPPORTED_LINK_RATES read failed\n"); + } + + /* Parse up to 8 entries (each 2 bytes) */ + for (int i = 0; i < DP_EDP_RATE_TABLE_SIZE / 2; i++) { + uint16_t raw = tbl[i * 2] | (tbl[i * 2 + 1] << 8); + if (!raw) + break; + + uint32_t rate_khz = raw * 20; + + if (rate_khz <= 810000 && rate_khz > best_rate_khz) { + best_rate_khz = rate_khz; + best_idx = i; + } + } + + ctrl->link_rate_khz = best_rate_khz; + ctrl->use_rate_select = true; + ctrl->rate_select_idx = best_idx; + + /* manual override for link rate < best_idx = -1;> */ + if (best_idx < 0) { + ctrl->link_rate_khz = 540000; + ctrl->use_rate_select = false; + ctrl->rate_select_idx = 0; + + printk(BIOS_DEBUG, "No valid eDP rate table, fallback 540000 kHz\n"); + } + + dpcd[DP_MAX_LINK_RATE] = ctrl->link_rate_khz / DP_LINK_RATE_UNIT_KHZ; + ctrl->link_rate = dpcd[DP_MAX_LINK_RATE]; + + printk(BIOS_DEBUG, "eDP rate-table: best_rate_khz=%u idx=%d\n", best_rate_khz, + best_idx); +} + +int edp_ctrl_on(struct edp_ctrl *ctrl, struct edid *edid, uint8_t *dpcd) +{ + uint8_t value; + int ret; + + printk(BIOS_DEBUG, "\nDPCD provided max link rate = %u\n", dpcd[DP_MAX_LINK_RATE]); + + if (dpcd[DP_MAX_LINK_RATE] == 0) { + edp_get_best_rate_from_table(ctrl, dpcd); + } else { + ctrl->link_rate_khz = dpcd[DP_MAX_LINK_RATE] * DP_LINK_RATE_UNIT_KHZ; + ctrl->link_rate = dpcd[DP_MAX_LINK_RATE]; + ctrl->use_rate_select = false; + ctrl->rate_select_idx = 0; + } + + ctrl->lane_cnt = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; + + edid->panel_bits_per_color = + choose_best_color_depth(edid, ctrl->link_rate_khz, ctrl->lane_cnt); + + edid->panel_bits_per_pixel = edid->panel_bits_per_color * 3; + ctrl->color_depth = edid->panel_bits_per_color; + ctrl->pixel_rate = edid->mode.pixel_clock; + + printk(BIOS_DEBUG, + "====================Link Training starts here ========================\n"); + printk(BIOS_DEBUG, + "eDP ctrl init: link_rate_khz=%u link_rate=0x%x lane_cnt=%u " + "v_level=%u p_level=%u pixel_rate=%u color_depth=%u\n", + ctrl->link_rate_khz, ctrl->link_rate, ctrl->lane_cnt, ctrl->v_level, + ctrl->p_level, ctrl->pixel_rate, ctrl->color_depth); + + /* DP_SET_POWER register is only available on DPCD v1.1 and later */ + if (dpcd[DP_DPCD_REV] >= 0x11) { + ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_READ, &value, 1); + printk(BIOS_DEBUG, "DPCD power read address=%x\n", DP_SET_POWER); + if (ret < 0) { + printk(BIOS_ERR, "edp native read failure\n"); + return -1; + } + + value &= ~DP_SET_POWER_MASK; + value |= DP_SET_POWER_D0; + + ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_WRITE, &value, 1); + printk(BIOS_DEBUG, "DPCD power Set address=%x : %x\n", DP_SET_POWER, value); + if (ret < 0) { + printk(BIOS_ERR, "edp native read failure\n"); + return -1; + } + + /* + * According to the DP 1.1 specification, a "Sink Device must + * exit the power saving state within 1 ms" (Section 2.5.3.1, + * Table 5-52, "Sink Control Field" (register 0x600). + */ + udelay(1000); + } + + edp_ctrl_irq_enable(1); + edp_ctrl_link_enable(ctrl, edid, dpcd, 1); + + /* Start link training */ + ret = edp_ctrl_training(ctrl, edid, dpcd); + if (ret != EDP_TRAIN_SUCCESS) { + printk(BIOS_ERR, "edp training failure\n"); + return -1; + } + + edp_train_pattern_set_write(0); + + printk(BIOS_DEBUG, + "====================Link Training Ends here ========================\n\n\n\n"); + edp_state_ctrl(SW_SEND_VIDEO); + + write32(&edp_lclk->mainlink_ctrl, 0x2000000); + write32(&edp_lclk->mainlink_ctrl, 0x2000002); + write32(&edp_lclk->mainlink_ctrl, 0x2000000); + write32(&edp_lclk->mainlink_ctrl, 0x2000001); + + edp_config_ctrl(ctrl, dpcd); + edp_ctrl_config_misc(ctrl); + edp_ctrl_timing_cfg(edid); + + if (edp_ctrl_config_msa(ctrl) < 0) + return -1; + + edp_ctrl_config_TU(ctrl, edid); + + edp_ctrl_irq_enable(0); + + return 0; +} diff --git a/src/soc/qualcomm/x1p42100/display/edp_panel_tu.c b/src/soc/qualcomm/x1p42100/display/edp_panel_tu.c new file mode 100644 index 00000000000..579672b8406 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/edp_panel_tu.c @@ -0,0 +1,951 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DP_TU_FP_EDGE 0x40000 +#define DRM_FIXED_POINT 32 +#define DRM_FIXED_ONE (1ULL << DRM_FIXED_POINT) +#define DRM_FIXED_EPSILON 1LL +#define DRM_FIXED_ALMOST_ONE (DRM_FIXED_ONE - DRM_FIXED_EPSILON) + +static inline s64 div64_s64(s64 dividend, s64 divisor) +{ + return dividend / divisor; +} + +static inline uint32_t drm_fixp_msbset(s64 a) +{ + uint32_t shift, sign = (a >> 63) & 1; + + for (shift = 62; shift > 0; --shift) + if (((a >> shift) & 1) != sign) + return shift; + + return 0; +} + +static inline s64 drm_fixp_div(s64 a, s64 b) +{ + uint32_t shift = 62 - drm_fixp_msbset(a); + s64 result; + + a <<= shift; + + if (shift < DRM_FIXED_POINT) + b >>= (DRM_FIXED_POINT - shift); + + result = div64_s64(a, b); + + if (shift > DRM_FIXED_POINT) + return result >> (shift - DRM_FIXED_POINT); + + return result; +} + +static inline int drm_fixp2int(s64 a) +{ + return ((s64)a) >> DRM_FIXED_POINT; +} + +static inline int drm_fixp2int_ceil(s64 a) +{ + if (a >= 0) + return drm_fixp2int(a + DRM_FIXED_ALMOST_ONE); + else + return drm_fixp2int(a - DRM_FIXED_ALMOST_ONE); +} + +static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline s64 drm_fixp_mul(s64 a, s64 b) +{ + uint32_t shift = drm_fixp_msbset(a) + drm_fixp_msbset(b); + s64 result; + + if (shift > 61) { + shift = shift - 61; + a >>= (shift >> 1) + (shift & 1); + b >>= shift >> 1; + } else + shift = 0; + + result = a * b; + + if (shift > DRM_FIXED_POINT) + return result << (shift - DRM_FIXED_POINT); + + if (shift < DRM_FIXED_POINT) + return result >> (DRM_FIXED_POINT - shift); + + return result; +} + +static inline s64 drm_fixp_from_fraction(s64 a, s64 b) +{ + s64 res; + bool a_neg = a < 0; + bool b_neg = b < 0; + u64 a_abs = a_neg ? -a : a; + u64 b_abs = b_neg ? -b : b; + u64 rem; + + /* determine integer part */ + u64 res_abs = div64_u64_rem(a_abs, b_abs, &rem); + + /* determine fractional part */ + { + u32 i = DRM_FIXED_POINT; + + do { + rem <<= 1; + res_abs <<= 1; + if (rem >= b_abs) { + res_abs |= 1; + rem -= b_abs; + } + } while (--i != 0); + } + + /* round up LSB */ + { + u64 summand = (rem << 1) >= b_abs; + + res_abs += summand; + } + + res = (s64)res_abs; + if (a_neg ^ b_neg) + res = -res; + return res; +} + +static int _tu_param_compare(s64 a, s64 b) +{ + u32 a_int, a_frac, a_sign; + u32 b_int, b_frac, b_sign; + s64 a_temp, b_temp, minus_1; + + if (a == b) + return 0; + + minus_1 = drm_fixp_from_fraction(-1, 1); + + a_int = (a >> 32) & 0x7FFFFFFF; + a_frac = a & 0xFFFFFFFF; + a_sign = (a >> 32) & 0x80000000 ? 1 : 0; + + b_int = (b >> 32) & 0x7FFFFFFF; + b_frac = b & 0xFFFFFFFF; + b_sign = (b >> 32) & 0x80000000 ? 1 : 0; + + if (a_sign > b_sign) + return 2; + else if (b_sign > a_sign) + return 1; + + if (!a_sign && !b_sign) { /* positive */ + if (a > b) + return 1; + else + return 2; + } else { /* negative */ + a_temp = drm_fixp_mul(a, minus_1); + b_temp = drm_fixp_mul(b, minus_1); + + if (a_temp > b_temp) + return 2; + else + return 1; + } + printk(BIOS_INFO, "%x, %x, %x\n", b_int, b_frac, b_sign); + printk(BIOS_INFO, "%x, %x, %x\n", a_int, a_frac, a_sign); +} + +static s64 fixp_subtract(s64 a, s64 b) +{ + s64 minus_1 = drm_fixp_from_fraction(-1, 1); + + if (a >= b) + return a - b; + + return drm_fixp_mul(b - a, minus_1); +} + +static inline int fixp2int_ceil(s64 a) +{ + return a ? drm_fixp2int_ceil(a) : 0; +} + +static void _tu_valid_boundary_calc(struct tu_algo_data *tu) +{ + s64 temp1_fp, temp2_fp; + int temp, temp1, temp2; + int compare_result_1, compare_result_2, compare_result_3; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + + tu->new_valid_boundary_link = fixp2int_ceil(temp2_fp); + + temp = (tu->i_upper_boundary_count * tu->new_valid_boundary_link + + tu->i_lower_boundary_count * (tu->new_valid_boundary_link - 1)); + temp1 = tu->i_upper_boundary_count + tu->i_lower_boundary_count; + tu->average_valid2_fp = drm_fixp_from_fraction(temp, temp1); + + temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); + temp2_fp = tu->lwidth_fp; + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); + tu->n_tus = drm_fixp2int(temp2_fp); + + if ((uint32_t)temp2_fp > 0xFFFFF000) + tu->n_tus += 1; + + temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); + temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); + temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); + temp2_fp = temp1_fp - temp2_fp; + temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu->n_remainder_symbols_per_lane_fp = temp2_fp; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + tu->last_partial_tu_fp = drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, temp1_fp); + + if (tu->n_remainder_symbols_per_lane_fp != 0) + tu->remainder_symbols_exist = 1; + else + tu->remainder_symbols_exist = 0; + + temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); + tu->n_tus_per_lane = drm_fixp2int(temp1_fp); + + tu->paired_tus = (int)((tu->n_tus_per_lane) / temp1); + + tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * temp1; + + if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { + tu->remainder_tus_upper = tu->i_upper_boundary_count; + tu->remainder_tus_lower = tu->remainder_tus - tu->i_upper_boundary_count; + } else { + tu->remainder_tus_upper = tu->remainder_tus; + tu->remainder_tus_lower = 0; + } + + temp = tu->paired_tus * + (tu->i_upper_boundary_count * tu->new_valid_boundary_link + + tu->i_lower_boundary_count * (tu->new_valid_boundary_link - 1)) + + (tu->remainder_tus_upper * tu->new_valid_boundary_link) + + (tu->remainder_tus_lower * (tu->new_valid_boundary_link - 1)); + tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); + + if (tu->remainder_symbols_exist) { + temp1_fp = tu->total_valid_fp + tu->n_remainder_symbols_per_lane_fp; + temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); + temp2_fp = temp2_fp + tu->last_partial_tu_fp; + temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); + } else { + temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); + temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); + } + tu->effective_valid_fp = temp1_fp; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + tu->n_n_err_fp = fixp_subtract(tu->effective_valid_fp, temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + tu->n_err_fp = fixp_subtract(tu->average_valid2_fp, temp2_fp); + + tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; + + temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); + temp2_fp = tu->lwidth_fp; + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); + tu->n_tus_incl_last_incomplete_tu = fixp2int_ceil(temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); + temp1_fp = fixp_subtract(tu->average_valid2_fp, temp2_fp); + temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + temp1 = fixp2int_ceil(temp1_fp); + + if ((uint32_t)temp1_fp < DP_TU_FP_EDGE) + temp1 = drm_fixp2int(temp1_fp); + + temp = tu->i_upper_boundary_count * tu->nlanes; + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); + temp2_fp = fixp_subtract(temp1_fp, temp2_fp); + temp1_fp = drm_fixp_from_fraction(temp, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + temp2 = fixp2int_ceil(temp2_fp); + + if ((uint32_t)temp2_fp < DP_TU_FP_EDGE) + temp2 = drm_fixp2int(temp2_fp); + + tu->extra_required_bytes_new_tmp = temp1 + temp2; + + temp = tu->extra_required_bytes_new_tmp * 8; + temp1_fp = drm_fixp_div(temp, tu->bpp); + tu->extra_pclk_cycles_tmp = fixp2int_ceil(temp1_fp); + + temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); + temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); + + temp1_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); + temp = fixp2int_ceil(temp1_fp); + + if ((uint32_t)temp1_fp < DP_TU_FP_EDGE) + temp = drm_fixp2int(temp1_fp); + + tu->extra_pclk_cycles_in_link_clk_tmp = temp; + tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; + + tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; + + tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + + tu->lower_filler_size_tmp + tu->extra_buffer_margin; + + temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); + tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); + + if (tu->rb2) { + temp1_fp = drm_fixp_mul(tu->delay_start_time_fp, tu->lclk_fp); + tu->delay_start_link_lclk = fixp2int_ceil(temp1_fp); + + if (tu->remainder_tus > tu->i_upper_boundary_count) { + temp = (tu->remainder_tus - tu->i_upper_boundary_count) * + (tu->new_valid_boundary_link - 1); + temp += (tu->i_upper_boundary_count * tu->new_valid_boundary_link); + temp *= tu->nlanes; + } else { + temp = tu->nlanes * tu->remainder_tus * tu->new_valid_boundary_link; + } + + temp1 = tu->i_lower_boundary_count * (tu->new_valid_boundary_link - 1); + temp1 += tu->i_upper_boundary_count * tu->new_valid_boundary_link; + temp1 *= tu->paired_tus * tu->nlanes; + temp1_fp = drm_fixp_from_fraction(tu->n_symbols - temp1 - temp, tu->nlanes); + tu->last_partial_lclk = fixp2int_ceil(temp1_fp); + + tu->tu_active_cycles = + (int)((tu->n_tus_per_lane * tu->tu_size) + tu->last_partial_lclk); + tu->post_tu_hw_pipe_delay = 4 /*BS_on_the_link*/ + 1 /*BE_next_ren*/; + temp = tu->pre_tu_hw_pipe_delay + tu->delay_start_link_lclk + + tu->tu_active_cycles + tu->post_tu_hw_pipe_delay; + + if (tu->fec_en == 1) { + if (tu->nlanes == 1) { + temp1_fp = drm_fixp_from_fraction(temp, 500); + tu->parity_symbols = fixp2int_ceil(temp1_fp) * 12 + 1; + } else { + temp1_fp = drm_fixp_from_fraction(temp, 250); + tu->parity_symbols = fixp2int_ceil(temp1_fp) * 6 + 1; + } + } else { /* no fec BW impact */ + tu->parity_symbols = 0; + } + + tu->link_config_hactive_time = temp + tu->parity_symbols; + + if (tu->resolution_line_time >= tu->link_config_hactive_time + 1 /*margin*/) + tu->hbp_delayStartCheck = 1; + else + tu->hbp_delayStartCheck = 0; + } else { + compare_result_3 = _tu_param_compare(tu->hbp_time_fp, tu->delay_start_time_fp); + if (compare_result_3 < 2) + tu->hbp_delayStartCheck = 1; + else + tu->hbp_delayStartCheck = 0; + } + + compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); + if (compare_result_1 == 2) + compare_result_1 = 1; + else + compare_result_1 = 0; + + compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); + if (compare_result_2 == 2) + compare_result_2 = 1; + else + compare_result_2 = 0; + + if (((tu->even_distribution == 1) || + ((tu->even_distribution_BF == 0) && (tu->even_distribution_legacy == 0))) && + tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && compare_result_2 && + (compare_result_1 || (tu->min_hblank_violated == 1)) && + (tu->new_valid_boundary_link - 1) > 0 && (tu->hbp_delayStartCheck == 1) && + (tu->delay_start_link_tmp <= 1023)) { + tu->upper_boundary_count = tu->i_upper_boundary_count; + tu->lower_boundary_count = tu->i_lower_boundary_count; + tu->err_fp = tu->n_n_err_fp; + tu->boundary_moderation_en = true; + tu->tu_size_desired = tu->tu_size; + tu->valid_boundary_link = tu->new_valid_boundary_link; + tu->effective_valid_recorded_fp = tu->effective_valid_fp; + tu->even_distribution_BF = 1; + tu->delay_start_link = tu->delay_start_link_tmp; + } else if (tu->boundary_mod_lower_err == 0) { + compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); + if (compare_result_1 == 2) + tu->boundary_mod_lower_err = 1; + } +} + +static void _dp_calc_boundary(struct tu_algo_data *tu) +{ + s64 temp1_fp = 0, temp2_fp = 0; + + do { + tu->err_fp = drm_fixp_from_fraction(1000, 1); + + temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); + temp2_fp = drm_fixp_from_fraction(tu->delay_start_link_extra_pixclk, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + tu->extra_buffer_margin = fixp2int_ceil(temp1_fp); + + temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); + temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); + tu->n_symbols = fixp2int_ceil(temp1_fp); + + for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { + for (tu->i_upper_boundary_count = 1; tu->i_upper_boundary_count <= 15; + tu->i_upper_boundary_count++) { + for (tu->i_lower_boundary_count = 1; + tu->i_lower_boundary_count <= 15; + tu->i_lower_boundary_count++) { + _tu_valid_boundary_calc(tu); + } + } + } + tu->delay_start_link_extra_pixclk--; + } while (!tu->boundary_moderation_en && tu->boundary_mod_lower_err == 1 && + tu->delay_start_link_extra_pixclk != 0 && + ((tu->second_loop_set == 0 && tu->rb2 == 1) || tu->rb2 == 0)); +} + +static void _dp_calc_extra_bytes(struct tu_algo_data *tu) +{ + s64 temp1_fp = 0, temp2_fp = 0; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); + temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); + + temp2_fp = fixp_subtract(temp1_fp, temp2_fp); + + if ((uint32_t)temp2_fp <= DP_TU_FP_EDGE) { + tu->extra_bytes = 0; + printk(BIOS_DEBUG, "extra_bytes set to 0\n"); + } else { + temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + tu->extra_bytes = fixp2int_ceil(temp2_fp); + } + + temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); + temp2_fp = drm_fixp_from_fraction(8, tu->bpp); + temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); + tu->extra_pclk_cycles = fixp2int_ceil(temp1_fp); + + temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); + temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + tu->extra_pclk_cycles_in_link_clk = fixp2int_ceil(temp1_fp); +} + +static void dp_tu_update_timings(struct dp_tu_calc_input *in, struct tu_algo_data *tu) +{ + int nlanes = in->nlanes; + int dsc_num_slices = in->num_of_dsc_slices; + int dsc_num_bytes = 0; + int numerator; + s64 pclk_dsc_fp; + s64 dwidth_dsc_fp; + s64 hbp_dsc_fp; + s64 overhead_dsc_fp; + int tot_num_eoc_symbols = 0; + int tot_num_hor_bytes = 0; + int tot_num_dummy_bytes = 0; + int dwidth_dsc_bytes = 0; + int eoc_bytes = 0; + s64 tot_num_hor_bytes_frac_fp = 0; + s64 temp1_fp, temp2_fp, temp3_fp; + + tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); + tu->orig_lclk_fp = tu->lclk_fp; + tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); + tu->orig_pclk_fp = tu->pclk_fp; + tu->lwidth = in->hactive; + tu->hbp_relative_to_pclk = in->hporch; + tu->nlanes = in->nlanes; + tu->bpp = in->bpp; + tu->pixelEnc = in->pixel_enc; + tu->dsc_en = in->dsc_en; + tu->fec_en = in->fec_en; + tu->async_en = in->async_en; + tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); + tu->orig_lwidth = in->hactive; + tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); + tu->orig_hbp = in->hporch; + tu->rb2 = (in->hporch < 160) ? 1 : 0; + tu->comp_bpp = in->comp_bpp; + tu->ppc_div_factor = in->ppc_div_factor; + + if (!in->comp_bpp) + tu->comp_bpp = 8; + + if (in->ppc_div_factor != 4) + tu->ppc_div_factor = 2; + + if (tu->pixelEnc == 420) { + temp1_fp = drm_fixp_from_fraction(2, 1); + tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); + tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); + tu->hbp_relative_to_pclk_fp = + drm_fixp_div(tu->hbp_relative_to_pclk_fp, temp1_fp); + } + + if (tu->pixelEnc == 422) { + switch (tu->bpp) { + case 24: + tu->bpp = 16; + tu->bpc = 8; + break; + case 30: + tu->bpp = 20; + tu->bpc = 10; + break; + default: + tu->bpp = 16; + tu->bpc = 8; + break; + } + } else + tu->bpc = tu->bpp / 3; + + if (!in->dsc_en) + goto fec_check; + + tu->bpp = 24; /* hardcode to 24 if DSC is enabled. */ + + temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); + temp2_fp = drm_fixp_from_fraction(in->bpp, 1); + temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); + + temp1_fp = drm_fixp_from_fraction(8, 1); + temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); + + numerator = drm_fixp2int(temp3_fp); + + dsc_num_bytes = numerator / dsc_num_slices; + eoc_bytes = dsc_num_bytes % nlanes; + tot_num_eoc_symbols = nlanes * dsc_num_slices; + tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; + tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; + + temp1_fp = drm_fixp_from_fraction(8, 1); + temp2_fp = drm_fixp_from_fraction(tu->orig_lwidth, 1); + temp3_fp = drm_fixp_div(tu->comp_bpp, temp1_fp); + tot_num_hor_bytes_frac_fp = drm_fixp_mul(temp3_fp, temp2_fp); + + if (dsc_num_bytes == 0) + printk(BIOS_DEBUG, "incorrect no of bytes per slice=%d\n", dsc_num_bytes); + + dwidth_dsc_bytes = (tot_num_hor_bytes + tot_num_eoc_symbols + + (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); + + temp1_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 1); + overhead_dsc_fp = drm_fixp_div(temp1_fp, tot_num_hor_bytes_frac_fp); + printk(BIOS_DEBUG, "%lld\n", overhead_dsc_fp); + + dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); + + temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); + temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); + pclk_dsc_fp = temp1_fp; + + temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); + temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); + hbp_dsc_fp = temp2_fp; + + /* output */ + tu->pclk_fp = pclk_dsc_fp; + tu->lwidth_fp = dwidth_dsc_fp; + tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; + +fec_check: + if (in->fec_en) { + temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ + tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); + } +} + +static void dp_tu_calculate(struct dp_tu_calc_input *in) +{ + struct tu_algo_data tu; + int compare_result_1, compare_result_2; + u64 temp = 0, temp1; + s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; + + s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ + s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); + + u8 DP_BRUTE_FORCE = 1; + s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ + uint32_t EXTRA_PIXCLK_CYCLE_DELAY = 4; + s64 HBLANK_MARGIN = drm_fixp_from_fraction(4, 1); + s64 HBLANK_MARGIN_EXTRA = 0; + + memset(&tu, 0, sizeof(tu)); + + dp_tu_update_timings(in, &tu); + + tu.err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ + + temp1_fp = drm_fixp_from_fraction(4, 1); + temp2_fp = drm_fixp_mul(temp1_fp, tu.lclk_fp); + temp_fp = drm_fixp_div(temp2_fp, tu.pclk_fp); + tu.extra_buffer_margin = fixp2int_ceil(temp_fp); + + if (in->compress_ratio == 375 && tu.bpp == 30) + temp1_fp = drm_fixp_from_fraction(24, 8); + else + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + + temp2_fp = drm_fixp_mul(tu.pclk_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu.nlanes, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu.ratio_fp = drm_fixp_div(temp2_fp, tu.lclk_fp); + + tu.original_ratio_fp = tu.ratio_fp; + tu.boundary_moderation_en = false; + tu.upper_boundary_count = 0; + tu.lower_boundary_count = 0; + tu.i_upper_boundary_count = 0; + tu.i_lower_boundary_count = 0; + tu.valid_lower_boundary_link = 0; + tu.even_distribution_BF = 0; + tu.even_distribution_legacy = 0; + tu.even_distribution = 0; + tu.hbp_delayStartCheck = 0; + tu.pre_tu_hw_pipe_delay = 0; + tu.post_tu_hw_pipe_delay = 0; + tu.link_config_hactive_time = 0; + tu.delay_start_link_lclk = 0; + tu.tu_active_cycles = 0; + tu.resolution_line_time = 0; + tu.last_partial_lclk = 0; + tu.delay_start_time_fp = 0; + tu.second_loop_set = 0; + + tu.err_fp = drm_fixp_from_fraction(1000, 1); + tu.n_err_fp = 0; + tu.n_n_err_fp = 0; + + temp = drm_fixp2int(tu.lwidth_fp); + if ((((u32)temp % tu.nlanes) != 0) && + (_tu_param_compare(tu.ratio_fp, DRM_FIXED_ONE) == 2) && (tu.dsc_en == 0)) { + tu.ratio_fp = drm_fixp_mul(tu.ratio_fp, RATIO_SCALE_fp); + } + + if (_tu_param_compare(tu.ratio_fp, DRM_FIXED_ONE) == 1) + tu.ratio_fp = DRM_FIXED_ONE; + + if (HBLANK_MARGIN_EXTRA != 0) { + HBLANK_MARGIN += HBLANK_MARGIN_EXTRA; + printk(BIOS_DEBUG, "increased HBLANK_MARGIN to %lld. (PLUS%lld)\n", + HBLANK_MARGIN, HBLANK_MARGIN_EXTRA); + } + + for (tu.tu_size = 32; tu.tu_size <= 64; tu.tu_size++) { + temp1_fp = drm_fixp_from_fraction(tu.tu_size, 1); + temp2_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + temp = fixp2int_ceil(temp2_fp); + temp1_fp = drm_fixp_from_fraction(temp, 1); + tu.n_err_fp = fixp_subtract(temp1_fp, temp2_fp); + + if (tu.n_err_fp < tu.err_fp) { + tu.err_fp = tu.n_err_fp; + tu.tu_size_desired = tu.tu_size; + } + } + + tu.tu_size_minus1 = tu.tu_size_desired - 1; + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + tu.valid_boundary_link = fixp2int_ceil(temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp2_fp = tu.lwidth_fp; + temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + temp1_fp = drm_fixp_from_fraction(tu.valid_boundary_link, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu.n_tus = drm_fixp2int(temp2_fp); + if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) + tu.n_tus += 1; + + tu.even_distribution_legacy = tu.n_tus % tu.nlanes == 0 ? 1 : 0; + + printk(BIOS_DEBUG, "n_sym= %d, n_tus= %d\n", tu.valid_boundary_link, tu.n_tus); + + _dp_calc_extra_bytes(&tu); + + tu.filler_size = tu.tu_size_desired - tu.valid_boundary_link; + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + tu.ratio_by_tu_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + + tu.delay_start_link = + tu.extra_pclk_cycles_in_link_clk + tu.filler_size + tu.extra_buffer_margin; + + tu.resulting_valid_fp = drm_fixp_from_fraction(tu.valid_boundary_link, 1); + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_div(tu.resulting_valid_fp, temp1_fp); + tu.TU_ratio_err_fp = temp2_fp - tu.original_ratio_fp; + + temp1_fp = drm_fixp_from_fraction((tu.hbp_relative_to_pclk - HBLANK_MARGIN), 1); + tu.hbp_time_fp = drm_fixp_div(temp1_fp, tu.pclk_fp); + + temp1_fp = drm_fixp_from_fraction(tu.delay_start_link, 1); + tu.delay_start_time_fp = drm_fixp_div(temp1_fp, tu.lclk_fp); + + compare_result_1 = _tu_param_compare(tu.hbp_time_fp, tu.delay_start_time_fp); + if (compare_result_1 == 2) /* hbp_time_fp < delay_start_time_fp */ + tu.min_hblank_violated = 1; + + tu.hactive_time_fp = drm_fixp_div(tu.lwidth_fp, tu.pclk_fp); + + compare_result_2 = _tu_param_compare(tu.hactive_time_fp, tu.delay_start_time_fp); + if (compare_result_2 == 2) + tu.min_hblank_violated = 1; + + /* brute force */ + + tu.delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; + tu.diff_abs_fp = tu.resulting_valid_fp - tu.ratio_by_tu_fp; + + temp = drm_fixp2int(tu.diff_abs_fp); + if (!temp && tu.diff_abs_fp <= 0xffff) + tu.diff_abs_fp = 0; + + /* if(diff_abs < 0) diff_abs *= -1 */ + if (tu.diff_abs_fp < 0) + tu.diff_abs_fp = drm_fixp_mul(tu.diff_abs_fp, -1); + + tu.boundary_mod_lower_err = 0; + + temp1_fp = drm_fixp_div(tu.orig_lclk_fp, tu.orig_pclk_fp); + + temp2_fp = drm_fixp_from_fraction(tu.orig_lwidth + tu.orig_hbp, tu.ppc_div_factor); + + temp_fp = drm_fixp_mul(temp1_fp, temp2_fp); + tu.resolution_line_time = drm_fixp2int(temp_fp); + tu.pre_tu_hw_pipe_delay = fixp2int_ceil(temp1_fp) + 2 /*cdc fifo write jitter+2*/ + + 3 /*pre-delay start cycles*/ + + 3 /*post-delay start cycles*/ + 1 /*BE on the link*/; + tu.post_tu_hw_pipe_delay = 4 /*BS_on_the_link*/ + 1 /*BE_next_ren*/; + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp1_fp = drm_fixp_mul(tu.lwidth_fp, temp1_fp); + tu.n_symbols = fixp2int_ceil(temp1_fp); + + if (tu.rb2) { + temp1_fp = drm_fixp_mul(tu.delay_start_time_fp, tu.lclk_fp); + tu.delay_start_link_lclk = fixp2int_ceil(temp1_fp); + + tu.new_valid_boundary_link = tu.valid_boundary_link; + tu.i_upper_boundary_count = 1; + tu.i_lower_boundary_count = 0; + + temp1 = tu.i_upper_boundary_count * tu.new_valid_boundary_link; + temp1 += tu.i_lower_boundary_count * (tu.new_valid_boundary_link - 1); + temp = tu.i_upper_boundary_count + tu.i_lower_boundary_count; + tu.average_valid2_fp = drm_fixp_from_fraction(temp1, temp); + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp1_fp = drm_fixp_mul(tu.lwidth_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu.average_valid2_fp); + tu.n_tus = drm_fixp2int(temp2_fp); + + tu.n_tus_per_lane = tu.n_tus / tu.nlanes; + tu.paired_tus = (int)((tu.n_tus_per_lane) / temp); + + tu.remainder_tus = tu.n_tus_per_lane - tu.paired_tus * temp; + + if (tu.remainder_tus > tu.i_upper_boundary_count) { + temp = (tu.remainder_tus - tu.i_upper_boundary_count) * + (tu.new_valid_boundary_link - 1); + temp += (tu.i_upper_boundary_count * tu.new_valid_boundary_link); + temp *= tu.nlanes; + } else { + temp = tu.nlanes * tu.remainder_tus * tu.new_valid_boundary_link; + } + + temp1 = tu.i_lower_boundary_count * (tu.new_valid_boundary_link - 1); + temp1 += tu.i_upper_boundary_count * tu.new_valid_boundary_link; + temp1 *= tu.paired_tus * tu.nlanes; + temp1_fp = drm_fixp_from_fraction(tu.n_symbols - temp1 - temp, tu.nlanes); + tu.last_partial_lclk = fixp2int_ceil(temp1_fp); + + tu.tu_active_cycles = + (int)((tu.n_tus_per_lane * tu.tu_size) + tu.last_partial_lclk); + + temp = tu.pre_tu_hw_pipe_delay + tu.delay_start_link_lclk + + tu.tu_active_cycles + tu.post_tu_hw_pipe_delay; + + if (tu.fec_en == 1) { + if (tu.nlanes == 1) { + temp1_fp = drm_fixp_from_fraction(temp, 500); + tu.parity_symbols = fixp2int_ceil(temp1_fp) * 12 + 1; + } else { + temp1_fp = drm_fixp_from_fraction(temp, 250); + tu.parity_symbols = fixp2int_ceil(temp1_fp) * 6 + 1; + } + } else { /* no fec BW impact */ + tu.parity_symbols = 0; + } + + tu.link_config_hactive_time = temp + tu.parity_symbols; + + if (tu.link_config_hactive_time + 1 /*margin*/ >= tu.resolution_line_time) + tu.min_hblank_violated = 1; + } + + tu.delay_start_time_fp = 0; + + if ((tu.diff_abs_fp != 0 && + ((tu.diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || + (tu.even_distribution_legacy == 0) || (DP_BRUTE_FORCE == 1))) || + (tu.min_hblank_violated == 1)) { + _dp_calc_boundary(&tu); + + if (tu.boundary_moderation_en) { + temp1_fp = drm_fixp_from_fraction( + (tu.upper_boundary_count * tu.valid_boundary_link + + tu.lower_boundary_count * (tu.valid_boundary_link - 1)), + 1); + temp2_fp = drm_fixp_from_fraction( + (tu.upper_boundary_count + tu.lower_boundary_count), 1); + + tu.resulting_valid_fp = drm_fixp_div(temp1_fp, temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + tu.ratio_by_tu_fp = drm_fixp_mul(tu.original_ratio_fp, temp1_fp); + + tu.valid_lower_boundary_link = tu.valid_boundary_link - 1; + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp1_fp = drm_fixp_mul(tu.lwidth_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu.resulting_valid_fp); + tu.n_tus = drm_fixp2int(temp2_fp); + + tu.tu_size_minus1 = tu.tu_size_desired - 1; + tu.even_distribution_BF = 1; + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_div(tu.resulting_valid_fp, temp1_fp); + tu.TU_ratio_err_fp = temp2_fp - tu.original_ratio_fp; + } + } + + if (tu.async_en) { + temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu.lwidth_fp); + temp = fixp2int_ceil(temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu.nlanes, 1); + temp2_fp = drm_fixp_mul(tu.original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); + temp1_fp = drm_fixp_from_fraction(temp, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + temp = drm_fixp2int(temp2_fp); + + tu.delay_start_link += (int)temp; + } + + temp1_fp = drm_fixp_from_fraction(tu.delay_start_link, 1); + tu.delay_start_time_fp = drm_fixp_div(temp1_fp, tu.lclk_fp); + + /* OUTPUTS */ + struct dp_tu_calc_output tu_table; + tu_table.valid_boundary_link = tu.valid_boundary_link; + tu_table.delay_start_link = tu.delay_start_link; + tu_table.boundary_moderation_en = tu.boundary_moderation_en; + tu_table.valid_lower_boundary_link = tu.valid_lower_boundary_link; + tu_table.upper_boundary_count = tu.upper_boundary_count; + tu_table.lower_boundary_count = tu.lower_boundary_count; + tu_table.tu_size_minus1 = tu.tu_size_minus1; + + printk(BIOS_DEBUG, "TU: %d %d %d %d %d %d %d\n", tu_table.valid_boundary_link, + tu_table.delay_start_link, tu_table.boundary_moderation_en, + tu_table.valid_lower_boundary_link, tu_table.upper_boundary_count, + tu_table.lower_boundary_count, tu_table.tu_size_minus1); + + write32(&edp_lclk->valid_boundary, + tu_table.delay_start_link << 16 | tu_table.valid_boundary_link); + + write32(&edp_lclk->tu, tu_table.tu_size_minus1); + + write32(&edp_lclk->valid_boundary2, tu_table.boundary_moderation_en | + tu_table.valid_lower_boundary_link << 1 | + tu_table.upper_boundary_count << 16 | + tu_table.lower_boundary_count << 20); +} + +void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid) +{ + struct dp_tu_calc_input inp; + + /* link clock (MHz) */ + inp.lclk = ctrl->link_rate_khz / 1000; + + /* pixel clock (kHz) */ + inp.pclk_khz = edid->mode.pixel_clock; + + /* horizontal timing */ + inp.hactive = edid->mode.ha; + inp.hporch = edid->mode.hbl; + + /* lanes */ + inp.nlanes = ctrl->lane_cnt; + + /* bits per pixel from EDID */ + inp.bpp = edid->panel_bits_per_pixel; + + /* Defaults unless advertised */ + inp.pixel_enc = 444; + inp.dsc_en = 0; + inp.fec_en = 0; + inp.async_en = 0; + inp.compress_ratio = 0; + inp.num_of_dsc_slices = 0; + inp.comp_bpp = 0; + inp.ppc_div_factor = 1; + + dp_tu_calculate(&inp); +} diff --git a/src/soc/qualcomm/x1p42100/display/edp_phy_4nm.c b/src/soc/qualcomm/x1p42100/display/edp_phy_4nm.c new file mode 100644 index 00000000000..e4de8fd9426 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/edp_phy_4nm.c @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void edp_phy_ssc_en(bool en) +{ + if (en) { + write32(&edp_phy_pll->qserdes_com_ssc_en_center, 0x01); + write32(&edp_phy_pll->qserdes_com_ssc_adj_per1, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_per1, 0x6B); + write32(&edp_phy_pll->qserdes_com_ssc_per2, 0x02); + write32(&edp_phy_pll->qserdes_com_ssc_step_size1_mode0, 0x92); + write32(&edp_phy_pll->qserdes_com_ssc_step_size2_mode0, 0x01); + } else { + write32(&edp_phy_pll->qserdes_com_ssc_en_center, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_adj_per1, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_per1, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_per2, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_step_size1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_ssc_step_size2_mode0, 0x00); + } +} + +void early_phy_enable(void) +{ + write32(&edp_phy->pd_ctl, 0x2); + write32(&edp_phy->pd_ctl, 0x7D); + + write32(&edp_phy->aux_interrupt_mask, 0x1F); + + write32(&edp_phy_pll->qserdes_com_bias_en_clkbuflr_en, 0x1F); + + write32(&edp_phy->aux_cfg[0], 0x00); + write32(&edp_phy->aux_cfg[1], 0x00); + write32(&edp_phy->aux_cfg[2], 0xA4); + write32(&edp_phy->aux_cfg[3], 0x00); + write32(&edp_phy->aux_cfg[4], 0x0A); + write32(&edp_phy->aux_cfg[5], 0x26); + write32(&edp_phy->aux_cfg[6], 0x0A); + write32(&edp_phy->aux_cfg[7], 0x03); + write32(&edp_phy->aux_cfg[8], 0x37); + write32(&edp_phy->aux_cfg[9], 0x03); + + write32(&edp_phy->aux_interrupt_mask, 0x1f); + write32(&edp_phy->mode, 0xFC); + + if (!wait_us(10000, read32(&edp_phy_pll->qserdes_com_cmn_status) & BIT(7))) + printk(BIOS_ERR, "%s: refgen not ready : 0x%x , Add= %p\n", __func__, + read32(&edp_phy_pll->qserdes_com_cmn_status), + (void *)(&edp_phy_pll->qserdes_com_cmn_status)); + + printk(BIOS_DEBUG, "qserdes_com_cmn_status = 0x%x\n", + read32(&edp_phy_pll->qserdes_com_cmn_status)); + + write32(&edp_phy_lane_tx0->tx_lane_mode1, 0x00); + write32(&edp_phy_lane_tx1->tx_lane_mode1, 0x00); +} + +int edp_phy_enable(uint32_t link_rate) +{ + write32(&edp_phy->pd_ctl, 0x2); + write32(&edp_phy->pd_ctl, 0x7D); + + write32(&edp_phy->aux_interrupt_mask, 0x1F); + + write32(&edp_phy_pll->qserdes_com_bias_en_clkbuflr_en, 0x1F); + + write32(&edp_phy->aux_cfg[0], 0x00); + write32(&edp_phy->aux_cfg[1], 0x00); + write32(&edp_phy->aux_cfg[2], 0xA4); + write32(&edp_phy->aux_cfg[3], 0x00); + write32(&edp_phy->aux_cfg[4], 0x0A); + write32(&edp_phy->aux_cfg[5], 0x26); + write32(&edp_phy->aux_cfg[6], 0x0A); + write32(&edp_phy->aux_cfg[7], 0x03); + write32(&edp_phy->aux_cfg[8], 0x37); + write32(&edp_phy->aux_cfg[9], 0x03); + + write32(&edp_phy->aux_interrupt_mask, 0x1f); + write32(&edp_phy->mode, 0xFC); + + if (!wait_us(10000, read32(&edp_phy_pll->qserdes_com_cmn_status) & BIT(7))) + printk(BIOS_ERR, "%s: refgen not ready : 0x%x , Add= %p\n", __func__, + read32(&edp_phy_pll->qserdes_com_cmn_status), + (void *)(&edp_phy_pll->qserdes_com_cmn_status)); + + printk(BIOS_DEBUG, "qserdes_com_cmn_status = 0x%x\n", + read32(&edp_phy_pll->qserdes_com_cmn_status)); + + write32(&edp_phy_lane_tx0->tx_lane_mode1, 0x00); + write32(&edp_phy_lane_tx1->tx_lane_mode1, 0x00); + + if (link_rate >= 324000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_ldo_config, 0x91); + write32(&edp_phy_lane_tx1->tx_ldo_config, 0x91); + } else { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_ldo_config, 0x51); + write32(&edp_phy_lane_tx1->tx_ldo_config, 0x51); + } + + write32(&edp_phy_lane_tx0->tx_lane_mode1, 0x00); + write32(&edp_phy_lane_tx1->tx_lane_mode1, 0x00); + + return 0; +} + + +static const u8 edp_rbr_voltage_swing[4][4] = { + {0x07, 0x0f, 0x16, 0x1f}, + {0x0d, 0x16, 0x1e, 0xff}, + {0x11, 0x1b, 0xff, 0xff}, + {0x16, 0xff, 0xff, 0xff} +}; +static const u8 edp_rbr_pre_emphasis[4][4] = { + {0x05, 0x11, 0x17, 0x1d}, + {0x05, 0x11, 0x18, 0xff}, + {0x06, 0x11, 0xff, 0xff}, + {0x00, 0xff, 0xff, 0xff} +}; + +static const u8 edp_hbr2_voltage_swing[4][4] = { + {0x0b, 0x11, 0x17, 0x1c}, /* sw0, 0.4v */ + {0x10, 0x19, 0x1f, 0xFF}, /* sw1, 0.6 v */ + {0x19, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ + {0x1f, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ +}; + +static const u8 edp_hbr2_pre_emphasis[4][4] = { + {0x0c, 0x15, 0x19, 0x1e}, /* pe0, 0 db */ + {0x0B, 0x15, 0x19, 0xFF}, /* pe1, 3.5 db */ + {0x0e, 0x14, 0xFF, 0xFF}, /* pe2, 6.0 db */ + {0x0d, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ +}; + +static void edp_phy_vm_pe_init(uint32_t link_rate, uint32_t lane_count) +{ + if (link_rate >= 324000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_drv_lvl, edp_hbr2_voltage_swing[0][0]); + write32(&edp_phy_lane_tx0->tx_emp_post1_lvl, edp_hbr2_pre_emphasis[0][0]); + write32(&edp_phy_lane_tx1->tx_drv_lvl, edp_hbr2_voltage_swing[0][0]); + write32(&edp_phy_lane_tx1->tx_emp_post1_lvl, edp_hbr2_pre_emphasis[0][0]); + } else { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_drv_lvl, edp_rbr_voltage_swing[0][0]); + write32(&edp_phy_lane_tx0->tx_emp_post1_lvl, edp_rbr_pre_emphasis[0][0]); + write32(&edp_phy_lane_tx1->tx_drv_lvl, edp_rbr_voltage_swing[0][0]); + write32(&edp_phy_lane_tx1->tx_emp_post1_lvl, edp_rbr_pre_emphasis[0][0]); + } + + u32 bias_en0, bias_en1, drvr_en0, drvr_en1, phy_cfg_1; + + if (lane_count == 1) { + printk(BIOS_DEBUG, "%s: lanes %u\n", __func__, lane_count); + bias_en0 = 0x01; + bias_en1 = 0x00; + drvr_en0 = 0x06; + drvr_en1 = 0x07; + phy_cfg_1 = 0x01; + } else if (lane_count == 2) { + printk(BIOS_DEBUG, "%s: lanes %u\n", __func__, lane_count); + bias_en0 = 0x03; + bias_en1 = 0x00; + drvr_en0 = 0x04; + drvr_en1 = 0x07; + phy_cfg_1 = 0x03; + } else { + printk(BIOS_DEBUG, "%s: lanes %u\n", __func__, lane_count); + bias_en0 = 0x03; + bias_en1 = 0x03; + drvr_en0 = 0x04; + drvr_en1 = 0x04; + phy_cfg_1 = 0x0f; + } + + write32(&edp_phy_lane_tx0->tx_highz_drvr_en, drvr_en0); + write32(&edp_phy_lane_tx0->tx_transceiver_bias_en, bias_en0); + write32(&edp_phy_lane_tx1->tx_highz_drvr_en, drvr_en1); + write32(&edp_phy_lane_tx1->tx_transceiver_bias_en, bias_en1); + write32(&edp_phy->cfg1, phy_cfg_1); + + printk(BIOS_DEBUG, "%s: Ends\n", __func__); +} + +void edp_phy_config(u8 v_level, u8 p_level, uint32_t link_rate) +{ + if (link_rate >= 324000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_drv_lvl, edp_hbr2_voltage_swing[v_level][p_level]); + write32(&edp_phy_lane_tx0->tx_emp_post1_lvl, edp_hbr2_pre_emphasis[v_level][p_level]); + write32(&edp_phy_lane_tx1->tx_drv_lvl, edp_hbr2_voltage_swing[v_level][p_level]); + write32(&edp_phy_lane_tx1->tx_emp_post1_lvl, edp_hbr2_pre_emphasis[v_level][p_level]); + } else { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_lane_tx0->tx_drv_lvl, edp_rbr_voltage_swing[v_level][p_level]); + write32(&edp_phy_lane_tx0->tx_emp_post1_lvl, edp_rbr_pre_emphasis[v_level][p_level]); + write32(&edp_phy_lane_tx1->tx_drv_lvl, edp_rbr_voltage_swing[v_level][p_level]); + write32(&edp_phy_lane_tx1->tx_emp_post1_lvl, edp_rbr_pre_emphasis[v_level][p_level]); + } +} + +static void edp_phy_pll_vco_init(uint32_t link_rate) +{ + edp_phy_ssc_en(false); + + write32(&edp_phy_pll->qserdes_com_svs_mode_clk_sel, 0x01); + write32(&edp_phy_pll->qserdes_com_sysclk_en_sel, 0x0b); + write32(&edp_phy_pll->qserdes_com_sys_clk_ctrl, 0x02); + write32(&edp_phy_pll->qserdes_com_clk_enable1, 0x0c); + write32(&edp_phy_pll->qserdes_com_sysclk_buf_enable, 0x06); + write32(&edp_phy_pll->qserdes_com_clk_sel, 0x30); + write32(&edp_phy_pll->qserdes_com_pll_ivco, 0x07); + write32(&edp_phy_pll->qserdes_com_lock_cmp_en, 0x08); + write32(&edp_phy_pll->qserdes_com_pll_cctrl_mode0, 0x36); + write32(&edp_phy_pll->qserdes_com_pll_rctrl_mode0, 0x16); + write32(&edp_phy_pll->qserdes_com_cp_ctrl_mode0, 0x06); + write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_cmn_config, 0x12); + write32(&edp_phy_pll->qserdes_com_integloop_gain0_mode0, 0x3f); + write32(&edp_phy_pll->qserdes_com_integloop_gain1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_vco_tune_map, 0x00); + write32(&edp_phy_pll->qserdes_com_bg_timer, 0x0a); + write32(&edp_phy_pll->qserdes_com_coreclk_div_mode0, 0x14); + write32(&edp_phy_pll->qserdes_com_vco_tune_ctrl, 0x00); + write32(&edp_phy_pll->qserdes_com_bias_en_clkbuflr_en, 0x17); + write32(&edp_phy_pll->qserdes_com_core_clk_en, 0x0f); + + if (link_rate == 810000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x00); + write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x34); + write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0xC0); + write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x0B); + write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x17); + write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x15); + + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code1_mode0, 0x71); + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code2_mode0, 0x0C); + + } else if (link_rate == 540000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x01); + write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x46); + write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x05); + write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x0F); + write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x0E); + + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code1_mode0, 0x97); + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code2_mode0, 0x10); + } else if (link_rate == 270000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x03); + write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x34); + write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0xC0); + write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x0B); + write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x07); + write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x07); + + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code1_mode0, 0x71); + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code2_mode0, 0x0C); + } else if (link_rate == 162000) { + printk(BIOS_DEBUG, "%s: link rate %u\n", __func__, link_rate); + write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x05); + write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x34); + write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00); + write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0xC0); + write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x0B); + write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x37); + write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x04); + + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code1_mode0, 0x71); + write32(&edp_phy_pll->qserdes_com_bin_vcocal_cmp_code2_mode0, 0x0C); + } +} + +static void edp_phy_lanes_init(void) +{ + write32(&edp_phy_lane_tx0->tx_clk_buf_enable, 0x0f); + write32(&edp_phy_lane_tx0->tx_reset_tsync_en, 0x03); + write32(&edp_phy_lane_tx0->tx_tran_drvr_emp_en, 0x01); + write32(&edp_phy_lane_tx0->tx_tx_band, 0x4); + + write32(&edp_phy_lane_tx1->tx_clk_buf_enable, 0x0f); + write32(&edp_phy_lane_tx1->tx_reset_tsync_en, 0x03); + write32(&edp_phy_lane_tx1->tx_tran_drvr_emp_en, 0x01); + write32(&edp_phy_lane_tx1->tx_tx_band, 0x4); +} + +static void edp_lanes_configure(void) +{ + write32(&edp_phy_lane_tx0->tx_tx_pol_inv, 0x00); + write32(&edp_phy_lane_tx1->tx_tx_pol_inv, 0x00); + + write32(&edp_phy_lane_tx0->tx_drv_lvl_offset, 0x10); + write32(&edp_phy_lane_tx1->tx_drv_lvl_offset, 0x10); + + write32(&edp_phy_lane_tx0->tx_rescode_lane_offset_tx0, 0x11); + write32(&edp_phy_lane_tx0->tx_rescode_lane_offset_tx1, 0x11); + + write32(&edp_phy_lane_tx1->tx_rescode_lane_offset_tx0, 0x11); + write32(&edp_phy_lane_tx1->tx_rescode_lane_offset_tx1, 0x11); +} + +static int edp_phy_pll_vco_configure(uint32_t link_rate, uint32_t lane_count) +{ + u32 phy_vco_div = 0; + + switch (link_rate) { + case 162000: + phy_vco_div = 1; + break; + case 216000: + case 243000: + case 270000: + phy_vco_div = 1; + break; + case 324000: + case 432000: + case 540000: + phy_vco_div = 2; + break; + case 594000: + phy_vco_div = 2; + break; + case 810000: + phy_vco_div = 0; + break; + default: + printk(BIOS_ERR, "%s: Invalid link rate. rate = %u\n", __func__, link_rate); + break; + } + + write32(&edp_phy->vco_div, phy_vco_div); + write32(&edp_phy->cfg, 0x01); + write32(&edp_phy->cfg, 0x05); + write32(&edp_phy->cfg, 0x01); + write32(&edp_phy->cfg, 0x09); + write32(&edp_phy_pll->qserdes_com_resetsm_cntrl, 0x20); + if (!wait_ms(500, read32(&edp_phy_pll->qserdes_com_c_ready_status) & BIT(0))) { + printk(BIOS_ERR, "%s: PLL not locked. Status .., c_ready_status=0x%08x\n", + __func__, read32(&edp_phy_pll->qserdes_com_c_ready_status)); + return -1; + } + + write32(&edp_phy->cfg, 0x19); + edp_lanes_configure(); + edp_phy_vm_pe_init(link_rate, lane_count); + if (!wait_us(10000, read32(&edp_phy->status) & BIT(1))) { + printk(BIOS_ERR, "%s: PHY not ready. Status\n", __func__); + return -1; + } + + write32(&edp_phy->cfg, 0x19); + write32(&edp_phy->cfg, 0x18); + + write32(&edp_phy->cfg, 0x18); + write32(&edp_phy->cfg, 0x19); + if (!wait_us(50000, read32(&edp_phy_pll->qserdes_com_c_ready_status) & BIT(0))) { + printk(BIOS_ERR, "%s: PLL not locked. Status B\n", __func__); + return -1; + } + + return 0; +} + +int edp_phy_power_on(uint32_t link_rate, uint32_t lane_count) +{ + int ret = 0; + edp_phy_pll_vco_init(link_rate); + + write32(&edp_phy->tx0_tx1_lane_ctl, 0x5); + write32(&edp_phy->tx2_tx3_lane_ctl, 0x5); + edp_phy_lanes_init(); + ret = edp_phy_pll_vco_configure(link_rate, lane_count); + + return ret; +} diff --git a/src/soc/qualcomm/x1p42100/display/mdp_intf_TG.c b/src/soc/qualcomm/x1p42100/display/mdp_intf_TG.c new file mode 100644 index 00000000000..fb02edfe73a --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/mdp_intf_TG.c @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#define MDSS_MDP_MAX_PREFILL_FETCH 24 + +void intf_tg_setup(struct edid *edid) +{ + const struct edid_mode *m; + uint32_t full_h_total, full_h_start, full_h_pw; + uint32_t h_total, h_start, h_pw, h_end; + uint32_t v_total, v_start, v_pw; + + /* 2 because of Databus widen, 2 pixels per clock. + HSYNC Period would be divided by 2 */ + uint32_t wide_bus = 2; + + if (!edid) + return; + + m = &edid->mode; + if (!m->ha || !m->va) + return; + + /* Full (non-split) timing from EDID */ + full_h_total = m->ha + m->hbl; + full_h_start = m->hbl; + full_h_pw = m->hspw; + + v_total = m->va + m->vbl; + v_start = m->vbl; + v_pw = m->vspw; + + /* Per-pipe horizontal timing */ + h_total = full_h_total / wide_bus; + h_start = full_h_start / wide_bus; + h_pw = full_h_pw / wide_bus; + h_end = h_total - 1; + + write32(&mdp_intf->intf_mux, 0xF0000); /* use ping_pong 0 & disable split */ + + write32(&mdp_intf->intf_hsync_ctl, (h_total << 16) | (h_pw)); + + write32(&mdp_intf->intf_vysnc_period_f0, v_total * h_total); + + write32(&mdp_intf->intf_vysnc_pulse_width_f0, v_pw * h_total); + + write32(&mdp_intf->intf_disp_v_start_f0, v_start * h_total); + + write32(&mdp_intf->intf_disp_v_end_f0, + (uint32_t)(((uint64_t)v_total * (uint64_t)h_total) - 1ULL)); + + /* same packed value written to both regs (as before) */ + uint32_t disp_hctl = (h_end << 16) | (h_start); + write32(&mdp_intf->intf_disp_hctl, disp_hctl); + write32(&mdp_intf->display_data_hctl, disp_hctl); + + write32(&mdp_intf->polarity_ctl, (m->phsync ? 0x1 : 0x0) | (m->pvsync ? 0x2 : 0x0)); + + write32(&mdp_intf->intf_panel_format, 0x2100); /* Color Format : RGB */ + write32(&mdp_intf->intf_prof_fetch_start, 0); +} + +void intf_fetch_start_config(struct edid *edid) +{ + uint32_t v_total, h_total, fetch_start, vfp_start; + uint32_t prefetch_avail, prefetch_needed; + uint32_t fetch_enable = PROG_FETCH_START_EN; + + /* 2 because of Databus widen, 2 pixels per clock. + HSYNC Period would be divided by 2 */ + uint32_t wide_bus = 2; + + v_total = edid->mode.va + edid->mode.vbl; + + /* Per-pipe horizontal total (match TG programming) */ + if (((edid->mode.ha + edid->mode.hbl) % wide_bus) != 0) + return; + h_total = (edid->mode.ha + edid->mode.hbl) / wide_bus; + + vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso; + + prefetch_avail = v_total - vfp_start; + + if (prefetch_avail >= MDSS_MDP_MAX_PREFILL_FETCH) { + fetch_start = 0; + fetch_enable = 0; + } else { + prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH; + fetch_start = (v_total - prefetch_needed) * h_total + h_total + 1; + fetch_enable = PROG_FETCH_START_EN; + } + + write32(&mdp_intf->intf_prof_fetch_start, fetch_start); + write32(&mdp_intf->intf_config, fetch_enable); +} + +void merge_3d_active(struct edid *edid) +{ + bool dual = (edid->mode.ha > MDSS_MAX_SINGLE_PIPE_PIXEL_WIDTH) || + (calculate_mode_mdp_clk(&edid->mode) > MDSS_MAX_MDP_CLK); + + if (dual) + write32(&mdp_ctl_0->merge_3d_flush, 0x1); + + write32(&mdp_ctl_0->ctl_intf_flush, 0x20); + write32(&mdp_ctl_0->periph_flush, 0x20); + + u32 flush_mask = FLUSH_INTF | FLUSH_PERIPH | FLUSH_CTL | FLUSH_LM0 | FLUSH_VIG0; + + if (dual) + flush_mask |= FLUSH_MERGE_3D | FLUSH_LM1 | FLUSH_VIG1; + + write32(&mdp_ctl_0->ctl_flush, flush_mask); + + write32(&edp_lclk->vsc_db16_db17_db18_pb8, 0x10100); + write32(&edp_lclk->compression_mode_ctrl, 0x2800); + write32(&mdp_intf->intf_config2, 0x111); + write32(&edp_lclk->db_ctrl, 0x01); + write32(&mdp_intf->intf_config, 0x800000); +} diff --git a/src/soc/qualcomm/x1p42100/display/sspp.c b/src/soc/qualcomm/x1p42100/display/sspp.c new file mode 100644 index 00000000000..075b8c5f0f2 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/sspp.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include + +uint32_t calculate_mode_mdp_clk(const struct edid_mode *mode) { + /* pixel clock = total_h * total_v * refresh. Use it for mode_mdp_clock */ + uint64_t mode_mdp_clk = (uint64_t)mode->pixel_clock * 1000; + + /* clock inefficiency factor of 5% */ + mode_mdp_clk *= MDSS_MDP_CLK_FUDGE_FACTOR_NUMER; + mode_mdp_clk /= MDSS_MDP_CLK_FUDGE_FACTOR_DENOM; + + return (uint32_t)mode_mdp_clk; +} + +void mdss_source_pipe_config(struct edid *edid, uintptr_t dram_display) +{ + uint32_t pipe_count = ((edid->mode.ha > MDSS_MAX_SINGLE_PIPE_PIXEL_WIDTH) || + (calculate_mode_mdp_clk(&edid->mode) > MDSS_MAX_MDP_CLK)) ? 2 : 1; + + /* Source Dimensions: Per Pipe */ + uint32_t src_h = edid->mode.va; + uint32_t src_w = (edid->mode.ha) / pipe_count; + uint32_t src_size_val = (src_h << 16) | src_w; + + uint32_t dst_w = src_w; + uint32_t dst_size_val = src_size_val; + + /* Offsets */ + uint32_t start_dst_x = 0; /* X offset here, if applicable */ + uint32_t stride_val = (edid->mode.ha) * 4; + + /* Starting Base Address (VIG_0) */ + uintptr_t current_base = MDP_VP_0_SSPP_BASE; + + for (int i = 0; i < pipe_count; i++) { + struct mdp_sspp_regs *sspp = (struct mdp_sspp_regs *)current_base; + + /* QSEED3 structure at offset 0xA00 (Disabled) */ + struct mdp_qseed3_regs *qseed3 = + (struct mdp_qseed3_regs *)(current_base + 0xA00); + + /* Clock Control at offset 0x1A00 (gate QSEED clock OFF) */ + uint32_t *clk_ctrl = (uint32_t *)(current_base + 0x1A00); + + /* Clock Control: disable QSEED clock (if enabled ?= 2) */ + write32(clk_ctrl, 0); + + /* SSPP Config */ + write32(&sspp->sspp_src0, dram_display); + write32(&sspp->sspp_src1, 0); + write32(&sspp->sspp_src2, 0); + write32(&sspp->sspp_src3, 0); + + write32(&sspp->sspp_src_ystride0, stride_val); + write32(&sspp->sspp_src_ystride1, 0); + + write32(&sspp->sspp_src_format, 0x237FF); + write32(&sspp->sspp_src_unpack_pattern, 0x3020001); + + /* Dual-pipe positioning */ + uint32_t src_x = i * src_w; + uint32_t out_x = start_dst_x + (i * dst_w); + + /* Rectangles */ + write32(&sspp->sspp_src_xy, src_x); + write32(&sspp->sspp_src_size, src_size_val); + + write32(&sspp->sspp_out_xy, out_x); + write32(&sspp->sspp_out_size, dst_size_val); + + /* QSEED3: DISABLE */ + write32(&qseed3->coef_lut_ctrl, 0x0); + write32(&qseed3->op_mode, 0x0); + + /* Pixel Extensions */ + write32(&sspp->sspp_sw_pix_ext_c0_lr, 0); + write32(&sspp->sspp_sw_pix_ext_c0_tb, 0); + write32(&sspp->sspp_sw_pic_ext_c0_req_pixels, src_size_val); + + write32(&sspp->sspp_sw_pix_ext_c1c2_lr, 0); + write32(&sspp->sspp_sw_pix_ext_c1c2_tb, 0); + write32(&sspp->sspp_sw_pic_ext_c1c2_req_pixels, src_size_val); + + write32(&sspp->sspp_sw_pix_ext_c3_lr, 0); + write32(&sspp->sspp_sw_pix_ext_c3_tb, 0); + write32(&sspp->sspp_sw_pic_ext_c3_req_pixels, src_size_val); + + write32(&sspp->sspp_src_op_mode, SW_PIX_EXT_OVERRIDE); + + /* Next pipe base (VIG_0 -> VIG_1) */ + current_base += 0x2000; + } +} + +void mdss_layer_mixer_setup(struct edid *edid) +{ + uint32_t full_w = edid->mode.ha; + uint32_t full_h = edid->mode.va; + bool dual = ((full_w > MDSS_MAX_SINGLE_PIPE_PIXEL_WIDTH) || + (calculate_mode_mdp_clk(&edid->mode) > MDSS_MAX_MDP_CLK)); + uint32_t lm_w = dual ? (full_w / 2) : full_w; + uint32_t lm_out_size = (full_h << 16) | (lm_w & 0xFFFF); + + write32(&mdp_layer_mixer->layer_out_size, lm_out_size); + write32(&mdp_layer_mixer->layer_op_mode, 0x0); + + write32(&mdp_ctl_0->ctl_intf_master, INTF_ACTIVE_5); + write32(&mdp_ctl_0->ctl_intf_active, INTF_ACTIVE_5); + + for (int i = 0; i < 6; i++) { + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100); + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000); + } + + write32(&mdp_ctl_0->ctl_layer0, MDP_CTL_LAYER0_VIG0_STAGE3_CFG); + write32(&mdp_ctl_0->ctl_fetch_pipe_active, FETCH_PIPE_VIG0_ACTIVE); + + if (dual) { + struct mdp_layer_mixer_regs *lm1 = + (struct mdp_layer_mixer_regs *)((uint8_t *)mdp_layer_mixer + 0x1000); + + write32(&lm1->layer_out_size, lm_out_size); + write32(&lm1->layer_op_mode, LM_LAYER_OP_MODE_SPLIT_RIGHT); + + for (int i = 0; i < 6; i++) { + write32(&lm1->layer_blend[i].layer_blend_op, 0x100); + write32(&lm1->layer_blend[i].layer_blend_const_alpha, 0x00ff0000); + } + + write32(&mdp_ctl_0->ctl_layer1, MDP_CTL_LAYER1_VIG1_STAGE3_CFG); + + write32(&mdp_ctl_0->ctl_fetch_pipe_active, + FETCH_PIPE_VIG0_ACTIVE | FETCH_PIPE_VIG1_ACTIVE); + + write32(&mdp_ctl_0->ctl_merge_3d_active, 1); + write32(&mdp_merge_3d_0->mode, 3); + } else { + write32(&mdp_ctl_0->ctl_merge_3d_active, 0); + write32(&mdp_merge_3d_0->mode, 0); + } +} diff --git a/src/soc/qualcomm/x1p42100/display/vbif.c b/src/soc/qualcomm/x1p42100/display/vbif.c new file mode 100644 index 00000000000..34ce7af4264 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/display/vbif.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void configure_vbif_qos(void) +{ + /* Global Inits */ + /* dynamic clock gating enabled */ + write32(&vbif_rt->vbif_clkon, 0x00000000); + + /* DDR AXI max bursts: RD=7+1, WR=7+1 */ + write32(&vbif_rt->vbif_ddr_out_max_burst, 0x00000707); + + /* enable SW override of AOOO per client */ + write32(&vbif_rt->vbif_out_axi_aooo_en, 0x0000FFFF); + + /* force AOOORD/AOOOWR for all clients */ + write32(&vbif_rt->vbif_out_axi_aooo, 0xFFFFFFFF); + + write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333); + write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333); + + write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003); + write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113); + write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224); + write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334); + write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445); + write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776); + write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003); + write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113); + write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224); + write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334); + write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445); + write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776); +} diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h index dc45a668d66..7ed710aaba8 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h +++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h @@ -24,6 +24,16 @@ #define LPASS_AON_CC_BASE (LPASS_BASE + 0x00E08000) #define LPASS_AON_CC_PLL_CM_BASE (LPASS_BASE + 0x00E01000) #define LPASS_CORE_GDSC_REG_BASE (LPASS_BASE + 0x01E00000) +#define LPASS_LPASS_CORE_CC_REG_BASE (LPASS_BASE + 0x01B08000) +#define LPASS_LPICX_NOC_BASE (LPASS_BASE + 0x01430000) +#define LPASS_LPI_TCM_REG_BASE (LPASS_BASE + 0x0126A000) +#define LPASS_MCC_LPASS_REG_BASE (LPASS_BASE + 0x01250000) +#define LPASS_QDSP6SS_PUB_BASE (LPASS_BASE + 0x00800000) +#define LPASS_QDSP6SS_PLL_BASE (LPASS_BASE + 0x00840000) +#define LPASS_QDSP6SS_CORE_CC_BASE (LPASS_BASE + 0x00848000) +#define LPASS_SSC_SCC_BASE (LPASS_BASE + 0x01A01000) + +#define LPASS_EFUSE_Q6SS_BASE (LPASS_BASE + 0x0125B000) #define RPMH_BASE 0x17520000 #define CMD_DB_BASE_ADDR 0x81c60000 @@ -51,6 +61,16 @@ #define GPIO_FUNC_QSPI_DATA_1 GPIO129_FUNC_QSPI0_DATA_1 #define GPIO_FUNC_QSPI_CLK GPIO127_FUNC_QSPI0_CLK +/* PMIC IDs */ +#define PMIC_A_SLAVE_ID 0x00 // PMK8380A +#define PMIC_B_SLAVE_ID 0x01 // PMC8380C +#define PMIC_C_SLAVE_ID 0x02 // PMC8380VE +#define PMIC_D_SLAVE_ID 0x03 // PMC8380VE +#define PMIC_E_SLAVE_ID 0x04 // PMC8380 +#define PMIC_F_SLAVE_ID 0x05 // PMC8380VE +#define PMIC_I_SLAVE_ID 0x08 // PMC8380VE +#define PMIC_J_SLAVE_ID 0x09 // PMC8380VE + /* QUP SERIAL ENGINE BASE ADDRESSES */ /* QUPV3_0 */ #define QUP_SERIAL0_BASE 0x00B80000 @@ -88,6 +108,9 @@ #define QUP_WRAP2_BASE 0x008C0000 #define QUP_2_GSI_BASE 0x00804000 +/* QUPV3_3 - Dummy Entry */ +#define QUP_WRAP3_BASE 0x00000000 + /* USB BASE ADDRESSES */ #define HS_USB_SS0_PHY_BASE 0x00FD3000 #define HS_USB_SS1_PHY_BASE 0x00FD9000 @@ -170,6 +193,7 @@ #define PCIE6A_BQPHY_PCS_PCIE_LANE1 0x01BFFE00 /* TCSR */ +#define TCSR_BASE 0x01FC0000 #define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE ((void *)0x1FD512C) #define TCSR_PCIE_CTRL_4LN_CONFIG_SEL ((void *)0x1FDA000) @@ -212,4 +236,44 @@ enum dload_mode_cookies { #define SPMI_PMIC_ARB_CHANNEL_BASE 0x0C500000 #define SPMI_PMIC_ARB_CHANNEL_SIZE 0x1000 +/* + * APID map entry format (PMIC_ARB_REG_ADDRp) for x1p42100: + * bit 24 : IRQ_OWN + * bits 19:16: SID + * bits 15:8 : ADDRESS (PPID) + * SID+PPID are extracted from addr bits[19:8] directly (no shift needed). + */ +/* ADDR.PPID is 12 bits: SID (19:16) + Periph (15:8) */ +#define SPMI_PPID_FROM_ADDR(a) ((a) & (0xfffU << 8)) +/* REG.PPID is 12 bits: SID (19:16) + Periph (15:8) */ +#define SPMI_PPID_FROM_REG(r) ((r) & (0xfffU << 8)) + +/* MDSS, MDP, EDP & EDP-phy Register bases */ +enum { + MDSS_BASE = 0xAE00000, +}; + +enum { + EDP_CTRL_BASE = 0xAEA0000, + DP_EDP_PHY_BASE = 0xAEC0000, +}; + +enum { + MDP_0_CTL_BASE = MDSS_BASE + 0x16000, + MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000, + MDP_VP_0_LAYER_MIXER_BASE = MDSS_BASE + 0x45000, + MDP_5_INTF_BASE = MDSS_BASE + 0x3A000, + MDP_VBIF_RT_BASE = MDSS_BASE + 0xB0000, + VBIF_NRT_BASE = MDSS_BASE + 0xB8000, + DSI0_CTL_BASE = MDSS_BASE + 0x94000, + DSI0_PHY_BASE = MDSS_BASE + 0x94400, + DSI0_PHY_DLN0_BASE = MDSS_BASE + 0x94600, + DSI0_PHY_DLN1_BASE = MDSS_BASE + 0x94680, + DSI0_PHY_DLN2_BASE = MDSS_BASE + 0x94700, + DSI0_PHY_DLN3_BASE = MDSS_BASE + 0x94780, + DSI0_PHY_CLKLN_BASE = MDSS_BASE + 0x94800, + DSI0_PHY_PLL_QLINK_COM = MDSS_BASE + 0x94a00, + MDP_PERIPH_TOP1 = MDSS_BASE + 0x00013F0, +}; + #endif /* __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/adsp.h b/src/soc/qualcomm/x1p42100/include/soc/adsp.h new file mode 100644 index 00000000000..6c53e49ad8e --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/adsp.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_X1P42100_ADSP_H__ +#define __SOC_QUALCOMM_X1P42100_ADSP_H__ + +#include +#include +#include +#include + +/* ADSP CBFS firmware paths */ +#define ADSP_CBFS_DTBS CONFIG_CBFS_PREFIX "/adsp_dtbs" +#define ADSP_CBFS_FIRMWARE CONFIG_CBFS_PREFIX "/adsp_lite" + +/* LPASS QDSP6SS Register Structure */ +struct x1p42100_lpass_qdsp6ss { + u8 _res0[0x10]; + u32 rst_evb; + u8 _res1[0x18 - 0x14]; + u32 dbg_cfg; + u32 ret_cfg; + u8 _res2[0x60 - 0x20]; + u32 boot_params[6]; + u8 _res3[0x400 - 0x78]; + u32 boot_core_start; + u32 boot_cmd; + u32 boot_status; +}; + +check_member(x1p42100_lpass_qdsp6ss, rst_evb, 0x10); +check_member(x1p42100_lpass_qdsp6ss, dbg_cfg, 0x18); +check_member(x1p42100_lpass_qdsp6ss, boot_params, 0x60); +check_member(x1p42100_lpass_qdsp6ss, boot_core_start, 0x400); +check_member(x1p42100_lpass_qdsp6ss, boot_status, 0x408); + +/* LPASS EFUSE Q6SS Register Structure */ +struct x1p42100_lpass_efuse_q6ss { + u32 evb_sel; + u32 evb_addr; +}; + +check_member(x1p42100_lpass_efuse_q6ss, evb_sel, 0x0); +check_member(x1p42100_lpass_efuse_q6ss, evb_addr, 0x4); + +static struct x1p42100_lpass_qdsp6ss *const lpass_qdsp6ss = (void *)LPASS_QDSP6SS_PUB_BASE; +static struct x1p42100_lpass_efuse_q6ss *const lpass_efuse_q6ss = (void *)LPASS_EFUSE_Q6SS_BASE; + +void adsp_fw_load(void); + +#endif /* __SOC_QUALCOMM_X1P42100_ADSP_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h index c126baac622..fa3fe899ef2 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/clock.h +++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h @@ -19,7 +19,9 @@ #define CLK_37_5MHZ (37.5 * MHz) /* CPU PLL*/ +#define L_VAL_2995P2MHz 0x9C #define L_VAL_1363P2MHz 0x47 +#define L_VAL_710P4MHz 0x25 /* DISP PLL */ #define L_VAL_1725MHz 0x59 @@ -221,6 +223,36 @@ struct x1p42100_lpass_aon_cc_pll_clock { u32 pll_test_ctl_u2; }; +/* LPASS QDSP6SS PLL register structure */ +struct x1p42100_lpass_qdsp6ss_pll_clock { + u32 pll_mode; + u32 pll_opmode; + u32 pll_state; + u32 pll_status; + u32 pll_l_val; + u32 pll_alpha_val; + u32 pll_user_ctl; + u32 pll_user_ctl_u; + u32 pll_config_ctl; + u32 pll_config_ctl_u; + u32 pll_config_ctl_u1; + u32 pll_test_ctl; + u32 pll_test_ctl_u; + u32 pll_test_ctl_u1; + u32 pll_test_ctl_u2; +}; + +/* LPASS QDSP6SS Core CC register structure */ +struct x1p42100_lpass_qdsp6ss_core_cc { + u32 core_cmd_rcgr; + u32 core_cfg_rcgr; + u8 _res0[0x0020 - 0x0008]; + u32 core_cbcr; +}; + +check_member(x1p42100_lpass_qdsp6ss_core_cc, core_cfg_rcgr, 0x0004); +check_member(x1p42100_lpass_qdsp6ss_core_cc, core_cbcr, 0x0020); + /* LPASS Audio CC register structure */ struct x1p42100_lpass_audio_cc { u8 _res0[0x28018]; @@ -275,28 +307,102 @@ struct x1p42100_lpass_core_gdsc { check_member(x1p42100_lpass_core_gdsc, lpass_core_gds_hm_ready, 0x000B8); check_member(x1p42100_lpass_core_gdsc, lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, 0x09000); +/* LPASS Core CC register structure */ +struct x1p42100_lpass_core_cc { + u8 _res0[0x23000]; + u32 lpass_lpass_core_cc_sysnoc_mport_core_cbcr; +}; + +check_member(x1p42100_lpass_core_cc, lpass_lpass_core_cc_sysnoc_mport_core_cbcr, 0x23000); + /* LPASS AON CC register structure */ struct x1p42100_lpass_aon_cc { - u8 _res0[0x9060]; + u8 _res0[0x2000]; + u32 lpass_noc_island_isolation; + u8 _res1[0x801C - 0x2004]; + u32 q6_xo_cbcr; + u8 _res2[0x901C - 0x8020]; + u32 q6_ahbm_cbcr; + u8 _res3[0x9060 - 0x9020]; u32 va_mem0_cbcr; - u8 _res1[0x2c]; + u8 _res4[0x9090 - 0x9064]; u32 lpass_audio_hm_gdscr; - u8 _res2[0x2f6c]; + u8 _res5[0x0A014 - 0x9094]; + u32 pclkdbg_cbcr; + u8 _res6[0x0A020 - 0x0A018]; + u32 at_cbcr; + u8 _res7[0xC000 - 0x0A024]; u32 lpass_hm_collapse_vote_for_q6; - u8 _res3[0x6008]; + u8 _res8[0x1200C - 0xC004]; u32 va_2x_cbcr; - u8 _res4[0x4]; + u8 _res9[0x12014 - 0x12010]; u32 va_cbcr; - u8 _res5[0xffc]; + u8 _res10[0x13014 - 0x12018]; u32 tx_mclk_cbcr; + u8 _res11[0x19008 - 0x13018]; + u32 lpi_noc_hs_cbcr; + u8 _res12[0x1902C - 0x1900C]; + u32 q6_axim_cbcr; }; +check_member(x1p42100_lpass_aon_cc, lpass_noc_island_isolation, 0x02000); +check_member(x1p42100_lpass_aon_cc, q6_xo_cbcr, 0x801C); +check_member(x1p42100_lpass_aon_cc, q6_ahbm_cbcr, 0x901C); check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060); check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090); +check_member(x1p42100_lpass_aon_cc, pclkdbg_cbcr, 0x0A014); +check_member(x1p42100_lpass_aon_cc, at_cbcr, 0x0A020); check_member(x1p42100_lpass_aon_cc, lpass_hm_collapse_vote_for_q6, 0xc000); check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C); check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014); check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014); +check_member(x1p42100_lpass_aon_cc, lpi_noc_hs_cbcr, 0x19008); +check_member(x1p42100_lpass_aon_cc, q6_axim_cbcr, 0x1902C); + +/* LPASS LPICX NOC register structure */ +struct x1p42100_lpass_lpicx_noc { + u8 _res0[0x2040]; + u32 sidebandmanager_chipcx_sbm_faultinen0_low; + u8 _res1[0x6090 - 0x2044]; + u32 sidebandmanager_rcg_sbm_flagoutstatus0_low; +}; + +check_member(x1p42100_lpass_lpicx_noc, sidebandmanager_chipcx_sbm_faultinen0_low, 0x2040); +check_member(x1p42100_lpass_lpicx_noc, sidebandmanager_rcg_sbm_flagoutstatus0_low, 0x6090); + +/* LPASS MCC_LPASS_REG register block */ +struct x1p42100_lpass_mcc_lpass_reg { + u8 _res0[0x18]; + u32 rsc_wait_event_ovrd_mask; + u8 _res1[0x5014 - 0x001c]; + u32 atb_low_power_handshake; + u32 apb_low_power_handshake; + u8 _res2[0x5020 - 0x501c]; + u32 nts_low_power_handshake; + u32 dap_low_power_handshake; +}; + +check_member(x1p42100_lpass_mcc_lpass_reg, rsc_wait_event_ovrd_mask, 0x0018); +check_member(x1p42100_lpass_mcc_lpass_reg, atb_low_power_handshake, 0x5014); +check_member(x1p42100_lpass_mcc_lpass_reg, nts_low_power_handshake, 0x5020); + +/* LPASS SSC_SCC register block */ +struct x1p42100_lpass_ssc_scc { + u8 _res0[0x30]; + u32 ssc_scc_smem_cbcr; +}; + +check_member(x1p42100_lpass_ssc_scc, ssc_scc_smem_cbcr, 0x0030); + +/* LPASS LPI TCM register block */ +struct x1p42100_lpass_lpi_tcm { + u32 tcm_256kb_block_cbcr[10]; + u8 _res0[0x0300 - 0x0028]; + u32 axis_hs_cbcr; +}; + +check_member(x1p42100_lpass_lpi_tcm, tcm_256kb_block_cbcr, 0x0000); +check_member(x1p42100_lpass_lpi_tcm, axis_hs_cbcr, 0x0300); struct x1p42100_disp_cc { uint8_t _res0[0x00C]; @@ -333,7 +439,7 @@ struct x1p42100_disp_cc { uint32_t xo_cbcr; }; -/* Offset checks (relative to DISP_CC_BASE) */ +/* Offset checks */ check_member(x1p42100_disp_cc, mdss_mdp_cbcr, 0x00000C); check_member(x1p42100_disp_cc, mdss_vsync_cbcr, 0x000024); check_member(x1p42100_disp_cc, mdss_dptx3_pixel0_cbcr, 0x000094); @@ -519,82 +625,111 @@ struct x1p42100_gcc { u32 gcc_aggre_usb3_prim_axi_cbcr; u8 _res36[0x42004 - 0x39094]; struct qupv3_clock qup_wrap0_s[8]; - u8 _res37[0x47000 - 0x429c4]; - u32 lpass_cfg_noc_sway_cbcr; - u8 _res38[0x4b000 - 0x47004]; + u8 _res37[0x45150 - 0x429c4]; + /* LPASS boot clock */ + u32 gcc_noc_lpass_dcd_xo_cbcr; + u32 gcc_ddrss_lpass_shub_cbcr; + u8 _res38[0x47000 - 0x45158]; + u32 gcc_lpass_cfg_noc_sway_cbcr; + u32 gcc_qmip_lpass_qtb_ahb_cbcr; + u8 _res39[0x47010 - 0x47008]; + u32 gcc_lpass_aon_noc_ddrss_shub_cbcr; + u32 gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr; + u32 gcc_lpass_hw_af_noc_ddrss_shub_cbcr; + u8 _res40[0x47024 - 0x4701c]; + u32 gcc_lpass_aggre_noc_ddrss_shub_cbcr; + u8 _res41[0x4702c - 0x47028]; + struct clock_rcg lpass_ddrss_shub_rcg; + u8 _res42[0x47160 - 0x47034]; + u32 gcc_cfg_noc_lpass_cbcr; + u8 _res43[0x4b000 - 0x47164]; u32 qspi_bcr; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; struct clock_rcg qspi_core; - u8 _res39[0x50000 - 0x4b014]; + u8 _res44[0x50000 - 0x4b014]; u32 gcc_usb3_phy_prim_bcr; u32 gcc_usb3phy_phy_prim_bcr; - u8 _res40[0x50010 - 0x50008]; + u8 _res45[0x50010 - 0x50008]; u32 gcc_usb4_0_dp0_phy_prim_bcr; - u8 _res41[0x52000 - 0x50014]; + u8 _res46[0x52000 - 0x50014]; u32 apcs_clk_br_en; - u8 _res42[0x52008 - 0x52004]; + u8 _res47[0x52008 - 0x52004]; u32 apcs_clk_br_en1; - u8 _res43[0x52010 - 0x5200c]; + u8 _res48[0x52010 - 0x5200c]; u32 apcs_clk_br_en2; - u8 _res44[0x52018 - 0x52014]; + u8 _res49[0x52018 - 0x52014]; u32 apcs_clk_br_en3; - u8 _res45[0x52020 - 0x5201c]; + u8 _res50[0x52020 - 0x5201c]; u32 apcs_clk_br_en4; - u8 _res46[0x52028 - 0x52024]; + u8 _res51[0x52028 - 0x52024]; u32 apcs_clk_br_en5; - u8 _res47[0x52030 - 0x5202c]; + u8 _res52[0x52030 - 0x5202c]; u32 apcs_pll_br_en; - u8 _res48[0x54000 - 0x52034]; + u8 _res53[0x54000 - 0x52034]; u32 usb3_uniphy_mp1_bcr; u32 usb3uniphy_phy_mp1_bcr; u32 gcc_usb3_mp_ss1_phy_bcr; u32 gcc_usb3_mp_ss1_phy_gdscr; - u8 _res49[0x8e000 - 0x54010]; + u8 _res54[0x55224 - 0x54010]; + u32 gcc_lpass_dsp_gdsc_sleep_ena_vote; + u8 _res55[0x8e000 - 0x55228]; u32 pcie_6_phy_gdscr; - u8 _res50[0xa1000 - 0x8e004]; + u8 _res56[0x99000 - 0x8e004]; + u32 gcc_lpass_qtb_gdscr; + u8 _res57[0x99014 - 0x99004]; + u32 gcc_lpass_qtb_ahb_cbcr; + u32 gcc_lpass_audio_qtb_cbcr; + u8 _res58[0x99024 - 0x9901c]; + u32 gcc_lpass_qosgen_extref_cbcr; + u32 gcc_lpass_qdss_tsctr_cbcr; + u32 gcc_lpass_qtb_at_cbcr; + u32 gcc_lpass_xo_cbcr; + u32 gcc_lpass_pwrctl_cbcr; + u32 gcc_tcu_lpass_audio_qtb_cbcr; + u8 _res59[0xa1000 - 0x9903c]; u32 gcc_usb30_sec_bcr; u32 gcc_usb30_sec_gdscr; - u8 _res51[0xa1018 - 0xa1008]; + u8 _res60[0xa1018 - 0xa1008]; u32 gcc_usb30_sec_master_cbcr; - u8 _res52[0xa1024 - 0xa101c]; + u8 _res61[0xa1024 - 0xa101c]; u32 gcc_usb30_sec_sleep_cbcr; u32 gcc_usb30_sec_mock_utmi_cbcr; struct clock_rcg usb30_sec_master_rcg; - u8 _res53[0xa1060 - 0xa1034]; + u8 _res62[0xa1060 - 0xa1034]; u32 gcc_usb3_sec_phy_aux_cbcr; u32 gcc_usb3_sec_phy_com_aux_cbcr; u32 gcc_usb3_sec_phy_pipe_cbcr; u32 gcc_usb3_sec_phy_pipe_muxr; - u8 _res54[0xa108c - 0xa1070]; + u8 _res63[0xa108c - 0xa1070]; u32 gcc_cfg_noc_usb3_sec_axi_cbcr; u32 gcc_aggre_usb3_sec_axi_cbcr; - u8 _res55[0xa2000 - 0xa1094]; + u8 _res64[0xa2000 - 0xa1094]; u32 gcc_usb30_tert_bcr; u32 gcc_usb30_tert_gdscr; - u8 _res56[0xa2018 - 0xa2008]; + u8 _res65[0xa2018 - 0xa2008]; u32 gcc_usb30_tert_master_cbcr; - u8 _res57[0xa2024 - 0xa201c]; + u8 _res66[0xa2024 - 0xa201c]; u32 gcc_usb30_tert_sleep_cbcr; u32 gcc_usb30_tert_mock_utmi_cbcr; - u8 _res58[0xa2034 - 0xa202c]; + u8 _res67[0xa2034 - 0xa202c]; u32 gcc_usb30_tert_master_m; u32 gcc_usb30_tert_master_n; u32 gcc_usb30_tert_master_d; - u8 _res59[0xa2060 - 0xa2040]; + u8 _res68[0xa2060 - 0xa2040]; u32 gcc_usb3_tert_phy_aux_cbcr; u32 gcc_usb3_tert_phy_com_aux_cbcr; u32 gcc_usb3_tert_phy_pipe_cbcr; u32 gcc_usb3_tert_phy_pipe_muxr; - u8 _res60[0xa208c - 0xa2070]; + u8 _res69[0xa208c - 0xa2070]; u32 gcc_cfg_noc_usb3_tert_axi_cbcr; u32 gcc_aggre_usb3_tert_axi_cbcr; - u8 _res61[0xa3000 - 0xa2094]; + u8 _res70[0xa3000 - 0xa2094]; u32 gcc_usb3_phy_tert_bcr; u32 gcc_usb3phy_phy_tert_bcr; - u8 _res62[0xa3010 - 0xa3008]; + u8 _res71[0xa3010 - 0xa3008]; u32 gcc_usb4_2_dp0_phy_tert_bcr; - u8 _res63[0xac01c - 0xa3014]; + u8 _res72[0xac01c - 0xa3014]; u32 pcie_6a_phy_bcr; }; @@ -643,7 +778,16 @@ check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034); check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2d174); check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2d17c); check_member(x1p42100_gcc, qup_wrap0_s, 0x42004); -check_member(x1p42100_gcc, lpass_cfg_noc_sway_cbcr, 0x47000); +check_member(x1p42100_gcc, gcc_noc_lpass_dcd_xo_cbcr, 0x45150); +check_member(x1p42100_gcc, gcc_ddrss_lpass_shub_cbcr, 0x45154); +check_member(x1p42100_gcc, gcc_lpass_cfg_noc_sway_cbcr, 0x47000); +check_member(x1p42100_gcc, gcc_qmip_lpass_qtb_ahb_cbcr, 0x47004); +check_member(x1p42100_gcc, gcc_lpass_aon_noc_ddrss_shub_cbcr, 0x47010); +check_member(x1p42100_gcc, gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr, 0x47014); +check_member(x1p42100_gcc, gcc_lpass_hw_af_noc_ddrss_shub_cbcr, 0x47018); +check_member(x1p42100_gcc, gcc_lpass_aggre_noc_ddrss_shub_cbcr, 0x47024); +check_member(x1p42100_gcc, lpass_ddrss_shub_rcg, 0x4702c); +check_member(x1p42100_gcc, gcc_cfg_noc_lpass_cbcr, 0x47160); check_member(x1p42100_gcc, qspi_bcr, 0x4b000); check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000); check_member(x1p42100_gcc, apcs_clk_br_en1, 0x52008); @@ -653,6 +797,16 @@ check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020); check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028); check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030); check_member(x1p42100_gcc, pcie_6_phy_gdscr, 0x8e000); +check_member(x1p42100_gcc, gcc_lpass_qtb_gdscr, 0x99000); +check_member(x1p42100_gcc, gcc_lpass_qtb_ahb_cbcr, 0x99014); +check_member(x1p42100_gcc, gcc_lpass_audio_qtb_cbcr, 0x99018); +check_member(x1p42100_gcc, gcc_lpass_qosgen_extref_cbcr, 0x99024); +check_member(x1p42100_gcc, gcc_lpass_qdss_tsctr_cbcr, 0x99028); +check_member(x1p42100_gcc, gcc_lpass_qtb_at_cbcr, 0x9902c); +check_member(x1p42100_gcc, gcc_lpass_xo_cbcr, 0x99030); +check_member(x1p42100_gcc, gcc_lpass_pwrctl_cbcr, 0x99034); +check_member(x1p42100_gcc, gcc_tcu_lpass_audio_qtb_cbcr, 0x99038); +check_member(x1p42100_gcc, gcc_lpass_dsp_gdsc_sleep_ena_vote, 0x55224); check_member(x1p42100_gcc, pcie_6a_phy_bcr, 0xac01c); /* Generic QUPV3 wrapper structure - all wrappers have identical layout */ @@ -866,6 +1020,25 @@ enum clk_lpass { LPASS_CLK_COUNT }; +enum lpass_boot_clk { + DDRSS_LPASS_SHUB_CBCR, + LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR, + LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR, + LPASS_AON_NOC_DDRSS_SHUB_CBCR, + LPASS_AUDIO_QTB_CBCR, + LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR, + LPASS_PWRCTL_CBCR, + LPASS_QDSS_TSCTR_CBCR, + LPASS_QOSGEN_EXTREF_CBCR, + LPASS_QTB_AHB_CBCR, + LPASS_QTB_AT_CBCR, + LPASS_XO_CBCR, + NOC_LPASS_DCD_XO_CBCR, + QMIP_LPASS_QTB_AHB_CBCR, + TCU_LPASS_AUDIO_QTB_CBCR, + LPASS_BOOT_CLK_COUNT +}; + enum subsystem_reset { AOP_RESET_SHFT, CORE_SW_RESET, @@ -892,6 +1065,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type); enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll, u32 l_val, u32 alpha_val); enum cb_err lpass_init(void); +enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val); void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg, uint32_t num_perfs); @@ -916,6 +1090,13 @@ static struct x1p42100_lpass_audio_cc *const lpass_audio_cc = (void *)LPASS_AUDI static struct x1p42100_lpass_aon_cc *const lpass_aon_cc = (void *)LPASS_AON_CC_BASE; static struct x1p42100_lpass_aon_cc_pll_clock *const lpass_aon_cc_pll = (void *)LPASS_AON_CC_PLL_CM_BASE; static struct x1p42100_lpass_core_gdsc *const lpass_core_gdsc = (void *)LPASS_CORE_GDSC_REG_BASE; +static struct x1p42100_lpass_core_cc *const lpass_core_cc = (void *)LPASS_LPASS_CORE_CC_REG_BASE; +static struct x1p42100_lpass_lpicx_noc *const lpass_lpicx_noc = (void *)LPASS_LPICX_NOC_BASE; +static struct x1p42100_lpass_qdsp6ss_pll_clock *const lpass_qdsp6ss_pll = (void *)LPASS_QDSP6SS_PLL_BASE; +static struct x1p42100_lpass_qdsp6ss_core_cc *const lpass_qdsp6ss_core_cc = (void *)LPASS_QDSP6SS_CORE_CC_BASE; +static struct x1p42100_lpass_mcc_lpass_reg *const lpass_mcc_lpass_reg = (void *)LPASS_MCC_LPASS_REG_BASE; +static struct x1p42100_lpass_ssc_scc *const lpass_ssc_scc = (void *)LPASS_SSC_SCC_BASE; +static struct x1p42100_lpass_lpi_tcm *const lpass_lpi_tcm = (void *)LPASS_LPI_TCM_REG_BASE; /* Does nothing */ #define clock_reset_aop() do {} while (0) diff --git a/src/soc/qualcomm/x1p42100/include/soc/cpucp.h b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h index 4aa7384da77..4838b184832 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/cpucp.h +++ b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h @@ -4,6 +4,5 @@ #define _SOC_QUALCOMM_X1P42100_CPUCP_H__ void cpucp_fw_load_reset(void); -void cpucp_prepare(void); #endif // _SOC_QUALCOMM_X1P42100_CPUCP_H__ diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/edp_aux.h b/src/soc/qualcomm/x1p42100/include/soc/display/edp_aux.h new file mode 100644 index 00000000000..e9fe7a0ebf8 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/edp_aux.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EDP_AUX_H +#define _EDP_AUX_H + +#include + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_STATUS 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 +#define REG_EDP_AUX_CTRL (0x00000030) +#define EDP_AUX_CTRL_ENABLE (0x00000001) +#define EDP_AUX_CTRL_RESET (0x00000002) + +#define REG_EDP_AUX_DATA (0x00000034) +#define EDP_AUX_DATA_READ (0x00000001) +#define EDP_AUX_DATA_DATA__MASK (0x0000ff00) +#define EDP_AUX_DATA_DATA__SHIFT (8) + +#define EDP_AUX_DATA_INDEX__MASK (0x00ff0000) +#define EDP_AUX_DATA_INDEX__SHIFT (16) + +#define EDP_AUX_DATA_INDEX_WRITE (0x80000000) + +#define REG_EDP_AUX_TRANS_CTRL (0x00000038) +#define EDP_AUX_TRANS_CTRL_I2C (0x00000100) +#define EDP_AUX_TRANS_CTRL_GO (0x00000200) +#define EDP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400) +#define EDP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) + +#define REG_EDP_TIMEOUT_COUNT (0x0000003C) +#define REG_EDP_AUX_LIMITS (0x00000040) +#define REG_EDP_AUX_STATUS (0x00000044) +#define AUX_CMD_READ (BIT(4)) + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val) +{ + return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK; +} + +static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val) +{ + return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK; +} + +void edp_aux_ctrl(int enable); +int edp_read_edid(struct edid *out); +ssize_t edp_aux_transfer(unsigned int address, u8 request, void *buffer, size_t size); + +#endif diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/edp_ctrl.h b/src/soc/qualcomm/x1p42100/include/soc/display/edp_ctrl.h new file mode 100644 index 00000000000..d5a5a0dc349 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/edp_ctrl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EDP_CTRL_H +#define _EDP_CTRL_H + +#include + +enum cb_err edp_ctrl_init(struct edid *edid); + +void edp_backlight_aux(void); + +#endif diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/edp_link_train.h b/src/soc/qualcomm/x1p42100/include/soc/display/edp_link_train.h new file mode 100644 index 00000000000..34b219b5c21 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/edp_link_train.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* eDP link training register and helper definitions for x1p42100 */ + +#ifndef _EDP_LINK_TRAIN_H_ +#define _EDP_LINK_TRAIN_H_ + +#include + +#define DPCD_LINK_VOLTAGE_MAX 4 +#define DPCD_LINK_PRE_EMPHASIS_MAX 4 +#define MAX_LINK_TRAINING_LOOP 5 +#define DP_LINK_RATE_UNIT_KHZ 27000 + +/* DP_TX Registers */ +#define MAX_16BITS_VALUE ((1 << 16) - 1) /* 16 bits value */ +#define EDP_INTR_AUX_I2C_DONE BIT(3) +#define EDP_INTR_WRONG_ADDR BIT(6) +#define EDP_INTR_TIMEOUT BIT(9) +#define EDP_INTR_NACK_DEFER BIT(12) +#define EDP_INTR_WRONG_DATA_CNT BIT(15) +#define EDP_INTR_I2C_NACK BIT(18) +#define EDP_INTR_I2C_DEFER BIT(21) +#define EDP_INTR_PLL_UNLOCKED BIT(24) +#define EDP_INTR_AUX_ERROR BIT(27) +#define EDP_INTR_READY_FOR_VIDEO BIT(0) +#define EDP_INTR_IDLE_PATTERN_SENT BIT(3) +#define EDP_INTR_FRAME_END BIT(6) +#define EDP_INTR_CRC_UPDATED BIT(9) +#define EDP_INTR_SST_FIFO_UNDERFLOW BIT(28) +#define REG_EDP_DP_HPD_CTRL (0x00000000) +#define EDP_DP_HPD_CTRL_HPD_EN (0x00000001) +#define EDP_DP_HPD_PLUG_INT_ACK (0x00000001) +#define EDP_DP_IRQ_HPD_INT_ACK (0x00000002) +#define EDP_DP_HPD_REPLUG_INT_ACK (0x00000004) +#define EDP_DP_HPD_UNPLUG_INT_ACK (0x00000008) +#define EDP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) +#define EDP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) +#define EDP_DP_HPD_PLUG_INT_MASK (0x00000001) +#define EDP_DP_IRQ_HPD_INT_MASK (0x00000002) +#define EDP_DP_HPD_REPLUG_INT_MASK (0x00000004) +#define EDP_DP_HPD_UNPLUG_INT_MASK (0x00000008) +#define EDP_DP_HPD_INT_MASK \ + (EDP_DP_HPD_PLUG_INT_MASK | EDP_DP_IRQ_HPD_INT_MASK | EDP_DP_HPD_REPLUG_INT_MASK | \ + EDP_DP_HPD_UNPLUG_INT_MASK) +#define EDP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) +#define EDP_DP_HPD_STATE_STATUS_PENDING (0x20000000) +#define EDP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) +#define EDP_DP_HPD_STATE_STATUS_MASK (0xE0000000) +#define EDP_DP_HPD_REFTIMER_ENABLE (1 << 16) +#define EDP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) +#define EDP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) +#define EDP_INTERRUPT_TRANS_NUM (0x000000A0) +#define EDP_MAINLINK_CTRL_ENABLE (0x00000001) +#define EDP_MAINLINK_CTRL_RESET (0x00000002) +#define EDP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) +#define EDP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define EDP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) +#define EDP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) +#define EDP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) +#define EDP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008) +#define EDP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) +#define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040) +#define EDP_CONFIGURATION_CTRL_SEND_VSC (0x00000080) +#define EDP_CONFIGURATION_CTRL_BPC (0x00000100) +#define EDP_CONFIGURATION_CTRL_ASSR (0x00000400) +#define EDP_CONFIGURATION_CTRL_RGB_YUV (0x00000800) +#define EDP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000) +#define EDP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04) +#define EDP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) +#define EDP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) +#define EDP_TOTAL_HOR_VER_HORIZ__MASK (0x0000FFFF) +#define EDP_TOTAL_HOR_VER_HORIZ__SHIFT (0) +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +#define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) +#define DP_FRAMING_CHANGE_CAP (1 << 1) +#define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ +#define EDP_MISC0_SYNCHRONOUS_CLK (0x00000001) +#define EDP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) +#define EDP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) +#define LANE0_MAPPING_SHIFT (0x00000000) +#define LANE1_MAPPING_SHIFT (0x00000002) +#define LANE2_MAPPING_SHIFT (0x00000004) +#define LANE3_MAPPING_SHIFT (0x00000006) +#define EDP_MAINLINK_READY_FOR_VIDEO (0x00000001) +#define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY (0x00000008) +#define EDP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) +#define EDP_LINK_BW_MAX DP_LINK_BW_5_4 +#define DP_RECEIVER_CAP_SIZE 0x0f +#define DP_LINK_STATUS_SIZE 6 +#define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV_10 0x10 +#define DP_DPCD_REV_11 0x11 +#define DP_DPCD_REV_12 0x12 +#define DP_DPCD_REV_13 0x13 +#define DP_DPCD_REV_14 0x14 +#define DP_SET_POWER 0x600 +#define DP_SET_POWER_D0 0x1 +#define DP_SET_POWER_D3 0x2 +#define DP_SET_POWER_MASK 0x3 +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LANE_COUNT 0x002 +#define DP_MAX_LANE_COUNT_MASK 0x1f +#define DP_TPS3_SUPPORTED (1 << 6) +#define DP_ENHANCED_FRAME_CAP (1 << 7) +#define DP_MAX_DOWNSPREAD 0x003 +#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) +#define DP_NORP 0x004 +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +#define DP_DWN_STRM_PORT_PRESENT (1 << 0) +#define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +#define DP_FORMAT_CONVERSION (1 << 3) +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 +#define DP_EDP_CONFIGURATION_CAP 0x00d +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e + +#define DP_SUPPORTED_LINK_RATES 0x0010 +#define DP_EDP_RATE_TABLE_SIZE 16 /* 0x10..0x1F */ +#define DP_LINK_RATE_SET 0x0115 +#define DP_LINK_RATE_SET_MASK 0x07 + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 // Sets link bit rate (e.g. 1.62/2.7/5.4/8.1 Gbps) +#define DP_LINK_RATE_TABLE 0x00 // Selects link rate from eDP 1.4 rate table instead of BW code +#define DP_LINK_BW_1_62 0x06 // Code for 1.62 Gbps link rate +#define DP_LINK_BW_2_7 0x0a // Code for 2.7 Gbps link rate +#define DP_LINK_BW_5_4 0x14 // Code for 5.4 Gbps link rate +#define DP_LINK_BW_8_1 0x1e // Code for 8.1 Gbps link rate + +#define DP_LANE_COUNT_SET 0x101 // Sets number of active lanes and enhanced framing +#define DP_LANE_COUNT_MASK 0x0f // Mask to extract lane-count bits +#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) // Enable enhanced framing + +#define DP_TRAINING_PATTERN_SET 0x102 // Selects link-training_link-quality pattern +#define DP_TRAINING_PATTERN_DISABLE 0 // Disable training pattern (normal operation) +#define DP_TRAINING_PATTERN_1 1 // Enable Training Pattern 1 (CR phase) +#define DP_TRAINING_PATTERN_2 2 // Enable Training Pattern 2 (EQ phase) +#define DP_TRAINING_PATTERN_3 3 // Enable Training Pattern 3 (HBR2/HBR3 EQ) +#define DP_TRAINING_PATTERN_MASK 0x3 // Mask for training pattern bits +#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) // Disable link-quality pattern +#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) // D10.2 compliance / test pattern +#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) // Error-rate measurement pattern +#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) // PRBS7 test pattern +#define DP_LINK_QUAL_PATTERN_MASK (3 << 2) // Mask for link-quality pattern bits +#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) // Enable recovered-clock output +#define DP_LINK_SCRAMBLING_DISABLE (1 << 5) // Disable data scrambling on link + +#define DP_EDP_CONFIGURATION_SET 0x10A // eDP-specific feature configuration +#define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) // Enable alt scrambler reset +#define DP_FRAMING_CHANGE_ENABLE (1 << 1) // Allow dynamic framing changes +#define DP_PANEL_SELF_TEST_ENABLE (1 << 7) // Enable panel self-test mode +#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) // Count both disparity & symbol errors +#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) // Count disparity errors +#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) // Count symbol errors +#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) // Mask for symbol-error count mode + +#define DP_TRAINING_LANE0_SET 0x103 // Lane 0 voltage swing pre-emphasis request +#define DP_TRAINING_LANE1_SET 0x104 // Lane 1 voltage swing pre-emphasis request +#define DP_TRAINING_LANE2_SET 0x105 // Lane 2 voltage swing pre-emphasis request +#define DP_TRAINING_LANE3_SET 0x106 // Lane 3 voltage swing pre-emphasis request + +#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +#define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) +#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) +#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) +#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) +#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) +#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) +#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) +#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) +#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) +#define DP_DOWNSPREAD_CTRL 0x107 +#define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#define DP_SET_ANSI_8B10B (1 << 0) +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +#define DP_LANE_CR_DONE (1 << 0) +#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +#define DP_LANE_SYMBOL_LOCKED (1 << 2) +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | DP_LANE_CHANNEL_EQ_DONE | DP_LANE_SYMBOL_LOCKED) +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 +#define DP_TEST_REQUEST 0x218 +#define DP_TEST_LINK_TRAINING (1 << 0) +#define DP_TEST_LINK_PATTERN (1 << 1) +#define DP_TEST_LINK_EDID_READ (1 << 2) +#define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +#define DP_TEST_LINK_RATE 0x219 +#define DP_LINK_RATE_162 (0x6) +#define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 +#define DP_TEST_PATTERN 0x221 +#define DP_TEST_RESPONSE 0x260 +#define DP_TEST_ACK (1 << 0) +#define DP_TEST_NAK (1 << 1) +#define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_SET_POWER 0x600 +#define DP_SET_POWER_D0 0x1 +#define DP_SET_POWER_D3 0x2 + +/* Link training return value */ +#define EDP_TRAIN_FAIL -1 +#define EDP_TRAIN_SUCCESS 0 +#define EDP_TRAIN_RECONFIG 1 + +#define EDP_INTERRUPT_STATUS_ACK_SHIFT 1 +#define EDP_INTERRUPT_STATUS_MASK_SHIFT 2 + +#define EDP_INTERRUPT_STATUS1 \ + (EDP_INTR_AUX_I2C_DONE | EDP_INTR_WRONG_ADDR | EDP_INTR_TIMEOUT | \ + EDP_INTR_NACK_DEFER | EDP_INTR_WRONG_DATA_CNT | EDP_INTR_I2C_NACK | \ + EDP_INTR_I2C_DEFER | EDP_INTR_PLL_UNLOCKED | EDP_INTR_AUX_ERROR) + +#define EDP_INTERRUPT_STATUS1_ACK (EDP_INTERRUPT_STATUS1 << EDP_INTERRUPT_STATUS_ACK_SHIFT) +#define EDP_INTERRUPT_STATUS1_MASK (EDP_INTERRUPT_STATUS1 << EDP_INTERRUPT_STATUS_MASK_SHIFT) + +#define EDP_INTERRUPT_STATUS2 \ + (EDP_INTR_READY_FOR_VIDEO | EDP_INTR_IDLE_PATTERN_SENT | EDP_INTR_FRAME_END | \ + EDP_INTR_CRC_UPDATED | EDP_INTR_SST_FIFO_UNDERFLOW) + +#define EDP_INTERRUPT_STATUS2_ACK (EDP_INTERRUPT_STATUS2 << EDP_INTERRUPT_STATUS_ACK_SHIFT) +#define EDP_INTERRUPT_STATUS2_MASK (EDP_INTERRUPT_STATUS2 << EDP_INTERRUPT_STATUS_MASK_SHIFT) + +enum edp_color_depth { + EDP_6BIT = 0, + EDP_8BIT = 1, + EDP_10BIT = 2, + EDP_12BIT = 3, + EDP_16BIT = 4, +}; + +struct dp_tu_calc_input { + u64 lclk; /* 162, 270, 540 and 810 MHz*/ + u64 pclk_khz; /* in KHz */ + u64 hactive; /* active h-width */ + u64 hporch; /* bp + fp + pulse */ + int nlanes; /* no.of.lanes */ + int bpp; /* bits */ + int pixel_enc; /* 444, 420, 422 */ + int dsc_en; /* dsc on/off */ + int async_en; /* async mode */ + int fec_en; /* fec */ + int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ + int num_of_dsc_slices; /* number of slices per line */ + s64 comp_bpp; /* compressed bpp = uncomp_bpp / compression_ratio */ + int ppc_div_factor; /* pass in ppc mode 2/4 */ +}; + +struct dp_tu_calc_output { + u32 valid_boundary_link; + u32 delay_start_link; + bool boundary_moderation_en; + u32 valid_lower_boundary_link; + u32 upper_boundary_count; + u32 lower_boundary_count; + u32 tu_size_minus1; +}; + +struct tu_algo_data { + s64 lclk_fp; + s64 orig_lclk_fp; + + s64 pclk_fp; + s64 orig_pclk_fp; + s64 lwidth; + s64 lwidth_fp; + int orig_lwidth; + s64 hbp_relative_to_pclk; + s64 hbp_relative_to_pclk_fp; + int orig_hbp; + int nlanes; + int bpp; + int pixelEnc; + int dsc_en; + int async_en; + int fec_en; + int bpc; + + int rb2; + unsigned int delay_start_link_extra_pixclk; + int extra_buffer_margin; + s64 ratio_fp; + s64 original_ratio_fp; + + s64 err_fp; + s64 n_err_fp; + s64 n_n_err_fp; + int tu_size; + int tu_size_desired; + int tu_size_minus1; + + int valid_boundary_link; + s64 resulting_valid_fp; + s64 total_valid_fp; + s64 effective_valid_fp; + s64 effective_valid_recorded_fp; + int n_tus; + int n_tus_per_lane; + int paired_tus; + int remainder_tus; + int remainder_tus_upper; + int remainder_tus_lower; + int extra_bytes; + int filler_size; + int delay_start_link; + + int extra_pclk_cycles; + int extra_pclk_cycles_in_link_clk; + s64 ratio_by_tu_fp; + s64 average_valid2_fp; + int new_valid_boundary_link; + int remainder_symbols_exist; + int n_symbols; + s64 n_remainder_symbols_per_lane_fp; + s64 last_partial_tu_fp; + s64 TU_ratio_err_fp; + + int n_tus_incl_last_incomplete_tu; + int extra_pclk_cycles_tmp; + int extra_pclk_cycles_in_link_clk_tmp; + int extra_required_bytes_new_tmp; + int filler_size_tmp; + int lower_filler_size_tmp; + int delay_start_link_tmp; + + bool boundary_moderation_en; + int boundary_mod_lower_err; + int upper_boundary_count; + int lower_boundary_count; + int i_upper_boundary_count; + int i_lower_boundary_count; + int valid_lower_boundary_link; + int even_distribution_BF; + int even_distribution_legacy; + int even_distribution; + int hbp_delayStartCheck; + int pre_tu_hw_pipe_delay; + int post_tu_hw_pipe_delay; + int link_config_hactive_time; + int delay_start_link_lclk; + int tu_active_cycles; + s64 parity_symbols; + int resolution_line_time; + int last_partial_lclk; + int min_hblank_violated; + s64 delay_start_time_fp; + s64 hbp_time_fp; + s64 hactive_time_fp; + s64 diff_abs_fp; + int second_loop_set; + s64 ratio; + s64 comp_bpp; + int ppc_div_factor; +}; + +struct edp_ctrl { + /* Link status */ + uint32_t link_rate_khz; + uint8_t link_rate; + uint32_t lane_cnt; + uint8_t v_level; + uint8_t p_level; + + /* eDP rate-table mode ORBs */ + bool use_rate_select; + uint8_t rate_select_idx; /* 0..7 -> DPCD 0x115[2:0] */ + + /* Timing status */ + uint32_t pixel_rate; /* in kHz */ + uint32_t color_depth; +}; + +struct edp_ctrl_tu { + uint32_t tu_size_minus1; /* Desired TU Size */ + uint32_t valid_boundary_link; /* Upper valid boundary */ + uint32_t delay_start_link; /* # of clock cycles to delay */ + bool boundary_moderation_en; /* Enable boundary Moderation? */ + uint32_t valid_lower_boundary_link; /* Valid lower boundary link */ + uint32_t upper_boundary_count; /* Upper boundary Count */ + uint32_t lower_boundary_count; /* Lower boundary Count */ +}; + +int edp_ctrl_on(struct edp_ctrl *ctrl, struct edid *edid, uint8_t *dpcd); +void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid); + +#endif diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/edp_phy.h b/src/soc/qualcomm/x1p42100/include/soc/display/edp_phy.h new file mode 100644 index 00000000000..e98f648c06c --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/edp_phy.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EDP_PHY_H +#define _EDP_PHY_H + +#include + +void edp_phy_config(u8 v_level, u8 p_level, uint32_t link_rate); +void early_phy_enable(void); +int edp_phy_enable(uint32_t link_rate); +int edp_phy_power_on(uint32_t link_rate, unsigned int lane_count); + +#endif diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/edp_reg.h b/src/soc/qualcomm/x1p42100/include/soc/display/edp_reg.h new file mode 100644 index 00000000000..d7425af67fb --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/edp_reg.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EDP_REG_H_ +#define _EDP_REG_H_ + +#include +#include + +struct __packed edp_ahbclk_regs { // 0xAEA0000 + uint32_t hw_version; // 0x0000 + uint32_t reserved0[3]; // 0x0004, 0x0008, 0x000C + uint32_t sw_reset; // 0x0010 + uint32_t phy_ctrl; // 0x0014 + uint32_t clk_ctrl; // 0x0018 + uint32_t clk_active; // 0x001C + uint32_t interrupt_status; // 0x0020 + uint32_t interrupt_status2; // 0x0024 + uint32_t interrupt_status3; // 0x0028 +}; +check_member(edp_ahbclk_regs, sw_reset, 0x10); + +struct __packed edp_auxclk_regs { // 0xAEA0200 + uint32_t hpd_ctrl; // 0x0000 + uint32_t hpd_int_status; // 0x0004 + uint32_t hpd_int_ack; // 0x0008 + uint32_t hpd_int_mask; // 0x000C + uint32_t reserved0[2]; // 0x0010, 0x0014 + uint32_t hpd_reftimer; // 0x0018 + uint32_t hpd_event_time0; // 0x001C + uint32_t hpd_event_time1; // 0x0020 + uint32_t reserved1[3]; // 0x0024, 0x0028, 0x002C + uint32_t aux_ctrl; // 0x0030 + uint32_t aux_data; // 0x0034 + uint32_t aux_trans_ctrl; // 0x0038 + uint32_t timeout_count; // 0x003C + uint32_t aux_limits; // 0x0040 + uint32_t status; // 0x0044 + uint32_t reserved2[22]; // 0x0048 - 0x009C + uint32_t interrupt_trans_num; // 0x00A0 +}; +check_member(edp_auxclk_regs, hpd_reftimer, 0x18); +check_member(edp_auxclk_regs, aux_ctrl, 0x30); +check_member(edp_auxclk_regs, interrupt_trans_num, 0xa0); + +struct __packed edp_lclk_regs { // 0xAEA0400 + uint32_t mainlink_ctrl; // 0x0000 + uint32_t state_ctrl; // 0x0004 + uint32_t configuration_ctrl; // 0x0008 + uint32_t top_bot_interlaced_num_of_lanes; // 0x000C + uint32_t software_mvid; // 0x0010 + uint32_t reserved0; // 0x0014 + uint32_t software_nvid; // 0x0018 + uint32_t total_hor_ver; // 0x001C + uint32_t start_hor_ver_from_sync; // 0x0020 + uint32_t hysnc_vsync_width_polarity; // 0x0024 + uint32_t active_hor_ver; // 0x0028 + uint32_t misc1_misc0; // 0x002C + uint32_t valid_boundary; // 0x0030 + uint32_t valid_boundary2; // 0x0034 + uint32_t logcial2physical_lane_mapping; // 0x0038 + uint32_t reserved1; // 0x003C + uint32_t mainlink_ready; // 0x0040 + uint32_t mainlink_levels; // 0x0044 + uint32_t mainlink_levels2; // 0x0048 + uint32_t tu; // 0x004C + uint32_t db_ctrl; // 0x0050 + uint32_t compliance_scramble_rest; // 0x0054 + uint32_t phy_bist_lane0_cfg; // 0x0058 + + uint32_t reserved2[72]; // 0x005C .. 0x0178 + + uint32_t vsc_db16_db17_db18_pb8; // 0x017C (abs 0xAEA057C) + uint32_t compression_mode_ctrl; // 0x0180 (abs 0xAEA0580) +}; +check_member(edp_lclk_regs, tu, 0x4C); + +struct __packed edp_p0clk_regs { // 0xAEA1000 + uint32_t bist_enable; // 0x0000 + uint32_t reserved0[3]; // 0x0004, 0x0008, 0x000C + uint32_t timing_engine_en; // 0x0010 + uint32_t intf_config; // 0x0014 + uint32_t hsync_ctl; // 0x0018 + uint32_t vsync_period_f0; // 0x001C + uint32_t vsync_period_f1; // 0x0020 + uint32_t vsync_pulse_width_f0; // 0x0024 + uint32_t vsync_pulse_width_f1; // 0x0028 + uint32_t display_v_start_f0; // 0x002C + uint32_t display_v_start_f1; // 0x0030 + uint32_t display_v_end_f0; // 0x0034 + uint32_t display_v_end_f1; // 0x0038 + uint32_t active_v_start_f0; // 0x003C + uint32_t active_v_start_f1; // 0x0040 + uint32_t active_v_end_f0; // 0x0044 + uint32_t active_v_end_f1; // 0x0048 + uint32_t display_hctl; // 0x004C + uint32_t active_hctl; // 0x0050 + uint32_t hsync_skew; // 0x0054 + uint32_t polarity_ctl; // 0x0058 + uint32_t reserved1; // 0x005C + uint32_t tpg_main_control; // 0x0060 + uint32_t tpg_video_config; // 0x0064 + uint32_t tpg_component_limits; // 0x0068 + uint32_t tpg_rectangle; // 0x006C + uint32_t tpg_initial_value; // 0x0070 + uint32_t tpg_color_changing_frames; // 0x0074 + uint32_t tpg_rgb_mapping; // 0x0078 + uint32_t dsc_dto; // 0x007C + uint32_t rgb_mapping; // 0x0080 + uint32_t dsc_dto_count; // 0x0084 + uint32_t async_fifo_config; // 0x0088 +}; +check_member(edp_p0clk_regs, dsc_dto, 0x7c); + +struct __packed edp_phy_regs { // 0xAEC5A00 + uint32_t revision_id0; // 0x0000 + uint32_t revision_id1; // 0x0004 + uint32_t revision_id2; // 0x0008 + uint32_t revision_id3; // 0x000C + uint32_t cfg; // 0x0010 + uint32_t cfg1; // 0x0014 + uint32_t cfg2; // 0x0018 + uint32_t pd_ctl; // 0x001C + uint32_t mode; // 0x0020 + uint32_t aux_cfg[13]; // 0x0024 - 0x0054 + uint32_t aux_interrupt_mask; // 0x0058 + uint32_t aux_interrupt_clr; // 0x005C + uint32_t aux_bist_cfg; // 0x0060 + uint32_t aux_bist_prbs_seed; // 0x0064 + uint32_t aux_bist_prbs_poly; // 0x0068 + uint32_t aux_tx_prog_pat_16b_lsb; // 0x006C + uint32_t aux_tx_prog_pat_16b_msb; // 0x0070 + uint32_t vco_div; // 0x0074 + uint32_t tsync_ovrd; // 0x0078 + uint32_t tx0_tx1_lane_ctl; // 0x007C + uint32_t tx0_tx1_bist_cfg[4]; // 0x0080 - 0x008C + uint32_t tx0_tx1_prbs_seed_byte0; // 0x0090 + uint32_t tx0_tx1_prbs_seed_byte1; // 0x0094 + uint32_t tx0_tx1_bist_pattern0; // 0x0098 + uint32_t tx0_tx1_bist_pattern1; // 0x009C + uint32_t tx2_tx3_lane_ctl; // 0x00A0 + uint32_t tx2_tx3_bist_cfg[4]; // 0x00A4 - 0x00B0 + uint32_t tx2_tx3_prbs_seed_byte0; // 0x00B4 + uint32_t tx2_tx3_prbs_seed_byte1; // 0x00B8 + uint32_t tx2_tx3_bist_pattern0; // 0x00BC + uint32_t tx2_tx3_bist_pattern1; // 0x00C0 + uint32_t misr_ctl; // 0x00C4 + uint32_t debug_bus_sel; // 0x00C8 + uint32_t spare[4]; // 0x00CC - 0x00D8 + uint32_t aux_interrupt_status; // 0x00DC + uint32_t status; // 0x00E0 +}; +check_member(edp_phy_regs, status, 0xE0); + +struct __packed edp_phy_lane_regs { // 0xAEC5200 + uint32_t tx_clk_buf_enable; // 0x00 + uint32_t tx_emp_post1_lvl; // 0x04 + uint32_t tx_post2_emph; // 0x08 + uint32_t tx_boost_lvl_up_dn; // 0x0C + uint32_t tx_idle_lvl_large_amp; // 0x10 + uint32_t tx_drv_lvl; // 0x14 + uint32_t tx_drv_lvl_offset; // 0x18 + uint32_t tx_reset_tsync_en; // 0x1C + uint32_t tx_pre_emph; // 0x20 + uint32_t tx_interface_select; // 0x24 + uint32_t tx_tx_band; // 0x28 + uint32_t tx_slew_cntl; // 0x2C + uint32_t tx_lpb0_cfg[3]; // 0x30, 0x34, 0x38 + uint32_t tx_rescode_lane_tx; // 0x3C + uint32_t tx_rescode_lane_tx1; // 0x40 + uint32_t tx_rescode_lane_offset_tx0; // 0x44 + uint32_t tx_rescode_lane_offset_tx1; // 0x48 + uint32_t tx_serdes_byp_en_out; // 0x4C + uint32_t tx_dbg_bus_sel; // 0x50 + uint32_t tx_transceiver_bias_en; // 0x54 + uint32_t tx_highz_drvr_en; // 0x58 + uint32_t tx_tx_pol_inv; // 0x5C + uint32_t tx_parrate_rec_detect_idle_en; // 0x60 + uint32_t tx_lane_mode1; // 0x64 + uint32_t tx_lane_mode2; // 0x68 + uint32_t tx_atb_sel1; // 0x6C + uint32_t tx_atb_sel2; // 0x70 + uint32_t tx_reset_gen_muxes; // 0x74 + uint32_t tx_tran_drvr_emp_en; // 0x78 + uint32_t tx_vmode_ctrl1; // 0x7C + uint32_t tx_lane_dig_config; // 0x80 + uint32_t tx_ldo_config; // 0x84 + uint32_t tx_dig_bkup_ctrl; // 0x88 +}; +check_member(edp_phy_lane_regs, tx_dig_bkup_ctrl, 0x88); + +struct __packed edp_phy_pll_regs { // 0xAEC5000 + uint32_t qserdes_com_ssc_step_size1_mode1; // 0x00 + uint32_t qserdes_com_ssc_step_size2_mode1; // 0x04 + uint32_t qserdes_com_ssc_step_size3_mode1; // 0x08 + uint32_t qserdes_com_clk_ep_div_mode1; // 0x0C + uint32_t qserdes_com_cp_ctrl_mode1; // 0x10 + uint32_t qserdes_com_pll_rctrl_mode1; // 0x14 + uint32_t qserdes_com_pll_cctrl_mode1; // 0x18 + uint32_t qserdes_com_coreclk_div_mode1; // 0x1C + uint32_t qserdes_com_lock_cmp1_mode1; // 0x20 + uint32_t qserdes_com_lock_cmp2_mode1; // 0x24 + uint32_t qserdes_com_dec_start_mode1; // 0x28 + uint32_t qserdes_com_dec_start_msb_mode1; // 0x2C + uint32_t qserdes_com_div_frac_start1_mode1; // 0x30 + uint32_t qserdes_com_div_frac_start2_mode1; // 0x34 + uint32_t qserdes_com_div_frac_start3_mode1; // 0x38 + uint32_t qserdes_com_hsclk_sel; // 0x3C + uint32_t qserdes_com_integloop_gain0_mode1; // 0x40 + uint32_t qserdes_com_integloop_gain1_mode1; // 0x44 + uint32_t qserdes_com_vco_tune1_mode1; // 0x48 + uint32_t qserdes_com_vco_tune2_mode1; // 0x4C + uint32_t qserdes_com_bin_vcocal_cmp_code1_mode1; // 0x50 + uint32_t qserdes_com_bin_vcocal_cmp_code2_mode1; // 0x54 + uint32_t qserdes_com_bin_vcocal_cmp_code1_mode0; // 0x58 + uint32_t qserdes_com_bin_vcocal_cmp_code2_mode0; // 0x5C + uint32_t qserdes_com_ssc_step_size1_mode0; // 0x60 + uint32_t qserdes_com_ssc_step_size2_mode0; // 0x64 + uint32_t qserdes_com_ssc_step_size3_mode0; // 0x68 + uint32_t qserdes_com_clk_ep_div_mode0; // 0x6C + uint32_t qserdes_com_cp_ctrl_mode0; // 0x70 + uint32_t qserdes_com_pll_rctrl_mode0; // 0x74 + uint32_t qserdes_com_pll_cctrl_mode0; // 0x78 + uint32_t qserdes_com_coreclk_div_mode0; // 0x7C + uint32_t qserdes_com_lock_cmp1_mode0; // 0x80 + uint32_t qserdes_com_lock_cmp2_mode0; // 0x84 + uint32_t qserdes_com_dec_start_mode0; // 0x88 + uint32_t qserdes_com_dec_start_msb_mode0; // 0x8C + uint32_t qserdes_com_div_frac_start1_mode0; // 0x90 + uint32_t qserdes_com_div_frac_start2_mode0; // 0x94 + uint32_t qserdes_com_div_frac_start3_mode0; // 0x98 + uint32_t qserdes_com_hsclk_hs_switch_sel; // 0x9C + uint32_t qserdes_com_integloop_gain0_mode0; // 0xA0 + uint32_t qserdes_com_integloop_gain1_mode0; // 0xA4 + uint32_t qserdes_com_vco_tune1_mode0; // 0xA8 + uint32_t qserdes_com_vco_tune2_mode0; // 0xAC + uint32_t qserdes_com_atb_sel1; // 0xB0 + uint32_t qserdes_com_atb_sel2; // 0xB4 + uint32_t qserdes_com_freq_update; // 0xB8 + uint32_t qserdes_com_bg_timer; // 0xBC + uint32_t qserdes_com_ssc_en_center; // 0xC0 + uint32_t qserdes_com_ssc_adj_per1; // 0xC4 + uint32_t qserdes_com_ssc_adj_per2; // 0xC8 + uint32_t qserdes_com_ssc_per1; // 0xCC + uint32_t qserdes_com_ssc_per2; // 0xD0 + uint32_t qserdes_com_post_div; // 0xD4 + uint32_t qserdes_com_post_div_mux; // 0xD8 + uint32_t qserdes_com_bias_en_clkbuflr_en; // 0xDC + uint32_t qserdes_com_clk_enable1; // 0xE0 + uint32_t qserdes_com_sys_clk_ctrl; // 0xE4 + uint32_t qserdes_com_sysclk_buf_enable; // 0xE8 + uint32_t qserdes_com_pll_en; // 0xEC + uint32_t qserdes_com_debug_bus_ovrd; // 0xF0 + uint32_t qserdes_com_pll_ivco; // 0xF4 + uint32_t qserdes_com_pll_ivco_mode1; // 0xF0 + uint32_t qserdes_com_cmn_iterim; // 0xFC + uint32_t qserdes_com_cmn_iptrim; // 0x100 + uint32_t qserdes_com_ep_clk_detect_ctrl; // 0x104 + uint32_t qserdes_com_pll_cntrl; // 0x108 + uint32_t qserdes_com_bias_en_ctrl_by_psm; // 0x10C + uint32_t qserdes_com_sysclk_en_sel; // 0x110 + uint32_t qserdes_com_cml_sysclk_sel; // 0x114 + uint32_t qserdes_com_resetsm_cntrl; // 0x118 + uint32_t qserdes_com_resetsm_cntrl2; // 0x11C + uint32_t qserdes_com_lock_cmp_en; // 0x120 + uint32_t qserdes_com_lock_cmp_cfg; // 0x124 + uint32_t qserdes_com_integloop_initval; // 0x128 + uint32_t qserdes_com_integloop_en; // 0x12C + uint32_t qserdes_com_integloop_p_path_gain0; // 0x130 + uint32_t qserdes_com_integloop_p_path_gain1; // 0x134 + uint32_t qserdes_com_vcoval_deadman_ctrl; // 0x138 + uint32_t qserdes_com_vco_tune_ctrl; // 0x13C + uint32_t qserdes_com_vco_tune_map; // 0x140 + uint32_t qserdes_com_vco_tune_initval1; // 0x144 + uint32_t qserdes_com_vco_tune_initval2; // 0x148 + uint32_t qserdes_com_vco_tune_minval1; // 0x14C + uint32_t qserdes_com_vco_tune_minval2; // 0x150 + uint32_t qserdes_com_vco_tune_maxval1; // 0x154 + uint32_t qserdes_com_vco_tune_maxval2; // 0x158 + uint32_t qserdes_com_vco_tune_timer1; // 0x15C + uint32_t qserdes_com_vco_tune_timer2; // 0x160 + uint32_t qserdes_com_clk_sel; // 0x164 + uint32_t qserdes_com_pll_analog; // 0x168 + uint32_t qserdes_com_sw_reset; // 0x16C + uint32_t qserdes_com_core_clk_en; // 0x170 + uint32_t qserdes_com_cmn_config; // 0x174 + uint32_t qserdes_com_cmn_rate_override; // 0x178 + uint32_t qserdes_com_svs_mode_clk_sel; // 0x17C + uint32_t qserdes_com_debug_bus_sel; // 0x180 + uint32_t qserdes_com_cmn_misc1; // 0x184 + uint32_t qserdes_com_cmn_mode; // 0x188 + uint32_t qserdes_com_cmn_mode_contd; // 0x18C + uint32_t qserdes_com_cmn_mode_contd1; // 0x190 + uint32_t qserdes_com_cmn_mode_contd2; // 0x194 + uint32_t qserdes_com_vco_dc_level_ctrl; // 0x198 + uint32_t qserdes_com_bin_vcocal_hsclk_sel_1; // 0x19C + uint32_t qserdes_com_additional_ctrl_1; // 0x1A0 + uint32_t qserdes_com_auto_gain_adj_ctrl_1; // 0x1A4 + uint32_t qserdes_com_auto_gain_adj_ctrl_2; // 0x1A8 + uint32_t qserdes_com_auto_gain_adj_ctrl_3; // 0x1AC + uint32_t qserdes_com_auto_gain_adj_ctrl_4; // 0x1B0 + uint32_t qserdes_com_additional_misc; // 0x1B4 + uint32_t qserdes_com_additional_misc_2; // 0x1B8 + uint32_t qserdes_com_additional_misc_3; // 0x1BC + uint32_t qserdes_com_additional_misc_4; // 0x1C0 + uint32_t qserdes_com_additional_misc_5; // 0x1C4 + uint32_t qserdes_com_mode_operation_status; // 0x1C8 + uint32_t qserdes_com_sysclk_det_comp_status; // 0x1CC + uint32_t qserdes_com_cmn_status; // 0x1D0 + uint32_t qserdes_com_reset_sm_status; // 0x1D4 + uint32_t qserdes_com_restrim_code_status; // 0x1D8 + uint32_t qserdes_com_pllcal_code1_status; // 0x1DC + uint32_t qserdes_com_pllcal_code2_status; // 0x1E0 + uint32_t qserdes_com_integloop_bincode_status; // 0x1E4 + uint32_t qserdes_com_debug_bus0; // 0x1E8 + uint32_t qserdes_com_debug_bus1; // 0x1EC + uint32_t qserdes_com_debug_bus2; // 0x1F0 + uint32_t qserdes_com_debug_bus3; // 0x1E4 + uint32_t qserdes_com_c_ready_status; // 0x1F8 +}; +check_member(edp_phy_pll_regs, qserdes_com_bias_en_clkbuflr_en, 0xdc); +check_member(edp_phy_pll_regs, qserdes_com_cmn_status, 0x1D0); +check_member(edp_phy_pll_regs, qserdes_com_c_ready_status, 0x1F8); + +/* EDP_STATE_CTRL */ +enum { + SW_LINK_TRAINING_PATTERN1 = BIT(0), + SW_LINK_TRAINING_PATTERN2 = BIT(1), + SW_LINK_TRAINING_PATTERN3 = BIT(2), + SW_LINK_TRAINING_PATTERN4 = BIT(3), + SW_LINK_SYMBOL_ERROR_RATE_MEASUREMENT = BIT(4), + SW_LINK_PRBS7 = BIT(5), + SW_LINK_TEST_CUSTOM_80BIT_PATTERN = BIT(6), + SW_SEND_VIDEO = BIT(7), + SW_PUSH_IDLE = BIT(8), +}; + +/* EDP_PHY_AUX_INTERRUPT_CLEAR */ +enum { + RX_STOP_ERR = BIT(0), + RX_DEC_ERR = BIT(1), + RX_SYNC_ERR = BIT(2), + RX_ALIGN_ERR = BIT(3), + TX_REQ_ERR = BIT(4), + GLOBE_REQ_CLR = BIT(5), +}; + +enum { + eDP_SAFE_EXIT_LVL_LANE1 = 14, + eDP_SAFE_EXIT_LVL_LANE2 = 8, + eDP_SAFE_EXIT_LVL_LANE4 = 5, +}; + +enum { + COLOR_DEPTH_6BPC = 6, + COLOR_DEPTH_8BPC = 8, + COLOR_DEPTH_10BPC = 10, +}; + +enum { + EDP_AHBCLK_BASE = EDP_CTRL_BASE, + EDP_AUXCLK_BASE = EDP_CTRL_BASE + 0x200, + EDP_LCLK_BASE = EDP_CTRL_BASE + 0x400, + EDP_P0CLK_BASE = EDP_CTRL_BASE + 0x1000, + EDP_PHY_BASE = DP_EDP_PHY_BASE + 0x5A00, + EDP_PHY_LANE_TX0_BASE = DP_EDP_PHY_BASE + 0x5200, + EDP_PHY_LANE_TX1_BASE = DP_EDP_PHY_BASE + 0x5600, + EDP_PHY_PLL_BASE = DP_EDP_PHY_BASE + 0x5000, +}; + +static struct edp_ahbclk_regs *const edp_ahbclk = (void *)EDP_AHBCLK_BASE; +static struct edp_auxclk_regs *const edp_auxclk = (void *)EDP_AUXCLK_BASE; +static struct edp_lclk_regs *const edp_lclk = (void *)EDP_LCLK_BASE; +static struct edp_p0clk_regs *const edp_p0clk = (void *)EDP_P0CLK_BASE; +static struct edp_phy_regs *const edp_phy = (void *)EDP_PHY_BASE; +static struct edp_phy_lane_regs *const edp_phy_lane_tx0 = (void *)EDP_PHY_LANE_TX0_BASE; +static struct edp_phy_lane_regs *const edp_phy_lane_tx1 = (void *)EDP_PHY_LANE_TX1_BASE; +static struct edp_phy_pll_regs *const edp_phy_pll = (void *)EDP_PHY_PLL_BASE; + +#endif diff --git a/src/soc/qualcomm/x1p42100/include/soc/display/mdssreg.h b/src/soc/qualcomm/x1p42100/include/soc/display/mdssreg.h new file mode 100644 index 00000000000..df3aa690f01 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/display/mdssreg.h @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0-only +#ifndef _SOC_DISPLAY_MDSS_REG_H_ +#define _SOC_DISPLAY_MDSS_REG_H_ + +#include +#include +#include + +#define INTF_FLUSH INTF_FLUSH_5 + +#define MDSS_MAX_SINGLE_PIPE_PIXEL_WIDTH 2560U +#define MDSS_MAX_MDP_CLK 575000000U +#define MDSS_MDP_CLK_FUDGE_FACTOR_NUMER 105U +#define MDSS_MDP_CLK_FUDGE_FACTOR_DENOM 100U + +#ifndef WRITE32_LOG +#define WRITE32_LOG(addr, val) \ + do { \ + uintptr_t __addr_tmp = (uintptr_t)(addr); \ + uint32_t __val_tmp = (uint32_t)(val); \ + write32((void *)__addr_tmp, __val_tmp); \ + printk(BIOS_DEBUG, "[%s:%d] write32 addr=%p val=0x%X\n", __func__, __LINE__, \ + (void *)__addr_tmp, (unsigned int)__val_tmp); \ + } while (0) +#endif + +struct dsi_regs { + uint32_t hw_version; + uint32_t ctrl; + uint32_t reserved0[2]; + uint32_t video_mode_ctrl; + uint32_t reserved1[4]; + uint32_t video_mode_active_h; + uint32_t video_mode_active_v; + uint32_t video_mode_active_total; + uint32_t video_mode_active_hsync; + uint32_t video_mode_active_vsync; + uint32_t video_mode_active_vsync_vpos; + uint32_t cmd_mode_dma_ctrl; + uint32_t cmd_mode_mdp_ctrl; + uint32_t cmd_mode_mdp_dcs_cmd_ctrl; + uint32_t dma_cmd_offset; + uint32_t dma_cmd_length; + uint32_t reserved2[2]; + uint32_t cmd_mode_mdp_stream0_ctrl; + uint32_t cmd_mode_mdp_stream0_total; + uint32_t cmd_mode_mdp_stream1_ctrl; + uint32_t cmd_mode_mdp_stream1_total; + uint32_t reserved4[7]; + uint32_t trig_ctrl; + uint32_t reserved5[2]; + uint32_t cmd_mode_dma_sw_trigger; + uint32_t reserved6[3]; + uint32_t misr_cmd_ctrl; + uint32_t misr_video_ctrl; + uint32_t lane_status; + uint32_t lane_ctrl; + uint32_t reserved7[3]; + uint32_t hs_timer_ctrl; + uint32_t timeout_status; + uint32_t clkout_timing_ctrl; + uint32_t eot_packet; + uint32_t eot_packet_ctrl; + uint32_t reserved8[15]; + uint32_t err_int_mask0; + uint32_t int_ctrl; + uint32_t iobist_ctrl; + uint32_t soft_reset; + uint32_t clk_ctrl; + uint32_t reserved9[15]; + uint32_t test_pattern_gen_ctrl; + uint32_t reserved10[7]; + uint32_t test_pattern_gen_cmd_dma_init_val; + uint32_t reserved11[14]; + uint32_t cmd_mode_mdp_ctrl2; + uint32_t reserved12[12]; + uint32_t tpg_dma_fifo_reset; + uint32_t reserved13[44]; + uint32_t video_compression_mode_ctrl; + uint32_t video_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl; + uint32_t cmd_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl3; +}; + +check_member(dsi_regs, video_mode_active_h, 0x24); +check_member(dsi_regs, cmd_mode_mdp_stream0_ctrl, 0x58); +check_member(dsi_regs, trig_ctrl, 0x84); +check_member(dsi_regs, cmd_mode_dma_sw_trigger, 0x90); +check_member(dsi_regs, misr_cmd_ctrl, 0xA0); +check_member(dsi_regs, hs_timer_ctrl, 0xBC); +check_member(dsi_regs, err_int_mask0, 0x10C); +check_member(dsi_regs, test_pattern_gen_ctrl, 0x15C); +check_member(dsi_regs, test_pattern_gen_cmd_dma_init_val, 0x17C); +check_member(dsi_regs, cmd_mode_mdp_ctrl2, 0x1B8); +check_member(dsi_regs, tpg_dma_fifo_reset, 0x1EC); +check_member(dsi_regs, video_compression_mode_ctrl, 0x2A0); + +struct dsi_phy_regs { + uint32_t phy_cmn_revision_id0; + uint32_t reserved0[3]; + uint32_t phy_cmn_clk_cfg0; + uint32_t phy_cmn_clk_cfg1; + uint32_t phy_cmn_glbl_ctrl; + uint32_t phy_cmn_rbuf_ctrl; + uint32_t phy_cmn_vreg_ctrl; + uint32_t phy_cmn_ctrl0; + uint32_t phy_cmn_ctrl1; + uint32_t phy_cmn_ctrl2; + uint32_t phy_cmn_lane_cfg0; + uint32_t phy_cmn_lane_cfg1; + uint32_t phy_cmn_pll_ctrl; + uint32_t reserved1[23]; + uint32_t phy_cmn_dsi_lane_ctrl0; + uint32_t reserved2[4]; + uint32_t phy_cmn_timing_ctrl[12]; + uint32_t reserved3[4]; + uint32_t phy_cmn_phy_status; + uint32_t reserved4[68]; + struct { + uint32_t dln0_cfg[4]; + uint32_t dln0_test_datapath; + uint32_t dln0_pin_swap; + uint32_t dln0_hstx_str_ctrl; + uint32_t dln0_offset_top_ctrl; + uint32_t dln0_offset_bot_ctrl; + uint32_t dln0_lptx_str_ctrl; + uint32_t dln0_lprx_ctrl; + uint32_t dln0_tx_dctrl; + uint32_t reserved5[20]; + } phy_ln_regs[5]; +}; + +check_member(dsi_phy_regs, phy_cmn_clk_cfg0, 0x10); +check_member(dsi_phy_regs, phy_cmn_dsi_lane_ctrl0, 0x98); +check_member(dsi_phy_regs, phy_cmn_timing_ctrl[0], 0xAC); +check_member(dsi_phy_regs, phy_cmn_phy_status, 0xEC); +check_member(dsi_phy_regs, phy_ln_regs[0], 0x200); +check_member(dsi_phy_regs, phy_ln_regs[1], 0x280); +check_member(dsi_phy_regs, phy_ln_regs[2], 0x300); +check_member(dsi_phy_regs, phy_ln_regs[3], 0x380); +check_member(dsi_phy_regs, phy_ln_regs[4], 0x400); + +struct dsi_phy_pll_qlink_regs { + uint32_t pll_analog_ctrls_one; + uint32_t pll_analog_ctrls_two; + uint32_t pll_int_loop_settings; + uint32_t pll_int_loop_settings_two; + uint32_t pll_analog_ctrls_three; + uint32_t pll_analog_ctrls_four; + uint32_t pll_int_loop_ctrls; + uint32_t pll_dsm_divider; + uint32_t pll_feedback_divider; + uint32_t pll_system_muxes; + uint32_t pll_freq_update_ctrl_overrides; + uint32_t pll_cmode; + uint32_t pll_cal_settings; + uint32_t pll_band_sel_cal_timer_low; + uint32_t pll_band_sel_cal_timer_high; + uint32_t pll_band_sel_cal_settings; + uint32_t pll_band_sel_min; + uint32_t pll_band_sel_max; + uint32_t pll_band_sel_pfilt; + uint32_t pll_band_sel_ifilt; + uint32_t pll_band_sel_cal_settings_two; + uint32_t pll_band_sel_cal_settings_three; + uint32_t pll_band_sel_cal_settings_four; + uint32_t pll_band_sel_icode_high; + uint32_t pll_band_sel_icode_low; + uint32_t pll_freq_detect_settings_one; + uint32_t pll_freq_detect_thresh; + uint32_t pll_freq_det_refclk_high; + uint32_t pll_freq_det_refclk_low; + uint32_t pll_freq_det_pllclk_high; + uint32_t pll_freq_det_pllclk_low; + uint32_t pll_pfilt; + uint32_t pll_ifilt; + uint32_t pll_pll_gain; + uint32_t pll_icode_low; + uint32_t pll_icode_high; + uint32_t pll_lockdet; + uint32_t pll_outdiv; + uint32_t pll_fastlock_ctrl; + uint32_t pll_pass_out_override_one; + uint32_t pll_pass_out_override_two; + uint32_t pll_core_override; + uint32_t pll_core_input_override; + uint32_t pll_rate_change; + uint32_t pll_digital_timers; + uint32_t pll_digital_timers_two; + uint32_t pll_decimal_div_start; + uint32_t pll_frac_div_start_low; + uint32_t pll_frac_div_start_mid; + uint32_t pll_frac_div_start_high; + uint32_t pll_dec_frac_muxes; + uint32_t pll_decimal_div_start_1; + uint32_t pll_frac_div_start_low1; + uint32_t pll_frac_div_start_mid1; + uint32_t pll_frac_div_start_high1; + uint32_t reserve0[4]; + uint32_t pll_mash_ctrl; + uint32_t reserved1[6]; + uint32_t pll_ssc_mux_ctrl; + uint32_t pll_ssc_stepsize_low1; + uint32_t pll_ssc_stepsize_high1; + uint32_t pll_ssc_div_per_low_1; + uint32_t pll_ssc_div_per_high_1; + uint32_t pll_ssc_adjper_low_1; + uint32_t pll_ssc_adjper_high_1; + uint32_t reserved2[6]; + uint32_t pll_ssc_ctrl; + uint32_t pll_outdiv_rate; + uint32_t pll_lockdet_rate[2]; + uint32_t pll_prop_gain_rate[2]; + uint32_t pll_band_set_rate[2]; + uint32_t pll_gain_ifilt_band[2]; + uint32_t pll_fl_int_gain_pfilt_band[2]; + uint32_t pll_pll_fastlock_en_band; + uint32_t reserved9[3]; + uint32_t pll_freq_tune_accum_init_mux; + uint32_t pll_lock_override; + uint32_t pll_lock_delay; + uint32_t pll_lock_min_delay; + uint32_t pll_clock_inverters; + uint32_t pll_spare_and_jpc_overrides; + uint32_t pll_bias_ctrl_1; + uint32_t pll_bias_ctrl_2; + uint32_t pll_alog_obsv_bus_ctrl_1; + uint32_t pll_common_status_one; +}; + +check_member(dsi_phy_pll_qlink_regs, pll_mash_ctrl, 0xEC); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_mux_ctrl, 0x108); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_ctrl, 0x13C); +check_member(dsi_phy_pll_qlink_regs, pll_freq_tune_accum_init_mux, 0x17C); + +// MDSS_BASE + 0x3A000 (0xAE3A000) +struct mdp_intf_regs { + uint32_t timing_eng_enable; // 0x000 + uint32_t intf_config; // 0x004 + uint32_t intf_hsync_ctl; // 0x008 + uint32_t intf_vysnc_period_f0; // 0x00C + uint32_t intf_vysnc_period_f1; // 0x010 + uint32_t intf_vysnc_pulse_width_f0; // 0x014 + uint32_t intf_vysnc_pulse_width_f1; // 0x018 + uint32_t intf_disp_v_start_f0; // 0x01C + uint32_t intf_disp_v_start_f1; // 0x020 + uint32_t intf_disp_v_end_f0; // 0x024 + uint32_t intf_disp_v_end_f1; // 0x028 + uint32_t intf_active_v_start_f0; // 0x02C + uint32_t intf_active_v_start_f1; // 0x030 + uint32_t intf_active_v_end_f0; // 0x034 + uint32_t intf_active_v_end_f1; // 0x038 + uint32_t intf_disp_hctl; // 0x03C + uint32_t intf_active_hctl; // 0x040 + uint32_t intf_border_color; // 0x044 + uint32_t intf_underflow_color; // 0x048 + uint32_t hsync_skew; // 0x04C + uint32_t polarity_ctl; // 0x050 + uint32_t test_ctl; // 0x054 + uint32_t tp_color0; // 0x058 + uint32_t tp_color1; // 0x05C + uint32_t intf_config2; // 0x060 + uint32_t display_data_hctl; // 0x064 + uint32_t reserved0[10]; // 0x068-0x08C + uint32_t intf_panel_format; // 0x090 + uint32_t reserved1[55]; // 0x094-0x16C + uint32_t intf_prof_fetch_start; // 0x170 + uint32_t reserved2a[20]; // 0x174-0x1C0 + uint32_t intf_intr_status; // 0x1C4 + uint32_t intf_intr_clear; // 0x1C8 + uint32_t reserved2b[9]; // 0x1CC-0x1EC + uint32_t throttling_count; // 0x1F0 + uint32_t throttling_count_msb; // 0x1F4 + uint32_t reserved2c[2]; // 0x1F8-0x1FC + uint32_t wd_timer_0_ltj_ctl; // 0x200 + uint32_t wd_timer_0_ltj_ctl_1; // 0x204 + uint32_t wd_timer_0_main_max_status; // 0x208 + uint32_t reserved2d[1]; // 0x20C + uint32_t vsync_timestamp_ctrl; // 0x210 + uint32_t vsync_timestamp0; // 0x214 + uint32_t vsync_timestamp1; // 0x218 + uint32_t mdp_vsync_timestamp0; // 0x21C + uint32_t mdp_vsync_timestamp1; // 0x220 + uint32_t wd_timer_0_jitter_ctl; // 0x224 + uint32_t wd_timer_0_ltj_slope; // 0x228 + uint32_t wd_timer_0_ltj_max; // 0x22C + uint32_t wd_timer_0_ctl; // 0x230 + uint32_t wd_timer_0_ctl2; // 0x234 + uint32_t wd_timer_0_load_value; // 0x238 + uint32_t wd_timer_0_status_value; // 0x23C + uint32_t wd_timer_0_ltj_int_status; // 0x240 + uint32_t wd_timer_0_ltj_frac_status; // 0x244 + uint32_t wd_timer_0_lfsr_status; // 0x248 + uint32_t edp_psr_override2; // 0x24C + uint32_t prog_line_intr_conf; // 0x250 + uint32_t edp_psr_update_ctrl; // 0x254 + uint32_t edp_psr_override; // 0x258 + uint32_t intf_mux; // 0x25C +}; + +check_member(mdp_intf_regs, intf_panel_format, 0x90); +check_member(mdp_intf_regs, intf_prof_fetch_start, 0x170); +check_member(mdp_intf_regs, intf_mux, 0x25C); + +// Base: MDP_0_CTL_BASE = 0xAE16000 +struct mdp_ctl_regs { + uint32_t ctl_layer0; // 0x000 + uint32_t ctl_layer1; // 0x004 + uint32_t layer_2; // 0x008 + uint32_t layer_3; // 0x00C + uint32_t layer_4; // 0x010 + uint32_t ctl_top; // 0x014 + uint32_t ctl_flush; // 0x018 + uint32_t ctl_start; // 0x01C + uint32_t pad0[1]; // 0x020 + uint32_t layer_5; // 0x024 + uint32_t pad1[2]; // 0x028-0x02C + uint32_t sw_reset; // 0x030 + uint32_t pad2[2]; // 0x034-0x038 + uint32_t ltm_start_dep; // 0x03C + uint32_t ctl_layer_0_ext; // 0x040 + uint32_t ctl_layer_1_ext; // 0x044 + uint32_t layer_2_ext; // 0x048 + uint32_t layer_3_ext; // 0x04C + uint32_t layer_4_ext; // 0x050 + uint32_t layer_5_ext; // 0x054 + uint32_t pad3[2]; // 0x058-0x05C + uint32_t sw_reset_override; // 0x060 + uint32_t ctl_status; // 0x064 + uint32_t sw_reset_ctrl; // 0x068 + uint32_t pad4[1]; // 0x06C + uint32_t ctl_layer_0_ext2; // 0x070 + uint32_t ctl_layer_1_ext2; // 0x074 + uint32_t layer_2_ext2; // 0x078 + uint32_t layer_3_ext2; // 0x07C + uint32_t layer_4_ext2; // 0x080 + uint32_t layer_5_ext2; // 0x084 + uint32_t pad5[2]; // 0x088-0x08C + uint32_t flush_mask; // 0x090 + uint32_t null_flush_status; // 0x094 + uint32_t null_flush_clear; // 0x098 + uint32_t flush_complete; // 0x09C + uint32_t layer_0_ext3; // 0x0A0 + uint32_t layer_1_ext3; // 0x0A4 + uint32_t layer_2_ext3; // 0x0A8 + uint32_t layer_3_ext3; // 0x0AC + uint32_t layer_4_ext3; // 0x0B0 + uint32_t layer_5_ext3; // 0x0B4 + uint32_t ctl_layer_0_ext4; // 0x0B8 + uint32_t ctl_layer_1_ext4; // 0x0BC + uint32_t layer_2_ext4; // 0x0C0 + uint32_t layer_3_ext4; // 0x0C4 + uint32_t layer_4_ext4; // 0x0C8 + uint32_t layer_5_ext4; // 0x0CC + uint32_t ctl_prepare; // 0x0D0 + uint32_t lut_dma_trigger; // 0x0D4 + uint32_t lut_dma_queue_0_flush_ctrl; // 0x0D8 + uint32_t lut_dma_queue_1_flush_ctrl; // 0x0DC + uint32_t lut_dma_start_dep; // 0x0E0 + uint32_t ctl_merge_3d_active; // 0x0E4 + uint32_t dsc_active; // 0x0E8 + uint32_t wb_active; // 0x0EC + uint32_t cwb_active; // 0x0F0 + uint32_t ctl_intf_active; // 0x0F4 + uint32_t ctl_cdm_active; // 0x0F8 + uint32_t ctl_fetch_pipe_active; // 0x0FC + uint32_t merge_3d_flush; // 0x100 + uint32_t dsc_flush; // 0x104 + uint32_t wb_flush; // 0x108 + uint32_t cwb_flush; // 0x10C + uint32_t ctl_intf_flush; // 0x110 + uint32_t cdm_flush; // 0x114 + uint32_t lut_dma_sb_flush_ctrl; // 0x118 + uint32_t pad6[3]; // 0x11C-0x124 + uint32_t periph_flush; // 0x128 + uint32_t pad7[2]; // 0x12C-0x130 + uint32_t ctl_intf_master; // 0x134 + uint32_t uidle_active; // 0x138 + uint32_t dspp_0_flush; // 0x13C + uint32_t dspp_1_flush; // 0x140 + uint32_t dspp_2_flush; // 0x144 + uint32_t dspp_3_flush; // 0x148 + uint32_t dspp_4_flush; // 0x14C + uint32_t merge_3d_flush_complete; // 0x150 + uint32_t dsc_flush_complete; // 0x154 + uint32_t cwb_flush_complete; // 0x158 + uint32_t intf_flush_complete; // 0x15C + uint32_t periph_flush_complete; // 0x160 + uint32_t wb_flush_complete; // 0x164 +}; + +check_member(mdp_ctl_regs, ctl_top, 0x14); +check_member(mdp_ctl_regs, ctl_intf_active, 0xF4); +check_member(mdp_ctl_regs, ctl_intf_flush, 0x110); +check_member(mdp_ctl_regs, ctl_intf_master, 0x134); + +// 0xAE4F000 +struct mdp_merge_3d_regs { + uint32_t reserved0; + uint32_t mode; // 0x004 +}; + +struct mdp_layer_mixer_regs { + uint32_t layer_op_mode; // 0x000 + uint32_t layer_out_size; // 0x004 + uint32_t layer_border_color_0; // 0x008 + uint32_t layer_border_color_1; // 0x00C + uint32_t layer_config_0x10; // 0x010 + uint32_t reserved0[3]; // 0x014, 0x018, 0x01C + struct { + uint32_t layer_blend_op; // 0x00 + uint32_t layer_blend_const_alpha; // 0x04 + uint32_t layer_blend_fg_color_fill_color0; // 0x08 + uint32_t layer_blend_fg_color_fill_color1; // 0x0C + uint32_t layer_blend_fg_fill_size; // 0x10 + uint32_t layer_blend_fg_fill_xy; // 0x14 + } layer_blend[6]; // 0x020 start, array of 6 stages (0..5) +}; + +struct mdp_sspp_regs { // MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000 + uint32_t sspp_src_size; // 0x0000 + uint32_t sspp_src_img_size; // 0x0004 + uint32_t sspp_src_xy; // 0x0008 + uint32_t sspp_out_size; // 0x000C + uint32_t sspp_out_xy; // 0x0010 + uint32_t sspp_src0; // 0x0014 + uint32_t sspp_src1; // 0x0018 + uint32_t sspp_src2; // 0x001C + uint32_t sspp_src3; // 0x0020 + uint32_t sspp_src_ystride0; // 0x0024 + uint32_t sspp_src_ystride1; // 0x0028 + uint32_t sspp_tile_frame_size; // 0x002C + uint32_t sspp_src_format; // 0x0030 + uint32_t sspp_src_unpack_pattern; // 0x0034 + uint32_t sspp_src_op_mode; // 0x0038 + uint32_t reserved0_a[9]; // 0x003C-0x05F + uint32_t sspp_danger_lut; // 0x0060 + uint32_t sspp_safe_lut; // 0x0064 + uint32_t reserved0_b[1]; // 0x0068 + uint32_t sspp_qos_ctrl; // 0x006C + uint32_t reserved0_c[1]; // 0x0070 + uint32_t sspp_creq_lut_0; // 0x0074 + uint32_t sspp_creq_lut_1; // 0x0078 + uint32_t reserved0_d[33]; // 0x007C-0x0FF + uint32_t sspp_sw_pix_ext_c0_lr; // 0x0100 + uint32_t sspp_sw_pix_ext_c0_tb; // 0x0104 + uint32_t sspp_sw_pic_ext_c0_req_pixels; // 0x0108 + uint32_t reserved1[1]; // 0x010C + uint32_t sspp_sw_pix_ext_c1c2_lr; // 0x0110 + uint32_t sspp_sw_pix_ext_c1c2_tb; // 0x0114 + uint32_t sspp_sw_pic_ext_c1c2_req_pixels; // 0x0118 + uint32_t reserved2[1]; // 0x011C + uint32_t sspp_sw_pix_ext_c3_lr; // 0x0120 + uint32_t sspp_sw_pix_ext_c3_tb; // 0x0124 + uint32_t sspp_sw_pic_ext_c3_req_pixels; // 0x0128 +}; + +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128); + +// Defined relative to Pipe Base + 0xA00 +struct mdp_qseed3_regs { + uint32_t reserved_0; // 0xA00 + uint32_t op_mode; // 0xA04 + uint32_t reserved_1[2]; // 0xA08-0xA0C + uint32_t phase_step_y_h; // 0xA10 + uint32_t phase_step_y_v; // 0xA14 + uint32_t phase_step_uv_h; // 0xA18 + uint32_t phase_step_uv_v; // 0xA1C + uint32_t preload; // 0xA20 + uint32_t reserved_2[7]; // 0xA24-0xA3F + uint32_t src_size_y_rgb_a; // 0xA40 + uint32_t src_size_uv; // 0xA44 + uint32_t dst_size; // 0xA48 + uint32_t coef_lut_ctrl; // 0xA4C + uint32_t reserved_3[16]; // 0xA50-0xA8F + uint32_t phase_init_y_h; // 0xA90 + uint32_t phase_init_y_v; // 0xA94 + uint32_t phase_init_uv_h; // 0xA98 + uint32_t phase_init_uv_v; // 0xA9C + uint32_t reserved_4[24]; // 0xAA0-0xAFF + uint32_t coef_lut_data[33]; // 0xB00-0xB80 +}; + +struct mdss_hw_regs { + uint32_t hw_version; +}; + +check_member(mdss_hw_regs, hw_version, 0x0); + +struct vbif_rt_regs { + uint32_t _rsvd_0000; // 0x0000 + uint32_t vbif_clkon; // 0x0004 + uint32_t _rsvd_0008_00D4[(0x00D8 - 0x0008) / 4]; // 0x0008-0x00D4 + uint32_t vbif_ddr_out_max_burst; // 0x00D8 + uint32_t _rsvd_00DC_0120[(0x0124 - 0x00DC) / 4]; // 0x00DC-0x0120 + uint32_t vbif_round_robin_qos_arb; // 0x0124 + uint32_t _rsvd_0128_015C[(0x0160 - 0x0128) / 4]; // 0x0128-0x015C + uint32_t vbif_out_axi_amemtype_conf0; // 0x0160 + uint32_t vbif_out_axi_amemtype_conf1; // 0x0164 + uint32_t _rsvd_0168_016C[(0x0170 - 0x0168) / 4]; // 0x0168-0x016C + uint32_t vbif_out_axi_ashared; // 0x0170 + uint32_t vbif_out_axi_innershared; // 0x0174 + uint32_t vbif_out_axi_aooo_en; // 0x0178 + uint32_t vbif_out_axi_aooo; // 0x017C + uint32_t _rsvd_0180_054C[(0x0550 - 0x0180) / 4]; // 0x0180-0x054C + struct { + uint32_t vbif_xinl_qos_rp_remap; // 0x0550 + idx*0x8 + uint32_t vbif_xinh_qos_rp_remap; // 0x0554 + idx*0x8 + } qos_rp_remap[8]; + struct { + uint32_t vbif_xinl_qos_lvl_remap; // 0x0590 + idx*0x8 + uint32_t vbif_xinh_qos_lvl_remap; // 0x0594 + idx*0x8 + } qos_lvl_remap[8]; +}; + +struct vbif_nrt_regs { + uint32_t _rsvd_0000; // 0x0000 + uint32_t vbif_clkon; // 0x0004 + uint32_t vbif_clk_force_ctrl0; // 0x0008 + uint32_t vbif_clk_force_ctrl1; // 0x000C + uint32_t vbif_qos_override_en; // 0x0010 + uint32_t vbif_prilvl_act_prop_en; // 0x0014 + uint32_t vbif_qos_override_reqpri0; // 0x0018 + uint32_t _rsvd_001C; // 0x001C + uint32_t vbif_qos_override_prilvl0; // 0x0020 + uint32_t _rsvd_0024_00A8[(0x00AC - 0x0024) / 4]; // 0x0024-0x00A8 + uint32_t vbif_write_gather_en; // 0x00AC + uint32_t vbif_in_rd_lim_conf0; // 0x00B0 + uint32_t _rsvd_00B4_00BC[(0x00C0 - 0x00B4) / 4]; // 0x00B4-0x00BC + uint32_t vbif_in_wr_lim_conf0; // 0x00C0 + uint32_t _rsvd_00C4_00CC[(0x00D0 - 0x00C4) / 4]; // 0x00C4-0x00CC + uint32_t vbif_out_rd_lim_conf0; // 0x00D0 + uint32_t vbif_out_wr_lim_conf0; // 0x00D4 + uint32_t vbif_ddr_out_max_burst; // 0x00D8 + uint32_t _rsvd_00DC_00EC[(0x00F0 - 0x00DC) / 4]; // 0x00DC-0x00EC + uint32_t vbif_arb_ctl; // 0x00F0 + uint32_t vbif_ddr_arb_conf0; // 0x00F4 + uint32_t _rsvd_00F8_00FC[(0x0100 - 0x00F8) / 4]; // 0x00F8-0x00FC + uint32_t vbif_fixed_arb_conf0; // 0x0100 + uint32_t _rsvd_0104; // 0x0104 + uint32_t vbif_arb_lcb; // 0x0108 + uint32_t _rsvd_010C_0120[(0x0124 - 0x010C) / 4]; // 0x010C-0x0120 + uint32_t vbif_round_robin_qos_arb; // 0x0124 + uint32_t _rsvd_0128_015C[(0x0160 - 0x0128) / 4]; // 0x0128-0x015C + uint32_t vbif_out_axi_amemtype_conf0; // 0x0160 + uint32_t vbif_out_axi_amemtype_conf1; // 0x0164 + uint32_t vbif_out_axi_ainst_override_en; // 0x0168 + uint32_t vbif_out_axi_ainst; // 0x016C + uint32_t vbif_out_axi_ashared; // 0x0170 + uint32_t vbif_out_axi_innershared; // 0x0174 + uint32_t vbif_out_axi_aooo_en; // 0x0178 + uint32_t vbif_out_axi_aooo; // 0x017C +}; + +check_member(vbif_rt_regs, vbif_out_axi_amemtype_conf0, 0x160); +check_member(vbif_rt_regs, qos_rp_remap[0], 0x550); + +struct mdp_periph_top1_regs { + /* 0x000-0x014: reserved area up to first known register */ + uint32_t reserved_000[0x018u / 4]; // 0x000-0x014 + + /* 0x018: HDMI/DP core select */ + uint32_t hdmi_dp_core_select; // 0x018 + + /* 0x01C-0x090: reserved area until HPD select */ + uint32_t reserved_01C[(0x094u - (0x018u + 4)) / 4]; + + /* 0x094: DP HPD select */ + uint32_t dp_hpd_select; // 0x094 +}; + +enum { + INTF = BIT(31), + PERIPH = BIT(30), + CWB = BIT(28), + ROT = BIT(27), + CDM_0 = BIT(26), + DMA_3 = BIT(25), + DMA_2 = BIT(24), + MERGE_3D = BIT(23), + DSC = BIT(22), + DSPP_3 = BIT(21), + LAYER_MIXER_5 = BIT(20), + DSPP_PA_LUTV_3 = BIT(19), + VIG_3 = BIT(18), + CTL = BIT(17), + WB = BIT(16), + DSPP_2 = BIT(15), + DSPP_1 = BIT(14), + DSPP_0 = BIT(13), + DMA_1 = BIT(12), + DMA_0 = BIT(11), + LAYER_MIXER_4 = BIT(10), + LAYER_MIXER_3 = BIT(9), + LAYER_MIXER_2 = BIT(8), + LAYER_MIXER_1 = BIT(7), + LAYER_MIXER_0 = BIT(6), + DSPP_PA_LUTV_2 = BIT(5), + DSPP_PA_LUTV_1 = BIT(4), + DSPP_PA_LUTV_0 = BIT(3), + VIG_2 = BIT(2), + VIG_1 = BIT(1), + VIG_0 = BIT(0), +}; + +enum { + DSI_AHBS_HCLK_ON = BIT(0), + DSI_AHBM_SCLK_ON = BIT(1), + DSI_PCLK_ON = BIT(2), + DSI_DSICLK_ON = BIT(3), + DSI_BYTECLK_ON = BIT(4), + DSI_ESCCLK_ON = BIT(5), + DSI_FORCE_ON_DYN_AHBS_HCLK = BIT(8), + DSI_FORCE_ON_DYN_AHBM_HCLK = BIT(9), + DSI_FORCE_ON_DYN_DSICLK = BIT(10), + DSI_FORCE_ON_DYN_BYTECLK = BIT(11), + DSI_AHBS_HCLK_HYSTERISIS1_CTRL = (3 << 11), + DSI_AHBM_HCLK_HYSTERISIS1_CTRL = (3 << 13), + DSI_DSICLK_HYSTERISIS1_CTRL = (3 << 15), + DSI_FORCE_ON_DYN_PCLK = BIT(20), + DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK = BIT(21), + DSI_DMA_CLK_STOP = BIT(22), +}; + +enum { + DSI_CMD_MODE_DMA_DONE_AK = BIT(0), + DSI_CMD_MODE_DMA_DONE_STAT = BIT(0), + DSI_CMD_MODE_DMA_DONE_MASK = BIT(1), + DSI_CMD_MODE_MDP_DONE_AK = BIT(8), + DSI_CMD_MODE_MDP_DONE_STAT = BIT(8), + DSI_CMD_MODE_MDP_DONE_MASK = BIT(9), + DSI_CMD_MDP_STREAM0_DONE_AK = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_STAT = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_MASK = BIT(11), + DSI_VIDEO_MODE_DONE_AK = BIT(16), + DSI_VIDEO_MODE_DONE_STAT = BIT(16), + DSI_VIDEO_MODE_DONE_MASK = BIT(17), + DSI_BTA_DONE_AK = BIT(20), + DSI_BTA_DONE_STAT = BIT(20), + DSI_BTA_DONE_MASK = BIT(21), + DSI_ERROR_AK = BIT(24), + DSI_ERROR_STAT = BIT(24), + DSI_ERROR_MASK = BIT(25), + DSI_DYNAMIC_BLANKING_DMA_DONE_AK = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_STAT = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_MASK = BIT(27), + DSI_DYNAMIC_REFRESH_DONE_AK = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_STAT = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_MASK = BIT(29), + DSI_DESKEW_DONE_AK = BIT(30), + DSI_DESKEW_DONE_STAT = BIT(30), + DSI_DESKEW_DONE_MASK = BIT(31), +}; + +enum { + WR_MEM_START = 255, + WR_MEM_CONTINUE = 255 << 8, + INSERT_DCS_COMMAND = BIT(16), +}; + +enum { + PACKET_TYPE = BIT(24), + POWER_MODE = BIT(26), + EMBEDDED_MODE = BIT(28), + WC_SEL = BIT(29), + BROADCAST_MASTER = BIT(30), + BROADCAST_EN = BIT(31), +}; + +enum { + BWC_DEC_EN = BIT(0), + SW_PIX_EXT_OVERRIDE = BIT(31), +}; + +enum { + INTERLACE_MODE = BIT(0), + REPEAT_PIXEL = BIT(1), + INTERLACE_INIT_SEL = BIT(2), + BORDER_ENABLE = BIT(3), + EDP_PSR_OVERRIDE_EN = BIT(7), + PACK_ALIGN = BIT(10), + DSI_VIDEO_STOP_MODE = BIT(23), + ACTIVE_H_EN = BIT(29), + ACTIVE_V_EN = BIT(30), + PROG_FETCH_START_EN = BIT(31), +}; + +enum { + VIG_0_OUT = BIT(0), + VIG_1_OUT = BIT(0), + BORDER_OUT = BIT(24), +}; + +enum { + FETCH_PIPE_VIG0_ACTIVE = BIT(16), + FETCH_PIPE_VIG1_ACTIVE = BIT(17), +}; + +enum { + INTF_ACTIVE_0 = BIT(0), + INTF_ACTIVE_1 = BIT(1), + INTF_ACTIVE_5 = BIT(5), +}; + +enum { + INTF_FLUSH_0 = BIT(0), + INTF_FLUSH_1 = BIT(1), + INTF_FLUSH_5 = BIT(5), +}; + +enum mdss_flush_bits { + FLUSH_INTF = BIT(31), + FLUSH_PERIPH = BIT(30), + FLUSH_MERGE_3D = BIT(23), + FLUSH_CTL = BIT(17), + FLUSH_LM1 = BIT(7), + FLUSH_LM0 = BIT(6), + FLUSH_VIG1 = BIT(1), + FLUSH_VIG0 = BIT(0), +}; + +#define MDP_CTL_LAYER_VIG0_OUT_SHIFT 0 +#define MDP_CTL_LAYER_VIG1_OUT_SHIFT 3 +#define MDP_CTL_LAYER_BORDER_OUT BIT(24) +#define MDP_LM_STAGE3_FG 0x5 + +#define MDP_CTL_LAYER0_VIG0_STAGE3_CFG \ + ((MDP_LM_STAGE3_FG << MDP_CTL_LAYER_VIG0_OUT_SHIFT) | \ + MDP_CTL_LAYER_BORDER_OUT) + +#define MDP_CTL_LAYER1_VIG1_STAGE3_CFG \ + ((MDP_LM_STAGE3_FG << MDP_CTL_LAYER_VIG1_OUT_SHIFT) | \ + MDP_CTL_LAYER_BORDER_OUT) + +#define LM_LAYER_OP_MODE_SPLIT_RIGHT BIT(31) + +enum { + MDSS_HW_REG_BASE = MDSS_BASE + 0x00000000, + MDSS_HW_REG_BASE_SIZE = 0x1000, + MDSS_HW_REG_BASE_USED = 0x154, + MDSS_HW_REG_BASE_OFFS = 0x00000000, +}; +enum edp_init_values { + EDP_HPD_INT_ACK_CLEAR_ALL = 0x0000000F, // Clear any pending HPD interrupts + EDP_AUX_CTRL_ENABLE_BASIC = 0x00000011, // AUX_CTRL = 0x11 + EDP_AUX_CTRL_ENABLE_RST = 0x00000013, // AUX_CTRL = 0x13 (AUX reset toggle) + EDP_HPD_REFTIMER_ENABLE_0013 = 0x00010013, // REFTIMER_ENABLE + interval + EDP_HPD_CTRL_ENABLE = 0x00000001, // Enable HPD logic with default polarity + MDP_DP_HPD_SELECT_HPDDPT3 = 0x00000322, // Select HPDDPT3 + MDP_HDMI_DP_CORE_SELECT_DP = 0x00000001, // Select DP core + EDP_AUX_TIMEOUT_COUNT_FFFF = 0x0000FFFF, // Timeout count + EDP_AUX_LIMITS_FFFF = 0x0000FFFF, // Retry, NACK/DEFER, read-zero limits + READ_WAIT2_WR_WAIT1 = 0x00000012, + AHB2EDPPHY_AHB2PHY_AHB2PHY_TOP_CFG = 0xAEC6010, +}; + +#define MDP_SSPP_TOP0_REG_BASE (MDSS_BASE + 0x00001000) +#define HWIO_MDP_INTR_EN_ADDR (MDP_SSPP_TOP0_REG_BASE + 0x10) // 0xAE01010 +#define HWIO_MDP_INTR_STATUS_ADDR (MDP_SSPP_TOP0_REG_BASE + 0x14) // 0xAE01014 +#define HWIO_MDP_INTR_CLEAR_ADDR (MDP_SSPP_TOP0_REG_BASE + 0x18) // 0xAE01018 +#define HWIO_MDP_INTR_EN_INTF_5_VSYNC_BMSK 0x800000 +#define HWIO_MDP_INTR_EN_PING_PONG_0_DONE_BMSK 0x100 + +#define GPIO_PANEL_POWER_ON GPIO(70) // INTERNAL_EDP_REG_EN_GPIO +#define GPIO_PANEL_HPD GPIO(119) // INTERNAL_EDP_HPD_GPIO + +static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE; +static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE; +static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM; + +static struct mdp_intf_regs *const mdp_intf = (void *)MDP_5_INTF_BASE; +static struct mdp_ctl_regs *const mdp_ctl_0 = (void *)MDP_0_CTL_BASE; +static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE; +static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE; +static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE; +static struct mdp_merge_3d_regs *const mdp_merge_3d_0 = (void *)0xAE4F000; +static struct vbif_nrt_regs *const vbif_nrt = (struct vbif_nrt_regs *)VBIF_NRT_BASE; +static struct mdp_periph_top1_regs *const mdp_periph_top1 = + (struct mdp_periph_top1_regs *)MDP_PERIPH_TOP1; + +void merge_3d_active(struct edid *edid); +void configure_vbif_qos(void); +void intf_tg_setup(struct edid *edid); +void intf_fetch_start_config(struct edid *edid); +void mdss_source_pipe_config(struct edid *edid, uintptr_t dram_display); +void mdss_layer_mixer_setup(struct edid *edid); +uint32_t calculate_mode_mdp_clk(const struct edid_mode *mode); + +#endif // _SOC_DISPLAY_MDSS_REG_H_ diff --git a/src/soc/qualcomm/x1p42100/include/soc/lpass.h b/src/soc/qualcomm/x1p42100/include/soc/lpass.h index 0b5a8bd4dd4..c3abd43149f 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/lpass.h +++ b/src/soc/qualcomm/x1p42100/include/soc/lpass.h @@ -3,6 +3,7 @@ #ifndef _SOC_QUALCOMM_X1P42100_LPASS_H_ #define _SOC_QUALCOMM_X1P42100_LPASS_H_ +#include #include /* LPASS AON CC PLL Settings */ @@ -20,12 +21,110 @@ #define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL 0x00E00041 #define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL_U 0x00000105 -#define LPASS_CORE_HM_READY BIT(0) -#define HW_CTL BIT(1) +enum lpass_voltage_level { + LPASS_VOLTAGE_LOWSVS_D1, + LPASS_VOLTAGE_LOWSVS, + LPASS_VOLTAGE_SVS, + LPASS_VOLTAGE_SVS_L1, + LPASS_VOLTAGE_NOMINAL, + LPASS_VOLTAGE_TURBO, + LPASS_VOLTAGE_MAX +}; + +/* Default voltage level for boot */ +#define LPASS_DEFAULT_VOLTAGE_LEVEL LPASS_VOLTAGE_SVS_L1 + +/* LPASS QDSP6SS PLL user control bit shifts */ +#define QDSP6SS_PLL_PLLOUT_MAIN_SHFT 0 + +/* LPASS QDSP6SS PLL Settings - Voltage-dependent values */ +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_LOWSVS_D1 0x00000018 +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS_D1 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_LOWSVS 0x0000001F +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS 0x00000029 +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1 0x00000032 +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_NOMINAL 0x0000003E +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_TURBO 0x0000004E +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_TURBO 0x00000000 + +#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1 +#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1 +#define HAL_CLK_LPASS_QDSP6SS_PLL_CAL_L_VALUE 0x00000044 +#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL 0x20485699 +#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U 0x00182261 +#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U1 0x82AA299C +#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL 0x00000000 +#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U 0x00000003 +#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U1 0x00009000 +#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U2 0x00000034 +#define HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL 0x00000000 +#define HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL_U 0x00000005 + +#define LPASS_CORE_HM_READY (1 << 0) +#define HW_CTL (1 << 1) #define GDSC_ENABLE_BIT 0 +#define GDSC_RETAIN_FF_ENABLE (1 << 11) #define LPASS_CORE_HM_VOTE_POWER_ON 0x0 #define GDSC_PWR_ON BIT(31) - +#define LPASS_CORE_HM_VOTE_POWER_DOWN 0x1 #define BCM_LP0_VOTE_VALUE 0x60004001 + +/* NanoRCG status bits */ +#define LPASS_NANO_RCG_PORT2 (1 << 2) + +/* Low power handshake bits */ +#define LPASS_LP_HANDSHAKE_ACK (1 << 0) /* Bit 0: ACK status (RO) */ +#define LPASS_LP_HANDSHAKE_ACTIVE (1 << 1) /* Bit 1: ACTIVE status (RO) */ +#define LPASS_LP_HANDSHAKE_REQUEST (1 << 2) /* Bit 2: REQUEST control (RW) */ + +/* NTS debug bridge handshake tuning */ +#define LPASS_NTS_HANDSHAKE_TIMEOUT_US 500000 +#define LPASS_NTS_HANDSHAKE_DELAY_US 100 + +/* Q6 Core RCG configuration */ +#define Q6_CORE_RCG_CFG 0x201 +#define CLK_CTL_CMD_UPDATE_SHFT 0 +#define LPASS_RCG_UPDATE_TIMEOUT_US 100000 + +/* RSC wait event override mask */ +#define LPASS_RSC_WAIT_EVENT_MASK 0x8 + +/* CR QCTDD10442361 workaround - NOC island isolation bits */ +#define CHIP_CX_RSCC_BYPASS_EN (1 << 21) +#define AON_NOC_STALL_MASK (1 << 22) +#define CHIPCX_SBM_FAULTINEN0_PORT0 (1 << 0) + +/* TCM (Tightly Coupled Memory) control bits */ +#define LPASS_TCM_MAX_BLOCKS 9 + +/* Q6 Boot control bits */ +#define BOOT_CORE_START (1 << 0) +#define BOOT_FSM_START (1 << 0) +#define LPASS_BOOT_FSM_TIMEOUT_US 1000000 + +#define TCSR_BOOT_IMEM_DISABLE_OFF 0x013300 +#define TCSR_BOOT_IMEM_DISABLE ((void *)(TCSR_BASE + TCSR_BOOT_IMEM_DISABLE_OFF)) + +enum cb_err lpass_bring_up(void); + +/* + * Clock workarounds for LPASS clocks. + * + * Keep these lists declarative (CBCR pointers only); apply behavior in + * lpass_apply_clock_workarounds(). + */ +struct lpass_cbcr_list { + uint32_t *cbcr; +}; + #endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/platform_info.h b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h new file mode 100644 index 00000000000..07585601661 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ +#define __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ + +/* ADSP BOOT_PARAMS helpers */ + +/* BOOT_PARAMS bitfield definitions */ +#define CHIP_FAMILY_MASK 0xFFFF +#define CHIP_FAMILY_SHIFT 16 +#define CHIP_ID_MASK 0xFFFF +#define CHIP_VERSION_MAJOR_SHIFT 8 +#define CHIP_VERSION_MASK 0xFF +#define PLATFORM_FIELD_MASK 0xFF +#define PLATFORM_SUBTYPE_SHIFT 16 +#define PLATFORM_TYPE_SHIFT 24 +#define PLATFORM_VERSION_MAJOR_SHIFT 8 + +#define EVB_ENABLE 1 + +/* + * ADSP BOOT_PARAMS chipinfo identifiers. + * + * Keep values as macros (no literals in packer code) to match SMEM chipinfo: + * - CHIPINFO_FAMILY_*: eChipInfoFamily + * - CHIPINFO_ID_SCP_*: eChipInfoId (SCP) + */ + +/* Hamoa (SC8380XP) identifiers used by ADSP BOOT_PARAMS on x1p42100 platforms. */ +#define HAMOA_FAMILY 0x0088 +#define HAMOA_ID_SCP 0x022B + +/* Purwa Compute (SC8340XP / X1P4x100) */ +#define X1P42100_FAMILY 0x009A +#define X1P42100_ID_SCP 0x027B + +#define CHIPINFO_CHIP_VERSION 0x00020000 /* nChipVersion (SMEM) */ +#define CHIPINFO_CHIP_VERSION_MAJOR 0x02 +#define CHIPINFO_CHIP_VERSION_MINOR 0x00 + +/* x1p42100 platform info used for BOOT_PARAMS[4] packing. */ +#define PLATFORMINFO_TYPE 0x28 /* ePlatformType */ +#define PLATFORMINFO_SUBTYPE 0x00 /* nPlatformSubtype */ +#define PLATFORMINFO_VERSION 0x00010000 /* nPlatformVersion */ +#define PLATFORMINFO_VERSION_MAJOR 0x01 +#define PLATFORMINFO_VERSION_MINOR 0x00 + +#define TCSR_SOC_HW_VERSION_DEVICE_NUM_HAMOA 0x09 +#define TCSR_SOC_HW_VERSION_DEVICE_NUM_X1P42100 0x16 + +enum qclib_soc_id { + SOC_ID_UNKNOWN, + SOC_ID_HAMOA, + SOC_ID_X1P42100, +}; + +union tcsr_soc_hw_version { + struct { + uint32_t minor_version : 8; /* bits[7:0] */ + uint32_t major_version : 8; /* bits[15:8] */ + uint32_t device_number : 12; /* bits[27:16] */ + uint32_t family_number : 4; /* bits[31:28] */ + }; + uint32_t data; +}; + +enum qclib_soc_id platform_get_soc_id(void); + +#endif /* __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/pmic.h b/src/soc/qualcomm/x1p42100/include/soc/pmic.h index db798d6b752..d98bcf24573 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/pmic.h +++ b/src/soc/qualcomm/x1p42100/include/soc/pmic.h @@ -6,8 +6,12 @@ #include #define PMIC_SLAVE_ID 0x00 +#define SDAM03_BASE_ADDR 0x7200 #define SDAM05_BASE_ADDR 0x7400 #define MEM_OFFSET_START 0x40 + +#define PMIC_SDAM3_PSI_VARIANT_MAJOR (SDAM03_BASE_ADDR + 0x97) +#define PMIC_PSI_WORKAROUND_ENABLE 0x01 #define PON_EVENT_LOG_AREA_SIZE (127 - 11 + 1) #define PON_EVENT_TOTAL_LOG_AREA_SIZE (PON_EVENT_LOG_AREA_SIZE * 2) diff --git a/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h index c1f9c4630ce..f6abd98072a 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h +++ b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h @@ -31,6 +31,7 @@ #define RPMH_REGULATOR_LEVEL_MIN_MM0 1 #define RPMH_REGULATOR_LEVEL_TURBO_MM0 6 +#define RPMH_REGULATOR_LEVEL_NOM_L1 5 #define BCM_MM0_VOTE_VALUE 0x60004001 #define AOP_BOOT_COOKIE 0xA0C00C1E diff --git a/src/soc/qualcomm/x1p42100/include/soc/variant.h b/src/soc/qualcomm/x1p42100/include/soc/variant.h new file mode 100644 index 00000000000..924c34d6474 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/variant.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_VARIANT_H_ +#define _SOC_QUALCOMM_X1P42100_VARIANT_H_ + +void mainboard_soc_init(void); + +#endif /* _SOC_QUALCOMM_X1P42100_VARIANT_H_ */ diff --git a/src/soc/qualcomm/x1p42100/lpass.c b/src/soc/qualcomm/x1p42100/lpass.c index fb96616dbdc..f467bcef38e 100644 --- a/src/soc/qualcomm/x1p42100/lpass.c +++ b/src/soc/qualcomm/x1p42100/lpass.c @@ -1,12 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include +#include #include +#include #include #include +#include +#include #include +/* Debug configuration value (0 = no debug, non-zero = 0x20000000 = enable debug) */ +u32 lpass_q6_debug_val = 0; + +static struct clock_freq_config lpass_ddrss_shub_cfg[] = { + { + .hz = 400 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(1.5), + }, +}; + +/* Configure LPASS DDRSS SHUB RCG (RCGR + M/N) to 400 MHz */ +static void lpass_configure_ddrss_shub_rcg(void) +{ + if (clock_configure(&gcc->lpass_ddrss_shub_rcg, + lpass_ddrss_shub_cfg, + 400 * MHz, ARRAY_SIZE(lpass_ddrss_shub_cfg)) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to configure DDRSS SHUB RCG\n"); + return; + } +} + static enum cb_err lpass_aon_cc_pll_enable(void) { struct alpha_pll_reg_val_config pll_cfg = {0}; @@ -55,15 +83,79 @@ static enum cb_err lpass_aon_cc_pll_enable(void) return CB_SUCCESS; } +static enum cb_err lpass_qdsp6ss_pll_enable(void) +{ + struct alpha_pll_reg_val_config pll_cfg = {0}; + + pll_cfg.reg_mode = &lpass_qdsp6ss_pll->pll_mode; + pll_cfg.reg_l = &lpass_qdsp6ss_pll->pll_l_val; + pll_cfg.l_val = HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1; + + pll_cfg.reg_alpha = &lpass_qdsp6ss_pll->pll_alpha_val; + pll_cfg.alpha_val = HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1; + + pll_cfg.reg_cal_l = &lpass_qdsp6ss_pll->pll_l_val; + pll_cfg.cal_l_val = HAL_CLK_LPASS_QDSP6SS_PLL_CAL_L_VALUE; + + pll_cfg.reg_config_ctl = &lpass_qdsp6ss_pll->pll_config_ctl; + pll_cfg.config_ctl_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL; + pll_cfg.reg_config_ctl_hi = &lpass_qdsp6ss_pll->pll_config_ctl_u; + pll_cfg.config_ctl_hi_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U; + pll_cfg.reg_config_ctl_hi1 = &lpass_qdsp6ss_pll->pll_config_ctl_u1; + pll_cfg.config_ctl_hi1_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U1; + + pll_cfg.reg_user_ctl = &lpass_qdsp6ss_pll->pll_user_ctl; + pll_cfg.user_ctl_val = HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL; + pll_cfg.reg_user_ctl_hi = &lpass_qdsp6ss_pll->pll_user_ctl_u; + pll_cfg.user_ctl_hi_val = HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL_U; + + pll_cfg.reg_opmode = &lpass_qdsp6ss_pll->pll_opmode; + + if (clock_configure_enable_gpll(&pll_cfg, false, 0) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: QDSP6SS PLL configuration failed\n"); + return CB_ERR; + } + + write32(&lpass_qdsp6ss_pll->pll_test_ctl, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL); + write32(&lpass_qdsp6ss_pll->pll_test_ctl_u, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U); + write32(&lpass_qdsp6ss_pll->pll_test_ctl_u1, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U1); + write32(&lpass_qdsp6ss_pll->pll_test_ctl_u2, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U2); + + if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: QDSP6SS PLL enable failed\n"); + return CB_ERR; + } + + /* Enable PLLOUT_MAIN for QDSP6SS PLL */ + setbits32(&lpass_qdsp6ss_pll->pll_user_ctl, BIT(QDSP6SS_PLL_PLLOUT_MAIN_SHFT)); + + /* Configure Q6 Core RCG */ + write32(&lpass_qdsp6ss_core_cc->core_cfg_rcgr, Q6_CORE_RCG_CFG); + setbits32(&lpass_qdsp6ss_core_cc->core_cmd_rcgr, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + /* Wait for RCG update */ + if (!wait_us(LPASS_RCG_UPDATE_TIMEOUT_US, + !(read32(&lpass_qdsp6ss_core_cc->core_cmd_rcgr) & + BIT(CLK_CTL_CMD_UPDATE_SHFT)))) { + printk(BIOS_ERR, "LPASS: RCG update timeout\n"); + return CB_ERR; + } + + /* Enable QDSP6 core clock */ + setbits32(&lpass_qdsp6ss_core_cc->core_cbcr, BIT(CLK_CTL_EN_SHFT)); + + return CB_SUCCESS; +} + static enum cb_err lpass_setup_core_infrastructure(void) { - if (clock_enable(&gcc->lpass_cfg_noc_sway_cbcr) != CB_SUCCESS) { + if (clock_enable(&gcc->gcc_lpass_cfg_noc_sway_cbcr) != CB_SUCCESS) { printk(BIOS_ERR, "LPASS: Failed to enable CFG NOC SWAY clock\n"); return CB_ERR; } - setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL); + clock_configure_hw_ctl(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, true); write32(&lpass_aon_cc->lpass_hm_collapse_vote_for_q6, LPASS_CORE_HM_VOTE_POWER_ON); @@ -77,9 +169,49 @@ static enum cb_err lpass_setup_core_infrastructure(void) return CB_ERR; } + /* Enable retention */ + setbits32(&lpass_core_gdsc->core_hm_gdscr, GDSC_RETAIN_FF_ENABLE); + + /* Enable SYSNOC interface */ + if (clock_enable(&lpass_core_cc->lpass_lpass_core_cc_sysnoc_mport_core_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable SYSNOC interface\n"); + return CB_ERR; + } + return CB_SUCCESS; } +static const struct lpass_cbcr_list lpass_rpmh_ignore_clks[] = { + { &gcc->gcc_ddrss_lpass_shub_cbcr }, + { &gcc->gcc_tcu_lpass_audio_qtb_cbcr }, +}; + +static const struct lpass_cbcr_list lpass_pmu_ignore_clks[] = { + { &gcc->gcc_lpass_hw_af_noc_ddrss_shub_cbcr }, + { &gcc->gcc_lpass_aggre_noc_ddrss_shub_cbcr }, + { &gcc->gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr }, +}; + +/* Boot clocks (GCC CBCRs). */ +static u32 *lpass_boot_cbcr[LPASS_BOOT_CLK_COUNT] = { + [DDRSS_LPASS_SHUB_CBCR] = &gcc->gcc_ddrss_lpass_shub_cbcr, + [LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR] = &gcc->gcc_lpass_aggre_noc_ddrss_shub_cbcr, + [LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR] = &gcc->gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr, + [LPASS_AON_NOC_DDRSS_SHUB_CBCR] = &gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr, + [LPASS_AUDIO_QTB_CBCR] = &gcc->gcc_lpass_audio_qtb_cbcr, + [LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR] = &gcc->gcc_lpass_hw_af_noc_ddrss_shub_cbcr, + [LPASS_PWRCTL_CBCR] = &gcc->gcc_lpass_pwrctl_cbcr, + [LPASS_QDSS_TSCTR_CBCR] = &gcc->gcc_lpass_qdss_tsctr_cbcr, + [LPASS_QOSGEN_EXTREF_CBCR] = &gcc->gcc_lpass_qosgen_extref_cbcr, + [LPASS_QTB_AHB_CBCR] = &gcc->gcc_lpass_qtb_ahb_cbcr, + [LPASS_QTB_AT_CBCR] = &gcc->gcc_lpass_qtb_at_cbcr, + [LPASS_XO_CBCR] = &gcc->gcc_lpass_xo_cbcr, + [NOC_LPASS_DCD_XO_CBCR] = &gcc->gcc_noc_lpass_dcd_xo_cbcr, + [QMIP_LPASS_QTB_AHB_CBCR] = &gcc->gcc_qmip_lpass_qtb_ahb_cbcr, + [TCU_LPASS_AUDIO_QTB_CBCR] = &gcc->gcc_tcu_lpass_audio_qtb_cbcr, +}; + +/* Array mapping enum clk_lpass to actual CBCR registers */ static u32 *lpass_cbcr[LPASS_CLK_COUNT] = { [LPASS_CODEC_MEM_CBCR] = &lpass_audio_cc->codec_mem_cbcr, [LPASS_CODEC_MEM0_CBCR] = &lpass_audio_cc->codec_mem0_cbcr, @@ -114,15 +246,323 @@ static enum cb_err lpass_audio_clocks_enable(void) return CB_SUCCESS; } -enum cb_err lpass_init(void) +static enum cb_err lpass_rpmh_bcm_vote(void) { + struct rpmh_vreg arc_reg; + enum cb_err ret; int rc; + volatile u32 *boot_cookie = (volatile u32 *)AOP_BOOT_COOKIE_ADDR; + + if (!wait_us(AOP_BOOT_TIMEOUT_US, *boot_cookie == AOP_BOOT_COOKIE)) { + printk(BIOS_ERR, + "AOP not booted after %dus (cookie: 0x%x, expected: 0x%x)\n", + AOP_BOOT_TIMEOUT_US, *boot_cookie, AOP_BOOT_COOKIE); + return CB_ERR; + } + + ret = cmd_db_ready(); + if (ret != CB_SUCCESS) { + ret = cmd_db_init(CMD_DB_BASE_ADDR, CMD_DB_SIZE); + if (ret != CB_SUCCESS) { + printk(BIOS_ERR, "CMD_DB: init failed\n"); + return CB_ERR; + } + } + + rc = rpmh_rsc_init(); + if (rc) { + printk(BIOS_ERR, "RPMH_RSC: init failed\n"); + return CB_ERR; + } + + /* Initialize LCX ARC regulator for LPASS power rail */ + rc = rpmh_regulator_init(&arc_reg, "lcx.lvl", RPMH_REGULATOR_TYPE_ARC); + if (rc) { + printk(BIOS_ERR, "Failed to initialize LPASS power rail lcx ARC regulator\n"); + return CB_ERR; + } + + /* Set LCX level to NOM_L1 */ + rc = rpmh_regulator_arc_set_level(&arc_reg, RPMH_REGULATOR_LEVEL_NOM_L1, true, false); + if (rc) { + printk(BIOS_ERR, "Failed to set LCX ARC level\n"); + return CB_ERR; + } + rc = rpmh_bcm_vote("LP0", BCM_LP0_VOTE_VALUE); if (rc) { printk(BIOS_ERR, "LPASS: Failed to send BCM vote for LPASS bus clock manager LP0\n"); return CB_ERR; } + return CB_SUCCESS; +} + +static void lpass_apply_clock_workarounds(void) +{ + size_t i; + + /* CR QCTDD08205470: ignore RPMh clock disable for TCU-QTB link clocks. */ + for (i = 0; i < ARRAY_SIZE(lpass_rpmh_ignore_clks); i++) + clock_configure_ignore_rpmh_clk_dis(lpass_rpmh_ignore_clks[i].cbcr, true); + + /* CR-3409636: keep AON NOC DDRSS SHUB clock enabled during sleep fencing. */ + clock_configure_ignore_rpmh_clk_dis(&gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr, true); + + /* PMU-GCC spec: ignore PMU clock disable for these clocks. */ + for (i = 0; i < ARRAY_SIZE(lpass_pmu_ignore_clks); i++) + clock_configure_ignore_pmu_clk_dis(lpass_pmu_ignore_clks[i].cbcr, true); + + /* Prevent automatic GDSC collapse (HW defaults enable it). */ + write32(&gcc->gcc_lpass_dsp_gdsc_sleep_ena_vote, 0x0); +} + +static enum cb_err lpass_enable_boot_clocks(void) +{ + size_t i; + enum cb_err ret; + + /* Configure LPASS DDRSS SHUB RCG */ + lpass_configure_ddrss_shub_rcg(); + + /* Enable QTB power domain */ + if (enable_and_poll_gdsc_status(&gcc->gcc_lpass_qtb_gdscr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable QTB GDSC\n"); + return CB_ERR; + } + + /* Ensure IGNORE_RPMH_CLK_DIS is set before enabling TCU-QTB link clock. */ + clock_configure_ignore_rpmh_clk_dis(&gcc->gcc_tcu_lpass_audio_qtb_cbcr, true); + + for (i = 0; i < LPASS_BOOT_CLK_COUNT; i++) { + ret = clock_enable(lpass_boot_cbcr[i]); + if (ret != CB_SUCCESS) + printk(BIOS_WARNING, "LPASS: Failed to enable boot clock %zu: %p\n", i, lpass_boot_cbcr[i]); + } + + return CB_SUCCESS; +} + +static enum cb_err lpass_enable_ssc_smem_clock(void) +{ + if (clock_enable(&lpass_ssc_scc->ssc_scc_smem_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable SSC_SCC_SMEM clock\n"); + return CB_ERR; + } + return CB_SUCCESS; +} + +static enum cb_err lpass_debug_bridge_setup(void) +{ + if (clock_enable(&lpass_aon_cc->at_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable AT clock\n"); + return CB_ERR; + } + + if (clock_enable(&lpass_aon_cc->pclkdbg_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable PCLKDBG clock\n"); + return CB_ERR; + } + + /* Allow debug bridge clocks/paths to settle before requesting handshake. */ + udelay(LPASS_NTS_HANDSHAKE_DELAY_US); + + /* + * In order to attach debugger T32 APB, DAP and NTS bridges need to be enabled + */ + setbits32(&lpass_mcc_lpass_reg->atb_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST); + setbits32(&lpass_mcc_lpass_reg->apb_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST); + setbits32(&lpass_mcc_lpass_reg->nts_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST); + dsb(); + + /* + * Wait for NTS ACK + */ + if (!wait_us(LPASS_NTS_HANDSHAKE_TIMEOUT_US, + read32(&lpass_mcc_lpass_reg->nts_low_power_handshake) & LPASS_LP_HANDSHAKE_ACK)) { + printk(BIOS_WARNING, "LPASS: NTS handshake timeout (NTS=0x%x)\n", + read32(&lpass_mcc_lpass_reg->nts_low_power_handshake)); + /* Non-fatal: continue boot even if debug bridge handshake doesn't complete */ + } + + return CB_SUCCESS; +} + +/* Enable TCM blocks for LPASS processor memory access. */ +static void lpass_tcm_init(void) +{ + uint32_t block; + + if (clock_enable(&lpass_lpi_tcm->axis_hs_cbcr) != CB_SUCCESS) { + printk(BIOS_WARNING, "LPASS: Failed to enable TCM AXIS HS clock\n"); + return; + } + + /* Initialize all TCM 256KB blocks (n=0..9) */ + for (block = 0; block <= LPASS_TCM_MAX_BLOCKS; block++) { + clock_configure_force_mem_core_on(&lpass_lpi_tcm->tcm_256kb_block_cbcr[block], true); + + if (clock_enable(&lpass_lpi_tcm->tcm_256kb_block_cbcr[block]) != CB_SUCCESS) { + printk(BIOS_WARNING, "LPASS: Failed to enable TCM block %d clock\n", block); + return; + } + } +} + +static enum cb_err setup_lpass_processor(void) +{ + /* HW_CTL settings */ + clock_configure_hw_ctl(&gcc->gcc_ddrss_lpass_shub_cbcr, false); + + /* Enable boot clocks */ + if (lpass_enable_boot_clocks() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable boot clocks\n"); + return CB_ERR; + } + + /* Apply clock workarounds */ + lpass_apply_clock_workarounds(); + + /* HPG Step 4: Enable LPASS access */ + if (clock_enable(&gcc->gcc_cfg_noc_lpass_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable CFG NOC access\n"); + return CB_ERR; + } + + /* HPG Step 11: Program LPASS_QDSP6SS_RET_CFG = 0x0 (CR QCTDD10415825) */ + write32(&lpass_qdsp6ss->ret_cfg, 0); + + /* HPG Step 12: Check NanoRCG and enable LPI_NOC_HS conditionally */ + if ((read32(&lpass_lpicx_noc->sidebandmanager_rcg_sbm_flagoutstatus0_low) & LPASS_NANO_RCG_PORT2) == 0) { + if (clock_enable(&lpass_aon_cc->lpi_noc_hs_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable LPI NOC HS clock\n"); + return CB_ERR; + } + } else { + if (clock_disable(&lpass_aon_cc->lpi_noc_hs_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to disable LPI NOC HS clock\n"); + return CB_ERR; + } + } + /* HPG Step 13: Enable Q6 AXIM clock after NanoRCG-based LPI_NOC_HS handling */ + if (clock_enable(&lpass_aon_cc->q6_axim_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable Q6 AXIM clock\n"); + return CB_ERR; + } + + /* Configure debug register */ + write32(&lpass_qdsp6ss->dbg_cfg, lpass_q6_debug_val); + + write32(&lpass_mcc_lpass_reg->rsc_wait_event_ovrd_mask, LPASS_RSC_WAIT_EVENT_MASK); + + /* Initialize TCM */ + lpass_tcm_init(); + + /* Enable Q6_AHBM clock for PRAM access */ + if (clock_enable(&lpass_aon_cc->q6_ahbm_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable Q6_AHBM clock\n"); + return CB_ERR; + } + + /* Enable SSC_SCC_SMEM clock */ + if (lpass_enable_ssc_smem_clock() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable SSC_SCC_SMEM clock\n"); + return CB_ERR; + } + + /* Setup debug bridges if debug is enabled */ + if (lpass_q6_debug_val != 0) { + if (lpass_debug_bridge_setup() != CB_SUCCESS) + printk(BIOS_WARNING, "LPASS: Debug bridge setup failed\n"); + } + /* Enable QDSP6SS PLL */ + if (lpass_qdsp6ss_pll_enable() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable QDSP6SS PLL\n"); + return CB_ERR; + } + + /* CR QCTDD10442361: mask RSCp trigger and disable CHIP_CX QCHANNEL timeout SBM. */ + /* HPG Step 24.e: Set CHIP_CX_RSCC_BYPASS_EN = 1 */ + setbits32(&lpass_aon_cc->lpass_noc_island_isolation, CHIP_CX_RSCC_BYPASS_EN); + + /* HPG Step 24.f: Set AON_NOC_STALL_MASK = 0 */ + clrbits32(&lpass_aon_cc->lpass_noc_island_isolation, AON_NOC_STALL_MASK); + + /* HPG Step 24.g: Set Port0 = 0 */ + clrbits32(&lpass_lpicx_noc->sidebandmanager_chipcx_sbm_faultinen0_low, + CHIPCX_SBM_FAULTINEN0_PORT0); + + clock_configure_hw_ctl(&gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr, true); + + printk(BIOS_INFO, "LPASS: Processor setup complete\n"); + return CB_SUCCESS; +} + +static enum cb_err enable_lpass_processor(void) +{ + /* HPG Step 14: Q6 boot sequence */ + /* + * De-assert QDSP6 stop core. QDSP6 will execute instructions after out of reset. + */ + setbits32(&lpass_qdsp6ss->boot_core_start, BOOT_CORE_START); + + /* + * Trigger boot FSM to start QDSP6 out of reset sequence. + */ + write32(&lpass_qdsp6ss->boot_cmd, BOOT_FSM_START); + dsb(); + + /* Wait for boot FSM completion */ + if (!wait_us(LPASS_BOOT_FSM_TIMEOUT_US, read32(&lpass_qdsp6ss->boot_status) != 0)) { + printk(BIOS_ERR, "LPASS: Boot FSM timeout (boot_status=0x%x)\n", + read32(&lpass_qdsp6ss->boot_status)); + return CB_ERR; + } + + /* Wait for core to come out of reset */ + udelay(5); + + /* HPG Step 19: Disable Q6_AXIM clock after Q6 boots */ + if (clock_disable(&lpass_aon_cc->q6_axim_cbcr) != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to disable Q6_AXIM clock\n"); + return CB_ERR; + } + + printk(BIOS_INFO, "LPASS: Q6 processor enabled\n"); + return CB_SUCCESS; +} + +enum cb_err lpass_bring_up(void) +{ + if (lpass_init() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: lpass_init() failed\n"); + return CB_ERR; + } + + if (setup_lpass_processor() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to setup LPASS processor\n"); + return CB_ERR; + } + + /* Disable BOOT IMEM */ + write32((void *)TCSR_BOOT_IMEM_DISABLE, 0x1); + + /* Boot the LPASS Q6 processor */ + if (enable_lpass_processor() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to enable LPASS processor\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err lpass_init(void) +{ + if (lpass_rpmh_bcm_vote() != CB_SUCCESS) { + printk(BIOS_ERR, "LPASS: Failed to initialize RPMH BCM vote\n"); + return CB_ERR; + } + if (enable_and_poll_gdsc_status(&lpass_aon_cc->lpass_audio_hm_gdscr) != CB_SUCCESS) { printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n"); return CB_ERR; diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index 2c06eccd24e..b8e87a47cec 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -26,11 +26,11 @@ * | dram_acdb | | | * +----------------------------------------------------------+ | | * | ... Usable memory ... | | | - * 0xE69C0000 +----------------------------------------------------------+ | | - * | dram_display | | | + * 0xE6A00000 +----------------------------------------------------------+ | | + * | framebuffer | | | * 0xE4800000 +----------------------------------------------------------+ | | * | ... Usable memory ... | | | - * 0xD9632000 +----------------------------------------------------------+ | | + * 0xDA132000 +----------------------------------------------------------+ | | * | dram_ta | | | * 0xD8632000 +----------------------------------------------------------+ | | * | BL31 (ARM Trusted Firmware) | | | @@ -58,10 +58,20 @@ * | dram_wlan | | | * 0x85380000 +----------------------------------------------------------+ | | * | ... Usable memory ... | | | + * 0x82900000 +----------------------------------------------------------+ | | + * | dram_tz_static | | | * 0x82800000 +----------------------------------------------------------+ | | * | dram_adsp_rpc_heap | | | * 0x82000000 +----------------------------------------------------------+ | | - * | dram_tz_static | | | + * | ... Usable memory ... | | | + * 0x81F38000 +----------------------------------------------------------+ | | + * | dram_pld_pdp | | | + * 0x81F37000 +----------------------------------------------------------+ | | + * | dram_pld_gmu | | | + * 0x81F36000 +----------------------------------------------------------+ | | + * | dram_pld_pep | | | + * 0x81F30000 +----------------------------------------------------------+ | | + * | ... Usable memory ... | | | * 0x81F00000 +----------------------------------------------------------+ | | * | dram_pdp | | | * 0x81E00000 +----------------------------------------------------------+ | | @@ -93,18 +103,24 @@ * 0x80004000 +----------------------------------------------------------+ | | * | POSTRAM STACK | v v * 0x80000000 +----------------------------------------------------------+ <-------------- + * | PCIe | PCIe + * 0x7E000000 +----------------------------------------------------------+ <--------- * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX * 0x24060000 +----------------------------------------------------------+ <--------- * | shrm | SHRM * 0x24040000 +----------------------------------------------------------+ <--------- * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX + * 0x1CB40000 +----------------------------------------------------------+ <--------- + * | CPUCP | + * 0x1CB00000 +----------------------------------------------------------+ <--------- + * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX * 0x14A80000 +----------------------------------------------------------+ <--------- * | auth_metadata | ^ * 0x14A7E000 +----------------------------------------------------------+ | * | debug_policy | | * 0x14A7D000 +----------------------------------------------------------+ | * | ... Usable memory ... | | - * 0x14A59000 +----------------------------------------------------------+ | + * 0x14A60000 +----------------------------------------------------------+ | * | OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE | | * 0x14A38000 +----------------------------------------------------------+ | * | PRERAM_CBMEM_CONSOLE | | @@ -116,6 +132,8 @@ * | qclib | | * 0x14897000 +----------------------------------------------------------+ | * | ... Usable memory ... | | + * 0x14892000 +----------------------------------------------------------+ | + * | cdt_data | | * 0x14891000 +----------------------------------------------------------+ | * | apdp_ramdump_meta | | * 0x14890000 +----------------------------------------------------------+ | @@ -132,7 +150,7 @@ * | ... Usable memory ... | | * 0x14860C00 +----------------------------------------------------------+ | * | FMAP_CACHE | | - * 0x14860000 +----------------------------------------------------------+ BSRAM + * 0x14861800 +----------------------------------------------------------+ BSRAM * | CBFS_MCACHE | | * 0x1485C000 +----------------------------------------------------------+ | * | qclib_serial_log | | @@ -212,29 +230,45 @@ SECTIONS BOOTBLOCK(0x14819000, 60K) PRERAM_CBFS_CACHE(0x14828000, 103K) TIMESTAMP(0x14841C00, 1K) +/* Bluey/CRD has more MMU entries hence it requires a bigger TTB region. */ +#if CONFIG(BOARD_GOOGLE_MODEL_BLUEY) + TTB(0x14842000, 64K) + PRERAM_STACK(0x14852000, 16K) + VBOOT2_WORK(0x14856000, 12K) + PRERAM_DMA_COHERENT(0x14859000, 8K) +#else TTB(0x14842000, 56K) PRERAM_STACK(0x14850000, 16K) VBOOT2_WORK(0x14854000, 12K) PRERAM_DMA_COHERENT(0x14858000, 8K) +#endif REGION(qclib_serial_log, 0x1485B000, 4K, 4K) - CBFS_MCACHE(0x1485C000,16K) - FMAP_CACHE(0x14860400, 2K) + CBFS_MCACHE(0x1485C000,22K) + FMAP_CACHE(0x14861800, 2K) REGION(dcb, 0x14862000, 56K, 4K) REGION(dtb, 0x14870000, 32K, 4K) REGION(ddr_training, 0x14878000, 64K, 4K) REGION(qc_blob_meta, 0x14888000, 16K, 4K) REGION(aop_blob_meta, 0x1488c000, 16K, 4K) REGION(apdp_ramdump_meta, 0x14890000, 4K, 4K) +#if CONFIG(SOC_QUALCOMM_CDT) + REGION(cdt_data, 0x14891000, 4K, 4K) +#endif REGION(qclib, 0x14897000, 1536K, 4K) REGION(cpr_settings, 0x14A17000, 12K, 4K) PRERAM_CBMEM_CONSOLE(0x14A30000, 32K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 160K) REGION(debug_policy, 0x14A7D000 , 4K, 4K) REGION(auth_metadata, 0x14A7E000, 8K, 4K) BSRAM_END(0x14A80000) + REGION(cpucp, 0x1CB00000, 256K , 4K) + REGION(shrm, 0x24040000, 128K , 4K) + /* PCIe Reserved Region: 0x7E000000 - 0x80000000 (32MB) */ + REGION(pcie, 0x7E000000, 32M, 4K) + DRAM_START(0x80000000) POSTRAM_STACK(0x80000000, 32K) POSTRAM_DMA_COHERENT(0x8000C000, 16K) @@ -252,8 +286,11 @@ SECTIONS REGION(dram_dc_log, 0x81CE4000, 0x10000, 4K) REGION(dram_pdp, 0x81E00000, 0x100000, 4K) - REGION(dram_tz_static, 0x81F00000, 0x100000, 4K) + REGION(dram_pld_pep, 0x81F30000, 24K, 4K) + REGION(dram_pld_gmu, 0x81F36000, 4K, 4K) + REGION(dram_pld_pdp, 0x81F37000, 4K, 4K) REGION(dram_adsp_rpc_heap, 0x82000000, 0x800000, 4K) + REGION(dram_tz_static, 0x82800000, 0x100000, 4K) REGION(dram_wlan, 0x85380000, 0xC00000, 4K) REGION(dram_pil, 0x866C0000, 0xACC0000, 4K) @@ -261,8 +298,8 @@ SECTIONS RAMSTAGE(0xA0800000, 16M) REGION(dram_tz, 0xD8000000, 0x56A000, 4K) BL31(0xD856A000, 800K) - REGION(dram_ta, 0xD8632000, 0x1000000, 4K) - REGION(dram_display, 0xE4800000, 0x21C0000, 4K) + REGION(dram_ta, 0xD8632000, 0x1B00000, 4K) + FRAMEBUFFER(0xE4800000, 0x2200000) REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K) REGION(dram_smem, 0xFFE00000, 0x200000, 4K) DRAM_END(0x100000000) diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c index 1648bc6f2f0..4834be83716 100644 --- a/src/soc/qualcomm/x1p42100/pcie.c +++ b/src/soc/qualcomm/x1p42100/pcie.c @@ -330,6 +330,12 @@ void gcom_pcie_power_on_ep(void) gpio_output(NVME_REG_EN, 1); } +/* Turn off NVMe */ +void gcom_pcie_power_off_ep(void) +{ + gpio_output(NVME_REG_EN, 0); +} + void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg) { host_cfg->cntlr_cfg = &pcie_host; diff --git a/src/soc/qualcomm/x1p42100/platform_info.c b/src/soc/qualcomm/x1p42100/platform_info.c new file mode 100644 index 00000000000..869c8345de8 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/platform_info.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* TCSR SoC HW version Register for platform identification */ +#define TCSR_SOC_HW_VERSION 0x1FC8000 + +enum qclib_soc_id platform_get_soc_id(void) +{ + union tcsr_soc_hw_version version; + + version.data = read32((void *)TCSR_SOC_HW_VERSION); + + switch (version.device_number) { + case TCSR_SOC_HW_VERSION_DEVICE_NUM_HAMOA: + return SOC_ID_HAMOA; + case TCSR_SOC_HW_VERSION_DEVICE_NUM_X1P42100: + return SOC_ID_X1P42100; + default: + printk(BIOS_WARNING, "Unknown Qualcomm SoC device number: 0x%03x\n", + version.device_number); + return SOC_ID_UNKNOWN; + } +} diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c index 6baabccb204..31ce37bac54 100644 --- a/src/soc/qualcomm/x1p42100/qclib.c +++ b/src/soc/qualcomm/x1p42100/qclib.c @@ -7,6 +7,7 @@ #include #include #include +#include __weak int qclib_mainboard_override(struct qclib_cb_if_table *table) { return 0; } @@ -27,10 +28,63 @@ bool qclib_check_dload_mode(void) return false; } +struct qclib_file_map { + const char *dcb; + const char *dtb; + const char *cpr; +}; + +static const struct qclib_file_map hamoa_files = { + .dcb = CONFIG_CBFS_PREFIX "/dcb_hamoa", + .dtb = CONFIG_CBFS_PREFIX "/dtb_hamoa", + .cpr = CONFIG_CBFS_PREFIX "/cpr_hamoa", +}; + +static const struct qclib_file_map x1p_files = { + .dcb = CONFIG_CBFS_PREFIX "/dcb_x1p42100", + .dtb = CONFIG_CBFS_PREFIX "/dtb_x1p42100", + .cpr = CONFIG_CBFS_PREFIX "/cpr_x1p42100", +}; + +static const struct qclib_file_map *get_soc_file_map(void) +{ + enum qclib_soc_id soc = platform_get_soc_id(); + + if (soc == SOC_ID_HAMOA) + return &hamoa_files; + + /* Fall back to x1p42100 configuration by default */ + return &x1p_files; +} + +const char *qclib_override_soc_file(enum qclib_cbfs_file file) +{ + const struct qclib_file_map *map = get_soc_file_map(); + + switch (file) { + case QCLIB_CBFS_DCB: + return map->dcb; + case QCLIB_CBFS_DTB: + return map->dtb; + case QCLIB_CBFS_CPR: + return map->cpr; + default: + return NULL; + } +} + int qclib_soc_override(struct qclib_cb_if_table *table) { ssize_t data_size; + /* Attempt to load DCB Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_DCB), _dcb, REGION_SIZE(dcb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /dcb failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0); + /* Attempt to load DTB Blob */ data_size = cbfs_load(qclib_file(QCLIB_CBFS_DTB), _dtb, REGION_SIZE(dtb)); if (!data_size) { diff --git a/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c b/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c index 7ddb3ac10d2..3721eef2f72 100644 --- a/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c +++ b/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include + #include #include #include diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c index df4e8036275..ee3641e4673 100644 --- a/src/soc/qualcomm/x1p42100/soc.c +++ b/src/soc/qualcomm/x1p42100/soc.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include @@ -7,8 +10,48 @@ #include #include #include +#include +#include #include +#define SPI_BUS_CLOCK_FREQ (50 * MHz) + +/* + * FIXME: Reduce SPI Frequency to 50-MHz to improve + * the platform stability during payload stage. + */ +void soc_prepare_bl31_handoff(void) +{ + printk(BIOS_WARNING, "%s: Reduce SPI frequency to 50MHz to better stability\n", + __func__); + qspi_set_bus_clock(SPI_BUS_CLOCK_FREQ); +} + +static void preload_bl31(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + cbfs_preload(CONFIG_CBFS_PREFIX"/bl31"); +} + +static void preload_bl32(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + cbfs_preload(CONFIG_CBFS_PREFIX"/secure_os"); +} + +/* + * Weak implementation of mainboard-specific display initialization. + * This can be overridden by mainboard-specific code. + */ +__weak void mainboard_soc_init(void) +{ + /* Default implementation: do nothing */ +} + static struct device_operations pci_domain_ops = { .read_resources = &qcom_pci_domain_read_resources, .set_resources = &pci_domain_set_resources, @@ -32,6 +75,7 @@ static void soc_read_resources(struct device *dev) ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size); mmio_range(dev, index++, (uintptr_t)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_ncc, REGION_SIZE(dram_ncc)); reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp)); reserved_ram_range(dev, index++, (uintptr_t)_dram_xbl_log, REGION_SIZE(dram_xbl_log)); @@ -49,6 +93,9 @@ static void soc_read_resources(struct device *dev) reserved_ram_range(dev, index++, (uintptr_t)_dram_pdp, REGION_SIZE(dram_pdp)); reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_static, REGION_SIZE(dram_tz_static)); reserved_ram_range(dev, index++, (uintptr_t)_dram_adsp_rpc_heap, REGION_SIZE(dram_adsp_rpc_heap)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pld_pep, REGION_SIZE(dram_pld_pep)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pld_gmu, REGION_SIZE(dram_pld_gmu)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_pld_pdp, REGION_SIZE(dram_pld_pdp)); reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan)); reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil)); reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta)); @@ -58,6 +105,9 @@ static void soc_read_resources(struct device *dev) calc_acdb_carveout_size()); reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi)); reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem)); + + /* Reserve PCIe region to prevent allocation */ + mmio_range(dev, index++, (uintptr_t)_pcie, REGION_SIZE(pcie)); } static void qtee_fw_config_load(void) @@ -90,7 +140,8 @@ static void soc_init(struct device *dev) { cpucp_fw_load_reset(); qtee_fw_config_load(); - lpass_init(); + preload_bl31(); + preload_bl32(); } static struct device_operations soc_ops = { @@ -115,3 +166,14 @@ struct chip_operations soc_qualcomm_x1p42100_ops = { .name = "SOC Qualcomm X1P-42-100", .enable_dev = enable_soc_dev, }; + +static void soc_late_init(void *unused) +{ + /* Doing LPASS init late to optimize boot time */ + lpass_init(); + + /* Doing board specific init late to optimize boot time */ + mainboard_soc_init(); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, soc_late_init, NULL); diff --git a/src/soc/qualcomm/x1p42100/tsens_map.c b/src/soc/qualcomm/x1p42100/tsens_map.c new file mode 100644 index 00000000000..dcd8a180432 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/tsens_map.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SoC Specific TSENS Map + */ + +#include + +/* Controller Configuration for SoC TSENS */ +static const struct tsens_controller tsens_blocks[] = { + /* Name, TM base, SROT base, Sensor count */ + {"tsens0", 0x0c271000, 0x0c222000, 13}, + {"tsens1", 0x0c272000, 0x0c223000, 11}, + {"tsens2", 0x0c273000, 0x0c224000, 11}, + {"tsens3", 0x0c274000, 0x0c225000, 15} +}; + +/* Sensor Definition Mapping */ +const struct thermal_zone_map qcom_thermal_zones[] = { + /* Label, Type, Controller, HW ID, Threshold (in milli degree C) */ + /* SoC TSENS Controller 0 */ + {"aoss-0", TYPE_TSENS, &tsens_blocks[0], 0, 105000}, + {"cpu-0-0-0", TYPE_TSENS, &tsens_blocks[0], 1, 108000}, + {"cpu-0-0-1", TYPE_TSENS, &tsens_blocks[0], 2, 108000}, + {"cpu-0-1-0", TYPE_TSENS, &tsens_blocks[0], 3, 108000}, + {"cpu-0-1-1", TYPE_TSENS, &tsens_blocks[0], 4, 108000}, + {"cpu-0-2-0", TYPE_TSENS, &tsens_blocks[0], 5, 108000}, + {"cpu-0-2-1", TYPE_TSENS, &tsens_blocks[0], 6, 108000}, + {"cpu-0-3-0", TYPE_TSENS, &tsens_blocks[0], 7, 108000}, + {"cpu-0-3-1", TYPE_TSENS, &tsens_blocks[0], 8, 108000}, + {"cpuss-0-0", TYPE_TSENS, &tsens_blocks[0], 9, 105000}, + {"cpuss-0-1", TYPE_TSENS, &tsens_blocks[0], 10, 105000}, + {"ddr-0", TYPE_TSENS, &tsens_blocks[0], 11, 105000}, + {"video", TYPE_TSENS, &tsens_blocks[0], 12, 105000}, + + /* SoC TSENS Controller 1 */ + {"aoss-1", TYPE_TSENS, &tsens_blocks[1], 0, 105000}, + {"cpu-1-0-0", TYPE_TSENS, &tsens_blocks[1], 1, 108000}, + {"cpu-1-0-1", TYPE_TSENS, &tsens_blocks[1], 2, 108000}, + {"cpu-1-1-0", TYPE_TSENS, &tsens_blocks[1], 3, 108000}, + {"cpu-1-1-1", TYPE_TSENS, &tsens_blocks[1], 4, 108000}, + {"cpu-1-2-0", TYPE_TSENS, &tsens_blocks[1], 5, 108000}, + {"cpu-1-2-1", TYPE_TSENS, &tsens_blocks[1], 6, 108000}, + {"cpu-1-3-0", TYPE_TSENS, &tsens_blocks[1], 7, 108000}, + {"cpu-1-3-1", TYPE_TSENS, &tsens_blocks[1], 8, 108000}, + {"cpuss-1-0", TYPE_TSENS, &tsens_blocks[1], 9, 105000}, + {"cpuss-1-1", TYPE_TSENS, &tsens_blocks[1], 10, 105000}, + + /* SoC TSENS Controller 2 */ + {"aoss-2", TYPE_TSENS, &tsens_blocks[2], 0, 105000}, + {"cpu-2-0-0", TYPE_TSENS, &tsens_blocks[2], 1, 108000}, + {"cpu-2-0-1", TYPE_TSENS, &tsens_blocks[2], 2, 108000}, + {"cpu-2-1-0", TYPE_TSENS, &tsens_blocks[2], 3, 108000}, + {"cpu-2-1-1", TYPE_TSENS, &tsens_blocks[2], 4, 108000}, + {"cpu-2-2-0", TYPE_TSENS, &tsens_blocks[2], 5, 108000}, + {"cpu-2-2-1", TYPE_TSENS, &tsens_blocks[2], 6, 108000}, + {"cpu-2-3-0", TYPE_TSENS, &tsens_blocks[2], 7, 108000}, + {"cpu-2-3-1", TYPE_TSENS, &tsens_blocks[2], 8, 108000}, + {"cpuss-2-0", TYPE_TSENS, &tsens_blocks[2], 9, 105000}, + {"cpuss-2-1", TYPE_TSENS, &tsens_blocks[2], 10, 105000}, + + /* SoC TSENS Controller 3 */ + {"aoss-3", TYPE_TSENS, &tsens_blocks[3], 0, 105000}, + {"nsp-0", TYPE_TSENS, &tsens_blocks[3], 1, 105000}, + {"nsp-1", TYPE_TSENS, &tsens_blocks[3], 2, 105000}, + {"nsp-2", TYPE_TSENS, &tsens_blocks[3], 3, 105000}, + {"nsp-3", TYPE_TSENS, &tsens_blocks[3], 4, 105000}, + {"gpuss-0", TYPE_TSENS, &tsens_blocks[3], 5, 95000}, + {"gpuss-1", TYPE_TSENS, &tsens_blocks[3], 6, 95000}, + {"gpuss-2", TYPE_TSENS, &tsens_blocks[3], 7, 95000}, + {"gpuss-3", TYPE_TSENS, &tsens_blocks[3], 8, 95000}, + {"gpuss-4", TYPE_TSENS, &tsens_blocks[3], 9, 95000}, + {"gpuss-5", TYPE_TSENS, &tsens_blocks[3], 10, 95000}, + {"gpuss-6", TYPE_TSENS, &tsens_blocks[3], 11, 95000}, + {"gpuss-7", TYPE_TSENS, &tsens_blocks[3], 12, 95000}, + {"camera-0", TYPE_TSENS, &tsens_blocks[3], 13, 105000}, + {"camera-1", TYPE_TSENS, &tsens_blocks[3], 14, 105000}, + + /* Sentinel */ + {NULL, 0, NULL, 0, 0} +}; diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index 0543475d84f..475c2f7156f 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -149,8 +149,7 @@ uintptr_t uart_platform_base(unsigned int idx) void uart_init(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); - uint16_t div = (uint16_t)uart_baudrate_divisor( - get_uart_baudrate(), uart_platform_refclk(), 16); + uint16_t div = (uint16_t)uart_get_baudrate_divisor(); am335x_uart_init(uart, div); } diff --git a/src/soc/xilinx/Kconfig b/src/soc/xilinx/Kconfig deleted file mode 100644 index 95100a0203d..00000000000 --- a/src/soc/xilinx/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# Load all chipsets -source "src/soc/xilinx/*/Kconfig" diff --git a/src/southbridge/amd/pi/Makefile.mk b/src/southbridge/amd/pi/Makefile.mk index ed4247da1a1..a8a9155457c 100644 --- a/src/southbridge/amd/pi/Makefile.mk +++ b/src/southbridge/amd/pi/Makefile.mk @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 134b57546d2..a38311cffb3 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -3,10 +3,7 @@ config SOUTHBRIDGE_AMD_PI_AVALON bool -config SOUTHBRIDGE_AMD_PI_KERN - bool - -if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN +if SOUTHBRIDGE_AMD_PI_AVALON config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y @@ -57,13 +54,6 @@ config HUDSON_IMC_FWM help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control -config HUDSON_GEC_FWM - bool - default n - help - Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. - Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. - config HUDSON_PSP bool default y if CPU_AMD_PI_00730F01 @@ -74,20 +64,14 @@ config AMDFW_CONFIG_FILE config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON - default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN + default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON - default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN + default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" depends on HUDSON_IMC_FWM -config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - depends on HUDSON_GEC_FWM - config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" @@ -141,13 +125,6 @@ config HUDSON_FADT_8042 Select if there is an 8042-compatible keyboard controller in the system. -config AMDFW_OUTSIDE_CBFS - def_bool n - help - The AMDFW (PSP) is typically locatable in cbfs. Select this - option to manually attach the generated amdfw.rom at an - offset of 0x20000 from the bottom of the coreboot ROM image. - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk index 9d71df5efca..c7b969856c6 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.mk +++ b/src/southbridge/amd/pi/hudson/Makefile.mk @@ -47,61 +47,16 @@ CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include # # EC ROM should be 64K aligned. -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -HUDSON_FWM_POSITION=0x20000 -else HUDSON_FWM_POSITION=0x720000 -endif - -ifeq ($(CONFIG_HUDSON_PSP), y) - -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_TYPE= - -endif - -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key - -endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) -OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) - -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(call strip_quotes, $(AMD_PUBKEY2_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY2_FILE)) \ - $(call strip_quotes, $(PSPBTLDR2_FILE)) \ - $(call strip_quotes, $(SMUFWM2_FILE)) \ - $(call strip_quotes, $(SMUFWM2_FN_FILE)) \ - $(call strip_quotes, $(PSPRCVR2_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS2_FILE)) \ - $(call strip_quotes, $(PSPNVRAM2_FILE)) \ - $(call strip_quotes, $(SMUSCS2_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG2_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS2_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_2_FN_FILE)) \ + $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(DEP_FILES) \ $(AMDFWTOOL) rm -f $@ @@ -109,37 +64,15 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ - $(OPT_HUDSON_GEC_FWM_FILE) \ - $(OPT_2AMD_PUBKEY_FILE) \ - $(OPT_2PSPBTLDR_FILE) \ - $(OPT_2SMUFWM_FILE) \ - $(OPT_2SMUFWM_FN_FILE) \ - $(OPT_2PSPRCVR_FILE) \ - $(OPT_2PUBSIGNEDKEY_FILE) \ - $(OPT_2PSPSECUREOS_FILE) \ - $(OPT_2PSPNVRAM_FILE) \ - $(OPT_2PSPSECUREDEBUG_FILE) \ - $(OPT_2PSPTRUSTLETS_FILE) \ - $(OPT_2TRUSTLETKEY_FILE) \ - $(OPT_2SMUFIRMWARE2_FILE) \ - $(OPT_2SMUFIRMWARE2_FN_FILE) \ - $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(HUDSON_FWM_POSITION) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --output $@ -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) - printf " DD Adding AMD Firmware\n" - dd if=$(obj)/amdfw.rom \ - of=$< conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 - -else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) - cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-position := $(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + 1 \ + $(HUDSON_FWM_POSITION)) apu/amdfw-type := raw - -endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 834b346ac4e..2d3d21f2108 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -35,9 +35,7 @@ Device(SBUS) { #include "usb.asl" /* 0:14.2 - HD Audio */ -#if !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #include "audio.asl" -#endif /* 0:14.3 - LPC */ #include "lpc.asl" diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 741a7b50cbf..9195ceadefc 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -36,8 +36,7 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \ - !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) +#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -51,8 +50,7 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \ - !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) +#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 094e00d4877..befd4bfc71f 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -55,15 +55,4 @@ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #endif -#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) -#define FCH_INT_TABLE_SIZE 0x76 -#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ -#define PIRQ_I2C0 0x70 -#define PIRQ_I2C1 0x71 -#define PIRQ_I2C2 0x72 -#define PIRQ_I2C3 0x73 -#define PIRQ_UART0 0x74 -#define PIRQ_UART1 0x75 -#endif - #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 59ddbd2cbd8..76cb4bf20e2 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -13,11 +13,6 @@ const char *intr_types[] = { #if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", -#elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN) - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", - [0x62] = "GPIO\t", - [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t", #endif }; diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg index 71593aead7c..b91977716dc 100644 --- a/src/southbridge/amd/pi/hudson/fw_avl.cfg +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -1,6 +1,8 @@ # PSP fw config file FIRMWARE_LOCATION 3rdparty/blobs/southbridge/amd/avalon/PSP +SOC_NAME Mullins + #PSP AMD_PUBKEY_FILE AmdPubKey.bin PSPBTLDR_FILE PspBootLoader.Bypass.sbin diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 381f7d3da9d..334e7989e21 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -9,7 +9,7 @@ static void sata_init(struct device *dev) { -#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || CONFIG(SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) /************************************** * Configure the SATA port multiplier * **************************************/ diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 3260021d088..464dbf4fd43 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index b4b6ea33e7b..1868e8d2ea9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -39,6 +39,7 @@ struct southbridge_intel_bd82x6x_config { /* IDE configuration */ uint8_t sata_port_map; + uint8_t sata_hotplug_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index cf31d4ed136..4b4f69aa4fa 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -232,7 +233,7 @@ static void pch_enable_bars(void) pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(PCH_LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index cdd1bb3f116..fea894f7618 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 534251d5e8c..d07fff2059b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,6 +22,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) @@ -116,8 +117,6 @@ void early_usb_init(void); #define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) -#define BIOS_CNTL 0xDC -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 @@ -126,35 +125,9 @@ void early_usb_init(void); #define GPI_IS_SCI 0x02 #define GPI_IS_NMI 0x03 -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ #define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ /* PCI Configuration Space (D31:F2): SATA */ @@ -183,9 +156,6 @@ void early_usb_init(void); #define HST_EN (1 << 0) /* Southbridge IO BARs */ - -#define GPIOBASE 0x48 - #define PMBASE 0x40 #define CIR0 0x0050 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index a30c01a94ce..fe513671634 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -152,6 +152,13 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0xa0); reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); + /* PxCMD */ + for (int port = 0; port < 6; port++) { + reg32 = read32(abar + 0x118 + 0x80 * port); + if (config->sata_hotplug_map & (1 << port)) + reg32 |= 1 << 18; + write32(abar + 0x118 + 0x80 * port, reg32); + } } else { /* IDE */ diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index 0da0d707420..d5de07ec196 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -58,6 +58,9 @@ config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ config HAVE_INTEL_CHIPSET_LOCKDOWN def_bool n +config HAVE_INSMM_STS + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/southbridge/intel/common/Makefile.mk b/src/southbridge/intel/common/Makefile.mk index 39cb1b985e8..57b10889774 100644 --- a/src/southbridge/intel/common/Makefile.mk +++ b/src/southbridge/intel/common/Makefile.mk @@ -50,6 +50,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c +smm-$(CONFIG_HAVE_INSMM_STS) += insmm_sts.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 3b5c3e58d08..bb0ce6f91be 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "acpi_pirq_gen.h" diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 95eda31c9d2..d461ed9bba6 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -128,6 +128,22 @@ config GBE_BIN_PATH depends on HAVE_GBE_BIN default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/gbe.bin" +config MAINBOARD_USES_IFD_PLATFORM_DATA_REGION + def_bool n + +config HAVE_PLATFORM_DATA_BIN + bool "Add Platform Data region binary" + depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_PLATFORM_DATA_REGION + help + Some platforms define a Platform Data region (SI_PDR) in the Intel + Flash Descriptor. Select this to supply a binary that ifdtool will + inject into that region when building coreboot.rom. + +config PLATFORM_DATA_BIN_PATH + string "Path to Platform Data region binary" + depends on HAVE_PLATFORM_DATA_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/platform_data.bin" + config MAINBOARD_USES_IFD_EC_REGION def_bool n diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk index 3c7ad906e6e..b68f77477ca 100644 --- a/src/southbridge/intel/common/firmware/Makefile.mk +++ b/src/southbridge/intel/common/firmware/Makefile.mk @@ -43,6 +43,9 @@ endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) add_intel_firmware: $(call strip_quotes,$(CONFIG_GBE_BIN_PATH)) endif +ifeq ($(CONFIG_HAVE_PLATFORM_DATA_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_PLATFORM_DATA_BIN_PATH)) +endif ifeq ($(CONFIG_HAVE_EC_BIN),y) add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH)) endif @@ -94,6 +97,14 @@ ifeq ($(CONFIG_HAVE_GBE_BIN),y) -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre endif +ifeq ($(CONFIG_HAVE_PLATFORM_DATA_BIN),y) + printf " IFDTOOL platform_data.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i 'Platform Data':$(CONFIG_PLATFORM_DATA_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif ifeq ($(CONFIG_HAVE_EC_BIN),y) printf " IFDTOOL ec.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index ae13cb95bf6..04fa605c351 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -6,9 +6,9 @@ #include #include #include -#include #include "southbridge/intel/common/gpio.h" +#include "southbridge/intel/common/lpc_def.h" #define MAX_GPIO_NUMBER 75 /* zero based */ @@ -17,9 +17,6 @@ * more helper functions to expose the functionality you want instead. */ -/* LPC GPIO Base Address Register */ -#define GPIO_BASE 0x48 - /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 @@ -40,15 +37,15 @@ static u16 get_gpio_base(void) { #ifdef __SIMPLE_DEVICE__ - /* Don't assume GPIO_BASE is still the same */ - return pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIO_BASE) & 0xfffe; + /* Don't assume GPIOBASE is still the same */ + return pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffe; #else static u16 gpiobase; if (gpiobase) return gpiobase; - gpiobase = pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffe; + gpiobase = pci_read_config16(pcidev_on_root(0x1f, 0), GPIOBASE) & 0xfffe; return gpiobase; #endif diff --git a/src/southbridge/intel/common/insmm_sts.c b/src/southbridge/intel/common/insmm_sts.c new file mode 100644 index 00000000000..8b663ea1af5 --- /dev/null +++ b/src/southbridge/intel/common/insmm_sts.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "insmm_sts.h" + +void set_insmm_sts(const bool enable_writes) +{ + msr_t msr = { + .lo = read32p(0xfed30880), + .hi = 0, + }; + if (enable_writes) + msr.lo |= 1; + else + msr.lo &= ~1; + + wrmsr(MSR_SPCL_CHIPSET_USAGE, msr); +} diff --git a/src/southbridge/intel/common/insmm_sts.h b/src/southbridge/intel/common/insmm_sts.h new file mode 100644 index 00000000000..1832e698901 --- /dev/null +++ b/src/southbridge/intel/common/insmm_sts.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_INSMM_STS_H +#define SOUTHBRIDGE_INTEL_INSMM_STS_H + +#include + +void set_insmm_sts(const bool enable_writes); + +#endif /* SOUTHBRIDGE_INTEL_INSMM_STS_H */ diff --git a/src/southbridge/intel/common/lpc_def.h b/src/southbridge/intel/common/lpc_def.h new file mode 100644 index 00000000000..af830316ca8 --- /dev/null +++ b/src/southbridge/intel/common/lpc_def.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LPC_DEF_H +#define SOUTHBRIDGE_INTEL_LPC_DEF_H + +/* LPC GPIO Base Address Register */ +#define GPIOBASE 0x48 + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6a +#define PIRQH_ROUT 0x6b + +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ + +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ + +/* Only available on ICH10 and newer*/ +#define LGMR 0x98 /* LPC Generic Memory Range */ + +#define BIOS_CNTL 0xdc +#define BIOS_CNTL_BIOSWE (1 << 0) +#define BIOS_CNTL_BLE (1 << 1) +#define BIOS_CNTL_SMM_BWP (1 << 5) + +#endif /* SOUTHBRIDGE_INTEL_LPC_DEF_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index b1a6a6689d9..a0bfc3567a5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -15,6 +15,8 @@ #include #include +#include "insmm_sts.h" +#include "lpc_def.h" #include "pmutil.h" u16 get_pmbase(void) @@ -266,9 +268,22 @@ static void southbridge_smi_store(void) /* Parameter buffer in EBX */ reg_rbx = (uintptr_t)io_smi->rbx; + const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + const bool wp_enabled = !(pci_read_config16(lpc_dev, BIOS_CNTL) & BIOS_CNTL_BIOSWE); + if (wp_enabled) { + if (CONFIG(HAVE_INSMM_STS)) + set_insmm_sts(true); + pci_or_config16(lpc_dev, BIOS_CNTL, BIOS_CNTL_BIOSWE); + } /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_rbx); io_smi->rax = ret; + + if (wp_enabled) { + pci_and_config16(lpc_dev, BIOS_CNTL, ~BIOS_CNTL_BIOSWE); + if (CONFIG(HAVE_INSMM_STS)) + set_insmm_sts(false); + } } static int mainboard_finalized = 0; @@ -375,9 +390,9 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL); - if (bios_cntl & 1) { + if (bios_cntl & BIOS_CNTL_BIOSWE) { /* BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */ @@ -389,8 +404,8 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + pci_write_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL, + (bios_cntl & ~BIOS_CNTL_BIOSWE)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 089e3ce234c..e56b6a2db2b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -20,6 +20,7 @@ #include #include +#include "lpc_def.h" #include "spi.h" #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ @@ -269,7 +270,7 @@ static void *get_spi_bar(pci_devfn_t dev) uintptr_t rcba; /* Root Complex Register Block */ uintptr_t sbase; - if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_I82801HX)) { rcba = pci_read_config32(dev, RCBA); return (void *)((rcba & 0xffffc000) + 0x3020); } @@ -1125,11 +1126,6 @@ __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_co { } -#define BIOS_CNTL 0xdc -#define BIOS_CNTL_BIOSWE (1 << 0) -#define BIOS_CNTL_BLE (1 << 1) -#define BIOS_CNTL_SMM_BWP (1 << 5) - static void spi_set_smm_only_flashing(bool enable) { if (!(CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9))) diff --git a/src/southbridge/intel/i82801dx/early_init.c b/src/southbridge/intel/i82801dx/early_init.c index 2ed7aa3f45a..d23cc1edd3b 100644 --- a/src/southbridge/intel/i82801dx/early_init.c +++ b/src/southbridge/intel/i82801dx/early_init.c @@ -12,7 +12,7 @@ void i82801dx_early_init(void) pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - pci_write_config32(dev, GPIO_BASE, GPIOBASE_ADDR | 1); + pci_write_config32(dev, GPIOBASE, GPIOBASE_ADDR | 1); pci_write_config8(dev, GPIO_CNTL, 0x10); if (ENV_RAMINIT) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 4eb73579879..c7bc06ec4c3 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -44,7 +44,7 @@ void i82801dx_lpc_setup(void); #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 +#define GPIOBASE 0x58 #define GPIO_CNTL 0x5C #define GPIOBASE_ADDR 0x0500 #define PIRQA_ROUT 0x60 diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index deb3debb81e..71f29b527e3 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -40,10 +41,10 @@ void i82801gx_lpc_setup(void) return; config = dev->chip_info; - pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec); - pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec); - pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); - pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); + pci_write_config32(d31f0, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, LPC_GEN4_DEC, config->gen4_dec); } void i82801gx_setup_bars(void) diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 1eb095f24aa..8857c2dc3dc 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 7088b64b385..e992738eb33 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -7,12 +7,9 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ -#define SPIBASE 0x3020 -#define SPIBAR16(x) RCBA16(SPIBASE + x) -#define SPIBAR32(x) RCBA32(SPIBASE + x) - #ifndef __ACPI__ #include @@ -61,38 +58,9 @@ void ich7_setup_cir(void); #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) -#define BIOS_CNTL 0xDC -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_EN (1 << 4) -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ - -#define GEN1_DEC 0x84 -#define GEN2_DEC 0x88 -#define GEN3_DEC 0x8c -#define GEN4_DEC 0x90 - /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ @@ -149,9 +117,6 @@ void ich7_setup_cir(void); #define HST_EN (1 << 0) /* Southbridge IO BARs */ - -#define GPIOBASE 0x48 - #define PMBASE 0x40 #define VCH 0x0000 /* 32bit */ @@ -214,6 +179,9 @@ void ich7_setup_cir(void); #define TCTL 0x3000 /* 8bit */ +#define SPIBAR_SPIS 0x3020 /* 16bit */ +#define SPIBAR_SPIC 0x3020 /* 16bit */ + #define D31IP 0x3100 /* 32bit */ #define D30IP 0x3104 /* 32bit */ #define D29IP 0x3108 /* 32bit */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a04b4b99e72..d69e0845ca6 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -289,9 +289,9 @@ static void i82801gx_spi_init(void) { u16 spicontrol; - spicontrol = RCBA16(SPIBASE + 2); + spicontrol = RCBA16(SPIBAR_SPIC); spicontrol &= ~(1 << 0); // SPI Access Request - RCBA16(SPIBASE + 2) = spicontrol; + RCBA16(SPIBAR_SPIC) = spicontrol; } static void i82801gx_fixups(struct device *dev) @@ -402,7 +402,7 @@ static void lpc_final(struct device *dev) spi_finalize_ops(); /* Lock SPIBAR */ - SPIBAR16(0) = SPIBAR16(0) | (1 << 15); + RCBA16(SPIBAR_SPIS) |= 1 << 15; /* BIOS Interface Lockdown */ RCBA32(0x3410) |= 1 << 0; diff --git a/src/southbridge/intel/i82801hx/Kconfig b/src/southbridge/intel/i82801hx/Kconfig new file mode 100644 index 00000000000..98bcc68326f --- /dev/null +++ b/src/southbridge/intel/i82801hx/Kconfig @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOUTHBRIDGE_INTEL_I82801HX + bool + select ACPI_COMMON_MADT_IOAPIC + select ACPI_COMMON_MADT_LAPIC + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS + select AZALIA_HDA_CODEC_SUPPORT + select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS + select INTEL_DESCRIPTOR_MODE_CAPABLE + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_GPIO + select SOUTHBRIDGE_INTEL_COMMON_HPET + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select TCO_SPACE_NOT_YET_SPLIT + select USE_WATCHDOG_ON_BOOT + select INTEL_HAS_TOP_SWAP + +if SOUTHBRIDGE_INTEL_I82801HX + +config EHCI_BAR + hex + default 0xfef00000 + +config HPET_MIN_TICKS + default 0x80 + +endif diff --git a/src/southbridge/intel/i82801hx/Makefile.mk b/src/southbridge/intel/i82801hx/Makefile.mk new file mode 100644 index 00000000000..5796eacf69f --- /dev/null +++ b/src/southbridge/intel/i82801hx/Makefile.mk @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801HX),y) + +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c +romstage-y += early_rcba.c +romstage-y += dmi_setup.c + +ramstage-y += azalia.c +ramstage-y += fadt.c +ramstage-y += i82801hx.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb.c +ramstage-y += usb_ehci.c +ramstage-y += ../common/pciehp.c + +smm-y += smihandler.c + +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801hx/include + +endif diff --git a/src/southbridge/intel/i82801hx/acpi/globalnvs.asl b/src/southbridge/intel/i82801hx/acpi/globalnvs.asl new file mode 100644 index 00000000000..7e891c90151 --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/globalnvs.asl @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Global Variables */ + +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + , 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + , 8, // 0x03 - SMI function parameter + , 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + , 8, // 0x06 - SCI function parameter + , 8, // 0x07 - SCI function parameter + , 8, // 0x08 - Global Lock function for EC + , 8, // 0x09 - Lock function parameter + , 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + , 8, // 0x10 - Power State (AC = 1) + DBGS, 8, // 0x11 - Debug State + LINX, 8, // 0x12 - Linux OS + DCKN, 8, // 0x13 - PCIe docking state + /* Thermal policy */ + Offset (0x14), + ACTT, 8, // 0x14 - active trip point + TPSV, 8, // 0x15 - passive trip point + TC1V, 8, // 0x16 - passive trip point TC1 + TC2V, 8, // 0x17 - passive trip point TC2 + TSPV, 8, // 0x18 - passive trip point TSP + TCRT, 8, // 0x19 - critical trip point + DTSE, 8, // 0x1a - Digital Thermal Sensor enable + DTS1, 8, // 0x1b - DT sensor 1 + FLVL, 8, // 0x1c - current fan level + /* Battery Support */ + Offset (0x1e), + BNUM, 8, // 0x1e - number of batteries + B0SC, 8, // 0x1f - BAT0 stored capacity + B1SC, 8, // 0x20 - BAT1 stored capacity + B2SC, 8, // 0x21 - BAT2 stored capacity + B0SS, 8, // 0x22 - BAT0 stored status + B1SS, 8, // 0x23 - BAT1 stored status + B2SS, 8, // 0x24 - BAT2 stored status + /* Processor Identification */ + Offset (0x28), + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable + PCP0, 8, // 0x2a - PDC CPU/CORE 0 + PCP1, 8, // 0x2b - PDC CPU/CORE 1 + PPCM, 8, // 0x2c - Max. PPC state + /* Super I/O & CMOS config */ + Offset (0x32), + NATP, 8, // 0x32 - + CMAP, 8, // 0x33 - + CMBP, 8, // 0x34 - + LPTP, 8, // 0x35 - LPT Port + FDCP, 8, // 0x36 - Floppy Disk Controller + RFDV, 8, // 0x37 - + HOTK, 8, // 0x38 - + RTCF, 8, // 0x39 - + UTIL, 8, // 0x3a - + ACIN, 8, // 0x3b - + /* Integrated Graphics Device */ + Offset (0x3c), + IGDS, 8, // 0x3c - IGD state (primary = 1) + TLST, 8, // 0x3d - Display Toggle List pointer + CADL, 8, // 0x3e - Currently Attached Devices List + PADL, 8, // 0x3f - Previously Attached Devices List + /* Backlight Control */ + Offset (0x64), + BLCS, 8, // 0x64 - Backlight control possible? + BRTL, 8, // 0x65 - Brightness Level + ODDS, 8, // 0x66 + /* Ambient Light Sensors */ + Offset (0x6e), + ALSE, 8, // 0x6e - ALS enable + ALAF, 8, // 0x6f - Ambient light adjustment factor + LLOW, 8, // 0x70 - LUX Low + LHIH, 8, // 0x71 - LUX High + /* EMA */ + Offset (0x78), + EMAE, 8, // 0x78 - EMA enable + EMAP, 16, // 0x79 - EMA pointer + EMAL, 16, // 0x7b - EMA length + /* MEF */ + Offset (0x82), + MEFE, 8, // 0x82 - MEF enable + /* TPM support */ + Offset (0x8c), + TPMP, 8, // 0x8c - TPM + TPME, 8, // 0x8d - TPM enable + /* SATA */ + Offset (0x96), + GTF0, 56, // 0x96 - GTF task file buffer for port 0 + GTF1, 56, // 0x9d - GTF task file buffer for port 1 + GTF2, 56, // 0xa4 - GTF task file buffer for port 2 + IDEM, 8, // 0xab - IDE mode (compatible / enhanced) + IDET, 8, // 0xac - IDE + /* Mainboard Specific (TODO move elsewhere) */ + Offset (0xf0), + DOCK, 8, // 0xf0 - Docking Status + BTEN, 8, // 0xf1 - Bluetooth Enable + , 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + +} diff --git a/src/southbridge/intel/i82801hx/acpi/ich8.asl b/src/southbridge/intel/i82801hx/acpi/ich8.asl new file mode 100644 index 00000000000..ec4602271a9 --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/ich8.asl @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel 82801Hx (ICH8) support */ + +Scope(\) +{ + // IO Trap at 0x800. SMI function in SMIF NVS variable. + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + /* SMI I/O Trap */ + Method(TRAP, 1, Serialized) + { + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler + } + + // ICH8 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) + { + Offset(0x11), + THRO, 1, // force thermal throttling + Offset(0x42), // General Purpose Control + , 1, // skip 1 bit + GPEC, 1, // TCO status + Offset(0x64), + , 9, // skip 9 more bits + SCIS, 1 // TCO DMI status + } + + // ICH8 GPIO IO mapped registers (0x1f.0 reg 0x48.l) + OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) + Field(GPIO, ByteAcc, NoLock, Preserve) + { + GU00, 8, // GPIO Use Select + GU01, 8, + GU02, 8, + GU03, 8, + Offset(0x04), // GPIO IO Select + GIO0, 8, + GIO1, 8, + GIO2, 8, + GIO3, 8, + Offset(0x0c), // GPIO Level + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, + GP07, 1, + GP08, 1, + GP09, 1, + GP10, 1, + GP11, 1, + GP12, 1, + GP13, 1, + GP14, 1, + GP15, 1, + GP16, 1, + GP17, 1, + GP18, 1, + GP19, 1, + GP20, 1, + GP21, 1, + GP22, 1, + GP23, 1, + GP24, 1, + GP25, 1, + GP26, 1, + GP27, 1, + GP28, 1, + GP29, 1, + GP30, 1, + GP31, 1, + Offset(0x18), // GPIO Blink + GB00, 8, + GB01, 8, + GB02, 8, + GB03, 8, + Offset(0x2c), // GPIO Invert + GIV0, 8, + GIV1, 8, + GIV2, 8, + GIV3, 8, + Offset(0x30), // GPIO Use Select 2 + GU04, 8, + GU05, 8, + GU06, 8, + GU07, 8, + Offset(0x34), // GPIO IO Select 2 + GIO4, 8, + GIO5, 8, + GIO6, 8, + GIO7, 8, + Offset(0x38), // GPIO Level 2 + GP32, 1, + GP33, 1, + GP34, 1, + GP35, 1, + GP36, 1, + GP37, 1, + GP38, 1, + GP39, 1, + GL05, 8, + GL06, 8, + GL07, 8 + } + + + // ICH8 Root Complex Register Block. Memory Mapped through RCBA) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) + Field(RCRB, DWordAcc, Lock, Preserve) + { + Offset(0x3404), // High Performance Timer Configuration + HPAS, 2, // Address Select + , 5, + HPTE, 1, // Address Enable + Offset(0x3418), // FD (Function Disable) + , 2, // Reserved + SA1D, 1, // SATA disable + SMBD, 1, // SMBUS disable + HDAD, 1, // Azalia disable + , 3, // Reserved (ICH8 has no UHCI #6) + US1D, 1, // UHCI #1 disable + US2D, 1, // UHCI #2 disable + US3D, 1, // UHCI #3 disable + US4D, 1, // UHCI #4 disable + US5D, 1, // UHCI #5 disable + EH2D, 1, // EHCI #2 disable + LPBD, 1, // LPC bridge disable + EH1D, 1, // EHCI #1 disable + RP1D, 1, // Root Port 1 disable + RP2D, 1, // Root Port 2 disable + RP3D, 1, // Root Port 3 disable + RP4D, 1, // Root Port 4 disable + RP5D, 1, // Root Port 5 disable + RP6D, 1, // Root Port 6 disable + , 2, // Reserved + THRD, 1, // Thermal Throttle disable + SA2D, 1, // SATA 2 disable + } + +} + +// 0:1b.0 High Definition Audio (Azalia) +#include + +// PCI Express Ports +#include + +// USB +#include "usb.asl" + +// PCI Bridge +#include "pci.asl" + +// LPC Bridge +#include "lpc.asl" + +// SATA +#include "sata.asl" + +// SMBus +#include + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + CDW1 |= 4 + Return (Arg3) + } +} diff --git a/src/southbridge/intel/i82801hx/acpi/lpc.asl b/src/southbridge/intel/i82801hx/acpi/lpc.asl new file mode 100644 index 00000000000..01b484fcb9a --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/lpc.asl @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field (LPC0, AnyAcc, NoLock, Preserve) + { + Offset (0x40), + PMBS, 16, // PMBASE + Offset (0x60), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + Offset (0x68), + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + + Offset (0x80), // IO Decode Ranges + IOD0, 8, + IOD1, 8, + } + + #include + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Name(BUF0, ResourceTemplate() + { + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) + }) + + Method (_STA, 0) // Device Status + { + Return (\HPTS(HPTE)) + } + + Method (_CRS, 0, Serialized) // Current resources + { + If (HPTE) { + CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x1000 * HPAS + } + + Return (BUF0) + } + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(MATH) // FPU + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH GPIO + }) + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + #include "acpi/superio.asl" + + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } +} diff --git a/src/southbridge/intel/i82801hx/acpi/pci.asl b/src/southbridge/intel/i82801hx/acpi/pci.asl new file mode 100644 index 00000000000..58ac8a105e6 --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/pci.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001e0000) + + Device (SLT1) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT2) + { + Name (_ADR, 0x00010000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT3) + { + Name (_ADR, 0x00020000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT6) + { + Name (_ADR, 0x00050000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (LANC) + { + Name (_ADR, 0x00080000) + Name (_PRW, Package(){ 11, 3 }) + } + + Device (LANR) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package(){ 11, 3 }) + } + + // TODO: How many slots, where? + + // PCI Interrupt Routing. + // If PICM is _not_ set, interrupts are routed over the i8259, otherwise + // over the IOAPIC. (Really? If they're above 15 they need to be routed + // fixed over the IOAPIC?) + + Method (_PRT) + { + #include "acpi/ich8_pci_irqs.asl" + } + +} diff --git a/src/southbridge/intel/i82801hx/acpi/sata.asl b/src/southbridge/intel/i82801hx/acpi/sata.asl new file mode 100644 index 00000000000..7c521dd2155 --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/sata.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel SATA Controller 0:1f.2 + +Device (AHC1) +{ + Name (_ADR, 0x001f0002) +} diff --git a/src/southbridge/intel/i82801hx/acpi/usb.asl b/src/southbridge/intel/i82801hx/acpi/usb.asl new file mode 100644 index 00000000000..26c7132b4f1 --- /dev/null +++ b/src/southbridge/intel/i82801hx/acpi/usb.asl @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel ICH8 USB support */ +/* ICH8-M has 5 UHCI controllers and 2 EHCI controllers: + * UHCI #1: D29F0, UHCI #2: D29F1, UHCI #3: D29F2 + * UHCI #4: D26F0, UHCI #5: D26F1 + * EHCI #1: D29F7, EHCI #2: D26F7 + */ + +// USB Controller 0:1d.0 + +Device (USB1) +{ + Name(_ADR, 0x001d0000) + + OperationRegion(U01P, PCI_Config, 0, 256) + Field(U01P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U1WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + U1WE = 3 + } Else { + U1WE = 0 + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} + + +// USB Controller 0:1d.1 + +Device (USB2) +{ + Name(_ADR, 0x001d0001) + + OperationRegion(U02P, PCI_Config, 0, 256) + Field(U02P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U2WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + U2WE = 3 + } Else { + U2WE = 0 + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// USB Controller 0:1d.2 + +Device (USB3) +{ + Name(_ADR, 0x001d0002) + + OperationRegion(U03P, PCI_Config, 0, 256) + Field(U03P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U3WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + U3WE = 3 + } Else { + U3WE = 0 + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// EHCI Controller 0:1d.7 + +Device (EHC1) +{ + Name(_ADR, 0x001d0007) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + + +// USB Controller 0:1a.0 + +Device (USB4) +{ + Name(_ADR, 0x001a0000) + + OperationRegion(U01P, PCI_Config, 0, 256) + Field(U01P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U1WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + U1WE = 3 + } Else { + U1WE = 0 + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} + + +// USB Controller 0:1a.1 + +Device (USB5) +{ + Name(_ADR, 0x001a0001) + + OperationRegion(U02P, PCI_Config, 0, 256) + Field(U02P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U2WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + U2WE = 3 + } Else { + U2WE = 0 + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// EHCI Controller 0:1a.7 + +Device (EHC2) +{ + Name(_ADR, 0x001a0007) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} diff --git a/src/southbridge/intel/i82801hx/azalia.c b/src/southbridge/intel/i82801hx/azalia.c new file mode 100644 index 00000000000..efd521fc00c --- /dev/null +++ b/src/southbridge/intel/i82801hx/azalia.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "i82801hx.h" + +static int codec_detect(u8 *base) +{ + u32 reg32; + + if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + + if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + HDA_STATESTS_REG); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec not found, put HDA back in reset */ + azalia_enter_reset(base); + printk(BIOS_DEBUG, "Azalia: No codec!\n"); + return 0; +} + +static void azalia_init(struct device *dev) +{ + u8 *base; + struct resource *res; + u32 codec_mask; + + // ESD + pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16); + + // Link1 description + pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16); + + // Port VC0 Resource Control Register + pci_update_config32(dev, 0x114, ~0x000000ff, 1); + + // VCi traffic class + pci_or_config8(dev, 0x44, 7 << 0); // TC7 + + // VCi Resource Control + pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ + + /* Set Bus Master */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status + + /* Lock some R/WO bits by writing their current value. */ + pci_update_config32(dev, 0x74, ~0, 0); + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + // NOTE this will break as soon as the Azalia gets a bar above 4G. + // Is there anything we can do about it? + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); + azalia_codecs_init(base, codec_mask); + } +} + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .ops_pci = &pci_dev_ops_pci, +}; + +/* ICH8/ICH8-M HD Audio */ +static const struct pci_driver i82801hx_azalia __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VID_INTEL, + .device = PCI_DID_INTEL_82801HB_HD_AUDIO, +}; diff --git a/src/southbridge/intel/i82801hx/bootblock.c b/src/southbridge/intel/i82801hx/bootblock.c new file mode 100644 index 00000000000..e49cafb3a5c --- /dev/null +++ b/src/southbridge/intel/i82801hx/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "i82801hx.h" + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetching_and_caching(); + + i82801hx_early_init(); + i82801hx_lpc_setup(); +} diff --git a/src/southbridge/intel/i82801hx/cfr.h b/src/southbridge/intel/i82801hx/cfr.h new file mode 100644 index 00000000000..9e69e5a2dd5 --- /dev/null +++ b/src/southbridge/intel/i82801hx/cfr.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs for sb/i82801hx + */ + +#ifndef SB_INTEL_I82801HX_CFR_H +#define SB_INTEL_I82801HX_CFR_H + +#include +#include + +/* Power state after power loss */ +static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ + .opt_name = "power_on_after_fail", + .ui_name = "Restore AC Power Loss", + .ui_helptext = "Specify what to do when power is re-applied after a power loss.", + .default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE, + .values = (const struct sm_enum_value[]) { + { "Power off (S5)", MAINBOARD_POWER_OFF }, + { "Power on (S0)", MAINBOARD_POWER_ON }, + { "Previous state", MAINBOARD_POWER_KEEP }, + SM_ENUM_VALUE_END }, +}); + +enum { + SATA_MODE_AHCI, + SATA_MODE_IDE_NATIVE, +}; + +/* SATA controller mode */ +static const struct sm_object sata_mode = SM_DECLARE_ENUM({ + .opt_name = "sata_mode", + .ui_name = "SATA Mode", + .ui_helptext = "Specify mode of the SATA controller.", + .default_value = SATA_MODE_AHCI, + .values = (const struct sm_enum_value[]) { + { "AHCI", SATA_MODE_AHCI }, + { "IDE", SATA_MODE_IDE_NATIVE }, + SM_ENUM_VALUE_END }, +}); + +enum { + NMI_OFF, + NMI_ON, +}; + +/* Non-maskable interrupts */ +static const struct sm_object nmi = SM_DECLARE_ENUM({ + .opt_name = "nmi", + .ui_name = "Non-maskable Interrupts", + .ui_helptext = "Enable or disable non-maskable interrupts.", + .default_value = NMI_ON, + .values = (const struct sm_enum_value[]) { + { "Disabled", NMI_OFF }, + { "Enabled", NMI_ON }, + SM_ENUM_VALUE_END }, +}); + +#endif /* SB_INTEL_I82801HX_CFR_H */ diff --git a/src/southbridge/intel/i82801hx/chip.h b/src/southbridge/intel/i82801hx/chip.h new file mode 100644 index 00000000000..db3849366f3 --- /dev/null +++ b/src/southbridge/intel/i82801hx/chip.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_I82801HX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801HX_CHIP_H + +#include +#include + +enum { + THTL_DEF = 0, + THTL_87_5 = 1, + THTL_75_0 = 2, + THTL_62_5 = 3, + THTL_50_0 = 4, + THTL_37_5 = 5, + THTL_25_0 = 6, + THTL_12_5 = 7 +}; + +struct southbridge_intel_i82801hx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * GPI Routing configuration + * + * Only the lower two bits have a meaning: + * 00: No effect + * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + * 10: SCI (if corresponding GPIO_EN bit is also set) + * 11: reserved + */ + uint8_t gpi0_routing; + uint8_t gpi1_routing; + uint8_t gpi2_routing; + uint8_t gpi3_routing; + uint8_t gpi4_routing; + uint8_t gpi5_routing; + uint8_t gpi6_routing; + uint8_t gpi7_routing; + uint8_t gpi8_routing; + uint8_t gpi9_routing; + uint8_t gpi10_routing; + uint8_t gpi11_routing; + uint8_t gpi12_routing; + uint8_t gpi13_routing; + uint8_t gpi14_routing; + uint8_t gpi15_routing; + + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + + /* IDE configuration */ + bool ide_enable_primary; + bool ide_enable_secondary; + + uint8_t sata_port_map : 6; + uint8_t sata_hotplug_map : 6; + bool sata_clock_request; + bool sata_traffic_monitor; + + bool c4onc3_enable; + bool c5_enable; + bool c6_enable; + + unsigned int throttle_duty : 3; + + /* Bit mask to tell whether a PCIe slot is implemented as slot. */ + unsigned int pcie_slot_implemented : 6; + + /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ + struct { + uint8_t value : 8; + uint8_t scale : 2; + } pcie_power_limits[6]; + + bool pcie_hotplug_map[6]; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; +}; + +#endif /* SOUTHBRIDGE_INTEL_I82801HX_CHIP_H */ diff --git a/src/southbridge/intel/i82801hx/dmi_setup.c b/src/southbridge/intel/i82801hx/dmi_setup.c new file mode 100644 index 00000000000..41eec7cbcd5 --- /dev/null +++ b/src/southbridge/intel/i82801hx/dmi_setup.c @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel ICH8-M (82801HBM) Southbridge - DMI Link Setup + * Reverse-engineered from ThinkPad X61 Phoenix BIOS + * + * Configures the DMI (Direct Media Interface) virtual channels + * on the southbridge side. Must be paired with northbridge DMI setup. + * + * Reference: coreboot ICH9 (i82801ix) dmi_setup.c + */ + +#include +#include +#include +#include +#include + +/* VC1 Port Arbitration Table - time-based weighted round robin + * Copied from coreboot ICH9 dmi_setup.c - identical for ICH8-M */ +static const u8 vc1_pat[] = { + 0x0f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xf0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0f, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x0f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xf0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0f, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +/* + * i82801hx_dmi_setup() - Configure DMI link (southbridge side) + * + * Sets up virtual channels VC0/VC1 in the RCBA, programs the + * VC1 port arbitration table, configures component IDs, and + * enables ASPM. + * + * BIOS equivalent: observed in bioscode_7.rom DMI init + * coreboot equivalent: i82801ix_dmi_setup() + */ +void i82801hx_dmi_setup(void) +{ + size_t i; + u32 reg32; + + /* + * VC1 capability: set WRR count. + * RCBA offset 0x001C, bits [22:16] = 0x12 + */ + RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f << 16)) | (0x12 << 16); + + /* CIR (Chipset Initialization Registers) */ + RCBA32(RCBA_CIR1) = 0x00109000; + RCBA16(RCBA_CIR3) = 0x060b; + RCBA32(RCBA_CIR2) = 0x86000040; + RCBA16(RCBA_CIR4) = 0x2008; + RCBA8(RCBA_BCR) = 0x45; + /* Vendor BIOS masked writes: clear bit 7, set high-word mask 0x0d00. */ + /* TODO: different on desktop */ + RCBA32(RCBA_CIR6) = (RCBA32(RCBA_CIR6) & ~((1 << 7) | (0xff00 << 16))) | + (0x0d00 << 16); + + /* Set VC1 virtual channel id to 1. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24); + /* Enable TC7 traffic on VC1. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7); + /* Disable TC7-TC1 traffic on VC0. */ + RCBA32(RCBA_V0CTL) &= ~(0x7f << 1); + + /* Set table type to time-based WRR. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17); + + /* Program port arbitration table */ + for (i = 0; i < sizeof(vc1_pat); i++) + RCBA8(RCBA_PAT + i) = vc1_pat[i]; + + /* Load port arbitration table */ + RCBA32(RCBA_V1CTL) |= (1 << 16); + + /* Enable VC1 */ + RCBA32(RCBA_V1CTL) |= (1 << 31); + + /* + * RCRB setup: + * - Set component ID to 2 (southbridge; northbridge is 1) + * - Set target port and component ID for northbridge + * - Set DMIBAR as target RCRB base + */ + RCBA8(RCBA_ESD + 2) = 2; /* SB component ID = 2 */ + RCBA8(RCBA_ULD + 3) = 1; /* Target port = 1 */ + RCBA8(RCBA_ULD + 2) = 1; /* Target component ID = 1 */ + RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; + + /* + * Enable ASPM (Active State Power Management). + * ICH8-M is always mobile, so enable L0s + L1. + */ + reg32 = RCBA32(RCBA_DMC); + /* Enable mobile specific power saving (set this first). */ + reg32 = (reg32 & ~(3 << 10)) | (1 << 10); + RCBA32(RCBA_DMC) = reg32; + /* Enable DMI power savings. */ + reg32 |= (1 << 19); + RCBA32(RCBA_DMC) = reg32; + + /* Advertise L0s and L1 support */ + RCBA32(RCBA_LCAP) |= (3 << 10); + /* Enable L0s and L1 */ + RCBA32(RCBA_LCTL) |= (3 << 0); +} + +/* + * i82801hx_dmi_poll_vc1() - Wait for VC1 negotiation to complete + * + * Called after both NB and SB sides have enabled VC1. + * Polls the VC1 status register until negotiation finishes. + * + * coreboot equivalent: i82801ix_dmi_poll_vc1() + */ +void i82801hx_dmi_poll_vc1(void) +{ + int timeout; + + /* Wait for VC1 negotiation pending bit to clear */ + timeout = 0x7ffff; + printk(BIOS_DEBUG, "ICH8-M waits for VC1 negotiation... "); + while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) + ; + if (!timeout) + printk(BIOS_DEBUG, "timeout!\n"); + else + printk(BIOS_DEBUG, "done.\n"); + + /* + * Check for x2 DMI link width. + * RCBA_LSTS bits [9:4] = negotiated link width. + * If x2, apply workaround settings. + */ + if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) { + printk(BIOS_DEBUG, "x2 DMI link detected.\n"); + RCBA32(RCBA_CIR6) = (RCBA32(RCBA_CIR6) & ~(7 << 21)) | (3 << 21); + RCBA16(0x20c4) |= (1 << 15); + RCBA16(0x20e4) |= (1 << 15); + } + + /* Wait for port arbitration table update */ + timeout = 0x7ffff; + printk(BIOS_DEBUG, "ICH8-M waits for port arbitration table update... "); + while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) + ; + if (!timeout) + printk(BIOS_DEBUG, "timeout!\n"); + else + printk(BIOS_DEBUG, "done.\n"); +} diff --git a/src/southbridge/intel/i82801hx/early_init.c b/src/southbridge/intel/i82801hx/early_init.c new file mode 100644 index 00000000000..6bf951784b5 --- /dev/null +++ b/src/southbridge/intel/i82801hx/early_init.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel ICH8-M (82801HBM) Southbridge - Early Initialization + * + * Reference: coreboot ICH9 (i82801ix) early_init.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +void i82801hx_lpc_setup(void) +{ + /* Configure serial IRQ: continuous mode, 21 frames */ + pci_write_config8(D31F0, D31F0_SERIRQ_CNTL, 0xd0); + + /* LPC I/O decode ranges */ + pci_write_config16(D31F0, D31F0_LPC_IODEC, 0x0010); + + /* + * Enable LPC I/O decode for: + * CNF2 (0x4E/0x4F) - SuperIO config + * CNF1 (0x2E/0x2F) - SuperIO config + * MC (0x62/0x66) - Embedded Controller + * KBC (0x60/0x64) - Keyboard Controller + * COMB (0x2F8) - Serial port + * COMA (0x3F8) - Serial port + */ + pci_write_config16(D31F0, D31F0_LPC_EN, + LPC_EN_CNF2 | LPC_EN_CNF1 | LPC_EN_MC | LPC_EN_KBC | LPC_EN_COMB | + LPC_EN_COMA); + + /* Generic decode ranges from chip config (devicetree). */ + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801hx_config *config; + + if (dev && dev->chip_info) { + config = dev->chip_info; + pci_write_config32(D31F0, D31F0_GEN1_DEC, config->gen1_dec); + pci_write_config32(D31F0, D31F0_GEN2_DEC, config->gen2_dec); + pci_write_config32(D31F0, D31F0_GEN3_DEC, config->gen3_dec); + pci_write_config32(D31F0, D31F0_GEN4_DEC, config->gen4_dec); + } +} + +/* SATA mode is configured by the ramstage sata.c driver. */ +int i82801hx_detect_s3_resume(void) +{ + uint16_t pm1_cnt; + uint8_t gen_pmcon_3; + + /* Check GEN_PMCON_3 for power failure (would invalidate S3) */ + gen_pmcon_3 = pci_read_config8(D31F0, D31F0_GEN_PMCON_3); + if (gen_pmcon_3 & (1 << 1)) /* PWR_FLR - power failure */ + return 0; + + /* Read PM1_CNT to check sleep type */ + pm1_cnt = inw(DEFAULT_PMBASE + PM1_CNT); + + /* SLP_TYP field is bits [12:10] */ + uint8_t slp_typ = (pm1_cnt >> 10) & 7; + + /* SLP_TYP = 5 means S3 (STR) */ + return (slp_typ == 5) ? 1 : 0; +} + +#define TCO_BASE 0x60 + +void i82801hx_early_init(void) +{ + /* Set up RCBA (Root Complex Base Address, D31:F0 offset 0xF0) */ + pci_write_config32(D31F0, D31F0_RCBA, RCBA_BASE | 1); + + /* Set up PMBASE (Power Management Base, D31:F0 offset 0x40) */ + pci_write_config32(D31F0, D31F0_PMBASE, DEFAULT_PMBASE); + /* Enable ACPI I/O decode (D31:F0 offset 0x44 bit 7) */ + pci_write_config8(D31F0, D31F0_ACPI_CNTL, 0x80); + + /* Set up GPIOBASE (D31:F0 offset 0x48) */ + pci_write_config32(D31F0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + /* Enable GPIO I/O decode (D31:F0 offset 0x4C bit 4) */ + pci_or_config8(D31F0, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* + * Reset TCO watchdog. + * If the watchdog fires before we get here, the system will + * keep rebooting. Clear TCO status to prevent this. + */ + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(RCBA_GCS) = RCBA32(RCBA_GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + + /* + * Enable upper 128 bytes of CMOS (RCBA offset 0x3400). + * Bit 2 enables the extended CMOS range. + */ + RCBA32(RCBA_RC) = (1 << 2); +} diff --git a/src/southbridge/intel/i82801hx/early_rcba.c b/src/southbridge/intel/i82801hx/early_rcba.c new file mode 100644 index 00000000000..424a5393fcf --- /dev/null +++ b/src/southbridge/intel/i82801hx/early_rcba.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "i82801hx.h" + +void southbridge_configure_default_intmap(void) +{ + /* + * For the ICH8 internal PCI functions, provide a reasonable + * default IRQ mapping that utilizes only PIRQ A to D. Higher + * PIRQs are sometimes used for other on-board chips that + * require an edge triggered interrupt which is not shareable. + */ + + /* + * We use a linear mapping for the pin numbers. They are not + * physical pins, and thus, have no relation between the dif- + * ferent devices. Only rule we must obey is that a single- + * function device has to use pin A. + */ + RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SMIP) | (INTB << D31IP_SIP) | + (INTA << D31IP_IDEP); + RCBA32(D30IP) = (INTA << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P) | (INTC << D29IP_U3P) | (INTB << D29IP_U2P) | + (INTA << D29IP_U1P); + RCBA32(D28IP) = (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | (INTD << D28IP_P4IP) | + (INTC << D28IP_P3IP) | (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P) | (INTB << D26IP_U5P) | (INTA << D26IP_U4P); + RCBA32(D25IP) = (INTA << D25IP_LIP); + + /* + * PIRQ allocation rationale (mirrors bd82x6x logic): + * + * o Interrupts of the PCIe root ports are only about + * events at the ports, not downstream devices. So we + * don't expect many interrupts there and ignore them. + * o We don't expect to talk constantly to the SMBus or + * thermal device, so ignore those too. + * + * The functions that might matter first: + * + * D31IP_IDEP IDE -> PIRQ A + * D31IP_SIP SATA -> PIRQ A (MSI capable in AHCI mode) + * D29IP_E1P EHCI 1 -> PIRQ C + * D27IP_ZIP HDA -> PIRQ D (MSI capable) + * D26IP_E2P EHCI 2 -> PIRQ D + * D25IP_LIP GbE -> PIRQ B (MSI capable) + * + * D31IP_SMIP SMBus -> PIRQ B + * D31IP_TTIP Thermal -> PIRQ B + * D30IP_PIP PCI Brg -> PIRQ A + * D28IP_* PCIe RP -> PIRQ A-D (MSI capable) + */ +#define _none 0 + DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB); + DIR_ROUTE(D30IR, PIRQA, _none, _none, _none); + DIR_ROUTE(D29IR, PIRQC, _none, _none, _none); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D26IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D25IR, PIRQB, _none, _none, _none); +#undef _none +} diff --git a/src/southbridge/intel/i82801hx/fadt.c b/src/southbridge/intel/i82801hx/fadt.c new file mode 100644 index 00000000000..795a4c48a78 --- /dev/null +++ b/src/southbridge/intel/i82801hx/fadt.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; + + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->duty_offset = 1; + fadt->duty_width = 3; + + fill_fadt_extended_pm_io(fadt); + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK; +} diff --git a/src/southbridge/intel/i82801hx/i82801hx.c b/src/southbridge/intel/i82801hx/i82801hx.c new file mode 100644 index 00000000000..610f9e6ec32 --- /dev/null +++ b/src/southbridge/intel/i82801hx/i82801hx.c @@ -0,0 +1,627 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Intel ICH8-M (82801HBM) Southbridge - Main Ramstage Driver + * + * ICH8-M differences from ICH9: + * - 5 UHCI controllers (not 6) + * - 3 SATA ports (not 6) + * - LAN disable is FDSW_LAND (RCBA 0x3420 bit 0) + * - ICH8-M is always mobile + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "i82801hx.h" + +#define NMI_OFF 0 + +/* ================================================================== */ +/* chip_operations: enable_dev callback */ +/* ================================================================== */ + +/* + * i82801hx_hide_devfn() - Disable a PCI function via the FD register. + * + * Sets the corresponding bit in RCBA FD to hide the device, + * based on its devfn. Modeled on bd82x6x pch_hide_devfn(). + */ +static void i82801hx_hide_devfn(unsigned int devfn) +{ + switch (devfn) { + case PCI_DEVFN(25, 0): /* GbE LAN */ + RCBA32_OR(RCBA_FDSW, FDSW_LAND); + break; + case PCI_DEVFN(31, 2): /* SATA #1 */ + RCBA32_OR(RCBA_FD, FD_SAD1); + break; + case PCI_DEVFN(31, 5): /* SATA #2 */ + RCBA32_OR(RCBA_FD, FD_SAD2); + break; + case PCI_DEVFN(31, 6): /* Thermal */ + RCBA32_OR(RCBA_FD, FD_TTD); + break; + case PCI_DEVFN(29, 0): /* UHCI #1 */ + RCBA32_OR(RCBA_FD, FD_U1D); + break; + case PCI_DEVFN(29, 1): /* UHCI #2 */ + RCBA32_OR(RCBA_FD, FD_U2D); + break; + case PCI_DEVFN(29, 2): /* UHCI #3 */ + RCBA32_OR(RCBA_FD, FD_U3D); + break; + case PCI_DEVFN(29, 7): /* EHCI #1 */ + RCBA32_OR(RCBA_FD, FD_EHCI1D); + break; + case PCI_DEVFN(26, 0): /* UHCI #4 */ + RCBA32_OR(RCBA_FD, FD_U4D); + break; + case PCI_DEVFN(26, 1): /* UHCI #5 */ + RCBA32_OR(RCBA_FD, FD_U5D); + break; + case PCI_DEVFN(26, 7): /* EHCI #2 */ + RCBA32_OR(RCBA_FD, FD_EHCI2D); + break; + case PCI_DEVFN(27, 0): /* HD Audio */ + RCBA32_OR(RCBA_FD, FD_HDAD); + break; + case PCI_DEVFN(28, 0): /* PCIe Root Port 1 */ + RCBA32_OR(RCBA_FD, FD_PE1D); + break; + case PCI_DEVFN(28, 1): /* PCIe Root Port 2 */ + RCBA32_OR(RCBA_FD, FD_PE2D); + break; + case PCI_DEVFN(28, 2): /* PCIe Root Port 3 */ + RCBA32_OR(RCBA_FD, FD_PE3D); + break; + case PCI_DEVFN(28, 3): /* PCIe Root Port 4 */ + RCBA32_OR(RCBA_FD, FD_PE4D); + break; + case PCI_DEVFN(28, 4): /* PCIe Root Port 5 */ + RCBA32_OR(RCBA_FD, FD_PE5D); + break; + case PCI_DEVFN(28, 5): /* PCIe Root Port 6 */ + RCBA32_OR(RCBA_FD, FD_PE6D); + break; + } +} + +static void i82801hx_enable_device(struct device *dev) +{ + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + i82801hx_hide_devfn(dev->path.pci.devfn); + } else { + /* Enable SERR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); + } +} + +/* ================================================================== */ +/* Chipset Init Registers (CIR) */ +/* ================================================================== */ + +static void i82801hx_early_settings(void) +{ + /* + * Vendor BIOS 2B_0.rom @ 0xd204 programs these RCBA/CIR bits as a + * table of 16-bit masked writes. ICH9 coreboot used CIR8=2 and set + * both CIR10 bits 16/17; the X61 ICH8-M vendor code uses CIR8=1 and + * explicitly clears CIR10 bit 17. Match the board firmware here. + */ + RCBA32_OR(RCBA_GCS, (1 << 6) | (1 << 5)); + RCBA32_AND_OR(RCBA_CIR8, ~(0x3 << 0), 0x1 << 0); + RCBA32_AND_OR(RCBA_CIR9, ~(0x3 << 26), 0x2 << 26); + RCBA32_AND_OR(RCBA_CIR7, ~(0xf << 16), 0x5 << 16); + RCBA32_AND_OR(RCBA_CIR13, ~(0xf << 16), 0x5 << 16); + RCBA32_OR(RCBA_CIR5, (1 << 0)); + RCBA32_AND_OR(RCBA_CIR10, ~(1 << 17), 0); +} + +/* ================================================================== */ +/* chip_operations: init callback */ +/* ================================================================== */ + +static void i82801hx_init(void *chip_info) +{ + printk(BIOS_DEBUG, "Initializing i82801hx southbridge...\n"); + + /* Intel-required chipset init registers. */ + i82801hx_early_settings(); + + /* PCIe root port setup. */ + i82801hx_pcie_init(); + + /* Reset watchdog timer. */ +#if !CONFIG(HAVE_SMI_HANDLER) + outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ +#endif + outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ +} + +/* ================================================================== */ +/* LPC device_operations: .init callback */ +/* ================================================================== */ + +/* + * Wrappers for functions from lpc.c and lpc_late.c that need a + * struct device * context (for chip_info access, etc.) + */ + +static void lpc_enable_apic(struct device *dev) +{ + /* Enable IOAPIC via RCBA OIC register. */ + i82801hx_enable_ioapic(); + + /* Lock maximum redirection entries (MRE), R/WO register. */ + ioapic_lock_max_vectors(IO_APIC_ADDR); + + /* Register the IOAPIC with the coreboot device model. */ + register_new_ioapic_gsi0(IO_APIC_ADDR); +} + +static void lpc_enable_serial_irqs(struct device *dev) +{ + /* + * SERIRQ: bit 7 = enable, bit 6 = continuous mode, 4 clocks as start frame pulse width + */ + pci_write_config8(dev, D31F0_SERIRQ_CNTL, (1 << 7) | (1 << 6) | (0 << 0)); +} + +static void lpc_pirq_init(struct device *dev) +{ + struct device *irq_dev; + struct southbridge_intel_i82801hx_config *config = dev->chip_info; + + pci_write_config8(dev, D31F0_PIRQA_ROUT, config->pirqa_routing); + pci_write_config8(dev, D31F0_PIRQB_ROUT, config->pirqb_routing); + pci_write_config8(dev, D31F0_PIRQC_ROUT, config->pirqc_routing); + pci_write_config8(dev, D31F0_PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, D31F0_PIRQE_ROUT, config->pirqe_routing); + pci_write_config8(dev, D31F0_PIRQF_ROUT, config->pirqf_routing); + pci_write_config8(dev, D31F0_PIRQG_ROUT, config->pirqg_routing); + pci_write_config8(dev, D31F0_PIRQH_ROUT, config->pirqh_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin = 0, int_line = 0; + + if (!is_enabled_pci(irq_dev)) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = config->pirqa_routing; + break; + case 2: /* INTB# */ + int_line = config->pirqb_routing; + break; + case 3: /* INTC# */ + int_line = config->pirqc_routing; + break; + case 4: /* INTD# */ + int_line = config->pirqd_routing; + break; + } + + if (!int_line) + continue; + + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } +} + +static void lpc_gpi_routing(struct device *dev) +{ + struct southbridge_intel_i82801hx_config *config = dev->chip_info; + u32 reg32 = 0; + + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; + reg32 |= (config->gpi10_routing & 0x03) << 20; + reg32 |= (config->gpi11_routing & 0x03) << 22; + reg32 |= (config->gpi12_routing & 0x03) << 24; + reg32 |= (config->gpi13_routing & 0x03) << 26; + reg32 |= (config->gpi14_routing & 0x03) << 28; + reg32 |= (config->gpi15_routing & 0x03) << 30; + + pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); +} + +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801hx_config *config = lpc_dev->chip_info; + return config->c5_enable; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801hx_config *config = lpc_dev->chip_info; + return config->c6_enable; +} + +static void lpc_power_options(struct device *dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + struct southbridge_intel_i82801hx_config *config = dev->chip_info; + + /* + * Enable USB transient disconnect detect and global reset on writes + * to the CF9 reset control port. The vendor BIOS sets D31:F0 + * offset 0xad bits [1:0] to 3. + */ + pci_or_config32(dev, D31F0_PMIR, + PMIR_USB_TRANSIENT_DISCONNECT | PMIR_CF9GR); + + /* + * Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. + */ + const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON); + + reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); + reg8 &= 0xfe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg8 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg8 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg8 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg8 |= GEN_PMCON_3_SLP_S4_MAW; /* SLP_S4# minimum assertion width. */ + reg8 &= ~GEN_PMCON_3_SLP_S4_STRETCH; + + pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1); + reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ + reg16 |= (1 << 2); /* CLKRUN_EN - Mobile/Ultra only */ + reg16 |= (1 << 3); /* Speedstep Enable - Mobile/Ultra only */ + reg16 |= (1 << 5); /* CPUSLP_EN Desktop only */ + + if (config->c4onc3_enable) + reg16 |= (1 << 7); + + reg16 |= (1 << 10); /* BIOS_PCI_EXP_EN - Desktop/Mobile only */ + if (CONFIG(DEBUG_PERIODIC_SMI)) + reg16 |= (3 << 0); /* Periodic SMI every 8s */ + if (southbridge_support_c5()) + reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ + pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); + + /* Set exit timings for C5/C6. */ + if (southbridge_support_c5()) { + reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); + reg8 &= ~((7 << 3) | (7 << 0)); + if (southbridge_support_c6()) + reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, + 95-102us DPRSTP# to STP_CPU# */ + else + reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#, + 34-40us DPRSTP# to STP_CPU# */ + pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8); + } + + /* Set the board's GPI routing. */ + lpc_gpi_routing(dev); + + pmbase = pci_read_config16(dev, D31F0_PMBASE) & 0xfffe; + + outl(config->gpe0_en, pmbase + GPE0_EN); + outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + + /* Set up power management block and determine sleep mode */ + reg16 = inw(pmbase + PM1_STS); + outw(reg16, pmbase + PM1_STS); /* Clear status bits. */ + + /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */ + reg32 = inl(pmbase + 0x10); + reg32 &= ~(7 << 5); + reg32 |= (config->throttle_duty & 7) << 5; + outl(reg32, pmbase + 0x10); +} + +static void lpc_configure_cstates(struct device *dev) +{ + /* Enable Popup & Popdown */ + pci_or_config8(dev, D31F0_C5_ENABLE, (1 << 4) | (1 << 3) | (1 << 2)); + + /* Set Deeper Sleep configuration to recommended values */ + pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0)); +} + +static void lpc_rtc_init(struct device *dev) +{ + u8 reg8; + int rtc_failed; + + reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8); + } + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + + cmos_init(rtc_failed); +} + +static void enable_clock_gating(void) +{ + u32 reg32; + + /* Enable DMI dynamic clock gating. */ + RCBA32(RCBA_DMIC) |= 3; + + /* Enable Clock Gating for most devices. */ + reg32 = RCBA32(RCBA_CG); + reg32 |= (1 << 31); /* LPC dynamic clock gating */ + /* USB UHCI dynamic clock gating: */ + reg32 |= (1 << 29) | (1 << 28); + /* SATA dynamic clock gating [0-3]: */ + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 23); /* LAN static clock gating (if LAN disabled) */ + reg32 |= (1 << 22); /* HD audio dynamic clock gating */ + reg32 &= ~(1 << 21); /* No HD audio static clock gating */ + reg32 &= ~(1 << 20); /* No USB EHCI static clock gating */ + reg32 |= (1 << 19); /* USB EHCI dynamic clock gating */ + /* More SATA dynamic clock gating [4-5]: */ + reg32 |= (1 << 18) | (1 << 17); + reg32 |= (1 << 16); /* PCI dynamic clock gating */ + /* PCIe, DMI dynamic clock gating: */ + reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1); + reg32 |= (1 << 0); /* PCIe root port static clock gating */ + RCBA32(RCBA_CG) = reg32; + + /* Enable SPI dynamic clock gating. */ + RCBA32(0x38c0) |= 7; +} + +static void i82801hx_set_acpi_mode(void) +{ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_ACPI_DISABLE); + else + apm_control(APM_CNT_ACPI_ENABLE); +} + +static void lpc_init(struct device *dev) +{ + printk(BIOS_DEBUG, "i82801hx: %s\n", __func__); + + /* IO APIC initialization. */ + lpc_enable_apic(dev); + + lpc_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + lpc_pirq_init(dev); + + /* Setup power options. */ + lpc_power_options(dev); + + /* Configure Cx state registers (ICH8-M is always mobile). */ + lpc_configure_cstates(dev); + + /* Initialize the real time clock. */ + lpc_rtc_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Enable HPET (common: RCBA_HPTC enable + start counter). + * The vendor BIOS also sets bit 2 of RCBA_RC (0x3400) at this point. */ + enable_hpet(); + RCBA8(RCBA_RC) |= (1 << 2); + + /* Initialize Clock Gating */ + enable_clock_gating(); + + setup_i8259(); + + /* The OS should do this? */ + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); + + i82801hx_set_acpi_mode(); +} + +/* ================================================================== */ +/* LPC device_operations: .final callback */ +/* ================================================================== */ + +static void lpc_final(struct device *dev) +{ + /* Lock the Function Disable register. */ + RCBA32_OR(RCBA_FDSW, (1 << 7)); + + /* Lock UHCI remap register (write current value back = R/WO lock). */ + RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); + + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); +} + +/* ================================================================== */ +/* LPC device_operations: .read_resources callback */ +/* ================================================================== */ + +static void i82801hx_lpc_read_resources(struct device *dev) +{ + /* + * I/O Resources + * + * 0x0000 - 0x000f....ISA DMA + * 0x0010 - 0x001f....ISA DMA aliases + * 0x0020 ~ 0x003d....PIC + * 0x002e - 0x002f....Maybe Super I/O + * 0x0040 - 0x0043....Timer + * 0x004e - 0x004f....Maybe Super I/O + * 0x0050 - 0x0053....Timer aliases + * 0x0061.............NMI_SC + * 0x0070.............NMI_EN (readable in alternative access mode) + * 0x0070 - 0x0077....RTC + * 0x0080 - 0x008f....ISA DMA + * 0x0090 ~ 0x009f....ISA DMA aliases + * 0x0092.............Fast A20 and Init + * 0x00a0 ~ 0x00bd....PIC + * 0x00b2 - 0x00b3....APM + * 0x00c0 ~ 0x00de....ISA DMA + * 0x00c1 ~ 0x00df....ISA DMA aliases + * 0x00f0.............Coprocessor Error + * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit) + * 0x04d0 - 0x04d1....PIC + * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) + * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) + * 0x05c0 - 0x05ff....SB GPIO cont. (mobile only) + * 0x0cf8 - 0x0cff....PCI + * 0x0cf9.............Reset Control + */ + + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff000000; + res->size = 0x01000000; /* 16 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/* ================================================================== */ +/* ACPI support */ +/* ================================================================== */ + +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + +static void southbridge_fill_ssdt(const struct device *device) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + struct southbridge_intel_i82801hx_config *chip = dev->chip_info; + + intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 6); + intel_acpi_gen_def_acpi_pirq(device); +} + +/* ================================================================== */ +/* LPC PCI device driver registration */ +/* ================================================================== */ + +static struct device_operations device_ops = { + .read_resources = i82801hx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, + .init = lpc_init, + .final = lpc_final, + .scan_bus = scan_static_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_82801HBM_LPC, + PCI_DID_INTEL_82801HEM_LPC, + 0 +}; + +static const struct pci_driver ich8_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; + +/* ================================================================== */ +/* chip_operations */ +/* ================================================================== */ + +struct chip_operations southbridge_intel_i82801hx_ops = { + .name = "Intel ICH8-M (82801HBM) Series Southbridge", + .enable_dev = i82801hx_enable_device, + .init = i82801hx_init, +}; diff --git a/src/southbridge/intel/i82801hx/i82801hx.h b/src/southbridge/intel/i82801hx/i82801hx.h new file mode 100644 index 00000000000..83c1603f12c --- /dev/null +++ b/src/southbridge/intel/i82801hx/i82801hx.h @@ -0,0 +1,476 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_I82801HX_I82801HX_H +#define SOUTHBRIDGE_INTEL_I82801HX_I82801HX_H + +#include /* IWYU pragma: export */ + +#define DEFAULT_TBAR ((u8 *)0xfed1b000) + +/* PCI Devices */ +#define D31F0 PCI_DEV(0, 31, 0) /* LPC Bridge */ +#define D31F1 PCI_DEV(0, 31, 1) /* IDE */ +#define D31F2 PCI_DEV(0, 31, 2) /* SATA */ +#define D31F3 PCI_DEV(0, 31, 3) /* SMBus */ +#define D31F5 PCI_DEV(0, 31, 5) /* SATA #2 */ +#define D31F6 PCI_DEV(0, 31, 6) /* Thermal */ +#define D29F0 PCI_DEV(0, 29, 0) /* USB UHCI #1 */ +#define D29F1 PCI_DEV(0, 29, 1) /* USB UHCI #2 */ +#define D29F2 PCI_DEV(0, 29, 2) /* USB UHCI #3 */ +#define D29F7 PCI_DEV(0, 29, 7) /* USB EHCI #1 */ +#define D26F0 PCI_DEV(0, 26, 0) /* USB UHCI #4 */ +#define D26F1 PCI_DEV(0, 26, 1) /* USB UHCI #5 */ +#define D26F7 PCI_DEV(0, 26, 7) /* USB EHCI #2 */ +#define D27F0 PCI_DEV(0, 27, 0) /* HD Audio */ +#define D28F0 PCI_DEV(0, 28, 0) /* PCIe Root Port #1 */ +#define D28F1 PCI_DEV(0, 28, 1) /* PCIe Root Port #2 */ +#define D28F2 PCI_DEV(0, 28, 2) /* PCIe Root Port #3 */ +#define D28F3 PCI_DEV(0, 28, 3) /* PCIe Root Port #4 */ +#define D30F0 PCI_DEV(0, 30, 0) /* PCI Bridge */ + +/* ================================================================== */ +/* D31:F0 LPC Bridge Registers */ +/* ================================================================== */ + +#define D31F0_PMBASE 0x40 +#define D31F0_ACPI_CNTL 0x44 +#define D31F0_GPIO_BASE 0x48 +#define D31F0_GPIO_CNTL 0x4c +#define D31F0_PIRQA_ROUT 0x60 +#define D31F0_PIRQB_ROUT 0x61 +#define D31F0_PIRQC_ROUT 0x62 +#define D31F0_PIRQD_ROUT 0x63 +#define D31F0_SERIRQ_CNTL 0x64 +#define D31F0_PIRQE_ROUT 0x68 +#define D31F0_PIRQF_ROUT 0x69 +#define D31F0_PIRQG_ROUT 0x6a +#define D31F0_PIRQH_ROUT 0x6b +#define D31F0_LPC_IODEC 0x80 +#define D31F0_LPC_EN 0x82 +#define D31F0_GEN1_DEC 0x84 +#define D31F0_GEN2_DEC 0x88 +#define D31F0_GEN3_DEC 0x8c +#define D31F0_GEN4_DEC 0x90 +#define D31F0_GEN_PMCON_1 0xa0 +#define D31F0_GEN_PMCON_2 0xa2 +#define D31F0_GEN_PMCON_3 0xa4 +#define D31F0_C5_EXIT_TIMING 0xa8 +#define D31F0_C5_ENABLE 0xa9 +#define D31F0_C4TIMING_CNT 0xaa +#define D31F0_PMIR 0xac /* Power Management Initialization Register */ +#define D31F0_GPIO_ROUT 0xb8 +#define D31F0_RCBA 0xf0 + +/* GEN_PMCON_1 bits */ +#define GEN_PMCON_1_SMI_LOCK (1 << 4) +#define GEN_PMCON_1_CLKRUN_EN (1 << 2) +#define GEN_PMCON_1_SS_EN (1 << 3) /* SpeedStep Enable */ +#define GEN_PMCON_1_CPUSLP_EN (1 << 5) +#define GEN_PMCON_1_C4ONC3 (1 << 7) +#define GEN_PMCON_1_BIOS_PCI_EXP_EN (1 << 10) +#define GEN_PMCON_1_C5_ENABLE (1 << 11) + +/* GEN_PMCON_2 bits */ +#define GEN_PMCON_2_DRAM_INIT (1 << 7) /* DRAM init scratchpad bit (DISB) */ +#define GEN_PMCON_2_W1C_BITS 0x19 /* Write 1 to clear bits 0,3,4 */ + +/* GEN_PMCON_3 bits */ +#define GEN_PMCON_3_SLP_S4_STRETCH (1 << 3) +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) +#define GEN_PMCON_3_SLP_S4_MAW (3 << 4) /* Minimum assertion width */ + +/* PMIR bits (D31F0 + 0xAC) */ +#define PMIR_USB_TRANSIENT_DISCONNECT (3 << 8) +#define PMIR_CF9GR (1 << 20) +#define PMIR_CF9LOCK (1 << 31) + +/* LPC_EN bits */ +#define LPC_EN_CNF2 (1 << 13) /* 0x4E/0x4F decode */ +#define LPC_EN_CNF1 (1 << 12) /* 0x2E/0x2F decode */ +#define LPC_EN_MC (1 << 11) /* 0x62/0x66 decode (EC) */ +#define LPC_EN_KBC (1 << 10) /* 0x60/0x64 decode (KBC) */ +#define LPC_EN_GAMEL (1 << 8) +#define LPC_EN_COMB (1 << 1) +#define LPC_EN_COMA (1 << 0) + +/* ================================================================== */ +/* D31:F1 IDE Registers (PATA controller, PCI ID 0x2850) */ +/* ================================================================== */ + +/* Standard IDE timing registers - same layout as ICH7 (i82801gx) */ +#define IDE_TIM_PRI 0x40 /* Primary channel timing */ +#define IDE_TIM_SEC 0x42 /* Secondary channel timing */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) + +/* IDE I/O Configuration Register - controls DMA/signal modes */ +#define IDE_CONFIG 0x54 +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +/* ================================================================== */ +/* D31:F2 SATA Registers */ +/* ================================================================== */ + +#define D31F2_IDE_TIM_PRI 0x40 +#define D31F2_IDE_TIM_SEC 0x42 +#define D31F2_SATA_MAP 0x90 +#define D31F2_SATA_PCS 0x92 +#define D31F2_SIR 0x94 +#define D31F2_SIDX 0xa0 +#define D31F2_SDAT 0xa4 + +/* ================================================================== */ +/* D30:F0 PCI-to-PCI Bridge Registers */ +/* ================================================================== */ + +#define D30F0_SMLT 0x1b /* Secondary ID Register */ + +/* ================================================================== */ +/* RCBA Register Offsets (base = 0xFED1C000) */ +/* ================================================================== */ + +#define RCBA_V0CTL 0x0014 +#define RCBA_V1CAP 0x001c +#define RCBA_V1CTL 0x0020 +#define RCBA_V1STS 0x0026 +#define RCBA_PAT 0x0030 /* 64 bytes */ +#define RCBA_CIR1 0x0088 +#define RCBA_ESD 0x0104 +#define RCBA_ULD 0x0110 +#define RCBA_ULBA 0x0118 +#define RCBA_LCAP 0x01a4 +#define RCBA_LCTL 0x01a8 +#define RCBA_LSTS 0x01aa +#define RCBA_CIR2 0x01f4 +#define RCBA_CIR3 0x01fc +#define RCBA_CIR4 0x0200 +#define RCBA_BCR 0x0220 +#define RCBA_DMIC 0x0234 +#define RCBA_RPFN 0x0238 +#define RCBA_CIR13 0x0f20 +#define RCBA_CIR5 0x1d40 +#define RCBA_DMC 0x2010 +#define RCBA_CIR6 0x2024 +#define RCBA_CIR7 0x2034 + +/* Interrupt pin values for DxxIP registers */ +#define NOINT 0 +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +/* PIRQ values for DxxIR registers */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* DxxIR nibble offsets */ +#define DIR_IDR 12 /* Interrupt D Pin Offset */ +#define DIR_ICR 8 /* Interrupt C Pin Offset */ +#define DIR_IBR 4 /* Interrupt B Pin Offset */ +#define DIR_IAR 0 /* Interrupt A Pin Offset */ + +#define DIR_ROUTE(x, a, b, c, d) \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR)) + +/* Interrupt routing - DxxIP (pin assignment) */ +#define D31IP 0x3100 /* 32-bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin (D31:F6) */ +#define D31IP_SMIP 12 /* SMBus Pin (D31:F3) */ +#define D31IP_SIP 8 /* SATA Pin (D31:F2) */ +#define D31IP_IDEP 4 /* IDE/PATA Pin (D31:F1) */ +#define D30IP 0x3104 /* 32-bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin (D30:F0) */ +#define D29IP 0x3108 /* 32-bit */ +#define D29IP_E1P 28 /* EHCI #1 Pin (D29:F7) */ +#define D29IP_U3P 8 /* UHCI #3 Pin (D29:F2) */ +#define D29IP_U2P 4 /* UHCI #2 Pin (D29:F1) */ +#define D29IP_U1P 0 /* UHCI #1 Pin (D29:F0) */ +#define D28IP 0x310c /* 32-bit */ +#define D28IP_P6IP 20 /* PCIe Port 6 (D28:F5) */ +#define D28IP_P5IP 16 /* PCIe Port 5 (D28:F4) */ +#define D28IP_P4IP 12 /* PCIe Port 4 (D28:F3) */ +#define D28IP_P3IP 8 /* PCIe Port 3 (D28:F2) */ +#define D28IP_P2IP 4 /* PCIe Port 2 (D28:F1) */ +#define D28IP_P1IP 0 /* PCIe Port 1 (D28:F0) */ +#define D27IP 0x3110 /* 32-bit */ +#define D27IP_ZIP 0 /* HD Audio Pin (D27:F0) */ +#define D26IP 0x3114 /* 32-bit */ +#define D26IP_E2P 28 /* EHCI #2 Pin (D26:F7) */ +#define D26IP_U5P 4 /* UHCI #5 Pin (D26:F1) */ +#define D26IP_U4P 0 /* UHCI #4 Pin (D26:F0) */ +#define D25IP 0x3118 /* 32-bit */ +#define D25IP_LIP 0 /* GbE LAN Pin (D25:F0) */ + +/* DxxIR - interrupt route (PIRQ mapping) */ +#define D31IR 0x3140 /* 16-bit */ +#define D30IR 0x3142 /* 16-bit */ +#define D29IR 0x3144 /* 16-bit */ +#define D28IR 0x3146 /* 16-bit */ +#define D27IR 0x3148 /* 16-bit */ +#define D26IR 0x314c /* 16-bit */ +#define D25IR 0x3150 /* 16-bit */ + +#define OIC 0x31ff /* 8-bit: IOAPIC control */ + +/* CIR (Chipset Initialization Registers) - Intel-required */ +#define RCBA_CIR8 0x3430 +#define RCBA_CIR9 0x350c +#define RCBA_CIR10 0x352c + +/* I/O Trap registers */ +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +/* Misc config */ +#define RCBA_RC 0x3400 /* Root Complex config */ +#define RCBA_HPTC 0x3404 /* HPET Configuration */ +#define RCBA_GCS 0x3410 /* General Control and Status */ +#define RCBA_BUC 0x3414 /* Backed Up Control */ +#define RCBA_FD 0x3418 /* Function Disable */ +#define RCBA_CG 0x341c /* Clock Gating */ +#define RCBA_FDSW 0x3420 /* Function Disable SUS Well */ +#define FDSW_LAND (1 << 0) /* LAN Disable */ +#define RCBA_MAP 0x35f0 /* UHCI controller remap (R/WO lock) */ + +/* Function Disable bits (RCBA_FD) */ +#define FD_SAD2 (1 << 25) /* SATA #2 */ +#define FD_TTD (1 << 24) /* Thermal Throttle */ +#define FD_PE6D (1 << 21) +#define FD_PE5D (1 << 20) +#define FD_PE4D (1 << 19) +#define FD_PE3D (1 << 18) +#define FD_PE2D (1 << 17) +#define FD_PE1D (1 << 16) +#define FD_EHCI1D (1 << 15) +#define FD_LBD (1 << 14) /* LPC Bridge */ +#define FD_EHCI2D (1 << 13) +#define FD_U5D (1 << 12) +#define FD_U4D (1 << 11) +#define FD_U3D (1 << 10) +#define FD_U2D (1 << 9) +#define FD_U1D (1 << 8) +#define FD_HDAD (1 << 4) /* HD Audio */ +#define FD_SD (1 << 3) /* SMBus */ +#define FD_SAD1 (1 << 2) /* SATA #1 */ + +/* EHCI PCI config registers */ +#define EHCI_USB_RELNUM 0x60 /* USB Release Number */ +#define EHCI_USB_LEGCTLSTS 0x6c /* Legacy Support/Control */ +#define EHCI_ACCESS_CNTL 0x80 /* Access Control (bit 0 = write enable) */ +#define EHCI_INTEL_FCREG 0xfc /* Intel-specific config (must program) */ + +/* EHCI MMIO registers (at BAR + CAPLENGTH, CAPLENGTH typically 0x20) */ +#define EHCI_CAPLENGTH 0x00 +#define EHCI_USBCMD 0x20 /* USB Command (BAR + 0x20 for Intel) */ +#define EHCI_USBCMD_RS (1 << 0) /* Run/Stop */ +#define EHCI_USBCMD_HCRST (1 << 1) /* Host Controller Reset */ + +/* IOAPIC */ +#define IO_APIC_ADDR 0xfec00000 +#define OIC_AEN (1 << 0) /* APIC Enable */ + +/* HPET */ +#define HPET_BASE_ADDR 0xfed00000 +#define HPTC_HPTE (1 << 7) /* HPET Address Enable */ +#define HPTC_HPAS_MASK (3 << 0) /* HPET Address Select */ + +/* ================================================================== */ +/* D28:Fx PCIe Root Port Registers */ +/* ================================================================== */ + +/* Standard PCI/PCIe config registers used on D28:Fx */ +#define D28Fx_CMD 0x04 /* PCI Command */ +#define D28Fx_CLS 0x0c /* Cache Line Size */ +#define D28Fx_BCTRL 0x3e /* Bridge Control */ +#define D28Fx_XCAP 0x42 /* PCI Express Capabilities */ +#define D28Fx_LCAP 0x4c /* Link Capabilities (R/WO for ASPM) */ +#define D28Fx_LCTL 0x50 /* Link Control (ASPM bits [1:0]) */ +#define D28Fx_SLCAP 0x54 /* Slot Capabilities */ +#define D28Fx_VC0RCTL 0x114 /* VC0 Resource Control */ +#define D28Fx_CTTOMASK 0x148 /* Completion Timeout Mask */ +#define D28Fx_CEMASK 0x154 /* Correctable Error Mask (R/WO lock) */ + +/* D28:Fx extended config */ +#define D28Fx_IOXAPIC 0xd8 /* IO xAPIC + hotplug control */ +#define D28Fx_BBCLKG 0xe1 /* Backbone Clock Gating */ +#define D28Fx_ASPM_MOBILE 0xe8 /* Mobile ASPM config */ + +/* D28:Fx CIR (Chipset Init) registers */ +#define D28Fx_CIR_300 0x300 /* CIR: bit 21 must set, bits 17:16 = link disable */ +#define D28Fx_CIR_324 0x324 /* CIR: must write 0x40 */ + +/* SLCAP field positions */ +#define D28_SLCAP_SLOTNUM_SHIFT 19 +#define D28_SLCAP_SCALE_SHIFT 16 +#define D28_SLCAP_POWER_SHIFT 7 + +/* ================================================================== */ +/* I/O Base Addresses */ +/* ================================================================== */ + +#define DEFAULT_PMBASE 0x0500 +#define DEFAULT_GPIOBASE 0x0580 + +#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) + +/* ================================================================== */ +/* MMIO Base Addresses */ +/* ================================================================== */ + +#define RCBA_BASE 0xfed1c000 + +/* ================================================================== */ +/* GPIO Register Offsets (from GPIO I/O base) */ +/* ================================================================== */ + +#define GP_IO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GP_IO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GP_IO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 + +/* ACPI / PM / TCO registers are defined in southbridge/intel/common/pmutil.h + * (shared across all ICH southbridges). ICH8 does NOT have 64 GPE events + * and uses TCO_SPACE_NOT_YET_SPLIT (selected in Kconfig). + */ + +/* ================================================================== */ +/* i8259 PIC I/O Ports */ +/* ================================================================== */ + +#define MASTER_PIC_ICW1 0x20 +#define SLAVE_PIC_ICW1 0xa0 +#define ICW_SELECT (1 << 4) +#define IC4 (1 << 0) + +#define MASTER_PIC_ICW2 0x21 +#define SLAVE_PIC_ICW2 0xa1 +#define INT_VECTOR_MASTER 0x20 /* IRQ0-7 -> INT 0x20-0x27 */ +#define INT_VECTOR_SLAVE 0x28 /* IRQ8-15 -> INT 0x28-0x2F */ + +#define MASTER_PIC_ICW3 0x21 +#define CASCADED_PIC (1 << 2) /* IRQ2 is cascade */ +#define SLAVE_PIC_ICW3 0xa1 +#define SLAVE_ID 0x02 + +#define MASTER_PIC_OCW1 0x21 /* IRQ mask register (master) */ +#define SLAVE_PIC_OCW1 0xa1 /* IRQ mask register (slave) */ +#define ALL_IRQS 0xff +#define IRQ2_MASK (1 << 2) +#define MICROPROCESSOR_MODE (1 << 0) + +/* Edge/Level Control Registers */ +#define ELCR1 0x4d0 +#define ELCR2 0x4d1 + +/* ================================================================== */ +/* ISA DMA Controller I/O Ports */ +/* ================================================================== */ + +#define DMA1_RESET_REG 0x0D /* Master Clear (slave DMA) */ +#define DMA2_RESET_REG 0xDA /* Master Clear (master DMA) */ +#define DMA2_MODE_REG 0xD6 /* Mode register (master DMA) */ +#define DMA2_MASK_REG 0xD4 /* Single-channel mask (master DMA) */ +#define DMA_MODE_CASCADE 0xC0 /* Pass thru DREQ->HRQ, DACK<-HLDA */ + +/* CMOS/RTC defines are in . + * i8259 and ISA DMA prototypes are in and . + */ + +#ifndef __ACPI__ + +#include +#include +#include +#include + +static inline int lpc_is_mobile(const uint16_t devid) +{ + return (devid == PCI_DID_INTEL_82801HBM_LPC) || (devid == PCI_DID_INTEL_82801HEM_LPC); +} +#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) + +/* ================================================================== */ +/* RCBA MMIO access helpers */ +/* ================================================================== */ + +#define rcba_read8(reg) read8p(RCBA_BASE + (reg)) +#define rcba_read16(reg) read16p(RCBA_BASE + (reg)) +#define rcba_read32(reg) read32p(RCBA_BASE + (reg)) +#define rcba_write8(reg, val) write8p(RCBA_BASE + (reg), (val)) +#define rcba_write16(reg, val) write16p(RCBA_BASE + (reg), (val)) +#define rcba_write32(reg, val) write32p(RCBA_BASE + (reg), (val)) + +/* ================================================================== */ +/* Function Prototypes */ +/* ==================================================================*/ + +/* early_init.c - pre-RAM southbridge setup */ +void i82801hx_early_init(void); +void i82801hx_lpc_setup(void); +void i82801hx_setup_gpio(void); +int i82801hx_detect_s3_resume(void); + +/* dmi_setup.c - DMI link configuration */ +void i82801hx_dmi_setup(void); +void i82801hx_dmi_poll_vc1(void); + +/* lpc.c - post-RAM LPC/IOAPIC init */ +void i82801hx_enable_ioapic(void); + +/* pcie.c - PCIe root port init, clock gating, RPFN */ +void i82801hx_pcie_init(void); + +/* early_rcba.c - default interrupt routing */ +void southbridge_configure_default_intmap(void); +/* Optional mainboard hook for additional RCBA configuration */ +void mainboard_late_rcba_config(void); + +#endif /* !__ACPI__ */ + +#endif /* SOUTHBRIDGE_INTEL_I82801HX_I82801HX_H */ diff --git a/src/southbridge/intel/i82801hx/ide.c b/src/southbridge/intel/i82801hx/ide.c new file mode 100644 index 00000000000..4e0ba6816f4 --- /dev/null +++ b/src/southbridge/intel/i82801hx/ide.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Intel ICH8-M (82801HBM) D31:F1 IDE controller driver + * + * The ICH8-M has a dedicated PATA IDE controller at D31:F1 (PCI ID 0x2850), + * separate from the SATA controller at D31:F2. On the ThinkPad X61 this + * controller drives the UltraBay device slot (optical drive). + * + * Ported from southbridge/intel/i82801gx/ide.c (ICH7). + * Register layout is identical; only the PCI device ID differs. + */ + +#include +#include +#include +#include +#include +#include "chip.h" +#include "i82801hx.h" + +static void ide_init(struct device *dev) +{ + u16 ideTimingConfig; + u32 reg32; + bool enable_primary, enable_secondary; + + const struct southbridge_intel_i82801hx_config *config = dev->chip_info; + + printk(BIOS_DEBUG, "i82801hx_ide: initializing..."); + + if (config == NULL) { + printk(BIOS_ERR, "\ni82801hx_ide: not in devicetree.cb, using safe defaults\n"); + enable_primary = true; + enable_secondary = false; + } else { + enable_primary = config->ide_enable_primary; + enable_secondary = config->ide_enable_secondary; + } + + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); + + /* Native Capable, but not enabled in compatibility mode */ + pci_write_config8(dev, 0x09, 0x8a); + + /* ---- Primary channel ---- */ + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_SITRE; + if (enable_primary) { + ideTimingConfig |= IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; + printk(BIOS_DEBUG, " IDE0"); + } + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + + /* ---- Secondary channel ---- */ + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_SITRE; + if (enable_secondary) { + ideTimingConfig |= IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; + printk(BIOS_DEBUG, " IDE1"); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); + + /* ---- IDE I/O Configuration (DMA / signal drive strength) ---- */ + reg32 = 0; + if (enable_primary) + reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1; + if (enable_secondary) + reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Interrupt line - set to 0xff (unrouted; OS assigns via PIRQ) */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + printk(BIOS_DEBUG, "\n"); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .ops_pci = &pci_dev_ops_pci, +}; + +/* 82801HM/HEM (ICH8M / ICH8M-E) IDE controller */ +static const struct pci_driver i82801hx_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VID_INTEL, + .device = PCI_DID_INTEL_82801HBM_IDE, +}; diff --git a/src/southbridge/intel/i82801hx/include/soc/nvs.h b/src/southbridge/intel/i82801hx/include/soc/nvs.h new file mode 100644 index 00000000000..7bb98fc8210 --- /dev/null +++ b/src/southbridge/intel/i82801hx/include/soc/nvs.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_I82801HX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801HX_NVS_H + +#include + +struct __packed global_nvs { + /* Miscellaneous */ + u16 unused_was_osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 unused_was_prm0; /* 0x03 - SMI function call parameter */ + u8 unused_was_prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 unused_was_prm2; /* 0x06 - SCI function call parameter */ + u8 unused_was_prm3; /* 0x07 - SCI function call parameter */ + u8 unused_was_lckf; /* 0x08 - Global Lock function for EC */ + u8 unused_was_prm4; /* 0x09 - Lock function parameter */ + u8 unused_was_prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ + u8 dbgs; /* 0x11 - Debug state */ + u8 linx; /* 0x12 - Linux OS */ + u8 dckn; /* 0x13 - PCIe docking state */ + /* Thermal policy */ + u8 actt; /* 0x14 - active trip point */ + u8 tpsv; /* 0x15 - passive trip point */ + u8 tc1v; /* 0x16 - passive trip point TC1 */ + u8 tc2v; /* 0x17 - passive trip point TC2 */ + u8 tspv; /* 0x18 - passive trip point TSP */ + u8 tcrt; /* 0x19 - critical trip point */ + u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ + u8 dts1; /* 0x1b - DT sensor 1 */ + u8 flvl; /* 0x1c - current fan level */ + u8 rsvd2; + /* Battery Support */ + u8 bnum; /* 0x1e - number of batteries */ + u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */ + u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ + u8 rsvd3[3]; + /* Processor Identification */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ + u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ + u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ + u8 ppcm; /* 0x2c - Max. PPC state */ + u8 rsvd4[5]; + /* Super I/O & CMOS config */ + u8 natp; /* 0x32 - SIO type */ + u8 cmap; /* 0x33 - */ + u8 cmbp; /* 0x34 - */ + u8 lptp; /* 0x35 - LPT port */ + u8 fdcp; /* 0x36 - Floppy Disk Controller */ + u8 rfdv; /* 0x37 - */ + u8 hotk; /* 0x38 - Hot Key */ + u8 rtcf; + u8 util; + u8 acin; + /* Integrated Graphics Device */ + u8 igds; /* 0x3c - IGD state */ + u8 tlst; /* 0x3d - Display Toggle List Pointer */ + u8 cadl; /* 0x3e - currently attached devices */ + u8 padl; /* 0x3f - previously attached devices */ + u8 rsvd5[36]; + /* Backlight Control */ + u8 blcs; /* 0x64 - Backlight Control possible */ + u8 brtl; + u8 odds; + u8 rsvd6[0x7]; + /* Ambient Light Sensors*/ + u8 alse; /* 0x6e - ALS enable */ + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd7[0x6]; + /* EMA */ + u8 emae; /* 0x78 - EMA enable */ + u16 emap; + u16 emal; + u8 rsvd8[0x5]; + /* MEF */ + u8 mefe; /* 0x82 - MEF enable */ + u8 rsvd9[0x9]; + /* TPM support */ + u8 tpmp; /* 0x8c - TPM */ + u8 tpme; + u8 rsvd10[8]; + /* SATA */ + u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ + u8 gtf1[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 rsvd11[67]; + /* Mainboard specific */ + u8 dock; /* 0xf0 - Docking Status */ + u8 bten; + + u32 unused_was_cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; +}; + +#endif /* SOUTHBRIDGE_INTEL_I82801HX_NVS_H */ diff --git a/src/southbridge/intel/i82801hx/lpc.c b/src/southbridge/intel/i82801hx/lpc.c new file mode 100644 index 00000000000..bd724a845ad --- /dev/null +++ b/src/southbridge/intel/i82801hx/lpc.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel ICH8-M LPC Bridge - IOAPIC enable + */ + +#include + +/* ================================================================== */ +/* IOAPIC Enable */ +/* ================================================================== */ + +void i82801hx_enable_ioapic(void) +{ + /* Enable IOAPIC. Keep APIC Range Select at zero. */ + RCBA8(OIC) = 0x03; + + /* Spec requires readback when bit 0 changes. */ + (void)RCBA8(OIC); +} diff --git a/src/southbridge/intel/i82801hx/pci.c b/src/southbridge/intel/i82801hx/pci.c new file mode 100644 index 00000000000..ba5cb403b3e --- /dev/null +++ b/src/southbridge/intel/i82801hx/pci.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "i82801hx.h" + +static void pci_init(struct device *dev) +{ + u16 reg16; + + /* This device has no interrupt */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Master Latency Count must be set to 0x04! */ + pci_update_config8(dev, D30F0_SMLT, 0x07, 0x04 << 3); + + /* Clear errors in status registers. FIXME: Do something? */ + reg16 = pci_read_config16(dev, PCI_STATUS); + //reg16 |= 0xf900; + pci_write_config16(dev, PCI_STATUS, reg16); + + reg16 = pci_read_config16(dev, PCI_SEC_STATUS); + // reg16 |= 0xf900; + pci_write_config16(dev, PCI_SEC_STATUS, reg16); +} + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_82801HB_PCI, /* Desktop */ + PCI_DID_INTEL_82801HBM_PCI, /* Mobile */ + 0, +}; + +static const struct pci_driver ich8_pci __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/i82801hx/pcie.c b/src/southbridge/intel/i82801hx/pcie.c new file mode 100644 index 00000000000..bfed5c373bf --- /dev/null +++ b/src/southbridge/intel/i82801hx/pcie.c @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel ICH8-M PCIe Root Port Initialization + * + * Reference: coreboot i82801ix/i82801ix.c, i82801ix/pcie.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define PCIE_PORT_COUNT 6 + +static uint32_t pcie_fd_bit(int fn) +{ + switch (fn) { + case 0: return FD_PE1D; + case 1: return FD_PE2D; + case 2: return FD_PE3D; + case 3: return FD_PE4D; + case 4: return FD_PE5D; + case 5: return FD_PE6D; + default: return 0; + } +} + +/* ================================================================== */ +/* Per-Port CIR Programming */ +/* ================================================================== */ + +static void pcie_port_cir_init(void) +{ + int i; + + for (i = 0; i < PCIE_PORT_COUNT; i++) { + struct device *dev = pcidev_on_root(28, i); + if (!dev) + continue; + + pci_or_config32(dev, D28Fx_CIR_300, (1 << 21)); + pci_write_config8(dev, D28Fx_CIR_324, 0x40); + } +} + +/* ================================================================== */ +/* Per-Port Device Initialization */ +/* ================================================================== */ + +static void pcie_port_init(struct device *dev) +{ + u32 reg32; + + /* Enable Bus Master */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* Set Cache Line Size to 0x10 (64 bytes) */ + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); + + /* Disable parity error response in Bridge Control */ + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); + + /* Enable IO xAPIC on this PCIe port */ + pci_or_config32(dev, D28Fx_IOXAPIC, (1 << 7)); + + /* Enable Backbone Clock Gating */ + pci_or_config8(dev, D28Fx_BBCLKG, 0x0f); + + /* Set VC0 transaction class: TC0 only */ + reg32 = pci_read_config32(dev, D28Fx_VC0RCTL); + reg32 = (reg32 & ~0x000000ff) | 1; + pci_write_config32(dev, D28Fx_VC0RCTL, reg32); + + /* Mask completion timeouts */ + pci_or_config32(dev, D28Fx_CTTOMASK, (1 << 14)); + + /* Lock R/WO Correctable Error Mask */ + pci_write_config32(dev, D28Fx_CEMASK, + pci_read_config32(dev, D28Fx_CEMASK)); + + /* Clear errors in status registers */ + pci_write_config16(dev, PCI_STATUS, + pci_read_config16(dev, PCI_STATUS)); + pci_write_config16(dev, PCI_SEC_STATUS, + pci_read_config16(dev, PCI_SEC_STATUS)); +} + +/* ================================================================== */ +/* Mobile ASPM Configuration */ +/* ================================================================== */ + +static void pcie_mobile_aspm(struct device *dev) +{ + u32 apmc; + + /* Enable mobile ASPM */ + pci_or_config32(dev, D28Fx_ASPM_MOBILE, (1 << 0)); + + /* If both L0s and L1 are enabled, set bit 1 too. */ + apmc = pci_read_config32(dev, D28Fx_LCTL) & 3; + if (apmc == 3) + pci_or_config32(dev, D28Fx_ASPM_MOBILE, (1 << 1)); +} + +/* ================================================================== */ +/* Slot Configuration */ +/* ================================================================== */ + +static void pcie_slot_config(void) +{ + const struct device *lpc_dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801hx_config *config; + int i; + int slot_number = 1; + + if (!lpc_dev || !lpc_dev->chip_info) + return; + + config = lpc_dev->chip_info; + + for (i = 0; i < PCIE_PORT_COUNT; i++) { + struct device *dev = pcidev_on_root(28, i); + u32 xcap; + + if (!dev) + continue; + + xcap = pci_read_config32(dev, D28Fx_XCAP); + + if (config->pcie_slot_implemented & (1 << i)) { + u32 slcap; + + xcap |= PCI_EXP_FLAGS_SLOT; + pci_write_config32(dev, D28Fx_XCAP, xcap); + + slcap = pci_read_config32(dev, D28Fx_SLCAP); + slcap &= ~(0x1fff << D28_SLCAP_SLOTNUM_SHIFT); + slcap |= (slot_number++ << D28_SLCAP_SLOTNUM_SHIFT); + slcap &= ~(0x0003 << D28_SLCAP_SCALE_SHIFT); + slcap |= (config->pcie_power_limits[i].scale + << D28_SLCAP_SCALE_SHIFT); + slcap &= ~(0x00ff << D28_SLCAP_POWER_SHIFT); + slcap |= (config->pcie_power_limits[i].value + << D28_SLCAP_POWER_SHIFT); + pci_write_config32(dev, D28Fx_SLCAP, slcap); + } else { + xcap &= ~PCI_EXP_FLAGS_SLOT; + pci_write_config32(dev, D28Fx_XCAP, xcap); + } + } +} + +/* ================================================================== */ +/* Trailing Port Disable */ +/* ================================================================== */ + +static void pcie_trailing_port_disable(void) +{ + int i; + u32 fd; + + fd = RCBA32(RCBA_FD); + + /* + * Walk from port 5 (highest) down to port 0. + * If the port is disabled in FD, set bits [17:16] in 0x300 + * to disable the link. Stop at the first enabled port. + */ + for (i = 5; i >= 0; i--) { + struct device *dev; + + if (!(fd & pcie_fd_bit(i))) + break; + + dev = pcidev_on_root(28, i); + if (!dev) + continue; + + pci_or_config32(dev, D28Fx_CIR_300, (0x3 << 16)); + } +} + +/* ================================================================== */ +/* ASPM Capability Lock */ +/* ================================================================== */ + +static void pcie_aspm_lock(void) +{ + int i; + + for (i = 0; i < PCIE_PORT_COUNT; i++) { + struct device *dev = pcidev_on_root(28, i); + if (!dev) + continue; + + /* Write back to latch R/WO bits */ + pci_write_config32(dev, D28Fx_LCAP, + pci_read_config32(dev, D28Fx_LCAP)); + } +} + +/* ================================================================== */ +/* Root Port Function Number Remap (RPFN) */ +/* ================================================================== */ + +static void pcie_rpfn_hide(void) +{ + int i; + u32 rpfn; + + rpfn = RCBA32(RCBA_RPFN); + + for (i = 0; i < PCIE_PORT_COUNT; i++) { + if (RCBA32(RCBA_FD) & pcie_fd_bit(i)) + rpfn |= (1 << ((i * 4) + 3)); + } + + RCBA32(RCBA_RPFN) = rpfn; +} + +/* ================================================================== */ +/* Public Entry Point */ +/* ================================================================== */ + +void i82801hx_pcie_init(void) +{ + int i; + + /* Per-port CIR programming */ + pcie_port_cir_init(); + + /* Mobile ASPM and per-port init on each root port */ + for (i = 0; i < PCIE_PORT_COUNT; i++) { + struct device *dev = pcidev_on_root(28, i); + if (!dev) + continue; + + pcie_mobile_aspm(dev); + pcie_port_init(dev); + } + + /* Trailing port disable (top-down unused ports) */ + pcie_trailing_port_disable(); + + /* Slot configuration from devicetree */ + pcie_slot_config(); + + /* ASPM capability lock */ + pcie_aspm_lock(); + + /* RPFN - hide disabled PCIe ports */ + pcie_rpfn_hide(); +} diff --git a/src/southbridge/intel/i82801hx/sata.c b/src/southbridge/intel/i82801hx/sata.c new file mode 100644 index 00000000000..1cf087fe4e6 --- /dev/null +++ b/src/southbridge/intel/i82801hx/sata.c @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "i82801hx.h" + +typedef struct southbridge_intel_i82801hx_config config_t; + +static void sata_enable_ahci_mmap(struct device *const dev, const config_t *const config, + const int is_mobile) +{ + int i; + u32 reg32; + struct resource *res; + + /* Initialize AHCI memory-mapped space */ + res = probe_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + u8 *abar = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); + + /* Set AHCI access mode. + No other ABAR registers should be accessed before this. */ + reg32 = read32(abar + 0x04); + reg32 |= 1 << 31; + write32(abar + 0x04, reg32); + + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + /* CCCS must be set. */ + reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + write32(abar + 0x00, reg32); + + /* PI (Ports implemented) */ + write32(abar + 0x0c, config->sata_port_map); + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ + + /* VSP (Vendor Specific Register) */ + reg32 = read32(abar + 0xa0); + reg32 &= ~0x00000001; /* clear SLPD */ + write32(abar + 0xa0, reg32); + + /* Lock R/WO bits in Port command registers. + ICH8-M has 3 SATA ports, ICH8 desktop has up to 6. */ + const int num_ports = is_mobile ? 3 : 6; + for (i = 0; i < num_ports; ++i) { + u8 *addr = abar + 0x118 + (i * 0x80); + reg32 = read32(addr); + if (config->sata_hotplug_map & (1 << i)) + reg32 |= 1 << 18; + write32(addr, reg32); + } +} + +static void sata_program_indexed(struct device *const dev, const int is_mobile) +{ + u32 reg32; + + pci_write_config8(dev, D31F2_SIDX, 0x18); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 6) | (7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x28); + pci_write_config32(dev, D31F2_SDAT, 0x00cc2080); + + pci_write_config8(dev, D31F2_SIDX, 0x40); + pci_write_config8(dev, D31F2_SDAT + 2, 0x22); + + pci_write_config8(dev, D31F2_SIDX, 0x78); + pci_write_config8(dev, D31F2_SDAT + 2, 0x22); + + if (!is_mobile) { + pci_write_config8(dev, D31F2_SIDX, 0x84); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + } + + pci_write_config8(dev, D31F2_SIDX, 0x88); + reg32 = pci_read_config32(dev, D31F2_SDAT); + if (!is_mobile) + reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + if (!is_mobile) + reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x8c); + reg32 = pci_read_config32(dev, D31F2_SDAT); + if (!is_mobile) + reg32 &= ~((7 << 27) | (7 << 24)); + reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); + if (!is_mobile) + reg32 |= (2 << 27) | (2 << 24); + reg32 |= (2 << 19) | (2 << 16) | 0x00aa; + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x94); + pci_write_config32(dev, D31F2_SDAT, 0x00000022); + + pci_write_config8(dev, D31F2_SIDX, 0xa0); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0xa8); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0xac); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); + reg32 |= (2 << 19) | (2 << 16) | 0x000a; + pci_write_config32(dev, D31F2_SDAT, reg32); +} + +static void sata_init(struct device *const dev) +{ + u16 reg16; + + /* Get the chip configuration */ + const struct southbridge_intel_i82801hx_config *const config = dev->chip_info; + + const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int is_mobile = (devid == PCI_DID_INTEL_82801HBM_SATA) || + (devid == PCI_DID_INTEL_82801HBM_SATA_AHCI) || + (devid == PCI_DID_INTEL_82801HBM_SATA_RAID); + + /* ICH8-M has 3 SATA ports, ICH8 desktop has up to 6. */ + const u8 port_mask = is_mobile ? 0x07 : 0x3f; + + printk(BIOS_DEBUG, "i82801hx_sata: initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "i82801hx_sata: device not in devicetree.cb!\n"); + return; + } + + /* Default to AHCI */ + u8 sata_mode = get_uint_option("sata_mode", 0); + + /* + * TODO: In contrast to ICH7 and PCH code we don't set + * timings, dma and IDE-I/O settings here. Looks like they + * became obsolete with the fading of real IDE ports. + * Maybe we can safely remove those settings from PCH code and + * even ICH7 code if it doesn't use the feature to combine the + * IDE and SATA controllers. + */ + + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | /* read-only in IDE modes */ + PCI_COMMAND_IO); + if (sata_mode != 0) + /* No AHCI: clear AHCI base */ + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); + + if (sata_mode == 0) { + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + } else { + printk(BIOS_DEBUG, "SATA controller in native mode.\n"); + + /* Enable native mode on both primary and secondary. */ + pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); + } + + /* Looks like we should only enable decoding here. */ + pci_write_config16(dev, D31F2_IDE_TIM_PRI, (1 << 15)); + pci_write_config16(dev, D31F2_IDE_TIM_SEC, (1 << 15)); + + /* Port enable. For AHCI, it's managed in memory mapped space. */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= (1 << 15) | ((sata_mode == 0) ? port_mask : config->sata_port_map); + pci_write_config16(dev, 0x92, reg16); + + /* SATA clock settings */ + u32 sclkcg = 0; + if (config->sata_clock_request && !(inb(DEFAULT_GPIOBASE + 0x30) & (1 << (35 - 32)))) + sclkcg |= 1 << 30; /* Enable SATA clock request. */ + /* Disable unused ports. */ + sclkcg |= ((~config->sata_port_map) & 0x3f) << 24; + /* Must be programmed. */ + sclkcg |= 0x193; + pci_write_config32(dev, 0x94, sclkcg); + + if (is_mobile && config->sata_traffic_monitor) { + struct device *const lpc_dev = pcidev_on_root(0x1f, 0); + if (((pci_read_config8(lpc_dev, D31F0_C5_ENABLE) >> 3) & 3) == 3) { + u8 reg8 = pci_read_config8(dev, 0x9c); + reg8 &= ~(0x1f << 2); + reg8 |= 3 << 2; + pci_write_config8(dev, 0x9c, reg8); + } + } + + if (sata_mode == 0) + sata_enable_ahci_mmap(dev, config, is_mobile); + + sata_program_indexed(dev, is_mobile); +} + +static void sata_enable(struct device *dev) +{ + /* Get the chip configuration */ + const struct southbridge_intel_i82801hx_config *const config = dev->chip_info; + + u16 map = 0; + + if (!config) + return; + + u8 sata_mode = get_uint_option("sata_mode", 0); + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + if (sata_mode == 0) + map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ + + map |= (config->sata_port_map ^ 0x3f) << 8; + + /* ICH8 SATA MAP register is 8 bits wide. */ + pci_write_config8(dev, 0x90, map & 0xff); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = sata_enable, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_82801HB_SATA1, + PCI_DID_INTEL_82801HB_SATA_AHCI_6, + PCI_DID_INTEL_82801HB_SATA_RAID, + PCI_DID_INTEL_82801HB_SATA_AHCI_4, + PCI_DID_INTEL_82801HB_SATA2, + PCI_DID_INTEL_82801HBM_SATA, + PCI_DID_INTEL_82801HBM_SATA_AHCI, + PCI_DID_INTEL_82801HBM_SATA_RAID, + 0, +}; + +static const struct pci_driver ich8_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/i82801hx/smbus.c b/src/southbridge/intel/i82801hx/smbus.c new file mode 100644 index 00000000000..e56b658a1a1 --- /dev/null +++ b/src/southbridge/intel/i82801hx/smbus.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "i82801hx.h" + +static void ich8_smbus_init(struct device *dev) +{ + /* Enable clock gating */ + pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); +} + +static struct device_operations smbus_ops = { + .read_resources = smbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_smbus, + .init = ich8_smbus_init, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver ich8_smbus __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VID_INTEL, + .device = PCI_DID_INTEL_82801HB_SMB, +}; diff --git a/src/southbridge/intel/i82801hx/smihandler.c b/src/southbridge/intel/i82801hx/smihandler.c new file mode 100644 index 00000000000..e70766224b4 --- /dev/null +++ b/src/southbridge/intel/i82801hx/smihandler.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "i82801hx.h" + +#include + +void southbridge_smi_monitor(void) +{ +#define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; + u32 data, mask = 0; + int i; + + trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register + RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR + + trap_cycle = RCBA32(0x1e10); + for (i = 16; i < 20; i++) { + if (trap_cycle & (1 << i)) + mask |= (0xff << ((i - 16) << 3)); + } + + /* IOTRAP(3) SMI function call */ + if (IOTRAP(3)) { + if (gnvs && gnvs->smif) + io_trap_handler(gnvs->smif); // call function smif + return; + } + + /* IOTRAP(2) currently unused + * IOTRAP(1) currently unused */ + + /* IOTRAP(0) SMIC */ + if (IOTRAP(0)) { + if (!(trap_cycle & (1 << 24))) { // It's a write + printk(BIOS_DEBUG, "SMI1 command\n"); + data = RCBA32(0x1e18); + } + } + + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i = 0; i < 4; i++) { + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + } + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + + if (!(trap_cycle & (1 << 24))) { + /* Write Cycle */ + data = RCBA32(0x1e18); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + } +#undef IOTRAP +} + +void southbridge_finalize_all(void) +{ +} diff --git a/src/southbridge/intel/i82801hx/thermal.c b/src/southbridge/intel/i82801hx/thermal.c new file mode 100644 index 00000000000..0ae21463405 --- /dev/null +++ b/src/southbridge/intel/i82801hx/thermal.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "i82801hx.h" + +static void thermal_init(struct device *dev) +{ + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) + return; + + u8 reg8; + + pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); + pci_or_config32(dev, 0x04, 1 << 1); + + write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */ + write32(DEFAULT_TBAR + 0x44, 0); + + write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */ + write8(DEFAULT_TBAR + 0x41, 0xba); + + reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */ + write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7)); + reg8 = read8(DEFAULT_TBAR + 0x48); + write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7)); + + pci_and_config32(dev, 0x04, ~(1 << 1)); + pci_write_config32(dev, 0x10, 0); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = thermal_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver ich8_thermal __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VID_INTEL, + .device = PCI_DID_INTEL_82801HB_THERMAL, +}; diff --git a/src/southbridge/intel/i82801hx/usb.c b/src/southbridge/intel/i82801hx/usb.c new file mode 100644 index 00000000000..2400d95831e --- /dev/null +++ b/src/southbridge/intel/i82801hx/usb.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel ICH8-M USB Controller Initialization + * + * Reverse-engineered from ThinkPad X61 Phoenix BIOS (2B_0.rom module) + * Reference: coreboot i82801ix/usb_ehci.c, i82801ix/i82801ix.c + * + * ICH8-M USB topology: + * D29:F0 UHCI #1 (PCI DID 0x2830) + * D29:F1 UHCI #2 (PCI DID 0x2831) + * D29:F2 UHCI #3 (PCI DID 0x2832) + * D29:F7 EHCI #1 (PCI DID 0x2836) + * D26:F0 UHCI #4 (PCI DID 0x2834) + * D26:F1 UHCI #5 (PCI DID 0x2835) + * D26:F7 EHCI #2 (PCI DID 0x283A) + * + * EHCI is initialized by usb_ehci.c as a PCI device after BAR/resource + * assignment, matching the ICH7 coreboot model. + */ + +#include +#include +#include +#include +#include +#include + +/* ================================================================== */ +/* UHCI Initialization */ +/* ================================================================== */ + +/* + * i82801hx_uhci_init() - Initialize all UHCI (USB 1.1) controllers + * + * UHCI controllers are simple PCI devices that need minimal setup: + * - Enable Bus Master for DMA transfers + * - I/O BAR is assigned by PCI resource allocation + * + * The BIOS does not perform any special UHCI register programming + * beyond standard PCI command bits. + */ +static void usb_uhci_init(struct device *dev) +{ + printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); + + /* USB Specification says the device must be Bus Master. */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* + * Do not apply the ICH7 config 0xca workaround here. It is not present + * in the X61 vendor USB sequence we found, and touching it on ICH8-M can + * wedge enumeration before the remaining UHCI functions are initialized. + */ + + printk(BIOS_DEBUG, "done.\n"); +} + +static struct device_operations usb_uhci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_uhci_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_uhci_device_ids[] = { + PCI_DID_INTEL_82801HB_USB1, + PCI_DID_INTEL_82801HB_USB2, + PCI_DID_INTEL_82801HB_USB3, + PCI_DID_INTEL_82801HB_USB4, + PCI_DID_INTEL_82801HB_USB5, + 0 +}; + +static const struct pci_driver ich8_usb_uhci __pci_driver = { + .ops = &usb_uhci_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_uhci_device_ids, +}; diff --git a/src/southbridge/intel/i82801hx/usb_ehci.c b/src/southbridge/intel/i82801hx/usb_ehci.c new file mode 100644 index 00000000000..7984748f61b --- /dev/null +++ b/src/southbridge/intel/i82801hx/usb_ehci.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "i82801hx.h" +#include + +static void usb_ehci_init(struct device *dev) +{ + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + // EHCIIR + pci_or_config32(dev, 0xfc, (1 << 17) | (1 << 29)); + + printk(BIOS_DEBUG, "done.\n"); +} + +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + u8 access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + pci_dev_set_subsystem(dev, vendor, device); + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_82801HB_EHCI1, + PCI_DID_INTEL_82801HB_EHCI2, + 0 +}; + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_ehci_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ich8_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 7a66b47de02..6188a50db73 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "i82801ix.h" diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 33f97133685..2266f08e492 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -56,6 +56,7 @@ struct southbridge_intel_i82801ix_config { /* IDE configuration */ uint8_t sata_port_map : 6; + uint8_t sata_hotplug_map : 6; bool sata_clock_request; bool sata_traffic_monitor; diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index b8bc9d83c91..b0cc3f17e05 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "i82801ix.h" #include "chip.h" @@ -26,8 +27,8 @@ void i82801ix_lpc_setup(void) * - 0x208-0x20f GAMEH * - 0x200-0x207 GAMEL */ - pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(d31f0, LPC_IO_DEC, 0x0010); + pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); @@ -37,10 +38,10 @@ void i82801ix_lpc_setup(void) return; config = dev->chip_info; - pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); - pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); - pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); - pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); + pci_write_config32(d31f0, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, LPC_GEN4_DEC, config->gen4_dec); } void i82801ix_early_init(void) @@ -59,7 +60,7 @@ void i82801ix_early_init(void) pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); /* Set up GPIOBASE. */ - pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE); /* Enable GPIO. */ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 2dffb614d59..a11ea988ac5 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -5,6 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ #if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) @@ -35,33 +36,8 @@ /* D31:F0 LPC bridge */ #define D31F0_ACPI_CNTL 0x44 -#define D31F0_GPIO_BASE 0x48 #define D31F0_GPIO_CNTL 0x4c -#define D31F0_PIRQA_ROUT 0x60 -#define D31F0_PIRQB_ROUT 0x61 -#define D31F0_PIRQC_ROUT 0x62 -#define D31F0_PIRQD_ROUT 0x63 #define D31F0_SERIRQ_CNTL 0x64 -#define D31F0_PIRQE_ROUT 0x68 -#define D31F0_PIRQF_ROUT 0x69 -#define D31F0_PIRQG_ROUT 0x6a -#define D31F0_PIRQH_ROUT 0x6b -#define D31F0_LPC_IODEC 0x80 -#define D31F0_LPC_EN 0x82 -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ -#define D31F0_GEN1_DEC 0x84 -#define D31F0_GEN2_DEC 0x88 -#define D31F0_GEN3_DEC 0x8c -#define D31F0_GEN4_DEC 0x90 #define D31F0_C5_EXIT_TIMING 0xa8 #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa @@ -145,6 +121,7 @@ #ifndef __ACPI__ +#include #include static inline int lpc_is_mobile(const u16 devid) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 9c26e2c6d54..73204647685 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -74,15 +74,15 @@ static void i82801ix_pirq_init(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - pci_write_config8(dev, D31F0_PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, D31F0_PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, D31F0_PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, D31F0_PIRQD_ROUT, config->pirqd_routing); - - pci_write_config8(dev, D31F0_PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, D31F0_PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, D31F0_PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, D31F0_PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 7621a4d4b9d..7007d82ec29 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -15,7 +15,7 @@ typedef struct southbridge_intel_i82801ix_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, +static void sata_enable_ahci_mmap(struct device *const dev, const config_t *config, const int is_mobile) { int i; @@ -44,7 +44,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, write32(abar + 0x00, reg32); /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); + write32(abar + 0x0c, config->sata_port_map); /* PCH code reads back twice, do we need it, too? */ (void)read32(abar + 0x0c); /* Read back 1 */ (void)read32(abar + 0x0c); /* Read back 2 */ @@ -59,7 +59,10 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, if (((i == 2) || (i == 3)) && is_mobile) continue; u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); + reg32 = read32(addr); + if (config->sata_hotplug_map & (1 << i)) + reg32 |= 1 << 18; + write32(addr, reg32); } } @@ -212,7 +215,7 @@ static void sata_init(struct device *const dev) } if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + sata_enable_ahci_mmap(dev, config, is_mobile); sata_program_indexed(dev, is_mobile); } diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 7caebdc7d9c..a9d77c151bd 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "i82801jx.h" diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index f7e880cf9ec..3ff7c47f0e0 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include "i82801jx.h" @@ -28,8 +29,8 @@ void i82801jx_lpc_setup(void) * - 0x208-0x20f GAMEH * - 0x200-0x207 GAMEL */ - pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(d31f0, LPC_IO_DEC, 0x0010); + pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); @@ -39,10 +40,10 @@ void i82801jx_lpc_setup(void) return; config = dev->chip_info; - pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); - pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); - pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); - pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); + pci_write_config32(d31f0, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, LPC_GEN4_DEC, config->gen4_dec); } void i82801jx_setup_bars(void) @@ -58,7 +59,7 @@ void i82801jx_setup_bars(void) pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); /* Set up GPIOBASE. */ - pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE); /* Enable GPIO. */ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index dc1130b379d..36ebd2643e2 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -5,6 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ #define DEFAULT_PMBASE 0x00000500 @@ -27,33 +28,8 @@ /* D31:F0 LPC bridge */ #define D31F0_ACPI_CNTL 0x44 #define ACPI_CNTL D31F0_ACPI_CNTL -#define D31F0_GPIO_BASE 0x48 #define D31F0_GPIO_CNTL 0x4c -#define D31F0_PIRQA_ROUT 0x60 -#define D31F0_PIRQB_ROUT 0x61 -#define D31F0_PIRQC_ROUT 0x62 -#define D31F0_PIRQD_ROUT 0x63 #define D31F0_SERIRQ_CNTL 0x64 -#define D31F0_PIRQE_ROUT 0x68 -#define D31F0_PIRQF_ROUT 0x69 -#define D31F0_PIRQG_ROUT 0x6a -#define D31F0_PIRQH_ROUT 0x6b -#define D31F0_LPC_IODEC 0x80 -#define D31F0_LPC_EN 0x82 -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ -#define D31F0_GEN1_DEC 0x84 -#define D31F0_GEN2_DEC 0x88 -#define D31F0_GEN3_DEC 0x8c -#define D31F0_GEN4_DEC 0x90 #define D31F0_C5_EXIT_TIMING 0xa8 #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a955dfe8e54..3e3919d8599 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -83,15 +83,15 @@ static void i82801jx_pirq_init(struct device *dev) */ const u8 pirq_routing = 11; - pci_write_config8(dev, D31F0_PIRQA_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQB_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQC_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQD_ROUT, pirq_routing); - - pci_write_config8(dev, D31F0_PIRQE_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQF_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQG_ROUT, pirq_routing); - pci_write_config8(dev, D31F0_PIRQH_ROUT, pirq_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing); + + pci_write_config8(dev, PIRQE_ROUT, pirq_routing); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 99fa5306ff0..2cd4903c87d 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -3,6 +3,7 @@ #include #include #include +#include #include "pch.h" #include "chip.h" diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 4df47f3cf17..dbc6e2ba381 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -8,10 +8,11 @@ #include #include #include +#include static void early_gpio_init(void) { - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(PCH_LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index bdf711b19d0..44a12dd98aa 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 97247612a84..6691168b0a4 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_IBEXPEAK_PCH_H #include +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ /* PCH types */ @@ -100,8 +101,6 @@ void pch_enable(struct device *dev); #define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) -#define BIOS_CNTL 0xDC -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 @@ -110,32 +109,6 @@ void pch_enable(struct device *dev); #define GPI_IS_SCI 0x02 #define GPI_IS_NMI 0x03 -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ - /* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) @@ -163,9 +136,6 @@ void pch_enable(struct device *dev); #define HST_EN (1 << 0) /* Southbridge IO BARs */ - -#define GPIOBASE 0x48 - #define PMBASE 0x40 #define VCH 0x0000 /* 32bit */ diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ced6a7c044..f21c809fdee 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 34f0753df88..27648b91deb 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -13,7 +13,6 @@ static void azalia_pch_init(struct device *dev, u8 *base) { - u8 reg8; u16 reg16; u32 reg32; @@ -44,12 +43,15 @@ static void azalia_pch_init(struct device *dev, u8 *base) pci_write_config32(dev, 0x120, reg32); } - reg8 = pci_read_config8(dev, 0x43); + /* TODO: Clean up and verify */ +#if !CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + u8 reg8 = pci_read_config8(dev, 0x43); if (pch_is_lp()) reg8 &= ~(1 << 6); else reg8 |= (1 << 4); pci_write_config8(dev, 0x43, reg8); +#endif if (!pch_is_lp()) pci_or_config32(dev, 0xc0, 1 << 17); @@ -105,6 +107,37 @@ static void azalia_init(struct device *dev) } } +static void azalia_enable(struct device *dev) +{ + /* TODO: Clean up and verify for LPT-LP */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + u16 reg16; + u8 reg8; + + reg8 = pci_read_config8(dev, 0x43); + reg8 |= 0x6f; + pci_write_config8(dev, 0x43, reg8); + + if (!dev->enabled) { + /* Route I/O buffers to ADSP function */ + reg8 = pci_read_config8(dev, 0x42); + reg8 |= (1 << 7) | (1 << 6); + pci_write_config8(dev, 0x42, reg8); + + printk(BIOS_INFO, "Azalia disabled, I/O buffers routed to ADSP\n"); + + /* Ensure memory, io, and bus master are all disabled */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* Disable this device */ + pch_disable_devfn(dev); + } +#endif +} + static void azalia_final(struct device *dev) { /* Set HDCFG.BCLD */ @@ -116,6 +149,7 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, + .enable = azalia_enable, .final = azalia_final, .ops_pci = &pci_dev_ops_pci, }; @@ -124,6 +158,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_AUDIO, PCI_DID_INTEL_LPT_H_AUDIO_9, PCI_DID_INTEL_LPT_LP_AUDIO, + PCI_DID_INTEL_WPT_LP_AUDIO, 0 }; diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 5bdebef4184..d7e719f1c4f 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -25,18 +25,18 @@ static void set_spi_speed(void) u8 ssfc; /* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(FDOC) = 0x1000; + RCBA32(SPIBAR_FDOC) = 0x1000; /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(FDOD); + fdod = RCBA32(SPIBAR_FDOD); fdod >>= 24; fdod &= 7; /* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SSFC + 2); + ssfc = RCBA8(SPIBAR_SSFC + 2); ssfc &= ~7; ssfc |= fdod; - SPIBAR8(SSFC + 2) = ssfc; + RCBA8(SPIBAR_SSFC + 2) = ssfc; } void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/intel/lynxpoint/cfr.h b/src/southbridge/intel/lynxpoint/cfr.h index 4d56b5c4217..83950ea8b59 100644 --- a/src/southbridge/intel/lynxpoint/cfr.h +++ b/src/southbridge/intel/lynxpoint/cfr.h @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * CFR enums and structs for sb/lynxpoint + * CFR enums and structs for sb/intel/lynxpoint */ #ifndef _LYNXPOINT_CFR_H_ #define _LYNXPOINT_CFR_H_ #include -#include "pch.h" +#include "pch_minimal.h" /* Power state after power loss */ static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ @@ -35,6 +35,11 @@ static const struct sm_object me_disable = SM_DECLARE_ENUM({ SM_ENUM_VALUE_END }, }); +/* + * Wildcat Point code does not implement the NMI option, so do not expose it + * TODO: Clean this up after unification, possibly drop the NMI option altogether + */ +#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) enum { NMI_OFF = 0, NMI_ON, @@ -51,5 +56,6 @@ static const struct sm_object nmi = SM_DECLARE_ENUM({ { "Enabled", NMI_ON }, SM_ENUM_VALUE_END }, }); +#endif #endif /* _LYNXPOINT_CFR_H_ */ diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 12bb401f776..2248946dc76 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -3,6 +3,11 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H +/* Temporary, to make it easier to unify LPT and WPT */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) +#include +#else + #include struct southbridge_intel_lynxpoint_config { @@ -40,6 +45,7 @@ struct southbridge_intel_lynxpoint_config { /* SATA configuration */ uint8_t sata_port_map; + uint8_t sata_hotplug_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; uint32_t sata_port0_gen3_dtle; @@ -91,4 +97,9 @@ struct southbridge_intel_lynxpoint_config { bool docking_supported; }; +/* Temporary, to make it easier to unify LPT and WPT */ +typedef struct southbridge_intel_lynxpoint_config pch_config_t; + +#endif /* CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) */ + #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6dab65238e5..179da50acdb 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -6,7 +6,9 @@ #include #include #include +#include #include + #include "me.h" #include "pch.h" @@ -118,7 +120,6 @@ int intel_early_me_init_done(u8 status) { u8 reset; int count; - u32 mebase_l, mebase_h; union me_hfs hfs; union me_did did = { .init_done = ME_INIT_DONE, @@ -126,8 +127,8 @@ int intel_early_me_init_done(u8 status) }; /* MEBASE from MESEG_BASE[35:20] */ - mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L); - mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf; + const u32 mebase_l = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 0); + const u32 mebase_h = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4) & 0xf; did.uma_base = (mebase_l >> 20) | (mebase_h << 12); /* Send message to ME */ @@ -195,3 +196,38 @@ int intel_early_me_init_done(u8 status) } return -1; } + +void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) +{ + int count; + u32 hsiover; + + /* Query for HSIO version, overloads H_GS and HFS */ + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) }; + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printk(BIOS_ERR, "ME failed to respond\n"); + return; + } + + /* HSIO version should be in HFS_5 */ + hsiover = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS5); + *version = hsiover >> 16; + *checksum = hsiover & 0xffff; + + printk(BIOS_DEBUG, "ME: HSIO Version : %d (CRC 0x%04x)\n", + *version, *checksum); + + /* Reset registers to normal behavior */ + /* TODO: Should this be ME_HSIO_CMD_CLOSE instead? */ + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 61c7ac196e3..da50f39f3d9 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include "pch.h" @@ -40,7 +41,7 @@ static void pch_enable_bars(void) /* Enable ACPI BAR */ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(PCH_LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); @@ -57,7 +58,7 @@ static void pch_generic_setup(void) void pch_enable_lpc(void) { const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_lynxpoint_config *config = NULL; + const pch_config_t *config = NULL; /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c index 452c8a5c0e8..04b5055c305 100644 --- a/src/southbridge/intel/lynxpoint/early_pch_native.c +++ b/src/southbridge/intel/lynxpoint/early_pch_native.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -97,7 +98,7 @@ void early_pch_init_native(bool s3resume) early_sata_init(pch_revision); pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1); - pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1)); + pci_and_config8(PCH_LPC_DEV, BIOS_CNTL, ~(BIOS_CNTL_SMM_BWP | BIOS_CNTL_BLE)); /** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/ diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 2eec269ee04..9ce8205e624 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "chip.h" @@ -8,7 +7,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { struct device *dev = pcidev_on_root(0x1f, 0); - struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; + const pch_config_t *cfg = dev->chip_info; u16 pmbase = get_pmbase(); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index e5884e8d8d7..b5413656a2a 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "pch.h" #include "lp_gpio.h" @@ -13,10 +14,10 @@ static u16 get_gpio_base(void) { #ifdef __SIMPLE_DEVICE__ - return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + return pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc; #else return pci_read_config16(pcidev_on_root(0x1f, 0), - GPIO_BASE) & 0xfffc; + GPIOBASE) & 0xfffc; #endif } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index bd6ac0729e9..38cc4a5e938 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -17,6 +17,7 @@ #include "pch.h" #include #include +#include #include #include #include @@ -141,7 +142,7 @@ static void pch_pirq_init(struct device *dev) } static void pch_gpi_routing(struct device *dev, - struct southbridge_intel_lynxpoint_config *config) + const pch_config_t *config) { u32 reg32 = 0; @@ -241,7 +242,7 @@ static void pch_power_options(struct device *dev) pci_write_config16(dev, GEN_PMCON_1, reg16); if (dev->chip_info) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; /* * Set the board's GPI routing on LynxPoint-H. @@ -316,7 +317,7 @@ static void configure_dmi_pm(struct device *dev) /* LynxPoint PCH Power Management init */ static void lpt_pm_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; struct device *const pcie_dev = pcidev_on_root(0x1c, 0); @@ -400,7 +401,7 @@ static void lpt_pm_init(struct device *dev) /* LynxPoint LP PCH Power Management init */ static void lpt_lp_pm_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; u32 data; printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); @@ -720,14 +721,14 @@ static void pch_lpc_add_io_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIOBASE); /* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); /* LPC Generic IO Decode range. */ if (dev->chip_info) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index ddeb4b4b50c..d59040c9b92 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -2,7 +2,7 @@ /* * This is a ramstage driver for the Intel Management Engine found in the - * 6-series chipset. It handles the required boot-time messages over the + * 8 / 9 series PCH. It handles the required boot-time messages over the * MMIO-based Management Engine Interface to tell the ME that the BIOS is * finished with POST. Additional messages are defined for debug but are * not used unless the console loglevel is high enough. @@ -506,7 +506,6 @@ static int mkhi_end_of_post(void) u32 eop_ack; /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; @@ -516,18 +515,83 @@ static int mkhi_end_of_post(void) return 0; } -void intel_me_finalize(struct device *dev) +/* TODO: Unify ME finalisation between LPT and WPT */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + +/* Send END OF POST message to the ME */ +static int mkhi_end_of_post_noack(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST_NOACK, + }; + + /* Send request, do not wait for response */ + if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) { + printk(BIOS_ERR, "ME: END OF POST NOACK message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST NOACK message successful\n"); + return 0; +} + +/* Send HMRFPO LOCK message to the ME */ +static int mkhi_hmrfpo_lock(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_HMRFPO, + .command = MKHI_HMRFPO_LOCK, + }; + u32 ack; + + /* Send request and wait for response */ + if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &ack, sizeof(ack)) < 0) { + printk(BIOS_ERR, "ME: HMRFPO LOCK message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: HMRFPO LOCK message successful (%d)\n", ack); + return 0; +} + +/* Send HMRFPO LOCK message to the ME, do not wait for response */ +static int mkhi_hmrfpo_lock_noack(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_HMRFPO, + .command = MKHI_HMRFPO_LOCK_NOACK, + }; + + /* Send request, do not wait for response */ + if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) { + printk(BIOS_ERR, "ME: HMRFPO LOCK NOACK message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: HMRFPO LOCK NOACK message successful\n"); + return 0; +} + +#endif + +static void intel_me_finalize(struct device *dev) { + /* TODO: Unify ME finalisation between LPT and WPT */ +#if !CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) union me_hfs hfs; u32 reg32; reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); mei_base_address = (u8 *)(uintptr_t)(reg32 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +#endif /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) return; + /* TODO: Unify ME finalisation between LPT and WPT */ +#if !CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(dev); @@ -542,6 +606,7 @@ void intel_me_finalize(struct device *dev) /* Try to send EOP command so ME stops accepting other commands */ mkhi_end_of_post(); +#endif if (!get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI))) return; @@ -552,6 +617,7 @@ void intel_me_finalize(struct device *dev) /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); + RCBA32(FD2); } static int me_icc_set_clock_enables(u32 mask) @@ -713,6 +779,23 @@ static int intel_me_extend_valid(struct device *dev) return 0; } +static void intel_me_print_mbp(struct me_bios_payload *mbp_data) +{ + me_print_fw_version(mbp_data->fw_version_name); + + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data->fw_capabilities); + + if (mbp_data->plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data->plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data->plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data->plat_time->pltrst_cpurst_time_ms); + } +} + static u32 me_to_host_words_pending(void) { union mei_csr me = read_me_csr(); @@ -732,6 +815,7 @@ struct mbp_payload { * * Return -1 to indicate a problem (give up) * Return 0 to indicate success (send LOCK+EOP) + * Return 1 to indicate success (send LOCK+EOP with NOACK) */ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *dev) { @@ -741,16 +825,19 @@ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *de union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; struct mbp_payload *mbp; int i; + int ret = 0; if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); - goto mbp_failure; + intel_me_mbp_give_up(dev); + return -1; } me2host_pending = me_to_host_words_pending(); if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data!\n"); - goto mbp_failure; + intel_me_mbp_give_up(dev); + return -1; } /* we know for sure that at least the header is there */ @@ -762,11 +849,14 @@ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *de " buffer contains %d words\n", mbp_hdr.num_entries, mbp_hdr.mbp_size, me2host_pending); - goto mbp_failure; + intel_me_mbp_give_up(dev); + return -1; } mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); - if (!mbp) - goto mbp_failure; + if (!mbp) { + intel_me_mbp_give_up(dev); + return -1; + } mbp->header = mbp_hdr; me2host_pending--; @@ -777,61 +867,91 @@ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *de i++; } - /* Signal to the ME that the host has finished reading the MBP. */ host = read_host_csr(); + + /* + * FIXME: Replace preprocessor once we know the correct flows + * for each ME version. There does not seem to be ANY mention + * of the "no-ack" versions of E ND OF POST / HMRFPO LOCK MKHI + * messages that Wildcat Point code makes use of. Can they be + * used on ME 9.x (LPT) or are they ME 10.x (WPT-LP) only? + */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + /* Check that read and write pointers are equal. */ + if (host.buffer_read_ptr != host.buffer_write_ptr) { + printk(BIOS_INFO, "ME: MBP Read/Write pointer mismatch\n"); + printk(BIOS_INFO, "ME: MBP Waiting for MBP cleared flag\n"); + + /* Tell ME that the host has finished reading the MBP. */ + host.interrupt_generate = 1; + host.reset = 0; + write_host_csr(host); + + /* Wait for the mbp_cleared indicator. */ + intel_me_mbp_clear(dev); + } else { + /* Indicate NOACK messages should be used. */ + ret = 1; + } +#else + /* Signal to the ME that the host has finished reading the MBP. */ host.interrupt_generate = 1; write_host_csr(host); +#endif /* Dump out the MBP contents. */ - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + if (CONFIG(DEBUG_INTEL_ME)) { printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); - if (CONFIG(DEBUG_INTEL_ME)) { - for (i = 0; i < mbp->header.mbp_size - 1; i++) { - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); - } - } + for (i = 0; i < mbp->header.mbp_size - 1; i++) + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } - #define ASSIGN_FIELD_PTR(field_,val_) \ - { \ - mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ +#define ASSIGN_FIELD_PTR(field_, val_) \ + { \ + mbp_data->field_ = (typeof(mbp_data->field_))val_; \ break; \ - } - /* Setup the pointers in the me_bios_payload structure. */ + } + + /* + * Set up the pointers in the me_bios_payload structure. + * We must NOT free `mbp` afterwards, because the memory + * is still referenced by the pointers in `mbp_data`! + */ for (i = 0; i < mbp->header.mbp_size - 1;) { struct mbp_item_header *item = (void *)&mbp->data[i]; + void *item_data = &mbp->data[i + 1]; switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { case MBP_IDENT(KERNEL, FW_VER): - ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(fw_version_name, item_data); case MBP_IDENT(ICC, PROFILE): - ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(icc_profile, item_data); case MBP_IDENT(INTEL_AT, STATE): - ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(at_state, item_data); case MBP_IDENT(KERNEL, FW_CAP): - ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(fw_capabilities, item_data); case MBP_IDENT(KERNEL, ROM_BIST): - ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(rom_bist_data, item_data); case MBP_IDENT(KERNEL, PLAT_KEY): - ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(platform_key, item_data); case MBP_IDENT(KERNEL, FW_TYPE): - ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(fw_plat_type, item_data); case MBP_IDENT(KERNEL, MFS_FAILURE): - ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(mfsintegrity, item_data); case MBP_IDENT(KERNEL, PLAT_TIME): - ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(plat_time, item_data); case MBP_IDENT(NFC, SUPPORT_DATA): - ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); + ASSIGN_FIELD_PTR(nfc_data, item_data); default: printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " @@ -840,19 +960,15 @@ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *de } i += item->length; } - #undef ASSIGN_FIELD_PTR +#undef ASSIGN_FIELD_PTR - return 0; - -mbp_failure: - intel_me_mbp_give_up(dev); - return -1; + return ret; } /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; enum me_bios_path path = intel_me_path(dev); struct me_bios_payload mbp_data; @@ -875,32 +991,68 @@ static void intel_me_init(struct device *dev) if (intel_mei_setup(dev) < 0) return; - if (intel_me_read_mbp(&mbp_data, dev)) + /* Read ME MBP data */ + int mbp_ret = intel_me_read_mbp(&mbp_data, dev); + if (mbp_ret < 0) return; - - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { - me_print_fw_version(mbp_data.fw_version_name); - - if (CONFIG(DEBUG_INTEL_ME)) - me_print_fwcaps(mbp_data.fw_capabilities); - - if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); - } - } + intel_me_print_mbp(&mbp_data); /* Set clock enables according to devicetree */ if (config && config->icc_clock_disable) me_icc_set_clock_enables(config->icc_clock_disable); + /* + * TODO: Unify ME finalisation between LPT and WPT. ME10 BWG + * recommends sending the HMRFPO LOCK message prior to OpROM + * execution, but we might want to skip sending that in case + * one wants to send HMRFPO ENABLE afterwards. + * + * TODO: ME10 BWG states that neither HMRFPO LOCK nor END OF + * POST MKHI messages should be sent when resuming from S3. + */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + /* Make sure ME is in a mode that expects EOP */ + union me_hfs hfs = { .raw = pci_read_config32(dev, PCI_ME_HFS) }; + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + if (mbp_ret) { + /* + * MBP Cleared wait is skipped, + * Do not expect ACK and reset when complete. + */ + + /* Send HMRFPO Lock command, no response */ + mkhi_hmrfpo_lock_noack(); + + /* Send END OF POST command, no response */ + mkhi_end_of_post_noack(); + + /* Assert reset and interrupt */ + union mei_csr csr = read_host_csr(); + csr.interrupt_generate = 1; + csr.reset = 1; + write_host_csr(csr); + } else { + /* + * MBP Cleared wait was not skipped + */ + + /* Send HMRFPO LOCK command */ + mkhi_hmrfpo_lock(); + + /* Send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + } +#else /* * Leave the ME unlocked. It will be locked later. */ +#endif } static void intel_me_enable(struct device *dev) @@ -926,6 +1078,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_MEI, PCI_DID_INTEL_LPT_H_MEI_9, PCI_DID_INTEL_LPT_LP_MEI, + PCI_DID_INTEL_WPT_LP_MEI, 0 }; diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 489fc6dc46d..24e037f3b1b 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -3,7 +3,6 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H -#include #include #define ME_RETRY 100000 /* 1 second */ @@ -13,10 +12,6 @@ * Management Engine PCI registers */ -#define PCI_CPU_DEVICE PCI_DEV(0,0,0) -#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ -#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ - #define PCI_ME_HFS 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 @@ -89,6 +84,10 @@ union me_uma { #define ME_INIT_STATUS_ERROR 2 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ +#define ME_HSIO_MESSAGE (7 << 28) +#define ME_HSIO_CMD_GETHSIOVER 1 +#define ME_HSIO_CMD_CLOSE 0 + union me_did { struct __packed { u32 uma_base: 16; @@ -196,6 +195,8 @@ union me_hfs2 { u32 raw; }; +#define PCI_ME_HFS5 0x68 + #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -260,19 +261,19 @@ union mei_header { }; #define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GLOBAL_RESET 0x0b #define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_GROUP_ID_HMRFPO 0x05 +#define MKHI_HMRFPO_LOCK 0x02 +#define MKHI_HMRFPO_LOCK_NOACK 0x05 #define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_MDES_ENABLE 0x09 #define MKHI_GROUP_ID_GEN 0xff - -#define MKHI_GLOBAL_RESET 0x0b - -#define MKHI_FWCAPS_GET_RULE 0x02 - -#define MKHI_MDES_ENABLE 0x09 - -#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_END_OF_POST 0x0c -#define MKHI_FEATURE_OVERRIDE 0x14 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 +#define MKHI_END_OF_POST_NOACK 0x1a struct mkhi_header { u32 group_id: 8; @@ -335,17 +336,6 @@ enum me_bios_path { ME_FIRMWARE_UPDATE_BIOS_PATH, }; -/* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); - -void intel_early_me_status(void); -int intel_early_me_init(void); -bool intel_early_me_cpu_replacement_check(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); - -void intel_me_finalize(struct device *dev); - /* * ME to BIOS Payload Datastructures and definitions. The ordering of the * structures follows the ordering in the ME9 BWG. @@ -510,5 +500,15 @@ struct me_fwcaps { struct mbp_mefwcaps caps_sku; u8 reserved[3]; } __packed; +void intel_me_hsio_version(uint16_t *version, uint16_t *checksum); + +/* Defined in me_status.c for both romstage and ramstage */ +void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); + +void intel_early_me_status(void); +int intel_early_me_init(void); +bool intel_early_me_cpu_replacement_check(void); +int intel_early_me_uma_size(void); +int intel_early_me_init_done(u8 status); #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index f9e0fcbb5b2..bab9eed58b7 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -3,15 +3,29 @@ #include #include "me.h" +#define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \ + (((__index__) < ARRAY_SIZE((__array__))) ? \ + (__array__)[(__index__)] : \ + (__default__)) + /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", + [3] = "Unknown (3)", + [4] = "Unknown (4)", [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", + [9] = "Unknown (9)", + [10] = "Unknown (10)", + [11] = "Unknown (11)", + [12] = "Unknown (12)", + [13] = "Unknown (13)", + [14] = "Unknown (14)", + [15] = "Unknown (15)", }; /* HFS1[8:6] Current Operation State Values */ @@ -142,39 +156,61 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2) printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", hfs.update_in_progress ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs.working_state]); + ARRAY_TO_ELEMENT(me_cws_values, + hfs.working_state, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs.operation_state]); + ARRAY_TO_ELEMENT(me_opstate_values, + hfs.operation_state, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs.operation_mode]); + ARRAY_TO_ELEMENT(me_opmode_values, + hfs.operation_mode, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs.error_code]); + ARRAY_TO_ELEMENT(me_error_values, + hfs.error_code, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2.progress_code]); + ARRAY_TO_ELEMENT(me_progress_values, + hfs2.progress_code, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2.current_pmevent]); + ARRAY_TO_ELEMENT(me_pmevent_values, + hfs2.current_pmevent, + "Unknown (OOB)")); printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2.current_state]); + ARRAY_TO_ELEMENT(me_progress_rom_values, + hfs2.current_state, + "Unknown (OOB)")); + break; + + case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2.current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2.current_state]) + if (ARRAY_TO_ELEMENT(me_progress_bup_values, + hfs2.current_state, NULL)) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2.current_state]); + ARRAY_TO_ELEMENT(me_progress_bup_values, + hfs2.current_state, + NULL)); else printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ - if (hfs2.current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[hfs2.current_state]) + if (ARRAY_TO_ELEMENT(me_progress_policy_values, + hfs2.current_state, NULL)) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[hfs2.current_state]); + ARRAY_TO_ELEMENT(me_progress_policy_values, + hfs2.current_state, + NULL)); else printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index ae4e71481f7..80473332ef4 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "iobp.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a5601ff9297..57e1cef2fc6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -4,8 +4,12 @@ #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #include +#include /* IWYU pragma: export */ #include /* IWYU pragma: export */ +/* TODO: Temporary to help unify Lynx Point and Wildcat Point, drop afterwards */ +#include /* IWYU pragma: export */ + #define CROS_GPIO_DEVICE_NAME "LynxPoint" /* @@ -46,72 +50,8 @@ #define SMBUS_SLAVE_ADDR 0x24 -#if CONFIG(INTEL_LYNXPOINT_LP) -#define DEFAULT_PMBASE 0x1000 -#define DEFAULT_GPIOBASE 0x1400 -#define DEFAULT_GPIOSIZE 0x400 -#else -#define DEFAULT_PMBASE 0x500 -#define DEFAULT_GPIOBASE 0x480 -#define DEFAULT_GPIOSIZE 0x80 -#endif - #ifndef __ACPI__ -#if CONFIG(INTEL_LYNXPOINT_LP) -#define MAX_USB2_PORTS 10 -#define MAX_USB3_PORTS 4 -#else -#define MAX_USB2_PORTS 14 -#define MAX_USB3_PORTS 6 -#endif - -/* There are 8 OC pins */ -#define USB_OC_PIN_SKIP 8 - -enum usb2_port_location { - USB_PORT_SKIP = 0, - USB_PORT_BACK_PANEL, - USB_PORT_FRONT_PANEL, - USB_PORT_DOCK, - USB_PORT_MINI_PCIE, - USB_PORT_FLEX, - USB_PORT_INTERNAL, -}; - -/* - * USB port length is in MRC format: binary-coded decimal length in tenths of an inch. - * 4.2 inches -> 0x0042 - * 12.7 inches -> 0x0127 - */ -struct usb2_port_config { - uint16_t length; - bool enable; - unsigned short oc_pin; - enum usb2_port_location location; -}; - -struct usb3_port_config { - bool enable; - unsigned int oc_pin; -}; - -/* Mainboard-specific USB configuration */ -extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS]; -extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS]; - -static inline bool pch_is_lp(void) -{ - return CONFIG(INTEL_LYNXPOINT_LP); -} - -/* PCH platform types, safe for MRC consumption */ -enum pch_platform_type { - PCH_TYPE_MOBILE = 0, - PCH_TYPE_DESKTOP = 1, /* or server */ - PCH_TYPE_ULT = 5, -}; - void pch_dmi_setup_physical_layer(void); void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); void early_usb_init(void); @@ -166,10 +106,6 @@ void uart_bootblock_init(void); void mainboard_config_superio(void); void mainboard_config_rcba(void); -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -230,39 +166,11 @@ void mainboard_config_rcba(void); #define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) -#define BIOS_CNTL 0xDC -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ #define LPC_HnBDF(n) (0x70 + (n) * 2) /* HPET n bus/dev/fn */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ /* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) @@ -463,9 +371,7 @@ void mainboard_config_rcba(void); #define HST_EN (1 << 0) /* Southbridge IO BARs */ - #define PMBASE 0x40 -#define GPIOBASE 0x48 #define CIR0050 0x0050 /* 32bit */ @@ -714,21 +620,7 @@ void mainboard_config_rcba(void); #define LP_GPE0_EN_3 0x98 #define LP_GPE0_EN_4 0x9c -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPIBAR_OFFSET 0x3800 -#define SPIBAR8(x) RCBA8((x) + SPIBAR_OFFSET) -#define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) -#define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET) - -/* Registers within the SPIBAR */ -#define SSFC 0x91 -#define FDOC 0xb0 -#define FDOD 0xb4 - +/* Registers within SPIBAR */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ @@ -743,5 +635,9 @@ void mainboard_config_rcba(void); #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * (n))) /* SPI flash data */ +#define SPIBAR_SSFC 0x3891 +#define SPIBAR_FDOC 0x38b0 +#define SPIBAR_FDOD 0x38b4 + #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */ diff --git a/src/southbridge/intel/lynxpoint/pch_minimal.h b/src/southbridge/intel/lynxpoint/pch_minimal.h new file mode 100644 index 00000000000..9698f25a45f --- /dev/null +++ b/src/southbridge/intel/lynxpoint/pch_minimal.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_MINIMAL_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_MINIMAL_H + +/* + * Temporary file to assist in unifying Lynx Point and Wildcat Point + */ + +#if CONFIG(INTEL_LYNXPOINT_LP) +#define DEFAULT_PMBASE 0x1000 +#define DEFAULT_GPIOBASE 0x1400 +#define DEFAULT_GPIOSIZE 0x400 +#else +#define DEFAULT_PMBASE 0x500 +#define DEFAULT_GPIOBASE 0x480 +#define DEFAULT_GPIOSIZE 0x80 +#endif + +#ifndef __ACPI__ + +#include + +#if CONFIG(INTEL_LYNXPOINT_LP) +#define MAX_USB2_PORTS 10 +#define MAX_USB3_PORTS 4 +#else +#define MAX_USB2_PORTS 14 +#define MAX_USB3_PORTS 6 +#endif + +/* There are 8 OC pins */ +#define USB_OC_PIN_SKIP 8 + +enum usb2_port_location { + USB_PORT_SKIP = 0, + USB_PORT_BACK_PANEL, + USB_PORT_FRONT_PANEL, + USB_PORT_DOCK, + USB_PORT_MINI_PCIE, + USB_PORT_FLEX, + USB_PORT_INTERNAL, +}; + +/* + * USB port length is in MRC format: binary-coded decimal length in tenths of an inch. + * 4.2 inches -> 0x0042 + * 12.7 inches -> 0x0127 + */ +struct usb2_port_config { + uint16_t length; + bool enable; + unsigned short oc_pin; + enum usb2_port_location location; +}; + +struct usb3_port_config { + bool enable; + unsigned int oc_pin; + /* + * Set to 0 if trace length is > 5 inches + * Set to 1 if trace length is <= 5 inches + */ + uint8_t fixed_eq; +}; + +/* Mainboard-specific USB configuration */ +extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS]; +extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS]; + +static inline bool pch_is_lp(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} + +/* PCH platform types, safe for MRC consumption */ +enum pch_platform_type { + PCH_TYPE_MOBILE = 0, + PCH_TYPE_DESKTOP = 1, /* or server */ + PCH_TYPE_ULT = 5, +}; + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_MINIMAL_H */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 969095207d9..d985ac928a6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -165,11 +166,17 @@ static void root_port_init_config(struct device *dev) rpc.num_ports = max_root_ports(); rpc.gbe_port = -1; + /* TODO: This is part of Power Management Programming in LPT RC */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + /* RP0 f5[3:0] = 0101b */ + pci_update_config8(dev, 0xf5, ~0xf, 0x5); +#endif + rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); if (dev->chip_info != NULL) { - struct southbridge_intel_lynxpoint_config *config; + const pch_config_t *config; config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce; @@ -205,6 +212,24 @@ static void root_port_init_config(struct device *dev) break; } + /* FIXME: This is conditional on LPT */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + pci_write_config32(dev, 0x418, 0x02000430); + + if (root_port_is_first(dev)) { + /* + * Set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1 + * before configuring ASPM + */ + u32 data = 0; + u8 resp; + u8 id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07); + pch_iobp_exec(0xe00000e0, IOBP_PCICFG_READ, id, &data, &resp); + data |= 0x30 << 16 | 0x40 << 8; + pch_iobp_exec(0xe00000e0, IOBP_PCICFG_WRITE, id, &data, &resp); + } +#endif + /* Cache pci device. */ rpc.ports[rp - 1] = dev; } @@ -303,17 +328,43 @@ static void pcie_enable_clock_gating(void) } /* Update PECR1 register. */ + /* FIXME: Figure out correct value for LPT */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + pci_or_config8(dev, 0xe8, 3); +#else pci_or_config8(dev, 0xe8, 1); +#endif - pci_or_config8(dev, 0x324, 1 << 5); + if (cpu_is_broadwell()) { + pci_or_config32(dev, 0x324, (1 << 5) | (1 << 14)); + } else { + pci_or_config32(dev, 0x324, 1 << 5); + } /* Per-Port CLKREQ# handling. */ - if (is_lp && gpio_is_native(18 + rp - 1)) + if (is_lp && gpio_is_native(18 + rp - 1)) { + /* FIXME: Confirm programming sequence (seems conditional?) */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + /* + * In addition to D28Fx PCICFG 420h[30:29] = 11b, + * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. + */ + pci_update_config32(dev, 0x420, ~(1 << 17), 3 << 29 | 1); +#else pci_or_config32(dev, 0x420, 3 << 29); +#endif + } /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) pci_or_config8(dev, 0xe1, 0x3c); + + /* FIXME: Should only be set for enabled CLKREQ# pins */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + /* CLKREQ# VR Idle Enable */ + if (is_lp) + RCBA32_OR(0x2b1c, 1 << (16 + i)); +#endif } if (!enabled_ports && is_lp && rpc.ports[0]) @@ -546,7 +597,7 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; int do_aspm = 0; int rp = root_port_number(dev); int is_lp = pch_is_lp(); @@ -704,7 +755,12 @@ static void pch_pcie_early(struct device *dev) /* Set Common Clock Exit Latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + /* TODO: Figure out why this value is different */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); +#else pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); +#endif /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); @@ -787,6 +843,17 @@ static void pch_pcie_enable(struct device *dev) root_port_commit_config(); } +static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop) +{ + *max_snoop = PCIE_LTR_MAX_SNOOP_LATENCY_3146US; + *max_nosnoop = PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US; +} + +static struct pci_operations pcie_ops_with_ltr = { + .set_subsystem = pci_dev_set_subsystem, + .get_ltr_max_latencies = pcie_get_ltr_max_latencies, +}; + static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -794,7 +861,7 @@ static struct device_operations device_ops = { .init = pch_pcie_init, .enable = pch_pcie_enable, .scan_bus = pciexp_scan_bridge, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &pcie_ops_with_ltr, }; static const unsigned short pci_device_ids[] = { @@ -820,6 +887,12 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_LP_PCIE_RP4, PCI_DID_INTEL_LPT_LP_PCIE_RP5, PCI_DID_INTEL_LPT_LP_PCIE_RP6, + PCI_DID_INTEL_WPT_LP_PCIE_RP1, + PCI_DID_INTEL_WPT_LP_PCIE_RP2, + PCI_DID_INTEL_WPT_LP_PCIE_RP3, + PCI_DID_INTEL_WPT_LP_PCIE_RP4, + PCI_DID_INTEL_WPT_LP_PCIE_RP5, + PCI_DID_INTEL_WPT_LP_PCIE_RP6, 0 }; diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 06075c24a6a..82bdaf1f343 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,6 +24,20 @@ #define GPIO_ALT_GPI_SMI_STS 0x50 #define GPIO_ALT_GPI_SMI_EN 0x54 +/* TODO: Deduplicate */ +#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) +uint16_t get_gpiobase(void) +{ + return DEFAULT_GPIOBASE; +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return DEFAULT_PMBASE; +} +#endif + /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) { @@ -297,11 +311,12 @@ void enable_alt_smi(u32 mask) * TCO */ -/* Clear TCO status and return events that are active */ +/* Clear TCO status and return events that are enabled and active */ static u32 reset_tco_status(void) { u32 tcobase = get_pmbase() + 0x60; u32 tco_sts = inl(tcobase + 0x04); + u32 tco_en = inl(get_pmbase() + 0x68); /* Don't clear BOOT_STS before SECOND_TO_STS */ outl(tco_sts & ~(1 << 18), tcobase + 0x04); @@ -310,7 +325,7 @@ static u32 reset_tco_status(void) if (tco_sts & (1 << 18)) outl(tco_sts & (1 << 18), tcobase + 0x04); - return tco_sts; + return tco_sts & tco_en; } /* Print TCO status bits */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index b6cbb133dad..43b08ea4cc1 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -41,10 +41,10 @@ static void sata_init(struct device *dev) { u32 reg32; - u32 *abar; + uintptr_t abar; /* Get the chip configuration */ - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -99,21 +99,21 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); + abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", (void *)abar); /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); + reg32 = read32p(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS if (pch_is_lp()) reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); + write32p(abar + 0x00, reg32); /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ + write32p(abar + 0x0c, config->sata_port_map); + (void)read32p(abar + 0x0c); /* Read back 1 */ + (void)read32p(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); + reg32 = read32p(abar + 0x24); /* Enable DEVSLP */ if (pch_is_lp()) { if (config->sata_devslp_disable) @@ -123,7 +123,16 @@ static void sata_init(struct device *dev) } else { reg32 &= ~0x00000002; } - write32(abar + 0x09, reg32); + write32p(abar + 0x24, reg32); + + /* PxCMD */ + const unsigned int num_ports = pch_is_lp() ? 4 : 6; + for (unsigned int port = 0; port < num_ports; port++) { + reg32 = read32p(abar + 0x118 + 0x80 * port); + if (config->sata_hotplug_map & (1 << port)) + reg32 |= 1 << 18; + write32p(abar + 0x118 + 0x80 * port, reg32); + } /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) @@ -197,7 +206,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; if (!config) return; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 208c52ab44e..e3408d7e82a 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -156,7 +156,7 @@ static void update_bars(int sio_index, u32 bar0, u32 bar1) static void serialio_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = config_of(dev); + const pch_config_t *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9ae78793a26..5f7d48af778 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -13,9 +13,12 @@ void smm_southbridge_clear_state(void) { u32 smi_en; + /* TODO: Consolidate LPT/WPT power state handling */ +#if !CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) /* Log events from chipset before clearing */ if (CONFIG(ELOG)) pch_log_state(); +#endif smi_en = inl(get_pmbase() + SMI_EN); if (smi_en & APMC_EN) { diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 838b448db44..a459c67ad0b 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -5,13 +5,17 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include +#include +#include #include #include #include @@ -238,9 +242,20 @@ static void southbridge_smi_store(void) /* Parameter buffer in EBX */ reg_ebx = io_smi->rbx; + const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + const bool wp_enabled = !(pci_read_config16(lpc_dev, BIOS_CNTL) & BIOS_CNTL_BIOSWE); + if (wp_enabled) { + set_insmm_sts(true); + pci_or_config16(lpc_dev, BIOS_CNTL, BIOS_CNTL_BIOSWE); + } /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_ebx); io_smi->rax = ret; + + if (wp_enabled) { + pci_and_config16(lpc_dev, BIOS_CNTL, ~BIOS_CNTL_BIOSWE); + set_insmm_sts(false); + } } static void southbridge_smi_apmc(void) @@ -257,7 +272,6 @@ static void southbridge_smi_apmc(void) } intel_pch_finalize_smm(); - intel_cpu_haswell_finalize_smm(); chipset_finalized = 1; break; @@ -334,7 +348,7 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL); - if (bios_cntl & 1) { + if (bios_cntl & BIOS_CNTL_BIOSWE) { /* * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS @@ -346,7 +360,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, bios_cntl & ~BIOS_CNTL_BIOSWE); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 2660be16679..8e94aef801c 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -275,7 +275,7 @@ static void usb_xhci_init(struct device *dev) { u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + const pch_config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); diff --git a/src/southbridge/intel/wildcatpoint/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig index 424b91d8329..513c9473e3c 100644 --- a/src/southbridge/intel/wildcatpoint/Kconfig +++ b/src/southbridge/intel/wildcatpoint/Kconfig @@ -17,6 +17,8 @@ config SOUTHBRIDGE_INTEL_WILDCATPOINT select INTEL_LYNXPOINT_LP select RTC select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/wildcatpoint/Makefile.mk b/src/southbridge/intel/wildcatpoint/Makefile.mk index 59f48805ce2..daac5ce2891 100644 --- a/src/southbridge/intel/wildcatpoint/Makefile.mk +++ b/src/southbridge/intel/wildcatpoint/Makefile.mk @@ -6,6 +6,7 @@ bootblock-y += bootblock.c ramstage-y += acpi.c ramstage-y += adsp.c +romstage-y += ../lynxpoint/early_me.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c @@ -13,28 +14,28 @@ ramstage-y += ../lynxpoint/lp_gpio.c romstage-y += ../lynxpoint/lp_gpio.c verstage-y += ../lynxpoint/lp_gpio.c smm-y += ../lynxpoint/lp_gpio.c -ramstage-y += hda.c +ramstage-y += ../lynxpoint/azalia.c ramstage-y += ../lynxpoint/hda_verb.c ramstage-y += ../lynxpoint/iobp.c romstage-y += ../lynxpoint/iobp.c ramstage-y += fadt.c ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c +ramstage-y += ../lynxpoint/me.c +ramstage-y += ../lynxpoint/me_status.c +romstage-y += ../lynxpoint/me_status.c ramstage-y += pch.c romstage-y += pch.c -ramstage-y += pcie.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c +ramstage-y += ../lynxpoint/pcie.c +ramstage-y += ../lynxpoint/pmutil.c +romstage-y += ../lynxpoint/pmutil.c +smm-y += ../lynxpoint/pmutil.c +verstage-y += ../lynxpoint/pmutil.c romstage-y += power_state.c ramstage-y += ramstage.c ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += ../lynxpoint/smbus.c -ramstage-y += smi.c +ramstage-y += ../lynxpoint/smi.c smm-y += smihandler.c bootblock-y += usb_debug.c romstage-y += usb_debug.c diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 80c77212cf4..e5565ed5d12 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -11,6 +11,7 @@ #include #include #include +#include static void map_rcba(void) { @@ -32,18 +33,18 @@ static void set_spi_speed(void) u8 ssfc; /* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(SPIBAR_FDOC) = 0x1000; + RCBA32(SPIBAR_FDOC) = 0x1000; /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(SPIBAR_FDOD); + fdod = RCBA32(SPIBAR_FDOD); fdod >>= 24; fdod &= 7; /* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SPIBAR_SSFC + 2); + ssfc = RCBA8(SPIBAR_SSFC + 2); ssfc &= ~7; ssfc |= fdod; - SPIBAR8(SPIBAR_SSFC + 2) = ssfc; + RCBA8(SPIBAR_SSFC + 2) = ssfc; } static void pch_enable_bars(void) @@ -55,7 +56,7 @@ static void pch_enable_bars(void) pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN); - pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, GPIOBASE, GPIO_BASE_ADDRESS | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN); diff --git a/src/southbridge/intel/wildcatpoint/chip.h b/src/southbridge/intel/wildcatpoint/chip.h index dd316458498..fd4d66b37f1 100644 --- a/src/southbridge/intel/wildcatpoint/chip.h +++ b/src/southbridge/intel/wildcatpoint/chip.h @@ -75,4 +75,7 @@ struct southbridge_intel_wildcatpoint_config { int deep_sx_enable_dc; }; +/* Temporary, to make it easier to unify LPT and WPT */ +typedef struct southbridge_intel_wildcatpoint_config pch_config_t; + #endif diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index adb65e61451..8a13ff95307 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,6 +11,7 @@ #include #include #include +#include #include static void pch_route_interrupts(void) diff --git a/src/southbridge/intel/wildcatpoint/finalize.c b/src/southbridge/intel/wildcatpoint/finalize.c index 71f06390e0d..9df9460b142 100644 --- a/src/southbridge/intel/wildcatpoint/finalize.c +++ b/src/southbridge/intel/wildcatpoint/finalize.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -9,13 +11,13 @@ #include #include -void broadwell_pch_finalize(void) +static void broadwell_pch_finalize(void) { spi_finalize_ops(); /* Lock SPIBAR */ if (!CONFIG(EM100PRO_SPI_CONSOLE)) - RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); + RCBA32_OR(SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); /* TC Lockdown */ RCBA32_OR(0x0050, 1 << 31); @@ -41,3 +43,14 @@ void broadwell_pch_finalize(void) /* Read+Write this R/WO register */ RCBA32(LCAP) = RCBA32(LCAP); } + +static void broadwell_finalize(void *unused) +{ + broadwell_pch_finalize(); + + /* Indicate finalize step with post code */ + post_code(POSTCODE_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c deleted file mode 100644 index ad3d8e92003..00000000000 --- a/src/southbridge/intel/wildcatpoint/hda.c +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void hda_pch_init(struct device *dev, u8 *base) -{ - u8 reg8; - u16 reg16; - u32 reg32; - - if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_read_config32(dev, 0x120); - reg32 &= 0xf8ffff01; - reg32 |= (1 << 25); - reg32 |= RCBA32(0x2030) & 0xfe; - pci_write_config32(dev, 0x120, reg32); - } else - printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n"); - - reg32 = pci_read_config32(dev, 0x114); - reg32 &= ~0xfe; - pci_write_config32(dev, 0x114, reg32); - - // Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { - reg32 = pci_read_config32(dev, 0x120); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0x120, reg32); - } - - /* Additional programming steps */ - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 24); - pci_write_config32(dev, 0xc4, reg32); - - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); - - reg16 = read32(base + 0x0012); - reg16 |= (1 << 0); - write32(base + 0x0012, reg16); - - /* disable Auto Voltage Detector */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x42, reg8); -} - -static void hda_init(struct device *dev) -{ - u8 *base; - struct resource *res; - u32 codec_mask; - - /* Find base address */ - res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "HDA: base = %p\n", base); - - /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - - hda_pch_init(dev, base); - - codec_mask = hda_codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); - azalia_codecs_init(base, codec_mask); - } -} - -static void hda_enable(struct device *dev) -{ - u16 reg16; - u8 reg8; - - reg8 = pci_read_config8(dev, 0x43); - reg8 |= 0x6f; - pci_write_config8(dev, 0x43, reg8); - - if (!dev->enabled) { - /* Route I/O buffers to ADSP function */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= (1 << 7) | (1 << 6); - pci_write_config8(dev, 0x42, reg8); - - printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); - - /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* Disable this device */ - pch_disable_devfn(dev); - } -} - -static void hda_final(struct device *dev) -{ - /* Set HDCFG.BCLD */ - pci_or_config16(dev, 0x40, 1 << 1); -} - -static struct device_operations hda_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &hda_init, - .enable = &hda_enable, - .final = &hda_final, - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - 0x9c20, /* LynxPoint-LP */ - 0x9ca0, /* WildcatPoint */ - 0 -}; - -static const struct pci_driver pch_hda __pci_driver = { - .ops = &hda_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/wildcatpoint/include/soc/cfr.h b/src/southbridge/intel/wildcatpoint/include/soc/cfr.h deleted file mode 100644 index 7f1e604e145..00000000000 --- a/src/southbridge/intel/wildcatpoint/include/soc/cfr.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * CFR enums and structs for northbridge/intel/broadwell - */ - -#ifndef _BROADWELL_CFR_H_ -#define _BROADWELL_CFR_H_ - -#include -#include "pm.h" - -/* Power state after power loss */ -static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ - .opt_name = "power_on_after_fail", - .ui_name = "Restore AC Power Loss", - .ui_helptext = "Specify what to do when power is re-applied after a power loss.", - .default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE, - .values = (const struct sm_enum_value[]) { - { "Power off (S5)", MAINBOARD_POWER_OFF }, - { "Power on (S0)", MAINBOARD_POWER_ON }, - { "Previous state", MAINBOARD_POWER_KEEP }, - SM_ENUM_VALUE_END }, -}); - -/* Intel ME State */ -static const struct sm_object me_disable = SM_DECLARE_ENUM({ - .opt_name = "me_disable", - .ui_name = "Intel Management Engine", - .ui_helptext = "Enable or disable the PCI/HECI interface of the Intel Management Engine", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Disabled", 1 }, - { "Enabled", 0 }, - SM_ENUM_VALUE_END }, -}); - -#endif /* _BROADWELL_CFR_H_ */ diff --git a/src/southbridge/intel/wildcatpoint/include/soc/iomap.h b/src/southbridge/intel/wildcatpoint/include/soc/iomap.h index 551f659ada7..a97276a27a3 100644 --- a/src/southbridge/intel/wildcatpoint/include/soc/iomap.h +++ b/src/southbridge/intel/wildcatpoint/include/soc/iomap.h @@ -3,8 +3,6 @@ #ifndef _BROADWELL_IOMAP_H_ #define _BROADWELL_IOMAP_H_ -#include - #define ACPI_BASE_ADDRESS 0x1000 #define ACPI_BASE_SIZE 0x100 diff --git a/src/southbridge/intel/wildcatpoint/include/soc/lpc.h b/src/southbridge/intel/wildcatpoint/include/soc/lpc.h index ad48a121e1d..75d988a46bc 100644 --- a/src/southbridge/intel/wildcatpoint/include/soc/lpc.h +++ b/src/southbridge/intel/wildcatpoint/include/soc/lpc.h @@ -3,6 +3,8 @@ #ifndef _BROADWELL_LPC_H_ #define _BROADWELL_LPC_H_ +#include /* IWYU pragma: export */ + /* PCI Configuration Space (D31:F0): LPC */ #define SERIRQ_CNTL 0x64 #define PMBASE 0x40 @@ -16,39 +18,10 @@ #define SCIS_IRQ21 5 #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 -#define GPIOBASE 0x48 -#define BIOS_CNTL 0xdc -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_EN (1 << 4) #define GPIO_ROUT 0xb8 -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ #define RCBA 0xf0 /* Root Complex Register Block */ /* Power Management */ diff --git a/src/southbridge/intel/wildcatpoint/include/soc/me.h b/src/southbridge/intel/wildcatpoint/include/soc/me.h deleted file mode 100644 index 959290def1a..00000000000 --- a/src/southbridge/intel/wildcatpoint/include/soc/me.h +++ /dev/null @@ -1,486 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_ME_H_ -#define _BROADWELL_ME_H_ - -#include - -#define ME_RETRY 100000 /* 1 second */ -#define ME_DELAY 10 /* 10 us */ - -/* - * Management Engine PCI registers - */ - -#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ -#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ - -#define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 - -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; -} __packed; - -#define PCI_ME_UMA 0x44 - -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; -} __packed; - -#define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 -#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ - -#define ME_HSIO_MESSAGE (7 << 28) -#define ME_HSIO_CMD_GETHSIOVER 1 -#define ME_HSIO_CMD_CLOSE 0 - -struct me_did { - u32 uma_base: 16; - u32 reserved: 7; - u32 rapid_start: 1; - u32 status: 4; - u32 init_done: 4; -} __packed; - -/* - * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according - * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature. - */ -#define PCI_ME_HFS2 0x48 -/* Infrastructure Progress Values */ -#define ME_HFS2_PHASE_ROM 0 -#define ME_HFS2_PHASE_BUP 1 -#define ME_HFS2_PHASE_UKERNEL 2 -#define ME_HFS2_PHASE_POLICY 3 -#define ME_HFS2_PHASE_MODULE_LOAD 4 -#define ME_HFS2_PHASE_UNKNOWN 5 -#define ME_HFS2_PHASE_HOST_COMM 6 -/* Current State - Based on Infra Progress values. */ -/* ROM State */ -#define ME_HFS2_STATE_ROM_BEGIN 0 -#define ME_HFS2_STATE_ROM_DISABLE 6 -/* BUP State */ -#define ME_HFS2_STATE_BUP_INIT 0 -#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 -#define ME_HFS2_STATE_BUP_FLOW_DET 4 -#define ME_HFS2_STATE_BUP_VSCC_ERR 8 -#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa -#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb -#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd -#define ME_HFS2_STATE_BUP_M3 0x11 -#define ME_HFS2_STATE_BUP_M0 0x12 -#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 -#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 -#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 -#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 -#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c -#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f -#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 -#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 -#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 -#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 -#define ME_HFS2_STATE_BUP_M0_CLK 0x26 -#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 -#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 -#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 -/* Policy Module State */ -#define ME_HFS2_STATE_POLICY_ENTRY 0 -#define ME_HFS2_STATE_POLICY_RCVD_S3 3 -#define ME_HFS2_STATE_POLICY_RCVD_S4 4 -#define ME_HFS2_STATE_POLICY_RCVD_S5 5 -#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 -#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 -#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 -#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 -#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa -#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb -#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc -#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd -#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe -#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf -#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 -/* Current PM Event Values */ -#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 -#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 -#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 -#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 -#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 -#define ME_HFS2_PMEVENT_S0MO_SXM3 7 -#define ME_HFS2_PMEVENT_SXM3_S0M0 8 -#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb -#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc - -struct me_hfs2 { - u32 bist_in_progress: 1; - u32 reserved1: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; - u32 reserved2: 4; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; -} __packed; - -#define PCI_ME_HFS5 0x68 - -#define PCI_ME_H_GS2 0x70 -#define PCI_ME_MBP_GIVE_UP 0x01 - -#define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) - -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; -} __packed; - -/* - * Management Engine MEI registers - */ - -#define MEI_H_CB_WW 0x00 -#define MEI_H_CSR 0x04 -#define MEI_ME_CB_RW 0x08 -#define MEI_ME_CSR_HA 0x0c - -struct mei_csr { - u32 interrupt_enable: 1; - u32 interrupt_status: 1; - u32 interrupt_generate: 1; - u32 ready: 1; - u32 reset: 1; - u32 reserved: 3; - u32 buffer_read_ptr: 8; - u32 buffer_write_ptr: 8; - u32 buffer_depth: 8; -} __packed; - -#define MEI_ADDRESS_CORE 0x01 -#define MEI_ADDRESS_AMT 0x02 -#define MEI_ADDRESS_RESERVED 0x03 -#define MEI_ADDRESS_WDT 0x04 -#define MEI_ADDRESS_MKHI 0x07 -#define MEI_ADDRESS_ICC 0x08 -#define MEI_ADDRESS_THERMAL 0x09 - -#define MEI_HOST_ADDRESS 0 - -struct mei_header { - u32 client_address: 8; - u32 host_address: 8; - u32 length: 9; - u32 reserved: 6; - u32 is_complete: 1; -} __packed; - -#define MKHI_GROUP_ID_CBM 0x00 -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_GROUP_ID_FWCAPS 0x03 -#define MKHI_FWCAPS_GET_RULE 0x02 -#define MKHI_GROUP_ID_HMRFPO 0x05 -#define MKHI_HMRFPO_LOCK 0x02 -#define MKHI_HMRFPO_LOCK_NOACK 0x05 -#define MKHI_GROUP_ID_MDES 0x08 -#define MKHI_MDES_ENABLE 0x09 -#define MKHI_GROUP_ID_GEN 0xff -#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_END_OF_POST 0x0c -#define MKHI_FEATURE_OVERRIDE 0x14 -#define MKHI_END_OF_POST_NOACK 0x1a - -struct mkhi_header { - u32 group_id: 8; - u32 command: 7; - u32 is_response: 1; - u32 reserved: 8; - u32 result: 8; -} __packed; - -struct me_fw_version { - u16 code_minor; - u16 code_major; - u16 code_build_number; - u16 code_hot_fix; - u16 recovery_minor; - u16 recovery_major; - u16 recovery_build_number; - u16 recovery_hot_fix; -} __packed; - -/* ICC Messages */ -#define ICC_SET_CLOCK_ENABLES 0x3 -#define ICC_API_VERSION_LYNXPOINT 0x00030000 - -struct icc_header { - u32 api_version; - u32 icc_command; - u32 icc_status; - u32 length; - u32 reserved; -} __packed; - -struct icc_clock_enables_msg { - u32 clock_enables; - u32 clock_mask; - u32 no_response: 1; - u32 reserved: 31; -} __packed; - -#define HECI_EOP_STATUS_SUCCESS 0x0 -#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 - -#define CBM_RR_GLOBAL_RESET 0x01 - -#define GLOBAL_RESET_BIOS_MRC 0x01 -#define GLOBAL_RESET_BIOS_POST 0x02 -#define GLOBAL_RESET_MEBX 0x03 - -struct me_global_reset { - u8 request_origin; - u8 reset_type; -} __packed; - -typedef enum { - ME_NORMAL_BIOS_PATH, - ME_S3WAKE_BIOS_PATH, - ME_ERROR_BIOS_PATH, - ME_RECOVERY_BIOS_PATH, - ME_DISABLE_BIOS_PATH, - ME_FIRMWARE_UPDATE_BIOS_PATH, -} me_bios_path; - -/* - * ME to BIOS Payload Datastructures and definitions. The ordering of the - * structures follows the ordering in the ME9 BWG. - */ - -#define MBP_APPID_KERNEL 1 -#define MBP_APPID_INTEL_AT 3 -#define MBP_APPID_HWA 4 -#define MBP_APPID_ICC 5 -#define MBP_APPID_NFC 6 -/* Kernel items: */ -#define MBP_KERNEL_FW_VER_ITEM 1 -#define MBP_KERNEL_FW_CAP_ITEM 2 -#define MBP_KERNEL_ROM_BIST_ITEM 3 -#define MBP_KERNEL_PLAT_KEY_ITEM 4 -#define MBP_KERNEL_FW_TYPE_ITEM 5 -#define MBP_KERNEL_MFS_FAILURE_ITEM 6 -#define MBP_KERNEL_PLAT_TIME_ITEM 7 -/* Intel AT items: */ -#define MBP_INTEL_AT_STATE_ITEM 1 -/* ICC Items: */ -#define MBP_ICC_PROFILE_ITEM 1 -/* HWA Items: */ -#define MBP_HWA_REQUEST_ITEM 1 -/* NFC Items: */ -#define MBP_NFC_SUPPORT_DATA_ITEM 1 - -#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) -#define MBP_IDENT(appid, item) \ - MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) - -typedef struct { - u32 mbp_size : 8; - u32 num_entries : 8; - u32 rsvd : 16; -} __packed mbp_header; - -typedef struct { - u32 app_id : 8; - u32 item_id : 8; - u32 length : 8; - u32 rsvd : 8; -} __packed mbp_item_header; - -typedef struct { - u32 major_version : 16; - u32 minor_version : 16; - u32 hotfix_version : 16; - u32 build_version : 16; -} __packed mbp_fw_version_name; - -typedef struct { - u32 full_net : 1; - u32 std_net : 1; - u32 manageability : 1; - u32 reserved_2 : 2; - u32 intel_at : 1; - u32 intel_cls : 1; - u32 reserved : 3; - u32 intel_mpc : 1; - u32 icc_over_clocking : 1; - u32 pavp : 1; - u32 reserved_1 : 4; - u32 ipv6 : 1; - u32 kvm : 1; - u32 och : 1; - u32 vlan : 1; - u32 tls : 1; - u32 reserved_4 : 1; - u32 wlan : 1; - u32 reserved_5 : 8; -} __packed mbp_mefwcaps; - -typedef struct { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; -} __packed mbp_rom_bist_data; - -typedef struct { - u32 key[8]; -} mbp_platform_key; - -typedef struct { - u32 mobile: 1; - u32 desktop: 1; - u32 server: 1; - u32 workstation: 1; - u32 corporate: 1; - u32 consumer: 1; - u32 regular_super_sku: 1; - u32 rsvd: 1; - u32 image_type: 4; - u32 brand: 4; - u32 rsvd1: 16; -} __packed mbp_me_firmware_type; - -typedef struct { - mbp_me_firmware_type rule_data; - u8 available; -} mbp_plat_type; - -typedef struct { - u16 icc_start_address; - u16 mask; -} __packed icc_address_mask; - -typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 icc_reg_bundles; - icc_address_mask icc_address_mask[]; -} __packed mbp_icc_profile; - -typedef struct { - u16 lock_state : 1; - u16 authenticate_module : 1; - u16 s3authentication : 1; - u16 flash_wear_out : 1; - u16 flash_variable_security : 1; - u16 reserved : 11; -} __packed tdt_state_flag; - -typedef struct { - u8 state; - u8 last_theft_trigger; - tdt_state_flag flags; -} __packed mbp_at_state; - -typedef struct { - u32 wake_event_mrst_time_ms; - u32 mrst_pltrst_time_ms; - u32 pltrst_cpurst_time_ms; -} __packed mbp_plat_time; - -typedef struct { - u32 device_type : 2; - u32 reserved : 30; -} __packed mbp_nfc_data; - -typedef struct { - mbp_fw_version_name *fw_version_name; - mbp_mefwcaps *fw_capabilities; - mbp_rom_bist_data *rom_bist_data; - mbp_platform_key *platform_key; - mbp_plat_type *fw_plat_type; - mbp_icc_profile *icc_profile; - mbp_at_state *at_state; - u32 *mfsintegrity; - mbp_plat_time *plat_time; - mbp_nfc_data *nfc_data; -} me_bios_payload; - -struct me_fwcaps { - u32 id; - u8 length; - mbp_mefwcaps caps_sku; - u8 reserved[3]; -} __packed; - -void intel_me_hsio_version(uint16_t *version, uint16_t *checksum); - -/* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(void); - -#endif diff --git a/src/southbridge/intel/wildcatpoint/include/soc/pch.h b/src/southbridge/intel/wildcatpoint/include/soc/pch.h index 118dad02139..38763d189dc 100644 --- a/src/southbridge/intel/wildcatpoint/include/soc/pch.h +++ b/src/southbridge/intel/wildcatpoint/include/soc/pch.h @@ -32,6 +32,4 @@ bool pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); -void broadwell_pch_finalize(void); - #endif diff --git a/src/southbridge/intel/wildcatpoint/include/soc/spi.h b/src/southbridge/intel/wildcatpoint/include/soc/spi.h index 726b37ed81b..7a1ccf37178 100644 --- a/src/southbridge/intel/wildcatpoint/include/soc/spi.h +++ b/src/southbridge/intel/wildcatpoint/include/soc/spi.h @@ -3,21 +3,12 @@ #ifndef _BROADWELL_SPI_H_ #define _BROADWELL_SPI_H_ -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPIBAR_OFFSET 0x3800 -#define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) -#define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) - -/* Registers within the SPIBAR */ -#define SPIBAR_SSFC 0x91 -#define SPIBAR_FDOC 0xb0 -#define SPIBAR_FDOD 0xb4 - -#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ +/* Registers within SPIBAR */ +#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ +#define SPIBAR_SSFC 0x3891 +#define SPIBAR_FDOC 0x38b0 +#define SPIBAR_FDOD 0x38b4 + #endif diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index 9dd2350c93c..aeb8c66088b 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -37,15 +38,6 @@ static void pch_enable_ioapic(struct device *dev) register_new_ioapic_gsi0(IO_APIC_ADDR); } -#define ACPI_SCI_IRQ 9 - -void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) -{ - *gsi = ACPI_SCI_IRQ; - *irq = ACPI_SCI_IRQ; - *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; -} - static void enable_hpet(struct device *dev) { size_t i; @@ -199,7 +191,7 @@ static void pch_misc_init(struct device *dev) pci_or_config8(dev, GEN_PMCON_2, 1 << 7); /* Enable BIOS updates outside of SMM */ - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + pci_and_config8(dev, BIOS_CNTL, ~BIOS_CNTL_SMM_BWP); /* Clear status bits to prevent unexpected wake */ RCBA32_OR(0x3310, 0x2f); @@ -568,7 +560,7 @@ static void pch_lpc_add_io_resources(struct device *dev) /* GPIOBASE */ pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE, GPIO_BASE); + GPIO_BASE_SIZE, GPIOBASE); /* PMBASE */ pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c deleted file mode 100644 index 33bf915fae2..00000000000 --- a/src/southbridge/intel/wildcatpoint/me.c +++ /dev/null @@ -1,1055 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This is a ramstage driver for the Intel Management Engine found in the - * southbridge. It handles the required boot-time messages over the - * MMIO-based Management Engine Interface to tell the ME that the BIOS is - * finished with POST. Additional messages are defined for debug but are - * not used unless the console loglevel is high enough. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; - -/* MMIO base address for MEI interface */ -static u8 *mei_base_address; - -static void mei_dump(void *ptr, int dword, int offset, const char *type) -{ - struct mei_csr *csr; - - if (!CONFIG(DEBUG_INTEL_ME)) - return; - - printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); - - switch (offset) { - case MEI_H_CSR: - case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } - printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); - break; - case MEI_ME_CB_RW: - case MEI_H_CB_WW: - printk(BIOS_SPEW, "CB: 0x%08x\n", dword); - break; - default: - printk(BIOS_SPEW, "0x%08x\n", offset); - break; - } -} - -/* - * ME/MEI access helpers using memcpy to avoid aliasing. - */ - -static inline void mei_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = read32(mei_base_address + offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); -} - -static inline void mei_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); - mei_dump(ptr, dword, offset, "WRITE"); -} - -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); -} - -static inline void write_cb(u32 dword) -{ - write32(mei_base_address + MEI_H_CB_WW, dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); -} - -static inline u32 read_cb(void) -{ - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); - return dword; -} - -/* Wait for ME ready bit to be asserted */ -static int mei_wait_for_me_ready(void) -{ - struct mei_csr me; - unsigned int try = ME_RETRY; - - while (try--) { - read_me_csr(&me); - if (me.ready) - return 0; - udelay(ME_DELAY); - } - - printk(BIOS_ERR, "ME: failed to become ready\n"); - return -1; -} - -static void mei_reset(void) -{ - struct mei_csr host; - - if (mei_wait_for_me_ready() < 0) - return; - - /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); - host.reset = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - if (mei_wait_for_me_ready() < 0) - return; - - /* Re-init and indicate host is ready */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); -} - -static int mei_send_packet(struct mei_header *mei, void *req_data) -{ - struct mei_csr host; - unsigned int ndata, n; - u32 *data; - - /* Number of dwords to write */ - ndata = mei->length >> 2; - - /* Pad non-dword aligned request message length */ - if (mei->length & 3) - ndata++; - if (!ndata) { - printk(BIOS_DEBUG, "ME: request has no data\n"); - return -1; - } - ndata++; /* Add MEI header */ - - /* - * Make sure there is still room left in the circular buffer. - * Reset the buffer pointers if the requested message will not fit. - */ - read_host_csr(&host); - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); - mei_reset(); - read_host_csr(&host); - } - - /* Ensure the requested length will fit in the circular buffer. */ - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); - return -1; - } - - /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); - ndata--; - - /* Write message data */ - data = req_data; - for (n = 0; n < ndata; ++n) - write_cb(*data++); - - /* Generate interrupt to the ME */ - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); -} - -static int mei_send_data(u8 me_address, u8 host_address, - void *req_data, int req_bytes) -{ - struct mei_header header = { - .client_address = me_address, - .host_address = host_address, - }; - struct mei_csr host; - int current = 0; - u8 *req_ptr = req_data; - - while (!header.is_complete) { - int remain = req_bytes - current; - int buf_len; - - read_host_csr(&host); - buf_len = host.buffer_depth - host.buffer_write_ptr; - - if (buf_len > remain) { - /* Send all remaining data as final message */ - header.length = req_bytes - current; - header.is_complete = 1; - } else { - /* Send as much data as the buffer can hold */ - header.length = buf_len; - } - - mei_send_packet(&header, req_ptr); - - req_ptr += header.length; - current += header.length; - } - - return 0; -} - -static int mei_send_header(u8 me_address, u8 host_address, - void *header, int header_len, int complete) -{ - struct mei_header mei = { - .client_address = me_address, - .host_address = host_address, - .length = header_len, - .is_complete = complete, - }; - return mei_send_packet(&mei, header); -} - -static int mei_recv_msg(void *header, int header_bytes, - void *rsp_data, int rsp_bytes) -{ - struct mei_header mei_rsp; - struct mei_csr me, host; - unsigned int ndata, n; - unsigned int expected; - u32 *data; - - /* Total number of dwords to read from circular buffer */ - expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2; - if (rsp_bytes & 3) - expected++; - - if (mei_wait_for_me_ready() < 0) - return -1; - - /* - * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the - * expected number of dwords are present in the circular buffer. - */ - for (n = ME_RETRY; n; --n) { - read_me_csr(&me); - if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) - break; - udelay(ME_DELAY); - } - if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); - return -1; - } - - /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); - if (!mei_rsp.is_complete) { - printk(BIOS_ERR, "ME: response is not complete\n"); - return -1; - } - - /* Handle non-dword responses and expect at least the header */ - ndata = mei_rsp.length >> 2; - if (mei_rsp.length & 3) - ndata++; - if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); - return -1; - } - - /* Read response header from the ME */ - data = header; - for (n = 0; n < (header_bytes >> 2); ++n) - *data++ = read_cb(); - ndata -= header_bytes >> 2; - - /* Make sure caller passed a buffer with enough space */ - if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); - return -1; - } - - /* Read response data from the circular buffer */ - data = rsp_data; - for (n = 0; n < ndata; ++n) - *data++ = read_cb(); - - /* Tell the ME that we have consumed the response */ - read_host_csr(&host); - host.interrupt_status = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - return mei_wait_for_me_ready(); -} - -static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, - void *req_data, int req_bytes, - void *rsp_data, int rsp_bytes) -{ - struct mkhi_header mkhi_rsp; - - /* Send header */ - if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, - mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0) - return -1; - - /* Send data if available */ - if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, - req_data, req_bytes) < 0) - return -1; - - /* Return now if no response expected */ - if (!rsp_bytes) - return 0; - - /* Read header and data */ - if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), - rsp_data, rsp_bytes) < 0) - return -1; - - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || - mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); - return -1; - } - - return 0; -} - -static inline int mei_sendrecv_icc(struct icc_header *icc, - void *req_data, int req_bytes, - void *rsp_data, int rsp_bytes) -{ - struct icc_header icc_rsp; - - /* Send header */ - if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) - return -1; - - /* Send data if available */ - if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - req_data, req_bytes) < 0) - return -1; - - /* Read header and data, if needed */ - if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), - rsp_data, rsp_bytes) < 0) - return -1; - - return 0; -} - -/* - * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read - * state machine on the BIOS end doesn't match the ME's state machine. - */ -static void intel_me_mbp_give_up(struct device *dev) -{ - struct mei_csr csr; - - pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); - - read_host_csr(&csr); - csr.reset = 1; - csr.interrupt_generate = 1; - write_host_csr(&csr); -} - -/* - * mbp clear routine. This will wait for the ME to indicate that - * the MBP has been read and cleared. - */ -static void intel_me_mbp_clear(struct device *dev) -{ - int count; - struct me_hfs2 hfs2; - - /* Wait for the mbp_cleared indicator */ - for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - if (hfs2.mbp_cleared) - break; - udelay(ME_DELAY); - } - - if (count == 0) { - printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); - intel_me_mbp_give_up(dev); - } else { - printk(BIOS_INFO, "ME: MBP cleared\n"); - } -} - -static void me_print_fw_version(mbp_fw_version_name *vers_name) -{ - if (!vers_name) { - printk(BIOS_ERR, "ME: mbp missing version report\n"); - return; - } - - printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", - vers_name->major_version, vers_name->minor_version, - vers_name->hotfix_version, vers_name->build_version); -} - -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); -} - -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mbp_mefwcaps *cap) -{ - u32 rule_id = 0; - struct me_fwcaps cap_msg; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - - /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), - &cap_msg, sizeof(cap_msg)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - *cap = cap_msg.caps_sku; - return 0; -} - -/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) -{ - mbp_mefwcaps local_caps; - if (!cap) { - cap = &local_caps; - printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); - if (mkhi_get_fwcaps(cap)) - return; - } - - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); -} - -/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - u32 eop_ack; - - /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - -/* Send END OF POST message to the ME */ -static int mkhi_end_of_post_noack(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST_NOACK, - }; - - /* Send request, do not wait for response */ - if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) { - printk(BIOS_ERR, "ME: END OF POST NOACK message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST NOACK message successful\n"); - return 0; -} - -/* Send HMRFPO LOCK message to the ME */ -static int mkhi_hmrfpo_lock(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_HMRFPO, - .command = MKHI_HMRFPO_LOCK, - }; - u32 ack; - - /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &ack, sizeof(ack)) < 0) { - printk(BIOS_ERR, "ME: HMRFPO LOCK message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: HMRFPO LOCK message successful (%d)\n", ack); - return 0; -} - -/* Send HMRFPO LOCK message to the ME, do not wait for response */ -static int mkhi_hmrfpo_lock_noack(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_HMRFPO, - .command = MKHI_HMRFPO_LOCK_NOACK, - }; - - /* Send request, do not wait for response */ - if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) { - printk(BIOS_ERR, "ME: HMRFPO LOCK NOACK message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: HMRFPO LOCK NOACK message successful\n"); - return 0; -} - -static void intel_me_finalize(struct device *dev) -{ - u16 reg16; - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) - return; - - if (!get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI))) - return; - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); - RCBA32(FD2); -} - -static int me_icc_set_clock_enables(u32 mask) -{ - struct icc_clock_enables_msg clk = { - .clock_enables = 0, /* Turn off specified clocks */ - .clock_mask = mask, - .no_response = 1, /* Do not expect response */ - }; - struct icc_header icc = { - .api_version = ICC_API_VERSION_LYNXPOINT, - .icc_command = ICC_SET_CLOCK_ENABLES, - .length = sizeof(clk), - }; - - /* Send request and wait for response */ - if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { - printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); - return -1; - } - printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); - return 0; -} - -/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(struct device *dev) -{ - me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_hfs2 hfs2; - - /* Check and dump status */ - intel_me_status(); - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - - /* Check Current Working State */ - switch (hfs.working_state) { - case ME_HFS_CWS_NORMAL: - path = ME_NORMAL_BIOS_PATH; - break; - case ME_HFS_CWS_REC: - path = ME_RECOVERY_BIOS_PATH; - break; - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check Current Operation Mode */ - switch (hfs.operation_mode) { - case ME_HFS_MODE_NORMAL: - break; - case ME_HFS_MODE_DEBUG: - case ME_HFS_MODE_DIS: - case ME_HFS_MODE_OVER_JMPR: - case ME_HFS_MODE_OVER_MEI: - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check for any error code and valid firmware and MBP */ - if (hfs.error_code || hfs.fpt_bad) - path = ME_ERROR_BIOS_PATH; - - /* Check if the MBP is ready */ - if (!hfs2.mbp_rdy) { - printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __func__); - path = ME_ERROR_BIOS_PATH; - } - - if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { - struct elog_event_data_me_extended data = { - .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = hfs2.progress_code, - .current_pmevent = hfs2.current_pmevent, - .current_state = hfs2.current_state, - }; - elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); - } - - return path; -} - -/* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) -{ - struct resource *res; - struct mei_csr host; - - /* Find the MMIO base for the ME interface */ - res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res || res->base == 0 || res->size == 0) { - printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); - return -1; - } - mei_base_address = res2mmio(res, 0, 0); - - /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - /* Clean up status for next message */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); - - return 0; -} - -/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) -{ - struct me_heres status; - u32 extend[8] = {0}; - int i, count = 0; - - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); - if (!status.extend_feature_present) { - printk(BIOS_ERR, "ME: Extend Feature not present\n"); - return -1; - } - - if (!status.extend_reg_valid) { - printk(BIOS_ERR, "ME: Extend Register not valid\n"); - return -1; - } - - switch (status.extend_reg_algorithm) { - case PCI_ME_EXT_SHA1: - count = 5; - printk(BIOS_DEBUG, "ME: Extend SHA-1: "); - break; - case PCI_ME_EXT_SHA256: - count = 8; - printk(BIOS_DEBUG, "ME: Extend SHA-256: "); - break; - default: - printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); - return -1; - } - - for (i = 0; i < count; ++i) { - extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend[i]); - } - printk(BIOS_DEBUG, "\n"); - - /* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS_NVS)) - chromeos_set_me_hash(extend, count); - - return 0; -} - -static void intel_me_print_mbp(me_bios_payload *mbp_data) -{ - me_print_fw_version(mbp_data->fw_version_name); - - if (CONFIG(DEBUG_INTEL_ME)) - me_print_fwcaps(mbp_data->fw_capabilities); - - if (mbp_data->plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data->plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data->plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data->plat_time->pltrst_cpurst_time_ms); - } -} - -static u32 me_to_host_words_pending(void) -{ - struct mei_csr me; - read_me_csr(&me); - if (!me.ready) - return 0; - return (me.buffer_write_ptr - me.buffer_read_ptr) & - (me.buffer_depth - 1); -} - -struct mbp_payload { - mbp_header header; - u32 data[]; -}; - -/* - * Read and print ME MBP data - * - * Return -1 to indicate a problem (give up) - * Return 0 to indicate success (send LOCK+EOP) - * Return 1 to indicate success (send LOCK+EOP with NOACK) - */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) -{ - mbp_header mbp_hdr; - u32 me2host_pending; - struct mei_csr host; - struct me_hfs2 hfs2; - struct mbp_payload *mbp; - int i; - int ret = 0; - - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - - if (!hfs2.mbp_rdy) { - printk(BIOS_ERR, "ME: MBP not ready\n"); - intel_me_mbp_give_up(dev); - return -1; - } - - me2host_pending = me_to_host_words_pending(); - if (!me2host_pending) { - printk(BIOS_ERR, "ME: no mbp data!\n"); - intel_me_mbp_give_up(dev); - return -1; - } - - /* we know for sure that at least the header is there */ - mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); - - if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || - (me2host_pending < mbp_hdr.mbp_size)) { - printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" - " buffer contains %d words\n", - mbp_hdr.num_entries, mbp_hdr.mbp_size, - me2host_pending); - intel_me_mbp_give_up(dev); - return -1; - } - mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); - if (!mbp) { - intel_me_mbp_give_up(dev); - return -1; - } - - mbp->header = mbp_hdr; - me2host_pending--; - - i = 0; - while (i != me2host_pending) { - mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); - i++; - } - - read_host_csr(&host); - - /* Check that read and write pointers are equal. */ - if (host.buffer_read_ptr != host.buffer_write_ptr) { - printk(BIOS_INFO, "ME: MBP Read/Write pointer mismatch\n"); - printk(BIOS_INFO, "ME: MBP Waiting for MBP cleared flag\n"); - - /* Tell ME that the host has finished reading the MBP. */ - host.interrupt_generate = 1; - host.reset = 0; - write_host_csr(&host); - - /* Wait for the mbp_cleared indicator. */ - intel_me_mbp_clear(dev); - } else { - /* Indicate NOACK messages should be used. */ - ret = 1; - } - - /* Dump out the MBP contents. */ - if (CONFIG(DEBUG_INTEL_ME)) { - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); - for (i = 0; i < mbp->header.mbp_size - 1; i++) - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); - } - -#define ASSIGN_FIELD_PTR(field_, val_) \ - { \ - mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ - break; \ - } - - /* Setup the pointers in the me_bios_payload structure. */ - for (i = 0; i < mbp->header.mbp_size - 1;) { - mbp_item_header *item = (void *)&mbp->data[i]; - - switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { - case MBP_IDENT(KERNEL, FW_VER): - ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); - - case MBP_IDENT(ICC, PROFILE): - ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); - - case MBP_IDENT(INTEL_AT, STATE): - ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, FW_CAP): - ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, ROM_BIST): - ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, PLAT_KEY): - ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, FW_TYPE): - ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, MFS_FAILURE): - ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); - - case MBP_IDENT(KERNEL, PLAT_TIME): - ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); - - case MBP_IDENT(NFC, SUPPORT_DATA): - ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); - } - i += item->length; - } - #undef ASSIGN_FIELD_PTR - - free(mbp); - return ret; -} - -/* Check whether ME is present and do basic init */ -static void intel_me_init(struct device *dev) -{ - const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); - me_bios_path path = intel_me_path(dev); - me_bios_payload mbp_data; - int mbp_ret; - struct me_hfs hfs; - struct mei_csr csr; - - /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); - - if (path == ME_NORMAL_BIOS_PATH) { - /* Validate the extend register */ - intel_me_extend_valid(dev); -} - - memset(&mbp_data, 0, sizeof(mbp_data)); - - /* - * According to the ME9 BWG, BIOS is required to fetch MBP data in - * all boot flows except S3 Resume. - */ - - /* Prepare MEI MMIO interface */ - if (intel_mei_setup(dev) < 0) - return; - - /* Read ME MBP data */ - mbp_ret = intel_me_read_mbp(&mbp_data, dev); - if (mbp_ret < 0) - return; - intel_me_print_mbp(&mbp_data); - - /* Set clock enables according to devicetree */ - if (config->icc_clock_disable) - me_icc_set_clock_enables(config->icc_clock_disable); - - /* Make sure ME is in a mode that expects EOP */ - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - if (mbp_ret) { - /* - * MBP Cleared wait is skipped, - * Do not expect ACK and reset when complete. - */ - - /* Send HMRFPO Lock command, no response */ - mkhi_hmrfpo_lock_noack(); - - /* Send END OF POST command, no response */ - mkhi_end_of_post_noack(); - - /* Assert reset and interrupt */ - read_host_csr(&csr); - csr.interrupt_generate = 1; - csr.reset = 1; - write_host_csr(&csr); - } else { - /* - * MBP Cleared wait was not skipped - */ - - /* Send HMRFPO LOCK command */ - mkhi_hmrfpo_lock(); - - /* Send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - } -} - -static void intel_me_enable(struct device *dev) -{ - /* Avoid talking to the device in S3 path */ - if (acpi_is_wakeup_s3() && get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI))) { - dev->enabled = 0; - pch_disable_devfn(dev); - } -} - -static struct device_operations device_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .enable = &intel_me_enable, - .init = &intel_me_init, - .final = &intel_me_finalize, - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - 0x9c3a, /* Low Power */ - 0x9cba, /* WildcatPoint */ - 0 -}; - -static const struct pci_driver intel_me __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c deleted file mode 100644 index ef6a0f3473d..00000000000 --- a/src/southbridge/intel/wildcatpoint/me_status.c +++ /dev/null @@ -1,325 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -#define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \ - (((__index__) < ARRAY_SIZE((__array__))) ? \ - (__array__)[(__index__)] : \ - (__default__)) - -static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -/* HFS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [3] = "Unknown (3)", - [4] = "Unknown (4)", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", - [9] = "Unknown (9)", - [10] = "Unknown (10)", - [11] = "Unknown (11)", - [12] = "Unknown (12)", - [13] = "Unknown (13)", - [14] = "Unknown (14)", - [15] = "Unknown (15)", -}; - -/* HFS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFS[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFS[15:12] Error Code Values */ -static const char *me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* HFS2[31:28] ME Progress Code */ -static const char *me_progress_values[] = { - [ME_HFS2_PHASE_ROM] = "ROM Phase", - [ME_HFS2_PHASE_BUP] = "BUP Phase", - [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", - [ME_HFS2_PHASE_POLICY] = "Policy Module", - [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", - [ME_HFS2_PHASE_UNKNOWN] = "Unknown", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" -}; - -/* HFS2[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_S0MO_SXM3] = - "S0/M0->Sx/M3", - [ME_HFS2_PMEVENT_SXM3_S0M0] = - "Sx/M3->S0/M0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_SXMX_SXMOFF] = - "Sx/Mx->Sx/Moff" -}; - -/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", - [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", -}; - -/* Progress Code 3 states */ -static const char *me_progress_policy_values[] = { - [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", - [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", - [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", - [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", - [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", - [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", - [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", - [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", - [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", - [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", - [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = - "VSCC Data not found for flash device", - [ME_HFS2_STATE_POLICY_VSCC_INVALID] = - "VSCC Table is not valid", - [ME_HFS2_STATE_POLICY_FPB_ERR] = - "Flash Partition Boundary is outside address space", - [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = - "ME cannot access the chipset descriptor region", - [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = - "Required VSCC values for flash parts do not match", -}; - -void intel_me_status(void) -{ - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) - return; - - struct me_hfs _hfs, *hfs = &_hfs; - struct me_hfs2 _hfs2, *hfs2 = &_hfs2; - - me_read_dword_ptr(hfs, PCI_ME_HFS); - me_read_dword_ptr(hfs2, PCI_ME_HFS2); - - /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - ARRAY_TO_ELEMENT(me_cws_values, - hfs->working_state, - "Unknown (OOB)")); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - ARRAY_TO_ELEMENT(me_opstate_values, - hfs->operation_state, - "Unknown (OOB)")); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - ARRAY_TO_ELEMENT(me_opmode_values, - hfs->operation_mode, - "Unknown (OOB)")); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - ARRAY_TO_ELEMENT(me_error_values, - hfs->error_code, - "Unknown (OOB)")); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - ARRAY_TO_ELEMENT(me_progress_values, - hfs2->progress_code, - "Unknown (OOB)")); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - ARRAY_TO_ELEMENT(me_pmevent_values, - hfs2->current_pmevent, - "Unknown (OOB)")); - - printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { - case ME_HFS2_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - ARRAY_TO_ELEMENT(me_progress_rom_values, - hfs2->current_state, - "Unknown (OOB)")); - break; - - case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (ARRAY_TO_ELEMENT(me_progress_bup_values, - hfs2->current_state, NULL)) - printk(BIOS_DEBUG, "%s", - ARRAY_TO_ELEMENT(me_progress_bup_values, - hfs2->current_state, - NULL)); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ - if (ARRAY_TO_ELEMENT(me_progress_policy_values, - hfs2->current_state, NULL)) - printk(BIOS_DEBUG, "%s", - ARRAY_TO_ELEMENT(me_progress_policy_values, - hfs2->current_state, - NULL)); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) - printk(BIOS_DEBUG, "Host communication established"); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); - } - printk(BIOS_DEBUG, "\n"); -} - -void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) -{ - int count; - u32 hsiover; - struct me_hfs hfs; - - /* Query for HSIO version, overloads H_GS and HFS */ - pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, - ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); - - /* Must wait for ME acknowledgement */ - for (count = ME_RETRY; count > 0; --count) { - me_read_dword_ptr(&hfs, PCI_ME_HFS); - if (hfs.bios_msg_ack) - break; - udelay(ME_DELAY); - } - if (!count) { - printk(BIOS_ERR, "ME failed to respond\n"); - return; - } - - /* HSIO version should be in HFS_5 */ - hsiover = pci_read_config32(PCH_DEV_ME, PCI_ME_HFS5); - *version = hsiover >> 16; - *checksum = hsiover & 0xffff; - - printk(BIOS_DEBUG, "ME: HSIO Version : %d (CRC 0x%04x)\n", - *version, *checksum); - - /* Reset registers to normal behavior */ - pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, - ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); -} diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index 3714a7d8a71..90e6192f1c1 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -47,15 +47,15 @@ u32 pch_read_soft_strap(int id) { u32 fdoc; - fdoc = SPIBAR32(SPIBAR_FDOC); + fdoc = RCBA32(SPIBAR_FDOC); fdoc &= ~0x00007ffc; - SPIBAR32(SPIBAR_FDOC) = fdoc; + RCBA32(SPIBAR_FDOC) = fdoc; fdoc |= 0x00004000; fdoc |= id * 4; - SPIBAR32(SPIBAR_FDOC) = fdoc; + RCBA32(SPIBAR_FDOC) = fdoc; - return SPIBAR32(SPIBAR_FDOD); + return RCBA32(SPIBAR_FDOD); } #ifndef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c deleted file mode 100644 index 37d24ef2ee8..00000000000 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ /dev/null @@ -1,644 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Low Power variant has 6 root ports. */ -#define MAX_NUM_ROOT_PORTS 6 - -struct root_port_config { - /* RPFN is a write-once register so keep a copy until it is written */ - u32 orig_rpfn; - u32 new_rpfn; - u32 pin_ownership; - u32 strpfusecfg1; - u32 strpfusecfg2; - u32 strpfusecfg3; - u32 b0d28f0_32c; - u32 b0d28f4_32c; - u32 b0d28f5_32c; - bool coalesce; - int gbe_port; - int num_ports; - struct device *ports[MAX_NUM_ROOT_PORTS]; -}; - -static struct root_port_config rpc; - -static inline int root_port_is_first(struct device *dev) -{ - return PCI_FUNC(dev->path.pci.devfn) == 0; -} - -static inline int root_port_is_last(struct device *dev) -{ - return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); -} - -/* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(struct device *dev) -{ - return PCI_FUNC(dev->path.pci.devfn) + 1; -} - -static void root_port_config_update_gbe_port(void) -{ - /* Is the Gbe Port enabled? */ - if (!((rpc.strpfusecfg1 >> 19) & 1)) - return; - - switch ((rpc.strpfusecfg1 >> 16) & 0x7) { - case 0: - rpc.gbe_port = 3; - break; - case 1: - rpc.gbe_port = 4; - break; - case 2: - case 3: - case 4: - case 5: - /* Lanes 0-4 of Root Port 5. */ - rpc.gbe_port = 5; - break; - default: - printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n"); - } -} - -static void pcie_iosf_port_grant_count(struct device *dev) -{ - u8 update_val; - u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3; - - switch (rpcd) { - case 1: - case 3: - update_val = 0x02; - break; - case 2: - update_val = 0x22; - break; - default: - update_val = 0x00; - break; - } - - RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val; -} - -static void root_port_init_config(struct device *dev) -{ - int rp; - u32 data = 0; - u8 resp, id; - - if (root_port_is_first(dev)) { - rpc.orig_rpfn = RCBA32(RPFN); - rpc.new_rpfn = rpc.orig_rpfn; - rpc.num_ports = MAX_NUM_ROOT_PORTS; - rpc.gbe_port = -1; - /* RP0 f5[3:0] = 0101b*/ - pci_update_config8(dev, 0xf5, ~0xa, 0x5); - - pcie_iosf_port_grant_count(dev); - - rpc.pin_ownership = pci_read_config32(dev, 0x410); - root_port_config_update_gbe_port(); - - const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); - rpc.coalesce = config->pcie_port_coalesce; - } - - rp = root_port_number(dev); - if (rp > rpc.num_ports) { - printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", - rp, rpc.num_ports); - return; - } - - /* Read the fuse configuration and pin ownership. */ - switch (rp) { - case 1: - rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc); - rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c); - break; - case 5: - rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc); - rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c); - break; - case 6: - rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c); - rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc); - break; - default: - break; - } - - pci_write_config32(dev, 0x418, 0x02000430); - - if (root_port_is_first(dev)) { - /* - * set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1 - * before configuring ASPM - */ - id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07); - pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp); - data |= ((0x30 << 16) | (0x40 << 8)); - pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp); - } - - /* Cache pci device. */ - rpc.ports[rp - 1] = dev; -} - -/* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_device_set_func(int index, int pci_func) -{ - struct device *dev; - unsigned int new_devfn; - - dev = rpc.ports[index]; - - /* Set the new PCI function field for this Root Port. */ - rpc.new_rpfn &= ~RPFN_FNMASK(index); - rpc.new_rpfn |= RPFN_FNSET(index, pci_func); - - /* Determine the new devfn for this port */ - new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func); - - if (dev && dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); - - dev->path.pci.devfn = new_devfn; - } -} - -static void pcie_enable_clock_gating(void) -{ - int i; - int enabled_ports = 0; - int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); - - for (i = 0; i < rpc.num_ports; i++) { - struct device *dev; - int rp; - - dev = rpc.ports[i]; - if (!dev) - continue; - - rp = root_port_number(dev); - - if (!dev->enabled) { - /* Configure shared resource clock gating. */ - if (rp == 1 || rp == 5 || rp == 6) - pci_or_config8(dev, 0xe1, 0x3c); - - pci_or_config8(dev, 0xe2, 3 << 4); - pci_or_config32(dev, 0x420, 1 << 31); - - /* Per-Port CLKREQ# handling. */ - if (gpio_is_native(18 + rp - 1)) - pci_or_config32(dev, 0x420, 3 << 29); - - /* Enable static clock gating. */ - if (rp == 1 && !rpc.ports[1]->enabled && - !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pci_or_config8(dev, 0xe2, 1); - pci_or_config8(dev, 0xe1, 1 << 7); - } else if (rp == 5 || rp == 6) { - pci_or_config8(dev, 0xe2, 1); - pci_or_config8(dev, 0xe1, 1 << 7); - } - continue; - } - - enabled_ports++; - - /* Enable dynamic clock gating. */ - pci_or_config8(dev, 0xe1, 0x03); - pci_or_config8(dev, 0xe2, 1 << 6); - pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); - - /* Update PECR1 register. */ - pci_or_config8(dev, 0xe8, 3); - - if (is_broadwell) { - pci_or_config32(dev, 0x324, (1 << 5) | (1 << 14)); - } else { - pci_or_config32(dev, 0x324, 1 << 5); - } - /* Per-Port CLKREQ# handling. */ - if (gpio_is_native(18 + rp - 1)) - /* - * In addition to D28Fx PCICFG 420h[30:29] = 11b, - * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. - */ - pci_update_config32(dev, 0x420, ~(1 << 17), (3 << 29) | 1); - - /* Configure shared resource clock gating. */ - if (rp == 1 || rp == 5 || rp == 6) - pci_or_config8(dev, 0xe1, 0x3c); - - /* CLKREQ# VR Idle Enable */ - RCBA32_OR(0x2b1c, (1 << (16 + i))); - } - - if (!enabled_ports) - pci_or_config8(rpc.ports[0], 0xe1, 1 << 6); -} - -static void root_port_commit_config(void) -{ - int i; - - /* If the first root port is disabled the coalesce ports. */ - if (!rpc.ports[0]->enabled) - rpc.coalesce = true; - - /* Perform clock gating configuration. */ - pcie_enable_clock_gating(); - - for (i = 0; i < rpc.num_ports; i++) { - struct device *dev; - u32 reg32; - int n = 0; - - dev = rpc.ports[i]; - - if (dev == NULL) { - printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1); - continue; - } - - if (dev->enabled) - continue; - - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* 8.2 Configuration of PCI Express Root Ports */ - pci_or_config32(dev, 0x338, 1 << 26); - - do { - reg32 = pci_read_config32(dev, 0x328); - n++; - if (((reg32 & 0xff000000) == 0x01000000) || (n > 50)) - break; - udelay(100); - } while (1); - - if (n > 50) - printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n", - dev_path(dev)); - - pci_or_config32(dev, 0x408, 1 << 27); - - /* Disable this device if possible */ - pch_disable_devfn(dev); - } - - if (rpc.coalesce) { - int current_func; - - /* For all Root Ports N enabled ports get assigned the lower - * PCI function number. The disabled ones get upper PCI - * function numbers. */ - current_func = 0; - for (i = 0; i < rpc.num_ports; i++) { - if (!rpc.ports[i]->enabled) - continue; - pch_pcie_device_set_func(i, current_func); - current_func++; - } - - /* Allocate the disabled devices' PCI function number. */ - for (i = 0; i < rpc.num_ports; i++) { - if (rpc.ports[i]->enabled) - continue; - pch_pcie_device_set_func(i, current_func); - current_func++; - } - } - - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); - RCBA32(RPFN) = rpc.new_rpfn; -} - -static void root_port_mark_disable(struct device *dev) -{ - /* Mark device as disabled. */ - dev->enabled = 0; - /* Mark device to be hidden. */ - rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); -} - -static void root_port_check_disable(struct device *dev) -{ - int rp; - - /* Device already disabled. */ - if (!dev->enabled) { - root_port_mark_disable(dev); - return; - } - - rp = root_port_number(dev); - - /* Is the GbE port mapped to this Root Port? */ - if (rp == rpc.gbe_port) { - root_port_mark_disable(dev); - return; - } - - /* Check Root Port Configuration. */ - switch (rp) { - case 2: - /* Root Port 2 is disabled for all lane configurations - * but config 00b (4x1 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 3: - /* Root Port 3 is disabled in config 11b (1x4 links). */ - if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 4: - /* Root Port 4 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x2) { - root_port_mark_disable(dev); - return; - } - break; - } - - /* Check Pin Ownership. */ - switch (rp) { - case 1: - /* Bit 0 is Root Port 1 ownership. */ - if ((rpc.pin_ownership & 0x1) == 0) { - root_port_mark_disable(dev); - return; - } - break; - case 2: - /* Bit 2 is Root Port 2 ownership. */ - if ((rpc.pin_ownership & 0x4) == 0) { - root_port_mark_disable(dev); - return; - } - break; - case 6: - /* Bits 7:4 are Root Port 6 pin-lane ownership. */ - if ((rpc.pin_ownership & 0xf0) == 0) { - root_port_mark_disable(dev); - return; - } - break; - } -} - -static void pcie_add_0x0202000_iobp(u32 reg) -{ - u32 reg32; - - reg32 = pch_iobp_read(reg); - reg32 += (0x2 << 16) | (0x2 << 8); - pch_iobp_write(reg, reg32); -} - -static void pch_pcie_early(struct device *dev) -{ - const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); - int do_aspm = 0; - int rp = root_port_number(dev); - - switch (rp) { - case 1: - case 2: - case 3: - case 4: - /* - * Bits 31:28 of b0d28f0 0x32c register correspond to - * Root Ports 4:1. - */ - do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); - break; - case 5: - /* - * Bit 28 of b0d28f4 0x32c register corresponds to - * Root Port 5. - */ - do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); - break; - case 6: - /* - * Bit 29 of b0d28f5 0x32c register corresponds to - * Root Port 6. - */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); - break; - } - - /* Allow ASPM to be forced on in devicetree */ - if ((config->pcie_port_force_aspm & (1 << (rp - 1)))) - do_aspm = 1; - - printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", - rp, do_aspm ? "en" : "dis"); - - if (do_aspm) { - /* Set ASPM bits in MPC2 register. */ - pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); - - /* Set unique clock exit latency in MPC register. */ - pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); - - switch (rp) { - case 1: - pcie_add_0x0202000_iobp(0xe9002440); - break; - case 2: - pcie_add_0x0202000_iobp(0xe9002640); - break; - case 3: - pcie_add_0x0202000_iobp(0xe9000840); - break; - case 4: - pcie_add_0x0202000_iobp(0xe9000a40); - break; - case 5: - pcie_add_0x0202000_iobp(0xe9000c40); - pcie_add_0x0202000_iobp(0xe9000e40); - pcie_add_0x0202000_iobp(0xe9001040); - pcie_add_0x0202000_iobp(0xe9001240); - break; - case 6: - /* Update IOBP based on lane ownership. */ - if (rpc.pin_ownership & (1 << 4)) - pcie_add_0x0202000_iobp(0xea002040); - if (rpc.pin_ownership & (1 << 5)) - pcie_add_0x0202000_iobp(0xea002240); - if (rpc.pin_ownership & (1 << 6)) - pcie_add_0x0202000_iobp(0xea002440); - if (rpc.pin_ownership & (1 << 7)) - pcie_add_0x0202000_iobp(0xea002640); - break; - } - - pci_update_config32(dev, 0x338, ~(1 << 26), 0); - } - - /* Enable LTR in Root Port. Disable OBFF. */ - pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11)); - pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10); - - pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); - - /* Set L1 exit latency in LCAP register. */ - if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) - pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); - else - pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - - pci_update_config32(dev, 0x314, 0, 0x743a361b); - - /* Set Common Clock Exit Latency in MPC register. */ - pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - - pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); - - /* Set Invalid Receive Range Check Enable in MPC register. */ - pci_or_config32(dev, 0xd8, 1 << 25); - - pci_and_config8(dev, 0xf5, 0x0f); - - if (rp == 1 || rp == 5 || rp == 6) - pci_and_config8(dev, 0xf7, ~0x0c); - - /* Set EOI forwarding disable. */ - pci_or_config32(dev, 0xd4, 1 << 1); - - /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - if (CONFIG(PCIEXP_AER)) - pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); - else - pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); - - /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - if (CONFIG(PCIEXP_L1_SUB_STATE)) - pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); - else - pci_update_config32(dev, 0x200, ~0xfffff, 0); - - pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); - - /* Enable Relaxed Order from Root Port. */ - pci_or_config32(dev, 0x320, 3 << 23); - - /* Read and write back write-once capability registers. */ - pci_update_config32(dev, 0x34, ~0, 0); - pci_update_config32(dev, 0x40, ~0, 0); - pci_update_config32(dev, 0x80, ~0, 0); - pci_update_config32(dev, 0x90, ~0, 0); -} - -static void pch_pcie_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); - - /* Enable SERR */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); - - /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* Set Cache Line Size to 0x10 */ - pci_write_config8(dev, 0x0c, 0x10); - - pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); - - /* Clear errors in status registers */ - pci_update_config16(dev, 0x06, ~0, 0); - pci_update_config16(dev, 0x1e, ~0, 0); -} - -static void pch_pcie_enable(struct device *dev) -{ - /* Add this device to the root port config structure. */ - root_port_init_config(dev); - - /* Check to see if this Root Port should be disabled. */ - root_port_check_disable(dev); - - /* Power Management init before enumeration */ - if (dev->enabled) - pch_pcie_early(dev); - - /* - * When processing the last PCIe root port we can now - * update the Root Port Function Number and Hide register. - */ - if (root_port_is_last(dev)) - root_port_commit_config(); -} - -static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop) -{ - *max_snoop = PCIE_LTR_MAX_SNOOP_LATENCY_3146US; - *max_nosnoop = PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US; -} - -static struct pci_operations pcie_ops = { - .set_subsystem = pci_dev_set_subsystem, - .get_ltr_max_latencies = pcie_get_ltr_max_latencies, -}; - -static struct device_operations device_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pch_pcie_init, - .enable = pch_pcie_enable, - .scan_bus = pciexp_scan_bridge, - .ops_pci = &pcie_ops, -}; - -static const unsigned short pcie_device_ids[] = { - /* Lynxpoint-LP */ - 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, - /* WildcatPoint */ - 0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448, - 0 -}; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pcie_device_ids, -}; diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c deleted file mode 100644 index 8fc16700378..00000000000 --- a/src/southbridge/intel/wildcatpoint/pmutil.c +++ /dev/null @@ -1,439 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Helper functions for dealing with power management registers - * and the differences between PCH variants. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GPIO_ALT_GPI_SMI_STS 0x50 -#define GPIO_ALT_GPI_SMI_EN 0x54 - -static inline uint16_t get_gpiobase(void) -{ - return GPIO_BASE_ADDRESS; -} - -/* Print status bits with descriptive names */ -static void print_status_bits(u32 status, const char *bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = 31; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -/* Print status bits as GPIO numbers */ -static void print_gpio_status(u32 status, int start) -{ - int i; - - if (!status) - return; - - for (i = 31; i >= 0; i--) { - if (status & (1 << i)) - printk(BIOS_DEBUG, "GPIO%d ", start + i); - } -} - -/* - * PM1_CNT - */ - -/* Enable events in PM1 control register */ -void enable_pm1_control(u32 mask) -{ - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); -} - -/* Disable events in PM1 control register */ -void disable_pm1_control(u32 mask) -{ - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); -} - -/* - * PM1 - */ - -/* Clear and return PM1 status register */ -static u16 reset_pm1_status(void) -{ - u16 pm1_sts = inw(get_pmbase() + PM1_STS); - outw(pm1_sts, get_pmbase() + PM1_STS); - return pm1_sts; -} - -/* Print PM1 status bits */ -static u16 print_pm1_status(u16 pm1_sts) -{ - const char *pm1_sts_bits[] = { - [0] = "TMROF", - [4] = "BM", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [11] = "PRBTNOR", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -/* Print, clear, and return PM1 status */ -u16 clear_pm1_status(void) -{ - return print_pm1_status(reset_pm1_status()); -} - -/* Set the PM1 register to events */ -void enable_pm1(u16 events) -{ - outw(events, get_pmbase() + PM1_EN); -} - -/* - * SMI - */ - -/* Clear and return SMI status register */ -static u32 reset_smi_status(void) -{ - u32 smi_sts = inl(get_pmbase() + SMI_STS); - outl(smi_sts, get_pmbase() + SMI_STS); - return smi_sts; -} - -/* Print SMI status bits */ -static u32 print_smi_status(u32 smi_sts) -{ - const char *smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY_USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", - [10] = "GPI", - [11] = "MCSMI", - [12] = "DEVMON", - [13] = "TCO", - [14] = "PERIODIC", - [15] = "SERIRQ_SMI", - [16] = "SMBUS_SMI", - [17] = "LEGACY_USB2", - [18] = "INTEL_USB2", - [20] = "PCI_EXP_SMI", - [21] = "MONITOR", - [26] = "SPI", - [27] = "GPIO_UNLOCK" - }; - - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; -} - -/* Print, clear, and return SMI status */ -u32 clear_smi_status(void) -{ - return print_smi_status(reset_smi_status()); -} - -/* Enable SMI event */ -void enable_smi(u32 mask) -{ - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en |= mask; - outl(smi_en, get_pmbase() + SMI_EN); -} - -/* Disable SMI event */ -void disable_smi(u32 mask) -{ - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en &= ~mask; - outl(smi_en, get_pmbase() + SMI_EN); -} - -/* - * ALT_GP_SMI - */ - -/* Clear GPIO SMI status and return events that are enabled and active */ -static u32 reset_alt_smi_status(void) -{ - u32 alt_sts, alt_en; - - /* Low Power variant moves this to GPIO region as dword */ - alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); - - /* Only report enabled events */ - return alt_sts & alt_en; -} - -/* Print GPIO SMI status bits */ -static u32 print_alt_smi_status(u32 alt_sts) -{ - if (!alt_sts) - return 0; - - printk(BIOS_DEBUG, "ALT_STS: "); - - /* First 16 events are GPIO 32-47 */ - print_gpio_status(alt_sts & 0xffff, 32); - - printk(BIOS_DEBUG, "\n"); - - return alt_sts; -} - -/* Print, clear, and return GPIO SMI status */ -u32 clear_alt_smi_status(void) -{ - return print_alt_smi_status(reset_alt_smi_status()); -} - -/* Enable GPIO SMI events */ -void enable_alt_smi(u32 mask) -{ - u32 alt_en; - - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); - alt_en |= mask; - outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); -} - -/* - * TCO - */ - -/* Clear TCO status and return events that are enabled and active */ -static u32 reset_tco_status(void) -{ - u32 tcobase = get_pmbase() + 0x60; - u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(get_pmbase() + 0x68); - - /* Don't clear BOOT_STS before SECOND_TO_STS */ - outl(tco_sts & ~(1 << 18), tcobase + 0x04); - - /* Clear BOOT_STS */ - if (tco_sts & (1 << 18)) - outl(tco_sts & (1 << 18), tcobase + 0x04); - - return tco_sts & tco_en; -} - -/* Print TCO status bits */ -static u32 print_tco_status(u32 tco_sts) -{ - const char *tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", - [10] = "DMISMI", - [12] = "DMISERR", - [13] = "SLVSEL", - [16] = "INTRD_DET", - [17] = "SECOND_TO", - [18] = "BOOT", - [20] = "SMLINK_SLV" - }; - - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; -} - -/* Print, clear, and return TCO status */ -u32 clear_tco_status(void) -{ - return print_tco_status(reset_tco_status()); -} - -/* Enable TCO SCI */ -void enable_tco_sci(void) -{ - /* Clear pending events */ - outl(TCOSCI_STS, get_pmbase() + GPE0_STS(3)); - - /* Enable TCO SCI events */ - enable_gpe(TCOSCI_EN); -} - -/* - * GPE0 - */ - -/* Clear a GPE0 status and return events that are enabled and active */ -static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) -{ - u32 gpe0_sts = inl(get_pmbase() + sts_reg); - u32 gpe0_en = inl(get_pmbase() + en_reg); - - outl(gpe0_sts, get_pmbase() + sts_reg); - - /* Only report enabled events */ - return gpe0_sts & gpe0_en; -} - -/* Print GPE0 status bits */ -static u32 print_gpe_status(u32 gpe0_sts, const char *bit_names[]) -{ - if (!gpe0_sts) - return 0; - - printk(BIOS_DEBUG, "GPE0_STS: "); - print_status_bits(gpe0_sts, bit_names); - printk(BIOS_DEBUG, "\n"); - - return gpe0_sts; -} - -/* Print GPE0 GPIO status bits */ -static u32 print_gpe_gpio(u32 gpe0_sts, int start) -{ - if (!gpe0_sts) - return 0; - - printk(BIOS_DEBUG, "GPE0_STS: "); - print_gpio_status(gpe0_sts, start); - printk(BIOS_DEBUG, "\n"); - - return gpe0_sts; -} - -/* Clear all GPE status and return "standard" GPE event status */ -u32 clear_gpe_status(void) -{ - const char *gpe0_sts_3_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", - [10] = "BATLOW", - [11] = "PME", - [12] = "ME", - [13] = "PME_B0", - [16] = "GPIO27", - [18] = "WADT" - }; - - print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); - print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); - print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); - return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), - gpe0_sts_3_bits); -} - -/* Enable all requested GPE */ -void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) -{ - u16 pmbase = get_pmbase(); - - outl(set1, pmbase + GPE0_EN(GPE_31_0)); - outl(set2, pmbase + GPE0_EN(GPE_63_32)); - outl(set3, pmbase + GPE0_EN(GPE_94_64)); - outl(set4, pmbase + GPE0_EN(GPE_STD)); -} - -/* Disable all GPE */ -void disable_all_gpe(void) -{ - enable_all_gpe(0, 0, 0, 0); -} - -/* Enable a standard GPE */ -void enable_gpe(u32 mask) -{ - u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); - gpe0_en |= mask; - outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); -} - -/* Disable a standard GPE */ -void disable_gpe(u32 mask) -{ - u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); - gpe0_en &= ~mask; - outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); -} - -int platform_is_resuming(void) -{ - if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) - return 0; - - return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; -} - -void poweroff(void) -{ - uint32_t pm1_cnt; - - /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); -} - -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t)ACPI_BASE_ADDRESS; -} diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c deleted file mode 100644 index 51f31a1280c..00000000000 --- a/src/southbridge/intel/wildcatpoint/smi.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void smm_southbridge_clear_state(void) -{ - u32 smi_en; - - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); -} - -static void smm_southbridge_enable(uint16_t pm1_events) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - enable_pm1(pm1_events); - disable_gpe(PME_B0_EN); - - /* Enable SMI generation: - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - * - on TCO events - */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); -} - -void global_smi_enable(void) -{ - smm_southbridge_enable(PWRBTN_EN | GBL_EN); -} diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c index 890167b45b3..643c6808134 100644 --- a/src/southbridge/intel/wildcatpoint/smihandler.c +++ b/src/southbridge/intel/wildcatpoint/smihandler.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include /** * @brief Set the EOS bit @@ -289,9 +291,21 @@ static void southbridge_smi_store(void) /* Parameter buffer in EBX */ reg_ebx = io_smi->rbx; + const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + const bool wp_enabled = !(pci_read_config16(lpc_dev, BIOS_CNTL) & BIOS_CNTL_BIOSWE); + if (wp_enabled) { + set_insmm_sts(true); + pci_or_config16(lpc_dev, BIOS_CNTL, BIOS_CNTL_BIOSWE); + } + /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_ebx); io_smi->rax = ret; + + if (wp_enabled) { + pci_and_config16(lpc_dev, BIOS_CNTL, ~BIOS_CNTL_BIOSWE); + set_insmm_sts(false); + } } static void southbridge_smi_apmc(void) @@ -370,7 +384,7 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL); - if (bios_cntl & 1) { + if (bios_cntl & BIOS_CNTL_BIOSWE) { /* * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS @@ -382,7 +396,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, bios_cntl & ~BIOS_CNTL_BIOSWE); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 645e5f11b47..5d40fc78259 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -7,11 +7,12 @@ #include #include #include +#include #include "rl5c476.h" #include "chip.h" static int enable_cf_boot = 0; -static unsigned int cf_base; +static uintptr_t cf_base; static void rl5c476_init(struct device *dev) { @@ -21,7 +22,7 @@ static void rl5c476_init(struct device *dev) /* cardbus controller function 1 for CF Socket */ printk(BIOS_DEBUG, "Ricoh RL5c476: Initializing.\n"); - printk(BIOS_DEBUG, "CF Base = %0x\n",cf_base); + printk(BIOS_DEBUG, "CF Base = %0lx\n", cf_base); /* misc control register */ pci_write_config16(dev,0x82,0x00a0); @@ -44,7 +45,7 @@ static void rl5c476_init(struct device *dev) /* pick up where 16 bit card control structure is * (0x800 bytes into config structure) */ - base = (unsigned char *)pci_read_config32(dev,0x10); + base = (unsigned char *)(uintptr_t)pci_read_config32(dev, 0x10); pc16 = (pc16reg_t *)(base + 0x800); /* disable memory and io windows and turn off socket power */ diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index a3277451686..53a9bd6e5f1 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include "pci7420.h" diff --git a/src/superio/nuvoton/Makefile.mk b/src/superio/nuvoton/Makefile.mk index eab992a666d..2a7cbc3362a 100644 --- a/src/superio/nuvoton/Makefile.mk +++ b/src/superio/nuvoton/Makefile.mk @@ -5,6 +5,7 @@ bootblock-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c ## include generic nuvoton helper ramstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/common.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_HWM) += common/hwm.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig index f3e8e4ae932..0d0a202398d 100644 --- a/src/superio/nuvoton/common/Kconfig +++ b/src/superio/nuvoton/common/Kconfig @@ -21,6 +21,13 @@ config HAVE_SHARED_PS2_PORT port. This one port usually works for keyboards only. Add the nvram/CFR option "ps2_port_role" to allow changing this port into a mouse port. +config SUPERIO_NUVOTON_COMMON_HWM + bool + help + Shared hardware monitor helpers for Nuvoton super I/Os whose HWM + block uses the banked-register interface (NCT67xx family). Provides + PECI enable, PECI calibration, and SmartFan IV fan-curve programming. + config SUPERIO_NUVOTON_PNP_BASE hex depends on SUPERIO_NUVOTON_COMMON_PRE_RAM diff --git a/src/superio/nuvoton/common/hwm.c b/src/superio/nuvoton/common/hwm.c new file mode 100644 index 00000000000..4464adfdf76 --- /dev/null +++ b/src/superio/nuvoton/common/hwm.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void nuvoton_hwm_enable_peci(uint16_t base, uint8_t tjmax) +{ + /* Bank 7: PECI agent config. */ + nuvoton_hwm_select_bank(base, 7); + pnp_write_hwm5_index(base, 0x01, 0x85); /* PECI_En | Is_PECI30 | Routine_En */ + pnp_write_hwm5_index(base, 0x02, 0x02); /* Timing: 1.5 MHz, 75% duty */ + pnp_write_hwm5_index(base, 0x03, 0x10); /* Enable Agent 0 only */ + pnp_write_hwm5_index(base, 0x04, 0x00); + pnp_write_hwm5_index(base, 0x09, tjmax); + + /* Bank 0 CR AEh bit 0: enable Agent 0 PECI reading. */ + nuvoton_hwm_select_bank(base, 0); + pnp_write_hwm5_index(base, 0xae, 1); +} + +void nuvoton_hwm_set_sensor_type(uint16_t base, + enum nuvoton_temp_source src, + enum nuvoton_temp_sensor_type type) +{ + uint8_t bit = 1 << src; + uint8_t cr5d, cr5e; + + nuvoton_hwm_select_bank(base, 0); + cr5d = pnp_read_hwm5_index(base, 0x5d); + cr5e = pnp_read_hwm5_index(base, 0x5e); + + if (type == NUVOTON_TEMP_SENSOR_DIODE) { + cr5d |= bit; + cr5e |= bit; + } else { + cr5d &= ~bit; + cr5e &= ~bit; + } + + pnp_write_hwm5_index(base, 0x5d, cr5d); + pnp_write_hwm5_index(base, 0x5e, cr5e); +} + +void nuvoton_hwm_enable_peci_calibration(uint16_t base) +{ + nuvoton_hwm_select_bank(base, 4); + pnp_write_hwm5_index(base, 0xf8, 0x50); /* 10 updates per interval, 1 C per step */ + pnp_write_hwm5_index(base, 0xfa, 0x51); /* 1 s interval, enable */ +} + +void nuvoton_hwm_configure_fan(uint16_t base, const struct nuvoton_fan_curve *fan) +{ + size_t i; + + printk(BIOS_DEBUG, "Nuvoton HWM: configuring fan %s (bank %u)\n", + fan->name, fan->bank); + + nuvoton_hwm_select_bank(base, fan->bank); + + pnp_write_hwm5_index(base, NUVOTON_FAN_SOURCE, fan->source); + + for (i = 0; i < NUVOTON_FAN_CURVE_NPOINTS; i++) + pnp_write_hwm5_index(base, NUVOTON_FAN_TEMP(i), fan->temp[i]); + for (i = 0; i < NUVOTON_FAN_CURVE_NPOINTS; i++) + pnp_write_hwm5_index(base, NUVOTON_FAN_DUTY(i), fan->duty[i]); + + pnp_write_hwm5_index(base, NUVOTON_FAN_CRIT_TEMP, fan->crit_temp); + pnp_write_hwm5_index(base, NUVOTON_FAN_CRIT_DUTY_EN, fan->crit_duty_en); + pnp_write_hwm5_index(base, NUVOTON_FAN_CRIT_DUTY, fan->crit_duty); + pnp_write_hwm5_index(base, NUVOTON_FAN_CRIT_TEMP_TOLERANCE, fan->crit_temp_tolerance); + + pnp_write_hwm5_index(base, NUVOTON_FAN_STEP_UP_TIME, fan->step_up_time); + pnp_write_hwm5_index(base, NUVOTON_FAN_STEP_DOWN_TIME, fan->step_down_time); + pnp_write_hwm5_index(base, NUVOTON_FAN_DUTY_PER_STEP, + (fan->duty_per_step_up << 4) | fan->duty_per_step_down); + + pnp_write_hwm5_index(base, NUVOTON_FAN_MODE_TEMP_TOLERANCE, + (NUVOTON_FAN_MODE_SMARTFAN_IV << 4) | fan->temp_tolerance); +} diff --git a/src/superio/nuvoton/common/hwm.h b/src/superio/nuvoton/common/hwm.h index 42e0f4af947..d2c197cdef3 100644 --- a/src/superio/nuvoton/common/hwm.h +++ b/src/superio/nuvoton/common/hwm.h @@ -15,4 +15,120 @@ static inline void nuvoton_hwm_select_bank(const u16 base, const u8 bank) pnp_write_hwm5_index(base, HWM_BANK_SELECT, bank); } +/* SmartFan IV register offsets within a per-fan bank. */ + +/* Fan control temperature source. */ +#define NUVOTON_FAN_SOURCE 0x00 +/* PECI agent raw; PECI_CAL is the CPUTIN-calibrated version. */ +#define NUVOTON_FAN_SOURCE_PECI0 0x10 +#define NUVOTON_FAN_SOURCE_PECI1 0x11 +#define NUVOTON_FAN_SOURCE_PECI0_CAL 0x1c +#define NUVOTON_FAN_SOURCE_PECI1_CAL 0x1d + +/* Fan mode + temperature tolerance: [7:4] mode, [2:0] tolerance */ +#define NUVOTON_FAN_MODE_TEMP_TOLERANCE 0x02 +#define NUVOTON_FAN_MODE_SMARTFAN_IV 4 + +/* Step up/down time, in 0.1 second units */ +#define NUVOTON_FAN_STEP_UP_TIME 0x03 +#define NUVOTON_FAN_STEP_DOWN_TIME 0x04 + +/* Duty change per step: [7:4] up, [3:0] down */ +#define NUVOTON_FAN_DUTY_PER_STEP 0x66 + +/* 4-point SmartFan IV curve */ +#define NUVOTON_FAN_TEMP(i) (0x21 + (i)) +#define NUVOTON_FAN_DUTY(i) (0x27 + (i)) + +/* Critical temperature handling */ +#define NUVOTON_FAN_CRIT_TEMP 0x35 +#define NUVOTON_FAN_CRIT_DUTY_EN 0x36 +#define NUVOTON_FAN_CRIT_DUTY 0x37 +#define NUVOTON_FAN_CRIT_TEMP_TOLERANCE 0x38 + +#define NUVOTON_PERCENT_TO_DUTY(perc) ((perc) * 255 / 100) + +#define NUVOTON_FAN_CURVE_NPOINTS 4 + +struct nuvoton_fan_curve { + const char *name; + + /* Per-fan register bank (1 = SYSFAN, 2 = CPUFAN, ...) */ + uint8_t bank; + + /* Temperature source (NUVOTON_FAN_SOURCE_*) */ + uint8_t source; + + /* Temperature vs duty curve */ + uint8_t temp[NUVOTON_FAN_CURVE_NPOINTS]; + uint8_t duty[NUVOTON_FAN_CURVE_NPOINTS]; + + /* Temperature tolerance */ + uint8_t temp_tolerance; + + /* Step up/down smoothing */ + uint8_t step_up_time; + uint8_t step_down_time; + uint8_t duty_per_step_up; + uint8_t duty_per_step_down; + + /* Critical mode */ + uint8_t crit_temp; + uint8_t crit_duty_en; + uint8_t crit_duty; + uint8_t crit_temp_tolerance; +}; + +/* + * Temperature sensor input channels. The numeric value of each enum + * matches the bit position in Bank 0 CR 5Dh (sensor type) and Bank 0 + * CR 5Eh (current-mode enable) for that channel. + */ +enum nuvoton_temp_source { + NUVOTON_TEMP_SRC_SYSTIN = 1, + NUVOTON_TEMP_SRC_CPUTIN = 2, + NUVOTON_TEMP_SRC_AUXTIN0 = 3, + NUVOTON_TEMP_SRC_AUXTIN1 = 4, + NUVOTON_TEMP_SRC_AUXTIN2 = 5, + NUVOTON_TEMP_SRC_AUXTIN3 = 6, + NUVOTON_TEMP_SRC_AUXTIN4 = 7, +}; + +enum nuvoton_temp_sensor_type { + NUVOTON_TEMP_SENSOR_THERMISTOR, /* voltage-divider mode */ + NUVOTON_TEMP_SENSOR_DIODE, /* current-sensing mode (external diode) */ +}; + +/* + * Configure the sensor type for one temperature input channel. Boards + * must call this before the relevant channel's reading is meaningful + * if the chip default (diode + current mode, except for SYSTIN which + * defaults to thermistor) does not match the hardware actually wired + * to the pin. + */ +void nuvoton_hwm_set_sensor_type(uint16_t base, + enum nuvoton_temp_source src, + enum nuvoton_temp_sensor_type type); + +/* + * Enable PECI Agent 0 on the HWM block as a readable temperature source. + * + * tjmax is the CPU's Tjmax in degrees Celsius (100 on most Intel + * desktop parts); PECI reports temperature as an offset below this. + * Devicetree must have configured the superio pin as PECI first. + */ +void nuvoton_hwm_enable_peci(uint16_t base, uint8_t tjmax); + +/* + * Enable the PECI calibration pass (NCT6796D datasheet s8.7.1). The + * chip slews the calibrated source toward CPUTIN in bounded steps. + * Boards with a real thermistor on CPUTIN must configure it via + * nuvoton_hwm_set_sensor_type beforehand, or the calibrated output + * will be garbage. + */ +void nuvoton_hwm_enable_peci_calibration(uint16_t base); + +/* Program SmartFan IV on one fan using the given curve. */ +void nuvoton_hwm_configure_fan(uint16_t base, const struct nuvoton_fan_curve *fan); + #endif /* SUPERIO_NUVOTON_COMMON_HWM_H */ diff --git a/src/vendorcode/amd/fsp/renoir/FspUpd.h b/src/vendorcode/amd/fsp/renoir/FspUpd.h index efd8bdd64e2..ebfe9e8e040 100644 --- a/src/vendorcode/amd/fsp/renoir/FspUpd.h +++ b/src/vendorcode/amd/fsp/renoir/FspUpd.h @@ -14,7 +14,7 @@ # include #endif -#define FSPM_UPD_SIGNATURE 0x4D5F31305F444D41 /* 'RENOIR_M' */ -#define FSPS_UPD_SIGNATURE 0x535F31305F444D41 /* 'RENOIR_S' */ +#define FSPM_UPD_SIGNATURE 0x4D5F31305F444D41 /* 'AMD_01_M' */ +#define FSPS_UPD_SIGNATURE 0x535F31305F444D41 /* 'AMD_01_S' */ #endif diff --git a/src/vendorcode/amd/fsp/strix_halo/FspUpd.h b/src/vendorcode/amd/fsp/strix_halo/FspUpd.h new file mode 100644 index 00000000000..f6e43498872 --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/FspUpd.h @@ -0,0 +1,21 @@ +/** @file + * + * This file is _NOT_ automatically generated in coreboot! + * + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#ifdef EFI32 +# include +# include +#else +# include +#endif + +#define FSPM_UPD_SIGNATURE 0x4D5F31305F444D41 /* 'AMD_01_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F31305F444D41 /* 'AMD_01_S' */ + +#endif diff --git a/src/vendorcode/amd/fsp/strix_halo/FspUsb.h b/src/vendorcode/amd/fsp/strix_halo/FspUsb.h new file mode 100644 index 00000000000..ca0a16b10d7 --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/FspUsb.h @@ -0,0 +1,60 @@ +#ifndef __FSPUSB_H__ +#define __FSPUSB_H__ + +#include + +#define FSP_USB_STRUCT_MAJOR_VERSION 0xf +#define FSP_USB_STRUCT_MINOR_VERSION 0x2 + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 3 +#define USBC_COMBO_PHY_COUNT 3 + +struct fch_usb2_phy { + uint8_t compdistune; ///< COMPDISTUNE + uint8_t pllbtune; ///< PLLBTUNE + uint8_t pllitune; ///< PLLITUNE + uint8_t pllptune; ///< PLLPTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +} __packed; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +} __packed; + +#define USB0_PORT0 0 +#define USB0_PORT1 1 +#define USB0_PORT2 1 +#define USB0_PORT3 3 +#define USB1_PORT0 (0<<2) +#define USB1_PORT1 (1<<2) +#define USB1_PORT2 (1<<2) +#define USB1_PORT3 (3<<2) + +#define USB_COMBO_PHY_MODE_USB_C 0 +#define USB_COMBO_PHY_MODE_USB_ONLY 1 +#define USB_COMBO_PHY_MODE_USB_DPM 2 +#define USB_COMBO_PHY_MODE_USB_DPP 3 + +struct usb_phy_config { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved1[5]; +} __packed; + +#endif diff --git a/src/vendorcode/amd/fsp/strix_halo/FspmUpd.h b/src/vendorcode/amd/fsp/strix_halo/FspmUpd.h new file mode 100644 index 00000000000..4475a69180b --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/FspmUpd.h @@ -0,0 +1,142 @@ +/** @file + * + * This file is _NOT_ automatically generated in coreboot! + * + */ + +/* TODO: Update for Glinda */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include +#include + +#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 +#define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 + +/** Fsp M Configuration +**/ +typedef struct __packed { + /** Offset 0x0040**/ uint32_t bert_size; + /** Offset 0x0044**/ uint32_t tseg_size; + /** Offset 0x0048**/ uint32_t pci_express_base_addr; + /** Offset 0x004C**/ uint8_t misc_reserved[32]; + /** Offset 0x006C**/ uint32_t serial_port_base; + /** Offset 0x0070**/ uint32_t serial_port_use_mmio; + /** Offset 0x0074**/ uint32_t serial_port_baudrate; + /** Offset 0x0078**/ uint32_t serial_port_refclk; + /** Offset 0x007C**/ uint32_t serial_reserved; + /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; + /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; + /** Offset 0x0359**/ uint8_t pcie_reserved[51]; + /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; + /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; + /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; + /** Offset 0x03A7**/ uint8_t ccx_disable_smt; + /** Offset 0x03A8**/ uint8_t ccx_reserved[32]; + /** Offset 0x03C8**/ uint8_t stt_control; + /** Offset 0x03C9**/ uint8_t stt_pcb_sensor_count; + /** Offset 0x03CA**/ uint16_t stt_min_limit; + /** Offset 0x03CC**/ uint16_t stt_m1; + /** Offset 0x03CE**/ uint16_t stt_m2; + /** Offset 0x03D0**/ uint16_t stt_m3; + /** Offset 0x03D2**/ uint16_t stt_m4; + /** Offset 0x03D4**/ uint16_t stt_m5; + /** Offset 0x03D6**/ uint16_t stt_m6; + /** Offset 0x03D8**/ uint16_t stt_c_apu; + /** Offset 0x03DA**/ uint16_t stt_c_gpu; + /** Offset 0x03DC**/ uint16_t stt_c_hs2; + /** Offset 0x03DE**/ uint16_t stt_alpha_apu; + /** Offset 0x03E0**/ uint16_t stt_alpha_gpu; + /** Offset 0x03E2**/ uint16_t stt_alpha_hs2; + /** Offset 0x03E4**/ uint16_t stt_skin_temp_apu; + /** Offset 0x03E6**/ uint16_t stt_skin_temp_gpu; + /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; + /** Offset 0x03EA**/ uint16_t stt_error_coeff; + /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; + /** Offset 0x03EE**/ uint8_t smartshift_enable; + /** Offset 0x03EF**/ uint32_t apu_only_sppt_limit; + /** Offset 0x03F3**/ uint32_t sustained_power_limit; + /** Offset 0x03F7**/ uint32_t fast_ppt_limit; + /** Offset 0x03FB**/ uint32_t slow_ppt_limit; + /** Offset 0x03FF**/ uint8_t system_configuration; + /** Offset 0x0400**/ uint8_t cppc_ctrl; + /** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range; + /** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range; + /** Offset 0x0403**/ uint8_t cppc_epp_max_range; + /** Offset 0x0404**/ uint8_t cppc_epp_min_range; + /** Offset 0x0405**/ uint8_t cppc_preferred_cores; + /** Offset 0x0406**/ uint8_t stapm_boost; + /** Offset 0x0407**/ uint32_t stapm_time_constant; + /** Offset 0x040B**/ uint32_t slow_ppt_time_constant; + /** Offset 0x040F**/ uint32_t thermctl_limit; + /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9]; + /** Offset 0x041C**/ uint8_t iommu_support; + /** Offset 0x041D**/ uint8_t pspp_policy; + /** Offset 0x041E**/ uint8_t enable_nb_azalia; + /** Offset 0x041F**/ uint8_t audio_io_ctl; + /** Offset 0x0420**/ uint8_t pdm_mic_selection; + /** Offset 0x0421**/ uint8_t hda_enable; + /** Offset 0x0422**/ uint8_t nbio_reserved[31]; + /** Offset 0x0441**/ uint32_t emmc0_mode; + /** Offset 0x0445**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; + /** Offset 0x049F**/ uint32_t gnb_ioapic_base; + /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; + /** Offset 0x04A4**/ uint8_t fch_ioapic_id; + /** Offset 0x04A5**/ uint8_t sata_enable; + /** Offset 0x04A6**/ uint8_t fch_reserved[32]; + /** Offset 0x04C6**/ uint8_t s0i3_enable; + /** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current; + /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; + /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; + /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; + /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; + /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ + /** Offset 0x04D8**/ uint32_t usb_phy_ptr; + /** Offset 0x04DC**/ uint8_t Usb4Rt0En; + /** Offset 0x04DD**/ uint8_t Usb4Rt1En; + /** Offset 0x04DE**/ uint8_t Usb4Rt0XhciEn; + /** Offset 0x04DF**/ uint8_t Usb4Rt1XhciEn; + /** Offset 0x04E0**/ uint64_t xgbe_port0_mac; + /** Offset 0x04E8**/ uint64_t xgbe_port1_mac; + /** Offset 0x04F0**/ uint8_t xgbe_port0_config_en; + /** Offset 0x04F1**/ uint8_t xgbe_port1_config_en; + /* xgbe_port0_table_ptr is actually uint32_t *, but that won't work for 64bit coreboot */ + /** Offset 0x04F2**/ uint32_t xgbe_port0_table_ptr; + /** Offset 0x04F6**/ uint32_t xgbe_port1_table_ptr; + /** Offset 0x04FA**/ uint8_t XgbeDisable; + /** Offset 0x04FB**/ uint8_t disp_combo_PHY; + /** Offset 0x04FC**/ uint8_t xgbe_led_en; + /** Offset 0x04FD**/ uint8_t xgbe_led_link_status0; + /** Offset 0x04FE**/ uint8_t xgbe_led_link_status1; + /** Offset 0x04FF**/ uint8_t xgbe_led_link_speed0; + /** Offset 0x0500**/ uint8_t xgbe_led_link_speed1; + /** Offset 0x0501**/ uint8_t xgbe_led_tx_rx_blink_rate0; + /** Offset 0x0502**/ uint8_t xgbe_led_tx_rx_blink_rate1; + /** Offset 0x0503**/ uint32_t fch_rt_device_enable_map; + /** Offset 0x0507**/ uint8_t amd_pcie_aer_report_mechanism; + /** Offset 0x0508**/ uint8_t amd_nbio_ras_controlv2; + /** Offset 0x0509**/ uint8_t pcie_ecrc_enablement; + /** Offset 0x050A**/ uint8_t UnusedUpdSpace2[246]; + /** Offset 0x0600**/ uint16_t UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; + /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + +#endif diff --git a/src/vendorcode/amd/fsp/strix_halo/FspsUpd.h b/src/vendorcode/amd/fsp/strix_halo/FspsUpd.h new file mode 100644 index 00000000000..bff5e065776 --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/FspsUpd.h @@ -0,0 +1,26 @@ +/** @file + * + * This file is _NOT_ automatically generated in coreboot! + * + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +typedef struct __packed { + /** Offset 0x0020**/ uint32_t vbios_buffer; + /** Offset 0x0024**/ uint64_t gop_reserved; + /** Offset 0x002C**/ uint32_t reserved1; + /** Offset 0x0030**/ uint16_t UpdTerminator; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig; +} FSPS_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/strix_halo/platform_descriptors.h b/src/vendorcode/amd/fsp/strix_halo/platform_descriptors.h new file mode 100644 index 00000000000..c627517d6be --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/platform_descriptors.h @@ -0,0 +1,335 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +/* TODO: Update for Glinda */ + +#ifndef PI_PLATFORM_DESCRIPTORS_H +#define PI_PLATFORM_DESCRIPTORS_H + +#include + +#define NUM_DXIO_PHY_PARAMS 6 +#define NUM_DXIO_PORT_PARAMS 6 + +/* Engine descriptor type */ +enum dxio_engine_type { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +}; + +/* PCIe link capability/speed */ +enum dxio_link_speed_cap { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN4, + GEN_INVALID // Max Gen for boundary check +}; + +/* Upstream Auto Speed Change Allowed */ +enum dxio_upstream_auto_speed_change { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISABLED, + SPDC_ENABLED, + SPDC_INVALID +}; + +/* SATA ChannelType initialization */ +enum dxio_sata_channel_type { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +}; + +/* CLKREQ for PCIe type descriptors */ +enum cpm_clk_req { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, + CLK_ENABLE = 0xff, +}; + +/* PCIe link ASPM initialization */ +enum dxio_aspm_type { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +}; + +/* PCIe link hotplug */ +enum dxio_link_hotplug_type { + HOTPLUG_DISABLED = 0, + HOTPLUG_BASIC, + HOTPLUG_SERVER, + HOTPLUG_ENHANCED, + HOTPLUG_INBOARD, + HOTPLUG_SERVER_SSD, +}; + +/* TODO: update dxio_port_param_type to match the AGESA/FSP code */ +enum dxio_port_param_type { + PP_DEVICE = 1, + PP_FUNCTION, + PP_PORT_PRESENT, + PP_LINK_SPEED_CAP, + PP_LINK_ASPM, + PP_HOTPLUG_TYPE, + PP_CLKREQ, + PP_ASPM_L1_1, + PP_ASPM_L1_2, + PP_COMPLIANCE, + PP_SAFE_MODE, + PP_CHIPSET_LINK, + PP_CLOCK_PM, + PP_CHANNELTYPE, + PP_TURN_OFF_UNUSED_LANES, + PP_APIC_GROUPMAP, + PP_APIC_SWIZZLE, + PP_APIC_BRIDGEINT, + PP_MASTER_PLL, + PP_SLOT_NUM, + PP_PHY_PARAM, + PP_ESM, + PP_CCIX, + PP_GEN3_DS_TX_PRESET, + PP_GEN3_DS_RX_PRESET_HINT, + PP_GEN3_US_TX_PRESET, + PP_GEN3_US_RX_PRESET_HINT, + PP_GEN4_DS_TX_PRESET, + PP_GEN4_US_TX_PRESET, + PP_GEN3_FIXED_PRESET, + PP_GEN4_FIXED_PRESET, + PP_PSPP_DC, + PP_PSPP_AC, + PP_GEN2_DEEMPHASIS, + PP_INVERT_POLARITY, + PP_TARGET_LINK_SPEED, + PP_GEN4_DLF_CAP_DISABLE, + PP_GEN4_DLF_EXCHG_DISABLE +}; + +/* DDI Aux channel */ +enum ddi_aux_type { + DDI_AUX1 = 0, + DDI_AUX2, + DDI_AUX3, + DDI_AUX4, + DDI_AUX5, + DDI_AUX6, + DDI_AUX_MAX // Not valid value, used to verify input +}; + +/* DDI Hdp Index */ +enum ddi_hdp_type { + DDI_HDP1 = 0, + DDI_HDP2, + DDI_HDP3, + DDI_HDP4, + DDI_HDP5, + DDI_HDP6, + DDI_HDP_MAX // Not valid value, used to verify input +}; + +/* DDI display connector type */ +enum ddi_connector_type { + DDI_DP = 0, // DP + DDI_EDP, // eDP + DDI_SINGLE_LINK_DVI, // Single Link DVI-D + DDI_DUAL_LINK_DVI, // Dual Link DVI-D + DDI_HDMI, // HDMI + DDI_DP_TO_VGA, // DP-to-VGA + DDI_DP_TO_LVDS, // DP-to-LVDS + DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I + DDI_DP_W_TYPEC, // DP with USB type C + DDI_DP_WO_TYPEC, // DP without USB type C + DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + DDI_AUTO_DETECT, // VBIOS auto detect connector type + DDI_UNUSED_TYPE, // UnusedType + DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input +}; + +/* DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; // see ddi_connector_type + uint8_t aux_index; // see ddi_aux_type + uint8_t hdp_index; // see ddi_hdp_type + uint8_t reserved; +} fsp_ddi_descriptor; + +/* + * Glinda DXIO Descriptor: Used for assigning lanes to PCIe engines, configure + * bifurcation and other settings. Beware that the lane numbers in here are the + * logical and not the physical lane numbers! + * + * Glinda DXIO logical lane to physical PCIe lane mapping: + * + * logical | physical + * --------|------------ + * [00:03] | GPP[03:00] + * + * Different ports mustn't overlap or be assigned to the same lane(s). Within + * ports with the same width the one with a higher start logical lane number + * needs to be assigned to a higher PCIe root port number; ports of the same + * size don't have to be assigned to consecutive PCIe root ports though. + */ +typedef struct __packed { + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // GPIO number used as reset + uint32_t port_present :1; // Should be TRUE if train link + uint32_t reserved_3 :7; + uint32_t device_number :5; // Desired root port device number + uint32_t function_number :3; // Desired root port function number + uint32_t :2; + uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint32_t eq_preset :4; // Gen3 equalization preset + uint32_t link_aspm :2; // See dxio_aspm_type + uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint32_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // See dxio_link_hotplug_type + uint8_t slot_power_limit; // Currently unused by FSP + uint32_t slot_power_limit_scale :2; // Currently unused by FSP + uint32_t link_speed_capability :3; // See dxio_link_speed_cap + uint32_t :3; + uint32_t link_compliance_mode :1; // Currently unused by FSP + uint32_t link_safe_mode :1; // Currently unused by FSP + uint32_t sb_link :1; // Currently unused by FSP + uint32_t clk_pm_support :1; // Currently unused by FSP + uint32_t channel_type :3; // See dxio_sata_channel_type + uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present + uint8_t reserved[4]; + uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2]; + uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type +} fsp_dxio_descriptor; + +typedef enum { + XGBE_PORT_DISABLE, + XGBE_PORT_ENABLE, +} xgbe_port_enable; + +typedef enum { + XGBE_PHY_MODE_RJ45, + XGBE_PHY_MODE_SFP_PLUS, + XGBE_PHY_MODE_BACKPLANE +} xgbe_port_phy_modes; + +typedef enum { + XGBE_RESERVED, + XGBE_10G_1G_BACKPLANE, + XGBE_2_5G_BACKPLANE, + XGBE_SOLDERED_DOWN_1000BASE_T, + XGBE_SOLDERED_DOWN_1000BASE_X, + XGBE_SOLDERED_DOWN_NBASE_T, + XGBE_SOLDERED_DOWN_10GBASE_T, + XGBE_SOLDERED_DOWN_10GBASE_R, + XGBE_SFP_PLUS_CONNECTOR, + XGBE_PORT_SGMII_BACKPLANE, + XGBE_5G_BACKPLANE, +} xgbe_port_platform_config; + +typedef enum { + XGBE_PORT_SPEED_10M = 0x1, + XGBE_PORT_SPEED_100M = 0x2, + XGBE_PORT_SPEED_1G = 0x4, + XGBE_PORT_SPEED_2500M = 0x8, + XGBE_PORT_SPEED_5G = 0x32, + XGBE_PORT_SPEED_10G = 0x10, + XGBE_PORT_SPEED_10_100_1000M = 0x7, +} xgbe_port_speed_config; + +typedef enum { + XGBE_PORT_NOT_USED = 0x0, + XGBE_SFP_PLUS_CONNECTION = 0x1, + XGBE_CONNECTION_MDIO_PHY = 0x2, + XGBE_BACKPLANE_CONNECTION = 0x4, +} xgbe_port_connection_type; + +struct __packed xgbe_port_table { + uint8_t XgbePortConfig; ///< XGbE controller Port Config Enable/disable + uint8_t XgbePortPlatformConfig; ///< Platform Config + /// @li 0000 - Reserved + /// @li 0001 - 10G/1G Backplane + /// @li 0010 - 2.5G Backplane + /// @li 0011 - 1000Base-T + /// @li 0100 - 1000Base-X + /// @li 0101 - NBase-T + /// @li 0110 - 10GBase-T + /// @li 0111 - 10GBase-X + /// @li 1000 - SFP+ + uint8_t XgbePortSupportedSpeed; ///< Indicated Ethernet speeds supported on platform + /// @li 1xxx - 10/100/1000M + /// @li x1xx - 1G + /// @li xx1x - 1G + /// @li xxx1 - 100M + uint8_t XgbePortConnectedType; ///< PHY connected type + /// @li 000 - Port not used + /// @li 001 - SFP+ + /// @li 010 - MDIO + /// @li 100 - Backplane connection + uint8_t XgbePortMdioId; ///< MDIO ID of the PHY associated with this port + uint8_t XgbePortMdioResetType; ///< MDIO PHY reset type + /// @li 00 - None + /// @li 01 - I2C GPIO + /// @li 10 - Integrated GPIO + /// @li 11 - Reserved + uint8_t XgbePortResetGpioNum; ///< GPIO used to control the reset + uint8_t XgbePortMdioResetI2cAddress; ///< I2C address of PCA9535 MDIO reset GPIO + uint8_t XgbePortSfpI2cAddress; ///< I2C address of PCA9535 for SFP + uint8_t XgbePortSfpTxFaultGpio; ///< GPIO number for SFP+ TX_FAULT + uint8_t XgbePortSfpRsGpio; ///< GPIO number for SFP+ RS + uint8_t XgbePortSfpModAbsGpio; ///< GPIO number for SFP+ Mod_ABS + uint8_t XgbePortSfpRxLosGpio; ///< GPIO number for SFP+ Rx_LOS + uint8_t XgbePortSfpGpioMask; ///< GPIO Mask for SFP+ + /// @li 1xxx - Rx_LOS not supported + /// @li x1xx - Mod_ABS not supported + /// @li xx1x - RS not supported + /// @li xxx1 - TX_FAULT not supported + uint8_t XgbePortSfpTwiAddress; ///< Address of PCA9545 I2C multiplexor + uint8_t XgbePortSfpTwiBus; ///< Downstream channel of PCA9545 + uint8_t XgbaPortRedriverPresent; ///< Redriver Present or not + uint8_t Reserve0[3]; ///< Reserved + uint8_t XgbaPortRedriverModel; ///< Redriver Model + /// @li 00 - InPhi 4223 + /// @li 01 - InPhi 4227 + uint8_t XgbaPortRedriverInterface; ///< Redriver Interface + /// @li 00 - MDIO + /// @li 01 - I2C + uint8_t XgbaPortRedriverAddress; ///< Redriver Address + uint8_t XgbaPortRedriverLane; ///< Redriver Lane + uint8_t XgbaPortPadGpio; ///< Portx_GPIO Pad selection + /// @li 001 - MDIO0 pin + /// @li 010 - MDIO1 pin + /// @li 100 - SFP pin + uint8_t XgbaPortPadMdio; ///< Portx_Mdio Pad selection + /// @li 001 - MDIO0 pin + /// @li 010 - MDIO1 pin + /// @li 100 - SFP pin + uint8_t XgbaPortPadI2C; ///< Portx_I2C Pad selection + /// @li 001 - MDIO0 pin + /// @li 010 - MDIO1 pin + /// @li 100 - SFP pin + uint8_t Reserve1; ///< Reserved + }; + +#endif /* PI_PLATFORM_DESCRIPTORS_H */ diff --git a/src/vendorcode/amd/fsp/strix_halo/soc_dmi_info.h b/src/vendorcode/amd/fsp/strix_halo/soc_dmi_info.h new file mode 100644 index 00000000000..073ceb72f83 --- /dev/null +++ b/src/vendorcode/amd/fsp/strix_halo/soc_dmi_info.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Strix Halo */ + +/* + * These definitions are used to describe memory modules physical layout + */ + +#ifndef SOC_DMI_INFO_H +#define SOC_DMI_INFO_H + +#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table +#define AGESA_STRUCT_CHANNELS_PER_SOCKET 16 ///< Channels per socket in AGESA FSP DMI T17 table +#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table +#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count +#define AGESA_STRUCT_T20_REGION_SUPPORTED 3 ///< Max SMBIOS T20 Memory Region count +#define AGESA_STRUCT_PART_NUMBER_SIZE 31 + +#define SMBIOS_3_2_SUPPORT 1 +#define SMBIOS_3_3_SUPPORT 1 + +#endif /* SOC_DMI_INFO_H */ diff --git a/src/vendorcode/google/chromeos/battery.c b/src/vendorcode/google/chromeos/battery.c index 0e676b3f2a1..6dc653e4ead 100644 --- a/src/vendorcode/google/chromeos/battery.c +++ b/src/vendorcode/google/chromeos/battery.c @@ -37,17 +37,13 @@ bool platform_is_low_battery_shutdown_needed(void) /* * Platform hooks for system shutdown due to critical battery levels. - * Provides visual feedback via the Lightbar/LEDs and logs the event - * to non-volatile storage before signaling to cut power. + * Logs the event to non-volatile storage before signaling to cut power. */ void platform_handle_emergency_low_battery(void) { if (!CONFIG(EC_GOOGLE_CHROMEEC)) return; - /* Visual alert: Set Lightbar to solid Red */ - google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00); - /* Record the event for post-mortem diagnostics (stored in CMOS/Flash) */ elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN); diff --git a/src/vendorcode/google/chromeos/splash_text.c b/src/vendorcode/google/chromeos/splash_text.c index bad33f3b49d..433e98dfbf7 100644 --- a/src/vendorcode/google/chromeos/splash_text.c +++ b/src/vendorcode/google/chromeos/splash_text.c @@ -6,22 +6,42 @@ #include #include +/* + * EC reserved 4% battery fuel as residue to avoid entering into critical battery. + * Therefore, while showing user visible battery SOC as part of low-battery or off-mode + * charging, need to consider this logic. Otherwise, user visible battery SOC would + * differ between FW and OS. + */ +#define MIN_BATTERY_THRESHOLD_FOR_CRITICAL_BOOT 4 + static bool get_battery_status_msg(char *msg, size_t msg_max) { uint32_t batt_pct; + uint32_t user_batt_pct; if (google_chromeec_read_batt_state_of_charge(&batt_pct)) { printk(BIOS_WARNING, "Failed to get battery level\n"); return false; } + /* + * Scale the raw EC battery percentage to user-visible percentage. + * If raw battery is below or equal to the threshold, user sees 0%. + */ + if (batt_pct <= MIN_BATTERY_THRESHOLD_FOR_CRITICAL_BOOT) { + user_batt_pct = 0; + } else { + user_batt_pct = ((batt_pct - MIN_BATTERY_THRESHOLD_FOR_CRITICAL_BOOT) * 100) / + (100 - MIN_BATTERY_THRESHOLD_FOR_CRITICAL_BOOT); + } + if (google_chromeec_is_critically_low_on_battery()) { - snprintf(msg, msg_max, "%u%%", batt_pct); + snprintf(msg, msg_max, "%u%%", user_batt_pct); } else if (google_chromeec_is_charger_present()) { - if (batt_pct == 100) + if (user_batt_pct == 100) snprintf(msg, msg_max, "Charged"); else - snprintf(msg, msg_max, "Charging: %u%%", batt_pct); + snprintf(msg, msg_max, "Charging: %u%%", user_batt_pct); } return true; diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/FirmwareVersionInfo.h new file mode 100644 index 00000000000..d3776cc8a37 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/FirmwareVersionInfo.h @@ -0,0 +1,55 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspProducerDataHeader.h new file mode 100644 index 00000000000..a6abd5a43e3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspProducerDataHeader.h @@ -0,0 +1,99 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2023 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspUpd.h new file mode 100644 index 00000000000..06413b819c4 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C564E /* 'NVLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C564E /* 'NVLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C564E /* 'NVLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspmUpd.h new file mode 100644 index 00000000000..a1a09dad348 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspmUpd.h @@ -0,0 +1,4593 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** FSP M Configuration +**/ +typedef struct { + +/** Offset 0x0060 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0061 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0062 - Reserved +**/ + UINT8 Reserved0[2]; + +/** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0068 - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x006C - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0070 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0074 - SerialIo Uart PowerGating + Select SerialIo Uart Powergating mode + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 SerialIoUartPowerGating; + +/** Offset 0x0075 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x0076 - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x0077 - DCI Clock Enable + Enable/Disable DCI clock in lowest power state + $EN_DIS +**/ + UINT8 DciClkEnable; + +/** Offset 0x0078 - Keep Early Trace + Trace is activated by default. When enable, keep early trace data and keep tracing, + may block s0ix.\n + When disabled will abandon trace data and stop tracing which allows enter s0ix\n + \n + noted:enable this option will not enable TraceHub; When probe is connected, keep + early trace will then be configured by tool, this option will not take effect. + $EN_DIS +**/ + UINT8 KeepEarlyTrace; + +/** Offset 0x0079 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x007A - Reserved +**/ + UINT8 Reserved1[6]; + +/** Offset 0x0080 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0088 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x008A - Reserved +**/ + UINT8 Reserved2[6]; + +/** Offset 0x0090 - Memory SPD Pointer per MC/CH/DIMM + Pointer to SPD data, only used when SpdAddressTable SPD Address is zero for this + MC/CH/DIMM +**/ + UINT64 MemorySpdPtr[32]; + +/** Offset 0x0190 - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x0192 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x019C - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x019E - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x01A0 - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x01A2 - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x01A4 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x01A6 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x01A8 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x01AA - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x01AC - Reserved +**/ + UINT8 Reserved3[16]; + +/** Offset 0x01BC - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x01CC - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x01DC - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x01EC - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x01FC - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x020C - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x021C - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x022C - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x023C - Reserved +**/ + UINT8 Reserved4[128]; + +/** Offset 0x02BC - LowerBasicMemTestSize + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 LowerBasicMemTestSize; + +/** Offset 0x02BD - EccGranularity32BEn + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 EccGranularity32BEn; + +/** Offset 0x02BE - EccCorrectionMode + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 EccCorrectionMode; + +/** Offset 0x02BF - CaVrefHigh + DDR5 CA Sweep High Vref Value for DDR5 OC +**/ + UINT8 CaVrefHigh; + +/** Offset 0x02C0 - CaVrefLow + DDR5 CA Sweep Low Vref Value for DDR5 OC +**/ + UINT8 CaVrefLow; + +/** Offset 0x02C1 - CsVrefHigh + DDR5 CS Sweep High Vref Value for DDR5 OC +**/ + UINT8 CsVrefHigh; + +/** Offset 0x02C2 - CsVrefLow + DDR5 CS Sweep Low Vref Value for DDR5 OC +**/ + UINT8 CsVrefLow; + +/** Offset 0x02C3 - DIMM DFE Tap1 Step Size + DIMM DFE Tap1 Step Size for DDR5 OC +**/ + UINT8 DFETap1StepSize; + +/** Offset 0x02C4 - DIMM DFE Tap2 Step Size + DIMM DFE Tap2 Step Size for DDR5 OC +**/ + UINT8 DFETap2StepSize; + +/** Offset 0x02C5 - Reserved +**/ + UINT8 Reserved5; + +/** Offset 0x02C6 - VDD2 override + VDD2 override for DDR5 OC; 0 - Auto +**/ + UINT16 Vdd2Mv; + +/** Offset 0x02C8 - tRAS + RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tRAS; + +/** Offset 0x02CA - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected != 0 (Standard Profile). +**/ + UINT16 tRCDtRP; + +/** Offset 0x02CC - tREFI + Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT32 tREFI; + +/** Offset 0x02D0 - tCL + CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tCL; + +/** Offset 0x02D2 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tCWL; + +/** Offset 0x02D4 - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tFAW; + +/** Offset 0x02D6 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tRFC; + +/** Offset 0x02D8 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tRRD; + +/** Offset 0x02DA - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected != 0 (Standard Profile). +**/ + UINT16 tRTP; + +/** Offset 0x02DC - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected != 0 (Standard Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT16 tWR; + +/** Offset 0x02DE - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + != 0 (Standard Profile). +**/ + UINT16 tWTR; + +/** Offset 0x02E0 - tWTR_S + tWTR_S value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tWTR_S; + +/** Offset 0x02E2 - tWTR_L + tWTR_L value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tWTR_L; + +/** Offset 0x02E4 - tCCD_L + tCCD_L value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L; + +/** Offset 0x02E6 - tRRD_S + tRRD_S value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tRRD_S; + +/** Offset 0x02E8 - tRRD_L + tRRD_L value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tRRD_L; + +/** Offset 0x02EA - tRFC4 + tRFC4 value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tRFC4; + +/** Offset 0x02EC - tRFC2 + tRFC2 value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tRFC2; + +/** Offset 0x02EE - tRFCpb + tRFCpb value for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tRFCpb; + +/** Offset 0x02F0 - tCCD_L_WR + Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same + bank groups, for XMP or Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L_WR; + +/** Offset 0x02F2 - Periodic COMP + Enable/disable Periodic Compensation + $EN_DIS +**/ + UINT8 EnPeriodicComp; + +/** Offset 0x02F3 - LPMode4 Support + LPMode4 Options + 0: Disable, 1:Enable, 2:Dynamic Threshold 2, 3:Dynamic Threshold 3 +**/ + UINT8 LpMode4; + +/** Offset 0x02F4 - LPMode Support + Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable), + Bit[2]: Enable Lpmode3 (Selfrefresh_enable) +**/ + UINT8 LpMode; + +/** Offset 0x02F5 - Opportunistic Read + Enables/Disable Opportunistic Read (Def= Enable) + $EN_DIS +**/ + UINT8 OpportunisticRead; + +/** Offset 0x02F6 - Cycle Bypass Support + Enables/Disable Cycle Bypass Support(Def=Disable) + $EN_DIS +**/ + UINT8 Disable2CycleBypass; + +/** Offset 0x02F7 - MRC OCSafeMode + OverClocking Safe Mode for tCL + $EN_DIS +**/ + UINT8 OCSafeMode; + +/** Offset 0x02F8 - DQ Vref Ctrl Offset + Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl + 0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4, + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8, + 9:+9, 10:+10, 11:+11, 12:+12 +**/ + UINT8 VrefCtlOffset; + +/** Offset 0x02F9 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x02FA - Mrc MustStaticSpdData Setting + Indicates MrcMustStaticSpdData setting: board-dependent + $EN_DIS +**/ + UINT16 MrcMustStaticSpdData; + +/** Offset 0x02FC - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x02FD - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x02FE - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x02FF - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x0300 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x0301 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x0302 - Reserved +**/ + UINT8 Reserved7[2]; + +/** Offset 0x0304 - Force MRC train on warm boot + Enable/Disable MRC training on warm boot. + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x0305 - Reserved +**/ + UINT8 Reserved8; + +/** Offset 0x0306 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x0308 - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x0309 - SAGV WP Mask + System Agent dynamic frequency workpoints that memory will be training at the enabled + frequencies. + 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 +**/ + UINT8 SaGvWpMask; + +/** Offset 0x030A - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x030E - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x0316 - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; + +/** Offset 0x0317 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0318 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x0319 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x031A - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x031B - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x031C - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x031D - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x031E - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x031F - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x0320 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x0321 - Interleaving mode of CCC pins + Disable/Enable Interleaving mode of CCC pins which depends on board routing. + $EN_DIS +**/ + UINT8 CccPinsInterleaved; + +/** Offset 0x0322 - Memory Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x0324 - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT16 Ratio; + +/** Offset 0x0326 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x0327 - RxVref Per-Bit Training + Enable/Disable RxVref Per-Bit Training + $EN_DIS +**/ + UINT8 RXVREFPERBIT; + +/** Offset 0x0328 - TXDQS DCC Training + Enables/Disable TXDQS DCC Training + $EN_DIS +**/ + UINT8 TXDQSDCC; + +/** Offset 0x0329 - Rx DQS Duty Cycle Correction + Enables/Disable Rx DQS Duty Cycle Correction + $EN_DIS +**/ + UINT8 RXDQSDCC; + +/** Offset 0x032A - Ch Hash Override + Select if Channel Hash setting values will be taken from input parameters or automatically + taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashOverride; + +/** Offset 0x032B - Voltage Readout + Enables/Disable Voltage Readout for VCCClk and PBias + $EN_DIS +**/ + UINT8 VoltageReadout; + +/** Offset 0x032C - DQS Rise/Fall + Enables/Disable DQS Rise/Fall + $EN_DIS +**/ + UINT8 DQSRF; + +/** Offset 0x032D - DQS Rise/Fall + Enables/Disable DQS Rise/Fall + $EN_DIS +**/ + UINT8 RDDQSODTT; + +/** Offset 0x032E - PreTraining + Enables/Disable PreTraining + $EN_DIS +**/ + UINT8 PRETRAIN; + +/** Offset 0x032F - DUNIT Configuration + Enables/Disable Dunit Configuration + $EN_DIS +**/ + UINT8 DUNITC; + +/** Offset 0x0330 - Functional Duty Cycle Correction for DDR5 CLK + Enable/Disable Functional Duty Cycle Correction for DDR5 CLK + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCCLK; + +/** Offset 0x0331 - Functional Duty Cycle Correction for DDR5 DQS + Enable/Disable Functional Duty Cycle Correction for DDR5 DQS + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQS; + +/** Offset 0x0332 +**/ + UINT8 FUNCDCCWCK; + +/** Offset 0x0333 - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x0334 - DQ/DQS Swizzle Training + Enable/Disable DQ/DQS Swizzle Training + $EN_DIS +**/ + UINT8 DQDQSSWZ; + +/** Offset 0x0335 - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x0336 - Functional Duty Cycle Correction for Data DQ + Enable/Disable Functional Duty Cycle Correction for Data DQ + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQ; + +/** Offset 0x0337 - SubCh Hash Override + Select if SubChannel Hash setting values will be taken from input parameters or + automatically taken from POR values depending on DRAM type detected. NOTE: ONLY + if Memory interleaved Mode + $EN_DIS +**/ + UINT8 SubChHashOverride; + +/** Offset 0x0338 - DDR5 Auto Precharge Enable + Auto Precharge Enable for DDR5: O=Auto, 1=Disable, 2=Enable + $EN_DIS +**/ + UINT8 Ddr5AutoPrechargeEnable; + +/** Offset 0x0339 - Lp5 SplitACT Enable + SplitACT enable for LP5 + 0:Auto, 1:Disable, 2:Enable +**/ + UINT8 Lp5SplitACTEnable; + +/** Offset 0x033A - CCC Half Frequency + CCC Half Frequency (CccGear4) Mode: 0 = Auto (Default), 1 = Disable, 2 = GroupGv0 + (SaGv0 only), 3 = GroupGv1 (Up to SaGv1), 4 = GroupGv2 (Up to SaGv2), 5 = GroupGv3 + (Up to SaGv3) + 0: Auto, 1: Disable, 2: GroupGv0, 3: GroupGv1, 4: GroupGv2, 5: GroupGv3 +**/ + UINT8 CccHalfFrequency; + +/** Offset 0x033B - DIMM Non-Target ODT Training + Enables/Disable DIMM Non-Target ODT Training + $EN_DIS +**/ + UINT8 DIMMNTODT; + +/** Offset 0x033C - Unmatched Rx Calibration + Enable/Disable Rx Unmatched Calibration + $EN_DIS +**/ + UINT8 RXUNMATCHEDCAL; + +/** Offset 0x033D - PPR Test Type + Deprecated +**/ + UINT8 PprTestType; + +/** Offset 0x033E - PPR Run Once + When Eanble, PPR will run only once and then is disabled at next training cycle + $EN_DIS +**/ + UINT8 PprRunOnce; + +/** Offset 0x033F - Reserved +**/ + UINT8 Reserved11[3]; + +/** Offset 0x0342 - PPR Repair Type + PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair + 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair +**/ + UINT8 PprRepairType; + +/** Offset 0x0343 - PPR Error Injection + When Eanble, PPR will inject bad rows during testing + $EN_DIS +**/ + UINT8 PprErrorInjection; + +/** Offset 0x0344 - Reserved +**/ + UINT8 Reserved12[2]; + +/** Offset 0x0346 - DIMM RX Offset + DIMM RX Offset Training: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DIMMRXOFFSET; + +/** Offset 0x0347 - Reserved +**/ + UINT8 Reserved13[7]; + +/** Offset 0x034E - Read Timing Centering Idle + Read Timing Centering Idle Training: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RDTCIDLE; + +/** Offset 0x034F - LVR Auto Trim + Enable/disable LVR Auto Trim + $EN_DIS +**/ + UINT8 LVRAUTOTRIM; + +/** Offset 0x0350 - Compensation Optimization + Enable/Disable Compensation Optimization + $EN_DIS +**/ + UINT8 OPTIMIZECOMP; + +/** Offset 0x0351 - Write DQ/DQS Retraining + Enable/Disable Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 WRTRETRAIN; + +/** Offset 0x0352 - DCC Phase Clk Calibration + Enable/disable DCC Phase Clk Calibration + $EN_DIS +**/ + UINT8 PHASECLKCAL; + +/** Offset 0x0353 - DCC Tline Clk Calibration + Enable/disable DCC Tline Clk Calibration + $EN_DIS +**/ + UINT8 TLINECLKCAL; + +/** Offset 0x0354 - DCC Tline Serializer Calibration + Enable/disable DCC PI Serializer Calibratio + $EN_DIS +**/ + UINT8 DCCPISERIALCAL; + +/** Offset 0x0355 - RDDQODTT + Enable/disable Read DQ ODT Training + $EN_DIS +**/ + UINT8 RDDQODTT; + +/** Offset 0x0356 - RDCTLET + Enable/disable Read CTLE Training + $EN_DIS +**/ + UINT8 RDCTLET; + +/** Offset 0x0357 - RxVref Pre EMPHASIS Training + Enable/Disable Pre EMPHASIS Training + $EN_DIS +**/ + UINT8 EMPHASIS; + +/** Offset 0x0358 - RX DQS VOC Centring Training + Enable/Disable RX DQS VOC Centring Training + $EN_DIS +**/ + UINT8 RXDQSVOCC; + +/** Offset 0x0359 - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x035A - LPDDR ODT RttWr + Initial RttWr for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttWr; + +/** Offset 0x035B - Retrain on Fast flow Failure + Restart MRC in Cold mode if SW MemTest fails during Fast flow. + $EN_DIS +**/ + UINT8 RetrainOnFastFail; + +/** Offset 0x035C - LPDDR ODT RttCa + Initial RttCa for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttCa; + +/** Offset 0x035D - DIMM DFE Training + Enable/Disable DIMM DFE Training + $EN_DIS +**/ + UINT8 WRTDIMMDFE; + +/** Offset 0x035E - DDR5 ODT Timing Config + Enable/Disable DDR5 ODT TIMING CONFIG + $EN_DIS +**/ + UINT8 DDR5ODTTIMING; + +/** Offset 0x035F - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0360 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0361 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0362 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0363 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0364 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0365 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0366 - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0367 - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x0368 - Unmatched Write Time Centering 1D + Enable/Disable Unmatched Write Time Centering 1D + $EN_DIS +**/ + UINT8 UNMATCHEDWRTC1D; + +/** Offset 0x0369 - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x036A - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x036B - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x036C - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x036D - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x036E - Reserved +**/ + UINT8 Reserved14; + +/** Offset 0x036F - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0370 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0371 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0372 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0373 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0374 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0375 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0376 - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x0377 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x0378 - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x0379 - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x037A - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x037B - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x037C - DLL DCC Calibration + Enables/Disable DLL DCC Calibration + $EN_DIS +**/ + UINT8 DLLDCC; + +/** Offset 0x037D - DLL BW Select Calibration + Enables/Disable DLL BW Select Calibration + $EN_DIS +**/ + UINT8 DLLBWSEL; + +/** Offset 0x037E - Ibecc + In-Band ECC Support + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x037F - Ibecc Ec Dis + This option enables or disables the Ibecc Control register Ec Dis field. Default + 0 = Disabled. + $EN_DIS +**/ + UINT8 IbeccEcDis; + +/** Offset 0x0380 - Reserved +**/ + UINT8 Reserved15[2]; + +/** Offset 0x0382 - LP5 DRAM voltage (VDD2H) in millivolts + 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. +**/ + UINT16 Vdd2HVoltage; + +/** Offset 0x0384 - LP5 DRAM voltage (VDD1) in millivolts + 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. +**/ + UINT16 Vdd1Voltage; + +/** Offset 0x0386 - LP5 DRAM voltage (VDD2L) in millivolts + 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. +**/ + UINT16 Vdd2LVoltage; + +/** Offset 0x0388 - VDDQ Voltage Override + Voltage is multiple of 5mV where 0 means Auto. +**/ + UINT16 VddqVoltage; + +/** Offset 0x038A - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x038B - MsHashEnable + Controller Hash Enable: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MsHashEnable; + +/** Offset 0x038C - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x038D - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x0395 - Reserved +**/ + UINT8 Reserved16; + +/** Offset 0x0396 - IbeccProtectedRegionBases + IBECC Protected Region Bases per IBECC instance +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x03A6 - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; + +/** Offset 0x03B6 - IbeccEccInjControl + Enables IBECC Error Injection + 0: No Error Injection, 1: Inject Correctable Error Address match, 3: Inject Correctable + Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7: Inject + Uncorrectable Error on insertion counter +**/ + UINT8 IbeccEccInjControl; + +/** Offset 0x03B7 - IbeccEccInjCount + Number of memory transactions between ECC error injection +**/ + UINT8 IbeccEccInjCount; + +/** Offset 0x03B8 - Reserved +**/ + UINT8 Reserved17[8]; + +/** Offset 0x03C0 - IbeccEccInjAddrBase + Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB +**/ + UINT32 IbeccEccInjAddrBase; + +/** Offset 0x03C4 - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x03C5 - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x03C6 - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x03C7 - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x03C8 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x03C9 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x03CA - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x03CB - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x03CC - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x03CD - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x03CE - Wck Pad DCC Calibration + Enable/disable Wck Pad DCC Calibration + $EN_DIS +**/ + UINT8 WCKPADDCCCAL; + +/** Offset 0x03CF - DCC PI Code LUT Calibration + Enable/Disable DCC PI Code LUT Calibration + $EN_DIS +**/ + UINT8 DCCPICODELUT; + +/** Offset 0x03D0 - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x03D1 - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x03D2 - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x03D3 - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x03D4 - CMD Drive Strength and Tx Equalization + Enable/Disable CMD Drive Strength and Tx Equalization + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x03D5 - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x03D6 - Read Vref Decap Training* + Enable/Disable Read Vref Decap Training* + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x03D7 - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x03D8 - Ref PI Calibration + Enable/Disable Ref PI Calibration + $EN_DIS +**/ + UINT8 REFPI; + +/** Offset 0x03D9 - VccClk FF Offset Correction + Enable/Disable VccClk FF Offset Correction + 0:Disable, 1:Enable +**/ + UINT8 VCCCLKFF; + +/** Offset 0x03DA - Data PI Linearity Calibration + Enable/Disable {Data PI Linearity Calibration + $EN_DIS +**/ + UINT8 DATAPILIN; + +/** Offset 0x03DB - Ddr5 Rx Cross-Talk Cancellation + Enable/Disable {Ddr5 Rx Cross-Talk Cancellation + $EN_DIS +**/ + UINT8 DDR5XTALK; + +/** Offset 0x03DC - Retrain On Working Channel + Enables/Disable Retrain On Working Channel feature + $EN_DIS +**/ + UINT8 RetrainToWorkingChannel; + +/** Offset 0x03DD - Row Press + Enables/Disable Row Press feature + $EN_DIS +**/ + UINT8 RowPressEn; + +/** Offset 0x03DE - DBI feature + Enables/Disable DBI feature + $EN_DIS +**/ + UINT8 DBI; + +/** Offset 0x03DF - DDR5 MR7 WICA support + Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment + $EN_DIS +**/ + UINT8 IsDdr5MR7WicaSupported; + +/** Offset 0x03E0 - Reserved +**/ + UINT8 Reserved18[2]; + +/** Offset 0x03E2 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x03E4 - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x03E5 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x03E6 - Allow Opp Ref Below Write Threhold + Allow opportunistic refreshes while we don't exit power down. + $EN_DIS +**/ + UINT8 AllowOppRefBelowWriteThrehold; + +/** Offset 0x03E7 - Write Threshold + Number of writes that can be accumulated while CKE is low before CKE is asserted. +**/ + UINT8 WriteThreshold; + +/** Offset 0x03E8 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x03E9 - Refresh Watermarks + Refresh Watermarks: 0-Low, 1-High (default) + 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) +**/ + UINT8 RefreshWm; + +/** Offset 0x03EA - Memory Slice Hash Mask + Memory Slice (Controller) Hash Mask when MsHashOverride=1. 0x0001=BIT6, 0x3FFF=BIT[19:6] +**/ + UINT16 MsHashMask; + +/** Offset 0x03EC - DRAM voltage (Vpp) in millivolts + 0=Platform Default (no override), 1800=1.8V, 2050=2.05V etc. +**/ + UINT16 VppVoltage; + +/** Offset 0x03EE - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x03EF - Bitmask of ranks that have CA bus terminated + LPDDR5: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is + terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x03F0 - MRC Safe Mode Override + SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode + override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] + Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] + Enable SaGv safe mode override +**/ + UINT8 SafeModeOverride; + +/** Offset 0x03F1 - Memory Slice Hash Override + Controller Hash Mask/LSB Override. 0=Use default, 1=Use MsHashMask and MsHashInterleaveBit + $EN_DIS +**/ + UINT8 MsHashOverride; + +/** Offset 0x03F2 - Memory Slice Hash Interleave Bit + Memory Slice (Controller) Hash LSB when MsHashOverride=1 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 MsHashInterleaveBit; + +/** Offset 0x03F3 - Reserved +**/ + UINT8 Reserved19[9]; + +/** Offset 0x03FC - DDR Phy Safe Mode Support + DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: + Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: + PLL Operation, DdrSafeMode[6]: Safe ODT +**/ + UINT32 DdrSafeMode; + +/** Offset 0x0400 - Mc Safe Mode Support + McSafeMode[0]: Reserved, McSafeMode[1]: OppSR +**/ + UINT8 McSafeMode; + +/** Offset 0x0401 - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x0402 - Tseg Retry Count + Tseg Retry count will increase based on TSEG Region Fail count + 0: Default, 1:3 +**/ + UINT8 RetryCount; + +/** Offset 0x0403 - Mrc Ppr Status + Get Mrc PPR Status after PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 MrcPprStatus; + +/** Offset 0x0404 - Tseg Memory Test Status + If enabled, PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 TsegMemoryTestStatus; + +/** Offset 0x0405 - Ppr Recovery Status Enable + 0: Disabled(Default), 1: Enabled. If enabled, PPR Recovery flow will get Trigger. + $EN_DIS +**/ + UINT8 PprRecoveryStatusEnable; + +/** Offset 0x0406 - Safe Loading Bios Enable State + 0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for + TSEG Region. + $EN_DIS +**/ + UINT8 SafeLoadingBiosEnableState; + +/** Offset 0x0407 - BDAT test type + When BdatEnable is set to TRUE, this option selects the type of data which will + be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 MrcBdatTestType; + +/** Offset 0x0408 - MrcBdatEnable + 0: Disabled(Default), 1: Enabled. This field enables the generation of the BIOS + DATA ACPI Tables: 0=FALSE, 1=TRUE. + $EN_DIS +**/ + UINT8 MrcBdatEnable; + +/** Offset 0x0409 - DisableMrcRetraining + 0: Disabled(Default), 1: Enabled. Enable/Disable DisableMrcRetraining + $EN_DIS +**/ + UINT8 DisableMrcRetraining; + +/** Offset 0x040A - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x040B - DdrOneDpc + DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 DdrOneDpc; + +/** Offset 0x040C - VccDdq Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VddqVoltageOverride; + +/** Offset 0x040E - VccIog Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccIogVoltageOverride; + +/** Offset 0x0410 - VccClk Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccClkVoltageOverride; + +/** Offset 0x0412 - ThrtCkeMinTmrLpddr + Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x0413 - Reserved +**/ + UINT8 Reserved20; + +/** Offset 0x0414 - Margin limit check L2 + Margin limit check L2 threshold: 100=Default +**/ + UINT16 MarginLimitL2; + +/** Offset 0x0416 - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x0417 - DRFM Blast Radius Configuration + Row Hammer DRFM Blast Radius Configuration determines number of victim rows around + aggressor row targeted to send the DRFM sequence to: 2=BlastRadius 2, 3=BlastRadius + 3, 4=BlastRadius 4 +**/ + UINT8 DrfmBrc; + +/** Offset 0x0418 - LP5 Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x0419 - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x041A - Time Measure + Time Measure: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x041B - DVFSQ Enabled + Enable/Disable DVFSQ + $EN_DIS +**/ + UINT8 DvfsqEnabled; + +/** Offset 0x041C - E-DVFSC Enabled + Eanble/Disable DVFSC + $EN_DIS +**/ + UINT8 DvfscEnabled; + +/** Offset 0x041D - Ddr5 Dca Training + Enable/Disable DDR5 Dca Training + $EN_DIS +**/ + UINT8 DCCDDR5READDCA; + +/** Offset 0x041E - PPR Entry Info + PPR Repair Info +**/ + UINT8 PprEntryInfo[16]; + +/** Offset 0x042E - PPR Run WCHMATS8 + Run WCHMATS8 in Post Package Repair flow +**/ + UINT8 PprRunWCHMATS8; + +/** Offset 0x042F - PPR Run Retention + Run Data Retention in Post Package Repair flow +**/ + UINT8 PprRunRetention; + +/** Offset 0x0430 - PPR Run XMarch + Run XMarch in Post Package Repair flow +**/ + UINT8 PprRunXMarch; + +/** Offset 0x0431 - PPR Run XMarchG + Run XMarchG in Post Package Repair flow +**/ + UINT8 PprRunXMarchG; + +/** Offset 0x0432 - PPR Run YMarchShort + Run YMarchShort in Post Package Repair flow +**/ + UINT8 PprRunYMarchShort; + +/** Offset 0x0433 - PPR Run YMarchLong + Run YMarchLong in Post Package Repair flow +**/ + UINT8 PprRunYMarchLong; + +/** Offset 0x0434 - PPR Run Mmrw + Run Mmrw in Post Package Repair flow +**/ + UINT8 PprRunMmrw; + +/** Offset 0x0435 - PPR Retry Limit + Sets a limit on the number of times Memory Testing will be retried after attempting + to repair using PPR. +**/ + UINT8 PprRetryLimit; + +/** Offset 0x0436 - PPR Test Disabled + Don't run any test in Post Package Repair flow +**/ + UINT8 PprTestDisabled; + +/** Offset 0x0437 - PPR Entry Address + PPR Repair Memory Address +**/ + UINT8 PprEntryAddress[16]; + +/** Offset 0x0447 - Reserved +**/ + UINT8 Reserved21[160]; + +/** Offset 0x04E7 - Rx Vref Offset Override + Override Rx Vref Offset setting +**/ + UINT8 RxVrefOffset; + +/** Offset 0x04E8 - Reserved +**/ + UINT8 Reserved22[12]; + +/** Offset 0x04F4 - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:Enable, 0x1:Disable, 0x2:Auto +**/ + UINT8 PwDownMode; + +/** Offset 0x04F5 - Reserved +**/ + UINT8 Reserved23; + +/** Offset 0x04F6 - Pwr Down Idle Timer + Default 0 = AUTO. Range is 30 to 2000(in us) +**/ + UINT16 PwDownIdleTimer; + +/** Offset 0x04F8 - Opportunistic Self Refresh IdleTimer + Default 0 = AUTO. Range is 500 to 10000(in us) +**/ + UINT16 OppSrefIdleTmr; + +/** Offset 0x04FA - Reserved +**/ + UINT8 Reserved24[8]; + +/** Offset 0x0502 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x0503 - Spd Address Table + Specify SPD Address table per MC/CH/DIMM. MemorySpdPtr will be used if SPD Address is 00 +**/ + UINT8 SpdAddressTable[32]; + +/** Offset 0x0523 - PCIE Resizable BAR Support + Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieResizableBarSupport; + +/** Offset 0x0524 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0525 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0526 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0527 - Reserved +**/ + UINT8 Reserved25[4]; + +/** Offset 0x052B - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x052C - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x052D - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x052E - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x0530 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0532 - Reserved +**/ + UINT8 Reserved26[10]; + +/** Offset 0x053C - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x0544 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0545 - Reserved +**/ + UINT8 Reserved27[3]; + +/** Offset 0x0548 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0550 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[7]; + +/** Offset 0x0557 - PCH Hda Disc Bt Off Enabled + Hda Disc Bt Off Enabled +**/ + UINT8 PchHdaDiscBtOffEnabled; + +/** Offset 0x0558 - PCH HDA Discrete BT Offload Ssp Link + Discrete BT Offload Ssp Link +**/ + UINT32 PchHdaDiscBtOffSspLink; + +/** Offset 0x055C - SSP Sclk Pin Muxing (N - SSP Number) + Determines SSP Sclk Pin muxing. See GPIOV2_*_MUXING_I2S*_SCLK +**/ + UINT32 PchHdaAudioLinkSspSclkPinMux[7]; + +/** Offset 0x0578 - SSP Sfmr Pin Muxing (N - SSP Number) + Determines SSP Sfmr Pin muxing. See GPIOV2_*_MUXING_I2S*_SFMR +**/ + UINT32 PchHdaAudioLinkSspSfmrPinMux[7]; + +/** Offset 0x0594 - SSP Txd Pin Muxing (N - SSP Number) + Determines SSP Txd Pin muxing. See GPIOV2_*_MUXING_I2S*_TXD +**/ + UINT32 PchHdaAudioLinkSspTxdPinMux[7]; + +/** Offset 0x05B0 - SSP Rxd Pin Muxing (N - SSP Number) + Determines SSP Rxd Pin muxing. See GPIOV2_*_MUXING_I2S*_RXD +**/ + UINT32 PchHdaAudioLinkSspRxdPinMux[7]; + +/** Offset 0x05CC - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[5]; + +/** Offset 0x05D1 - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x05D2 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x05D3 - Sndw Multilane enablement + SoundWire Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled, + 2: Three lines enabled, 3: Four Lines enabled. + $EN_DIS +**/ + UINT8 PchHdAudioSndwMultilaneEnable[2]; + +/** Offset 0x05D5 - Reserved +**/ + UINT8 Reserved28[3]; + +/** Offset 0x05D8 - SoundWire Clk Pin Muxing (N - SoundWire number) + Determines SoundWire Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_CLK* +**/ + UINT32 PchHdaAudioLinkMultilaneClkPinMux[2]; + +/** Offset 0x05E0 - SoundWire Multilane Data0 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA0* +**/ + UINT32 PchHdaAudioLinkMultilaneData0PinMux[2]; + +/** Offset 0x05E8 - SoundWire Multilane Data1 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA1* +**/ + UINT32 PchHdaAudioLinkMultilaneData1PinMux[2]; + +/** Offset 0x05F0 - SoundWire Multilane Data2 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA2* +**/ + UINT32 PchHdaAudioLinkMultilaneData2PinMux[2]; + +/** Offset 0x05F8 - SoundWire Multilane Data3 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA3* +**/ + UINT32 PchHdaAudioLinkMultilaneData3PinMux[2]; + +/** Offset 0x0600 - iDisplay Interface Select + iDisplay interface selection.\n + If SoundWire is selected or set to Disabled, the iDisplay Audio Codec will be disconnected. + 0: Disabled, 1: HD-Audio, 2: SoundWire +**/ + UINT8 IDispInterfaceSelect; + +/** Offset 0x0601 - Sndw Interface for Multilanes (N - SoundWire number) + iDisplay interface selection.\n + If SoundWire is selected or set to Disabled, the iDisplay Audio Codec will be disconnected. + 0: Sndw0, 1: Sndw1, 2: Sndw2, 3: Sndw3, 4: Sndw4, 5: Sndw5 +**/ + UINT8 PchHdAudioSndwMultilaneSndwInterface[2]; + +/** Offset 0x0603 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x0604 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT16 ResetWaitTimer; + +/** Offset 0x0606 - Reserved +**/ + UINT8 Reserved29[2]; + +/** Offset 0x0608 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT32 PchHdaSubSystemIds; + +/** Offset 0x060C - SoundWire clock source select + Select clock source for the SoundWire controllers. 0: XTAL, 1: Audio PLL. + $EN_DIS +**/ + UINT8 PchHdaSndwClockSourceSelect; + +/** Offset 0x060D - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x060E - Reserved +**/ + UINT8 Reserved30[26]; + +/** Offset 0x0628 - Usage type for ClkSrc + 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x0638 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x0648 - Reserved +**/ + UINT8 Reserved31[4]; + +/** Offset 0x064C - Clk Req GPIO Pin + Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. +**/ + UINT32 PcieClkReqGpioMux[16]; + +/** Offset 0x068C - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x0690 - Usage type for ClkSrc + 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PchPcieClkSrcUsage[16]; + +/** Offset 0x06A0 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PchPcieClkSrcClkReq[16]; + +/** Offset 0x06B0 - Reserved +**/ + UINT8 Reserved32[64]; + +/** Offset 0x06F0 - Enable PCH PCIE RP Mask + Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, + bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PchPcieRpEnableMask; + +/** Offset 0x06F4 - Reserved +**/ + UINT8 Reserved33[8]; + +/** Offset 0x06FC - Debug Interfaces + Debug Interfaces. BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT0 and + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x06FD - Reserved +**/ + UINT8 Reserved34[3]; + +/** Offset 0x0700 - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0704 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0705 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x0706 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0707 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0708 - Reserved +**/ + UINT8 Reserved35[4]; + +/** Offset 0x070C - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0710 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0711 - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0712 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x0718 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0719 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x071A - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x071D - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x071E - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x071F - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x0720 - Enable KT device + Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0721 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x0722 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0723 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0724 - HECI Communication + Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter + error state. + $EN_DIS +**/ + UINT8 HeciCommunication; + +/** Offset 0x0725 - HECI3 Interface Communication + Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication3; + +/** Offset 0x0726 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0727 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0728 - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x072A - Enable/Disable I2cPostcode + Enable (Default): Postcode via I2C, Disable: Postcode via Port80 + $EN_DIS +**/ + UINT8 I2cPostCodeEnable; + +/** Offset 0x072B - Reserved +**/ + UINT8 Reserved37[29]; + +/** Offset 0x0748 - FSPM Validation Pointer + Point to FSPM Validation configuration structure +**/ + UINT64 FspmValidationPtr; + +/** Offset 0x0750 - Extended BIOS Support + Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 ExtendedBiosDecodeRange; + +/** Offset 0x0751 - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x0752 - Reserved +**/ + UINT8 Reserved38[2]; + +/** Offset 0x0754 - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x0758 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; + +/** Offset 0x075C - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x075D - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x075E - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x075F - Reserved +**/ + UINT8 Reserved39; + +/** Offset 0x0760 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0762 - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0763 - Reserved +**/ + UINT8 Reserved40[5]; + +/** Offset 0x0768 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT64 RsvdSmbusAddressTablePtr; + +/** Offset 0x0770 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0771 - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x0772 - Row Hammer pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) +**/ + UINT8 Lfsr0Mask; + +/** Offset 0x0773 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0774 - Row Hammer pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x0775 - Row Hammer DRAM Refresh Management Mode + Row Hammer Adaptive Refresh Management Level: 0-RFM (default), 1-ARFMLevel A, 2-ARFMLevel + B, 3-ARFMLevel C, 4-Disable ARFM and RFM + 0: RFM, 1: ARFM Level A, 2: ARFM Level B, 3: ARFM Level C, 4: ARFM and RFM Disabled +**/ + UINT8 DramRfmMode; + +/** Offset 0x0776 - Row Hammer Targeted Row Refresh Mode + Row Hammer Targeted Row Refresh: 0-DRFM, 1-pTRR (default), 2-Disable DRFM and pTRR + 0: DRFM, 1: pTRR, 2: Targeted Row Refresh Disabled +**/ + UINT8 TargetedRowRefreshMode; + +/** Offset 0x0777 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x0778 - Reserved +**/ + UINT8 Reserved41[2]; + +/** Offset 0x077A - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x077C - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x077D +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x077E - Txt + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x077F - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x0780 - Reset Auxiliary content + Reset Auxiliary content, 0: Disabled, 1: Enabled + $EN_DIS +**/ + UINT8 ResetAux; + +/** Offset 0x0781 - TseEnable + Enable/Disable. 0: Disable, Enable/Disable Tse feature, 1: enable + $EN_DIS +**/ + UINT8 TseEnable; + +/** Offset 0x0782 - Enable or Disable TDX + Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager + (VMM)/hypervisor 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TdxEnable; + +/** Offset 0x0783 - Reserved +**/ + UINT8 Reserved42[5]; + +/** Offset 0x0788 - TdxActmModuleAddr + Base address of Tdx Actm module, used for launching the Actm +**/ + UINT64 TdxActmModuleAddr; + +/** Offset 0x0790 - TdxActmModuleSize + size of Tdx Actm module, used for launching the Actm +**/ + UINT32 TdxActmModuleSize; + +/** Offset 0x0794 - TdxSeamldrSvn + TdxSeamldrSvn +**/ + UINT8 TdxSeamldrSvn; + +/** Offset 0x0795 - MKTME Key-Id Bits Override Enable + TME_PREMEM_CONFIG Start + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x0796 - Reserved +**/ + UINT8 Reserved43[2]; + +/** Offset 0x0798 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x07A0 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x07A8 - Reserved +**/ + UINT8 Reserved44; + +/** Offset 0x07A9 - Enable or Disable TME + Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x07AA - Boot max frequency + Enable Boot Maximum Frequency in CPU strap. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BootMaxFrequency; + +/** Offset 0x07AB - Boot frequency + Select the performance state that the BIOS will set starting from reset vector. + 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x07AC - BIST on Reset + Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x07AD - Enable or Disable VMX + Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities + provided by Vanderpool Technology. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x07AE - Processor Early Power On Configuration FCLK setting + FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). + 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x07AF - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x07B0 - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x07B1 - Over clocking Lock + Lock Overclocking. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x07B2 - CPU ratio value + This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio + set by Hardware (HFM). Valid Range 0 to 63. +**/ + UINT8 CpuRatio; + +/** Offset 0x07B3 - Reserved +**/ + UINT8 Reserved45[3]; + +/** Offset 0x07B6 - DFD Enable + Enable or Disable DFD. 0: Disable, 1:Enable + $EN_DIS +**/ + UINT8 DfdEnable; + +/** Offset 0x07B7 - Reserved +**/ + UINT8 Reserved46; + +/** Offset 0x07B8 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x07BC - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x07C0 - Reserved +**/ + UINT8 Reserved47[3]; + +/** Offset 0x07C3 - SmmRelocationEnable Enable + Enable or Disable SmmRelocationEnable. 0: Disable, 1:Enable + $EN_DIS +**/ + UINT8 SmmRelocationEnable; + +/** Offset 0x07C4 - Reserved +**/ + UINT8 Reserved48[33]; + +/** Offset 0x07E5 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts. Default = 0h. +**/ + UINT8 TccActivationOffset; + +/** Offset 0x07E6 - Reserved +**/ + UINT8 Reserved49[2]; + +/** Offset 0x07E8 - Platform PL1 power + Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new PL1 value for the Package + RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range + 0 to 32767. +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x07EC - PlatformAtxTelemetryUnit Mode + Enable/Disable PlatformAtxTelemetryUnit Mode. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT32 PlatformAtxTelemetryUnit; + +/** Offset 0x07F0 - Reserved +**/ + UINT8 Reserved50[2]; + +/** Offset 0x07F2 - Enable or Disable Intel SpeedStep Technology + Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x07F3 - Reserved +**/ + UINT8 Reserved51; + +/** Offset 0x07F4 - Platform PL1 power + Short term Power Limit value for custom cTDP level. Units are 125 milliwatt. +**/ + UINT16 CustomPowerLimit1; + +/** Offset 0x07F6 - Platform PL1 power + Short term Power Limit value for custom cTDP level. Units are 125 milliwatt. +**/ + UINT16 CustomPowerLimit2; + +/** Offset 0x07F8 - Platform PL2 power + Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value + for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x07FC - Vsys Max System battery volatge + Vsys Max defined in 1/1000 increments. Range is 0-65535. For a 1.25 voltage, enter + 1250. Default =0xFF. +**/ + UINT16 VsysMax; + +/** Offset 0x07FE - ThETA Ibatt Feature + Enable or Disable ThETA Ibatt Feature. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ThETAIbattEnable; + +/** Offset 0x07FF - Reserved +**/ + UINT8 Reserved52; + +/** Offset 0x0800 - ISYS Current Limit L1 + This field indicated the current limitiation of L1. Indicate current limit for which + dependency is on AC/DC mode before PSYS.Units of measurements are 1/8 A +**/ + UINT16 IsysCurrentLimitL1; + +/** Offset 0x0802 - ISYS Current Limit L1 Tau + This Specifies the time window used to calculate average current for ISYS_L1. The + units of measuremnts are specified in PACKAGE_POWER_SKU[TIME_UNIT] +**/ + UINT8 IsysCurrentL1Tau; + +/** Offset 0x0803 - Reserved +**/ + UINT8 Reserved53; + +/** Offset 0x0804 - ISYS Current Limit L2 + This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit + for which dependency is on AC/DC mode before PSYS. Units of measurements are 1/8 A +**/ + UINT16 IsysCurrentLimitL2; + +/** Offset 0x0806 - ISYS Current Limit L1 Enable + This bits enables disables ISYS_CURRENT_LIMIT_L1 algorithm. It control loop based + on the system power source AC or DC mode. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 IsysCurrentLimitL1Enable; + +/** Offset 0x0807 - ISYS Current Limit L2 Enable + This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm. It control loop based + on the system power source AC or DC mode. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 IsysCurrentLimitL2Enable; + +/** Offset 0x0808 - Package PL4 boost configuration + Configure Power Limit 4 Boost in Watts. Valid Range 0 to 63000 in step size of 125 + mWatt. The value 0 means disable. +**/ + UINT16 PowerLimit4Boost; + +/** Offset 0x080A - Skin Temperature Target + Target temperature is limit to which the control mechanism is regulating.It is defined + in 1/2 C increments.Range is 0-255. Temperature Range is 0-122.5 C.0: Auto. +**/ + UINT8 SkinTargetTemp[3]; + +/** Offset 0x080D - Skin Control Temperature Enable MMIO + Enables the skin temperature control for MMIO register. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempControlEnable[3]; + +/** Offset 0x0810 - Skin Temperature Loop Gain + Sets the aggressiveness of control loop where 0 is graceful, favors performance + on expense of temperature overshoots and 7 is for aggressive, favors tight regulation + over performance. Range is 0-7.0: Auto. +**/ + UINT8 SkinControlLoopGain[3]; + +/** Offset 0x0813 - Skin Temperature Override Enable + When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding + sensor.. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempOverrideEnable[3]; + +/** Offset 0x0816 - Skin Temperature Minimum Performance Level + Minimum Performance level below which the STC limit will not throttle. 0 - all levels + of throttling allowed incl. survivability actions. 256 - no throttling allowed.0: Auto. +**/ + UINT8 SkinMinPerformanceLevel[3]; + +/** Offset 0x0819 - Skin Temperature Override + Allows SW to override the input temperature. Pcode will use this value instead of + the sensor temperature. EC control is not impacted. Units: 0.5C. Values are 0 to + 255 which represents 0C-122.5C range.0: Auto. +**/ + UINT8 SkinTempOverride[3]; + +/** Offset 0x081C - Skin Temperature Control Enable + Enables Skin Temperature Control Sensors Feature. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempControl; + +/** Offset 0x081D - AC or DC Power State + AC or DC power State; 0: DC; 1: AC + 0:DC, 1:AC +**/ + UINT8 AcDcPowerState; + +/** Offset 0x081E - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x081F - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x0820 - Configuration for boot TDP selection + Assured Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate Base Power (TDP) selection. + Deactivate option will set MSR to Nominal and MMIO to Zero. 0: Base Power (TDP) + Nominal; 1: Base Power (TDP) Down; 2: Base Power (TDP) Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x0821 - ConfigTdp mode settings Lock + Assured Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and + CONFIG_TDP_CONTROL. Note: When CTDP (Assured Power) Lock is enabled Custom ConfigTDP + Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. + 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x0822 - Load Configurable TDP SSDT + Enables Assured Power (cTDP) control via runtime ACPI BIOS methods. This 'BIOS only' + feature does not require EC or driver support. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x0823 - CustomTurboActivationRatio + Turbo Activation Ratio for custom cTDP level + $EN_DIS +**/ + UINT8 CustomTurboActivationRatio; + +/** Offset 0x0824 - CustomPowerLimit1Time + Short term Power Limit time window value for custom cTDP level. + $EN_DIS +**/ + UINT8 CustomPowerLimit1Time; + +/** Offset 0x0825 - PL1 Enable value + Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it + activates the PL1 value to be used by the processor to limit the average power + of given time window. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x0826 - PL1 timewindow + Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to + 128. 0 = default values. Indicates the time window over which Platform Processor + Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to + 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x0827 - PL2 Enable Value + Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS + will program the default values for Platform Power Limit 2. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x0828 - Package PL3 time window + Power Limit 3 Time Window value in Milli seconds. Indicates the time window over + which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves + the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, + 28, 32, 40, 48, 56, 64. +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x0829 - Package Long duration turbo mode time + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. Valid values(Unit + in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , + 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x082A - Reserved +**/ + UINT8 Reserved54[2]; + +/** Offset 0x082C - Package Long duration turbo mode power limit + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor + Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid + Range 0 to 32767. +**/ + UINT32 PowerLimit1; + +/** Offset 0x0830 - Package Short duration turbo mode power limit + Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor + Base Power (TDP). Processor applies control policies such that the package power + does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x0834 - Package PL3 power limit + Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value + must be between Max and Min Power Limits. Other SKUs: This value must be between + Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves + the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit3; + +/** Offset 0x0838 - Package PL4 power limit + Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based + on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767. +**/ + UINT32 PowerLimit4; + +/** Offset 0x083C - Short term Power Limit value for custom cTDP level 1 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x0840 - Long term Power Limit value for custom cTDP level 1 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x0844 - Enable Configurable TDP + Applies Assured Power (cTDP) initialization settings based on non-Assured Power + (cTDP) or Assured Power (cTDP). Default is 1: Applies to Assured Power (cTDP) ; + if 0 then applies non-Assured Power (cTDP) and BIOS will bypass Assured Power (cTDP) + initialization flow + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x0845 - Dual Tau Boost + Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W + sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 DualTauBoost; + +/** Offset 0x0846 - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 1:Enabled ; 0: Disabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x0847 - Package PL3 Duty Cycle + Specify the duty cycle in percentage that the CPU is required to maintain over the + configured time window. Range is 0-100. +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x0848 - Package PL3 Lock + Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled + PL3 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x0849 - Package PL4 Lock + Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled + PL4 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x084A - Short Duration Turbo Mode + Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program + the default values for Power Limit 2. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x084B - Response Mode + Enable/Disable Response Mode. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 ResponseMode; + +/** Offset 0x084C - Reserved +**/ + UINT8 Reserved55[280]; + +/** Offset 0x0964 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0968 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x096C - TxtDprMemorySize + Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize + , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x0970 - Reserved +**/ + UINT8 Reserved56[8]; + +/** Offset 0x0978 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x0980 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0988 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0990 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT64 ApStartupBase; + +/** Offset 0x0998 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT64 BiosAcmBase; + +/** Offset 0x09A0 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x09A4 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x09A8 - IsTPMPresence + IsTPMPresence default values +**/ + UINT32 IsTPMPresence; + +/** Offset 0x09AC - TXT CMOS Offset + CMOS Offset for TXT policy data. Default 0x2A +**/ + UINT8 CmosTxtOffset; + +/** Offset 0x09AD - Reserved +**/ + UINT8 Reserved57[3]; + +/** Offset 0x09B0 - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x09B1 - Platform Psys slope correction + PSYS Slope defined in 1/100 increments. 0 - Auto Specified in 1/100 increment + values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x09B2 - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x09B4 - Thermal Design Current current limit + TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current + Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, + [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT16 TdcCurrentLimit[6]; + +/** Offset 0x09C0 - AcLoadline + AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 AcLoadline[6]; + +/** Offset 0x09CC - DcLoadline + DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 DcLoadline[6]; + +/** Offset 0x09D8 - Power State 1 Threshold current + PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Ps1Threshold[6]; + +/** Offset 0x09E4 - Power State 2 Threshold current + PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Ps2Threshold[6]; + +/** Offset 0x09F0 - Power State 3 Threshold current + PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] + through [5] are Reserved. +**/ + UINT16 Ps3Threshold[6]; + +/** Offset 0x09FC - Imon offset correction + IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, + 127999]. For an offset of 25.348, enter 25348. 0: Auto. [0] for IA, [1] + for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT32 ImonOffset[6]; + +/** Offset 0x0A14 - Icc Max limit + Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous + current allowed at any given time. The value is represented in 1/4 A increments. + A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccMax[6]; + +/** Offset 0x0A20 - VR Fast Vmode VoltageLimit support + Voltage Regulator Fast VoltageLimit . +**/ + UINT16 VrVoltageLimit[6]; + +/** Offset 0x0A2C - Imon slope correction + IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter + 125. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 ImonSlope[6]; + +/** Offset 0x0A38 - Power State 3 enable/disable + PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Ps3Enable[6]; + +/** Offset 0x0A3E - Power State 4 enable/disable + PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Ps4Enable[6]; + +/** Offset 0x0A44 - Enable/Disable BIOS configuration of VR + VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + 0: Disable; 1: Enable. +**/ + UINT8 VrConfigEnable[6]; + +/** Offset 0x0A4A - Thermal Design Current enable/disable + Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, + [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT8 TdcEnable[6]; + +/** Offset 0x0A50 - Thermal Design Current Lock + Thermal Design Current Lock; 0: Disable; 1: Enable. [0] for IA, [1] for GT, + [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT8 TdcLock[6]; + +/** Offset 0x0A56 - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x0A5C - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x0A62 - Reserved +**/ + UINT8 Reserved58[2]; + +/** Offset 0x0A64 - Platform Psys offset correction + PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed + value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset + of 25.348, enter 25348. +**/ + UINT32 PsysOffset; + +/** Offset 0x0A68 - Thermal Design Current time window + Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] + for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT32 TdcTimeWindow[6]; + +/** Offset 0x0A80 - TDC Mode + TDC Mode based on IRMS supported bit from Mailbox. 0: iPL2; 1: Irms. [0] + for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved. +**/ + UINT8 TdcMode[6]; + +/** Offset 0x0A86 - Reserved +**/ + UINT8 Reserved59[12]; + +/** Offset 0x0A92 - VCC Demotion Shutdown Threshold + User configured time threshold in msec. Range is 0~255 msec. +**/ + UINT8 VccDemotionShutdownThreshold[6]; + +/** Offset 0x0A98 - Reserved +**/ + UINT8 Reserved60[12]; + +/** Offset 0x0AA4 - DLVR RFI Spread Spectrum Percentage + DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 10 = 4%. 0x00: 0% , 0x02: + 0.5%, 0x04: 1% , 0x08: 2% ,0x10: 4%; u3.2 value from 0% - 4%. +**/ + UINT8 DlvrSpreadSpectrumPercentage; + +/** Offset 0x0AA5 - DLVR RFI Enable + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DlvrRfiEnable; + +/** Offset 0x0AA6 - Pcore VR Hysteresis time window + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. +**/ + UINT8 PcoreHysteresisWindow; + +/** Offset 0x0AA7 - Ecore VR Hysteresis time window + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. +**/ + UINT8 EcoreHysteresisWindow; + +/** Offset 0x0AA8 - DLVR RFI Frequency + DLVR RFI Frequency in MHz. 0: 2227 MHz , 1: 2140MHZ. +**/ + UINT16 DlvrRfiFrequency; + +/** Offset 0x0AAA - DLVR PHASE_SSC Enable + Enable/Disable DLVR PHASE_SSC. 0: Disable. 1:Enable. + $EN_DIS +**/ + UINT8 VrPowerDeliveryDesign; + +/** Offset 0x0AAB - Vsys Critical + PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255. +**/ + UINT8 EnableVsysCritical; + +/** Offset 0x0AAC - Assertion Deglitch Mantissa + Assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchMantissa; + +/** Offset 0x0AAD - Assertion Deglitch Exponent + Assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchExponent; + +/** Offset 0x0AAE - De assertion Deglitch Mantissa + De assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchMantissa; + +/** Offset 0x0AAF - De assertion Deglitch Exponent + De assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchExponent; + +/** Offset 0x0AB0 - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x0ABC - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x0AC2 - Enable/Disable CEP + Control for enabling/disabling CEP (Current Excursion Protection). 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 CepEnable[6]; + +/** Offset 0x0AC8 - Enable/Disable SIRP + Control for enabling/disabling SIRP (SoC Iccmax Reactive Protection). 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 SirpEnable[6]; + +/** Offset 0x0ACE - Reserved +**/ + UINT8 Reserved61[2]; + +/** Offset 0x0AD0 - Vsys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 VsysFullScale; + +/** Offset 0x0AD4 - Vsys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 VsysCriticalThreshold; + +/** Offset 0x0AD8 - Psys Full Scale + Psys Full Scale, Range is 0-255000mV +**/ + UINT32 PsysFullScale; + +/** Offset 0x0ADC - Psys Critical Threshold + Psys Critical Threshold, Range is 0-255000mV +**/ + UINT32 PsysCriticalThreshold; + +/** Offset 0x0AE0 - Reserved +**/ + UINT8 Reserved62[68]; + +/** Offset 0x0B24 - IOE Debug Enable + Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock + is enabled + $EN_DIS +**/ + UINT8 IoeDebugEn; + +/** Offset 0x0B25 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x0B26 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0B27 - Pmc Privacy Consent + Enable/Disable Pmc Privacy Consent + $EN_DIS +**/ + UINT8 PmcPrivacyConsent; + +/** Offset 0x0B28 - Reserved +**/ + UINT8 Reserved63[39]; + +/** Offset 0x0B4F - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x0B50 - The policy for VTd driver behavior + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x0B51 - Reserved +**/ + UINT8 Reserved64[3]; + +/** Offset 0x0B54 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x0B58 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x0B7C - Reserved +**/ + UINT8 Reserved65[4]; + +/** Offset 0x0B80 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT64 MchBar; + +/** Offset 0x0B88 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT64 RegBar; + +/** Offset 0x0B90 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x0B92 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x0B94 - Temporary address for ApicLocalAddress + The reference code will use this as Temporary address space +**/ + UINT32 ApicLocalAddress; + +/** Offset 0x0B98 - Temporary address for EcExtraIoBase + The reference code will use this as Temporary address space +**/ + UINT16 EcExtraIoBase; + +/** Offset 0x0B9A - Temporary address for SioBaseAddress + The reference code will use this as Temporary address space +**/ + UINT16 SioBaseAddress; + +/** Offset 0x0B9C - Temporary CfgBar address for VMD + The reference code will use this as Temporary address space +**/ + UINT32 VmdCfgBarBar; + +/** Offset 0x0BA0 - System Agent SafBar + Address of System Agent SafBar +**/ + UINT64 SafBar; + +/** Offset 0x0BA8 - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x0BA9 - Reserved +**/ + UINT8 Reserved66[15]; + +/** Offset 0x0BB8 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x0BB9 - Reserved +**/ + UINT8 Reserved67[55]; + +/** Offset 0x0BF0 - StreamTracer Mode + Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended + when all groups in high verbosity are traced in 'red', Auto: StreamTracer size + 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in + med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB + 0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input +**/ + UINT32 StreamTracerMode; + +/** Offset 0x0BF4 +**/ + UINT32 StreamTracerSize; + +/** Offset 0x0BF8 - Enable/Disable CrashLog Device + Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable + $EN_DIS +**/ + UINT32 CpuCrashLogDevice; + +/** Offset 0x0BFC - Reserved +**/ + UINT8 Reserved68[4]; + +/** Offset 0x0C00 - StreamTracer physical address + StreamTracer physical address +**/ + UINT64 StreamTracerBase; + +/** Offset 0x0C08 - Temporary MemBar1 address for VMD + StreamTracer physical address +**/ + UINT32 VmdMemBar1Bar; + +/** Offset 0x0C0C - Temporary MemBar2 address for VMD + StreamTracer physical address +**/ + UINT32 VmdMemBar2Bar; + +/** Offset 0x0C10 - Skip override boot mode When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to + BOOT_WITH_FULL_CONFIGURATION in PEI memory init. + $EN_DIS +**/ + UINT8 SiSkipOverrideBootModeWhenFwUpdate; + +/** Offset 0x0C11 - Reserved +**/ + UINT8 Reserved69; + +/** Offset 0x0C12 - Static Content at 4GB Location + 0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, + 0x400:1GB, 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB + 0: No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, 0x400:1GB, + 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB +**/ + UINT16 StaticContentSizeAt4Gb; + +/** Offset 0x0C14 - Platform Debug Option + Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n + \n + Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n + \n + Enabled Trace power off: TraceHub is powergated, provide setting close to functional + low power state\n + \n + Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual +**/ + UINT8 PlatformDebugOption; + +/** Offset 0x0C15 - Reserved +**/ + UINT8 Reserved70[25]; + +/** Offset 0x0C2E - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0C2F - Reserved +**/ + UINT8 Reserved71; + +/** Offset 0x0C30 - HgSubSystemId + Hybrid Graphics SubSystemId +**/ + UINT16 HgSubSystemId; + +/** Offset 0x0C32 - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x0C33 - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x0C34 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0C35 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0C36 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0C37 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0C38 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0C39 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0C3A - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0C3B - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0C3C - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0C3D - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0C3E - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0C3F - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0C40 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0C41 - Oem T12 Dealy Override + Oem T12 Dealy Override. 0(Default)=Disable 1=Enable + $EN_DIS +**/ + UINT8 OemT12DelayOverride; + +/** Offset 0x0C42 - Reserved +**/ + UINT8 Reserved72[6]; + +/** Offset 0x0C48 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1) +**/ + UINT64 LMemBar; + +/** Offset 0x0C50 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT64 GttMmAdr; + +/** Offset 0x0C58 - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelay; + +/** Offset 0x0C5A - Enable/Disable Memory Bandwidth Compression + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 MemoryBandwidthCompression; + +/** Offset 0x0C5B - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0C5C - Selection of the primary display device + 0(Default)=AUTO, 1=IGFX, 2=Hybrid Graphics, 3=PCIe Graphics + 0:AUTO, 1:IGFX, 2:HG, 3:PCI +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0C5D - Internal Graphics Data Stolen Memory GSM2 + Size of memory preallocated for internal graphics GSM2. + 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, + 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation +**/ + UINT8 IGpuGsm2Size; + +/** Offset 0x0C5E - Reserved +**/ + UINT8 Reserved73[2]; + +/** Offset 0x0C60 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0C64 - Reserved +**/ + UINT8 Reserved74[4]; + +/** Offset 0x0C68 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 VbtPtr; + +/** Offset 0x0C70 - SOL Training Message Pointer + Points to SOL Message String +**/ + UINT64 VgaMessage; + +/** Offset 0x0C78 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0C79 - Control SOL VGA Initialition sequence + Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),, + BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, + 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During + MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5 + - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support) + 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA +**/ + UINT8 VgaInitControl; + +/** Offset 0x0C7A - SOL VGA Graphics Mode 12 LogoPixelHeight + Heigh of VGA Graphics Mode 12 Logo +**/ + UINT16 LogoPixelHeight; + +/** Offset 0x0C7C - SOL VGA Graphics Mode 12 LogoPixelWidth + Width of VGA Graphics Mode 12 Logo +**/ + UINT16 LogoPixelWidth; + +/** Offset 0x0C7E - SOL VGA Graphics Mode 12 Image X Position + X position of Image on Display +**/ + UINT16 LogoXPosition; + +/** Offset 0x0C80 - SOL VGA Graphics Mode 12 Image Pointer + Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for + 58Hx200W as example, +**/ + UINT64 VgaGraphicsMode12ImagePtr; + +/** Offset 0x0C88 - SOL VGA Graphics Mode 12 Image Y Position + Y position of Image on Display +**/ + UINT16 LogoYPosition; + +/** Offset 0x0C8A - TCSS Port USB4V2 80G Support + Enable/Disable TCSS USB4V2 80G Support if HW is 80G capable. + $EN_DIS +**/ + UINT8 Usb4v2Enable[3]; + +/** Offset 0x0C8D - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x0C8E - TCSS Port configuration + USBC Port configuration, Options are 0x0: Type-C connector, 0x1: DisplayPort connector, + 0x2: HDMI connector, 0x3: eDP connector, 0x0F: DISABLE, 0x10:DP Only, 0x11: No + PCIe, 0x12:Full Function + 0x0: Type-C connector, 0x1: DisplayPort connector, 0x2: HDMI connector, 0x3: eDP + connector, 0x0F: DISABLE, 0x10:DP_ONLY, 0x11: NO_PCIE, 0x12:FULL_FUN +**/ + UINT8 TcssCapPolicy[4]; + +/** Offset 0x0C92 - TCSS Port Platform Configuration + USBC Port Platform Configuration, 2 bits per port, TCP1 BIT[1:0]. 2'b00: Retimerless; + 2'b01: Retimer present; 2'b10: Redriver present. +**/ + UINT8 TcssPlatConf; + +/** Offset 0x0C93 - Reserved +**/ + UINT8 Reserved75[39]; + +/** Offset 0x0CBA - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x0CBB - SOC Trace Hub Mode + Enable/Disable SOC TraceHub + $EN_DIS +**/ + UINT8 SocTraceHubMode; + +/** Offset 0x0CBC - PCH Trace Hub Mode + Enable/Disable PCH TraceHub + $EN_DIS +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0CBD - Reserved +**/ + UINT8 Reserved76; + +/** Offset 0x0CBE - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg0Size; + +/** Offset 0x0CC0 - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg1Size; + +/** Offset 0x0CC2 - PCH Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg0Size; + +/** Offset 0x0CC4 - PCH Trace Hub Memory Region 1 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg1Size; + +/** Offset 0x0CC6 - AET Trace Hub Mode Select + Select AET to Trace Hub destination. + 0:SOC Trace Hub, 1:PCH Trace Hub +**/ + UINT8 AetTraceHubMode; + +/** Offset 0x0CC7 - BIOS trace destination + Select BIOS trace destination. + 0:SOC Trace Hub, 1:PCH Trace Hub +**/ + UINT8 BiosTraceSinkMode; + +/** Offset 0x0CC8 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, + 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, + 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT16 IgdDvmt50PreAlloc; + +/** Offset 0x0CCA - Internal Graphics + Expect 3 values from 0 to 2 + 2:AUTO, 1:Enable, 0:Disable +**/ + UINT8 InternalGraphics; + +/** Offset 0x0CCB - Reserved +**/ + UINT8 Reserved77[51]; + +/** Offset 0x0CFE - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0CFF - DMI ASPM Configuration + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x0D00 - Reserved +**/ + UINT8 Reserved78; + +/** Offset 0x0D01 - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): + Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x0D02 - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x0D03 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x0D04 - DMI Hw Eq Gen3 CoeffList Cm + DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 DmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x0D0C - DMI Hw Eq Gen3 CoeffList Cp + DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 DmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0D14 - DMI Hw Eq Gen4 CoeffList Cm + DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 DmiHwEqGen4CoeffListCm[8]; + +/** Offset 0x0D1C - DMI Hw Eq Gen4 CoeffList Cp + DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 DmiHwEqGen4CoeffListCp[8]; + +/** Offset 0x0D24 - Reserved +**/ + UINT8 Reserved79[64]; + +/** Offset 0x0D64 - L1SS State Control Policy + Choose the L1SS State Control Policy, Default = 0 + 0: Auto, 1: L1.2 +**/ + UINT8 DmiL1ssEnable; + +/** Offset 0x0D65 - Enable/Disable DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen4RtcoRtpoEnable; + +/** Offset 0x0D66 - Reserved +**/ + UINT8 Reserved80[82]; + +/** Offset 0x0DB8 - Asynchronous ODT + This option configures the Memory Controler Asynchronous ODT control + 0:Enabled, 1:Disabled +**/ + UINT8 AsyncOdtDis; + +/** Offset 0x0DB9 - DLL Weak Lock Support + Enables/Disable DLL Weak Lock Support + $EN_DIS +**/ + UINT8 WeaklockEn; + +/** Offset 0x0DBA - Reserved +**/ + UINT8 Reserved81[2]; + +/** Offset 0x0DBC - Rx DQS Delay Comp Support + Enables/Disable Rx DQS Delay Comp Support + $EN_DIS +**/ + UINT8 RxDqsDelayCompEn; + +/** Offset 0x0DBD - Mrc Failure On Unsupported Dimm + Enables/Disable Mrc Failure On Unsupported Dimm + $EN_DIS +**/ + UINT8 MrcFailureOnUnsupportedDimm; + +/** Offset 0x0DBE - TX VREF Override + Override for initial DDR5 TxVref value. 0=Auto, valid range 350-975 +**/ + UINT16 TxVrefOverride; + +/** Offset 0x0DC0 - Reserved +**/ + UINT8 Reserved82[4]; + +/** Offset 0x0DC4 - Fore Single Rank config + Enables/Disable Fore Single Rank config + $EN_DIS +**/ + UINT32 ForceSingleRank; + +/** Offset 0x0DC8 - DynamicMemoryBoost + Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is + an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. + $EN_DIS +**/ + UINT32 DynamicMemoryBoost; + +/** Offset 0x0DCC - RealtimeMemoryFrequency + Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected + is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. + $EN_DIS +**/ + UINT32 RealtimeMemoryFrequency; + +/** Offset 0x0DD0 - SelfRefresh IdleTimer + SelfRefresh IdleTimer, Default is 256 +**/ + UINT16 SrefCfgIdleTmr; + +/** Offset 0x0DD2 - MC Register Offset + Apply user offsets to select MC registers(Def=Disable) + $EN_DIS +**/ + UINT8 MCREGOFFSET; + +/** Offset 0x0DD3 - CA Vref Ctl Offset + Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref + 0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4, + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8, + 9:+9, 10:+10, 11:+11, 12:+12 +**/ + UINT8 CAVrefCtlOffset; + +/** Offset 0x0DD4 - Clk PI Code Offset + Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3] + 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, + 5:+5, 6:+6 +**/ + UINT8 ClkPiCodeOffset; + +/** Offset 0x0DD5 - RcvEn Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 RcvEnOffset; + +/** Offset 0x0DD6 - Rx Dqs Offset + Offset to be applied to DDRDATACHX_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 RxDqsOffset; + +/** Offset 0x0DD7 - Tx Dq Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 TxDqOffset; + +/** Offset 0x0DD8 - Tx Dqs Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 TxDqsOffset; + +/** Offset 0x0DD9 - Vref Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset + 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, + 5:+5, 6:+6 +**/ + UINT8 VrefOffset; + +/** Offset 0x0DDA - Controller mask + Controller mask to apply on parameter offset +**/ + UINT8 CntrlrMask; + +/** Offset 0x0DDB - Channel mask + Channel mask to apply on parameter offset +**/ + UINT8 ChMask; + +/** Offset 0x0DDC - tRRSG Delta + Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRSG; + +/** Offset 0x0DDD - tRRDG Delta + Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRDG; + +/** Offset 0x0DDE - tRRDR Delta + Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDR; + +/** Offset 0x0DDF - tRRDD Delta + Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDD; + +/** Offset 0x0DE0 - tWRSG Delta + Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRSG; + +/** Offset 0x0DE1 - tWRDG Delta + Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRDG; + +/** Offset 0x0DE2 - tWRDR Delta + Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDR; + +/** Offset 0x0DE3 - tWRDD Delta + Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDD; + +/** Offset 0x0DE4 - tWWSG Delta + Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWWSG; + +/** Offset 0x0DE5 - tWWDG Delta + Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed + TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta + range of [-127..127] +**/ + UINT8 tWWDG; + +/** Offset 0x0DE6 - tWWDR Delta + Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDR; + +/** Offset 0x0DE7 - tWWDD Delta + Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDD; + +/** Offset 0x0DE8 - tRWSG Delta + Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWSG; + +/** Offset 0x0DE9 - tRWDG Delta + Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWDG; + +/** Offset 0x0DEA - tRWDR Delta + Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDR; + +/** Offset 0x0DEB - tRWDD Delta + Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDD; + +/** Offset 0x0DEC - MRC Interpreter + Select CMOS location match of DD01 or Ctrl-Break key or force entry + 0:CMOS, 1:Break, 2:Force +**/ + UINT8 Interpreter; + +/** Offset 0x0DED - ODT mode + ODT mode + 0:Default, 1:Vtt, 2:Vddq, 3:Vss, 4:Max +**/ + UINT8 IoOdtMode; + +/** Offset 0x0DEE - PerBankRefresh + Control of Per Bank Refresh feature for LPDDR DRAMs + $EN_DIS +**/ + UINT8 PerBankRefresh; + +/** Offset 0x0DEF - Mimic WC display pattern in IPQ + Using for Disable/Enable Mimic WC display pattern in IPQ: 0:Disable, 1:Enable 1 + ACT resources usage, 3:Enable 2 ACT resources usage, 3:Enable 3 ACT resources usage,0xf: + Enable 4 ACT resources usage + 1:1, 3:3, 0xf:0xf, 0:Auto +**/ + UINT8 MimicWcDisaplayInIpq; + +/** Offset 0x0DF0 - Fake SAGV + Fake SAGV: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT8 FakeSagv; + +/** Offset 0x0DF1 - Board Stack Up + Board Stack Up: 0=Typical, 1=Freq Limited + 0:Typical, 1:Freq Limited +**/ + UINT8 BoardStackUp; + +/** Offset 0x0DF2 - PPR ForceRepair + When Eanble, PPR will force repair some rows many times (90) + $EN_DIS +**/ + UINT8 PprForceRepair; + +/** Offset 0x0DF3 - Board Topology + Board Topology: 0=Daisy Chain, 1=Tee. + 0:Daisy Chain, 1:Tee +**/ + UINT8 BoardTopology; + +/** Offset 0x0DF4 - SubCh Hash Interleaved Bit + Select the MC Enhanced Channel interleave bit, to set different address bit for + sub channel selection than bit-6 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 SubChHashInterleaveBit; + +/** Offset 0x0DF5 - Single VDD2 Rail + LP5x VDD2 rail: 0: Dual rail (E-DVFSC is possible), 1: Single rail(No E-DVFSC; VDD2L == VDD2H) + $EN_DIS +**/ + UINT8 SingleVdd2Rail; + +/** Offset 0x0DF6 - SubCh Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x834 +**/ + UINT16 SubChHashMask; + +/** Offset 0x0DF8 - Use 1.5 Read Postamble + Enable using 1.5 tCK Read Postamble for higher frequencies: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 Use1p5ReadPostamble; + +/** Offset 0x0DF9 - Reserved +**/ + UINT8 Reserved83[3]; + +/** Offset 0x0DFC - Disable Zq + Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled + $EN_DIS +**/ + UINT32 DisableZq; + +/** Offset 0x0E00 - Replicate SAGV + Replicate SAGV: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT8 ReplicateSagv; + +/** Offset 0x0E01 - Reserved +**/ + UINT8 Reserved84; + +/** Offset 0x0E02 - Control MC/PMA telemetry + Control MC/PMA telemetry: 0: Default, 1: Enable, 2: Disable + 0: Default, 1: Enable, 2: Disable +**/ + UINT8 TelemetryControl; + +/** Offset 0x0E03 - PHclk\Qclk SPINE gating Control + PHclk\Qclk SPINE gating Control: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT8 SpineAndPhclkGateControl; + +/** Offset 0x0E04 - SpineGating per lpmode + SpineGatePerLpmode[0]:Lpmode0.5, SpineGatePerLpmode[1]:Lpmode2, SpineGatePerLpmode[2]:Lpmode3, + SpineGatePerLpmode[3]:Lpmode4 +**/ + UINT8 SpineGatePerLpmode; + +/** Offset 0x0E05 - PhClkGating control per lpmode + PhclkGatePerLpmode[0]:Lpmode0.5, PhclkGatePerLpmode[1]:Lpmode1, PhclkGatePerLpmode[2]:Lpmode2, + PhclkGatePerLpmode[3]:Lpmode3, PhclkGatePerLpmode[4]:Lpmode4 +**/ + UINT8 PhclkGatePerLpmode; + +/** Offset 0x0E06 - DFI Control after cold boot + Disable Switch DFI Control to MC after cold boot: 0(Default)=switch DFI to MC, 1=Keep + with PHY/MPTU + $EN_DIS +**/ + UINT8 DisableSwitchDfiToMc; + +/** Offset 0x0E07 - Channel to CKD QCK Mapping + Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 ChannelToCkdQckMapping[8]; + +/** Offset 0x0E0F - DDRIO Clock to CKD DIMM + Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 PhyClockToCkdDimm[8]; + +/** Offset 0x0E17 - CKD Address Table + Specify CKD Address table for all DIMMs +**/ + UINT8 CkdAddressTable[16]; + +/** Offset 0x0E27 - VIEW Pin Calibration + VIEW Pin Calibration Training: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 VIEWPINCAL; + +/** Offset 0x0E28 - Write Equalization Training + Write Equalization Training: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 WREQT; + +/** Offset 0x0E29 - Reserved +**/ + UINT8 Reserved85[2]; + +/** Offset 0x0E2B - Force CKD Bypass Mode + Force CKD in Bypass Mode if CKD DIMM is detected: 0 = Single PLL mode, 1 = Bypass mode. + $EN_DIS +**/ + UINT8 ForceCkdBypass; + +/** Offset 0x0E2C - Reserved +**/ + UINT8 Reserved86[499]; + +/** Offset 0x101F - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x1020 - Reserved +**/ + UINT8 Reserved87; + +/** Offset 0x1021 - Granular Ratio Override + Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 GranularRatioOverride; + +/** Offset 0x1022 - Reserved +**/ + UINT8 Reserved88[4]; + +/** Offset 0x1026 - IA Atom PLL Voltage Offset + PLL Voltage Offset, Range 0-15. Units are in 17.5mV. Default is 0. This control + can be used to increase the range of this domain frequency in extreme overclocking + conditions. +**/ + UINT8 IaAtomPllVoltageOffset; + +/** Offset 0x1027 - Reserved +**/ + UINT8 Reserved89[2]; + +/** Offset 0x1029 - Core Operating Point Reporting + Enables Core Operating point reporting. 0: Disable; 1: Enable + 0:Disable, 1:Enable +**/ + UINT8 CoreOpPointReportingEn; + +/** Offset 0x102A - Reserved +**/ + UINT8 Reserved90[18]; + +/** Offset 0x103C - CPU D2D Ratio + Set CPU D2D Ratio from Range 15 to 40. 0 indicates no setting +**/ + UINT8 CpuD2dRatio; + +/** Offset 0x103D - CPU DLVR Mode + Select Core(s) and RING DLVR Mode +**/ + UINT8 CpuDlvrMode; + +/** Offset 0x103E - Reserved +**/ + UINT8 Reserved91; + +/** Offset 0x103F - Force Pcore Residency + Enable/Disable Force Pcore Residency + $EN_DIS +**/ + UINT8 ForcePcoreResidency; + +/** Offset 0x1040 - VR Limit Bypass + Enable/Disable VR Limit Bypass + $EN_DIS +**/ + UINT8 VrLimitBypass; + +/** Offset 0x1041 - Reserved +**/ + UINT8 Reserved92[33]; + +/** Offset 0x1062 - VCCSA Boot Voltage + Select VCCSA boot voltage between Nominal and High Voltage(up to 1.2/1.3V). VCCSA + boot Voltage - the default voltage is Nominal, to support the high voltage, BIOS + can program the EPOC2 bits to bump up voltage to up to 1.2/1.3V. 0 - Nominal. + 1 - High Voltage(up to 1.2/1.3V) +**/ + UINT8 VccsaBootVoltageSel; + +/** Offset 0x1063 - CPU BGREF Mode + Select CPU Bandgap Reference Mode between Normal and Bandgap Bypassed. CPU Bandgap + Reference Mode - the default voltage is Normal. +**/ + UINT8 CpuBandgapRefMode; + +/** Offset 0x1064 - VCCIA Boot Voltage + Select VCCIA boot voltage between Nominal and High Voltage. VCCIA boot Voltage - + the default voltage is Nominal, to support the high voltage, BIOS can program VCCIA + boot voltage higher than 1.65v (max 2.01v)) +**/ + UINT8 VcciaBootVoltageSel; + +/** Offset 0x1065 - Reserved +**/ + UINT8 Reserved93[32]; + +/** Offset 0x1085 - IA ICC Unlimited Mode + Enable/Disable IA Unlimited ICCMAX. When Enabled, IA VR ICCMAX value is set to max + ICC current 512A. + $EN_DIS +**/ + UINT8 IaIccUnlimitedMode; + +/** Offset 0x1086 - IA ICC Max Current Limit Override + IA Voltage Regulator Current Limit (Icc Max). This value represents the Maximum + instantaneous current allowed at any given time. The value is represented in 1/4 + A increments. A value of 400 = 100A. Range is 0 to 4096. Uses OC mailbox command 0x17 +**/ + UINT16 IaIccMax; + +/** Offset 0x1088 - GT ICC Unlimited Mode + Enable/Disable GT Unlimited ICCMAX. When Enabled, GT VR ICCMAX value is set to max + ICC current 512A. + $EN_DIS +**/ + UINT8 GtIccUnlimitedMode; + +/** Offset 0x1089 - Reserved +**/ + UINT8 Reserved94; + +/** Offset 0x108A - GT ICC Max Current Limit Override + GT Voltage Regulator Current Limit (Icc Max). This value represents the Maximum + instantaneous current allowed at any given time. The value is represented in 1/4 + A increments. A value of 400 = 100A. Range is 0 to 4096. Uses OC mailbox command 0x17 +**/ + UINT16 GtIccMax; + +/** Offset 0x108C - SA ICC Unlimited Mode + Enable/Disable SA Unlimited ICCMAX. When Enabled, SA VR ICCMAX value is set to max + ICC current 512A. + $EN_DIS +**/ + UINT8 SaIccUnlimitedMode; + +/** Offset 0x108D - Reserved +**/ + UINT8 Reserved95; + +/** Offset 0x108E - SA ICC Max Current Limit Override + SA Voltage Regulator Current Limit (Icc Max). This value represents the Maximum + instantaneous current allowed at any given time. The value is represented in 1/4 + A increments. A value of 400 = 100A. Range is 0 to 4096. Uses OC mailbox command 0x17 +**/ + UINT16 SaIccMax; + +/** Offset 0x1090 - Reserved +**/ + UINT8 Reserved96; + +/** Offset 0x1091 - OC TVB + This control will allow user to modify and program new parameters for temperature + thresholds T0, T1 and delta DownBins for temp thresholds T0 and T1 + $EN_DIS +**/ + UINT8 OcTvb; + +/** Offset 0x1092 - P-core TVB Temp Threshold T0 + For Pcores Running ABOVE this temperature (in degrees C) will clip delta Down Bins + for Threshold 0 from the resolved OC Ratio +**/ + UINT8 PcoreTvbTempThreshold0[2]; + +/** Offset 0x1094 - P-core TVB Temp Threshold T1 + For Pcores Running ABOVE this temperature (in degrees C) will clip delta Down Bins + for Threshold 0 from the resolved OC Ratio +**/ + UINT8 PcoreTvbTempThreshold1[2]; + +/** Offset 0x1096 - E-core TVB Temp Threshold T0 + For Pcores Running ABOVE this temperature (in degrees C) will clip delta Down Bins + for Threshold 0 from the resolved OC Ratio +**/ + UINT8 EcoreTvbTempThreshold0[2]; + +/** Offset 0x1098 - E-core TVB Temp Threshold T1 + For Pcores Running ABOVE this temperature (in degrees C) will clip delta Down Bins + for Threshold 0 from the resolved OC Ratio +**/ + UINT8 EcoreTvbTempThreshold1[2]; + +/** Offset 0x109A - Reserved +**/ + UINT8 Reserved97[120]; + +/** Offset 0x1112 - ProcessVmaxLimit + Disabling Process Vmax Limit will allow user to set any voltage +**/ + UINT8 ProcessVmaxLimit; + +/** Offset 0x1113 - CorePllCurrentRefTuningOffset + Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllCurrentRefTuningOffset; + +/** Offset 0x1114 - RingPllCurrentRefTuningOffset + Ring PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllCurrentRefTuningOffset; + +/** Offset 0x1115 - IaAtomPllCurrentRefTuningOffset + IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 IaAtomPllCurrentRefTuningOffset; + +/** Offset 0x1116 - CoreMinRatio + equest Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default + 0 indicates no request +**/ + UINT8 CoreMinRatio; + +/** Offset 0x1117 - CoreMiNegativeTemperatureReportingnRatio + Negative Temperature Reporting Enable. 0: Disable, 1: enable +**/ + UINT8 NegativeTemperatureReporting; + +/** Offset 0x1118 - PcorePowerDensityThrottle + Power Density Throttle control allows user to disable P-core +**/ + UINT8 PcorePowerDensityThrottle; + +/** Offset 0x1119 - EcorePowerDensityThrottle + Power Density Throttle control allows user to disable P-core +**/ + UINT8 EcorePowerDensityThrottle; + +/** Offset 0x111A - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x111B - UnderVolt Protection + When UnderVolt Protection is enabled, user will be not be able to program under + voltage in OS runtime. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 UnderVoltProtection; + +/** Offset 0x111C - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x111D - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x111E - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x111F - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x1120 - Reserved +**/ + UINT8 Reserved98[15]; + +/** Offset 0x112F - Core VF Configuration Scope + Allows both all-core VF curve or per-core VF curve configuration; 0: All-core; + 1: Per-core. + 0:All-core, 1:Per-core +**/ + UINT8 CoreVfConfigScope; + +/** Offset 0x1130 - Per-core VF Offset + Array used to specifies the selected Core Offset Voltage. This voltage is specified + in millivolts. +**/ + UINT16 PerCoreVoltageOffset[8]; + +/** Offset 0x1140 - C Die for Core, Atom and Ring FLL Overclock Mode + Select FLL Mode Value from 0 to 3. 0 = no overclocking, 1 = ratio overclocking with + nominal (0.5-1x) reference clock frequency, 2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 3 = BCLK overclocking with extreme elevated (3-5x) + reference clock frequency and ratio limited to 63. +**/ + UINT8 FllOverclockMode; + +/** Offset 0x1141 - Reserved +**/ + UINT8 Reserved99[535]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH2_UPD FspmArchUpd; + +/** Offset 0x0060 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x1358 +**/ + UINT8 TerminatorReserved[6]; + +/** Offset 0x135E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspsUpd.h new file mode 100644 index 00000000000..4882bcb624b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/FspsUpd.h @@ -0,0 +1,3799 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** FSP S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - BgpdtHash[6] + BgpdtHash values +**/ + UINT64 BgpdtHash[6]; + +/** Offset 0x0070 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x0074 - Reserved +**/ + UINT8 Reserved0[4]; + +/** Offset 0x0078 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x0080 - EcProvisionEav + EcProvisionEav function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8 + *ReturnValue); @endcode +**/ + UINT64 EcProvisionEav; + +/** Offset 0x0088 - EcBiosGuardCmdLock + EcBiosGuardCmdLock function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode +**/ + UINT64 EcBiosGuardCmdLock; + +/** Offset 0x0090 - PCH eSPI Host and Device BME enabled + PCH eSPI Host and Device BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeHostDeviceEnabled; + +/** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x0092 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x0093 - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0094 - Reserved +**/ + UINT8 Reserved1[4]; + +/** Offset 0x0098 - PCH eSPI PmHAE + $EN_DIS +**/ + UINT8 PchEspiPmHAE; + +/** Offset 0x0099 - PCH eSPI NmiEnableCs1 + Set this bit to enable eSPI NMI VW events to be processed by the SOC + $EN_DIS +**/ + UINT8 PchEspiNmiEnableCs1; + +/** Offset 0x009A - Reserved +**/ + UINT8 Reserved2[6]; + +/** Offset 0x00A0 - CpuBistData + Pointer CPU BIST Data +**/ + UINT64 CpuBistData; + +/** Offset 0x00A8 - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT64 CpuMpPpi; + +/** Offset 0x00B0 - AC Split Lock + AC Split Lock; 0: disable, 1: enable + $EN_DIS +**/ + UINT8 AcSplitLock; + +/** Offset 0x00B1 - #GP Fault UC Lock + Enable or Disable GP Fault Exception (GP#). When enabled, this will assert an GP# + when encountering a Lock to un-cacheable memory before the bus is locked.; 0: disable, 1: enable + $EN_DIS +**/ + UINT8 GpfaultUcLock; + +/** Offset 0x00B2 - Enable TCC Mode + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 TccMode; + +/** Offset 0x00B3 - Reserved +**/ + UINT8 Reserved3[229]; + +/** Offset 0x0198 - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x0199 - Reserved +**/ + UINT8 Reserved4[3]; + +/** Offset 0x019C - StreamTracer Mode + Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended + when all groups in high verbosity are traced in 'red', Auto: StreamTracer size + 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in + med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB + 0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input +**/ + UINT32 StreamTracerMode; + +/** Offset 0x01A0 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT64 MicrocodeRegionBase; + +/** Offset 0x01A8 - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT64 MicrocodeRegionSize; + +/** Offset 0x01B0 - Enable or Disable TXT + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x01B1 - PpinSupport to view Protected Processor Inventory Number + PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn + off this feature. When 'PPIN Enable Mode' is selected, this shows second option + where feature can be enabled based on EOM (End of Manufacturing) flag or it is + always enabled + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x01B2 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x01B3 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x01C3 - Enable or Disable Intel SpeedStep Technology + Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x01C4 - Enable or Disable Energy Efficient P-state + Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access + to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support + for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS + MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is + supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x01C5 - Enable or Disable Energy Efficient Turbo + Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically + lower the turbo frequency to increase efficiency. Recommended only to disable in + overclocking situations where turbo frequency must remain constant. Otherwise, + leave enabled. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x01C6 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x01C7 - Enable or Disable CPU power states (C-states) + Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not + 100% utilized. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x01C8 - Configure C-State Configuration Lock + Configure MSR to CFG Lock bit. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x01C9 - Enable or Disable Package Cstate Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x01CA - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x01CB - Set the Max Pkg Cstate + Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. + Auto: Initializes to deepest available Package C State Limit. Valid values 0 - + C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - + CPU Default, 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x01CC - ForcePr Demotion Algorithm configuration + ForcePr Demotion Algorithm configuration. 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 ForcePrDemotion; + +/** Offset 0x01CD - VrAlert Demotion Algorithm configuration + VrAlert Demotion Algorithm configuration. 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 VrAlertDemotion; + +/** Offset 0x01CE - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: + Round robin; 2: Hash vector; 7: No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x01CF - Turbo Mode + Enable/Disable processor Turbo Mode. 0:disable, 1: Enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x01D0 - Power Floor PCIe Gen Downgrade + SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0: + Disable: Reduction in PCIe gen speed will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorPcieGenDowngrade; + +/** Offset 0x01D1 - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x01F9 - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table. Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x01FA - Max P-State Ratio + Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x01FB - Boot frequency + Select the performance state that the BIOS will set starting from reset vector. + 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x01FC - Turbo Ratio Limit Ratio array + Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max + is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio + Limit Ratio0 must be greater than or equal all other ratio values. If this value + is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio + Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit + Ratio1 must be <= to Turbo Ratio Limit Ratio0~6. +**/ + UINT8 TurboRatioLimitRatio[8]; + +/** Offset 0x0204 - ATOM Turbo Ratio Limit Ratio array + Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective + of the core extension mode), the core range is defined in E-core Turbo Ratio Limit + CoreCount0-7. +**/ + UINT8 AtomTurboRatioLimitRatio[8]; + +/** Offset 0x020C - ATOM Turbo Ratio Limit Num Core array + Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo + ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry + is ignored. +**/ + UINT8 AtomTurboRatioLimitNumCore[8]; + +/** Offset 0x0214 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x0215 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x0216 - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x0217 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x0218 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x0219 - Resource Priority Feature + Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 EnableRp; + +/** Offset 0x021A - Enable or Disable HWP + Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the + CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: + Enable; + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x021B - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x021C - Enable or Disable HwP Autonomous Per Core P State OS control + Disable Autonomous PCPS Autonomous will request the same value for all cores all + the time. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x021D - Enable or Disable HwP Autonomous EPP Grouping + Enable EPP grouping Autonomous will request the same values for all cores with same + EPP. Disable EPP grouping autonomous will not necessarily request same values for + all cores with same EPP. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x021E - Dynamic Efficiency Control + Enable or Disable SoC to control energy efficiency targets autonomously, regardless + of EPP, EPB and other SW inputs. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableDynamicEfficiencyControl; + +/** Offset 0x021F - Power Floor Managment for SOC + Option to disable Power Floor Managment for SOC. Disabling this might effectively + raise power floor of the SoC and may lead to stability issues. 0: Disable, 1: + Enable + $EN_DIS +**/ + UINT8 PowerFloorManagement; + +/** Offset 0x0220 - Power Floor Disaplay Disconnect + SoC can disconnect secondary/external display to lower SoC floor power (Default + enabled). 0: Disable: Display disconnect will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorDisplayDisconnect; + +/** Offset 0x0221 - Reserved +**/ + UINT8 Reserved5[5]; + +/** Offset 0x0226 - Memory size per thread allocated for Processor Trace + Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment + and size in bytes per thread, from 4KB to 128MB.\n + 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, + 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M +**/ + UINT8 ProcessorTraceMemSize; + +/** Offset 0x0227 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x0228 - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x0229 - Enable or Disable Monitor /MWAIT instructions + Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner + should not set in MWAIT Loop. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x022A - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x022B - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x022C - Processor trace enabled for Bsp only or all cores + Processor trace enabled for Bsp only or all cores; 0: all cores; 1: Bsp only. + 0: all cores, 1: Bsp only +**/ + UINT8 ProcessorTraceBspOnly; + +/** Offset 0x022D - Enable/Disable processor trace Timing Packet + Enable/Disable collocting processor trace performance (CYC, TSC); 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceTimingPacket; + +/** Offset 0x022E - Enable or Disable Three Strike Counter + Enable (default): Three Strike counter will be incremented. Disable: Prevents Three + Strike counter from incrementing; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThreeStrikeCounter; + +/** Offset 0x022F - CpuPostMemRsvd + Reserved for CPU Post-Mem + $EN_DIS +**/ + UINT8 CpuPostMemRsvd[64]; + +/** Offset 0x026F - Reserved +**/ + UINT8 Reserved6[113]; + +/** Offset 0x02E0 - UFS enable/disable + Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller + 0 and (0,1) to enable controller 1 + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x02E2 - UFS Inline Encryption enable/disable + Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0) + to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption + for controller 1 + $EN_DIS +**/ + UINT8 UfsInlineEncryption[2]; + +/** Offset 0x02E4 - UFS Connection Status + UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to + controller 0 and (0,1) to UFS connected to controller 1 + $EN_DIS +**/ + UINT8 UfsDeviceConnected[2]; + +/** Offset 0x02E6 - Reserved +**/ + UINT8 Reserved7[10]; + +/** Offset 0x02F0 - FSPS Validation + Point to FSPS Validation configuration structure +**/ + UINT64 FspsValidationPtr; + +/** Offset 0x02F8 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x02F9 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x02FA - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x02FB - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x02FC - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x02FD - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x02FE - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0300 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x0302 - Iax Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality. + $EN_DIS +**/ + UINT8 IaxEnable; + +/** Offset 0x0303 - Reserved +**/ + UINT8 Reserved8[9]; + +/** Offset 0x030C - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[12]; + +/** Offset 0x033C - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x0348 - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0354 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0360 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x036C - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x0378 - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0384 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x038C - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0394 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x039C - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x03AC - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[12]; + +/** Offset 0x03B8 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x03BB - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x03BE - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x03C1 - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x03C4 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x03C7 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x03CA - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x03CC - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x03CE - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x03D0 - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x03D4 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + +/** Offset 0x03D8 - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x03D9 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x03DA - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x03DC - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x03DF - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[12]; + +/** Offset 0x03EB - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x03EC - PCH ISH MSI Interrupts + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshMsiInterrupt; + +/** Offset 0x03ED - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x03EE - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x03EF - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x03F0 - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x03F1 - CSE Data Resilience Support + 0: Disable CSE Data Resilience Support. 1: Enable CSE Data Resilience Support. + $EN_DIS +**/ + UINT8 CseDataResilience; + +/** Offset 0x03F2 - PSE EOM Flow Control + 0: Disable PSE EOM Flow. 1: Enable PSE EOM Flow. + $EN_DIS +**/ + UINT8 PseEomFlowEnable; + +/** Offset 0x03F3 - ISH I3C SDA Pin Muxing + Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values. +**/ + UINT8 IshI3cSdaPinMuxing[8]; + +/** Offset 0x03FB - ISH I3C SCL Pin Muxing + Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values. +**/ + UINT8 IshI3cSclPinMuxing[8]; + +/** Offset 0x0403 - ISH I3C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI3cSdaPadTermination[2]; + +/** Offset 0x0405 - ISH I3C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI3cSclPadTermination[2]; + +/** Offset 0x0407 - Enable PCH ISH I3C pins assigned + Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI3cEnable[2]; + +/** Offset 0x0409 - Reserved +**/ + UINT8 Reserved10[3]; + +/** Offset 0x040C - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x0410 - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x0411 - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x0412 - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x0413 - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x0414 - Reserved +**/ + UINT8 Reserved11[8]; + +/** Offset 0x041C - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x041D - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x041E - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x041F - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x0420 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x0421 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x0422 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x0423 - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x0424 - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x0425 - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x0426 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x0427 - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x0428 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x0429 - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + UINT8 PchPmDeepSxPol; + +/** Offset 0x042A - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x042B - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x042C - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + UINT8 PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x042D - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x042E - Enable Timed GPIO0 + Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization + as extension of Hammock Harbor time synchronization. + $EN_DIS +**/ + UINT8 EnableTimedGpio0; + +/** Offset 0x042F - Enable Timed GPIO1 + Enable/Disable Timed GPIO1. When disabled, it disables cross time stamp time-synchronization + as extension of Hammock Harbor time synchronization. + $EN_DIS +**/ + UINT8 EnableTimedGpio1; + +/** Offset 0x0430 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0431 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0432 - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x0433 - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x0434 - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x0435 - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x0436 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x0437 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcPchLpmS0ixSubStateEnableMask; + +/** Offset 0x0438 - PCH PMC ER Debug mode + Disable/Enable Energy Reporting Debug Mode. + $EN_DIS +**/ + UINT8 PchPmErDebugMode; + +/** Offset 0x0439 - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x043A - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x043F - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x0444 - Reserved +**/ + UINT8 Reserved12[4]; + +/** Offset 0x0448 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x0452 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x045C - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x0478 - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[28]; + +/** Offset 0x0494 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[28]; + +/** Offset 0x04B0 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[28]; + +/** Offset 0x04CC - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[28]; + +/** Offset 0x0504 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x0520 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[28]; + +/** Offset 0x053C - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x0558 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x0574 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[28]; + +/** Offset 0x0590 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[28]; + +/** Offset 0x05AC - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[28]; + +/** Offset 0x05C8 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[28]; + +/** Offset 0x05E4 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[28]; + +/** Offset 0x0600 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[28]; + +/** Offset 0x061C - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[28]; + +/** Offset 0x0638 - PCIE RP Max Payload + Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x0654 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[28]; + +/** Offset 0x0670 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[28]; + +/** Offset 0x068C - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[28]; + +/** Offset 0x06A8 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x06C4 - Reserved +**/ + UINT8 Reserved13[168]; + +/** Offset 0x076C - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[28]; + +/** Offset 0x0788 - HostL0sTxDis + Disable Host L0 transmission state + $EN_DIS +**/ + UINT8 HostL0sTxDis[28]; + +/** Offset 0x07A4 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x07C0 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x07DC - Enable/Disable ASPM Optionality Compliance + Enable/Disable ASPM Optionality Compliance. +**/ + UINT8 PcieRpTestAspmOc[28]; + +/** Offset 0x07F8 - PCIE RP override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault[28]; + +/** Offset 0x0814 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen3EqMethod; + +/** Offset 0x0815 - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen3EqMode; + +/** Offset 0x0816 - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen3EqLocalTxOverrideEn; + +/** Offset 0x0817 - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen3EqPh3NoOfPresetOrCoeff; + +/** Offset 0x0818 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor0List; + +/** Offset 0x0819 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor0List; + +/** Offset 0x081A - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor1List; + +/** Offset 0x081B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor1List; + +/** Offset 0x081C - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor2List; + +/** Offset 0x081D - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor2List; + +/** Offset 0x081E - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor3List; + +/** Offset 0x081F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor3List; + +/** Offset 0x0820 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor4List; + +/** Offset 0x0821 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor4List; + +/** Offset 0x0822 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor5List; + +/** Offset 0x0823 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor5List; + +/** Offset 0x0824 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor6List; + +/** Offset 0x0825 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor6List; + +/** Offset 0x0826 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor7List; + +/** Offset 0x0827 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor7List; + +/** Offset 0x0828 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor8List; + +/** Offset 0x0829 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor8List; + +/** Offset 0x082A - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor9List; + +/** Offset 0x082B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor9List; + +/** Offset 0x082C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset0List; + +/** Offset 0x082D - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset1List; + +/** Offset 0x082E - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset2List; + +/** Offset 0x082F - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset3List; + +/** Offset 0x0830 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset4List; + +/** Offset 0x0831 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset5List; + +/** Offset 0x0832 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset6List; + +/** Offset 0x0833 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset7List; + +/** Offset 0x0834 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset8List; + +/** Offset 0x0835 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset9List; + +/** Offset 0x0836 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset10List; + +/** Offset 0x0837 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen3EqPh1DpTxPreset; + +/** Offset 0x0838 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen3EqPh1UpTxPreset; + +/** Offset 0x0839 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen3EqPh2LocalTxOverridePreset; + +/** Offset 0x083A - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen4EqMethod; + +/** Offset 0x083B - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen4EqMode; + +/** Offset 0x083C - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen4EqLocalTxOverrideEn; + +/** Offset 0x083D - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen4EqPh3NoOfPresetOrCoeff; + +/** Offset 0x083E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor0List; + +/** Offset 0x083F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor0List; + +/** Offset 0x0840 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor1List; + +/** Offset 0x0841 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor1List; + +/** Offset 0x0842 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor2List; + +/** Offset 0x0843 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor2List; + +/** Offset 0x0844 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor3List; + +/** Offset 0x0845 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor3List; + +/** Offset 0x0846 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor4List; + +/** Offset 0x0847 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor4List; + +/** Offset 0x0848 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor5List; + +/** Offset 0x0849 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor5List; + +/** Offset 0x084A - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor6List; + +/** Offset 0x084B - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor6List; + +/** Offset 0x084C - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor7List; + +/** Offset 0x084D - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor7List; + +/** Offset 0x084E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor8List; + +/** Offset 0x084F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor8List; + +/** Offset 0x0850 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor9List; + +/** Offset 0x0851 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor9List; + +/** Offset 0x0852 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset0List; + +/** Offset 0x0853 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset1List; + +/** Offset 0x0854 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset2List; + +/** Offset 0x0855 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset3List; + +/** Offset 0x0856 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset4List; + +/** Offset 0x0857 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset5List; + +/** Offset 0x0858 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset6List; + +/** Offset 0x0859 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset7List; + +/** Offset 0x085A - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset8List; + +/** Offset 0x085B - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset9List; + +/** Offset 0x085C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset10List; + +/** Offset 0x085D - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen4EqPh1DpTxPreset; + +/** Offset 0x085E - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen4EqPh1UpTxPreset; + +/** Offset 0x085F - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen4EqPh2LocalTxOverridePreset; + +/** Offset 0x0860 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen5EqMethod; + +/** Offset 0x0861 - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen5EqMode; + +/** Offset 0x0862 - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen5EqLocalTxOverrideEn; + +/** Offset 0x0863 - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen5EqPh3NoOfPresetOrCoeff; + +/** Offset 0x0864 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor0List; + +/** Offset 0x0865 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor0List; + +/** Offset 0x0866 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor1List; + +/** Offset 0x0867 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor1List; + +/** Offset 0x0868 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor2List; + +/** Offset 0x0869 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor2List; + +/** Offset 0x086A - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor3List; + +/** Offset 0x086B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor3List; + +/** Offset 0x086C - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor4List; + +/** Offset 0x086D - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor4List; + +/** Offset 0x086E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor5List; + +/** Offset 0x086F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor5List; + +/** Offset 0x0870 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor6List; + +/** Offset 0x0871 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor6List; + +/** Offset 0x0872 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor7List; + +/** Offset 0x0873 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor7List; + +/** Offset 0x0874 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor8List; + +/** Offset 0x0875 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor8List; + +/** Offset 0x0876 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor9List; + +/** Offset 0x0877 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor9List; + +/** Offset 0x0878 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset0List; + +/** Offset 0x0879 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset1List; + +/** Offset 0x087A - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset2List; + +/** Offset 0x087B - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset3List; + +/** Offset 0x087C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset4List; + +/** Offset 0x087D - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset5List; + +/** Offset 0x087E - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset6List; + +/** Offset 0x087F - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset7List; + +/** Offset 0x0880 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset8List; + +/** Offset 0x0881 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset9List; + +/** Offset 0x0882 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset10List; + +/** Offset 0x0883 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen5EqPh1DpTxPreset; + +/** Offset 0x0884 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen5EqPh1UpTxPreset; + +/** Offset 0x0885 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen5EqPh2LocalTxOverridePreset; + +/** Offset 0x0886 - Phase3 RP Gen3 EQ enable + Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh3Bypass; + +/** Offset 0x0887 - Phase3 RP Gen4 EQ enable + Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh3Bypass; + +/** Offset 0x0888 - Phase3 RP Gen5 EQ enable + Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh3Bypass; + +/** Offset 0x0889 - Phase2-3 RP Gen3 EQ enable + Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh23Bypass; + +/** Offset 0x088A - Phase2-3 RP Gen4 EQ enable + Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh23Bypass; + +/** Offset 0x088B - Phase2-3 RP Gen5 EQ enable + Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh23Bypass; + +/** Offset 0x088C - PCET Timer + Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen3PcetTimer; + +/** Offset 0x088D - Gen4 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen4PcetTimer; + +/** Offset 0x088E - Gen5 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen5PcetTimer; + +/** Offset 0x088F - TS Lock Timer for Gen3 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock + Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen3TsLockTimer; + +/** Offset 0x0890 - PTS Lock Timer for Gen4 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock + Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen4TsLockTimer; + +/** Offset 0x0891 - PTS Lock Timer for Gen5 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock + Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen5TsLockTimer; + +/** Offset 0x0892 - PCIe Configuration Space Dump + Enable/Disable PCIe Configuration Space Dump + $EN_DIS +**/ + UINT8 PcieCfgDump[28]; + +/** Offset 0x08AE - PCIE RP Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite[28]; + +/** Offset 0x08CA - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable +**/ + UINT8 PcieRpLinkDownGpios[28]; + +/** Offset 0x08E6 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x08E7 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x08E8 - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 PcieFomsCp[28]; + +/** Offset 0x0904 - EqPhBypass Control Policy + PCIe Equalization Phase Enable Control, Disabled (0x0) : Disable Phase + (Default), Enabled (0x1) : Enable Phase + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 PcieEqPhBypass; + +/** Offset 0x0905 - PCIe TBT Performance Boost Bitmap + Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers + connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE +**/ + UINT8 PcieTbtPerfBoost; + +/** Offset 0x0906 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[28]; + +/** Offset 0x093E - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; + +/** Offset 0x0976 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[28]; + +/** Offset 0x0992 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x09AE - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[28]; + +/** Offset 0x09E6 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; + +/** Offset 0x0A02 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x0A1E - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[28]; + +/** Offset 0x0A56 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[28]; + +/** Offset 0x0A72 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[28]; + +/** Offset 0x0AAA - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x0AAB - PCIe RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PciePowerGating[28]; + +/** Offset 0x0AC7 - PCIe RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieClockGating[28]; + +/** Offset 0x0AE3 - PCIe RootPort AutoPower Gating + Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieAutoPowerGating[28]; + +/** Offset 0x0AFF - PCIe RootPort VISA Clock Gating + Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieVisaClockGating[28]; + +/** Offset 0x0B1B - PCIe RootPort PHY AutoPower Gating + Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PciePhyAutoPowerGating; + +/** Offset 0x0B1C - PCIE RP LTR Override Spec Compliant + Override LTR based on Ep capability. +**/ + UINT8 PcieRpLtrOverrideSpecCompliant[28]; + +/** Offset 0x0B38 - Force LTR Override + Force LTR Override. +**/ + UINT8 PcieRpTestForceLtrOverride[28]; + +/** Offset 0x0B54 - Reserved +**/ + UINT8 Reserved14; + +/** Offset 0x0B55 - PCIe AER _OSC Setting + Enable/Disable Global PCIe Advanced Error Reporting + 0:Disable, 1:Enable +**/ + UINT8 GlobalPcieAer; + +/** Offset 0x0B56 - Reserved +**/ + UINT8 Reserved15[66]; + +/** Offset 0x0B98 - Serial IO SPI CLK Pin Muxing + Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* + for possible values. +**/ + UINT32 SerialIoLpssSpiClkPinMux[7]; + +/** Offset 0x0BB4 - Serial IO SPI CS Pin Muxing + Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* + for possible values. +**/ + UINT32 SerialIoLpssSpiCsPinMux[14]; + +/** Offset 0x0BEC - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden +**/ + UINT8 SerialIoLpssSpiMode[7]; + +/** Offset 0x0BF3 - Reserved +**/ + UINT8 Reserved16[5]; + +/** Offset 0x0BF8 - LPSS SPI MOSI Pin Muxing + Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values. +**/ + UINT32 SerialIoLpssSpiMosiPinMux[7]; + +/** Offset 0x0C14 - LPSS SPI MISO Pin Muxing + Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values. +**/ + UINT32 SerialIoLpssSpiMisoPinMux[7]; + +/** Offset 0x0C30 - SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh +**/ + UINT8 SerialIoLpssSpiCsPolarity[14]; + +/** Offset 0x0C3E - Reserved +**/ + UINT8 Reserved17[8]; + +/** Offset 0x0C46 - SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoLpssSpiCsEnable[14]; + +/** Offset 0x0C54 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoLpssSpiCsMode[7]; + +/** Offset 0x0C5B - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoLpssSpiCsState[7]; + +/** Offset 0x0C62 - Reserved +**/ + UINT8 Reserved18[98]; + +/** Offset 0x0CC4 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x0CCB - Reserved +**/ + UINT8 Reserved19[13]; + +/** Offset 0x0CD8 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x0CF4 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x0CFB - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x0D02 - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x0D09 - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x0D10 - Reserved +**/ + UINT8 Reserved20[7]; + +/** Offset 0x0D17 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x0D1E - Reserved +**/ + UINT8 Reserved21[7]; + +/** Offset 0x0D25 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0D2C - Reserved +**/ + UINT8 Reserved22[12]; + +/** Offset 0x0D38 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0D54 - Reserved +**/ + UINT8 Reserved23[28]; + +/** Offset 0x0D70 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0D8C - Reserved +**/ + UINT8 Reserved24[28]; + +/** Offset 0x0DA8 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x0DAF - Reserved +**/ + UINT8 Reserved25[61]; + +/** Offset 0x0DEC - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x0DF4 - Reserved +**/ + UINT8 Reserved26[8]; + +/** Offset 0x0DFC - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x0E1C - Reserved +**/ + UINT8 Reserved27[32]; + +/** Offset 0x0E3C - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x0E5C - Reserved +**/ + UINT8 Reserved28[32]; + +/** Offset 0x0E7C - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x0E84 - Reserved +**/ + UINT8 Reserved29[8]; + +/** Offset 0x0E8C - I3C Device Mode + Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, + 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) +**/ + UINT8 SerialIoI3cMode[4]; + +/** Offset 0x0E90 - Reserved +**/ + UINT8 Reserved30[4]; + +/** Offset 0x0E94 - Serial IO I3C SDA Pin Muxing + Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for + possible values. +**/ + UINT32 SerialIoI3cSdaPinMux[4]; + +/** Offset 0x0EA4 - Serial IO I3C SDA Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,I3C2,I3C3 pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSdaPadTermination[4]; + +/** Offset 0x0EA8 - Serial IO I3C SCL Pin Muxing + Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for + possible values. +**/ + UINT32 SerialIoI3cSclPinMux[4]; + +/** Offset 0x0EB8 - Serial IO I3C SCL Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,I3C2,I3C3 pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclPadTermination[4]; + +/** Offset 0x0EBC - Serial IO I3C SCL FB Pin Muxing + Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* + for possible values. +**/ + UINT32 SerialIoI3cSclFbPinMux[4]; + +/** Offset 0x0ECC - Serial IO I3C SCL FB Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,I3C2,I3C3 pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclFbPadTermination[4]; + +/** Offset 0x0ED0 - Reserved +**/ + UINT8 Reserved31[64]; + +/** Offset 0x0F10 - Enable VMD controller + Enable/disable to VMD controller. 0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0F11 - Enable VMD Global Mapping + Enable/disable to VMD Global Mapping. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0F12 - Reserved +**/ + UINT8 Reserved32[2]; + +/** Offset 0x0F14 - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0F33 - VMD Port Bus + VMD Root port bus number. +**/ + UINT8 VmdPortBus[31]; + +/** Offset 0x0F52 - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0F71 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x0F90 - VMD Variable + VMD Variable Pointer. +**/ + UINT64 VmdVariablePtr; + +/** Offset 0x0F98 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x0F9C - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x0FA0 - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x0FA4 - Reserved +**/ + UINT8 Reserved33[22]; + +/** Offset 0x0FBA - TCSS TBT Performance Boost Bitmap + Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0, + Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3 +**/ + UINT8 TcssTbtPerfBoost; + +/** Offset 0x0FBB - Reserved +**/ + UINT8 Reserved34[2]; + +/** Offset 0x0FBD - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[10]; + +/** Offset 0x0FC7 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x0FC8 - Reserved +**/ + UINT8 Reserved35[8]; + +/** Offset 0x0FD0 - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x0FD1 - TC Notify Igd + Tc Notify Igd +**/ + UINT8 TcNotifyIgd; + +/** Offset 0x0FD2 - TCSS CPU USB PDO Programming + Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow + for programming during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 TcssCpuUsbPdoProgramming; + +/** Offset 0x0FD3 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x0FD4 - Reserved +**/ + UINT8 Reserved36[7]; + +/** Offset 0x0FDB - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x0FDC - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x0FE0 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x0FE4 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x0FE8 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0FEC - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x0FF4 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x0FF8 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0FFC - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x1004 - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x1008 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x100C - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA + $EN_DIS +**/ + UINT8 EnableTcssCovTypeA[4]; + +/** Offset 0x1010 - Reserved +**/ + UINT8 Reserved37[16]; + +/** Offset 0x1020 - Touch Host Controller Assignment + Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcAssignment[2]; + +/** Offset 0x1022 - Touch Host Controller Interrupt Pin Mux + Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* + for possible values. +**/ + UINT8 ThcInterruptPinMuxing[8]; + +/** Offset 0x102A - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid +**/ + UINT8 ThcMode[2]; + +/** Offset 0x102C - Touch Host Controller Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI +**/ + UINT8 ThcWakeOnTouch[2]; + +/** Offset 0x102E - Reserved +**/ + UINT8 Reserved38[2]; + +/** Offset 0x1030 - Touch Host Controller Active Ltr + Expose Active Ltr for OS driver to set +**/ + UINT32 ThcActiveLtr[2]; + +/** Offset 0x1038 - Touch Host Controller Idle Ltr + Expose Idle Ltr for OS driver to set +**/ + UINT32 ThcIdleLtr[2]; + +/** Offset 0x1040 - Touch Host Controller Timestamp timer behavior in D0i2 + Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer + is paused instead of reset to 0 when entering D0i2 +**/ + UINT8 TimestampTimerMode[2]; + +/** Offset 0x1042 - Reserved +**/ + UINT8 Reserved39[2]; + +/** Offset 0x1044 - Touch Host Controller Display Frame Sync Period + Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum + period is 100ms +**/ + UINT32 DisplayFrameSyncPeriod[2]; + +/** Offset 0x104C - Touch Host Controller ResetPad + ResetPad +**/ + UINT32 ThcResetPad[2]; + +/** Offset 0x1054 - Touch Host Controller ResetPad Trigger + Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High +**/ + UINT32 ThcResetPadTrigger[2]; + +/** Offset 0x105C - Touch Host Controller DYSync + Based on this setting GPIO for given THC will be in native mode +**/ + UINT8 ThcDsyncPad[2]; + +/** Offset 0x105E - Reserved +**/ + UINT8 Reserved40[2]; + +/** Offset 0x1060 - Touch Host Controller Hid Over Spi Connection Speed + Hid Over Spi Connection Speed - SPI Frequency +**/ + UINT32 ThcHidSpiConnectionSpeed[2]; + +/** Offset 0x1068 - Touch Host Controller Hid Over Spi Limit PacketSize + When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc + packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes +**/ + UINT32 ThcHidSpiLimitPacketSize[2]; + +/** Offset 0x1070 - Touch Host Controller Hid Over Spi Limit PacketSize + Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation + and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, + 1-65535 (0xFFFF) - up to 655350 us +**/ + UINT32 ThcPerformanceLimitation[2]; + +/** Offset 0x1078 - Touch Host Controller Hid Over Spi Input Report Header Address + Hid Over Spi Input Report Header Address +**/ + UINT32 ThcHidSpiInputReportHeaderAddress[2]; + +/** Offset 0x1080 - Touch Host Controller Hid Over Spi Input Report Body Address + Hid Over Spi Input Report Body Address +**/ + UINT32 ThcHidSpiInputReportBodyAddress[2]; + +/** Offset 0x1088 - Touch Host Controller Hid Over Spi Output Report Address + Hid Over Spi Output Report Address +**/ + UINT32 ThcHidSpiOutputReportAddress[2]; + +/** Offset 0x1090 - Touch Host Controller Hid Over Spi Read Opcode + Hid Over Spi Read Opcode +**/ + UINT32 ThcHidSpiReadOpcode[2]; + +/** Offset 0x1098 - Touch Host Controller Hid Over Spi Write Opcode + Hid Over Spi Write Opcode +**/ + UINT32 ThcHidSpiWriteOpcode[2]; + +/** Offset 0x10A0 - Touch Host Controller Hid Over Spi Flags + Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode +**/ + UINT32 ThcHidSpiFlags[2]; + +/** Offset 0x10A8 - Touch Host Controller Reset Sequencing Delay [ms] + Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms +**/ + UINT16 ThcResetSequencingDelay[2]; + +/** Offset 0x10AC - Touch Host Controller Hid Over I2c Device Address + Hid Over I2c Device Address +**/ + UINT32 ThcHidI2cDeviceAddress[2]; + +/** Offset 0x10B4 - Touch Host Controller Hid Over I2c Connection Speed + Hid Over I2c Connection Speed [Hz] +**/ + UINT32 ThcHidI2cConnectionSpeed[2]; + +/** Offset 0x10BC - Touch Host Controller Hid Over I2c Addressing Mode + Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0: + The connection uses 7-bit addressing. +**/ + UINT8 ThcHidI2cAddressingMode[2]; + +/** Offset 0x10BE - Reserved +**/ + UINT8 Reserved41[2]; + +/** Offset 0x10C0 - Touch Host Controller Hid Over I2c Device Descriptor Address + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cDeviceDescriptorAddress[2]; + +/** Offset 0x10C8 - Touch Host Controller Hid Over I2c Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialClockLineHighPeriod[2]; + +/** Offset 0x10D0 - Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialClockLineLowPeriod[2]; + +/** Offset 0x10D8 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x10E0 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x10E8 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialClockLineHighPeriod[2]; + +/** Offset 0x10F0 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialClockLineLowPeriod[2]; + +/** Offset 0x10F8 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x1100 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x1108 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cMaxSuppressedSpikesSMFMFMP[2]; + +/** Offset 0x1110 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialClockLineHighPeriod[2]; + +/** Offset 0x1118 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialClockLineLowPeriod[2]; + +/** Offset 0x1120 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x1128 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x1130 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod[2]; + +/** Offset 0x1138 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod[2]; + +/** Offset 0x1140 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x1148 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x1150 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode[2]; + +/** Offset 0x1158 - THC Wake On Touch GPIO resource Edge or Level + Definition of GPIO resource configuration of Edge or Level +**/ + UINT8 ThcWotEdgeLevel[2]; + +/** Offset 0x115A - THC Wake On Touch GPIO resource of Active Level + Definition of GPIO resource configuration of Active Level +**/ + UINT8 ThcWotActiveLevel[2]; + +/** Offset 0x115C - THC Wake On Touch GPIO resource of pin configuration + Definition of GPIO resource configuration of pin configuration +**/ + UINT8 ThcWotPinConfig[2]; + +/** Offset 0x115E - THC customized SubSytem ID for Port + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcCustomizedSsid[2]; + +/** Offset 0x1162 - THC Sets Customized SubSytem Vendor ID for Port + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcCustomizedSvid[2]; + +/** Offset 0x1166 - Touch Host Controller Hid Over I2c Maximum Frame Size Enable + Definition of GPIO resource configuration of pin configuration +**/ + UINT8 ThcHidI2cMaxFrameSize[2]; + +/** Offset 0x1168 - Touch Host Controller Hid Over I2c Maximum Frame Size Value + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcHidI2cMaxFrameSizeValue[2]; + +/** Offset 0x116C - Touch Host Controller Hid Over I2c Interrupt Delay Enable + Definition of GPIO resource configuration of pin configuration +**/ + UINT8 ThcHidI2cIntDelay[2]; + +/** Offset 0x116E - Touch Host Controller Hid Over I2c Interrupt Delay Value + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcHidI2cIntDelayValue[2]; + +/** Offset 0x1172 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd[15]; + +/** Offset 0x1181 - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x1182 - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x1184 - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x1186 - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x1188 - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x1189 - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x118A - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x118B - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 TTSuggestedSetting; + +/** Offset 0x118C - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x118E - Reserved +**/ + UINT8 Reserved42[2]; + +/** Offset 0x1190 - Fusa Psf Configuration + Fusa (Functional Safety) Enable Fusa Feature on Psf, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PsfFusaConfigEnable; + +/** Offset 0x1191 - Fusa Display Configuration + Fusa (Functional Safety) Enable Fusa Feature on Display, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 DisplayFusaConfigEnable; + +/** Offset 0x1192 - Fusa Graphics Configuration + Fusa (Functional Safety) Enable Fusa Feature on Graphics, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 GraphicFusaConfigEnable; + +/** Offset 0x1193 - Fusa Opio Configuration + Fusa (Functional Safety) Enable Fusa Feature on Opio, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 OpioFusaConfigEnable; + +/** Offset 0x1194 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x11A4 - Enable USB2 SW Device Mode + Enable/disable SW device mode per USB2 ports. One byte for each port, byte0 for + port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb20SwDeviceModeEnable[16]; + +/** Offset 0x11B4 - USB2 DWB Integrated Camera Port + Indicate if each USB2 port has an integrated camera connected. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb20IntegratedCamera[16]; + +/** Offset 0x11C4 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x11CE - USB 3.1 Speed Selection + Choose USB 3.1 Speed Selection. 1: Gen1, 0: Gen2 + $EN_DIS +**/ + UINT8 PortUsb31Speed[10]; + +/** Offset 0x11D8 - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x11D9 - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x11DA - USB Audio Offload enable + Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default) + $EN_DIS +**/ + UINT8 PchXhciUaolEnable; + +/** Offset 0x11DB - Reserved +**/ + UINT8 Reserved43; + +/** Offset 0x11DC - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x11DD - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x11ED - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x11F7 - Reserved +**/ + UINT8 Reserved44[5]; + +/** Offset 0x11FC - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x120C - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x120D - Reserved +**/ + UINT8 Reserved45[46]; + +/** Offset 0x123B - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x124B - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x125B - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x126B - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x127B - PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieFiaProgramming; + +/** Offset 0x127C - Enable SSE Device + Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space + $EN_DIS +**/ + UINT8 SseCommunication; + +/** Offset 0x127D - Reserved +**/ + UINT8 Reserved46[2]; + +/** Offset 0x127F - Enable/Disable NPU Device + Enable(Default): Enable NPU Device, Disable: Disable NPU Device + $EN_DIS +**/ + UINT8 NpuEnable; + +/** Offset 0x1280 - Reserved +**/ + UINT8 Reserved47[4]; + +/** Offset 0x1284 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x1285 - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x1286 - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x1287 - Reserved +**/ + UINT8 Reserved48[3]; + +/** Offset 0x128A - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x128C - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x128E - Reserved +**/ + UINT8 Reserved49[18]; + +/** Offset 0x12A0 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT64 SiSsidTablePtr; + +/** Offset 0x12A8 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x12AA - Skip DFX. + Skip DFX. + $EN_DIS +**/ + UINT8 DfxSkipBiosDone; + +/** Offset 0x12AB - Reserved +**/ + UINT8 Reserved50[13]; + +/** Offset 0x12B8 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x12BC - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x12C0 - Reserved +**/ + UINT8 Reserved51[8]; + +/** Offset 0x12C8 - Blt Buffer Address + Address of Blt buffer +**/ + UINT64 BltBufferAddress; + +/** Offset 0x12D0 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 GraphicsConfigPtr; + +/** Offset 0x12D8 - Reserved +**/ + UINT8 Reserved52; + +/** Offset 0x12D9 - Enable/Disable Media Configuration + Enable(Default): Configure Media for use, Disable: Skip Media Configuration + $EN_DIS +**/ + UINT8 ConfigureMedia; + +/** Offset 0x12DA - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x12DB - Enable/Disable GT Configuration + Enable(Default): Configure GT for use, Disable: Skip GT Configuration + $EN_DIS +**/ + UINT8 ConfigureGT; + +/** Offset 0x12DC - Enable RC1p GT frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pGtFreqEnable; + +/** Offset 0x12DD - Enable RC1p Media frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pMediaFreqEnable; + +/** Offset 0x12DE - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x12DF - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x12E0 - Enable/Disable IGFX Media Standby + Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby + $EN_DIS +**/ + UINT8 MediaStandby; + +/** Offset 0x12E1 - Enable/Disable Gfx Workstation + Enable(Default): Is a workstation, Disable: Is not a workstation + $EN_DIS +**/ + UINT8 Dev2IsGfxWorkstation; + +/** Offset 0x12E2 - Reserved +**/ + UINT8 Reserved53[2]; + +/** Offset 0x12E4 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x12E8 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x12E9 - Reserved +**/ + UINT8 Reserved54[3]; + +/** Offset 0x12EC - HorizontalResolution for PEI Logo + HorizontalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 HorizontalResolution; + +/** Offset 0x12F0 - VerticalResolution for PEI Logo + VerticalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 VerticalResolution; + +/** Offset 0x12F4 - Reserved +**/ + UINT8 Reserved55[52]; + +/** Offset 0x1328 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x132C - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x132D - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x132E - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x132F - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x1330 - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x1331 - PMC ADR enable + Enable/disable asynchronous DRAM refresh + $EN_DIS +**/ + UINT8 PmcAdrEn; + +/** Offset 0x1332 - PMC ADR timer configuration enable + Enable/disable ADR timer configuration + $EN_DIS +**/ + UINT8 PmcAdrTimerEn; + +/** Offset 0x1333 - PMC ADR phase 1 timer value + Enable/disable ADR timer configuration +**/ + UINT8 PmcAdrTimer1Val; + +/** Offset 0x1334 - PMC ADR phase 1 timer multiplier value + Specify the multiplier value for phase 1 ADR timer +**/ + UINT8 PmcAdrMultiplier1Val; + +/** Offset 0x1335 - PMC ADR host reset partition enable + Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message + $EN_DIS +**/ + UINT8 PmcAdrHostPartitionReset; + +/** Offset 0x1336 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x1337 - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x1338 - PCH P2SB + PCH P2SB + $EN_DIS +**/ + UINT8 SvTestUnhideP2sb; + +/** Offset 0x1339 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x133A - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x133B - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x133C - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x133D - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x133E - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x133F - CNVi Wi-Fi Core + Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviWifiCore; + +/** Offset 0x1340 - WWAN Coex + WWAN Coex is getting updated from UEFI variable +**/ + UINT8 CnviWwanCoex; + +/** Offset 0x1341 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x1342 +**/ + UINT16 FspsUpdRsvd36; + +/** Offset 0x1344 - Reserved +**/ + UINT8 Reserved56[4]; + +/** Offset 0x1348 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT32 CnviBtAudioOffload; + +/** Offset 0x134C - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x1350 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x1354 - CNVi BT Audio OffOffloadInterfaceload + Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffloadInterface; + +/** Offset 0x1355 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x1356 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x1357 - Reserved +**/ + UINT8 Reserved57[53]; + +/** Offset 0x138C - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x138D - Reserved +**/ + UINT8 Reserved58[19]; + +/** Offset 0x13A0 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT64 PchHdaVerbTablePtr; + +/** Offset 0x13A8 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x13A9 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x13AA - HD Audio Microphone Privacy Mode + HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed + Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute + 0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed + Microphone Privacy, 3: Force Microphone Mute +**/ + UINT8 PchHdaMicPrivacyMode; + +/** Offset 0x13AB - HD Audio Microphone Privacy Deglitch + HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyDeglitch; + +/** Offset 0x13AC - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire0; + +/** Offset 0x13AD - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire1; + +/** Offset 0x13AE - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire2; + +/** Offset 0x13AF - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire3; + +/** Offset 0x13B0 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire4; + +/** Offset 0x13B1 - HD Audio Microphone Privacy applied for Dmic in HW Mode + HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeDmic; + +/** Offset 0x13B2 - Reserved +**/ + UINT8 Reserved59[2]; + +/** Offset 0x13B4 - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing. + HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before + forcing the actual microphone privacy DMA data zeroing. +**/ + UINT32 PchHdaMicPrivacyTimeout; + +/** Offset 0x13B8 - Reserved +**/ + UINT8 Reserved60[8]; + +/** Offset 0x13C0 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x13C1 - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x13C2 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x13C3 - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x13C4 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x13CC - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x13CD - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x13D5 - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x13DD - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x13E5 - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x13ED - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x13F5 - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x13FD - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x1405 - Reserved +**/ + UINT8 Reserved61; + +/** Offset 0x1406 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x1416 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x141E - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x141F - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x1420 - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x1421 - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x1422 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x1423 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x1424 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x1425 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x1426 - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x1427 - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x1428 - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x1429 - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x142A - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x142B - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x142C - Reserved +**/ + UINT8 Reserved62[4]; + +/** Offset 0x1430 - Pointer to ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT64 ChipsetInitBinPtr; + +/** Offset 0x1438 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x143C - Reserved +**/ + UINT8 Reserved63[4]; + +/** Offset 0x1440 - Pointer to NPHY Binary + Nphy Binary Pointer. +**/ + UINT64 NphyBinPtr; + +/** Offset 0x1448 - Length of NPHY Binary + Nphy Binary Length. +**/ + UINT32 NphyBinLen; + +/** Offset 0x144C - Reserved +**/ + UINT8 Reserved64[4]; + +/** Offset 0x1450 - Pointer to SYNPS PHY Binary + Synps Binary Pointer. +**/ + UINT64 SynpsPhyBinPtr; + +/** Offset 0x1458 - Length of SYNPS PHY Binary + Synps Binary Length. +**/ + UINT32 SynpsPhyBinLen; + +/** Offset 0x145C - Skip setting BIOS_DONE When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR + at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing + 3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE. + $EN_DIS +**/ + UINT8 SiSkipBiosDoneWhenFwUpdate; + +/** Offset 0x145D - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x145E - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x145F - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x1460 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x1461 - PMC WDT enable + Enable/disable PMC WDT configuration + $EN_DIS +**/ + UINT8 PmcWdtTimerEn; + +/** Offset 0x1462 - Reserved +**/ + UINT8 Reserved65[14]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH2_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x1470 +**/ + UINT8 FspsUpdRsvd45[6]; + +/** Offset 0x1476 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/novalake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/novalake/MemInfoHob.h new file mode 100644 index 00000000000..b07017d84a3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/novalake/MemInfoHob.h @@ -0,0 +1,364 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 1999 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include +#include +#include +#include +#ifndef MAX_CONTROLLER_GLOBAL +#define MAX_CONTROLLER_GLOBAL (2) ///< The maximum number of memory controllers +#endif + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE MAX_CONTROLLER_GLOBAL +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 +#define _MAX_RANK_IN_CHANNEL (4) ///< The maximum number of ranks per channel. +#define _MAX_SDRAM_IN_DIMM (5) ///< The maximum number of SDRAMs per DIMM. + +// Must match the corresponding definition in CMrcExtTypes.h +#define PPR_REQUEST_MAX (2) +#define HOB_MAX_SAGV_POINTS 4 +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 39 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; +#ifndef CONTROLLER_NOT_PRESENT +#define CONTROLLER_NOT_PRESENT 0 // There is no controller present in the system. +#endif +#ifndef CONTROLLER_DISABLED +#define CONTROLLER_DISABLED 1 // There is a controller present but it is disabled. +#endif +#ifndef CONTROLLER_PRESENT +#define CONTROLLER_PRESENT 2 // There is a controller present and it is enabled. +#endif + +#define CHANNEL_NOT_FOUND 0xFF +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif +#ifndef DIMM_NOT_SUPPORTED +#define DIMM_NOT_SUPPORTED 4 // There is a DIMM present, but its type it's not supported. +#endif +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 0 +#endif +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 2 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#ifndef MAX_COPY_DIMM_DFE_TAPS +#define MAX_COPY_DIMM_DFE_TAPS 2 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. + UINT8 Resv[2]; ///< Reserved. +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} HOB_MANUFACTURER_ID_CODE; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + HOB_MANUFACTURER_ID_CODE MfgId; ///< Dram module manufacturer ID + HOB_MANUFACTURER_ID_CODE CkdMfgID; ///< Clock Driver (CKD) Manufacturer ID + UINT8 CkdDeviceRev; ///< Clock Driver (CKD) device revision + HOB_MANUFACTURER_ID_CODE DramMfgID; ///< Manufacturer ID code for DRAM chip on the module + UINT8 ModulePartNum[30]; ///< Module part number in ASCII + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. + UINT8 Banks; ///< Number of banks the DIMM contains. + UINT8 BankGroups; ///< Number of bank groups the DIMM contains. + UINT8 DeviceDensity; ///< Device Density in Gb + UINT32 SerialNumber; ///< DIMM Serial Number + UINT8 TotalWidth; ///< Total Data width in bits + UINT8 DataWidth; ///< Primary bus width in bits +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. + UINT32 ControllerCapacity; ///< The total capacity of the controller in MBytes. +} CONTROLLER_INFO; + +// +// Each DIMM Slot Mechanical present bit map +// +typedef struct { + UINT8 MrcSlotMap[MAX_NODE][MAX_CH]; +} MRC_SLOTMAP; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific + UINT16 MaxMemoryBandwidth; ///< Maximum theoretical bandwidth in GB/s supported by GV +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct _PPR_RESULT_COLUMNS_HOB { + UINT8 PprRowRepairsSuccessful; + UINT8 Controller; + UINT8 Channel; + UINT8 Rank; + UINT8 BankGroup; + UINT8 Bank; + UINT32 Row; + UINT8 Device; +} PPR_RESULT_COLUMNS_HOB; + +/** + Memory Info Data Hob + + Revision 1: - Initial version. (from MTL) +**/ +typedef struct { + UINT8 Revision; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR5 or LPDDR5, uses SMBIOS MEMORY_DEVICE_TYPE encoding + UINT16 MaximumMemoryClockSpeed; ///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + INT8 DimmDFE[MAX_PROFILE_NUM][MAX_DDR5_CH][MAX_DIMM][MAX_COPY_DIMM_DFE_TAPS]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + UINT8 MemSsEnableMask; ///< Memory SubSystem enable Bit mask, 0 - MemSS disabled, 1 - MemSS enabled + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT8 MopPackages; ///< Mop DRAM package population + UINT8 MopDensity; ///< Mop DRAM die density + UINT8 MopRanks; ///< Mop Number of ranks + UINT8 MopVendor; ///< Mop DRAM vendor ID + UINT8 PprRanInLastBoot; ///< Whether PPR ran in the prior boot + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status + UINT16 PprRepairsSuccessful; ///< PPR: Counts of repair successes + UINT32 PprFailingChannelBitMask; ///< PPR failing channel mask + PPR_RESULT_COLUMNS_HOB PprErrorInfo; ///< PPR: Error location + UINT8 PprAvailableResources[MAX_NODE][MAX_CH][_MAX_RANK_IN_CHANNEL][_MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device + UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB] + BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed) +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: - Initial version. +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT64 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; + UINT8 Reserved1[3]; // Reserved for alignment + UINT64 BiosPeiMemoryBaseAddress; + UINT64 BiosPeiMemoryLength; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h index 9661285ef31..33ae66b1e5c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2024, Intel Corporation. All rights reserved.
+Copyright (c) 2026, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h index cb221b9e143..890a813c408 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2025, Intel Corporation. All rights reserved.
+Copyright (c) 2026, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,6 +50,41 @@ typedef struct { UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table } CHIPSET_INIT_INFO; +/// +/// MRC Error Key Value Entry structure maps an MRC error code to an error message string. +/// +/* +// +// MRC Error Key Value Table Entries +// OEM can customize this table to display error messages on VGA display +// The Key is used to look up the error message, and the Value is the message string +// +// Message types: +// - MRC_NO_MEMORY_DETECTED (0xDF7E) - "NO MEMORY DETECTED" +// - MRC_MEM_INIT_DONE_WITH_ERRORS (0xDF55) - "BASIC MEMORY TEST FAILED" +// - 0xFFFF (Fallback) - "MRC FAILED, POST CODE: " + POST code in hex +// Any other MRC failure (SPD processing, PLL lock, calibration, training etc.) +// will use the fallback message with the actual POST code appended. +// +// Maximum message length (excluding null terminator): +// - Exact match messages (specific POST code keys): 80 characters +// - Fallback message (key 0xFFFF): 73 characters (+ "0xXXXX" appended automatically) +// +*/ +typedef struct { + UINT32 Key; ///< MRC POST code (16-bit value, 0xFFFF = fallback key) + CONST CHAR8 *Value; ///< MRC error message string +} FSP_MRC_ERROR_KEY_VALUE_ENTRY; + +/// +/// MRC Error Key Value Table contains array of error code to message mappings. +/// +typedef struct { + UINT32 Count; ///< Number of entries in Entry[] array + UINT32 Size; ///< Total size of table in bytes + FSP_MRC_ERROR_KEY_VALUE_ENTRY Entry[]; ///< Variable length array of key-value pairs +} FSP_MRC_ERROR_KEY_VALUE_TABLE; + /** Fsp M Configuration **/ @@ -141,9 +176,30 @@ typedef struct { **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x007B - Reserved +/** Offset 0x007B - NnFlex Override for PHY RxEqTap0 + Controlled by NnFlexPhyOvrdMask bit[0], 6 bit 2's complement +**/ + UINT8 NnFlexPhyRxEqTap0; + +/** Offset 0x007C - NnFlex Override for PHY RxEqTap1 + Controlled by NnFlexPhyOvrdMask bit[1], 6 bit 2's complement, valid range: [-16..15] +**/ + UINT8 NnFlexPhyRxEqTap1; + +/** Offset 0x007D - NnFlex Override for PHY DqTcoComp + Controlled by NnFlexPhyOvrdMask bit[2], 6 bit 2's complement +**/ + UINT8 NnFlexPhyDqTcoComp; + +/** Offset 0x007E - NnFlex Override for PHY RxCtleR + Controlled by NnFlexPhyOvrdMask bit[3] **/ - UINT8 Reserved1[5]; + UINT8 NnFlexPhyRxCtleR; + +/** Offset 0x007F - NnFlex Override for PHY RxCtleC + Controlled by NnFlexPhyOvrdMask bit[4] +**/ + UINT8 NnFlexPhyRxCtleC; /** Offset 0x0080 - Platform Reserved Memory Size The minimum platform memory size required to pass control into DXE @@ -156,9 +212,35 @@ typedef struct { **/ UINT16 MemorySpdDataLen; -/** Offset 0x008A - Reserved +/** Offset 0x008A - NnFlex Override for PHY RxCtleRcmn + Controlled by NnFlexPhyOvrdMask bit[5] +**/ + UINT8 NnFlexPhyRxCtleRcmn; + +/** Offset 0x008B - NnFlex Override for PHY RxCtleEq + Controlled by NnFlexPhyOvrdMask bit[6] +**/ + UINT8 NnFlexPhyRxCtleEq; + +/** Offset 0x008C - NnFlex Override for PHY RxCtleTailCtl + Controlled by NnFlexPhyOvrdMask bit[7] +**/ + UINT8 NnFlexPhyRxCtleTailCtl; + +/** Offset 0x008D - NnFlex Override for LP5 Dfeq + Controlled by NnFlexDramOvrdMask bit[0], MR24 encoding **/ - UINT8 Reserved2[6]; + UINT8 NnFlexLpddr5Dfeq; + +/** Offset 0x008E - NnFlex Override for LP5 PdDrvStr + Controlled by NnFlexDramOvrdMask bit[1], MR3 encoding +**/ + UINT8 NnFlexLpddr5PdDrvStr; + +/** Offset 0x008F - NnFlex Override for LP5 SocOdt + Controlled by NnFlexDramOvrdMask bit[2], MR17 encoding +**/ + UINT8 NnFlexLpddr5SocOdt; /** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 @@ -1259,9 +1341,10 @@ typedef struct { **/ UINT8 IbeccProtectedRegionEnable[8]; -/** Offset 0x027D - Reserved +/** Offset 0x027D - NnFlex Override for LP5 PreEmpDn + Controlled by NnFlexDramOvrdMask bit[3], MR58 encoding **/ - UINT8 Reserved3; + UINT8 NnFlexLpddr5PreEmpDn; /** Offset 0x027E - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -1541,9 +1624,10 @@ typedef struct { **/ UINT8 SafeModeOverride; -/** Offset 0x02CB - Reserved +/** Offset 0x02CB - NnFlex Override for LP5 PreEmpUp + Controlled by NnFlexDramOvrdMask bit[4], MR58 encoding **/ - UINT8 Reserved4; + UINT8 NnFlexLpddr5PreEmpUp; /** Offset 0x02CC - IbeccEccInjAddrBase Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB @@ -1651,9 +1735,10 @@ typedef struct { **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x02E7 - Reserved +/** Offset 0x02E7 - NnFlex Override for LP5 WckDcaWr + Controlled by NnFlexDramOvrdMask bit[5], 4-bit 2's complement, valid range: [-7..7] **/ - UINT8 Reserved5; + UINT8 NnFlexLpddr5WckDcaWr; /** Offset 0x02E8 - Margin limit check L2 Margin limit check L2 threshold: 100=Default @@ -1789,9 +1874,94 @@ typedef struct { **/ UINT8 Lp5SafeSpeed; -/** Offset 0x031F - Reserved +/** Offset 0x031F - Force InternalClkOn + Force InternalClocksOn and TxPiOn to be set to 1 for frequencies >= 7467 + $EN_DIS +**/ + UINT8 ForceInternalClkOn; + +/** Offset 0x0320 - DIMM Rx Offset Calibration training + Enable/Disable DIMM Rx Offset Calibration training + $EN_DIS +**/ + UINT8 DIMMRXOFFSET; + +/** Offset 0x0321 - Enable Flexible Analog Settings + Enable/Disable Flexible Analog Settings + $EN_DIS +**/ + UINT8 FlexibleAnalogSettings; + +/** Offset 0x0322 - Force WRDSEQT at 2400 + Force Enable Write Drive Strength training at 2400 + $EN_DIS +**/ + UINT8 ForceWRDSEQT2400; + +/** Offset 0x0323 - NnFlex Override for LP5 WckDcaRd + Controlled by NnFlexDramOvrdMask bit[6], 4-bit 2's complement, valid range: [-7..7] +**/ + UINT8 NnFlexLpddr5WckDcaRd; + +/** Offset 0x0324 - NnFlex Override for LP5 RttNT + Controlled by NnFlexDramOvrdMask bit[7], MR41 encoding +**/ + UINT8 NnFlexLpddr5RttNT; + +/** Offset 0x0325 - NnFlex Override for DDR5 DfeTap1 + Controlled by NnFlexDramOvrdMask bit[0], 8-bit 2's complement, valid range: [-40..40] **/ - UINT8 Reserved6[16]; + UINT8 NnFlexDdr5DfeTap1; + +/** Offset 0x0326 - NnFlex Override for DDR5 DfeTap2 + Controlled by NnFlexDramOvrdMask bit[1], 8-bit 2's complement, valid range: [-15..15] +**/ + UINT8 NnFlexDdr5DfeTap2; + +/** Offset 0x0327 - NnFlex Override for DDR5 RttWr + Controlled by NnFlexDramOvrdMask bit[2], MR34 encoding +**/ + UINT8 NnFlexDdr5RttWr; + +/** Offset 0x0328 - NnFlex Override for DDR5 RttNomWr + Controlled by NnFlexDramOvrdMask bit[3], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomWr; + +/** Offset 0x0329 - NnFlex Override for DDR5 RttNomRd + Controlled by NnFlexDramOvrdMask bit[4], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomRd; + +/** Offset 0x032A - NnFlex Override for DDR5 RonUp + Controlled by NnFlexDramOvrdMask bit[5], MR5 encoding +**/ + UINT8 NnFlexDdr5RonUp; + +/** Offset 0x032B - NnFlex Override for DDR5 RonDn + Controlled by NnFlexDramOvrdMask bit[6], MR5 encoding +**/ + UINT8 NnFlexDdr5RonDn; + +/** Offset 0x032C - NnFlex Phy Override Enable bit mask + Bitmask to enable PHY NnFlex overrides. [0]: PhyRxEqTap0 [1]: PhyRxEqTap1 [2]: PhyDqTcoComp + [3]: PhyRxCtleR [4]: PhyRxCtleC [5]: PhyRxCtleRcmn [6]: PhyRxCtleEq [7]: PhyRxCtleTailCtl +**/ + UINT8 NnFlexPhyOvrdMask; + +/** Offset 0x032D - NnFlex LP5/DDR5 Override Enable bit mask + Bitmask to enable LP5/DDR5 NnFlex overrides. [0]: Lp5Dfeq/Ddr5DfeTap1 [1]: Lp5PdDrvStr/Ddr5DfeTap2 + [2]: Lp5SocOdt/Ddr5RttWr [3]: Lp5PreEmpDn/Ddr5RttNomWr [4]: Lp5PreEmpUp/Ddr5RttNomRd + [5]: Lp5WckDcaWr/Ddr5RonUp [6]: Lp5WckDcaRd/Ddr5RonDn [7]: Lp5RttNT +**/ + UINT8 NnFlexDramOvrdMask; + +/** Offset 0x032E - Force DIMM Rx Offset Calibration training + Force DIMM Rx Offset Calibration training for LPDDR5X, frequencies >= 6800: 0 = + Disable, 1 = Enable + $EN_DIS +**/ + UINT8 ForceDIMMRXOFFSET; /** Offset 0x032F - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -1945,7 +2115,7 @@ typedef struct { /** Offset 0x04D6 - Reserved **/ - UINT8 Reserved7[2]; + UINT8 Reserved1[2]; /** Offset 0x04D8 - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -1960,7 +2130,7 @@ typedef struct { /** Offset 0x04E1 - Reserved **/ - UINT8 Reserved8[3]; + UINT8 Reserved2[3]; /** Offset 0x04E4 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -2028,7 +2198,7 @@ typedef struct { /** Offset 0x0571 - Reserved **/ - UINT8 Reserved9[3]; + UINT8 Reserved3[3]; /** Offset 0x0574 - SoundWire Clk Pin Muxing (N - SoundWire number) Determines SoundWire Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_CLK* @@ -2069,7 +2239,7 @@ typedef struct { /** Offset 0x059F - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved4; /** Offset 0x05A0 - Audio Sub System IDs Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. @@ -2108,7 +2278,7 @@ typedef struct { /** Offset 0x05AA - Usage type for ClkSrc 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used -**/ +*/ UINT8 PcieClkSrcUsage[18]; /** Offset 0x05BC - ClkReq-to-ClkSrc mapping @@ -2118,7 +2288,7 @@ typedef struct { /** Offset 0x05CE - Reserved **/ - UINT8 Reserved11[14]; + UINT8 Reserved5[14]; /** Offset 0x05DC - Clk Req GPIO Pin Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. @@ -2139,7 +2309,7 @@ typedef struct { /** Offset 0x0601 - Reserved **/ - UINT8 Reserved12[3]; + UINT8 Reserved6[3]; /** Offset 0x0604 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode @@ -2220,7 +2390,7 @@ typedef struct { /** Offset 0x061B - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved7; /** Offset 0x061C - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2309,7 +2479,7 @@ typedef struct { /** Offset 0x062B - Reserved **/ - UINT8 Reserved14[5]; + UINT8 Reserved8[5]; /** Offset 0x0630 - FSPM Validation Pointer Point to FSPM Validation configuration structure @@ -2331,7 +2501,7 @@ typedef struct { /** Offset 0x063A - Reserved **/ - UINT8 Reserved15[2]; + UINT8 Reserved9[2]; /** Offset 0x063C - Extended BIOS Direct Read Decode Range base Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. @@ -2362,7 +2532,7 @@ typedef struct { /** Offset 0x0647 - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved10; /** Offset 0x0648 - SMBUS Base Address SMBUS Base Address (IO space). @@ -2377,7 +2547,7 @@ typedef struct { /** Offset 0x064B - Reserved **/ - UINT8 Reserved17[13]; + UINT8 Reserved11[13]; /** Offset 0x0658 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2584,7 +2754,7 @@ typedef struct { /** Offset 0x06EB - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved12; /** Offset 0x06EC - Per-core VF Offset Array used to specifies the selected Core Offset Voltage. This voltage is specified @@ -2612,7 +2782,7 @@ typedef struct { /** Offset 0x070D - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved13; /** Offset 0x070E - Per-core Voltage Override Array used to specifies the selected Core Voltage Override. @@ -2656,7 +2826,7 @@ typedef struct { /** Offset 0x0731 - Reserved **/ - UINT8 Reserved20; + UINT8 Reserved14; /** Offset 0x0732 - Ring VF Point Offset Array used to specifies the Ring Voltage Offset applied to the each selected VF @@ -2724,7 +2894,7 @@ typedef struct { /** Offset 0x0783 - Reserved **/ - UINT8 Reserved21[5]; + UINT8 Reserved15[5]; /** Offset 0x0788 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller @@ -2734,7 +2904,7 @@ typedef struct { /** Offset 0x0789 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved16; /** Offset 0x078A - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != @@ -2795,7 +2965,7 @@ typedef struct { /** Offset 0x0794 - Reserved **/ - UINT8 Reserved23[4]; + UINT8 Reserved17[4]; /** Offset 0x0798 - TME Exclude Base Address TME Exclude Base Address. @@ -2928,7 +3098,7 @@ typedef struct { /** Offset 0x07C5 - Reserved **/ - UINT8 Reserved24[3]; + UINT8 Reserved18[3]; /** Offset 0x07C8 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -2956,7 +3126,7 @@ typedef struct { /** Offset 0x07D2 - Reserved **/ - UINT8 Reserved25[2]; + UINT8 Reserved19[2]; /** Offset 0x07D4 - Platform PL1 power Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W @@ -3006,7 +3176,7 @@ typedef struct { /** Offset 0x07E7 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved20; /** Offset 0x07E8 - ISYS Current Limit L1 This field indicated the current limitiation of L1. Indicate current limit for which @@ -3022,7 +3192,7 @@ typedef struct { /** Offset 0x07EB - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved21; /** Offset 0x07EC - ISYS Current Limit L2 This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit @@ -3191,7 +3361,7 @@ typedef struct { /** Offset 0x0812 - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved22[2]; /** Offset 0x0814 - Package Long duration turbo mode power limit Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. @@ -3428,7 +3598,7 @@ typedef struct { /** Offset 0x08BA - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved23[2]; /** Offset 0x08BC - Imon offset correction IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, @@ -3506,7 +3676,7 @@ typedef struct { /** Offset 0x0922 - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved24[2]; /** Offset 0x0924 - Platform Psys offset correction PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed @@ -3555,9 +3725,11 @@ typedef struct { **/ UINT8 EcoreHysteresisWindow; -/** Offset 0x094B - Reserved +/** Offset 0x094B - VCCSA Shutdown + Enable/Disable VCCSA Shutdown hopping. 0: Disable; 1: Enable. + $EN_DIS **/ - UINT8 Reserved31; + UINT8 VccsaShutdown; /** Offset 0x094C - DLVR RFI Frequency DLVR RFI Frequency in MHz. 0: 2227 MHz , 1: 2140MHZ. @@ -3603,7 +3775,7 @@ typedef struct { /** Offset 0x0955 - Reserved **/ - UINT8 Reserved32; + UINT8 Reserved26; /** Offset 0x0956 - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -3628,7 +3800,7 @@ typedef struct { /** Offset 0x096E - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved27[2]; /** Offset 0x0970 - Vsys Full Scale Vsys Full Scale, Range is 0-255000mV @@ -3652,7 +3824,7 @@ typedef struct { /** Offset 0x0980 - Reserved **/ - UINT8 Reserved34[8]; + UINT8 Reserved28[8]; /** Offset 0x0988 - IOE Debug Enable Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock @@ -3694,7 +3866,7 @@ typedef struct { /** Offset 0x098E - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved29[2]; /** Offset 0x0990 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3731,7 +3903,7 @@ typedef struct { /** Offset 0x09BC - Reserved **/ - UINT8 Reserved36[4]; + UINT8 Reserved30[4]; /** Offset 0x09C0 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB @@ -3813,7 +3985,7 @@ typedef struct { /** Offset 0x09FA - Reserved **/ - UINT8 Reserved37[2]; + UINT8 Reserved31[2]; /** Offset 0x09FC - StreamTracer Mode Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended @@ -3858,7 +4030,7 @@ typedef struct { /** Offset 0x0A19 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved32; /** Offset 0x0A1A - Static Content at 4GB Location 0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, @@ -3888,7 +4060,7 @@ typedef struct { /** Offset 0x0A1E - Reserved **/ - UINT8 Reserved39[13]; + UINT8 Reserved33[13]; /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -3999,7 +4171,7 @@ typedef struct { /** Offset 0x0A3E - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved34[2]; /** Offset 0x0A40 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -4051,7 +4223,7 @@ typedef struct { /** Offset 0x0A56 - Reserved **/ - UINT8 Reserved41[2]; + UINT8 Reserved35[2]; /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image @@ -4060,7 +4232,7 @@ typedef struct { /** Offset 0x0A5C - Reserved **/ - UINT8 Reserved42[4]; + UINT8 Reserved36[4]; /** Offset 0x0A60 - Graphics Configuration Ptr Points to VBT @@ -4083,7 +4255,8 @@ typedef struct { BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5 - - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support) + - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White + Support), BIT6-7 - (0 : No Higher Cd Clock, 1 : 442 MHz, 2 : 461 MHz, 3 : Reserved) 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA **/ UINT8 VgaInitControl; @@ -4238,7 +4411,7 @@ typedef struct { /** Offset 0x0ACB - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved37; /** Offset 0x0ACC - Rx DQS Delay Comp Support Enables/Disable Rx DQS Delay Comp Support @@ -4248,7 +4421,7 @@ typedef struct { /** Offset 0x0ACD - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved38[2]; /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm Enables/Disable Mrc Failure On Unsupported Dimm @@ -4525,7 +4698,7 @@ typedef struct { /** Offset 0x0B09 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved39; /** Offset 0x0B0A - SubCh Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -4541,7 +4714,7 @@ typedef struct { /** Offset 0x0B0D - Reserved **/ - UINT8 Reserved46[3]; + UINT8 Reserved40[3]; /** Offset 0x0B10 - Disable Zq Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled @@ -4649,9 +4822,23 @@ typedef struct { **/ UINT16 VddqVoltage; -/** Offset 0x0B4A - Reserved +/** Offset 0x0B4A +**/ + UINT8 Reserved41[6]; +/** Offset 0x0B50 - Graphics Mode 12 Font Pointer + Pointer to VGA Mode 12 Font Data (8x16 character set).\n + Format: UINT8 array[256][16] where each character is 16 bytes (16 rows of 8 pixels).\n + Must be provided if VGA Mode 12 is enabled. +**/ + UINT64 GraphicsMode12FontPtr; +/** Offset 0x0B58 - MRC Error Key Value Table Pointer + Pointer to MRC Error Key Value Table. Table maps MRC error codes to error message + strings for display during memory init. See FSP_MRC_ERROR_KEY_VALUE_TABLE. +**/ + UINT64 MrcErrorKeyValueTablePtr; +/** Offset 0x0B60 **/ - UINT8 Reserved47[30]; + UINT8 Reserved42[8]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h index be67c19c806..051aa8c2ded 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2025, Intel Corporation. All rights reserved.
+Copyright (c) 2026, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h index e50c114e416..9c0edd55431 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h @@ -389,6 +389,9 @@ typedef struct { PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; BOOLEAN MrcBasicMemoryTestPass; + UINT8 Reserved1[3]; // Reserved for alignment + UINT64 BiosPeiMemoryBaseAddress; + UINT64 BiosPeiMemoryLength; } MEMORY_PLATFORM_DATA; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h index 50e13411f6b..8d0076237ec 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h @@ -50,6 +50,41 @@ typedef struct { UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table } CHIPSET_INIT_INFO; +/// +/// MRC Error Key Value Entry structure maps an MRC error code to an error message string. +/// +/* +// +// MRC Error Key Value Table Entries +// OEM can customize this table to display error messages on VGA display +// The Key is used to look up the error message, and the Value is the message string +// +// Message types: +// - MRC_NO_MEMORY_DETECTED (0xDF7E) - "NO MEMORY DETECTED" +// - MRC_MEM_INIT_DONE_WITH_ERRORS (0xDF55) - "BASIC MEMORY TEST FAILED" +// - 0xFFFF (Fallback) - "MRC FAILED, POST CODE: " + POST code in hex +// Any other MRC failure (SPD processing, PLL lock, calibration, training etc.) +// will use the fallback message with the actual POST code appended. +// +// Maximum message length (excluding null terminator): +// - Exact match messages (specific POST code keys): 80 characters +// - Fallback message (key 0xFFFF): 73 characters (+ "0xXXXX" appended automatically) +// +*/ +typedef struct { + UINT32 Key; ///< MRC POST code (16-bit value, 0xFFFF = fallback key) + CONST CHAR8 *Value; ///< MRC error message string +} FSP_MRC_ERROR_KEY_VALUE_ENTRY; + +/// +/// MRC Error Key Value Table contains array of error code to message mappings. +/// +typedef struct { + UINT32 Count; ///< Number of entries in Entry[] array + UINT32 Size; ///< Total size of table in bytes + FSP_MRC_ERROR_KEY_VALUE_ENTRY Entry[]; ///< Variable length array of key-value pairs +} FSP_MRC_ERROR_KEY_VALUE_TABLE; + /** Fsp M Configuration **/ @@ -67,9 +102,9 @@ typedef struct { **/ UINT8 SerialIoUartDebugAutoFlow; -/** Offset 0x0062 - Reserved +/** Offset 0x0062 **/ - UINT8 Reserved0[2]; + UINT8 FspmUpdRsvd0[2]; /** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -141,9 +176,30 @@ typedef struct { **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x007B - Reserved +/** Offset 0x007B - NnFlex Override for PHY RxEqTap0 + Controlled by NnFlexPhyOvrdMask bit[0], 6 bit 2's complement +**/ + UINT8 NnFlexPhyRxEqTap0; + +/** Offset 0x007C - NnFlex Override for PHY RxEqTap1 + Controlled by NnFlexPhyOvrdMask bit[1], 6 bit 2's complement, valid range: [-16..15] **/ - UINT8 Reserved1[5]; + UINT8 NnFlexPhyRxEqTap1; + +/** Offset 0x007D - NnFlex Override for PHY DqTcoComp + Controlled by NnFlexPhyOvrdMask bit[2], 6 bit 2's complement +**/ + UINT8 NnFlexPhyDqTcoComp; + +/** Offset 0x007E - NnFlex Override for PHY RxCtleR + Controlled by NnFlexPhyOvrdMask bit[3] +**/ + UINT8 NnFlexPhyRxCtleR; + +/** Offset 0x007F - NnFlex Override for PHY RxCtleC + Controlled by NnFlexPhyOvrdMask bit[4] +**/ + UINT8 NnFlexPhyRxCtleC; /** Offset 0x0080 - Platform Reserved Memory Size The minimum platform memory size required to pass control into DXE @@ -156,9 +212,35 @@ typedef struct { **/ UINT16 MemorySpdDataLen; -/** Offset 0x008A - Reserved +/** Offset 0x008A - NnFlex Override for PHY RxCtleRcmn + Controlled by NnFlexPhyOvrdMask bit[5] +**/ + UINT8 NnFlexPhyRxCtleRcmn; + +/** Offset 0x008B - NnFlex Override for PHY RxCtleEq + Controlled by NnFlexPhyOvrdMask bit[6] +**/ + UINT8 NnFlexPhyRxCtleEq; + +/** Offset 0x008C - NnFlex Override for PHY RxCtleTailCtl + Controlled by NnFlexPhyOvrdMask bit[7] **/ - UINT8 Reserved2[6]; + UINT8 NnFlexPhyRxCtleTailCtl; + +/** Offset 0x008D - NnFlex Override for LP5 Dfeq + Controlled by NnFlexDramOvrdMask bit[0], MR24 encoding +**/ + UINT8 NnFlexLpddr5Dfeq; + +/** Offset 0x008E - NnFlex Override for LP5 PdDrvStr + Controlled by NnFlexDramOvrdMask bit[1], MR3 encoding +**/ + UINT8 NnFlexLpddr5PdDrvStr; + +/** Offset 0x008F - NnFlex Override for LP5 SocOdt + Controlled by NnFlexDramOvrdMask bit[2], MR17 encoding +**/ + UINT8 NnFlexLpddr5SocOdt; /** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 @@ -1259,9 +1341,10 @@ typedef struct { **/ UINT8 IbeccProtectedRegionEnable[8]; -/** Offset 0x027D - Reserved +/** Offset 0x027D - NnFlex Override for LP5 PreEmpDn + Controlled by NnFlexDramOvrdMask bit[3], MR58 encoding **/ - UINT8 Reserved3; + UINT8 NnFlexLpddr5PreEmpDn; /** Offset 0x027E - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -1541,9 +1624,10 @@ typedef struct { **/ UINT8 SafeModeOverride; -/** Offset 0x02CB - Reserved +/** Offset 0x02CB - NnFlex Override for LP5 PreEmpUp + Controlled by NnFlexDramOvrdMask bit[4], MR58 encoding **/ - UINT8 Reserved4; + UINT8 NnFlexLpddr5PreEmpUp; /** Offset 0x02CC - IbeccEccInjAddrBase Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB @@ -1651,9 +1735,10 @@ typedef struct { **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x02E7 - Reserved +/** Offset 0x02E7 - NnFlex Override for LP5 WckDcaWr + Controlled by NnFlexDramOvrdMask bit[5], 4-bit 2's complement, valid range: [-7..7] **/ - UINT8 Reserved5; + UINT8 NnFlexLpddr5WckDcaWr; /** Offset 0x02E8 - Margin limit check L2 Margin limit check L2 threshold: 100=Default @@ -1801,9 +1886,82 @@ typedef struct { **/ UINT8 DIMMRXOFFSET; -/** Offset 0x0321 - Reserved +/** Offset 0x0321 - Enable Flexible Analog Settings + Enable/Disable Flexible Analog Settings + $EN_DIS +**/ + UINT8 FlexibleAnalogSettings; + +/** Offset 0x0322 - Force WRDSEQT at 2400 + Force Enable Write Drive Strength training at 2400 + $EN_DIS **/ - UINT8 Reserved6[14]; + UINT8 ForceWRDSEQT2400; + +/** Offset 0x0323 - NnFlex Override for LP5 WckDcaRd + Controlled by NnFlexDramOvrdMask bit[6], 4-bit 2's complement, valid range: [-7..7] +**/ + UINT8 NnFlexLpddr5WckDcaRd; + +/** Offset 0x0324 - NnFlex Override for LP5 RttNT + Controlled by NnFlexDramOvrdMask bit[7], MR41 encoding +**/ + UINT8 NnFlexLpddr5RttNT; + +/** Offset 0x0325 - NnFlex Override for DDR5 DfeTap1 + Controlled by NnFlexDramOvrdMask bit[0], 8-bit 2's complement, valid range: [-40..40] +**/ + UINT8 NnFlexDdr5DfeTap1; + +/** Offset 0x0326 - NnFlex Override for DDR5 DfeTap2 + Controlled by NnFlexDramOvrdMask bit[1], 8-bit 2's complement, valid range: [-15..15] +**/ + UINT8 NnFlexDdr5DfeTap2; + +/** Offset 0x0327 - NnFlex Override for DDR5 RttWr + Controlled by NnFlexDramOvrdMask bit[2], MR34 encoding +**/ + UINT8 NnFlexDdr5RttWr; + +/** Offset 0x0328 - NnFlex Override for DDR5 RttNomWr + Controlled by NnFlexDramOvrdMask bit[3], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomWr; + +/** Offset 0x0329 - NnFlex Override for DDR5 RttNomRd + Controlled by NnFlexDramOvrdMask bit[4], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomRd; + +/** Offset 0x032A - NnFlex Override for DDR5 RonUp + Controlled by NnFlexDramOvrdMask bit[5], MR5 encoding +**/ + UINT8 NnFlexDdr5RonUp; + +/** Offset 0x032B - NnFlex Override for DDR5 RonDn + Controlled by NnFlexDramOvrdMask bit[6], MR5 encoding +**/ + UINT8 NnFlexDdr5RonDn; + +/** Offset 0x032C - NnFlex Phy Override Enable bit mask + Bitmask to enable PHY NnFlex overrides. [0]: PhyRxEqTap0 [1]: PhyRxEqTap1 [2]: PhyDqTcoComp + [3]: PhyRxCtleR [4]: PhyRxCtleC [5]: PhyRxCtleRcmn [6]: PhyRxCtleEq [7]: PhyRxCtleTailCtl +**/ + UINT8 NnFlexPhyOvrdMask; + +/** Offset 0x032D - NnFlex LP5/DDR5 Override Enable bit mask + Bitmask to enable LP5/DDR5 NnFlex overrides. [0]: Lp5Dfeq/Ddr5DfeTap1 [1]: Lp5PdDrvStr/Ddr5DfeTap2 + [2]: Lp5SocOdt/Ddr5RttWr [3]: Lp5PreEmpDn/Ddr5RttNomWr [4]: Lp5PreEmpUp/Ddr5RttNomRd + [5]: Lp5WckDcaWr/Ddr5RonUp [6]: Lp5WckDcaRd/Ddr5RonDn [7]: Lp5RttNT +**/ + UINT8 NnFlexDramOvrdMask; + +/** Offset 0x032E - Force DIMM Rx Offset Calibration training + Force DIMM Rx Offset Calibration training for LPDDR5X, frequencies >= 6800: 0 = + Disable, 1 = Enable + $EN_DIS +**/ + UINT8 ForceDIMMRXOFFSET; /** Offset 0x032F - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -1955,9 +2113,9 @@ typedef struct { **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x04D6 - Reserved +/** Offset 0x04D6 **/ - UINT8 Reserved7[2]; + UINT8 FspmUpdRsvd1543[2]; /** Offset 0x04D8 - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -1970,9 +2128,9 @@ typedef struct { **/ UINT8 PchHdaDspEnable; -/** Offset 0x04E1 - Reserved +/** Offset 0x04E1 **/ - UINT8 Reserved8[3]; + UINT8 FspmUpdRsvd1554[3]; /** Offset 0x04E4 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -2038,9 +2196,21 @@ typedef struct { **/ UINT8 PchHdAudioSndwMultilaneEnable[2]; -/** Offset 0x0571 - Reserved +/** Offset 0x0571 - NnFlexCmdOvrdMask + Bitmask to enable CMD NnFlex overrides. [0]: CmdDrvVrefUp, [1]: CtlDrvVrefUp, [2]: + CmdCaTxEq, [3]: CtlDrvVrefDn +**/ + UINT8 NnFlexCmdOvrdMask; + +/** Offset 0x0572 - NnFlexCmdDrvVrefUp + Controlled by NnFlexCmdOvrdMask bit[0], [0..191] +**/ + UINT8 NnFlexCmdDrvVrefUp; + +/** Offset 0x0573 - NnFlexCtlDrvVrefUp + Controlled by NnFlexCmdOvrdMask bit[1], [0..191] **/ - UINT8 Reserved9[3]; + UINT8 NnFlexCtlDrvVrefUp; /** Offset 0x0574 - SoundWire Clk Pin Muxing (N - SoundWire number) Determines SoundWire Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_CLK* @@ -2079,9 +2249,9 @@ typedef struct { **/ UINT8 PchHdAudioSndwMultilaneSndwInterface[2]; -/** Offset 0x059F - Reserved +/** Offset 0x059F **/ - UINT8 Reserved10; + UINT8 FspmUpdRsvd11; /** Offset 0x05A0 - Audio Sub System IDs Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. @@ -2128,9 +2298,9 @@ typedef struct { **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x05CE - Reserved +/** Offset 0x05CE **/ - UINT8 Reserved11[14]; + UINT8 PcieClkSrcClkReqRsvd[14]; /** Offset 0x05DC - Clk Req GPIO Pin Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. @@ -2149,9 +2319,20 @@ typedef struct { **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x0601 - Reserved +/** Offset 0x0601 - NnFlexCmdCaTxEq + Controlled by NnFlexCmdOvrdMask bit[2], [0..31] +**/ + UINT8 NnFlexCmdCaTxEq; + +/** Offset 0x0602 - NnFlexCtlDrvVrefDn + Controlled by NnFlexCmdOvrdMask bit[3], [0..191] +**/ + UINT8 NnFlexCtlDrvVrefDn; + +/** Offset 0x0603 - FspmUpdRsvd12 + Reserved **/ - UINT8 Reserved12[3]; + UINT8 FspmUpdRsvd12; /** Offset 0x0604 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode @@ -2230,9 +2411,9 @@ typedef struct { **/ UINT8 FabricGVDisable; -/** Offset 0x061B - Reserved +/** Offset 0x061B **/ - UINT8 Reserved13; + UINT8 FspmUpdRsvd13[1]; /** Offset 0x061C - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2319,9 +2500,9 @@ typedef struct { **/ UINT8 I2cPostCodeEnable; -/** Offset 0x062B - Reserved +/** Offset 0x062B **/ - UINT8 Reserved14[5]; + UINT8 FspmUpdRsvd14[5]; /** Offset 0x0630 - FSPM Validation Pointer Point to FSPM Validation configuration structure @@ -2341,9 +2522,9 @@ typedef struct { **/ UINT8 PchSpiExtendedBiosDecodeRangeEnable; -/** Offset 0x063A - Reserved +/** Offset 0x063A **/ - UINT8 Reserved15[2]; + UINT8 FspmUpdRsvd15[2]; /** Offset 0x063C - Extended BIOS Direct Read Decode Range base Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. @@ -2372,9 +2553,9 @@ typedef struct { **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0647 - Reserved +/** Offset 0x0647 **/ - UINT8 Reserved16; + UINT8 FspmUpdRsvd16; /** Offset 0x0648 - SMBUS Base Address SMBUS Base Address (IO space). @@ -2387,9 +2568,14 @@ typedef struct { **/ UINT8 PchSmbAlertEnable; -/** Offset 0x064B - Reserved +/** Offset 0x064B **/ - UINT8 Reserved17[13]; + UINT8 FspmUpdRsvd17[5]; + +/** Offset 0x0650 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT64 RsvdSmbusAddressTablePtr; /** Offset 0x0658 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2594,9 +2780,9 @@ typedef struct { **/ UINT8 CoreVfConfigScope; -/** Offset 0x06EB - Reserved +/** Offset 0x06EB **/ - UINT8 Reserved18; + UINT8 FspmUpdRsvd18; /** Offset 0x06EC - Per-core VF Offset Array used to specifies the selected Core Offset Voltage. This voltage is specified @@ -2622,9 +2808,9 @@ typedef struct { **/ UINT8 PerCoreVoltageMode[8]; -/** Offset 0x070D - Reserved +/** Offset 0x070D **/ - UINT8 Reserved19; + UINT8 FspmUpdRsvd19; /** Offset 0x070E - Per-core Voltage Override Array used to specifies the selected Core Voltage Override. @@ -2666,9 +2852,9 @@ typedef struct { **/ UINT8 FllOverclockMode; -/** Offset 0x0731 - Reserved +/** Offset 0x0731 **/ - UINT8 Reserved20; + UINT8 FspmUpdRsvd20; /** Offset 0x0732 - Ring VF Point Offset Array used to specifies the Ring Voltage Offset applied to the each selected VF @@ -2734,9 +2920,11 @@ typedef struct { **/ UINT8 RingPllVoltageOffset; -/** Offset 0x0783 - Reserved +/** Offset 0x0783 - OcPreMemRsvd + Reserved for OC Pre-Mem + $EN_DIS **/ - UINT8 Reserved21[5]; + UINT8 OcPreMemRsvd[5]; /** Offset 0x0788 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller @@ -2744,9 +2932,9 @@ typedef struct { **/ UINT8 PchIshEnable; -/** Offset 0x0789 - Reserved +/** Offset 0x0789 **/ - UINT8 Reserved22; + UINT8 FspmUpdRsvd21; /** Offset 0x078A - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != @@ -2805,9 +2993,9 @@ typedef struct { **/ UINT8 GenerateNewTmeKey; -/** Offset 0x0794 - Reserved +/** Offset 0x0794 **/ - UINT8 Reserved23[4]; + UINT8 FspmUpdRsvd22[4]; /** Offset 0x0798 - TME Exclude Base Address TME Exclude Base Address. @@ -2938,9 +3126,9 @@ typedef struct { **/ UINT8 DfdEnable; -/** Offset 0x07C5 - Reserved +/** Offset 0x07C5 **/ - UINT8 Reserved24[3]; + UINT8 FspmUpdRsvd23[3]; /** Offset 0x07C8 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -2966,9 +3154,9 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x07D2 - Reserved +/** Offset 0x07D2 **/ - UINT8 Reserved25[2]; + UINT8 FspmUpdRsvd24[2]; /** Offset 0x07D4 - Platform PL1 power Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W @@ -3016,9 +3204,9 @@ typedef struct { **/ UINT8 ThETAIbattEnable; -/** Offset 0x07E7 - Reserved +/** Offset 0x07E7 **/ - UINT8 Reserved26; + UINT8 FspmUpdRsvd25; /** Offset 0x07E8 - ISYS Current Limit L1 This field indicated the current limitiation of L1. Indicate current limit for which @@ -3032,9 +3220,9 @@ typedef struct { **/ UINT8 IsysCurrentL1Tau; -/** Offset 0x07EB - Reserved +/** Offset 0x07EB **/ - UINT8 Reserved27; + UINT8 FspmUpdRsvd26; /** Offset 0x07EC - ISYS Current Limit L2 This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit @@ -3201,9 +3389,9 @@ typedef struct { **/ UINT8 PowerLimit1Time; -/** Offset 0x0812 - Reserved +/** Offset 0x0812 **/ - UINT8 Reserved28[2]; + UINT8 FspmUpdRsvd27[2]; /** Offset 0x0814 - Package Long duration turbo mode power limit Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. @@ -3438,9 +3626,9 @@ typedef struct { **/ UINT16 Ps3Threshold[6]; -/** Offset 0x08BA - Reserved +/** Offset 0x08BA **/ - UINT8 Reserved29[2]; + UINT8 FspmUpdRsvd28[2]; /** Offset 0x08BC - Imon offset correction IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, @@ -3516,9 +3704,9 @@ typedef struct { **/ UINT8 SlowSlewRate[6]; -/** Offset 0x0922 - Reserved +/** Offset 0x0922 **/ - UINT8 Reserved30[2]; + UINT8 FspmUpdRsvd29[2]; /** Offset 0x0924 - Platform Psys offset correction PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed @@ -3567,9 +3755,11 @@ typedef struct { **/ UINT8 EcoreHysteresisWindow; -/** Offset 0x094B - Reserved +/** Offset 0x094B - VCCSA Shutdown + Enable/Disable VCCSA Shutdown hopping. 0: Disable; 1: Enable. + $EN_DIS **/ - UINT8 Reserved31; + UINT8 VccsaShutdown; /** Offset 0x094C - DLVR RFI Frequency DLVR RFI Frequency in MHz. 0: 2227 MHz , 1: 2140MHZ. @@ -3613,9 +3803,9 @@ typedef struct { **/ UINT8 VsysDeassertionDeglitchExponent; -/** Offset 0x0955 - Reserved +/** Offset 0x0955 **/ - UINT8 Reserved32; + UINT8 FspmUpdRsvd31; /** Offset 0x0956 - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -3638,9 +3828,9 @@ typedef struct { **/ UINT8 CepEnable[6]; -/** Offset 0x096E - Reserved +/** Offset 0x096E **/ - UINT8 Reserved33[2]; + UINT8 FspmUpdRsvd48[2]; /** Offset 0x0970 - Vsys Full Scale Vsys Full Scale, Range is 0-255000mV @@ -3662,9 +3852,11 @@ typedef struct { **/ UINT32 PsysCriticalThreshold; -/** Offset 0x0980 - Reserved +/** Offset 0x0980 - CpuPmVrRsvd + Reserved for CPU Power Mgmt VR Config + $EN_DIS **/ - UINT8 Reserved34[8]; + UINT8 CpuPmVrRsvd[8]; /** Offset 0x0988 - IOE Debug Enable Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock @@ -3704,9 +3896,9 @@ typedef struct { **/ UINT8 PchTestDmiMeUmaRootSpaceCheck; -/** Offset 0x098E - Reserved +/** Offset 0x098E **/ - UINT8 Reserved35[2]; + UINT8 FspmUpdRsvd32[2]; /** Offset 0x0990 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3741,9 +3933,9 @@ typedef struct { **/ UINT32 VtdBaseAddress[9]; -/** Offset 0x09BC - Reserved +/** Offset 0x09BC **/ - UINT8 Reserved36[4]; + UINT8 FspmUpdRsvd34[4]; /** Offset 0x09C0 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB @@ -3823,9 +4015,9 @@ typedef struct { **/ UINT8 CridEnable; -/** Offset 0x09FA - Reserved +/** Offset 0x09FA **/ - UINT8 Reserved37[2]; + UINT8 FspmUpdRsvd35[2]; /** Offset 0x09FC - StreamTracer Mode Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended @@ -3868,9 +4060,9 @@ typedef struct { **/ UINT8 SiSkipOverrideBootModeWhenFwUpdate; -/** Offset 0x0A19 - Reserved +/** Offset 0x0A19 **/ - UINT8 Reserved38; + UINT8 FspmUpdRsvd36; /** Offset 0x0A1A - Static Content at 4GB Location 0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, @@ -3898,9 +4090,11 @@ typedef struct { **/ UINT8 CmosTxtOffset; -/** Offset 0x0A1E - Reserved +/** Offset 0x0A1E - SiPreMemRsvd + Reserved for SI Pre-Mem + $EN_DIS **/ - UINT8 Reserved39[13]; + UINT8 SiPreMemRsvd[13]; /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -4009,9 +4203,9 @@ typedef struct { **/ UINT8 OemT12DelayOverride; -/** Offset 0x0A3E - Reserved +/** Offset 0x0A3E **/ - UINT8 Reserved40[2]; + UINT8 FspmUpdRsvd37[2]; /** Offset 0x0A40 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -4061,18 +4255,18 @@ typedef struct { **/ UINT8 IGpuGsm2Size; -/** Offset 0x0A56 - Reserved +/** Offset 0x0A56 **/ - UINT8 Reserved41[2]; + UINT8 FspmUpdRsvd46[2]; /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image **/ UINT32 VbtSize; -/** Offset 0x0A5C - Reserved +/** Offset 0x0A5C **/ - UINT8 Reserved42[4]; + UINT8 FspmUpdRsvd47[4]; /** Offset 0x0A60 - Graphics Configuration Ptr Points to VBT @@ -4095,7 +4289,8 @@ typedef struct { BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5 - - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support) + - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White + Support), BIT6-7 - (0 : No Higher Cd Clock, 1 : 442 MHz, 2 : 461 MHz, 3 : Reserved) 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA **/ UINT8 VgaInitControl; @@ -4248,9 +4443,9 @@ typedef struct { **/ UINT8 WeaklockEn; -/** Offset 0x0ACB - Reserved +/** Offset 0x0ACB **/ - UINT8 Reserved43; + UINT8 FspmUpdRsvd39; /** Offset 0x0ACC - Rx DQS Delay Comp Support Enables/Disable Rx DQS Delay Comp Support @@ -4258,9 +4453,9 @@ typedef struct { **/ UINT8 RxDqsDelayCompEn; -/** Offset 0x0ACD - Reserved +/** Offset 0x0ACD **/ - UINT8 Reserved44[2]; + UINT8 FspmUpdRsvd336[2]; /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm Enables/Disable Mrc Failure On Unsupported Dimm @@ -4535,9 +4730,9 @@ typedef struct { **/ UINT8 SubChHashInterleaveBit; -/** Offset 0x0B09 - Reserved +/** Offset 0x0B09 **/ - UINT8 Reserved45; + UINT8 FspmUpdRsvd40; /** Offset 0x0B0A - SubCh Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -4551,9 +4746,9 @@ typedef struct { **/ UINT8 ForceCkdBypass; -/** Offset 0x0B0D - Reserved +/** Offset 0x0B0D **/ - UINT8 Reserved46[3]; + UINT8 FspmUpdRsvd41[3]; /** Offset 0x0B10 - Disable Zq Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled @@ -4661,9 +4856,30 @@ typedef struct { **/ UINT16 VddqVoltage; -/** Offset 0x0B4A - Reserved +/** Offset 0x0B4A +**/ + UINT8 FspmUpdRsvd50[6]; + +/** Offset 0x0B50 - Graphics Mode 12 Font Pointer + Pointer to VGA Mode 12 Font Data (8x16 character set).\n + Format: UINT8 array[256][16] where each character is 16 bytes (16 rows of 8 pixels).\n + Must be provided if VGA Mode 12 is enabled. +**/ + UINT64 GraphicsMode12FontPtr; + +/** Offset 0x0B58 - MRC Error Key Value Table Pointer + Pointer to MRC Error Key Value Table. Table maps MRC error codes to error message + strings for display during memory init. See FSP_MRC_ERROR_KEY_VALUE_TABLE. +**/ + UINT64 MrcErrorKeyValueTablePtr; + +/** Offset 0x0B60 +**/ + UINT8 FspmUpdRsvd49[5]; + +/** Offset 0x0B65 **/ - UINT8 Reserved47[30]; + UINT8 ReservedFspmUpd[3]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h index 051aa8c2ded..8bedfb309b7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h @@ -95,9 +95,9 @@ typedef struct { **/ UINT32 BiosGuardAttr; -/** Offset 0x0074 - Reserved +/** Offset 0x0074 **/ - UINT8 Reserved0[4]; + UINT8 FspsUpdRsvd0[4]; /** Offset 0x0078 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -160,9 +160,9 @@ typedef struct { **/ UINT8 PchEspiNmiEnableCs1; -/** Offset 0x0097 - Reserved +/** Offset 0x0097 **/ - UINT8 Reserved1; + UINT8 FspsUpdRsvd1; /** Offset 0x0098 - CpuBistData Pointer CPU BIST Data @@ -182,9 +182,9 @@ typedef struct { **/ UINT8 CpuCrashLogEnable; -/** Offset 0x00A9 - Reserved +/** Offset 0x00A9 **/ - UINT8 Reserved2[3]; + UINT8 FspsUpdRsvd2[3]; /** Offset 0x00AC - StreamTracer Mode Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended @@ -621,9 +621,9 @@ typedef struct { **/ UINT8 ITbtPcieTunnelingForUsb4; -/** Offset 0x0152 - Reserved +/** Offset 0x0152 **/ - UINT8 Reserved3[2]; + UINT8 FspsUpdRsvd3[2]; /** Offset 0x0154 - ITBTForcePowerOn Timeout value ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. @@ -647,9 +647,9 @@ typedef struct { **/ UINT8 Usb4CmMode; -/** Offset 0x015D - Reserved +/** Offset 0x015D **/ - UINT8 Reserved4[11]; + UINT8 FspsUpdRsvd4[11]; /** Offset 0x0168 - FSPS Validation Point to FSPS Validation configuration structure @@ -711,9 +711,9 @@ typedef struct { **/ UINT8 IaxEnable; -/** Offset 0x017B - Reserved +/** Offset 0x017B **/ - UINT8 Reserved5; + UINT8 FspsUpdRsvd5; /** Offset 0x017C - ISH GP GPIO Pin Muxing Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER @@ -974,9 +974,9 @@ typedef struct { **/ UINT8 PchIshI3cEnable[2]; -/** Offset 0x0279 - Reserved +/** Offset 0x0279 **/ - UINT8 Reserved6[3]; + UINT8 FspsUpdRsvd6[3]; /** Offset 0x027C - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will @@ -2200,9 +2200,9 @@ typedef struct { **/ UINT8 SerialIoLpssSpiMode[7]; -/** Offset 0x0E07 - Reserved +/** Offset 0x0E07 **/ - UINT8 Reserved7; + UINT8 FspsUpdRsvd8; /** Offset 0x0E08 - LPSS SPI MOSI Pin Muxing Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values. @@ -2243,9 +2243,9 @@ typedef struct { **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x0E71 - Reserved +/** Offset 0x0E71 **/ - UINT8 Reserved8[3]; + UINT8 FspsUpdRsvd9[3]; /** Offset 0x0E74 - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 @@ -2283,9 +2283,9 @@ typedef struct { **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0EBA - Reserved +/** Offset 0x0EBA **/ - UINT8 Reserved9[2]; + UINT8 FspsUpdRsvd10[2]; /** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -2323,9 +2323,9 @@ typedef struct { **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x0F26 - Reserved +/** Offset 0x0F26 **/ - UINT8 Reserved10[2]; + UINT8 FspsUpdRsvd11[2]; /** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for @@ -2352,9 +2352,9 @@ typedef struct { **/ UINT8 SerialIoI3cMode[3]; -/** Offset 0x0F73 - Reserved +/** Offset 0x0F73 **/ - UINT8 Reserved11; + UINT8 FspsUpdRsvd12; /** Offset 0x0F74 - Serial IO I3C SDA Pin Muxing Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for @@ -2369,9 +2369,9 @@ typedef struct { **/ UINT8 SerialIoI3cSdaPadTermination[3]; -/** Offset 0x0F83 - Reserved +/** Offset 0x0F83 **/ - UINT8 Reserved12; + UINT8 FspsUpdRsvd13; /** Offset 0x0F84 - Serial IO I3C SCL Pin Muxing Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for @@ -2386,9 +2386,9 @@ typedef struct { **/ UINT8 SerialIoI3cSclPadTermination[3]; -/** Offset 0x0F93 - Reserved +/** Offset 0x0F93 **/ - UINT8 Reserved13; + UINT8 FspsUpdRsvd14; /** Offset 0x0F94 - Serial IO I3C SCL FB Pin Muxing Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* @@ -2436,9 +2436,9 @@ typedef struct { **/ UINT8 VmdPortFunc[31]; -/** Offset 0x1021 - Reserved +/** Offset 0x1021 **/ - UINT8 Reserved14[7]; + UINT8 FspsUpdRsvd37[7]; /** Offset 0x1028 - VMD Variable VMD Variable Pointer. @@ -2472,9 +2472,9 @@ typedef struct { **/ UINT8 TcssTbtPerfBoost; -/** Offset 0x103E - Reserved +/** Offset 0x103E **/ - UINT8 Reserved15[2]; + UINT8 FspsUpdRsvd15[2]; /** Offset 0x1040 - TypeC port GPIO setting GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined @@ -2517,9 +2517,9 @@ typedef struct { **/ UINT8 PmcPdEnable; -/** Offset 0x107F - Reserved +/** Offset 0x107F **/ - UINT8 Reserved16; + UINT8 FspsUpdRsvd16; /** Offset 0x1080 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -2637,9 +2637,9 @@ typedef struct { **/ UINT8 TimestampTimerMode[2]; -/** Offset 0x10DA - Reserved +/** Offset 0x10DA **/ - UINT8 Reserved17[2]; + UINT8 FspsUpdRsvd17[2]; /** Offset 0x10DC - Touch Host Controller Display Frame Sync Period Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum @@ -2662,9 +2662,9 @@ typedef struct { **/ UINT8 ThcDsyncPad[2]; -/** Offset 0x10F6 - Reserved +/** Offset 0x10F6 **/ - UINT8 Reserved18[2]; + UINT8 FspsUpdRsvd18[2]; /** Offset 0x10F8 - Touch Host Controller Hid Over Spi Connection Speed Hid Over Spi Connection Speed - SPI Frequency @@ -2735,9 +2735,9 @@ typedef struct { **/ UINT8 ThcHidI2cAddressingMode[2]; -/** Offset 0x1156 - Reserved +/** Offset 0x1156 **/ - UINT8 Reserved19[2]; + UINT8 FspsUpdRsvd19[2]; /** Offset 0x1158 - Touch Host Controller Hid Over I2c Device Descriptor Address Hid Over I2c Device Descriptor Address @@ -2859,9 +2859,9 @@ typedef struct { **/ UINT16 ThcCustomizedSvid[2]; -/** Offset 0x11FE - Reserved +/** Offset 0x11FE **/ - UINT8 Reserved20[2]; + UINT8 FspsUpdRsvd38[2]; /** Offset 0x1200 - USB 3.1 Speed Selection Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 @@ -2888,9 +2888,11 @@ typedef struct { **/ UINT16 ThcHidI2cIntDelayValue[2]; -/** Offset 0x1210 - Reserved +/** Offset 0x1210 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS **/ - UINT8 Reserved21[9]; + UINT8 PchPostMemRsvd[9]; /** Offset 0x1219 - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable @@ -2949,9 +2951,9 @@ typedef struct { **/ UINT8 PchTsnEnable[4]; -/** Offset 0x122A - Reserved +/** Offset 0x122A **/ - UINT8 Reserved22[2]; + UINT16 FspsUpdRsvd20; /** Offset 0x122C - PCH TSN MAC Address High Bits Set TSN MAC Address High. @@ -3053,9 +3055,9 @@ typedef struct { **/ UINT8 PchXhciDwbEnable; -/** Offset 0x1286 - Reserved +/** Offset 0x1286 **/ - UINT8 Reserved23[2]; + UINT8 FspsUpdRsvd21[2]; /** Offset 0x1288 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -3225,9 +3227,11 @@ typedef struct { **/ UINT8 SseCommunication; -/** Offset 0x13AF - Reserved +/** Offset 0x13AF - MePostMemRestrictedRsvd + Reserved for ME Post-Mem Restricted + $EN_DIS **/ - UINT8 Reserved24[2]; + UINT8 MePostMemRestrictedRsvd[2]; /** Offset 0x13B1 - Enable/Disable NPU Device Enable(Default): Enable NPU Device, Disable: Disable NPU Device @@ -3278,9 +3282,9 @@ typedef struct { **/ UINT8 PchCanEnable[2]; -/** Offset 0x13BC - Reserved +/** Offset 0x13BC **/ - UINT8 Reserved25[4]; + UINT8 FspsUpdRsvd22[4]; /** Offset 0x13C0 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -3300,9 +3304,15 @@ typedef struct { **/ UINT8 DfxSkipBiosDone; -/** Offset 0x13CB - Reserved +/** Offset 0x13CB - SiPostMemRsvd + Reserved for SI Post-Mem + $EN_DIS +**/ + UINT8 SiPostMemRsvd[6]; + +/** Offset 0x13D1 **/ - UINT8 Reserved26[9]; + UINT8 FspsUpdRsvd23[3]; /** Offset 0x13D4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3314,9 +3324,9 @@ typedef struct { **/ UINT32 LogoPixelWidth; -/** Offset 0x13DC - Reserved +/** Offset 0x13DC **/ - UINT8 Reserved27[4]; + UINT8 FspsUpdRsvd24[4]; /** Offset 0x13E0 - Blt Buffer Address Address of Blt buffer @@ -3389,9 +3399,9 @@ typedef struct { **/ UINT8 Dev2IsGfxWorkstation; -/** Offset 0x13FA - Reserved +/** Offset 0x13FA **/ - UINT8 Reserved28[2]; + UINT8 FspsUpdRsvd25[2]; /** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image @@ -3410,9 +3420,9 @@ typedef struct { **/ UINT8 MaxActiveDisplays; -/** Offset 0x1402 - Reserved +/** Offset 0x1402 **/ - UINT8 Reserved29[2]; + UINT8 FspsUpdRsvd26[2]; /** Offset 0x1404 - HorizontalResolution for PEI Logo HorizontalResolution from PEIm Gfx for PEI Logo @@ -3424,9 +3434,16 @@ typedef struct { **/ UINT32 VerticalResolution; -/** Offset 0x140C - Reserved +/** Offset 0x140C - Power Floor Aggressive Media Throttling + SoC can divide the media PLL to lower SoC floor power (Default disabled). 0: Disable: + Aggressive Media Throttling will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorAggressiveMedia; + +/** Offset 0x140D **/ - UINT8 Reserved30[56]; + UINT8 FspsUpdRsvd388[55]; /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. @@ -3518,9 +3535,9 @@ typedef struct { **/ UINT8 PchFivrExtVnnRailSupportedVoltageStates; -/** Offset 0x1459 - Reserved +/** Offset 0x1459 **/ - UINT8 Reserved31; + UINT8 FspsUpdRsvd27; /** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 @@ -3579,9 +3596,9 @@ typedef struct { **/ UINT8 PchFivrDynPm; -/** Offset 0x1467 - Reserved +/** Offset 0x1467 **/ - UINT8 Reserved32; + UINT8 FspsUpdRsvd28; /** Offset 0x1468 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA @@ -3702,9 +3719,9 @@ typedef struct { **/ UINT8 SkipBtPreInit; -/** Offset 0x147F - Reserved +/** Offset 0x147F **/ - UINT8 Reserved33; + UINT8 FspsUpdRsvd29[1]; /** Offset 0x1480 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) @@ -3748,9 +3765,9 @@ typedef struct { **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x148D - Reserved +/** Offset 0x148D **/ - UINT8 Reserved34[3]; + UINT8 FspsUpdRsvd30[3]; /** Offset 0x1490 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. @@ -3824,9 +3841,9 @@ typedef struct { **/ UINT8 PchHdaMicPrivacyHwModeDmic; -/** Offset 0x14A3 - Reserved +/** Offset 0x14A3 **/ - UINT8 Reserved35; + UINT8 FspsUpdRsvd31; /** Offset 0x14A4 - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing. HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before @@ -3834,9 +3851,13 @@ typedef struct { **/ UINT32 PchHdaMicPrivacyTimeout; -/** Offset 0x14A8 - Reserved +/** Offset 0x14A8 +**/ + UINT8 PchHdaRsvd[5]; + +/** Offset 0x14AD **/ - UINT8 Reserved36[8]; + UINT8 FspsUpdRsvd32[3]; /** Offset 0x14B0 - Pointer to ChipsetInit Binary ChipsetInit Binary Pointer. @@ -3848,9 +3869,9 @@ typedef struct { **/ UINT32 ChipsetInitBinLen; -/** Offset 0x14BC - Reserved +/** Offset 0x14BC **/ - UINT8 Reserved37[4]; + UINT8 FspsUpdRsvd33[4]; /** Offset 0x14C0 - Pointer to NPHY Binary Nphy Binary Pointer. @@ -3862,9 +3883,9 @@ typedef struct { **/ UINT32 NphyBinLen; -/** Offset 0x14CC - Reserved +/** Offset 0x14CC **/ - UINT8 Reserved38[4]; + UINT8 FspsUpdRsvd34[4]; /** Offset 0x14D0 - Pointer to SYNPS PHY Binary Synps Binary Pointer. @@ -3890,9 +3911,13 @@ typedef struct { **/ UINT8 PmcWdtTimerEn; -/** Offset 0x14DE - Reserved +/** Offset 0x14DE +**/ + UINT8 FspsUpdRsvd35; + +/** Offset 0x14DF **/ - UINT8 Reserved39[2]; + UINT8 ReservedFspsUpd; } FSP_S_CONFIG; /** Fsp S UPD Configuration diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c index 0c0e59530bf..aabde49a7ab 100644 --- a/tests/commonlib/list-test.c +++ b/tests/commonlib/list-test.c @@ -154,15 +154,16 @@ static void test_list_remove_head(void **state) expect_assert_failure(list_remove(&head)); } -static void test_list_append(void **state) +static void test_list_append_and_pop(void **state) { - size_t idx; + int idx; struct test_container *node; struct list_node head = {}; struct test_container nodes[] = { {1}, {2}, {3} }; + /* Append nodes. */ for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx) list_append(&nodes[idx].list_node, &head); @@ -174,6 +175,15 @@ static void test_list_append(void **state) assert_int_equal(3, idx); assert_int_equal(3, list_length(&head)); + + /* Pop nodes. */ + for (idx = ARRAY_SIZE(nodes) - 1; idx >= 0; idx--) { + struct list_node *last = list_pop(&head); + assert_non_null(last); + assert_ptr_equal(last, &nodes[idx].list_node); + } + + assert_null(list_pop(&head)); } static void test_list_move(void **state) @@ -237,7 +247,7 @@ int main(void) cmocka_unit_test(test_list_insert_before_head), cmocka_unit_test(test_list_remove), cmocka_unit_test(test_list_remove_head), - cmocka_unit_test(test_list_append), + cmocka_unit_test(test_list_append_and_pop), cmocka_unit_test(test_list_move), cmocka_unit_test(test_list_move_empty), cmocka_unit_test(test_list_move_invalid), diff --git a/util/amdfwtool/Makefile.mk b/util/amdfwtool/Makefile.mk index 0b9cc1b644b..95e960128c0 100644 --- a/util/amdfwtool/Makefile.mk +++ b/util/amdfwtool/Makefile.mk @@ -2,7 +2,7 @@ ifneq ($(BUILD_ALL_TOOLS)$(CONFIG_USE_AMDFWTOOL),) -amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o +amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o soc.o amdfwreadobj = amdfwread.o amdfwheader = amdfwtool.h @@ -10,6 +10,7 @@ WERROR ?= -Werror AMDFWTOOLCFLAGS :=-O2 -Wall -Wextra -Wshadow $(WERROR) AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include AMDFWTOOLCFLAGS += -D_GNU_SOURCE # memmem() from string.h +AMDFWTOOLCFLAGS += -ffunction-sections -fdata-sections ifneq ($(PKG_CONFIG),) HOSTPKGCONFIG ?= $(PKG_CONFIG) @@ -21,7 +22,7 @@ AMDFWTOOLCFLAGS += $(shell $(HOSTPKGCONFIG) --cflags libcrypto) ifneq ($(.SHELLSTATUS),0) $(error "Ensure that pkg-config is installed.") endif -LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto) +LDFLAGS += $(shell $(HOSTPKGCONFIG) --libs libcrypto) -Wl,-gc-sections $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c $(dir)/$(amdfwheader) printf " AMDFW $@\n" diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index 4dde162cd3c..2c511fd602f 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -8,8 +8,6 @@ #include #include "amdfwtool.h" -#define FILE_REL_MASK 0xffffff - #define ERR(...) fprintf(stderr, __VA_ARGS__) enum spi_frequency { @@ -35,12 +33,38 @@ enum spi_read_mode { /* Possible locations for the header */ const uint32_t fw_header_offsets[] = { 0xfa0000, + 0xf20000, 0xe20000, 0xc20000, 0x820000, 0x020000, }; +/* Possible locations for the header on 8 MiB ROM */ +const uint32_t fw_header_offsets_8MiB[] = { + 0x7A0000, + 0x720000, + 0x620000, + 0x420000, + 0x020000, +}; + +/* Possible locations for the header on 4 MiB ROM */ +const uint32_t fw_header_offsets_4MiB[] = { + 0x3A0000, + 0x320000, + 0x220000, + 0x020000, +}; + +/* Size of the FW in bytes */ +static uint32_t rom_size; + +static uint32_t file_rel_mask(uint32_t addr) +{ + return addr & (rom_size - 1); +} + /* Converts addresses to be relative to the start of the file */ static uint64_t relative_offset(uint32_t header_offset, uint64_t addr, uint64_t mode) { @@ -48,18 +72,19 @@ static uint64_t relative_offset(uint32_t header_offset, uint64_t addr, uint64_t /* Since this utility operates on the BIOS file, physical address is converted relative to the start of the BIOS file. */ case AMD_ADDR_PHYSICAL: - if (addr < SPI_ROM_BASE || addr > (SPI_ROM_BASE + FILE_REL_MASK)) { + if (addr < MAX(SPI_ROM_BASE, 0xffffffff - rom_size + 1) || + addr > 0xffffffff) { ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode); exit(1); } - return addr & FILE_REL_MASK; + return file_rel_mask(addr); case AMD_ADDR_REL_BIOS: - if (addr > FILE_REL_MASK) { + if (addr >= rom_size) { ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode); exit(1); } - return addr & FILE_REL_MASK; + return file_rel_mask(addr); case AMD_ADDR_REL_TAB: return addr + header_offset; @@ -95,11 +120,24 @@ static int read_fw_header(FILE *fw, uint32_t offset, embedded_firmware *fw_heade return fw_header->signature != EMBEDDED_FW_SIGNATURE; } +/* Returns true if there's a PSP directory with the expected cookie */ +static bool test_if_psp_directory(FILE *fw, uint32_t offset, uint32_t expected_cookie) +{ + psp_directory_header header; + offset = file_rel_mask(offset); + + if (read_header(fw, offset, &header, sizeof(psp_directory_header))) { + ERR("Failed to read PSP header\n"); + return false; + } + return header.cookie == expected_cookie; +} + static int read_psp_directory(FILE *fw, uint32_t offset, uint32_t expected_cookie, psp_directory_header *header, psp_directory_entry **entries, size_t *num_entries) { - offset &= FILE_REL_MASK; + offset = file_rel_mask(offset); if (read_header(fw, offset, header, sizeof(psp_directory_header))) { ERR("Failed to read PSP header\n"); @@ -130,14 +168,14 @@ static int read_psp_directory(FILE *fw, uint32_t offset, uint32_t expected_cooki static int read_ish_directory(FILE *fw, uint32_t offset, ish_directory_table *table) { - return read_header(fw, offset & FILE_REL_MASK, table, sizeof(*table)); + return read_header(fw, file_rel_mask(offset), table, sizeof(*table)); } static int read_bios_directory(FILE *fw, uint32_t offset, uint32_t expected_cookie, bios_directory_hdr *header, bios_directory_entry **entries, size_t *num_entries) { - offset &= FILE_REL_MASK; + offset = file_rel_mask(offset); if (read_header(fw, offset, header, sizeof(bios_directory_hdr))) { ERR("Failed to read BIOS header\n"); @@ -195,14 +233,14 @@ static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) uint64_t fuse; switch (type) { - case AMD_PSP_FUSE_CHAIN: + case AMD_FW_PSP_FUSE_CHAIN: fuse = mode << 62 | addr; printf("Soft-fuse:0x%lx\n", fuse); free(current_entries); return 0; - case AMD_FW_L2_PTR: + case AMD_FW_PSP_L2_PTR: /* There's a second level PSP directory to read */ if (l2_dir_offset != 0) { ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", @@ -214,7 +252,7 @@ static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) l2_dir_offset = relative_offset(psp_offset, addr, mode); break; - case AMD_FW_RECOVERYAB_A: + case AMD_FW_PSP_RECOVERYAB_A: if (l2_dir_offset != 0) { ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", l2_dir_offset); @@ -222,7 +260,7 @@ static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) return 1; } - ish_dir_offset = relative_offset(psp_offset, addr, mode); + ish_dir_offset = relative_offset(psp_offset, addr, AMD_ADDR_REL_BIOS); if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { ERR("Error reading ISH directory\n"); free(current_entries); @@ -258,6 +296,7 @@ static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) #define MAX_INDENTATION_LEN (MAX_NUM_LEVELS * MAX_INDENT_PER_LEVEL + 1) static void do_indentation_string(char *dest, uint8_t level) { + dest[0] = '\0'; for (uint8_t i = 0; i < level && i < MAX_NUM_LEVELS; i++) strcat(dest, " "); strcat(dest, "+-->"); @@ -344,7 +383,7 @@ static int amdfw_psp_dir_size(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui else *size = header.additional_info_fields.dir_size; - *size *= TABLE_ALIGNMENT; + *size *= TABLE_GRANULARITY; return 0; } @@ -373,7 +412,7 @@ static int amdfw_bios_dir_size(FILE *fw, uint32_t bios_offset, uint32_t cookie, else *size = header.additional_info_fields.dir_size; - *size *= TABLE_ALIGNMENT; + *size *= TABLE_GRANULARITY; return 0; } @@ -382,7 +421,7 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui psp_directory_entry *current_entries = NULL; size_t num_current_entries = 0; psp_directory_header header; - uint32_t l2_dir_offset = 0; + uint32_t l2_dir_offset = 0, l2b_dir_offset = 0; uint32_t bios_dir_offset = 0; uint32_t ish_dir_offset = 0; ish_directory_table ish_dir; @@ -408,7 +447,11 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui if (dir_mode < AMD_ADDR_REL_TAB) mode = dir_mode; - if (type == AMD_PSP_FUSE_CHAIN) + /* RECOVERY_AB is always relative to BIOS */ + if (type == AMD_FW_PSP_RECOVERYAB_B || type == AMD_FW_PSP_RECOVERYAB_A) + mode = AMD_ADDR_REL_BIOS; + + if (type == AMD_FW_PSP_FUSE_CHAIN) printf("%sPSP%s: 0x%02x 0x%lx(Soft-fuse)\n", indent, cookie == PSP_COOKIE ? "L1" : "L2", type, (uint64_t)current_entries[i].address_mode << 62 | addr); @@ -419,7 +462,7 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui current_entries[i].size); switch (type) { - case AMD_FW_L2_PTR: + case AMD_FW_PSP_L2_PTR: /* There's a second level PSP directory to read */ if (l2_dir_offset != 0) { ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", @@ -437,7 +480,44 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2); break; - case AMD_FW_RECOVERYAB_A: + case AMD_FW_PSP_RECOVERYAB_B: + if (l2b_dir_offset != 0) { + ERR("Duplicate PSP L2B Entry, prior offset: %08x\n", + l2b_dir_offset); + free(current_entries); + return 1; + } + + ish_dir_offset = relative_offset(psp_offset, addr, AMD_ADDR_REL_BIOS); + /* Test if it points to PSP L2 */ + if (test_if_psp_directory(fw, ish_dir_offset, PSPL2_COOKIE)) { + /* Legacy A/B recovery has no ISH */ + l2b_dir_offset = ish_dir_offset; + } else { + /* Newer platforms use ISH for A/B recovery */ + if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { + ERR("Error reading ISH directory\n"); + free(current_entries); + return 1; + } + do_indentation_string(indent, level); + printf(" %sISHB: PSPID 0x%08x\n", indent, ish_dir.psp_id); + do_indentation_string(indent, level+1); + + l2b_dir_offset = ish_dir.pl2_location; + } + + if (amdfw_psp_dir_size(fw, l2b_dir_offset, PSPL2_COOKIE, &dir_size) == 0) + printf(" %sPSPL2(B): Dir [0x%08x-0x%08x)\n", indent, l2b_dir_offset, l2b_dir_offset + dir_size); + else + printf(" %sPSPL2(B): Dir @0x%08x\n", indent, l2b_dir_offset); + amdfw_psp_dir_walk(fw, l2b_dir_offset, PSPL2_COOKIE, level + 3); + + do_indentation_string(indent, level); + + break; + + case AMD_FW_PSP_RECOVERYAB_A: if (l2_dir_offset != 0) { ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", l2_dir_offset); @@ -445,22 +525,34 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui return 1; } - ish_dir_offset = relative_offset(psp_offset, addr, mode); - if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { - ERR("Error reading ISH directory\n"); - free(current_entries); - return 1; + ish_dir_offset = relative_offset(psp_offset, addr, AMD_ADDR_REL_BIOS); + /* Test if it points to PSP L2 */ + if (test_if_psp_directory(fw, ish_dir_offset, PSPL2_COOKIE)) { + /* Legacy A/B recovery has no ISH */ + l2_dir_offset = ish_dir_offset; + } else { + /* Newer platforms use ISH for A/B recovery */ + if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { + ERR("Error reading ISH directory\n"); + free(current_entries); + return 1; + } + do_indentation_string(indent, level); + printf(" %sISHA: PSPID 0x%08x\n", indent, ish_dir.psp_id); + do_indentation_string(indent, level+1); + + l2_dir_offset = ish_dir.pl2_location; } - l2_dir_offset = ish_dir.pl2_location; if (amdfw_psp_dir_size(fw, l2_dir_offset, PSPL2_COOKIE, &dir_size) == 0) printf(" %sPSPL2: Dir [0x%08x-0x%08x)\n", indent, l2_dir_offset, l2_dir_offset + dir_size); else printf(" %sPSPL2: Dir @0x%08x\n", indent, l2_dir_offset); - amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2); + amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 3); + do_indentation_string(indent, level); break; - case AMD_FW_BIOS_TABLE: + case AMD_FW_PSP_BIOS_TABLE: bios_dir_offset = relative_offset(psp_offset, addr, mode); if (amdfw_bios_dir_size(fw, bios_dir_offset, BHDL2_COOKIE, &dir_size) == 0) printf(" %sBIOSL2: Dir [0x%08x-0x%08x)\n", indent, bios_dir_offset, bios_dir_offset + dir_size); @@ -638,6 +730,7 @@ int main(int argc, char **argv) { char *fw_file = NULL; int mode_dump = 0; + ssize_t fw_size; int selected_functions = 0; while (1) { @@ -679,13 +772,44 @@ int main(int argc, char **argv) return 1; } + /* Get file size */ + fseek(fw, 0, SEEK_END); + if ((fw_size = ftell(fw)) == -1) { + ERR("Failed to get FW file size\n"); + fclose(fw); + return -1; + } + if (fw_size > 128 * MiB) { + ERR("FW ROM size 0x%zx not supported\n", fw_size); + fclose(fw); + return -1; + } + fseek(fw, 0, SEEK_SET); + rom_size = fw_size; + /* Find the FW header by checking each possible location */ embedded_firmware fw_header; int found_header = 0; - for (size_t i = 0; i < ARRAY_SIZE(fw_header_offsets); i++) { - if (read_fw_header(fw, fw_header_offsets[i], &fw_header) == 0) { - found_header = 1; - break; + if (rom_size <= 4 * MiB) { + for (size_t i = 0; i < ARRAY_SIZE(fw_header_offsets_4MiB); i++) { + if (read_fw_header(fw, fw_header_offsets_4MiB[i], &fw_header) == 0) { + found_header = 1; + break; + } + } + } else if (rom_size <= 8 * MiB) { + for (size_t i = 0; i < ARRAY_SIZE(fw_header_offsets_8MiB); i++) { + if (read_fw_header(fw, fw_header_offsets_8MiB[i], &fw_header) == 0) { + found_header = 1; + break; + } + } + } else { + for (size_t i = 0; i < ARRAY_SIZE(fw_header_offsets); i++) { + if (read_fw_header(fw, fw_header_offsets[i], &fw_header) == 0) { + found_header = 1; + break; + } } } diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 15d2926fd3e..11bb90967cb 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -68,7 +68,7 @@ * +------------+---------------+----------------+------------+ * BDT Combo is similar */ - +#include #include #include #include @@ -85,28 +85,9 @@ #include "amdfwtool.h" -#define AMD_ROMSIG_OFFSET 0x20000 - #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) static void output_manifest(int manifest_fd, amd_fw_entry *fw_entry); - -/* - * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP - * can support an optional "combo" implementation. If the PSP sees the - * PSP2 cookie, it interprets the table as a roadmap to additional PSP - * tables. Using this, support for multiple product generations may be - * built into one image. If the PSP$ cookie is found, the table is a - * normal directory table. - * - * Modern generations supporting the combo directories require the - * pointer to be at offset 0x14 of the Embedded Firmware Structure, - * regardless of the type of directory used. The --use-combo - * argument enforces this placement. - * - * TODO: Future work may require fully implementing the PSP_COMBO feature. - */ - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -175,111 +156,114 @@ amd_fw_entry amd_psp_fw_table[] = { .skip_hashing = true }, { .type = AMD_FW_PSP_TEEIPKEY, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, - { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_HW_IPCFG, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, - { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB, + { .type = AMD_FW_PSP_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_HW_IPCFG, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_PSP_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL0, .level = PSP_BOTH | PSP_LVL2_AB, .generate_manifest = true }, - { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DXIO, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_BIOS_TABLE, .level = PSP_LVL2_AB }, + { .type = AMD_FW_PSP_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MSMU, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MSMU, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MSMU, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MSMU, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AB_NVRAM, .level = PSP_LVL1_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB, .generate_manifest = true }, - { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_RIB, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, - { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MFD_MPM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MFD_MPM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_WLAN, .inst = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_WLAN, .inst = 3, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MPCCX, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MPCCX, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_GFXIMU_0, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_GFXIMU_0, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_GFXIMU_1, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_GFXIMU_1, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_S3IMG, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_USB4, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_INVALID }, + { .type = AMD_FW_PSP_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_RIB, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_PSP_SFDR, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MFD_MPM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MFD_MPM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_WLAN, .inst = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_WLAN, .inst = 3, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MPCCX, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MPCCX, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_GFXIMU_0, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_GFXIMU_0, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_GFXIMU_1, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_GFXIMU_1, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_S3IMG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_USB4, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_INVALID }, }; amd_fw_entry amd_fw_table[] = { - { .type = AMD_FW_XHCI }, - { .type = AMD_FW_IMC }, - { .type = AMD_FW_GEC }, - { .type = AMD_FW_INVALID }, + { .type = AMD_FW_PSP_XHCI }, + { .type = AMD_FW_PSP_IMC }, + { .type = AMD_FW_PSP_GEC }, + { .type = AMD_FW_PSP_INVALID }, }; amd_bios_entry amd_bios_table[] = { @@ -400,30 +384,35 @@ amd_bios_entry amd_bios_table[] = { #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) -#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) /* AMD PSP Spec: Only set the address mode in entry if the table is mode 2 or 3. */ /* For address mode 3, it is not be used in any SOC family yet. For address mode 1, we can use it to store and transfer the address mode. It can reduce the complexity. */ #define SET_ADDR_MODE(table, mode) \ + ( \ + ((table)->header.additional_info_fields.version == 0) ? ( \ ((table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_TAB || \ (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_BIOS || \ (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_SLOT \ - ? (mode) : 0) + ? (mode) : 0)) : ( \ + ((table)->header.additional_info_fields_v1.address_mode == AMD_ADDR_REL_TAB || \ + (table)->header.additional_info_fields_v1.address_mode == AMD_ADDR_REL_BIOS || \ + (table)->header.additional_info_fields_v1.address_mode == AMD_ADDR_REL_SLOT \ + ? (mode) : 0)) \ + ) + #define SET_ADDR_MODE_BY_TABLE(table) \ - SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) + SET_ADDR_MODE((table), (((table)->header.additional_info_fields.version == 0) ? \ + (table)->header.additional_info_fields.address_mode : \ + (table)->header.additional_info_fields_v1.address_mode)) static void free_psp_firmware_filenames(amd_fw_entry *fw_table) { amd_fw_entry *index; - for (index = fw_table; index->type != AMD_FW_INVALID; index++) { - if (index->filename && - index->type != AMD_FW_VERSTAGE_SIG && - index->type != AMD_FW_PSP_VERSTAGE && - index->type != AMD_FW_SPL && - index->type != AMD_FW_PSP_WHITELIST) { + for (index = fw_table; index->type != AMD_FW_PSP_INVALID; index++) { + if (index->filename) { free(index->filename); index->filename = NULL; } @@ -435,11 +424,7 @@ static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) amd_bios_entry *index; for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { - if (index->filename && - index->type != AMD_BIOS_APCB && - index->type != AMD_BIOS_BIN && - index->type != AMD_BIOS_APCB_BK && - index->type != AMD_BIOS_UCODE) { + if (index->filename) { free(index->filename); index->filename = NULL; } @@ -497,31 +482,46 @@ static void adjust_current_pointer(context *ctx, uint32_t add, uint32_t align) set_current_pointer(ctx, ALIGN_UP(ctx->current + add, align)); } -static void *new_psp_dir(context *ctx, int multi, uint32_t cookie) +static void *new_psp_dir(context *ctx, const amd_cb_config *cb_config, + const uint32_t cookie) { - void *ptr; + psp_directory_header *psp; /* * Force both onto boundary when multi. Primary table is after * updatable table, so alignment ensures primary can stay intact * if secondary is reprogrammed. */ - if (multi) + if (platform_is_multi_level(cb_config->soc_id)) adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT); else adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); - ptr = BUFF_CURRENT(*ctx); - ((psp_directory_header *)ptr)->cookie = cookie; - ((psp_directory_header *)ptr)->num_entries = 0; - ((psp_directory_header *)ptr)->additional_info = 0; - ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; - ((psp_directory_header *)ptr)->additional_info_fields.spi_block_size = 1; - ((psp_directory_header *)ptr)->additional_info_fields.base_addr = 0; + psp = (psp_directory_header *)BUFF_CURRENT(*ctx); + + psp->cookie = cookie; + psp->num_entries = 0; + psp->additional_info = 0; + + /* Updated in fill_dir_header() after filling the table. */ + if (platform_has_dir_header_v1(cb_config->soc_id)) { + psp->additional_info_fields_v1.version = 1; + psp->additional_info_fields_v1.dir_size = 0; + psp->additional_info_fields_v1.spi_block_size = 0; + psp->additional_info_fields_v1.dir_hdr_size = 0; + psp->additional_info_fields_v1.address_mode = ctx->address_mode; + } else { + psp->additional_info_fields.version = 0; + psp->additional_info_fields.dir_size = 0; + psp->additional_info_fields.spi_block_size = 1; + psp->additional_info_fields.address_mode = ctx->address_mode; + psp->additional_info_fields.base_addr = 0; + } + adjust_current_pointer(ctx, sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry), 1); - return ptr; + return psp; } static void *new_ish_dir(context *ctx) @@ -529,57 +529,47 @@ static void *new_ish_dir(context *ctx) void *ptr; adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); - adjust_current_pointer(ctx, TABLE_ALIGNMENT, 1); + adjust_current_pointer(ctx, TABLE_GRANULARITY, 1); return ptr; } -static void *new_combo_dir(context *ctx, uint32_t cookie) +static void copy_psp_header(void *bak, void *orig) { - void *ptr; - - adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); - ptr = BUFF_CURRENT(*ctx); - ((psp_combo_header *)ptr)->cookie = cookie; - /* lookup mode is hardcoded for now. */ - ((psp_combo_header *)ptr)->lookup = 1; - ((psp_combo_header *)ptr)->reserved[0] = 0; - ((psp_combo_header *)ptr)->reserved[1] = 0; + uint32_t count = ((psp_directory_header *)orig)->num_entries; + memcpy(bak, orig, count * sizeof(bios_directory_entry) + sizeof(psp_directory_table)); +} - adjust_current_pointer(ctx, - sizeof(psp_combo_header) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry), - 1); - return ptr; +/** + * Returns the Additional Info Field struct version number part of the PSP header. + * Currently support: 0, 1 + */ +static uint8_t psp_directory_aif_version(const psp_directory_table *dir) +{ + return dir->header.additional_info_fields_v1.version; } -/* - * For some SOC generations the APOB_NV binary seems to be treated special regarding the - * interpretaion of the source address. No matter the address_mode specified for the address - * the memory ABL always seems to the interpret the source address as MMIO address even if - * AMD_ADDR_REL_BIOS is specified. So for them we need to always use an MMIO address. - * This seems to be a bug which affects all SOCs before phoenix generation. +/** + * Returns the Additional Info Field struct version number part of the BDT header. + * Currently support: 0, 1 */ -static bool has_apob_nv_quirk(enum platform platform_type) +static uint8_t bdt_directory_aif_version(const bios_directory_table *dir) { - switch (platform_type) { - case PLATFORM_CARRIZO: - case PLATFORM_STONEYRIDGE: - case PLATFORM_RAVEN: - case PLATFORM_PICASSO: - case PLATFORM_RENOIR: - case PLATFORM_CEZANNE: - case PLATFORM_MENDOCINO: - case PLATFORM_LUCIENNE: - return true; - default: - return false; - } + return dir->header.additional_info_fields_v1.version; } -static void copy_psp_header(void *bak, void *orig) +static int psp_directory_size_from_aif(const psp_directory_table *dir) { - uint32_t count = ((psp_directory_header *)orig)->num_entries; - memcpy(bak, orig, count * sizeof(bios_directory_entry) + sizeof(psp_directory_table)); + if (psp_directory_aif_version(dir) == 1) + return dir->header.additional_info_fields_v1.dir_size * TABLE_GRANULARITY; + return dir->header.additional_info_fields.dir_size * TABLE_GRANULARITY; +} + +static int bdt_directory_size_from_aif(const bios_directory_table *dir) +{ + if (bdt_directory_aif_version(dir) == 1) + return dir->header.additional_info_fields_v1.dir_size * TABLE_GRANULARITY; + return dir->header.additional_info_fields.dir_size * TABLE_GRANULARITY; } static void fill_dir_header(void *directory, uint32_t count, context *ctx) @@ -614,16 +604,20 @@ static void fill_dir_header(void *directory, uint32_t count, context *ctx) case PSPL2_COOKIE: /* The table size is only set once. Later calls only update * the count and fletcher. So does the BIOS table. */ - if (dir->header.additional_info_fields.dir_size == 0) { + if (psp_directory_size_from_aif(dir) == 0) { table_size = ctx->current - ctx->current_table; - if ((table_size % TABLE_ALIGNMENT) != 0 && - (table_size / TABLE_ALIGNMENT) != 0) { - fprintf(stderr, "The PSP table size should be 4K aligned\n"); + if ((table_size % TABLE_GRANULARITY) != 0 && (table_size / TABLE_GRANULARITY) != 0) { + fprintf(stderr, "The PSP table size should be %d aligned\n", TABLE_GRANULARITY); amdfwtool_cleanup(ctx); exit(1); } - dir->header.additional_info_fields.dir_size = - table_size / TABLE_ALIGNMENT; + if (psp_directory_aif_version(dir) == 1) { + u_int32_t hdr_size = sizeof(psp_directory_header) + count * sizeof(psp_directory_entry); + dir->header.additional_info_fields_v1.dir_size = table_size / TABLE_GRANULARITY; + dir->header.additional_info_fields_v1.dir_hdr_size = DIV_ROUND_UP(hdr_size, 1024); + } else { + dir->header.additional_info_fields.dir_size = table_size / TABLE_GRANULARITY; + } } dir->header.num_entries = count; /* checksum everything that comes after the Checksum field */ @@ -634,16 +628,21 @@ static void fill_dir_header(void *directory, uint32_t count, context *ctx) break; case BHD_COOKIE: case BHDL2_COOKIE: - if (bdir->header.additional_info_fields.dir_size == 0) { + if (bdt_directory_size_from_aif(bdir) == 0) { table_size = ctx->current - ctx->current_table; - if ((table_size % TABLE_ALIGNMENT) != 0 && - table_size / TABLE_ALIGNMENT != 0) { - fprintf(stderr, "The BIOS table size should be 4K aligned\n"); + if ((table_size % TABLE_GRANULARITY) != 0 && table_size / TABLE_GRANULARITY != 0) { + fprintf(stderr, "The BIOS table size should be %d aligned\n", TABLE_GRANULARITY); amdfwtool_cleanup(ctx); exit(1); } - bdir->header.additional_info_fields.dir_size = - table_size / TABLE_ALIGNMENT; + + if (bdt_directory_aif_version(bdir) == 1) { + u_int32_t hdr_size = sizeof(bios_directory_table) + count * sizeof(bios_directory_entry); + bdir->header.additional_info_fields_v1.dir_size = table_size / TABLE_GRANULARITY; + bdir->header.additional_info_fields_v1.dir_hdr_size = DIV_ROUND_UP(hdr_size, 1024); + } else { + bdir->header.additional_info_fields.dir_size = table_size / TABLE_GRANULARITY; + } } bdir->header.num_entries = count; /* checksum everything that comes after the Checksum field */ @@ -659,7 +658,7 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi context *ctx, amd_cb_config *cb_config) { switch (cb_config->soc_id) { - case PLATFORM_UNKNOWN: + case PLATFORM_MULLINS: amd_romsig->psp_directory = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); break; @@ -687,82 +686,38 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi static void fill_psp_bak_directory_to_efs(embedded_firmware *amd_romsig, void *pspdir_bak, context *ctx, amd_cb_config *cb_config) { - if (cb_config->recovery_ab) - amd_romsig->psp_bak_directory = + if (!pspdir_bak) + return; + if (!platform_needs_ish(cb_config->soc_id)) + return; + + /* Only used on platforms that support ISH, pointing to PSP L1B */ + amd_romsig->psp_bak_directory = BUFF_TO_RUN_MODE(*ctx, pspdir_bak, AMD_ADDR_REL_BIOS); } static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *biosdir, context *ctx, amd_cb_config *cb_config) { - switch (cb_config->soc_id) { - case PLATFORM_RENOIR: - case PLATFORM_LUCIENNE: - case PLATFORM_CEZANNE: - case PLATFORM_GENOA: - if (!cb_config->recovery_ab) - amd_romsig->bios3_entry = - BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); - break; - case PLATFORM_MENDOCINO: - case PLATFORM_PHOENIX: - case PLATFORM_STRIX: - case PLATFORM_KRACKAN2E: - case PLATFORM_STRIXHALO: - break; - case PLATFORM_CARRIZO: - case PLATFORM_STONEYRIDGE: - case PLATFORM_RAVEN: - case PLATFORM_PICASSO: - default: - amd_romsig->bios1_entry = - BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); - break; - } -} + /* + * On ISH enabled platforms BIOS directory is always pointed to by PSP L2. + */ + if (platform_needs_ish(cb_config->soc_id)) + return; -static uint32_t get_psp_id(enum platform soc_id) -{ - uint32_t psp_id; - switch (soc_id) { - case PLATFORM_RAVEN: - case PLATFORM_PICASSO: - psp_id = 0xBC0A0000; - break; - case PLATFORM_RENOIR: - case PLATFORM_LUCIENNE: - psp_id = 0xBC0C0000; - break; - case PLATFORM_CEZANNE: - psp_id = 0xBC0C0140; - break; - case PLATFORM_MENDOCINO: - psp_id = 0xBC0D0900; - break; - case PLATFORM_STONEYRIDGE: - psp_id = 0x10220B00; - break; - case PLATFORM_STRIX: - psp_id = 0xBC0E0200; - break; - case PLATFORM_PHOENIX: - psp_id = 0xBC0D0400; - break; - case PLATFORM_GENOA: - psp_id = 0xBC0C0111; - break; - case PLATFORM_KRACKAN2E: - psp_id = 0xbc0e1000; - break; - case PLATFORM_STRIXHALO: - psp_id = 0xbc0e0900; - break; - case PLATFORM_CARRIZO: - default: - psp_id = 0; - break; + if (!platform_is_multi_level(cb_config->soc_id)) { + /* + * Old SoCs always advertise BHD in EFS. There's no support for A/B + * recovery since it doesn't support PSP L2 tables. + */ + amd_romsig->bios1_entry = BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); + } else if (!cb_config->recovery_ab) { + /* + * Multi level SoCs only advertise BHD in EFS when not using A/B recovery. + * In A/B recovery mode BHD is advertised by PSP L2 table. + */ + amd_romsig->bios3_entry = BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); } - return psp_id; } static void integrate_firmwares(context *ctx, @@ -774,17 +729,17 @@ static void integrate_firmwares(context *ctx, adjust_current_pointer(ctx, 0, BLOB_ALIGNMENT); - for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (fw_table[i].filename != NULL) { switch (fw_table[i].type) { - case AMD_FW_IMC: + case AMD_FW_PSP_IMC: adjust_current_pointer(ctx, 0, 0x10000U); romsig->imc_entry = RUN_CURRENT(*ctx); break; - case AMD_FW_GEC: + case AMD_FW_PSP_GEC: romsig->gec_entry = RUN_CURRENT(*ctx); break; - case AMD_FW_XHCI: + case AMD_FW_PSP_XHCI: romsig->xhci_entry = RUN_CURRENT(*ctx); break; default: @@ -792,8 +747,7 @@ static void integrate_firmwares(context *ctx, break; } - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); + bytes = copy_blob(ctx, fw_table[i].filename); if (bytes < 0) { amdfwtool_cleanup(ctx); exit(1); @@ -844,7 +798,7 @@ static void dump_blob_version(char *manifest_file, amd_fw_entry *fw_table) return; } - for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + for (index = fw_table; index->type != AMD_FW_PSP_INVALID; index++) { if (!(index->filename)) continue; @@ -861,8 +815,8 @@ static void dump_psp_firmwares(amd_fw_entry *fw_table) amd_fw_entry *index; printf("PSP firmware components:\n"); - for (index = fw_table; index->type != AMD_FW_INVALID; index++) { - if (index->type == AMD_PSP_FUSE_CHAIN) + for (index = fw_table; index->type != AMD_FW_PSP_INVALID; index++) { + if (index->type == AMD_FW_PSP_FUSE_CHAIN) printf(" %2x: level=%x, subprog=%x, inst=%x\n", index->type, index->level, index->subprog, index->inst); else if (index->filename) @@ -884,30 +838,43 @@ static void dump_bdt_firmwares(amd_bios_entry *fw_table) } } +static void dump_psp_table(context *ctx, psp_directory_table *t, const char *name) +{ + uint32_t s = BUFF_TO_RUN(*ctx, t); + uint32_t e = s + psp_directory_size_from_aif(t); + + printf("PSP %-20s: [%06x-%06x)\n", name, s, e); +} + +static void dump_bdt_table(context *ctx, bios_directory_table *t, const char *name) +{ + uint32_t s = BUFF_TO_RUN(*ctx, t); + uint32_t e = s + bdt_directory_size_from_aif(t); + + printf("BHD %-20s: [%06x-%06x)\n", name, s, e); +} + static void dump_image_addresses(context *ctx) { - printf("romsig offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->amd_romsig_ptr)); - printf("PSP L1 offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->pspdir)); + printf("romsig offset : %lx\n", BUFF_TO_RUN(*ctx, ctx->amd_romsig_ptr)); + + dump_psp_table(ctx, ctx->pspdir, "L1 offset"); if (ctx->pspdir_bak != NULL) - printf("PSP L1 backup offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->pspdir_bak)); + dump_psp_table(ctx, ctx->pspdir_bak, "L1 backup offset"); if (ctx->pspdir2 != NULL) - printf("PSP L2(A) offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->pspdir2)); + dump_psp_table(ctx, ctx->pspdir2, "L2(A) offset"); if (ctx->ish_a_dir != NULL) - printf("ISHA offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->ish_a_dir)); + printf("ISH %-20s: %lx\n", "ISHA offset", BUFF_TO_RUN(*ctx, ctx->ish_a_dir)); if (ctx->ish_b_dir != NULL) - printf("ISHB offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->ish_b_dir)); + printf("ISH %-20s: %lx\n", "ISHB offset", BUFF_TO_RUN(*ctx, ctx->ish_b_dir)); if (ctx->pspdir2_b != NULL) - printf("PSP L2B offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->pspdir2_b)); + dump_psp_table(ctx, ctx->pspdir2_b, "L2B offset"); if (ctx->biosdir != NULL) - printf("BHD offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->biosdir)); + dump_bdt_table(ctx, ctx->biosdir, "offset"); if (ctx->biosdir2 != NULL) - printf("BHD L2(A) offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->biosdir2)); + dump_bdt_table(ctx, ctx->biosdir2, "L2(A) offset"); if (ctx->biosdir2_b != NULL) - printf("BHD L2B offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->biosdir2_b)); - if (ctx->psp_combo_dir != NULL) - printf("PSP combo offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->psp_combo_dir)); - if (ctx->bhd_combo_dir != NULL) - printf("BHD combo offset:%lx\n", BUFF_TO_RUN(*ctx, ctx->bhd_combo_dir)); + dump_bdt_table(ctx, ctx->biosdir2_b, "L2B offset"); } static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, @@ -926,17 +893,17 @@ static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, pspdir->entries[count].rsvd = 0; if (ish != NULL) { ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); - ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1; + ish->boot_priority = ab == AMD_FW_PSP_RECOVERYAB_A ? 0xFFFFFFFF : 1; ish->update_retry_count = 2; ish->glitch_retry_count = 0; - ish->psp_id = get_psp_id(soc_id); + ish->psp_id = platform_get_psp_id(soc_id); ish->checksum = fletcher32(&ish->boot_priority, sizeof(ish_directory_table) - sizeof(uint32_t)); pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS); pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); - pspdir->entries[count].size = TABLE_ALIGNMENT; + pspdir->entries[count].size = TABLE_GRANULARITY; } else { pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); @@ -953,14 +920,17 @@ static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, ctx->current_table = current_table_save; } -static void integrate_psp_levels(context *ctx, - amd_cb_config *cb_config) +static void integrate_psp_level2(context *ctx, amd_cb_config *cb_config) { uint32_t current_table_save; bool recovery_ab = cb_config->recovery_ab; unsigned int count; psp_directory_table *pspdir, *pspdir2, *pspdir2_b; - bool use_only_a = (cb_config->soc_id == PLATFORM_PHOENIX); /* TODO: b:285390041 */ + + /* PSP L1 must exist */ + assert(ctx->pspdir); + /* PSP L2 must exist */ + assert(ctx->pspdir2); pspdir = ctx->pspdir; pspdir2 = ctx->pspdir2; @@ -969,22 +939,26 @@ static void integrate_psp_levels(context *ctx, current_table_save = ctx->current_table; ctx->current_table = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); - if (recovery_ab && (pspdir2 != NULL)) { + if (recovery_ab) { integrate_psp_ab(ctx, pspdir, pspdir2, ctx->ish_a_dir, - AMD_FW_RECOVERYAB_A, cb_config->soc_id); + AMD_FW_PSP_RECOVERYAB_A, cb_config->soc_id); if (pspdir2_b != NULL) integrate_psp_ab(ctx, pspdir, pspdir2_b, ctx->ish_b_dir, - use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B, - cb_config->soc_id); + AMD_FW_PSP_RECOVERYAB_B, cb_config->soc_id); else integrate_psp_ab(ctx, pspdir, pspdir2, ctx->ish_a_dir, - use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B, - cb_config->soc_id); + AMD_FW_PSP_RECOVERYAB_B, cb_config->soc_id); - copy_psp_header(ctx->pspdir_bak, ctx->pspdir); + /* + * The PSP L1(B) can only be used on ISH platforms. On those platforms, there + * are no files present in PSP L1(A) directory, thus it's sufficient to only + * copy the header. + */ + if (ctx->pspdir_bak != NULL) + copy_psp_header(ctx->pspdir_bak, ctx->pspdir); } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); - pspdir->entries[count].type = AMD_FW_L2_PTR; + pspdir->entries[count].type = AMD_FW_PSP_L2_PTR; pspdir->entries[count].subprog = 0; pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = sizeof(pspdir2->header) @@ -1001,10 +975,10 @@ static void integrate_psp_levels(context *ctx, ctx->current_table = current_table_save; } -static void integrate_psp_firmwares(context *ctx, - amd_fw_entry *fw_table, - uint32_t cookie, - amd_cb_config *cb_config) +static psp_directory_table *integrate_psp_firmwares(context *ctx, + amd_fw_entry *fw_table, + uint32_t cookie, + amd_cb_config *cb_config) { ssize_t bytes; unsigned int i, count; @@ -1015,40 +989,13 @@ static void integrate_psp_firmwares(context *ctx, uint32_t current_table_save; bool recovery_ab = cb_config->recovery_ab; - /* This function can create a primary table, a secondary table, or a - * flattened table which contains all applicable types. These if-else - * statements infer what the caller intended. If a 2nd-level cookie - * is passed, clearly a 2nd-level table is intended. However, a - * 1st-level cookie may indicate level 1 or flattened. - */ + assert(cookie == PSP_COOKIE || cookie == PSPL2_COOKIE); + current_table_save = ctx->current_table; - if (cookie == PSP_COOKIE) { - if (!cb_config->combo_new_rab || ctx->combo_index == 0) { - pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); - ctx->pspdir = pspdir; - if (recovery_ab) - ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie); - } - /* The ISH tables are with PSP L1. */ - if (cb_config->need_ish && ctx->ish_a_dir == NULL) /* Need ISH */ - ctx->ish_a_dir = new_ish_dir(ctx); - if (cb_config->need_ish && ctx->ish_b_dir == NULL) /* Need ISH */ - ctx->ish_b_dir = new_ish_dir(ctx); - } else if (cookie == PSPL2_COOKIE) { - if (ctx->pspdir2 == NULL) { - pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); - ctx->pspdir2 = pspdir; - } else if (ctx->pspdir2_b == NULL) { - pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); - ctx->pspdir2_b = pspdir; - } - } - if (pspdir == NULL) { - goto out; - } + pspdir = new_psp_dir(ctx, cb_config, cookie); - if (!cb_config->multi_level) + if (!platform_is_multi_level(cb_config->soc_id)) level = PSP_BOTH; else if (cookie == PSPL2_COOKIE) level = PSP_LVL2; @@ -1069,13 +1016,13 @@ static void integrate_psp_firmwares(context *ctx, ctx->current_table = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); - for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0, count = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (!(fw_table[i].level & level)) continue; assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); - if (fw_table[i].type == AMD_TOKEN_UNLOCK) { + if (fw_table[i].type == AMD_FW_PSP_TOKEN_UNLOCK) { if (!fw_table[i].other) continue; adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); @@ -1087,16 +1034,45 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].rsvd = 0; adjust_current_pointer(ctx, 4096, 0x100U); count++; - } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + } else if (fw_table[i].type == AMD_FW_PSP_FUSE_CHAIN) { pspdir->entries[count].type = fw_table[i].type; pspdir->entries[count].subprog = fw_table[i].subprog; pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = 0xFFFFFFFF; pspdir->entries[count].addr = fw_table[i].other; pspdir->entries[count].address_mode = fw_table[i].other >> 62; + count++; + } else if (fw_table[i].type == AMD_FW_PSP_AB_NVRAM && + platform_has_legacy_ab_recovery(cb_config) && + fw_table[i].size != 0 && + fw_table[i].filename == NULL && + level == PSP_LVL1_AB) { + /* + * Special case as entry 0x6e is FSDL driver (fw_table[i].filename != NULL) + * on a platforms that don't use legacy A/B recovery. Here only the legacy + * A/B recovery NVRAM region is handled, thus fw_table[i].filename == NULL. + */ + size = fw_table[i].size; + addr = fw_table[i].dest; + if (addr != ALIGN_UP(addr, ERASE_ALIGNMENT)) { + fprintf(stderr, + "Error: PSP NVRAM section not aligned with erase block size.\n\n"); + amdfwtool_cleanup(ctx); + exit(1); + } + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = fw_table[i].subprog; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = size; + pspdir->entries[count].addr = addr; + pspdir->entries[count].writable = 1; + + pspdir->entries[count].address_mode = + SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); + count++; } else if (fw_table[i].type == AMD_FW_PSP_NVRAM || - fw_table[i].type == AMD_RPMC_NVRAM) { + fw_table[i].type == AMD_FW_PSP_RPMC_NVRAM) { if (fw_table[i].filename == NULL) { if (fw_table[i].size == 0) continue; @@ -1110,8 +1086,7 @@ static void integrate_psp_firmwares(context *ctx, } } else { adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); + bytes = copy_blob(ctx, fw_table[i].filename); if (bytes <= 0) { amdfwtool_cleanup(ctx); exit(1); @@ -1127,10 +1102,22 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = size; pspdir->entries[count].addr = addr; + pspdir->entries[count].writable = 1; pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); + count++; + } else if (fw_table[i].type == AMD_FW_PSP_BIOS_TABLE) { + /* Updated after BHD table was written */ + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = 0; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = 0; + pspdir->entries[count].addr = 0; + pspdir->entries[count].writable = 0; + pspdir->entries[count].address_mode = 0; + count++; } else if (fw_table[i].filename != NULL) { if (fw_table[i].addr_signed) { @@ -1140,8 +1127,7 @@ static void integrate_psp_firmwares(context *ctx, SET_ADDR_MODE_BY_TABLE(pspdir); bytes = fw_table[i].file_size; } else { - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); + bytes = copy_blob(ctx, fw_table[i].filename); if (bytes < 0) { amdfwtool_cleanup(ctx); exit(1); @@ -1165,8 +1151,9 @@ static void integrate_psp_firmwares(context *ctx, } fill_dir_header(pspdir, count, ctx); -out: + ctx->current_table = current_table_save; + return pspdir; } static void add_psp_firmware_entry(context *ctx, @@ -1200,25 +1187,39 @@ static void add_psp_firmware_entry(context *ctx, ctx->current_table = current_table_save; } -static void *new_bios_dir(context *ctx, bool multi, uint32_t cookie) +static void *new_bios_dir(context *ctx, const amd_cb_config *cb_config, const uint32_t cookie) { - void *ptr; + bios_directory_hdr *ptr; /* * Force both onto boundary when multi. Primary table is after * updatable table, so alignment ensures primary can stay intact * if secondary is reprogrammed. */ - if (multi) + if (platform_is_multi_level(cb_config->soc_id)) adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT); else adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); - ptr = BUFF_CURRENT(*ctx); - ((bios_directory_hdr *) ptr)->cookie = cookie; - ((bios_directory_hdr *) ptr)->additional_info = 0; - ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; - ((bios_directory_hdr *) ptr)->additional_info_fields.spi_block_size = 1; - ((bios_directory_hdr *) ptr)->additional_info_fields.base_addr = 0; + ptr = (bios_directory_hdr *)BUFF_CURRENT(*ctx); + + ptr->cookie = cookie; + + + if (platform_has_dir_header_v1(cb_config->soc_id)) { + ptr->additional_info_fields_v1.version = 1; + ptr->additional_info_fields_v1.dir_size = 0; + ptr->additional_info_fields_v1.spi_block_size = 0; + ptr->additional_info_fields_v1.dir_hdr_size = 0; + ptr->additional_info_fields_v1.address_mode = ctx->address_mode; + ptr->additional_info_fields_v1.reserved = 0; + } else { + ptr->additional_info_fields.version = 0; + ptr->additional_info_fields.dir_size = 0; + ptr->additional_info_fields.spi_block_size = 1; + ptr->additional_info_fields.address_mode = ctx->address_mode; + ptr->additional_info_fields.base_addr = 0; + } + adjust_current_pointer(ctx, sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry), 1); @@ -1303,10 +1304,10 @@ static void integrate_bios_levels(context *ctx, amd_cb_config *cb_config) if (cb_config->recovery_ab) { add_psp_firmware_entry(ctx, ctx->pspdir2, ctx->biosdir2, - AMD_FW_BIOS_TABLE, TABLE_L2_SIZE_MAX); + AMD_FW_PSP_BIOS_TABLE, TABLE_L2_SIZE_MAX); if (ctx->pspdir2_b != NULL) add_psp_firmware_entry(ctx, ctx->pspdir2_b, - ctx->biosdir2_b, AMD_FW_BIOS_TABLE, + ctx->biosdir2_b, AMD_FW_PSP_BIOS_TABLE, TABLE_L2_SIZE_MAX); } else if (ctx->biosdir2) { current_table_save = ctx->current_table; @@ -1329,15 +1330,19 @@ static void integrate_bios_levels(context *ctx, amd_cb_config *cb_config) ctx->biosdir->entries[count].dest = -1; ctx->biosdir->entries[count].reset = 0; ctx->biosdir->entries[count].ro = 0; + ctx->biosdir->entries[count].romid = 0; + ctx->biosdir->entries[count].writable = 0; + ctx->biosdir->entries[count].rsvd = 0; count++; fill_dir_header(ctx->biosdir, count, ctx); ctx->current_table = current_table_save; } } -static void integrate_bios_firmwares(context *ctx, - amd_bios_entry *fw_table, - uint32_t cookie, - amd_cb_config *cb_config) + +static bios_directory_table *integrate_bios_firmwares(context *ctx, + amd_bios_entry *fw_table, + uint32_t cookie, + amd_cb_config *cb_config) { ssize_t bytes; unsigned int i, count; @@ -1348,16 +1353,7 @@ static void integrate_bios_firmwares(context *ctx, uint32_t current_table_save; bios_directory_table *biosdir; - biosdir = new_bios_dir(ctx, cb_config->multi_level, cookie); - - if (cookie == BHD_COOKIE) - ctx->biosdir = biosdir; - else if (cookie == BHDL2_COOKIE) { - if (ctx->biosdir2 == NULL) - ctx->biosdir2 = biosdir; - else if (ctx->biosdir2_b == NULL) - ctx->biosdir2_b = biosdir; - } + biosdir = new_bios_dir(ctx, cb_config, cookie); /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -1365,7 +1361,7 @@ static void integrate_bios_firmwares(context *ctx, * is passed, clearly a 2nd-level table is intended. However, a * 1st-level cookie may indicate level 1 or flattened. */ - if (!cb_config->multi_level) + if (!platform_is_multi_level(cb_config->soc_id)) level = BDT_BOTH; else if (cookie == BHDL2_COOKIE) level = BDT_LVL2; @@ -1387,13 +1383,20 @@ static void integrate_bios_firmwares(context *ctx, fw_table[i].type != AMD_BIOS_APOB_NV && fw_table[i].type != AMD_BIOS_L2_PTR && fw_table[i].type != AMD_BIOS_BIN && + fw_table[i].type != AMD_BIOS_NV_ST && fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) continue; /* BIOS Directory items may have additional requirements */ - /* SIG needs a size, else no choice but to skip */ - if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size) + if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size) { + /* When signature is empty reserve some space to fill it in later. */ + fw_table[i].size = platform_psb_reserved_size(cb_config->soc_id); + } + + /* NV_ST needs a src and size, else no choice but to skip */ + if (fw_table[i].type == AMD_BIOS_NV_ST && + (!fw_table[i].src || !fw_table[i].size)) continue; /* Check APOB_NV requirements */ @@ -1450,6 +1453,9 @@ static void integrate_bios_firmwares(context *ctx, biosdir->entries[count].compressed = fw_table[i].zlib; biosdir->entries[count].inst = fw_table[i].inst; biosdir->entries[count].subprog = fw_table[i].subpr; + biosdir->entries[count].romid = 0; + biosdir->entries[count].writable = 0; + biosdir->entries[count].rsvd = 0; switch (fw_table[i].type) { case AMD_BIOS_SIG: @@ -1468,14 +1474,15 @@ static void integrate_bios_firmwares(context *ctx, biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); break; case AMD_BIOS_APOB_NV: - if (has_apob_nv_quirk(cb_config->soc_id)) { + case AMD_BIOS_NV_ST: + if (platform_has_apob_nv_quirk(cb_config->soc_id)) { /* * once ROM3 mapping (>16MiB) is used on any SOC that * has the apob quirk, this needs to be updated, since * using an MMIO address is then not as simply as adding * the SPI_ROM_BASE offset anymore. */ - if (fw_table[i].src + fw_table[i].size >= 16*MiB) { + if (fw_table[i].src + fw_table[i].size > 16*MiB) { fprintf(stderr, "APOB_NV location too high (0x%lx + 0x%lx)\n", fw_table[i].src, fw_table[i].size); @@ -1490,6 +1497,7 @@ static void integrate_bios_firmwares(context *ctx, SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); } biosdir->entries[count].size = fw_table[i].size; + biosdir->entries[count].writable = 1; break; case AMD_BIOS_BIN: /* Don't make a 2nd copy, point to the same one */ @@ -1512,8 +1520,7 @@ static void integrate_bios_firmwares(context *ctx, if (!fw_table[i].filename) break; - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); + bytes = copy_blob(ctx, fw_table[i].filename); if (bytes <= 0) { amdfwtool_cleanup(ctx); exit(1); @@ -1530,23 +1537,21 @@ static void integrate_bios_firmwares(context *ctx, biosdir->entries[count].dest = fw_table[i].dest; biosdir->entries[count].size = fw_table[i].size; break; - - default: /* everything else is copied from input */ - if (fw_table[i].type == AMD_BIOS_APCB || - fw_table[i].type == AMD_BIOS_APCB_BK) - adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); + case AMD_BIOS_APCB: + case AMD_BIOS_APCB_BK: + adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); + bytes = copy_blob(ctx, fw_table[i].filename); if (bytes <= 0) { amdfwtool_cleanup(ctx); exit(1); } - + /* Size needs to be multiple of 4K. Most APCB files are padded, some are not. */ + bytes = ALIGN_UP(bytes, ERASE_ALIGNMENT); biosdir->entries[count].size = (uint32_t)bytes; biosdir->entries[count].source = RUN_CURRENT(*ctx); biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); - adjust_current_pointer(ctx, bytes, 0x100U); + adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); if (fw_table[i].type == AMD_BIOS_APCB && !cb_config->have_apcb_bk) { size = biosdir->entries[count].size; source = biosdir->entries[count].source; @@ -1554,6 +1559,19 @@ static void integrate_bios_firmwares(context *ctx, add_bios_apcb_bk_entry(biosdir, count, fw_table[i].inst, size, source); } break; + default: /* everything else is copied from input */ + bytes = copy_blob(ctx, fw_table[i].filename); + if (bytes <= 0) { + amdfwtool_cleanup(ctx); + exit(1); + } + + biosdir->entries[count].size = (uint32_t)bytes; + biosdir->entries[count].source = RUN_CURRENT(*ctx); + biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); + + adjust_current_pointer(ctx, bytes, 0x100U); + break; } count++; @@ -1561,25 +1579,24 @@ static void integrate_bios_firmwares(context *ctx, fill_dir_header(biosdir, count, ctx); ctx->current_table = current_table_save; + return biosdir; } -static void add_combo_entry(void *combo_dir, void *dir, uint32_t combo_index, - context *ctx, amd_cb_config *cb_config) +static int integrate_efs_table(context *ctx, amd_cb_config *cb_config) { - psp_combo_directory *cdir = combo_dir; - assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, ctx); - /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - cdir->entries[combo_index].id_sel = 0; - cdir->entries[combo_index].id = get_psp_id(cb_config->soc_id); - cdir->entries[combo_index].lvl2_addr = - BUFF_TO_RUN_MODE(*ctx, dir, AMD_ADDR_REL_BIOS); - - fill_dir_header(combo_dir, combo_index + 1, ctx); -} + set_current_pointer(ctx, cb_config->efs_location); + ctx->amd_romsig_ptr = BUFF_OFFSET(*ctx, cb_config->efs_location); + embedded_firmware *amd_romsig = (embedded_firmware *)ctx->amd_romsig_ptr; + adjust_current_pointer(ctx, sizeof(embedded_firmware), BLOB_ALIGNMENT); + + amd_romsig->signature = EMBEDDED_FW_SIGNATURE; + amd_romsig->imc_entry = 0; + amd_romsig->gec_entry = 0; + amd_romsig->xhci_entry = 0; + + if (cb_config->soc_id == PLATFORM_MULLINS) + return 0; -static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, - embedded_firmware *amd_romsig) -{ if ((cb_config->efs_spi_readmode == 0xFF) || (cb_config->efs_spi_speed == 0xFF)) { fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; @@ -1587,7 +1604,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. * Leave as 0xffffffff for first gen */ - if (cb_config->second_gen) { + if (platform_is_second_gen(cb_config->soc_id)) { amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->efs_gen.reserved = 0; } else { @@ -1595,7 +1612,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, amd_romsig->efs_gen.reserved = ~0; } - switch (soc_id) { + switch (cb_config->soc_id) { case PLATFORM_CARRIZO: case PLATFORM_STONEYRIDGE: amd_romsig->spi_readmode_f15_mod_60_6f = cb_config->efs_spi_readmode; @@ -1651,74 +1668,52 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, return 0; } -void open_process_config(char *config, amd_cb_config *cb_config) +static int open_process_config(char *config, amd_cb_config *cb_config) { FILE *config_handle; - if (config) { - config_handle = fopen(config, "r"); - if (config_handle == NULL) { - fprintf(stderr, "Can not open file %s for reading: %s\n", - config, strerror(errno)); - exit(1); - } - if (process_config(config_handle, cb_config) == 0) { - fprintf(stderr, "Configuration file %s parsing error\n", - config); - fclose(config_handle); - exit(1); - } + config_handle = fopen(config, "r"); + if (config_handle == NULL) { + fprintf(stderr, "Can not open file %s for reading: %s\n", + config, strerror(errno)); + return 1; + } + if (process_config(config_handle, cb_config) == 0) { + fprintf(stderr, "Configuration file %s parsing error\n", + config); fclose(config_handle); + return 1; } + fclose(config_handle); /* For debug. */ if (cb_config->debug) { dump_psp_firmwares(amd_psp_fw_table); dump_bdt_firmwares(amd_bios_table); } -} - -static bool is_initial_alignment_required(enum platform soc_id) -{ - switch (soc_id) { - case PLATFORM_MENDOCINO: - case PLATFORM_PHOENIX: - case PLATFORM_STRIX: - case PLATFORM_KRACKAN2E: - case PLATFORM_STRIXHALO: - return false; - default: - return true; - } + return 0; } int main(int argc, char **argv) { int retval = 0; - int targetfd; context ctx = { 0 }; - uint32_t romsig_offset; amd_cb_config cb_config = { .efs_spi_readmode = 0xff, .efs_spi_speed = 0xff, .efs_spi_micron_flag = 0xff }; - ctx.current_pointer_saved = 0xFFFFFFFF; - - retval = amdfwtool_getopt(argc, argv, &cb_config, &ctx); + retval = amdfwtool_getopt(argc, argv, &cb_config); + if (retval) + return retval; + retval = open_process_config(cb_config.config, &cb_config); if (retval) { + amdfwtool_cleanup(&ctx); return retval; } - if (cb_config.use_combo) { - ctx.amd_psp_fw_table_clean = malloc(sizeof(amd_psp_fw_table)); - ctx.amd_bios_table_clean = malloc(sizeof(amd_bios_table)); - memcpy(ctx.amd_psp_fw_table_clean, amd_psp_fw_table, sizeof(amd_psp_fw_table)); - memcpy(ctx.amd_bios_table_clean, amd_bios_table, sizeof(amd_bios_table)); - } - - open_process_config(cb_config.config, &cb_config); - + ctx.current_pointer_saved = 0xFFFFFFFF; + ctx.rom_size = cb_config.rom_size; ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { fprintf(stderr, "Error: Failed to allocate memory\n"); @@ -1726,40 +1721,26 @@ int main(int argc, char **argv) } memset(ctx.rom, 0xFF, ctx.rom_size); - romsig_offset = cb_config.efs_location ? cb_config.efs_location : AMD_ROMSIG_OFFSET; - set_current_pointer(&ctx, romsig_offset); - - ctx.amd_romsig_ptr = BUFF_OFFSET(ctx, romsig_offset); - ctx.amd_romsig_ptr->signature = EMBEDDED_FW_SIGNATURE; - ctx.amd_romsig_ptr->imc_entry = 0; - ctx.amd_romsig_ptr->gec_entry = 0; - ctx.amd_romsig_ptr->xhci_entry = 0; - - if (cb_config.soc_id != PLATFORM_UNKNOWN) { - retval = set_efs_table(cb_config.soc_id, &cb_config, ctx.amd_romsig_ptr); - if (retval) { - fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); - return retval; - } - } else { - fprintf(stderr, "WARNING: No SOC name specified.\n"); + /* Fill EFS with defaults, eSPI and SPI configuration. Pointers are added later. */ + retval = integrate_efs_table(&ctx, &cb_config); + if (retval) { + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); + return retval; } - if (cb_config.need_ish) + if (platform_needs_ish(cb_config.soc_id)) ctx.address_mode = AMD_ADDR_REL_TAB; - else if (cb_config.second_gen) + else if (platform_is_second_gen(cb_config.soc_id)) ctx.address_mode = AMD_ADDR_REL_BIOS; else ctx.address_mode = AMD_ADDR_PHYSICAL; if (cb_config.efs_location != cb_config.body_location) set_current_pointer(&ctx, cb_config.body_location); - else - set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware)); integrate_firmwares(&ctx, ctx.amd_romsig_ptr, amd_fw_table); - if (is_initial_alignment_required(cb_config.soc_id)) { + if (platform_is_initial_alignment_required(cb_config.soc_id)) { /* TODO: Check for older platforms. */ adjust_current_pointer(&ctx, 0, 0x10000U); } @@ -1773,154 +1754,156 @@ int main(int argc, char **argv) cb_config.signed_start_addr, cb_config.soc_id); - if (cb_config.use_combo && !cb_config.combo_new_rab) { - ctx.psp_combo_dir = new_combo_dir(&ctx, PSP2_COOKIE); - - adjust_current_pointer(&ctx, 0, 0x1000U); - - if (!cb_config.recovery_ab) - ctx.bhd_combo_dir = new_combo_dir(&ctx, BHD2_COOKIE); + ctx.pspdir = NULL; + ctx.pspdir_bak = NULL; + ctx.pspdir2 = NULL; + ctx.pspdir2_b = NULL; + ctx.biosdir = NULL; + ctx.biosdir2 = NULL; + ctx.biosdir2_b = NULL; + ctx.ish_a_dir = NULL; + ctx.ish_b_dir = NULL; + + if (cb_config.recovery_ab_single_copy) { + if (!platform_is_multi_level(cb_config.soc_id) || + !platform_needs_ish(cb_config.soc_id)) { + fprintf(stderr, "Error: AB recovery with single copy option requires multiple levels and ISH\n\n"); + amdfwtool_cleanup(&ctx); + return 1; + } } - ctx.combo_index = 0; - if (cb_config.config) - cb_config.combo_config[0] = cb_config.config; + if (platform_is_multi_level(cb_config.soc_id)) { - do { - if (cb_config.use_combo && cb_config.debug) - printf("Processing %dth combo entry\n", ctx.combo_index); + ctx.current_l1_pointer = 0; + ctx.current_a_pointer = cb_config.ral2_location; + ctx.current_b_pointer = cb_config.rbl2_location; - /* The pspdir level 1 is special. For new combo layout, all the combo entries - share one pspdir L1. It should not be cleared at each iteration. */ - if (!cb_config.combo_new_rab || ctx.combo_index == 0) { - ctx.pspdir = NULL; - ctx.pspdir_bak = NULL; - } - ctx.pspdir2 = NULL; - ctx.pspdir2_b = NULL; - ctx.biosdir = NULL; - ctx.biosdir2 = NULL; - ctx.biosdir2_b = NULL; - ctx.ish_a_dir = NULL; - ctx.ish_b_dir = NULL; - /* for non-combo image, combo_config[0] == config, and - * it already is processed. Actually "combo_index > - * 0" is enough. Put both of them here to make sure - * and make it clear this will not affect non-combo - * case. + /* PSP L1. + * On multi-level platforms, the PSP L1 table contains mandatory files and + * a pointer to the PSP L2 table. On ISH platforms the PSP L1 table only contains + * pointers to PSP L2, but there are no files present. */ - if (cb_config.use_combo && ctx.combo_index > 0) { - /* Restore the table as clean data. */ - memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean, - sizeof(amd_psp_fw_table)); - memcpy(amd_bios_table, ctx.amd_bios_table_clean, - sizeof(amd_bios_table)); - assert_fw_entry(ctx.combo_index, MAX_COMBO_ENTRIES, &ctx); - open_process_config(cb_config.combo_config[ctx.combo_index], &cb_config); - - /* In most cases, the address modes are same. */ - if (cb_config.need_ish) - ctx.address_mode = AMD_ADDR_REL_TAB; - else if (cb_config.second_gen) - ctx.address_mode = AMD_ADDR_REL_BIOS; - else - ctx.address_mode = AMD_ADDR_PHYSICAL; - - register_apcb_combo(&cb_config, ctx.combo_index, &ctx); + ctx.pspdir = integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); + + if (platform_needs_ish(cb_config.soc_id)) { + /* Only on ISH platforms the backup PSP L1 directory can be used. */ + ctx.pspdir_bak = new_psp_dir(&ctx, &cb_config, PSP_COOKIE); + ctx.ish_a_dir = new_ish_dir(&ctx); + if (!cb_config.recovery_ab_single_copy) + ctx.ish_b_dir = new_ish_dir(&ctx); } - - if (cb_config.multi_level) { - /* PSP L1 */ - integrate_psp_firmwares(&ctx, - amd_psp_fw_table, PSP_COOKIE, &cb_config); - /* PSP L2 & BIOS L2 (if AB recovery) */ - integrate_psp_firmwares(&ctx, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - if (cb_config.recovery_ab) { - integrate_bios_firmwares(&ctx, - amd_bios_table, BHDL2_COOKIE, &cb_config); - if (!cb_config.recovery_ab_single_copy) { - integrate_psp_firmwares(&ctx, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - integrate_bios_firmwares(&ctx, - amd_bios_table, BHDL2_COOKIE, &cb_config); - } - integrate_bios_levels(&ctx, &cb_config); + ctx.current_l1_pointer = ctx.current; + + if (cb_config.recovery_ab && cb_config.ral2_location) + set_current_pointer(&ctx, cb_config.ral2_location); + + /* PSP L2 & BIOS L2 (if AB recovery) */ + ctx.pspdir2 = integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + if (cb_config.recovery_ab) { + ctx.biosdir2 = integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, + &cb_config); + ctx.current_a_pointer = ctx.current; + + if (!cb_config.recovery_ab_single_copy) { + if (cb_config.recovery_ab && cb_config.rbl2_location) + set_current_pointer(&ctx, cb_config.rbl2_location); + + ctx.pspdir2_b = integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, + &cb_config); + ctx.biosdir2_b = integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, + &cb_config); + ctx.current_b_pointer = ctx.current; } - integrate_psp_levels(&ctx, &cb_config); - } else { - /* flat: PSP 1 cookie and no pointer to 2nd table */ - integrate_psp_firmwares(&ctx, - amd_psp_fw_table, PSP_COOKIE, &cb_config); + integrate_bios_levels(&ctx, &cb_config); } - - if (!cb_config.use_combo || (cb_config.combo_new_rab && ctx.combo_index == 0)) { - /* For new combo layout, there is only 1 PSP level 1 directory. */ - fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); - fill_psp_bak_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir_bak, &ctx, &cb_config); - } else if (cb_config.use_combo && !cb_config.combo_new_rab) { - fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config); - add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, ctx.combo_index, &ctx, &cb_config); + integrate_psp_level2(&ctx, &cb_config); + } else { + if (cb_config.recovery_ab) { + fprintf(stderr, "Error: AB recovery requires multiple levels\n\n"); + amdfwtool_cleanup(&ctx); + return 1; } + /* flat: PSP 1 cookie and no pointer to 2nd table */ + ctx.pspdir = integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); + } - if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) { - if (cb_config.multi_level) { - integrate_bios_firmwares(&ctx, - amd_bios_table, BHD_COOKIE, &cb_config); - integrate_bios_firmwares(&ctx, - amd_bios_table, BHDL2_COOKIE, &cb_config); - integrate_bios_levels(&ctx, &cb_config); - } else { - /* flat: BHD1 cookie and no pointer to 2nd table */ - integrate_bios_firmwares(&ctx, - amd_bios_table, BHD_COOKIE, &cb_config); - } - if (!cb_config.use_combo) { - fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.biosdir, - &ctx, &cb_config); - } else if (ctx.bhd_combo_dir != NULL) { - /* In recovery A/B mode, there isn't a BHD combo directory. - * Instead, the BIOS tables level 2 are linked by PSP tables. - */ - fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.bhd_combo_dir, - &ctx, &cb_config); - add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, ctx.combo_index, &ctx, &cb_config); - } + + fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); + fill_psp_bak_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir_bak, &ctx, &cb_config); + + if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) { + if (platform_is_multi_level(cb_config.soc_id)) { + ctx.biosdir = integrate_bios_firmwares(&ctx, amd_bios_table, BHD_COOKIE, &cb_config); + ctx.biosdir2 = integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, &cb_config); + integrate_bios_levels(&ctx, &cb_config); + } else { + /* flat: BHD1 cookie and no pointer to 2nd table */ + ctx.biosdir = integrate_bios_firmwares(&ctx, amd_bios_table, BHD_COOKIE, &cb_config); } - if (cb_config.debug) - dump_image_addresses(&ctx); - } while (cb_config.use_combo && ++ctx.combo_index < MAX_COMBO_ENTRIES && - cb_config.combo_config[ctx.combo_index] != NULL); - - targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666); - if (targetfd >= 0) { - uint32_t offset = cb_config.efs_location; - uint32_t bytes = cb_config.efs_location == cb_config.body_location ? - ctx.current - offset : sizeof(embedded_firmware); - uint32_t ret_bytes; - - ret_bytes = write_from_buf_to_file(targetfd, BUFF_OFFSET(ctx, offset), bytes); - if (bytes != ret_bytes) { - fprintf(stderr, "Error: Writing to file %s failed\n", cb_config.output); - retval = 1; + + fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.biosdir, &ctx, &cb_config); + } + if (cb_config.debug) + dump_image_addresses(&ctx); + + /* Validate A/B recovery config */ + if (cb_config.recovery_ab && cb_config.rbl2_location && cb_config.ral2_location) { + ssize_t abytes = 0, bbytes = 0; + abytes = ctx.current_a_pointer - cb_config.ral2_location; + bbytes = ctx.current_b_pointer - cb_config.rbl2_location; + if (abytes != bbytes) { + fprintf(stderr, "Warning: The size of A and B tables are not the same\n"); + amdfwtool_cleanup(&ctx); + return 1; } - close(targetfd); + } + + uint32_t efs_offset = cb_config.efs_location; + ssize_t bytes, ret_bytes; + + if (cb_config.recovery_ab && cb_config.ral2_location) { + /* EFS, PSP L1 and ISH A and ISH B is split off. */ + bytes = ctx.current_l1_pointer - cb_config.efs_location; + } else if (cb_config.efs_location != cb_config.body_location) { + /* Special case for VBOOT on PSP. Only write EFS. */ + bytes = sizeof(embedded_firmware); } else { - fprintf(stderr, "Error: could not open file: %s\n", cb_config.output); + /* Write whole image (EFS + all tables) */ + bytes = ctx.current - efs_offset; + } + + ret_bytes = write_blob(cb_config.output, BUFF_OFFSET(ctx, efs_offset), bytes, ""); + if (bytes != ret_bytes) { + fprintf(stderr, "Error: Writing to file %s failed\n", cb_config.output); retval = 1; } + /* Special case for VBOOT on PSP. Write body (all tables except EFS). */ if (cb_config.efs_location != cb_config.body_location) { - ssize_t bytes; - - bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location), - ctx.current - cb_config.body_location); + bytes = write_blob(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location), + ctx.current - cb_config.body_location, BODY_FILE_SUFFIX); if (bytes != ctx.current - cb_config.body_location) { fprintf(stderr, "Error: Writing body\n"); retval = 1; } } + /* When recovery A location was provided generate a separate file for it. */ + if (cb_config.recovery_ab && cb_config.ral2_location) { + ssize_t abytes = 0; + abytes = ctx.current_a_pointer - cb_config.ral2_location; + write_blob(cb_config.output, BUFF_OFFSET(ctx, cb_config.ral2_location), + abytes, RA_FILE_SUFFIX); + } + /* When recovery B location was provided generate a separate file for it. */ + if (cb_config.recovery_ab && cb_config.rbl2_location) { + ssize_t bbytes = 0; + bbytes = ctx.current_b_pointer - cb_config.rbl2_location; + write_blob(cb_config.output, BUFF_OFFSET(ctx, cb_config.rbl2_location), + bbytes, RB_FILE_SUFFIX); + } + if (cb_config.manifest_file) { dump_blob_version(cb_config.manifest_file, amd_psp_fw_table); } diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index bd973638ede..e26cc128118 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -16,6 +16,7 @@ #define ERASE_ALIGNMENT 0x1000U #define TABLE_ALIGNMENT 0x1000U +#define TABLE_GRANULARITY 0x1000U #define TABLE_L2_SIZE_MAX 0x400U #define BLOB_ALIGNMENT 0x100U #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) @@ -23,6 +24,7 @@ enum platform { PLATFORM_UNKNOWN, + PLATFORM_MULLINS, PLATFORM_CARRIZO, PLATFORM_STONEYRIDGE, PLATFORM_RAVEN, @@ -47,89 +49,90 @@ typedef enum _amd_fw_type { AMD_FW_PSP_RTM_PUBKEY = 0x05, AMD_FW_PSP_SMU_FIRMWARE = 0x08, AMD_FW_PSP_SECURED_DEBUG = 0x09, - AMD_FW_ABL_PUBKEY = 0x0a, - AMD_PSP_FUSE_CHAIN = 0x0b, + AMD_FW_PSP_ABL_PUBKEY = 0x0a, + AMD_FW_PSP_FUSE_CHAIN = 0x0b, AMD_FW_PSP_TRUSTLETS = 0x0c, AMD_FW_PSP_TRUSTLETKEY = 0x0d, AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, - AMD_DEBUG_UNLOCK = 0x13, + AMD_FW_PSP_DEBUG_UNLOCK = 0x13, AMD_FW_PSP_TEEIPKEY = 0x15, - AMD_BOOT_DRIVER = 0x1b, - AMD_SOC_DRIVER = 0x1c, - AMD_DEBUG_DRIVER = 0x1d, - AMD_INTERFACE_DRIVER = 0x1f, - AMD_HW_IPCFG = 0x20, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_FW_KVM_IMAGE = 0x29, - AMD_FW_MP5 = 0x2a, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_SEV_DATA = 0x38, - AMD_SEV_CODE = 0x39, + AMD_FW_PSP_BOOT_DRIVER = 0x1b, + AMD_FW_PSP_SOC_DRIVER = 0x1c, + AMD_FW_PSP_DEBUG_DRIVER = 0x1d, + AMD_FW_PSP_INTERFACE_DRIVER = 0x1f, + AMD_FW_PSP_HW_IPCFG = 0x20, + AMD_FW_PSP_WRAPPED_IKEK = 0x21, + AMD_FW_PSP_TOKEN_UNLOCK = 0x22, + AMD_FW_PSP_SEC_GASKET = 0x24, + AMD_FW_PSP_MP2_FW = 0x25, + AMD_FW_PSP_DRIVER_ENTRIES = 0x28, + AMD_FW_PSP_KVM_IMAGE = 0x29, + AMD_FW_PSP_MP5 = 0x2a, + AMD_FW_PSP_S0I3_DRIVER = 0x2d, + AMD_FW_PSP_ABL0 = 0x30, + AMD_FW_PSP_ABL1 = 0x31, + AMD_FW_PSP_ABL2 = 0x32, + AMD_FW_PSP_ABL3 = 0x33, + AMD_FW_PSP_ABL4 = 0x34, + AMD_FW_PSP_ABL5 = 0x35, + AMD_FW_PSP_ABL6 = 0x36, + AMD_FW_PSP_ABL7 = 0x37, + AMD_FW_PSP_SEV_DATA = 0x38, + AMD_FW_PSP_SEV_CODE = 0x39, AMD_FW_PSP_WHITELIST = 0x3a, - AMD_VBIOS_BTLOADER = 0x3c, - AMD_FW_L2_PTR = 0x40, - AMD_FW_DXIO = 0x42, - AMD_FW_USB_PHY = 0x44, - AMD_FW_TOS_SEC_POLICY = 0x45, - AMD_FW_DRTM_TA = 0x47, - AMD_FW_RECOVERYAB_A = 0x48, - AMD_FW_RECOVERYAB_B = 0x4A, - AMD_FW_BIOS_TABLE = 0x49, - AMD_FW_KEYDB_BL = 0x50, - AMD_FW_KEYDB_TOS = 0x51, + AMD_FW_PSP_VBIOS_BTLOADER = 0x3c, + AMD_FW_PSP_L2_PTR = 0x40, + AMD_FW_PSP_DXIO = 0x42, + AMD_FW_PSP_USB_PHY = 0x44, + AMD_FW_PSP_TOS_SEC_POLICY = 0x45, + AMD_FW_PSP_DRTM_TA = 0x47, + AMD_FW_PSP_RECOVERYAB_A = 0x48, + AMD_FW_PSP_RECOVERYAB_B = 0x4A, + AMD_FW_PSP_BIOS_TABLE = 0x49, + AMD_FW_PSP_KEYDB_BL = 0x50, + AMD_FW_PSP_KEYDB_TOS = 0x51, AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_VERSTAGE_SIG = 0x53, - AMD_RPMC_NVRAM = 0x54, - AMD_FW_SPL = 0x55, - AMD_FW_DMCU_ERAM = 0x58, - AMD_FW_DMCU_ISR = 0x59, - AMD_FW_MSMU = 0x5a, - AMD_FW_SPIROM_CFG = 0x5c, - AMD_FW_MPIO = 0x5d, - AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ + AMD_FW_PSP_VERSTAGE_SIG = 0x53, + AMD_FW_PSP_RPMC_NVRAM = 0x54, + AMD_FW_PSP_SPL = 0x55, + AMD_FW_PSP_DMCU_ERAM = 0x58, + AMD_FW_PSP_DMCU_ISR = 0x59, + AMD_FW_PSP_MSMU = 0x5a, + AMD_FW_PSP_SPIROM_CFG = 0x5c, + AMD_FW_PSP_MPIO = 0x5d, + AMD_FW_PSP_TPMLITE = 0x5f, /* family 17h & 19h */ AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ - AMD_FW_DMCUB = 0x71, + AMD_FW_PSP_AB_NVRAM = 0x6e, /* PSP_AB_NVRAM on V2000A, FSDL driver on other SoCs */ + AMD_FW_PSP_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, - AMD_RIB = 0x76, - AMD_FW_AMF_SRAM = 0x85, - AMD_FW_AMF_DRAM = 0x86, - AMD_FW_MFD_MPM = 0x87, - AMD_FW_AMF_WLAN = 0x88, - AMD_FW_AMF_MFD = 0x89, - AMD_FW_MPDMA_TF = 0x8c, - AMD_TA_IKEK = 0x8d, - AMD_FW_MPCCX = 0x90, - AMD_FW_GMI3_PHY = 0x91, - AMD_FW_MPDMA_PM = 0x92, - AMD_FW_LSDMA = 0x94, - AMD_FW_C20_MP = 0x95, - AMD_FW_FCFG_TABLE = 0x98, - AMD_FW_MINIMSMU = 0x9a, - AMD_FW_GFXIMU_0 = 0x9b, - AMD_FW_GFXIMU_1 = 0x9c, - AMD_FW_SRAM_FW_EXT = 0x9d, - AMD_FW_UMSMU = 0xa2, - AMD_FW_S3IMG = 0xa0, - AMD_FW_USBDP = 0xa4, - AMD_FW_USBSS = 0xa5, - AMD_FW_USB4 = 0xa6, - AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ - AMD_FW_SKIP /* This is for non-applicable options. */ + AMD_FW_PSP_RIB = 0x76, + AMD_FW_PSP_AMF_SRAM = 0x85, + AMD_FW_PSP_AMF_DRAM = 0x86, + AMD_FW_PSP_MFD_MPM = 0x87, + AMD_FW_PSP_AMF_WLAN = 0x88, + AMD_FW_PSP_AMF_MFD = 0x89, + AMD_FW_PSP_MPDMA_TF = 0x8c, + AMD_FW_PSP_TA_IKEK = 0x8d, + AMD_FW_PSP_SFDR = 0x8e, + AMD_FW_PSP_MPCCX = 0x90, + AMD_FW_PSP_GMI3_PHY = 0x91, + AMD_FW_PSP_MPDMA_PM = 0x92, + AMD_FW_PSP_LSDMA = 0x94, + AMD_FW_PSP_C20_MP = 0x95, + AMD_FW_PSP_FCFG_TABLE = 0x98, + AMD_FW_PSP_MINIMSMU = 0x9a, + AMD_FW_PSP_GFXIMU_0 = 0x9b, + AMD_FW_PSP_GFXIMU_1 = 0x9c, + AMD_FW_PSP_SRAM_FW_EXT = 0x9d, + AMD_FW_PSP_UMSMU = 0xa2, + AMD_FW_PSP_S3IMG = 0xa0, + AMD_FW_PSP_USBDP = 0xa4, + AMD_FW_PSP_USBSS = 0xa5, + AMD_FW_PSP_USB4 = 0xa6, + AMD_FW_PSP_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ + AMD_FW_PSP_GEC, + AMD_FW_PSP_XHCI, + AMD_FW_PSP_INVALID, /* Real last one to detect the last entry in table. */ } amd_fw_type; typedef enum _amd_bios_type { @@ -149,7 +152,6 @@ typedef enum _amd_bios_type { AMD_BIOS_NV_ST = 0x6d, AMD_BIOS_L2_PTR = 0x70, AMD_BIOS_INVALID, - AMD_BIOS_SKIP } amd_bios_type; typedef enum _amd_addr_mode { @@ -206,19 +208,19 @@ typedef struct _psp_directory_header { union { uint32_t additional_info; struct { - uint32_t dir_size:10; + uint32_t dir_size:10; /* in 4K blocks */ uint32_t spi_block_size:4; - uint32_t base_addr:15; - uint32_t address_mode:2; - uint32_t version:1; + uint32_t base_addr:15; /* [26:12] of directory base addr */ + uint32_t address_mode:2; /* directory address mode */ + uint32_t version:1; /* Always 0 */ } __attribute__((packed)) additional_info_fields; struct { - uint32_t dir_size:16; - uint32_t spi_block_size:4; - uint32_t dir_header_size:4; - uint32_t address_mode:2; + uint32_t dir_size:16; /* in 4K blocks */ + uint32_t spi_block_size:4; /* 4K << (1 << value) */ + uint32_t dir_hdr_size:4; /* in 1K blocks */ + uint32_t address_mode:2; /* directory address mode */ uint32_t reserved:5; - uint32_t version:1; + uint32_t version:1; /* Always 1 */ } __attribute__((packed)) additional_info_fields_v1; }; } __attribute__((packed, aligned(16))) psp_directory_header; @@ -267,8 +269,6 @@ typedef struct _psp_combo_directory { psp_combo_entry entries[]; } __attribute__((packed, aligned(16))) psp_combo_directory; -#define MAX_COMBO_ENTRIES 2 - typedef struct _bios_directory_hdr { uint32_t cookie; uint32_t checksum; @@ -276,19 +276,19 @@ typedef struct _bios_directory_hdr { union { uint32_t additional_info; struct { - uint32_t dir_size:10; + uint32_t dir_size:10; /* in 4K blocks */ uint32_t spi_block_size:4; uint32_t base_addr:15; uint32_t address_mode:2; - uint32_t version:1; + uint32_t version:1; /* Always 0 */ } __attribute__((packed)) additional_info_fields; struct { - uint32_t dir_size:16; - uint32_t spi_block_size:4; - uint32_t dir_header_size:4; - uint32_t address_mode:2; + uint32_t dir_size:16; /* in 4K blocks */ + uint32_t spi_block_size:4; /* 4K << (1 << value) */ + uint32_t dir_hdr_size:4; /* in 1K blocks */ + uint32_t address_mode:2; /* directory address mode */ uint32_t reserved:5; - uint32_t version:1; + uint32_t version:1; /* Always 1 */ } __attribute__((packed)) additional_info_fields_v1; }; } __attribute__((packed, aligned(16))) bios_directory_hdr; @@ -296,12 +296,15 @@ typedef struct _bios_directory_hdr { typedef struct _bios_directory_entry { uint8_t type; uint8_t region_type; - int reset:1; - int copy:1; - int ro:1; - int compressed:1; - int inst:4; - uint8_t subprog; /* b[7:3] reserved */ + uint8_t reset:1; + uint8_t copy:1; + uint8_t ro:1; + uint8_t compressed:1; + uint8_t inst:4; + uint8_t subprog:3; + uint8_t romid:2; + uint8_t writable:1; + uint8_t rsvd:2; uint32_t size; uint64_t source:62; uint64_t address_mode:2; @@ -450,25 +453,20 @@ typedef struct _amd_cb_config { bool unlock_secure; bool use_secureos; bool load_mp2_fw; - bool multi_level; bool s0i3; - bool second_gen; bool have_mb_spl; bool recovery_ab; bool recovery_ab_single_copy; - bool need_ish; - bool use_combo; - bool combo_new_rab; /* new combo layout for recovery A/B */ bool have_apcb_bk; enum platform soc_id; uint8_t efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag; - uint32_t body_location, efs_location; + uint32_t body_location, efs_location, ral2_location, rbl2_location; uint64_t signed_start_addr; + uint32_t rom_size; char *manifest_file; const char *signed_output_file; char *output, *config; - char *combo_config[MAX_COMBO_ENTRIES]; int debug; } amd_cb_config; @@ -479,18 +477,12 @@ typedef struct _context { uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current_pointer_saved; uint32_t current_table; - uint32_t combo_index; + uint32_t current_a_pointer, current_b_pointer, current_l1_pointer; void *amd_psp_fw_table_clean; void *amd_bios_table_clean; - struct _combo_apcb { - char *filename; - uint8_t ins; - uint8_t sub; - } combo_apcb[MAX_COMBO_ENTRIES], combo_apcb_bk[MAX_COMBO_ENTRIES]; embedded_firmware *amd_romsig_ptr; psp_directory_table *pspdir, *pspdir_bak, *pspdir2, *pspdir2_b; bios_directory_table *biosdir, *biosdir2, *biosdir2_b; - psp_combo_directory *psp_combo_dir, *bhd_combo_dir; ish_directory_table *ish_a_dir, *ish_b_dir; } context; @@ -504,18 +496,31 @@ int find_bios_entry(amd_bios_type type); #define EFS_FILE_SUFFIX ".efs" #define TMP_FILE_SUFFIX ".tmp" #define BODY_FILE_SUFFIX ".body" +#define RA_FILE_SUFFIX ".ra" +#define RB_FILE_SUFFIX ".rb" void write_or_fail(int fd, void *ptr, size_t size); ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size); ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size); -ssize_t write_body(char *output, void *body_offset, ssize_t body_size); -ssize_t copy_blob(void *dest, const char *src_file, size_t room); +ssize_t write_blob(char *output, void *body_offset, ssize_t body_size, char *suffix); +ssize_t copy_blob(context *ctx, const char *src_file); #define OK 0 #define LINE_EOF (1) #define LINE_TOO_LONG (2) -int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx); -void register_apcb_combo(amd_cb_config *cb_config, int combo_index, context *ctx); +int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config); + + +enum platform platform_identify(char *soc_name); +bool platform_needs_ish(enum platform platform_type); +bool platform_is_multi_level(enum platform platform_type); +bool platform_is_second_gen(enum platform platform_type); +bool platform_has_dir_header_v1(enum platform platform_type); +bool platform_has_apob_nv_quirk(enum platform platform_type); +uint32_t platform_get_psp_id(enum platform platform_type); +bool platform_is_initial_alignment_required(enum platform platform_type); +bool platform_has_legacy_ab_recovery(amd_cb_config *cb_config); +bool platform_psb_reserved_size(enum platform platform_type); #endif /* _AMD_FW_TOOL_H_ */ diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 314d741b6b7..ac526bb55fc 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -9,6 +9,146 @@ #include "amdfwtool.h" +struct psp_fw_name_entry { + const char *name; + amd_fw_type type; + uint8_t subprog; + uint8_t instance; +}; + +static const struct psp_fw_name_entry psp_fw_name_table[] = { + /* Name , type , subprog, instance */ + { "PSPBTLDR_WL_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0, 0 }, + { "PSPBTLDR_AB_STAGE1_FILE", AMD_FW_PSP_BOOTLOADER, 0, 0 }, + { "PSPBTLDR_FILE", AMD_FW_PSP_BOOTLOADER, 0, 0 }, + { "AMD_PUBKEY_FILE", AMD_FW_PSP_PUBKEY, 0, 0 }, + { "AMD_FUSE_CHAIN", AMD_FW_PSP_FUSE_CHAIN, 0, 0 }, + { "PSPRCVR_FILE", AMD_FW_PSP_RECOVERY, 0, 0 }, + { "PUBSIGNEDKEY_FILE", AMD_FW_PSP_RTM_PUBKEY, 0, 0 }, + { "PSPNVRAM_FILE", AMD_FW_PSP_NVRAM, 0, 0 }, + { "SMUSCS_FILE", AMD_FW_PSP_SMUSCS, 0, 0 }, + { "PSPTRUSTLETS_FILE", AMD_FW_PSP_TRUSTLETS, 0, 0 }, + { "PSPSECUREDEBUG_FILE", AMD_FW_PSP_SECURED_DEBUG, 0, 0 }, + { "PSP_SMUFW1_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE, 0, 0 }, + { "PSP_HW_IPCFG_FILE_SUB0", AMD_FW_PSP_HW_IPCFG, 0, 0 }, + { "PSP_HW_IPCFG_FILE_SUB1", AMD_FW_PSP_HW_IPCFG, 1, 0 }, + { "PSP_HW_IPCFG_FILE_SUB2", AMD_FW_PSP_HW_IPCFG, 2, 0 }, + { "PSP_SMUFW1_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE, 1, 0 }, + { "PSP_SMUFW1_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE, 2, 0 }, + { "PSP_SMUFW2_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 0, 0 }, + { "PSP_SMUFW2_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 1, 0 }, + { "PSP_TEEIPKEY_FILE", AMD_FW_PSP_TEEIPKEY, 0, 0 }, + { "PSP_SMUFW2_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 2, 0 }, + { "PSP_BOOT_DRIVER_FILE", AMD_FW_PSP_BOOT_DRIVER, 0, 0 }, + { "PSP_SOC_DRIVER_FILE", AMD_FW_PSP_SOC_DRIVER, 0, 0 }, + { "PSP_DEBUG_DRIVER_FILE", AMD_FW_PSP_DEBUG_DRIVER, 0, 0 }, + { "PSP_INTERFACE_DRIVER_FILE", AMD_FW_PSP_INTERFACE_DRIVER, 0, 0 }, + { "PSP_SEC_DBG_KEY_FILE", AMD_FW_PSP_SECURED_DEBUG, 0, 0 }, + { "PSP_SEC_DEBUG_FILE", AMD_FW_PSP_DEBUG_UNLOCK, 0, 0 }, + { "PSP_ABL0_FILE", AMD_FW_PSP_ABL0, 0, 0 }, + { "PSP_ABL1_FILE", AMD_FW_PSP_ABL1, 0, 0 }, + { "PSP_ABL2_FILE", AMD_FW_PSP_ABL2, 0, 0 }, + { "PSP_ABL3_FILE", AMD_FW_PSP_ABL3, 0, 0 }, + { "PSP_ABL4_FILE", AMD_FW_PSP_ABL4, 0, 0 }, + { "PSP_ABL5_FILE", AMD_FW_PSP_ABL5, 0, 0 }, + { "PSP_ABL6_FILE", AMD_FW_PSP_ABL6, 0, 0 }, + { "PSP_ABL7_FILE", AMD_FW_PSP_ABL7, 0, 0 }, + { "PSPSECUREOS_FILE", AMD_FW_PSP_SECURED_OS, 0, 0 }, + { "TRUSTLETKEY_FILE", AMD_FW_PSP_TRUSTLETKEY, 0, 0 }, + { "PSP_IKEK_FILE", AMD_FW_PSP_WRAPPED_IKEK, 0, 0 }, + { "PSP_SECG0_FILE", AMD_FW_PSP_SEC_GASKET, 0, 0 }, + { "PSP_SECG1_FILE", AMD_FW_PSP_SEC_GASKET, 1, 0 }, + { "PSP_SECG2_FILE", AMD_FW_PSP_SEC_GASKET, 2, 0 }, + { "PSP_MP2FW0_FILE", AMD_FW_PSP_MP2_FW, 0, 0 }, + { "PSP_MP2FW1_FILE", AMD_FW_PSP_MP2_FW, 1, 0 }, + { "PSP_MP2FW2_FILE", AMD_FW_PSP_MP2_FW, 2, 0 }, + { "PSP_C20MP_FILE", AMD_FW_PSP_C20_MP, 0, 0 }, + { "AMF_SRAM_FILE", AMD_FW_PSP_AMF_SRAM, 0, 0 }, + { "AMF_DRAM_FILE_INS0", AMD_FW_PSP_AMF_DRAM, 0, 0 }, + { "AMF_DRAM_FILE_INS1", AMD_FW_PSP_AMF_DRAM, 0, 1 }, + { "MFD_MPM_TEE_INS0", AMD_FW_PSP_MFD_MPM, 0, 0 }, + { "MFD_MPM_TEE_INS1", AMD_FW_PSP_MFD_MPM, 0, 1 }, + { "AMF_WLAN_FILE_INS0", AMD_FW_PSP_AMF_WLAN, 0, 0 }, + { "AMF_WLAN_FILE_INS1", AMD_FW_PSP_AMF_WLAN, 0, 1 }, + { "AMF_WLAN_FILE_INS2", AMD_FW_PSP_AMF_WLAN, 0, 2 }, + { "AMF_WLAN_FILE_INS3", AMD_FW_PSP_AMF_WLAN, 0, 3 }, + { "AMF_MFD_FILE", AMD_FW_PSP_AMF_MFD, 0, 0 }, + { "MPCCX_FILE", AMD_FW_PSP_MPCCX, 0, 0 }, + { "MPCCX_FILE_SUB1_FILE", AMD_FW_PSP_MPCCX, 1, 0 }, + { "LSDMA_FILE", AMD_FW_PSP_LSDMA, 0, 0 }, + { "MINIMSMU_FILE", AMD_FW_PSP_MINIMSMU, 0, 0 }, + { "MINIMSMU_FILE_SUB1_FILE", AMD_FW_PSP_MINIMSMU, 1, 0 }, + { "PSP_GFX_IMMU_FILE_0", AMD_FW_PSP_GFXIMU_0, 0, 0 }, + { "PSP_GFX_IMMU_FILE_0_SUB1", AMD_FW_PSP_GFXIMU_0, 1, 0 }, + { "PSP_GFX_IMMU_FILE_1", AMD_FW_PSP_GFXIMU_1, 0, 0 }, + { "PSP_GFX_IMMU_FILE_1_SUB1", AMD_FW_PSP_GFXIMU_1, 1, 0 }, + { "MINIMSMU_FILE_INS1", AMD_FW_PSP_MINIMSMU, 0, 1 }, + { "SRAM_FW_EXT_FILE", AMD_FW_PSP_SRAM_FW_EXT, 0, 0 }, + { "PSP_DRIVERS_FILE", AMD_FW_PSP_DRIVER_ENTRIES, 0, 0 }, + { "PSP_S0I3_FILE", AMD_FW_PSP_S0I3_DRIVER, 0, 0 }, + { "AMD_DRIVER_ENTRIES", AMD_FW_PSP_DRIVER_ENTRIES, 0, 0 }, + { "VBIOS_BTLOADER_FILE", AMD_FW_PSP_VBIOS_BTLOADER, 0, 0 }, + { "SECURE_POLICY_L1_FILE", AMD_FW_PSP_TOS_SEC_POLICY, 0, 0 }, + { "UNIFIEDUSB_FILE", AMD_FW_PSP_USB_PHY, 0, 0 }, + { "DRTMTA_FILE", AMD_FW_PSP_DRTM_TA, 0, 0 }, + { "KEYDBBL_FILE", AMD_FW_PSP_KEYDB_BL, 0, 0 }, + { "KEYDB_TOS_FILE", AMD_FW_PSP_KEYDB_TOS, 0, 0 }, + { "SPL_TABLE_FILE", AMD_FW_PSP_SPL, 0, 0 }, + { "DMCUERAMDCN21_FILE", AMD_FW_PSP_DMCU_ERAM, 0, 0 }, + { "DMCUINTVECTORSDCN21_FILE", AMD_FW_PSP_DMCU_ISR, 0, 0 }, + { "MSMU_FILE", AMD_FW_PSP_MSMU, 0, 0 }, + { "MSMU_FILE_SUB1_FILE", AMD_FW_PSP_MSMU, 1, 0 }, + { "DMCUB_FILE", AMD_FW_PSP_DMCUB, 0, 0 }, + { "SPIROM_CONFIG_FILE", AMD_FW_PSP_SPIROM_CFG, 0, 0 }, + { "MPIO_FILE", AMD_FW_PSP_MPIO, 0, 0 }, + { "TPMLITE_FILE", AMD_FW_PSP_TPMLITE, 0, 0 }, + { "PSP_KVM_ENGINE_DUMMY_FILE", AMD_FW_PSP_KVM_IMAGE, 0, 0 }, + { "RPMC_FILE", AMD_FW_PSP_RPMC_NVRAM, 0, 0 }, + { "PSPBTLDR_AB_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0, 0 }, + { "TA_IKEK_FILE", AMD_FW_PSP_TA_IKEK, 0, 0 }, + { "SFDR_FILE", AMD_FW_PSP_SFDR, 0, 0 }, + { "UMSMU_FILE", AMD_FW_PSP_UMSMU, 0, 0 }, + { "PSP_S3_IMG", AMD_FW_PSP_S3IMG, 0, 0 }, + { "PSP_USB_DP", AMD_FW_PSP_USBDP, 0, 0 }, + { "PSP_USB_SS", AMD_FW_PSP_USBSS, 0, 0 }, + { "PSP_USB_4", AMD_FW_PSP_USB4, 0, 0 }, + { "PSP_OEM_ABL_KEY_FILE", AMD_FW_PSP_ABL_PUBKEY, 0, 0 }, + { "PSP_MP5FW_SUB0_FILE", AMD_FW_PSP_MP5, 0, 0 }, + { "PSP_MP5FW_SUB1_FILE", AMD_FW_PSP_MP5, 1, 0 }, + { "PSP_MP5FW_SUB2_FILE", AMD_FW_PSP_MP5, 2, 0 }, + { "PSP_DXIOFW_FILE", AMD_FW_PSP_DXIO, 0, 0 }, + { "PSP_MPIOFW_FILE", AMD_FW_PSP_MPIO, 0, 0 }, + { "PSP_RIB_FILE_SUB0", AMD_FW_PSP_RIB, 0, 0 }, + { "PSP_RIB_FILE_SUB1", AMD_FW_PSP_RIB, 1, 0 }, + { "PSP_RIB_FILE_SUB2", AMD_FW_PSP_RIB, 2, 0 }, + { "FEATURE_TABLE_FILE", AMD_FW_PSP_FCFG_TABLE, 0, 0 }, + { "PSP_MPDMATFFW_FILE", AMD_FW_PSP_MPDMA_TF, 0, 0 }, + { "PSP_GMI3PHYFW_FILE", AMD_FW_PSP_GMI3_PHY, 0, 0 }, + { "PSP_MPDMAPMFW_FILE", AMD_FW_PSP_MPDMA_PM, 0, 0 }, + { "PSP_TOKEN_UNLOCK_FILE", AMD_FW_PSP_TOKEN_UNLOCK, 0, 0 }, + { "SEV_DATA_FILE", AMD_FW_PSP_SEV_DATA, 0, 0 }, + { "SEV_CODE_FILE", AMD_FW_PSP_SEV_CODE, 0, 0 }, + { NULL, AMD_FW_PSP_INVALID, 0, 0 }, +}; + +static amd_fw_type psp_fw_type_lookup(const char *fw_name, uint8_t *subprog, uint8_t *instance) +{ + const struct psp_fw_name_entry *entry = psp_fw_name_table; + + while (entry->name != NULL) { + if (strcmp(fw_name, entry->name) == 0) { + *subprog = entry->subprog; + *instance = entry->instance; + return entry->type; + } + entry++; + } + + *subprog = 0; + *instance = 0; + return AMD_FW_PSP_INVALID; +} + /* TODO: a empty line does not matched. */ static const char blank_or_comment_regex[] = /* a blank line */ @@ -93,38 +233,6 @@ void compile_reg_expr(int cflags, const char *expr, regex_t *reg) } } -static enum platform identify_platform(char *soc_name) -{ - if (!strcasecmp(soc_name, "Stoneyridge")) - return PLATFORM_STONEYRIDGE; - else if (!strcasecmp(soc_name, "Carrizo")) - return PLATFORM_CARRIZO; - else if (!strcasecmp(soc_name, "Raven")) - return PLATFORM_RAVEN; - else if (!strcasecmp(soc_name, "Picasso")) - return PLATFORM_PICASSO; - else if (!strcasecmp(soc_name, "Cezanne")) - return PLATFORM_CEZANNE; - else if (!strcasecmp(soc_name, "Mendocino")) - return PLATFORM_MENDOCINO; - else if (!strcasecmp(soc_name, "Renoir")) - return PLATFORM_RENOIR; - else if (!strcasecmp(soc_name, "Lucienne")) - return PLATFORM_LUCIENNE; - else if (!strcasecmp(soc_name, "Phoenix")) - return PLATFORM_PHOENIX; - else if (!strcasecmp(soc_name, "Strix")) - return PLATFORM_STRIX; - else if (!strcasecmp(soc_name, "Genoa")) - return PLATFORM_GENOA; - else if (!strcasecmp(soc_name, "Krackan2e")) - return PLATFORM_KRACKAN2E; - else if (!strcasecmp(soc_name, "Strixhalo")) - return PLATFORM_STRIXHALO; - else - return PLATFORM_UNKNOWN; -} - #define SET_LEVEL(tableptr, l, TABLE, ab) \ do { \ switch ((l)) { \ @@ -148,444 +256,83 @@ extern amd_fw_entry amd_psp_fw_table[]; extern amd_bios_entry amd_bios_table[]; static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, - char level_to_set, uint8_t hash_tbl_id, fwid_type_t fwid_type, - amd_cb_config *cb_config) + char level_to_set, uint8_t hash_tbl_id, + fwid_type_t fwid_type, amd_cb_config *cb_config) { - amd_fw_type fw_type = AMD_FW_INVALID; + amd_fw_type fw_type; amd_fw_entry *psp_tableptr; uint8_t subprog; - uint8_t instance = 0; + uint8_t instance; - if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - if (cb_config->have_whitelist) { - fw_type = AMD_FW_PSP_BOOTLOADER_AB; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSPBTLDR_AB_STAGE1_FILE") == 0) { - if (cb_config->recovery_ab) { - fw_type = AMD_FW_PSP_BOOTLOADER; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { - if (!cb_config->recovery_ab) { - fw_type = AMD_FW_PSP_BOOTLOADER; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { - fw_type = AMD_FW_PSP_PUBKEY; - subprog = 0; - } else if (strcmp(fw_name, "AMD_FUSE_CHAIN") == 0) { - fw_type = AMD_PSP_FUSE_CHAIN; - subprog = 0; - } else if (strcmp(fw_name, "PSPRCVR_FILE") == 0) { - fw_type = AMD_FW_PSP_RECOVERY; - subprog = 0; - } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { - fw_type = AMD_FW_PSP_RTM_PUBKEY; - subprog = 0; - } else if (strcmp(fw_name, "PSPNVRAM_FILE") == 0) { - fw_type = AMD_FW_PSP_NVRAM; - subprog = 0; - } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { - fw_type = AMD_FW_PSP_SMUSCS; - subprog = 0; - } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - fw_type = AMD_FW_PSP_TRUSTLETS; - subprog = 0; - } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { - fw_type = AMD_FW_PSP_SECURED_DEBUG; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 0; - } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB0") == 0) { - fw_type = AMD_HW_IPCFG; - subprog = 0; - } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB1") == 0) { - fw_type = AMD_HW_IPCFG; - subprog = 1; - } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB2") == 0) { - fw_type = AMD_HW_IPCFG; - subprog = 2; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 1; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 2; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB0_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 1; - } else if (strcmp(fw_name, "PSP_TEEIPKEY_FILE") == 0) { - fw_type = AMD_FW_PSP_TEEIPKEY; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 2; - } else if (strcmp(fw_name, "PSP_BOOT_DRIVER_FILE") == 0) { - fw_type = AMD_BOOT_DRIVER; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SOC_DRIVER_FILE") == 0) { - fw_type = AMD_SOC_DRIVER; - subprog = 0; - } else if (strcmp(fw_name, "PSP_DEBUG_DRIVER_FILE") == 0) { - fw_type = AMD_DEBUG_DRIVER; - subprog = 0; - } else if (strcmp(fw_name, "PSP_INTERFACE_DRIVER_FILE") == 0) { - fw_type = AMD_INTERFACE_DRIVER; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { - if (cb_config->unlock_secure) { - fw_type = AMD_FW_PSP_SECURED_DEBUG; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { - if (cb_config->unlock_secure) { - fw_type = AMD_DEBUG_UNLOCK; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { - fw_type = AMD_ABL0; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { - fw_type = AMD_ABL1; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { - fw_type = AMD_ABL2; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { - fw_type = AMD_ABL3; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { - fw_type = AMD_ABL4; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { - fw_type = AMD_ABL5; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { - fw_type = AMD_ABL6; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { - fw_type = AMD_ABL7; - subprog = 0; - } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_SECURED_OS; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_TRUSTLETS; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_TRUSTLETKEY; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { - fw_type = AMD_WRAPPED_IKEK; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 1; - } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 2; - } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 1; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 2; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "PSP_C20MP_FILE") == 0) { - fw_type = AMD_FW_C20_MP; - subprog = 0; - } else if (strcmp(fw_name, "AMF_SRAM_FILE") == 0) { - fw_type = AMD_FW_AMF_SRAM; - subprog = 0; - } else if (strcmp(fw_name, "AMF_DRAM_FILE_INS0") == 0) { - fw_type = AMD_FW_AMF_DRAM; - subprog = 0; - instance = 0; - } else if (strcmp(fw_name, "AMF_DRAM_FILE_INS1") == 0) { - fw_type = AMD_FW_AMF_DRAM; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "MFD_MPM_TEE_INS0") == 0) { - fw_type = AMD_FW_MFD_MPM; - subprog = 0; - instance = 0; - } else if (strcmp(fw_name, "MFD_MPM_TEE_INS1") == 0) { - fw_type = AMD_FW_MFD_MPM; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS0") == 0) { - fw_type = AMD_FW_AMF_WLAN; - subprog = 0; - instance = 0; - } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS1") == 0) { - fw_type = AMD_FW_AMF_WLAN; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS2") == 0) { - fw_type = AMD_FW_AMF_WLAN; - subprog = 0; - instance = 2; - } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS3") == 0) { - fw_type = AMD_FW_AMF_WLAN; - subprog = 0; - instance = 3; - } else if (strcmp(fw_name, "AMF_MFD_FILE") == 0) { - fw_type = AMD_FW_AMF_MFD; - subprog = 0; - } else if (strcmp(fw_name, "MPCCX_FILE") == 0) { - fw_type = AMD_FW_MPCCX; - subprog = 0; - } else if (strcmp(fw_name, "MPCCX_FILE_SUB1_FILE") == 0) { - fw_type = AMD_FW_MPCCX; - subprog = 1; - } else if (strcmp(fw_name, "LSDMA_FILE") == 0) { - fw_type = AMD_FW_LSDMA; - subprog = 0; - } else if (strcmp(fw_name, "MINIMSMU_FILE") == 0) { - fw_type = AMD_FW_MINIMSMU; - instance = 0; - subprog = 0; - } else if (strcmp(fw_name, "MINIMSMU_FILE_SUB1_FILE") == 0) { - fw_type = AMD_FW_MINIMSMU; - instance = 0; - subprog = 1; - } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_0") == 0) { - fw_type = AMD_FW_GFXIMU_0; - instance = 0; - subprog = 0; - } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_01") == 0) { - fw_type = AMD_FW_GFXIMU_0; - instance = 0; - subprog = 1; - } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_1") == 0) { - fw_type = AMD_FW_GFXIMU_1; - instance = 0; - subprog = 0; - } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_11") == 0) { - fw_type = AMD_FW_GFXIMU_1; - instance = 0; - subprog = 1; - } else if (strcmp(fw_name, "MINIMSMU_FILE_INS1") == 0) { - fw_type = AMD_FW_MINIMSMU; - instance = 1; - subprog = 0; - } else if (strcmp(fw_name, "SRAM_FW_EXT_FILE") == 0) { - fw_type = AMD_FW_SRAM_FW_EXT; - subprog = 0; - } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { - fw_type = AMD_DRIVER_ENTRIES; - subprog = 0; - } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { - if (cb_config->s0i3) { - fw_type = AMD_S0I3_DRIVER; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "AMD_DRIVER_ENTRIES") == 0) { - fw_type = AMD_DRIVER_ENTRIES; - subprog = 0; - } else if (strcmp(fw_name, "VBIOS_BTLOADER_FILE") == 0) { - fw_type = AMD_VBIOS_BTLOADER; - subprog = 0; - } else if (strcmp(fw_name, "SECURE_POLICY_L1_FILE") == 0) { - fw_type = AMD_FW_TOS_SEC_POLICY; - subprog = 0; - } else if (strcmp(fw_name, "UNIFIEDUSB_FILE") == 0) { - fw_type = AMD_FW_USB_PHY; - subprog = 0; - } else if (strcmp(fw_name, "DRTMTA_FILE") == 0) { - fw_type = AMD_FW_DRTM_TA; - subprog = 0; - } else if (strcmp(fw_name, "KEYDBBL_FILE") == 0) { - fw_type = AMD_FW_KEYDB_BL; - subprog = 0; - } else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) { - fw_type = AMD_FW_KEYDB_TOS; - subprog = 0; - } else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) { - if (cb_config->have_mb_spl) { - fw_type = AMD_FW_SKIP; - } else { - fw_type = AMD_FW_SPL; - subprog = 0; - } - } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { - fw_type = AMD_FW_DMCU_ERAM; - subprog = 0; - } else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) { - fw_type = AMD_FW_DMCU_ISR; - subprog = 0; - } else if (strcmp(fw_name, "MSMU_FILE") == 0) { - fw_type = AMD_FW_MSMU; - subprog = 0; - } else if (strcmp(fw_name, "MSMU_FILE_SUB1_FILE") == 0) { - fw_type = AMD_FW_MSMU; - subprog = 1; - } else if (strcmp(fw_name, "DMCUB_FILE") == 0) { - fw_type = AMD_FW_DMCUB; - subprog = 0; - } else if (strcmp(fw_name, "SPIROM_CONFIG_FILE") == 0) { - fw_type = AMD_FW_SPIROM_CFG; - subprog = 0; - } else if (strcmp(fw_name, "MPIO_FILE") == 0) { - fw_type = AMD_FW_MPIO; - subprog = 0; - } else if (strcmp(fw_name, "TPMLITE_FILE") == 0) { - fw_type = AMD_FW_TPMLITE; - subprog = 0; - } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { - fw_type = AMD_FW_KVM_IMAGE; - subprog = 0; - } else if (strcmp(fw_name, "RPMC_FILE") == 0) { - fw_type = AMD_RPMC_NVRAM; - subprog = 0; - } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - if (!cb_config->have_whitelist || cb_config->recovery_ab) { - fw_type = AMD_FW_PSP_BOOTLOADER_AB; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } - } else if (strcmp(fw_name, "TA_IKEK_FILE") == 0) { - fw_type = AMD_TA_IKEK; - subprog = 0; - } else if (strcmp(fw_name, "UMSMU_FILE") == 0) { - fw_type = AMD_FW_UMSMU; - subprog = 0; - } else if (strcmp(fw_name, "PSP_S3_IMG") == 0) { - fw_type = AMD_FW_S3IMG; - subprog = 0; - } else if (strcmp(fw_name, "PSP_USB_DP") == 0) { - fw_type = AMD_FW_USBDP; - subprog = 0; - } else if (strcmp(fw_name, "PSP_USB_SS") == 0) { - fw_type = AMD_FW_USBSS; - subprog = 0; - } else if (strcmp(fw_name, "PSP_USB_4") == 0) { - fw_type = AMD_FW_USB4; - subprog = 0; - } else if (strcmp(fw_name, "PSP_OEM_ABL_KEY_FILE") == 0) { - fw_type = AMD_FW_ABL_PUBKEY; - subprog = 0; - } else if (strcmp(fw_name, "PSP_MP5FW_SUB0_FILE") == 0) { - fw_type = AMD_FW_MP5; - subprog = 0; - } else if (strcmp(fw_name, "PSP_MP5FW_SUB1_FILE") == 0) { - fw_type = AMD_FW_MP5; - subprog = 1; - } else if (strcmp(fw_name, "PSP_MP5FW_SUB2_FILE") == 0) { - fw_type = AMD_FW_MP5; - subprog = 2; - } else if (strcmp(fw_name, "PSP_DXIOFW_FILE") == 0) { - fw_type = AMD_FW_DXIO; - subprog = 0; - } else if (strcmp(fw_name, "PSP_MPIOFW_FILE") == 0) { - fw_type = AMD_FW_MPIO; - subprog = 0; - } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB0") == 0) { - fw_type = AMD_RIB; - subprog = 0; - } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB1") == 0) { - fw_type = AMD_RIB; - subprog = 1; - } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB2") == 0) { - fw_type = AMD_RIB; - subprog = 2; - } else if (strcmp(fw_name, "FEATURE_TABLE_FILE") == 0) { - fw_type = AMD_FW_FCFG_TABLE; - subprog = 0; - } else if (strcmp(fw_name, "PSP_MPDMATFFW_FILE") == 0) { - fw_type = AMD_FW_MPDMA_TF; - subprog = 0; - } else if (strcmp(fw_name, "PSP_GMI3PHYFW_FILE") == 0) { - fw_type = AMD_FW_GMI3_PHY; - subprog = 0; - } else if (strcmp(fw_name, "PSP_MPDMAPMFW_FILE") == 0) { - fw_type = AMD_FW_MPDMA_PM; - subprog = 0; - } else if (strcmp(fw_name, "PSP_TOKEN_UNLOCK_FILE") == 0) { - fw_type = AMD_TOKEN_UNLOCK; - subprog = 0; - } else if (strcmp(fw_name, "SEV_DATA_FILE") == 0) { - fw_type = AMD_SEV_DATA; - subprog = 0; - } else if (strcmp(fw_name, "SEV_CODE_FILE") == 0) { - fw_type = AMD_SEV_CODE; - subprog = 0; - } else { - fw_type = AMD_FW_INVALID; - /* TODO: Add more */ + fw_type = psp_fw_type_lookup(fw_name, &subprog, &instance); + if (fw_type == AMD_FW_PSP_INVALID) + return 0; + + /* Apply quirks based on cb_config. Returning 1 means skip the entry. */ + if (fw_type == AMD_FW_PSP_BOOTLOADER_AB) { + if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0 && + cb_config->have_whitelist && + !cb_config->recovery_ab) + return 1; + if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0 && + !cb_config->have_whitelist) + return 1; + } else if (fw_type == AMD_FW_PSP_BOOTLOADER) { + if (strcmp(fw_name, "PSPBTLDR_AB_STAGE1_FILE") == 0 && + !cb_config->recovery_ab) + return 1; + if (strcmp(fw_name, "PSPBTLDR_FILE") == 0 && + cb_config->recovery_ab) + return 1; + } else if (fw_type == AMD_FW_PSP_SECURED_DEBUG) { + if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0 && + !cb_config->unlock_secure) + return 1; + } else if (fw_type == AMD_FW_PSP_DEBUG_UNLOCK) { + if (!cb_config->unlock_secure) + return 1; + } else if (fw_type == AMD_FW_PSP_SECURED_OS) { + if (!cb_config->use_secureos) + return 1; + } else if (fw_type == AMD_FW_PSP_TRUSTLETKEY) { + if (!cb_config->use_secureos) + return 1; + } else if (fw_type == AMD_FW_PSP_TRUSTLETS) { + if (!cb_config->use_secureos) + return 1; + } else if (fw_type == AMD_FW_PSP_MP2_FW) { + if (!cb_config->load_mp2_fw) + return 1; + } else if (fw_type == AMD_FW_PSP_S0I3_DRIVER) { + if (!cb_config->s0i3) + return 1; + } else if (fw_type == AMD_FW_PSP_SPL) { + if (cb_config->have_mb_spl) + return 1; } /* Search and fill the filename */ psp_tableptr = &amd_psp_fw_table[0]; - if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) { - while (psp_tableptr->type != AMD_FW_INVALID) { - /* instance are not used in PSP table */ - if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog - && psp_tableptr->inst == instance) { - if (psp_tableptr->type != AMD_PSP_FUSE_CHAIN) { - psp_tableptr->filename = filename; - psp_tableptr->hash_tbl_id = hash_tbl_id; - psp_tableptr->fwid_type = fwid_type; - } - SET_LEVEL(psp_tableptr, level_to_set, PSP, - cb_config->recovery_ab); - break; + while (psp_tableptr->type != AMD_FW_PSP_INVALID) { + /* instance are not used in PSP table */ + if (psp_tableptr->type == fw_type && + psp_tableptr->subprog == subprog && + psp_tableptr->inst == instance) { + if (psp_tableptr->type != AMD_FW_PSP_FUSE_CHAIN) { + psp_tableptr->filename = filename; + psp_tableptr->hash_tbl_id = hash_tbl_id; + psp_tableptr->fwid_type = fwid_type; } - psp_tableptr++; + SET_LEVEL(psp_tableptr, level_to_set, PSP, + cb_config->recovery_ab); + break; } + psp_tableptr++; } - if (fw_type == AMD_FW_INVALID) - return 0; - else - return 1; + + return 1; } + #define PMUI_STR_BASE "PSP_PMUI_FILE" #define PMUD_STR_BASE "PSP_PMUD_FILE" #define PMU_STR_BASE_LEN strlen(PMUI_STR_BASE) @@ -593,60 +340,63 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, #define PMU_STR_INS_INDEX strlen(PMUI_STR_BASE"_SUBx_INS") #define PMU_STR_ALL_LEN strlen(PMUI_STR_BASE"_SUBx_INSx") -static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, - char level_to_set, amd_cb_config *cb_config) +static amd_bios_type bios_fw_type_lookup(char *fw_name, uint8_t *subprog, uint8_t *instance) { - amd_bios_type fw_type = AMD_BIOS_INVALID; - amd_bios_entry *bhd_tableptr; - uint8_t subprog = 0; - uint8_t instance = 0; - - (void) (cb_config); /* Remove warning and reserved for future. */ - if (strncmp(fw_name, PMUI_STR_BASE, PMU_STR_BASE_LEN) == 0) { assert(strlen(fw_name) == PMU_STR_ALL_LEN); - fw_type = AMD_BIOS_PMUI; - subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16); - instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16); + *subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16); + *instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16); + return AMD_BIOS_PMUI; } else if (strncmp(fw_name, PMUD_STR_BASE, PMU_STR_BASE_LEN) == 0) { assert(strlen(fw_name) == PMU_STR_ALL_LEN); - fw_type = AMD_BIOS_PMUD; - subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16); - instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16); + *subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16); + *instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16); + return AMD_BIOS_PMUD; } else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) { - fw_type = AMD_BIOS_RTM_PUBKEY; - subprog = 0; - instance = 0; + *subprog = 0; + *instance = 0; + return AMD_BIOS_RTM_PUBKEY; } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_BIOS_MP2_CFG; - subprog = 0; - } else { - fw_type = AMD_BIOS_SKIP; - } - } else { - fw_type = AMD_BIOS_INVALID; + *subprog = 0; + *instance = 0; + return AMD_BIOS_MP2_CFG; } - bhd_tableptr = amd_bios_table; + *subprog = 0; + *instance = 0; + return AMD_BIOS_INVALID; +} - if (fw_type != AMD_BIOS_INVALID && fw_type != AMD_BIOS_SKIP) { - while (bhd_tableptr->type != AMD_BIOS_INVALID) { - if (bhd_tableptr->type == fw_type && - bhd_tableptr->subpr == subprog && - bhd_tableptr->inst == instance) { - bhd_tableptr->filename = filename; - SET_LEVEL(bhd_tableptr, level_to_set, BDT, - cb_config->recovery_ab); - break; - } - bhd_tableptr++; - } - } +static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, + char level_to_set, amd_cb_config *cb_config) +{ + amd_bios_type fw_type = AMD_BIOS_INVALID; + amd_bios_entry *bhd_tableptr; + uint8_t subprog = 0; + uint8_t instance = 0; + + fw_type = bios_fw_type_lookup(fw_name, &subprog, &instance); if (fw_type == AMD_BIOS_INVALID) return 0; - else + + /* Apply quirks based on cb_config */ + if (fw_type == AMD_BIOS_MP2_CFG && !cb_config->load_mp2_fw) return 1; + + bhd_tableptr = amd_bios_table; + while (bhd_tableptr->type != AMD_BIOS_INVALID) { + if (bhd_tableptr->type == fw_type && + bhd_tableptr->subpr == subprog && + bhd_tableptr->inst == instance) { + bhd_tableptr->filename = filename; + SET_LEVEL(bhd_tableptr, level_to_set, BDT, + cb_config->recovery_ab); + break; + } + bhd_tableptr++; + } + + return 1; } #define MAX_LINE_SIZE 1024 @@ -790,46 +540,6 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir, return 1; } -static bool needs_ish(enum platform platform_type) -{ - if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX || - platform_type == PLATFORM_STRIX || platform_type == PLATFORM_KRACKAN2E || - platform_type == PLATFORM_STRIXHALO) - return true; - else - return false; -} - -static bool needs_new_combo_layout(enum platform soc_id) -{ - return needs_ish(soc_id); -} - -static bool is_second_gen(enum platform platform_type) -{ - switch (platform_type) { - case PLATFORM_CARRIZO: - case PLATFORM_STONEYRIDGE: - case PLATFORM_RAVEN: - case PLATFORM_PICASSO: - return false; - case PLATFORM_RENOIR: - case PLATFORM_LUCIENNE: - case PLATFORM_CEZANNE: - case PLATFORM_MENDOCINO: - case PLATFORM_PHOENIX: - case PLATFORM_STRIX: - case PLATFORM_GENOA: - case PLATFORM_KRACKAN2E: - case PLATFORM_STRIXHALO: - return true; - case PLATFORM_UNKNOWN: - default: - fprintf(stderr, "Error: Invalid SOC name.\n\n"); - return false; - } -} - #define FW_LOCATION "FIRMWARE_LOCATION" #define SOC_NAME "SOC_NAME" /* @@ -843,6 +553,7 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config) regmatch_t match[N_MATCHES]; char dir[MAX_LINE_SIZE] = {'\0'}; uint32_t dir_len; + char *platform_name = NULL; int index; for (index = 0; index < N_MATCHES; index++) { @@ -868,26 +579,25 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config) snprintf(dir, MAX_LINE_SIZE, "%.*s", dir_len, &(oneline[match[FW_FILE].rm_so])); } else if (strcmp(&(oneline[match[FW_TYPE].rm_so]), SOC_NAME) == 0) { - cb_config->soc_id = identify_platform( - &(oneline[match[FW_FILE].rm_so])); + platform_name = strdup(&(oneline[match[FW_FILE].rm_so])); + cb_config->soc_id = platform_identify(platform_name); } } } - cb_config->second_gen = is_second_gen(cb_config->soc_id); - - if (needs_ish(cb_config->soc_id)) - cb_config->need_ish = true; + if (!platform_name) { + fprintf(stderr, "AMDFWTOOL: Platform not specified in config\n"); + return 0; + } else if (cb_config->soc_id == PLATFORM_UNKNOWN) { + fprintf(stderr, "AMDFWTOOL: Unknown platform '%s'\n", platform_name); + free(platform_name); + return 0; + } + free(platform_name); - if (cb_config->need_ish) + if (platform_needs_ish(cb_config->soc_id)) cb_config->recovery_ab = true; - if (cb_config->use_combo && needs_new_combo_layout(cb_config->soc_id)) - cb_config->combo_new_rab = true; - - if (cb_config->recovery_ab) - cb_config->multi_level = true; - if (dir[0] == '\0') { fprintf(stderr, "No line with FIRMWARE_LOCATION\n"); return 0; diff --git a/util/amdfwtool/handle_file.c b/util/amdfwtool/handle_file.c index c37bb2c8eb5..cfb2fc8c685 100644 --- a/util/amdfwtool/handle_file.c +++ b/util/amdfwtool/handle_file.c @@ -83,7 +83,7 @@ ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size) return buf_size; } -ssize_t write_body(char *output, void *body_offset, ssize_t body_size) +ssize_t write_blob(char *output, void *body_offset, ssize_t body_size, char *suffix) { char body_name[PATH_MAX], body_tmp_name[PATH_MAX]; int ret; @@ -93,7 +93,7 @@ ssize_t write_body(char *output, void *body_offset, ssize_t body_size) /* Create a tmp file and rename it at the end so that make does not get confused if amdfwtool is killed for some unexpected reasons. */ ret = snprintf(body_tmp_name, sizeof(body_tmp_name), "%s%s%s", - output, BODY_FILE_SUFFIX, TMP_FILE_SUFFIX); + output, suffix, TMP_FILE_SUFFIX); if (ret < 0) { fprintf(stderr, "Error %s forming BODY tmp file name: %d\n", strerror(errno), ret); @@ -117,7 +117,7 @@ ssize_t write_body(char *output, void *body_offset, ssize_t body_size) close(fd); /* Rename the tmp file */ - ret = snprintf(body_name, sizeof(body_name), "%s%s", output, BODY_FILE_SUFFIX); + ret = snprintf(body_name, sizeof(body_name), "%s%s", output, suffix); if (ret < 0) { fprintf(stderr, "Error %s forming BODY file name: %d\n", strerror(errno), ret); return -1; @@ -131,7 +131,8 @@ ssize_t write_body(char *output, void *body_offset, ssize_t body_size) return bytes; } -ssize_t copy_blob(void *dest, const char *src_file, size_t room) +/* Copy the contents of the source file into the rom at current position */ +ssize_t copy_blob(context *ctx, const char *src_file) { int fd; struct stat fd_stat; @@ -150,13 +151,13 @@ ssize_t copy_blob(void *dest, const char *src_file, size_t room) return -2; } - if ((size_t)fd_stat.st_size > room) { + if ((size_t)fd_stat.st_size > (ctx->rom_size - ctx->current)) { fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; } - bytes = read(fd, dest, (size_t)fd_stat.st_size); + bytes = read_from_file_to_buf(fd, ctx->rom + ctx->current, (size_t)fd_stat.st_size); close(fd); if (bytes != (ssize_t)fd_stat.st_size) { fprintf(stderr, "Error while reading %s\n", src_file); diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c index 158eb656aa2..ffc97d9685f 100644 --- a/util/amdfwtool/opts.c +++ b/util/amdfwtool/opts.c @@ -23,9 +23,6 @@ enum { AMDFW_OPT_GEC, AMDFW_OPT_RECOVERY_AB, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, - AMDFW_OPT_USE_COMBO, - AMDFW_OPT_COMBO1_CONFIG, - AMDFW_OPT_MULTILEVEL, AMDFW_OPT_NVRAM, AMDFW_OPT_FUSE, @@ -41,7 +38,6 @@ enum { AMDFW_OPT_INSTANCE, AMDFW_OPT_APCB, - AMDFW_OPT_APCB_COMBO1, AMDFW_OPT_APOBBASE, AMDFW_OPT_BIOSBIN, AMDFW_OPT_BIOSBIN_SOURCE, @@ -61,15 +57,20 @@ enum { AMDFW_OPT_SIGNED_OUTPUT, AMDFW_OPT_SIGNED_ADDR, AMDFW_OPT_BODY_LOCATION, + AMDFW_OPT_VARIABLE_NVRAM_BASE, + AMDFW_OPT_VARIABLE_NVRAM_SIZE, + AMDFW_OPT_RECOVERY_A_LOCATION, + AMDFW_OPT_RECOVERY_B_LOCATION, /* begin after ASCII characters */ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, LONGOPT_SPI_MICRON_FLAG = 258, - LONGOPT_BIOS_SIG = 259, LONGOPT_NVRAM_BASE = 260, LONGOPT_NVRAM_SIZE = 261, LONGOPT_RPMC_NVRAM_BASE = 262, LONGOPT_RPMC_NVRAM_SIZE = 263, + LONGOPT_AB_NVRAM_BASE = 264, + LONGOPT_AB_NVRAM_SIZE = 265, }; static const char optstring[] = {AMDFW_OPT_CONFIG, ':', @@ -83,14 +84,15 @@ static struct option long_options[] = { /* PSP Directory Table items */ {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, - {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, - {"combo-config1", required_argument, 0, AMDFW_OPT_COMBO1_CONFIG }, - {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, + {"variable-nvram-base", required_argument, 0, AMDFW_OPT_VARIABLE_NVRAM_BASE }, + {"variable-nvram-size", required_argument, 0, AMDFW_OPT_VARIABLE_NVRAM_SIZE }, {"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE }, {"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE }, {"rpmc-nvram-base", required_argument, 0, LONGOPT_RPMC_NVRAM_BASE }, {"rpmc-nvram-size", required_argument, 0, LONGOPT_RPMC_NVRAM_SIZE }, + {"ab-nvram-base", required_argument, 0, LONGOPT_AB_NVRAM_BASE }, + {"ab-nvram-size", required_argument, 0, LONGOPT_AB_NVRAM_SIZE }, {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, @@ -104,14 +106,12 @@ static struct option long_options[] = { /* BIOS Directory Table items */ {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, {"apcb", required_argument, 0, AMDFW_OPT_APCB }, - {"apcb-combo1", required_argument, 0, AMDFW_OPT_APCB_COMBO1 }, {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, {"bios-bin-uncomp", no_argument, 0, AMDFW_OPT_BIOSBIN_UNCOMP }, - {"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG }, {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, @@ -120,6 +120,8 @@ static struct option long_options[] = { {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"recovery-a-location", required_argument, 0, AMDFW_OPT_RECOVERY_A_LOCATION }, + {"recovery-b-location", required_argument, 0, AMDFW_OPT_RECOVERY_B_LOCATION }, /* other */ {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, @@ -140,79 +142,89 @@ static struct option long_options[] = { static void usage(void) { printf("amdfwtool: Create AMD Firmware combination\n"); - printf("Usage: amdfwtool [options] --flashsize --output \n"); - printf("--xhci Add XHCI blob\n"); - printf("--imc Add IMC blob\n"); - printf("--gec Add GEC blob\n"); + printf("Usage: amdfwtool [options] --config --flashsize --output \n"); + printf("--xhci Add XHCI blob\n"); + printf("--imc Add IMC blob\n"); + printf("--gec Add GEC blob\n"); printf("\nPSP options:\n"); - printf("--use-combo Use the COMBO layout\n"); - printf("--combo-config1 Config for 1st combo entry\n"); - printf("--multilevel Generate primary and secondary tables\n"); - printf("--nvram Add nvram binary\n"); - printf("--soft-fuse Set soft fuse\n"); - printf("--token-unlock Set token unlock\n"); - printf("--nvram-base Base address of nvram\n"); - printf("--nvram-size Size of nvram\n"); - printf("--rpmc-nvram-base Base address of RPMC nvram\n"); - printf("--rpmc-nvram-size Size of RPMC nvram\n"); - printf("--whitelist Set if there is a whitelist\n"); - printf("--use-pspsecureos Set if psp secure OS is needed\n"); - printf("--load-mp2-fw Set if load MP2 firmware\n"); - printf("--load-s0i3 Set if load s0i3 firmware\n"); - printf("--verstage Add verstage\n"); - printf("--verstage_sig Add verstage signature\n"); - printf("--recovery-ab Use the recovery A/B layout\n"); + printf("--nvram Add nvram binary\n"); + printf("--soft-fuse Set soft fuse\n"); + printf("--token-unlock Set token unlock\n"); + printf("--nvram-base Base address of nvram\n"); + printf("--nvram-size Size of nvram\n"); + printf("--variable-nvram-base Base address of variable nvram\n"); + printf("--variable-nvram-size Size of variable nvram\n"); + printf("--rpmc-nvram-base Base address of RPMC nvram\n"); + printf("--rpmc-nvram-size Size of RPMC nvram\n"); + printf("--whitelist Set if there is a whitelist\n"); + printf("--use-pspsecureos Set if psp secure OS is needed\n"); + printf("--load-mp2-fw Set if load MP2 firmware\n"); + printf("--load-s0i3 Set if load s0i3 firmware\n"); + printf("--verstage Add verstage\n"); + printf("--verstage_sig Add verstage signature\n"); + printf("--recovery-ab Use the recovery A/B layout\n"); + printf("--recovery-a-location Flash offset to recovery A partition\n"); + printf(" Depends on recovery-ab\n"); + printf(" When set generates a separate file with\n"); + printf(" the .ra suffix, containing the PSP L2A and\n"); + printf(" BHD L2A tables.\n"); + printf("--recovery-b-location Flash offset to recovery B partition\n"); + printf(" Depends on recovery-ab\n"); + printf(" When set generates a separate file with\n"); + printf(" the .rb suffix, containing the PSP L2B and\n"); + printf(" BHD L2B tables.\n"); printf("\nBIOS options:\n"); - printf("--instance Sets instance field for the next BIOS\n"); - printf(" firmware\n"); - printf("--apcb Add AGESA PSP customization block\n"); - printf("--apcb-combo1 Add APCB for 1st combo\n"); - printf("--apob-base Destination for AGESA PSP output block\n"); - printf("--apob-nv-base Location of S3 resume data\n"); - printf("--apob-nv-size Size of S3 resume data\n"); - printf("--ucode Add microcode patch\n"); - printf("--bios-bin Add compressed image; auto source address\n"); - printf("--bios-bin-src Address in flash of source if -V not used\n"); - printf("--bios-bin-dest Destination for uncompressed BIOS\n"); - printf("--bios-uncomp-size Uncompressed size of BIOS image\n"); - printf("--output output filename\n"); - printf("--flashsize ROM size in bytes\n"); - printf(" size must be larger than %dKB\n", + printf("--instance Sets instance field for the next BIOS\n"); + printf(" firmware\n"); + printf("--apcb Add AGESA PSP customization block\n"); + printf("--apob-base Destination for AGESA PSP output block\n"); + printf("--apob-nv-base Location of S3 resume data\n"); + printf("--apob-nv-size Size of S3 resume data\n"); + printf("--ucode Add microcode patch\n"); + printf("--bios-bin Add compressed image; auto source address\n"); + printf("--bios-bin-src Address in flash of source if -V not used\n"); + printf("--bios-bin-dest Destination for uncompressed BIOS\n"); + printf("--bios-uncomp-size Uncompressed size of BIOS image\n"); + printf("--output output filename [MANDATORY]\n"); + printf("--flashsize ROM size in bytes [MANDATORY]\n"); + printf(" size must be larger than %dKB\n", MIN_ROM_KB); - printf(" and must a multiple of 1024\n"); - printf("--location Location of Directory\n"); - printf("--anywhere Use any 64-byte aligned addr for Directory\n"); - printf("--sharedmem Location of PSP/FW shared memory\n"); - printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); - printf(" area\n"); - printf("--output-manifest Writes a manifest with the blobs versions\n"); + printf(" and must a multiple of 1024\n"); + printf("--location Location of EFS table [MANDATORY]\n"); + printf("--anywhere Use any 64-byte aligned addr for Directory\n"); + printf("--sharedmem Location of PSP/FW shared memory\n"); + printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); + printf(" area\n"); + printf("--output-manifest Writes a manifest with the blobs versions\n"); printf("\nEmbedded Firmware Structure options used by the PSP:\n"); - printf("--spi-speed SPI fast speed to place in EFS Table\n"); - printf(" 0x0 66.66Mhz\n"); - printf(" 0x1 33.33MHz\n"); - printf(" 0x2 22.22MHz\n"); - printf(" 0x3 16.66MHz\n"); - printf(" 0x4 100MHz\n"); - printf(" 0x5 800KHz\n"); - printf("--spi-read-mode SPI read mode to place in EFS Table\n"); - printf(" 0x0 Normal Read (up to 33M)\n"); - printf(" 0x1 Reserved\n"); - printf(" 0x2 Dual IO (1-1-2)\n"); - printf(" 0x3 Quad IO (1-1-4)\n"); - printf(" 0x4 Dual IO (1-2-2)\n"); - printf(" 0x5 Quad IO (1-4-4)\n"); - printf(" 0x6 Normal Read (up to 66M)\n"); - printf(" 0x7 Fast Read\n"); - printf("--spi-micron-flag Micron SPI part support for RV and later SOC\n"); - printf(" 0x0 Micron parts are not used\n"); - printf(" 0x1 Micron parts are always used\n"); - printf(" 0x2 Micron parts optional, this option is only\n"); + printf("--spi-speed SPI fast speed to place in EFS Table\n"); + printf(" 0x0 66.66Mhz\n"); + printf(" 0x1 33.33MHz\n"); + printf(" 0x2 22.22MHz\n"); + printf(" 0x3 16.66MHz\n"); + printf(" 0x4 100MHz\n"); + printf(" 0x5 800KHz\n"); + printf(" [MANDATORY, except for Mullins]n"); + printf("--spi-read-mode SPI read mode to place in EFS Table\n"); + printf(" 0x0 Normal Read (up to 33M)\n"); + printf(" 0x1 Reserved\n"); + printf(" 0x2 Dual IO (1-1-2)\n"); + printf(" 0x3 Quad IO (1-1-4)\n"); + printf(" 0x4 Dual IO (1-2-2)\n"); + printf(" 0x5 Quad IO (1-4-4)\n"); + printf(" 0x6 Normal Read (up to 66M)\n"); + printf(" 0x7 Fast Read\n"); + printf(" [MANDATORY, except for Mullins]n"); + printf("--spi-micron-flag Micron SPI part support for RV and later SOC\n"); + printf(" 0x0 Micron parts are not used\n"); + printf(" 0x1 Micron parts are always used\n"); + printf(" 0x2 Micron parts optional, this option is only\n"); printf(" supported with RN/LCN SOC\n"); printf("\nGeneral options:\n"); - printf("-c|--config Config file\n"); - printf("-d|--debug Print debug message\n"); - printf("-h|--help Show this help\n"); + printf("-c|--config Config file [MANDATORY]\n"); + printf("-d|--debug Print debug message\n"); + printf("-h|--help Show this help\n"); } extern amd_fw_entry amd_psp_fw_table[]; @@ -224,7 +236,7 @@ static void register_amd_psp_fw_addr(amd_fw_type type, int sub, { unsigned int i; - for (i = 0; amd_psp_fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0; amd_psp_fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (amd_psp_fw_table[i].type != type) continue; @@ -261,8 +273,8 @@ static void register_fw_token_unlock(void) { uint32_t i; - for (i = 0; amd_psp_fw_table[i].type != AMD_FW_INVALID; i++) { - if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) + for (i = 0; amd_psp_fw_table[i].type != AMD_FW_PSP_INVALID; i++) { + if (amd_psp_fw_table[i].type != AMD_FW_PSP_TOKEN_UNLOCK) continue; amd_psp_fw_table[i].other = 1; @@ -274,19 +286,19 @@ static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) { unsigned int i; - for (i = 0; amd_fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0; amd_fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (amd_fw_table[i].type == type) { - amd_fw_table[i].filename = filename; + amd_fw_table[i].filename = strdup(filename); return; } } - for (i = 0; amd_psp_fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0; amd_psp_fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (amd_psp_fw_table[i].type != type) continue; if (amd_psp_fw_table[i].subprog == sub) { - amd_psp_fw_table[i].filename = filename; + amd_psp_fw_table[i].filename = strdup(filename); return; } } @@ -298,9 +310,9 @@ static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { if (amd_bios_table[i].type == type - && amd_bios_table[i].inst == ins - && amd_bios_table[i].subpr == sub) { - amd_bios_table[i].filename = name; + && amd_bios_table[i].inst == ins + && amd_bios_table[i].subpr == sub) { + amd_bios_table[i].filename = strdup(name); return; } } @@ -310,8 +322,8 @@ static void register_fw_fuse(char *str) { uint32_t i; - for (i = 0; amd_psp_fw_table[i].type != AMD_FW_INVALID; i++) { - if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) + for (i = 0; amd_psp_fw_table[i].type != AMD_FW_PSP_INVALID; i++) { + if (amd_psp_fw_table[i].type != AMD_FW_PSP_FUSE_CHAIN) continue; amd_psp_fw_table[i].other = strtoull(str, NULL, 16); @@ -319,31 +331,7 @@ static void register_fw_fuse(char *str) } } -void register_apcb_combo(amd_cb_config *cb_config, int combo_index, context *ctx) -{ - if (ctx->combo_apcb[combo_index].filename != NULL) { - register_bdt_data(AMD_BIOS_APCB, - ctx->combo_apcb[combo_index].sub, - ctx->combo_apcb[combo_index].ins & 0xF, - ctx->combo_apcb[combo_index].filename); - if (cb_config->have_apcb_bk) - register_bdt_data(AMD_BIOS_APCB_BK, - ctx->combo_apcb_bk[combo_index].sub, - ctx->combo_apcb_bk[combo_index].ins & 0xF, - ctx->combo_apcb_bk[combo_index].filename); - } else { - /* Use main APCB if no Combo APCB is provided */ - register_bdt_data(AMD_BIOS_APCB, ctx->combo_apcb[0].sub, - ctx->combo_apcb[0].ins & 0xF, ctx->combo_apcb[0].filename); - if (cb_config->have_apcb_bk) - register_bdt_data(AMD_BIOS_APCB_BK, - ctx->combo_apcb_bk[0].sub, - ctx->combo_apcb_bk[0].ins & 0xF, - ctx->combo_apcb_bk[0].filename); - } -} - -int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx) +int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config) { int c; /* Values cleared after each firmware or parameter, regardless if N/A */ @@ -364,15 +352,15 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * switch (c) { case AMDFW_OPT_XHCI: - register_fw_filename(AMD_FW_XHCI, sub, optarg); + register_fw_filename(AMD_FW_PSP_XHCI, sub, optarg); sub = instance = 0; break; case AMDFW_OPT_IMC: - register_fw_filename(AMD_FW_IMC, sub, optarg); + register_fw_filename(AMD_FW_PSP_IMC, sub, optarg); sub = instance = 0; break; case AMDFW_OPT_GEC: - register_fw_filename(AMD_FW_GEC, sub, optarg); + register_fw_filename(AMD_FW_PSP_GEC, sub, optarg); sub = instance = 0; break; case AMDFW_OPT_RECOVERY_AB: @@ -382,17 +370,6 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * cb_config->recovery_ab = true; cb_config->recovery_ab_single_copy = true; break; - case AMDFW_OPT_USE_COMBO: - cb_config->use_combo = true; - break; - case AMDFW_OPT_COMBO1_CONFIG: - cb_config->use_combo = true; - /* assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); */ - cb_config->combo_config[1] = optarg; - break; - case AMDFW_OPT_MULTILEVEL: - cb_config->multi_level = true; - break; case AMDFW_OPT_UNLOCK: register_fw_token_unlock(); cb_config->unlock_secure = true; @@ -419,29 +396,9 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * case AMDFW_OPT_APCB: if ((instance & 0xF0) == 0) { register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); - ctx->combo_apcb[0].filename = optarg; - ctx->combo_apcb[0].ins = instance; - ctx->combo_apcb[0].sub = sub; } else { register_bdt_data(AMD_BIOS_APCB_BK, sub, instance & 0xF, optarg); - ctx->combo_apcb_bk[0].filename = optarg; - ctx->combo_apcb_bk[0].ins = instance; - ctx->combo_apcb_bk[0].sub = sub; - cb_config->have_apcb_bk = 1; - } - sub = instance = 0; - break; - case AMDFW_OPT_APCB_COMBO1: - /* assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); */ - if ((instance & 0xF0) == 0) { - ctx->combo_apcb[1].filename = optarg; - ctx->combo_apcb[1].ins = instance; - ctx->combo_apcb[1].sub = sub; - } else { - ctx->combo_apcb_bk[1].filename = optarg; - ctx->combo_apcb_bk[1].ins = instance; - ctx->combo_apcb_bk[1].sub = sub; cb_config->have_apcb_bk = 1; } sub = instance = 0; @@ -461,6 +418,16 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); sub = instance = 0; break; + case AMDFW_OPT_VARIABLE_NVRAM_BASE: + /* APOB variable NVRAM base */ + register_bios_fw_addr(AMD_BIOS_NV_ST, optarg, 0, 0); + sub = instance = 0; + break; + case AMDFW_OPT_VARIABLE_NVRAM_SIZE: + /* APOB variable NVRAM size */ + register_bios_fw_addr(AMD_BIOS_NV_ST, 0, 0, optarg); + sub = instance = 0; + break; case AMDFW_OPT_BIOSBIN: register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); sub = instance = 0; @@ -485,11 +452,6 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * if (bios_tbl_index != -1) amd_bios_table[bios_tbl_index].zlib = 0; break; - case LONGOPT_BIOS_SIG: - /* BIOS signature size */ - register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg); - sub = instance = 0; - break; case AMDFW_OPT_UCODE: register_bdt_data(AMD_BIOS_UCODE, sub, instance, optarg); @@ -499,7 +461,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * cb_config->s0i3 = true; break; case AMDFW_OPT_SPL_TABLE: - register_fw_filename(AMD_FW_SPL, sub, optarg); + register_fw_filename(AMD_FW_PSP_SPL, sub, optarg); sub = instance = 0; cb_config->have_mb_spl = true; break; @@ -513,7 +475,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * sub = instance = 0; break; case AMDFW_OPT_VERSTAGE_SIG: - register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + register_fw_filename(AMD_FW_PSP_VERSTAGE_SIG, sub, optarg); sub = instance = 0; break; case AMDFW_OPT_OUTPUT_MANIFEST: @@ -543,7 +505,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * cb_config->output = optarg; break; case AMDFW_OPT_FLASHSIZE: - ctx->rom_size = (uint32_t)strtoul(optarg, &tmp, 16); + cb_config->rom_size = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { fprintf(stderr, "Error: ROM size specified" " incorrectly (%s)\n\n", optarg); @@ -585,12 +547,22 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * break; case LONGOPT_RPMC_NVRAM_BASE: /* PSP RPMC NV base */ - register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, optarg, 0); + register_amd_psp_fw_addr(AMD_FW_PSP_RPMC_NVRAM, sub, optarg, 0); sub = instance = 0; break; case LONGOPT_RPMC_NVRAM_SIZE: /* PSP RPMC NV size */ - register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, 0, optarg); + register_amd_psp_fw_addr(AMD_FW_PSP_RPMC_NVRAM, sub, 0, optarg); + sub = instance = 0; + break; + case LONGOPT_AB_NVRAM_BASE: + /* PSP legacy AB_RECOVERY NV base */ + register_amd_psp_fw_addr(AMD_FW_PSP_AB_NVRAM, sub, optarg, 0); + sub = instance = 0; + break; + case LONGOPT_AB_NVRAM_SIZE: + /* PSP legacy AB_RECOVERY NV size */ + register_amd_psp_fw_addr(AMD_FW_PSP_AB_NVRAM, sub, 0, optarg); sub = instance = 0; break; case AMDFW_OPT_CONFIG: @@ -610,12 +582,22 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * retval = 1; } break; - + case AMDFW_OPT_RECOVERY_A_LOCATION: + cb_config->ral2_location = (uint32_t)strtoul(optarg, &tmp, 16); + break; + case AMDFW_OPT_RECOVERY_B_LOCATION: + cb_config->rbl2_location = (uint32_t)strtoul(optarg, &tmp, 16); + break; default: break; } } + if (!cb_config->config) { + fprintf(stderr, "Error: No configuration file given\n"); + retval = 1; + } + if (!fuse_defined) register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); @@ -624,36 +606,36 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * retval = 1; } - if (ctx->rom_size % 1024 != 0) { + if (cb_config->rom_size % 1024 != 0) { fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" - " 1024 bytes.\n\n", ctx->rom_size); + " 1024 bytes.\n\n", cb_config->rom_size); retval = 1; } - if (ctx->rom_size < MIN_ROM_KB * 1024) { + if (cb_config->rom_size < MIN_ROM_KB * 1024) { fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", - ctx->rom_size / 1024, MIN_ROM_KB); + cb_config->rom_size / 1024, MIN_ROM_KB); retval = 1; } - printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx->rom_size / 1024); + if (!cb_config->efs_location) { + fprintf(stderr, "Error: No EFS location specified\n\n"); + return 1; + } + + printf(" AMDFWTOOL Using ROM size of %dKB\n", cb_config->rom_size / 1024); /* If the flash size is larger than 16M, we assume the given addresses are already relative ones. Otherwise we print error.*/ - if (cb_config->efs_location && cb_config->efs_location > ctx->rom_size) { + if (cb_config->efs_location > cb_config->rom_size) { fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n"); return 1; } - if (cb_config->body_location && cb_config->body_location > ctx->rom_size) { + if (cb_config->body_location && cb_config->body_location > cb_config->rom_size) { fprintf(stderr, "Error: Body location outside of ROM.\n\n"); return 1; } - if (!cb_config->efs_location && cb_config->body_location) { - fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); - return 1; - } - if (cb_config->body_location != cb_config->efs_location && cb_config->body_location < ALIGN(cb_config->efs_location + sizeof(embedded_firmware), @@ -672,7 +654,6 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * } else { /* efs_location is relative address now. */ switch (cb_config->efs_location) { - case 0: case 0xFA0000: case 0xF20000: case 0xE20000: @@ -685,7 +666,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * case 0x620000: case 0x420000: /* Special cases for 8M. */ - if (ctx->rom_size != 0x800000) { + if (cb_config->rom_size != 0x800000) { fprintf(stderr, "Error: Invalid Directory location.\n"); fprintf(stderr, "%x is only for 8M image size.", cb_config->efs_location); return 1; @@ -695,7 +676,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * case 0x320000: case 0x220000: /* Special cases for 4M. */ - if (ctx->rom_size != 0x400000) { + if (cb_config->rom_size != 0x400000) { fprintf(stderr, "Error: Invalid Directory location.\n"); fprintf(stderr, "%x is only for 4M image size.", cb_config->efs_location); return 1; @@ -718,6 +699,31 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context * else printf("\n"); + if (!cb_config->recovery_ab && + (cb_config->ral2_location || cb_config->rbl2_location)) { + fprintf(stderr, "Error: A/B location specified, but argument 'recovery-ab' is missing\n"); + return 1; + } + if (cb_config->recovery_ab && !cb_config->recovery_ab_single_copy && + (!cb_config->ral2_location || !cb_config->rbl2_location)) { + fprintf(stderr, "Error: A/B location not specified, but argument 'recovery-ab' set\n"); + return 1; + } + if (cb_config->recovery_ab_single_copy && cb_config->rbl2_location) { + fprintf(stderr, "Error: B location specified, but argument 'recovery_ab_single_copy' set\n"); + return 1; + } + if (cb_config->ral2_location && cb_config->rbl2_location && + (cb_config->ral2_location == cb_config->rbl2_location)) { + fprintf(stderr, "Error: A location equals B location\n"); + return 1; + } + if ((cb_config->body_location != cb_config->efs_location) && + cb_config->recovery_ab && + (cb_config->ral2_location || cb_config->rbl2_location)) { + fprintf(stderr, "Error: EFS split body isn't supported with A/B location\n"); + return 1; + } if (retval) { usage(); return retval; diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c index 8dbb596a014..cf28be451f3 100644 --- a/util/amdfwtool/signed_psp.c +++ b/util/amdfwtool/signed_psp.c @@ -214,7 +214,7 @@ static void write_psp_firmware_hash(amd_fw_entry *fw_table) { uint8_t hash_tbl_id; - for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { hash_tbl_id = fw_table[i].hash_tbl_id; assert(hash_files[hash_tbl_id].present); @@ -248,7 +248,7 @@ static void write_psp_firmware_hash(amd_fw_entry *fw_table) /* Add all the SHA256 hash entries first followed by SHA384 entries. PSP verstage processes the table in that order. Mixing and matching SHA256 and SHA384 entries will cause the hash verification failure at run-time. */ - for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { hash_tbl_id = fw_table[i].hash_tbl_id; for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) @@ -257,7 +257,7 @@ static void write_psp_firmware_hash(amd_fw_entry *fw_table) } } - for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { hash_tbl_id = fw_table[i].hash_tbl_id; for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { if (fw_table[i].hash_entries[j].sha_len == SHA384_DIGEST_LENGTH) @@ -266,7 +266,7 @@ static void write_psp_firmware_hash(amd_fw_entry *fw_table) } } - for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (unsigned int i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { if (!fw_table[i].num_hash_entries || !fw_table[i].hash_entries) continue; @@ -318,7 +318,7 @@ void process_signed_psp_firmwares(const char *signed_rom, return; } - for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + for (i = 0; fw_table[i].type != AMD_FW_PSP_INVALID; i++) { fw_table[i].num_hash_entries = 0; fw_table[i].hash_entries = NULL; diff --git a/util/amdfwtool/soc.c b/util/amdfwtool/soc.c new file mode 100644 index 00000000000..bb41c0fa163 --- /dev/null +++ b/util/amdfwtool/soc.c @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "amdfwtool.h" + +/* This file contains the SoC quirks. */ + +struct platform_info { + const char *name; + bool needs_ish; + bool is_multi_level; + bool has_apob_nv_quirk; + bool is_initial_alignment_required; + bool is_second_gen; + bool has_dir_header_v1; + uint32_t psp_id; + uint32_t psb_reserved_size; +}; + +static const struct platform_info platform_table[] = { + [PLATFORM_MULLINS] = { + .name = "Mullins", + .needs_ish = false, + .is_multi_level = false, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = false, + .has_dir_header_v1 = false, + .psp_id = 0, + .psb_reserved_size = 0, + }, + [PLATFORM_CARRIZO] = { + .name = "Carrizo", + .needs_ish = false, + .is_multi_level = false, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = false, + .has_dir_header_v1 = false, + .psp_id = 0, + .psb_reserved_size = 0, + }, + [PLATFORM_STONEYRIDGE] = { + .name = "Stoneyridge", + .needs_ish = false, + .is_multi_level = false, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = false, + .has_dir_header_v1 = false, + .psp_id = 0x10220B00, + .psb_reserved_size = 0, + }, + [PLATFORM_RAVEN] = { + .name = "Raven", + .needs_ish = false, + .is_multi_level = false, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = false, + .has_dir_header_v1 = false, + .psp_id = 0xBC0A0000, + .psb_reserved_size = 0x100, + }, + [PLATFORM_PICASSO] = { + .name = "Picasso", + .needs_ish = false, + .is_multi_level = false, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = false, + .has_dir_header_v1 = false, + .psp_id = 0xBC0A0000, + .psb_reserved_size = 0x100, + }, + [PLATFORM_RENOIR] = { + .name = "Renoir", + .needs_ish = false, + .is_multi_level = true, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0C0000, + .psb_reserved_size = 0x200, + }, + [PLATFORM_LUCIENNE] = { + .name = "Lucienne", + .needs_ish = false, + .is_multi_level = true, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0C0000, + .psb_reserved_size = 0x200, + }, + [PLATFORM_CEZANNE] = { + .name = "Cezanne", + .needs_ish = false, + .is_multi_level = true, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = true, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0C0140, + .psb_reserved_size = 0x200, + }, + [PLATFORM_MENDOCINO] = { + .name = "Mendocino", + .needs_ish = true, + .is_multi_level = true, + .has_apob_nv_quirk = true, + .is_initial_alignment_required = false, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0D0900, + .psb_reserved_size = 0x200, + }, + [PLATFORM_PHOENIX] = { + .name = "Phoenix", + .needs_ish = true, + .is_multi_level = true, + .has_apob_nv_quirk = false, + .is_initial_alignment_required = false, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0D0400, + .psb_reserved_size = 0x200, + }, + [PLATFORM_STRIX] = { + .name = "Strix", + .needs_ish = true, + .is_multi_level = true, + .has_apob_nv_quirk = false, + .is_initial_alignment_required = false, + .is_second_gen = true, + .has_dir_header_v1 = true, + .psp_id = 0xBC0E0200, + .psb_reserved_size = 0x200, + }, + [PLATFORM_GENOA] = { + .name = "Genoa", + .needs_ish = false, + .is_multi_level = true, + .has_apob_nv_quirk = false, + .is_initial_alignment_required = true, + .is_second_gen = true, + .has_dir_header_v1 = false, + .psp_id = 0xBC0C0111, + .psb_reserved_size = 0x200, + }, + [PLATFORM_KRACKAN2E] = { + .name = "Krackan2e", + .needs_ish = true, + .is_multi_level = true, + .has_apob_nv_quirk = false, + .is_initial_alignment_required = false, + .is_second_gen = true, + .has_dir_header_v1 = true, + .psp_id = 0xbc0e1000, + .psb_reserved_size = 0x200, + }, + [PLATFORM_STRIXHALO] = { + .name = "Strixhalo", + .needs_ish = true, + .is_multi_level = true, + .has_apob_nv_quirk = false, + .is_initial_alignment_required = false, + .is_second_gen = true, + .has_dir_header_v1 = true, + .psp_id = 0xbc0e0900, + .psb_reserved_size = 0x200, + }, +}; + +/** + * Identify the platform based on SoC name string. + * + * @param soc_name: Case-insensitive SoC name string to match + * @return: Matching platform enum value, or PLATFORM_UNKNOWN if no match found + */ +enum platform platform_identify(char *soc_name) +{ + for (size_t i = 0; i < ARRAY_SIZE(platform_table); i++) { + if (!platform_table[i].name) /* PLATFORM_UNKNOWN has no entry */ + continue; + if (!strcasecmp(soc_name, platform_table[i].name)) + return i; + } + return PLATFORM_UNKNOWN; +} + +/** + * Check if the platform requires ISH (Image slot header) support. + * + * @param platform_type: Platform enum to check + * @return: true if ISH is needed, false otherwise + */ +bool platform_needs_ish(enum platform platform_type) +{ + return platform_table[platform_type].needs_ish; +} + +/** + * Check if the platform uses multi-level directory structure. + * Multi-level means there are separate PSP L1 and PSP L2 directory tables, + * as opposed to a flat structure with only one PSP directory. + * + * Combo directory tables do not count as multi-level since they are a different + * format and not supported. + * + * @param platform_type: Platform enum to check + * @return: true if multi-level directory is used, false for flat structure + */ +bool platform_is_multi_level(enum platform platform_type) +{ + return platform_table[platform_type].is_multi_level; +} + +/** + * Check if the platform has APOB NV (AMD PSP Output Block Non-Volatile) quirk. + * On older platforms that only had 16 MiB of ROM space or less, the address-mode was + * always physical and the PSP would do address translation internally by cutting off the upper bits. + * + * On newer platforms, the address-mode is always AMD_ADDR_REL_BIOS. + * + * @param platform_type: Platform enum to check + * @return: true if APOB NV quirk is present, false otherwise + */ +bool platform_has_apob_nv_quirk(enum platform platform_type) +{ + return platform_table[platform_type].has_apob_nv_quirk; +} + +/** + * Check if the platform requires initial alignment for firmware layout. + * + * @param platform_type: Platform enum to check + * @return: true if initial alignment is required, false otherwise + */ +bool platform_is_initial_alignment_required(enum platform platform_type) +{ + return platform_table[platform_type].is_initial_alignment_required; +} + +/** + * Check if the platform is second generation EFS structure. + * + * First generation platforms support at most 16MiB of flash. They typically + * use x86 MMIO addresses as the whole flash is mapped into the MMIO space. + * + * Second generation platforms support more than 16MiB of flash and thus the + * PSP searches every 16MiB page for an EFS that offset 0x24 BIT0 cleared. + * On those platforms, the address in the directory is a relative offset to + * the flash start. + * + * @param platform_type: Platform enum to check + * @return: true if second generation, false for first generation + */ +bool platform_is_second_gen(enum platform platform_type) +{ + return platform_table[platform_type].is_second_gen; +} + +/** + * Check if the platform uses PSP directory header version 1 format. + * If false it uses the PSP directory header version 0 and supports a maximum + * of 4 MiB directory size, while version 1 supports up to 64 MiB. + * + * @param platform_type: Platform enum to check + * @return: true if dir header v1 is used, false for other versions + */ +bool platform_has_dir_header_v1(enum platform platform_type) +{ + return platform_table[platform_type].has_dir_header_v1; +} + +/** + * Get the PSP (Platform Security Processor) ID for the platform. + * Older platforms might not insert a PSP ID in the directory, in which case + * this function returns 0. + * + * @param platform_type: Platform enum to query + * @return: 32-bit PSP ID value, or 0 if not applicable + */ +uint32_t platform_get_psp_id(enum platform platform_type) +{ + return platform_table[platform_type].psp_id; +} + +/** + * Returns true when legacy A/B recovery is enabled, which means that the PSP will look for + * PSP type 0x6e (PSP_AB_NVRAM) in the directory and treat it as A/B recovery data. + * + * @param cb_config: Configuration struct + * @return: true if legacy A/B recovery is enabled, false otherwise + */ +bool platform_has_legacy_ab_recovery(amd_cb_config *cb_config) +{ + return cb_config->soc_id == PLATFORM_RENOIR && cb_config->recovery_ab; +} + +/** + * Returns the maximum size of BIOS type 0x07 used for PSB. + * + * @param cb_config: Configuration struct + * @return: number of bytes to reserve for PSB, or 0 if PSB is unsupported + */ +bool platform_psb_reserved_size(enum platform platform_type) +{ + return platform_table[platform_type].psb_reserved_size; +} diff --git a/util/amdtool/cpu.c b/util/amdtool/cpu.c index abac90f4787..ae9400843c3 100644 --- a/util/amdtool/cpu.c +++ b/util/amdtool/cpu.c @@ -167,6 +167,20 @@ static bool is_sme_enabled(int cpunum) return !!(data.lo & (1 << 23)); } +static bool is_sme_hmk_enabled(int cpunum) +{ + msr_t data; + data = rdmsr_from_cpu(cpunum, 0xC0010010); + return !!(data.lo & (1 << 26)); +} + +static bool is_sev_snp_enabled(int cpunum) +{ + msr_t data; + data = rdmsr_from_cpu(cpunum, 0xC0010010); + return !!(data.lo & (1 << 24)); +} + #endif static int print_sme(void) @@ -189,9 +203,12 @@ static int print_sme(void) printf("------------- CPU %d ----------------\n", i); printf("SME supported : %s\n", sme_supported ? "YES" : "NO"); - if (sme_supported) + if (sme_supported) { printf("SME enabled : %s\n", is_sme_enabled(i) ? "YES" : "NO"); + printf("SME-HMK enabled : %s\n", + is_sme_hmk_enabled(i) ? "YES" : "NO"); + } } error = 0; } @@ -233,30 +250,6 @@ static bool is_sev_snp_supported(void) return !!(cpuid_regs.eax & 0x10); } -static bool is_sev_enabled(int cpunum) -{ - msr_t data; - - data = rdmsr_from_cpu(cpunum, 0xC0010131); - return !!(data.lo & 1); -} - -static bool is_sev_es_enabled(int cpunum) -{ - msr_t data; - - data = rdmsr_from_cpu(cpunum, 0xC0010131); - return !!(data.lo & 2); -} - -static bool is_sev_snp_enabled(int cpunum) -{ - msr_t data; - - data = rdmsr_from_cpu(cpunum, 0xC0010131); - return !!(data.lo & 4); -} - static unsigned int get_sev_max_guest_num(void) { cpuid_result_t cpuid_regs; @@ -279,7 +272,7 @@ static int print_sev(void) #ifndef __DARWIN__ int ncpus = get_number_of_cpus(); int i = 0; - bool sev_supported, sev_es_supported, sev_snp_supported; + bool sev_supported, sev_snp_supported; unsigned int max_guest, min_asid; printf("\n============= Dumping AMD SEV status =============\n"); @@ -293,7 +286,6 @@ static int print_sev(void) * in the scope of processor. */ sev_supported = is_sev_supported(); - sev_es_supported = is_sev_es_supported(); sev_snp_supported = is_sev_snp_supported(); if (sev_supported) { max_guest = get_sev_max_guest_num(); @@ -309,14 +301,9 @@ static int print_sev(void) max_guest); printf("Min SEV ASID : %u\n", min_asid); - printf("SEV enabled : %s\n", - is_sev_enabled(i) ? "YES" : "NO"); } printf("SEV-ES supported : %s\n", - sev_es_supported ? "YES" : "NO"); - if (sev_es_supported) - printf("SEV-ES enabled : %s\n", - is_sev_es_enabled(i) ? "YES" : "NO"); + is_sev_es_supported() ? "YES" : "NO"); printf("SEV-SNP supported : %s\n", sev_snp_supported ? "YES" : "NO"); if (sev_snp_supported) diff --git a/util/amdtools/ec_usb_pd_fw/Makefile b/util/amdtools/ec_usb_pd_fw/Makefile index 6049884a2f9..20f767765b0 100644 --- a/util/amdtools/ec_usb_pd_fw/Makefile +++ b/util/amdtools/ec_usb_pd_fw/Makefile @@ -13,6 +13,7 @@ HOSTCFLAGS ?= $(CFLAGS) HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3 HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/ HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include +HOSTCFLAGS += -include $(TOP)/src/commonlib/bsd/include/commonlib/bsd/compiler.h HOSTLDFLAGS ?= $(LDFLAGS) diff --git a/util/amdtools/ec_usb_pd_fw/Makefile.mk b/util/amdtools/ec_usb_pd_fw/Makefile.mk index 0905f8524d2..4a03f98d803 100644 --- a/util/amdtools/ec_usb_pd_fw/Makefile.mk +++ b/util/amdtools/ec_usb_pd_fw/Makefile.mk @@ -9,6 +9,7 @@ EC_USB_PD_FWCFLAGS += -Wno-array-bounds -Wextra -MMD -MP -O3 -Wshadow $(WERROR) EC_USB_PD_FWCFLAGS += -I $(top)/util/cbfstool/flashmap/ EC_USB_PD_FWCFLAGS += -I $(top)/util/amdtools/ec_usb_pd_fw EC_USB_PD_FWCFLAGS += -I $(top)/src/commonlib/bsd/include +EC_USB_PD_FWCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h additional-dirs += $(objutil)/ec_usb_pd_fw diff --git a/util/apl_ifwi/apl_ifwi.py b/util/apl_ifwi/apl_ifwi.py new file mode 100644 index 00000000000..3905d0de190 --- /dev/null +++ b/util/apl_ifwi/apl_ifwi.py @@ -0,0 +1,1072 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0-only + +"""Create an Apollo Lake/Gemini Lake IFWI image from build inputs.""" + +import argparse +import hashlib +import os +import re +import struct +import subprocess +import sys +import tempfile +import time +from pathlib import Path + + +KiB = 1024 +BPDT_SIGNATURE = 0x55AA +BPDT_HEADER_SIZE = 24 +BPDT_ENTRY_SIZE = 12 +CPD_HEADER_SIZE = 16 +CPD_ENTRY_SIZE = 24 +MN2_HEADER_SIZE = 0x284 +MN2_HEADER_DWORDS = MN2_HEADER_SIZE // 4 +MN2_SIGNATURE_OFFSET = 0x184 +RSA2048_SIZE = 256 +SHA256_SIZE = 32 + +IBB_SUBPARTITION_LENGTH = 0xa0000 +IBBP_OFFSET = 0x1000 +IBBL_OFFSET = 0x1000 +BPM_METADATA_OFFSET = 0x380 +OBBP_DATA_OFFSET = 0x1000 + +EXT_KEY_MANIFEST = 0x0e +EXT_SIGNED_PACKAGE_INFO = 0x0f +EXT_BOOT_POLICY_MANIFEST = 0x13 +EXT_SIZE = 0x68 +BPM_METADATA_SIZE = 0xb4 + +HASH_ALG_SHA256 = 2 +MODULE_TYPE_METADATA = 3 +MODULE_TYPE_SMIP = 2 +KEY_TYPE_OEM = 2 +OEM_KEY_ID = 1 +RSA_EXPONENT = 65537 + +# Usage bitmap for: +# IfwiManifest | OemSmipManifest | OemDnxIfwiManifest | BootPolicyManifest +OEM_KEY_USAGE_BITMAP = bytes.fromhex("00000000210102000000000000000000") + +# Usage bitmaps emitted by MEU for the APL/GLK BIOS and SMIP manifests. +IBBP_USAGE_BITMAP = bytes.fromhex("00000000010000000000000000000000") +SMIP_USAGE_BITMAP = bytes.fromhex("00000000000100000000000000000000") +SMIP_IAFW_OFFSET = 0x4f2 + + +BPDT_DLMP = 9 +BPDT_IFP_OVERRIDE = 10 +BPDT_S_BPDT = 5 +BPDT_RBEP = 1 +BPDT_UFS_PHY = 12 +BPDT_UFS_GPP = 13 +BPDT_FTPR = 2 +BPDT_UEP = 17 +BPDT_SMIP = 0 +BPDT_PMCP = 14 +BPDT_UCOD = 3 +BPDT_IBBP = 4 +BPDT_DEBUG_TOKENS = 11 +BPDT_NFTP = 7 +BPDT_OBBP = 6 + + +def align_up(value, align): + if value % align: + value += align - value % align + return value + + +def read_file(filename): + return Path(filename).read_bytes() + + +def run_openssl(*args, input_data=None): + cmd = ["openssl", *args] + result = subprocess.run(cmd, input=input_data, stdout=subprocess.PIPE, + stderr=subprocess.PIPE, check=False) + if result.returncode: + stderr = result.stderr.decode("utf-8", "replace").strip() + raise ValueError(f"openssl failed: {' '.join(cmd[:3])}: {stderr}") + return result.stdout + + +def rsa_key_material(private_key): + modulus = run_openssl("rsa", "-in", private_key, "-noout", "-modulus") + match = re.search(rb"Modulus=([0-9a-fA-F]+)", modulus) + if not match: + raise ValueError("unable to extract RSA modulus") + + modulus_be = bytes.fromhex(match.group(1).decode("ascii")) + if len(modulus_be) > RSA2048_SIZE and modulus_be[0] == 0: + modulus_be = modulus_be[1:] + if len(modulus_be) != RSA2048_SIZE: + raise ValueError("only RSA2048 IFWI signing keys are supported") + + text = run_openssl("rsa", "-in", private_key, "-noout", "-text") + match = re.search(rb"publicExponent:\s+([0-9]+)", text) + exponent = int(match.group(1)) if match else RSA_EXPONENT + if exponent != RSA_EXPONENT: + raise ValueError("only RSA exponent 65537 is supported") + + public_key = modulus_be[::-1] + exponent_bytes = exponent.to_bytes(4, "little") + public_hash = hashlib.sha256(public_key + exponent_bytes).digest() + return public_key, exponent_bytes, public_hash + + +def rsa_sign_sha256(private_key, data): + with tempfile.TemporaryDirectory() as tmpdir: + input_file = Path(tmpdir) / "sign-data.bin" + signature_file = Path(tmpdir) / "signature.bin" + input_file.write_bytes(data) + run_openssl("dgst", "-sha256", "-sign", private_key, "-out", + str(signature_file), str(input_file)) + signature = signature_file.read_bytes() + + if len(signature) != RSA2048_SIZE: + raise ValueError("unexpected RSA signature size") + return signature[::-1] + + +def mn2_date(): + source_date_epoch = os.environ.get("SOURCE_DATE_EPOCH") + if source_date_epoch: + date = time.strftime("%Y%m%d", time.gmtime(int(source_date_epoch))) + return int(date, 16) + return int(time.strftime("%Y%m%d", time.localtime()), 16) + + +def sign_mn2_manifest(manifest, private_key, public_key, exponent): + out = bytearray(manifest) + if len(out) < MN2_HEADER_SIZE: + raise ValueError("MN2 manifest is too small") + if out[0x1c:0x20] != b"$MN2": + raise ValueError("missing MN2 manifest header") + + header_size = struct.unpack_from(" len(out): + raise ValueError("MN2 manifest size exceeds buffer") + + out[0x78:0x7c] = struct.pack(" 14: + raise ValueError(f"RTD record name {name!r} is too long") + return (name.encode("ascii").ljust(14, b"\x00") + + struct.pack(" BPM_METADATA_SIZE: + raise ValueError("Boot Policy Manifest metadata is too large") + metadata += b"\x00" * (BPM_METADATA_SIZE - len(metadata)) + return bytes(metadata) + + +def signed_package_extension(partition_name, usage_bitmap, module_name, + module_type, metadata): + if len(partition_name) != 4: + raise ValueError("partition name must be four characters") + if len(usage_bitmap) != 16: + raise ValueError("usage bitmap must be 16 bytes") + + extension = bytearray() + extension += struct.pack("> 24) & 0xff) != 0xff + if entry_name == name: + if not valid: + raise ValueError(f"CSE FPT partition {name} is invalid") + return cse_image[entry_offset:entry_offset + length] + offset += 32 + + raise ValueError(f"CSE FPT partition {name} not found") + + +def parse_bios_partition(bios, name): + if bios[:4] != b"BIOS": + raise ValueError("BIOS manifest does not start with BIOS") + + count = struct.unpack_from("> 16) & 0x7fff + if base > limit: + return None + return base * 4 * KiB, (limit - base + 1) * 4 * KiB + + +def bpdt_header(count, fit_tool_version): + return struct.pack(" args.bp2_offset: + raise ValueError("BP1 overlaps BP2") + + if args.bp2_offset + len(bp2) > bios_end: + raise ValueError("BP2 exceeds BIOS region") + + out = bytearray(b"\xff" * args.flash_size) + out[:len(descriptor)] = descriptor + out[args.bp1_offset:args.bp1_offset + len(bp1)] = bp1 + out[args.bp2_offset:args.bp2_offset + len(bp2)] = bp2 + + if args.ec: + if ec_region is None: + raise ValueError("EC image supplied, but descriptor has no EC region") + ec_offset, ec_size = ec_region + ec = read_file(args.ec) + if len(ec) > ec_size: + raise ValueError("EC image exceeds EC region") + out[ec_offset:ec_offset + len(ec)] = ec + + Path(args.output).write_bytes(out) + + +def main(argv): + parser = argparse.ArgumentParser() + parser.add_argument("--output", required=True) + parser.add_argument("--flash-size", type=parse_int, default=8 * 1024 * 1024) + parser.add_argument("--bp1-offset", type=parse_int, default=0) + parser.add_argument("--bp2-offset", type=parse_int, required=True) + parser.add_argument("--debug-token-size", type=parse_int, default=0x2000) + parser.add_argument("--fit-tool-version", type=parse_int, default=0) + parser.add_argument("--descriptor", required=True) + parser.add_argument("--cse-image", required=True) + parser.add_argument("--ibbl", required=True) + parser.add_argument("--ibb", required=True) + parser.add_argument("--obb", required=True) + parser.add_argument("--private-key", required=True) + parser.add_argument("--pmcp", required=True) + parser.add_argument("--smip") + parser.add_argument("--smip-iafw") + parser.add_argument("--ifp-override") + parser.add_argument("--uep") + parser.add_argument("--uep-fpf-flags", type=parse_int, default=0xc880) + parser.add_argument("--uep-boot-policy", type=parse_int, default=0x11f) + parser.add_argument("--fitc-config") + parser.add_argument("--fitc-config-profile") + parser.add_argument("--microcode", action="append", required=True) + parser.add_argument("--ec") + args = parser.parse_args(argv) + + create_ifwi(args) + return 0 + + +if __name__ == "__main__": + try: + sys.exit(main(sys.argv[1:])) + except ValueError as err: + print(f"apl_ifwi.py: {err}", file=sys.stderr) + sys.exit(1) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 919c043d07a..79c6d0f2a7b 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -104,11 +104,11 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { pcieHotplugMap += "0 }" } - pchComment := "Intel Series " + pchComment := "Intel " if b.variant == "BD82X6X" { - pchComment += "6 Cougar Point PCH" + pchComment += "6 Series Cougar Point PCH" } else { - pchComment += "7 Panther Point PCH" + pchComment += "7 Series Panther Point PCH" } cur := DevTreeNode{ diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 267b64f6f55..03d73cee3a1 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -186,7 +186,7 @@ void mainboard_smi_sleep(u8 slp_typ) }, }, }, - Comment: "FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb", + Comment: "FIXME: has_thinklight, has_keyboard_backlight, has_power_management_beeps, has_uwb", Registers: map[string]string{ "config0": FormatHex8(ecs[0]), "config1": FormatHex8(ecs[1]), diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go index ffb955d2295..3a2c36f590e 100644 --- a/util/autoport/lynxpoint.go +++ b/util/autoport/lynxpoint.go @@ -183,7 +183,7 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { cur := DevTreeNode{ Chip: "southbridge/intel/lynxpoint", - Comment: "Intel Series 8 Lynx Point PCH", + Comment: "Intel 8 Series Lynx Point PCH", /* alt_gp_smi_en is not generated because coreboot doesn't use SMI like OEM firmware */ Registers: map[string]string{ @@ -251,7 +251,6 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { }) DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", - Comment: "global NVS and variables", }) DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/sleepstates.asl", diff --git a/util/autoport/readme.md b/util/autoport/readme.md index b755d436ff4..9d5d413e96d 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -374,10 +374,11 @@ improves. If you really care about CMOS options: ## EC (lenovo) -You need to set `has_keyboard_backlight` (backlit keyboard like X230), -`has_power_management_beeps` (optional beeps when e.g. plugging the cord -in) and `has_uwb` (third MiniPCIe slot) in accordance to functions available -on your machine +You need to set `has_thinklight` (keyboard light like T420), +`has_keyboard_backlight` (backlit keyboard like T440p), +`has_power_management_beeps` (optional beeps when e.g. plugging the cord in) +and `has_uwb` (third MiniPCIe slot) in accordance to functions available +on your machine. In rare cases autoport is unable to detect GPE. You can detect it from dmesg or ACPI tables. Look for line in dmesg like diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 5a33598c849..51c2a3efe51 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -16,7 +16,7 @@ VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) SPDX_ID_STRING := SPDX-License-Identifier .PHONY: all -all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger +all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger test cbfstool: $(objutil)/cbfstool/cbfstool @@ -36,7 +36,9 @@ cse_fpt: $(objutil)/cbfstool/cse_fpt cse_serger: $(objutil)/cbfstool/cse_serger -.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger +test: $(objutil)/cbfstool/test + +.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger test clean: $(RM) -f fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h $(RM) -f $(objutil)/cbfstool/cbfstool $(cbfsobj) @@ -48,6 +50,7 @@ clean: $(RM) -f $(objutil)/cbfstool/elogtool $(elogobj) $(RM) -f $(objutil)/cbfstool/cse_fpt $(cse_fpt_obj) $(RM) -f $(objutil)/cbfstool/cse_serger $(cse_serger_obj) + $(RM) -f $(objutil)/cbfstool/test $(test_obj) $(RM) -rf $(VBOOT_HOST_BUILD) linux_trampoline.c: linux_trampoline.S @@ -87,6 +90,7 @@ help: @echo " elogtool - Display ELOG events" @echo " cse_fpt - Manage Intel CSE Flash Partition Table (FPT)" @echo " cse_serger - Stitch Intel CSE components" + @echo " test - build tests" ifneq ($(V),1) .SILENT: diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk index d3f07f97773..88387364829 100644 --- a/util/cbfstool/Makefile.mk +++ b/util/cbfstool/Makefile.mk @@ -140,6 +140,12 @@ cse_serger_obj += common.o cse_serger_obj += cse_helpers.o cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var)) +test_obj := +test_obj += test.o +test_obj += fmap.o +test_obj += kv_pair.o +test_obj += valstr.o + TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -275,6 +281,10 @@ $(objutil)/cbfstool/cse_serger: $(addprefix $(objutil)/cbfstool/,$(cse_serger_ob printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cse_serger_obj)) +$(objutil)/cbfstool/test: $(addprefix $(objutil)/cbfstool/,$(test_obj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(test_obj)) + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c index 9b778cbc074..c858f45e771 100644 --- a/util/cbfstool/amdcompress.c +++ b/util/cbfstool/amdcompress.c @@ -17,6 +17,7 @@ #define DIR_UNDEF 0 #define DIR_COMP 1 #define DIR_UNCOMP 2 +#define DIR_COPY 3 typedef struct _header { uint32_t rsvd1[5]; @@ -32,6 +33,7 @@ static struct option long_options[] = { {"compress", no_argument, 0, 'c' }, {"maxsize", required_argument, 0, 'm' }, {"uncompress", no_argument, 0, 'u' }, + {"elfcopy", no_argument, 0, 'p' }, {"help", no_argument, 0, 'h' }, }; @@ -44,6 +46,7 @@ static void usage(void) printf("-i | --infile Input file\n"); printf("-o | --outfile Output file\n"); printf("-c | --compress Compress\n"); + printf("-p | --elfcopy Copy\n"); printf("-m | --maxsize Maximum uncompressed size (optional)\n"); printf(" * On compress: verify uncompressed size\n"); printf(" will be less than or equal maxsize\n"); @@ -133,7 +136,9 @@ static int iself(const void *input) * Those two functions can operate on streams and process chunks of data. */ -/* Build the required header and follow it with the compressed image. Detect +/* + * zlib compressed case: + * Build the required header and follow it with the compressed image. Detect * whether the input is an elf image, and if so, compress only the progbits. * * header @@ -151,7 +156,7 @@ static int iself(const void *input) * | ... | * n +------------------------------+ */ -static void do_compress(char *outf, char *inf, size_t max_size) +static void do_process(char *outf, char *inf, size_t max_size, bool do_compress) { int out_fd, in_fd; struct buffer inbf, outbf; @@ -198,6 +203,19 @@ static void do_compress(char *outf, char *inf, size_t max_size) goto out_free_in; } + if (!do_compress) { + /* + * When no zlib compression is being used there's also no 256 byte header. + * Simply copy the input to the output. + */ + err = 0; + if (write(out_fd, inbf.data, inbf.size) != (ssize_t)(inbf.size)) { + printf("\tError writing to %s\n", outf); + err = 1; + } + goto out_free_in; + } + outbf.size = inbf.size; /* todo: tbd worst case? */ outbf.size += sizeof(header); outbf.data = calloc(outbf.size, 1); @@ -344,6 +362,11 @@ int main(int argc, char *argv[]) usage(); direction = DIR_COMP; break; + case 'p': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_COPY; + break; case 'u': if (direction != DIR_UNDEF) usage(); @@ -360,7 +383,9 @@ int main(int argc, char *argv[]) usage(); if (direction == DIR_COMP) - do_compress(outf, inf, max_size); + do_process(outf, inf, max_size, true); + else if (direction == DIR_COPY) + do_process(outf, inf, max_size, false); else do_uncompress(outf, inf, max_size); diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 9a356e8b3fc..3788260eb54 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -248,6 +248,11 @@ int parse_fv_to_payload(const struct buffer *input, struct buffer *output, DEBUG("start: parse_fv_to_payload\n"); + if (input->size < sizeof(*fv)) { + INFO("Too small for a UEFI firmware volume.\n"); + return -1; + } + fv = (firmware_volume_header_t *)input->data; if (fv->signature != FV_SIGNATURE) { INFO("Not a UEFI firmware volume.\n"); @@ -368,6 +373,10 @@ int parse_fit_to_payload(const struct buffer *input, struct buffer *output, DEBUG("start: parse_fit_to_payload\n"); fdt_h = buffer_get(input); + if (buffer_size(input) < sizeof(*fdt_h)) { + INFO("Too small for a FIT payload.\n"); + return -1; + } if (read_be32(&fdt_h->magic) != FDT_HEADER_MAGIC) { INFO("Not a FIT payload.\n"); return -1; diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 33f154f3268..06f9af09e63 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -214,6 +214,11 @@ int parse_bzImage_to_payload(const struct buffer *input, if (bzp_add_cmdline(&bzp, cmdline) != 0) return -1; + if (input->size < sizeof(*hdr)) { + DEBUG("File too small.\n"); + return -1; + } + if (hdr->setup_sects != 0) { setup_size = (hdr->setup_sects + 1) * 512; } else { diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h index c3479bbfd29..ee43c284237 100644 --- a/util/cbfstool/cbfs_sections.h +++ b/util/cbfstool/cbfs_sections.h @@ -10,9 +10,9 @@ #define SECTION_NAME_FMAP "FMAP" #define SECTION_NAME_PRIMARY_CBFS "COREBOOT" -#define SECTION_NAME_TOPSWAP_CBFS "COREBOOT_TS" +#define SECTION_NAME_SECONDARY_CBFS "COREBOOT_B" #define SECTION_NAME_BOOTBLOCK "BOOTBLOCK" -#define SECTION_NAME_TOPSWAP "TOPSWAP" +#define SECTION_NAME_BOOTBLOCK_B "BOOTBLOCK_B" #define SECTION_ANNOTATION_CBFS "CBFS" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 68dbd32984d..d9c285d8e16 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -118,6 +118,15 @@ static struct param { .u64val = -1, }; +/* Indicates which CBFS is described by an mh_cache. Multiple firmware slots imply multiple + hash anchors, necessitating differentiating between them when caching. */ +enum mhc_kind { + MHC_NONE, /* The cache is uninitialized. */ + MHC_PRIMARY, /* Normal and always-present "COREBOOT" CBFS (separate or embedded + bootblock). */ + MHC_SECONDARY /* Top Swap CBFS called "COREBOOT_B" with bootblock in "BOOTBLOCK_B". */ +}; + /* * This "metadata_hash cache" caches the value and location of the CBFS metadata * hash embedded in the bootblock when CBFS verification is enabled. The first @@ -132,37 +141,49 @@ struct mh_cache { size_t offset; struct vb2_hash cbfs_hash; platform_fixup_func fixup; - bool initialized; + enum mhc_kind kind; }; static bool is_main_cbfs_region(const char *region_name) { return strcmp(region_name, SECTION_NAME_PRIMARY_CBFS) == 0 || - strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS) == 0; + strcmp(region_name, SECTION_NAME_SECONDARY_CBFS) == 0; } -static bool is_topswap_region(const char *region_name) +static enum mhc_kind derive_mhc_kind(const char *region_name) { - return strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS) == 0 || - strcmp(region_name, SECTION_NAME_TOPSWAP) == 0; + /* Only these two regions are specific to Top Swap. */ + if (strcmp(region_name, SECTION_NAME_SECONDARY_CBFS) == 0 || + strcmp(region_name, SECTION_NAME_BOOTBLOCK_B) == 0) + return MHC_SECONDARY; + + return MHC_PRIMARY; } static struct mh_cache *get_mh_cache(void) { static struct mh_cache mhc; - if (mhc.initialized) + /* + * A single invocation of cbfstool can process regions that use different CBFS metadata. + * Right now, the only such case is when Top Swap redundancy is in use. Check for Top + * Swap region to decide if the cache can be reused. + * + * This implicitly checks whether the cache is initialized. + */ + const enum mhc_kind kind = derive_mhc_kind(param.region_name); + if (mhc.kind == kind) return &mhc; - mhc.initialized = true; + mhc.kind = kind; const struct fmap *fmap = partitioned_file_get_fmap(param.image_file); if (!fmap) goto no_metadata_hash; const char *bootblock_region = SECTION_NAME_BOOTBLOCK; - if (is_topswap_region(param.region_name)) - bootblock_region = SECTION_NAME_TOPSWAP; + if (kind == MHC_SECONDARY) + bootblock_region = SECTION_NAME_BOOTBLOCK_B; /* Find the metadata_hash container. If there is a "BOOTBLOCK" FMAP section, it's there. If not, it's a normal file in the primary CBFS section. */ @@ -175,6 +196,12 @@ static struct mh_cache *get_mh_cache(void) offset = 0; size = buffer.size; } else { + if (kind != MHC_PRIMARY) { + /* Top Swap requires BOOTBLOCK_B region. */ + ERROR("Malformed image: '%s' region is missing\n", bootblock_region); + goto no_metadata_hash; + } + struct cbfs_image cbfs; struct cbfs_file *mh_container; if (!partitioned_file_read_region(&buffer, param.image_file, SECTION_NAME_PRIMARY_CBFS)) @@ -282,7 +309,7 @@ static int maybe_update_metadata_hash(struct cbfs_image *cbfs) static int maybe_update_fmap_hash(void) { if (strcmp(param.region_name, SECTION_NAME_BOOTBLOCK) && - strcmp(param.region_name, SECTION_NAME_TOPSWAP) && + strcmp(param.region_name, SECTION_NAME_BOOTBLOCK_B) && strcmp(param.region_name, SECTION_NAME_FMAP) && param.type != CBFS_TYPE_BOOTBLOCK && param.type != CBFS_TYPE_AMDFW) @@ -2379,10 +2406,6 @@ int main(int argc, char **argv) strcpy(region_name_scratch, param.region_name); param.region_name = strtok(region_name_scratch, ","); for (unsigned region = 0; region < num_regions; ++region) { - // Reset metadata cache in case region uses anchor from a different - // location. - get_mh_cache()->initialized = false; - if (!param.region_name) { ERROR("Encountered illegal degenerate region name in -r list\n"); ERROR("The image will be left unmodified.\n"); @@ -2390,7 +2413,8 @@ int main(int argc, char **argv) return 1; } - if (is_main_cbfs_region(param.region_name)) + // "COREBOOT" CBFS region is a mandatory one. + if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS) == 0) seen_primary_cbfs = true; param.image_region = image_regions + region; diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index d5eb87ca25c..6d003b190ef 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -46,6 +46,18 @@ int buffer_create(struct buffer *buffer, size_t size, const char *name) int buffer_from_file_aligned_size(struct buffer *buffer, const char *filename, size_t size_granularity) { + struct stat st; + + if (stat(filename, &st) == -1) { + perror(filename); + return -1; + } + + if (!S_ISREG(st.st_mode)) { + fprintf(stderr, "%s is not a regular file\n", filename); + return -1; + } + FILE *fp = fopen(filename, "rb"); if (!fp) { perror(filename); diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd deleted file mode 100644 index d0e17b194e4..00000000000 --- a/util/cbfstool/default-x86.fmd +++ /dev/null @@ -1,21 +0,0 @@ -# layout for firmware residing at top of 4GB address space -# +-------------+ <-- 4GB - FLASH_SIZE / start of flash -# | unspecified | -# +-------------+ <-- 4GB - BIOS_SIZE -# | FMAP | -# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE -# | CBFS | -# +-------------+ <-- 4GB / end of flash - -FLASH ##FLASH_SIZE## { - BIOS@##BIOS_BASE## ##BIOS_SIZE## { - ##CONSOLE_ENTRY## - ##MRC_CACHE_ENTRY## - ##SMMSTORE_ENTRY## - ##SPD_CACHE_ENTRY## - ##VPD_ENTRY## - ##HSPHY_FW_ENTRY## - FMAP@##FMAP_BASE## ##FMAP_SIZE## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## - } -} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd deleted file mode 100644 index 97cf441445c..00000000000 --- a/util/cbfstool/default.fmd +++ /dev/null @@ -1,20 +0,0 @@ -# layout for firmware when flash address space matches used address layout -# +-------------+ <-- 0 -# | unspecified | -# +-------------+ <-- BIOS_BASE -# | bootblock | -# +-------------+ <-- BIOS_BASE + 128K -# | FMAP | -# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE -# | CBFS | -# +-------------+ <-- FLASH_SIZE - -FLASH ##FLASH_SIZE## { - BIOS@##BIOS_BASE## ##BIOS_SIZE## { - BOOTBLOCK 128K - FMAP@##FMAP_BASE## ##FMAP_SIZE## - ##CONSOLE_ENTRY## - ##MRC_CACHE_ENTRY## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## - } -} diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index 5bcac15e4ad..603948c1dad 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -493,6 +493,11 @@ int parse_elf(const struct buffer *pinput, struct parsed_elf *pelf, int flags) /* Zero out the parsed elf structure. */ memset(pelf, 0, sizeof(*pelf)); + if (buffer_size(pinput) < sizeof(*ehdr)) { + DEBUG("The stage file is too short!\n"); + return -1; + } + if (!iself(buffer_get(pinput))) { DEBUG("The stage file is not in ELF format!\n"); return -1; diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index e8064911b67..5c12dd5c5cd 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -326,325 +326,3 @@ const struct fmap_area *fmap_find_area(const struct fmap *fmap, return area; } - -/* - * LCOV_EXCL_START - * Unit testing stuff done here so we do not need to expose static functions. - */ -static enum test_status { pass = EXIT_SUCCESS, fail = EXIT_FAILURE } status; -static struct fmap *fmap_create_test(void) -{ - struct fmap *fmap; - uint64_t base = 0; - uint32_t size = 0x100000; - char name[] = "test_fmap"; - - status = fail; - - fmap = fmap_create(base, size, (uint8_t *)name); - if (!fmap) - return NULL; - - if (memcmp(&fmap->signature, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE))) { - printf("FAILURE: signature is incorrect\n"); - goto fmap_create_test_exit; - } - - if ((fmap->ver_major != FMAP_VER_MAJOR) || - (fmap->ver_minor != FMAP_VER_MINOR)) { - printf("FAILURE: version is incorrect\n"); - goto fmap_create_test_exit; - } - - if (le64toh(fmap->base) != base) { - printf("FAILURE: base is incorrect\n"); - goto fmap_create_test_exit; - } - - if (le32toh(fmap->size) != 0x100000) { - printf("FAILURE: size is incorrect\n"); - goto fmap_create_test_exit; - } - - if (strcmp((char *)fmap->name, "test_fmap")) { - printf("FAILURE: name is incorrect\n"); - goto fmap_create_test_exit; - } - - if (le16toh(fmap->nareas) != 0) { - printf("FAILURE: number of areas is incorrect\n"); - goto fmap_create_test_exit; - } - - status = pass; -fmap_create_test_exit: - /* preserve fmap if all went well */ - if (status == fail) { - fmap_destroy(fmap); - fmap = NULL; - } - return fmap; -} - -static int fmap_print_test(struct fmap *fmap) -{ - return fmap_print(fmap); -} - -static int fmap_size_test(void) -{ - status = fail; - - if (fmap_size(NULL) >= 0) { - printf("FAILURE: failed to abort on NULL pointer input\n"); - goto fmap_size_test_exit; - } - - status = pass; -fmap_size_test_exit: - return status; -} - -/* this test re-allocates the fmap, so it gets a double-pointer */ -static int fmap_append_area_test(struct fmap **fmap) -{ - int total_size; - uint16_t nareas_orig; - /* test_area will be used by fmap_csum_test and find_area_test */ - struct fmap_area test_area = { - .offset = htole32(0x400), - .size = htole32(0x10000), - .name = "test_area_1", - .flags = htole16(FMAP_AREA_STATIC), - }; - - status = fail; - - if ((fmap_append_area(NULL, 0, 0, test_area.name, 0) >= 0) || - (fmap_append_area(fmap, 0, 0, NULL, 0) >= 0)) { - printf("FAILURE: failed to abort on NULL pointer input\n"); - goto fmap_append_area_test_exit; - } - - nareas_orig = le16toh((*fmap)->nareas); - (*fmap)->nareas = htole16(~(0)); - if (fmap_append_area(fmap, 0, 0, (const uint8_t *)"foo", 0) >= 0) { - printf("FAILURE: failed to abort with too many areas\n"); - goto fmap_append_area_test_exit; - } - (*fmap)->nareas = htole16(nareas_orig); - - total_size = sizeof(**fmap) + sizeof(test_area); - if (fmap_append_area(fmap, - le32toh(test_area.offset), - le32toh(test_area.size), - test_area.name, - le16toh(test_area.flags) - ) != total_size) { - printf("failed to append area\n"); - goto fmap_append_area_test_exit; - } - - if (le16toh((*fmap)->nareas) != 1) { - printf("FAILURE: failed to increment number of areas\n"); - goto fmap_append_area_test_exit; - } - - status = pass; -fmap_append_area_test_exit: - return status; -} - -static int fmap_find_area_test(struct fmap *fmap) -{ - status = fail; - char area_name[] = "test_area_1"; - - if (fmap_find_area(NULL, area_name) || - fmap_find_area(fmap, NULL)) { - printf("FAILURE: failed to abort on NULL pointer input\n"); - goto fmap_find_area_test_exit; - } - - if (fmap_find_area(fmap, area_name) == NULL) { - printf("FAILURE: failed to find \"%s\"\n", area_name); - goto fmap_find_area_test_exit; - } - - status = pass; -fmap_find_area_test_exit: - return status; -} - -static int fmap_flags_to_string_test(void) -{ - char *str = NULL; - char *my_str = NULL; - unsigned int i; - uint16_t flags; - - status = fail; - - /* no area flag */ - str = fmap_flags_to_string(0); - if (!str || strcmp(str, "")) { - printf("FAILURE: failed to return empty string when no flag" - "are set"); - goto fmap_flags_to_string_test_exit; - } - free(str); - - /* single area flags */ - for (i = 0; i < ARRAY_SIZE(flag_lut); i++) { - if (!flag_lut[i].str) - continue; - - if ((str = fmap_flags_to_string(flag_lut[i].val)) == NULL) { - printf("FAILURE: failed to translate flag to string"); - goto fmap_flags_to_string_test_exit; - } - free(str); - } - - /* construct our own flags field and string using all available flags - * and compare output with fmap_flags_to_string() */ - my_str = calloc(256, 1); - flags = 0; - for (i = 0; i < ARRAY_SIZE(flag_lut); i++) { - if (!flag_lut[i].str) - continue; - else if (i > 0) - strcat(my_str, ","); - - flags |= flag_lut[i].val; - strcat(my_str, flag_lut[i].str); - } - - str = fmap_flags_to_string(flags); - if (strcmp(str, my_str)) { - printf("FAILURE: bad result from fmap_flags_to_string\n"); - goto fmap_flags_to_string_test_exit; - } - - status = pass; -fmap_flags_to_string_test_exit: - free(str); - free(my_str); - return status; - -} - -static int fmap_find_test(struct fmap *fmap) -{ - uint8_t *buf; - size_t total_size, offset; - - status = fail; - - /* - * Note: In these tests, we'll use fmap_find() and control usage of - * lsearch and bsearch by using a power-of-2 total_size. For lsearch, - * use total_size - 1. For bsearch, use total_size. - */ - - total_size = 0x100000; - buf = calloc(total_size, 1); - - /* test if image length is zero */ - if (fmap_find(buf, 0) >= 0) { - printf("FAILURE: failed to abort on zero-length image\n"); - goto fmap_find_test_exit; - } - - /* test if no fmap exists */ - if (fmap_find(buf, total_size - 1) >= 0) { - printf("FAILURE: lsearch returned false positive\n"); - goto fmap_find_test_exit; - } - if (fmap_find(buf, total_size) >= 0) { - printf("FAILURE: bsearch returned false positive\n"); - goto fmap_find_test_exit; - } - - /* simple test case: fmap at (total_size / 2) + 1 */ - offset = (total_size / 2) + 1; - memcpy(&buf[offset], fmap, fmap_size(fmap)); - - if ((unsigned)fmap_find(buf, total_size - 1) != offset) { - printf("FAILURE: lsearch failed to find fmap\n"); - goto fmap_find_test_exit; - } - if ((unsigned)fmap_find(buf, total_size) != offset) { - printf("FAILURE: bsearch failed to find fmap\n"); - goto fmap_find_test_exit; - } - - /* test bsearch if offset is at 0 */ - offset = 0; - memset(buf, 0, total_size); - memcpy(buf, fmap, fmap_size(fmap)); - if ((unsigned)fmap_find(buf, total_size) != offset) { - printf("FAILURE: bsearch failed to find fmap at offset 0\n"); - goto fmap_find_test_exit; - } - - /* test overrun detection */ - memset(buf, 0, total_size); - memcpy(&buf[total_size - fmap_size(fmap) + 1], - fmap, - fmap_size(fmap) + 1); - if (fmap_find(buf, total_size - 1) >= 0) { - printf("FAILURE: lsearch failed to catch overrun\n"); - goto fmap_find_test_exit; - } - if (fmap_find(buf, total_size) >= 0) { - printf("FAILURE: bsearch failed to catch overrun\n"); - goto fmap_find_test_exit; - } - - status = pass; -fmap_find_test_exit: - free(buf); - return status; -} - -int fmap_test(void) -{ - int rc = EXIT_SUCCESS; - struct fmap *my_fmap; - - /* - * This test has two parts: Creation of an fmap with one or more - * area(s), and other stuff. Since a valid fmap is required to run - * many tests, we abort if fmap creation fails in any way. - * - * Also, fmap_csum_test() makes some assumptions based on the areas - * appended. See fmap_append_area_test() for details. - */ - if ((my_fmap = fmap_create_test()) == NULL) { - rc = EXIT_FAILURE; - goto fmap_test_exit; - } - - if (fmap_find_test(my_fmap)) { - rc = EXIT_FAILURE; - goto fmap_test_exit; - } - - if (fmap_append_area_test(&my_fmap)) { - rc = EXIT_FAILURE; - goto fmap_test_exit; - } - - rc |= fmap_find_area_test(my_fmap); - rc |= fmap_size_test(); - rc |= fmap_flags_to_string_test(); - rc |= fmap_print_test(my_fmap); - -fmap_test_exit: - fmap_destroy(my_fmap); - if (rc) - printf("FAILED\n"); - return rc; -} -/* LCOV_EXCL_STOP */ diff --git a/util/cbfstool/flashmap_tests.c b/util/cbfstool/flashmap_tests.c deleted file mode 100644 index 0ed3fc936ed..00000000000 --- a/util/cbfstool/flashmap_tests.c +++ /dev/null @@ -1,21 +0,0 @@ -/* fmap_from_fmd.c, simple launcher for fmap library unit test suite */ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "flashmap/fmap.h" - -#include - -int main(void) -{ - int result = fmap_test(); - - puts(""); - puts("==="); - puts(""); - if (!result) - puts("RESULT: All unit tests PASSED."); - else - puts("RESULT: One or more tests FAILED!"); - - return result; -} diff --git a/util/cbfstool/fmd_parser.c_shipped b/util/cbfstool/fmd_parser.c_shipped index 56e33b38966..5a002172e2d 100644 --- a/util/cbfstool/fmd_parser.c_shipped +++ b/util/cbfstool/fmd_parser.c_shipped @@ -75,6 +75,9 @@ struct flashmap_descriptor *res = NULL; +extern int yylineno; +extern char *lineptr; + # ifndef YY_CAST # ifdef __cplusplus @@ -515,9 +518,9 @@ static const yytype_int8 yytranslate[] = /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int8 yyrline[] = { - 0, 68, 68, 74, 88, 95, 96, 97, 97, 98, - 99, 100, 101, 102, 103, 104, 105, 107, 111, 112, - 113, 124 + 0, 71, 71, 77, 91, 98, 99, 100, 100, 101, + 102, 103, 104, 105, 106, 107, 108, 110, 114, 115, + 116, 127 }; #endif @@ -1435,7 +1438,9 @@ struct flashmap_descriptor *parse_descriptor( return region; } + void yyerror(const char *s) { - fprintf(stderr, "%s\n", s); + fprintf(stderr, "error: %s in line %d:\n", s, yylineno); + fprintf(stderr, "> %s\n", lineptr); } diff --git a/util/cbfstool/fmd_parser.y b/util/cbfstool/fmd_parser.y index a29c9d64ac3..939530af15e 100644 --- a/util/cbfstool/fmd_parser.y +++ b/util/cbfstool/fmd_parser.y @@ -8,6 +8,9 @@ #include struct flashmap_descriptor *res = NULL; + +extern int yylineno; +extern char *lineptr; %} %union { @@ -176,5 +179,6 @@ struct flashmap_descriptor *parse_descriptor( void yyerror(const char *s) { - fprintf(stderr, "%s\n", s); + fprintf(stderr, "error: %s in line %d:\n", s, yylineno); + fprintf(stderr, "> %s\n", lineptr); } diff --git a/util/cbfstool/fmd_scanner.c_shipped b/util/cbfstool/fmd_scanner.c_shipped index 105791be876..6af5a961a81 100644 --- a/util/cbfstool/fmd_scanner.c_shipped +++ b/util/cbfstool/fmd_scanner.c_shipped @@ -159,10 +159,27 @@ extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 - - #define YY_LESS_LINENO(n) - #define YY_LINENO_REWIND_TO(ptr) - + /* Note: We specifically omit the test for yy_rule_can_match_eol because it requires + * access to the local variable yy_act. Since yyless() is a macro, it would break + * existing scanners that call yyless() from OUTSIDE yylex. + * One obvious solution it to make yy_act a global. I tried that, and saw + * a 5% performance hit in a non-yylineno scanner, because yy_act is + * normally declared as a register variable-- so it is not worth it. + */ + #define YY_LESS_LINENO(n) \ + do { \ + int yyl;\ + for ( yyl = n; yyl < yyleng; ++yyl )\ + if ( yytext[yyl] == '\n' )\ + --yylineno;\ + }while(0) + #define YY_LINENO_REWIND_TO(dst) \ + do {\ + const char *p;\ + for ( p = yy_cp-1; p >= (dst); --p)\ + if ( *p == '\n' )\ + --yylineno;\ + }while(0) /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ @@ -451,6 +468,11 @@ static const flex_int16_t yy_chk[85] = 39, 39, 39, 39 } ; +/* Table of booleans, true if rule could match eol. */ +static const flex_int32_t yy_rule_can_match_eol[14] = + { 0, +1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + static yy_state_type yy_last_accepting_state; static char *yy_last_accepting_cpos; @@ -475,6 +497,28 @@ char *yytext; int parse_integer(char *src, int base); int copy_string(const char *src); +char *lineptr = NULL; +size_t linebuffer_len = 0; +ssize_t consumed = 0; +ssize_t available = 0; + +size_t min(size_t a, size_t b); +#define YY_INPUT(buf,result,max_size) { \ + if(available <= 0) { \ + consumed = 0; \ + available = getline(&lineptr, &linebuffer_len, yyin); \ + if (available < 0) { \ + if (ferror(yyin)) { perror("read error:"); } \ + available = 0; \ + } \ + } \ + result = min(available, max_size); \ + strncpy(buf, lineptr + consumed, result); \ + consumed += result; \ + available -= result; \ + } +#define YY_NO_INPUT 1 + #define INITIAL 0 #define FLAGS 1 @@ -736,6 +780,15 @@ yy_find_action: YY_DO_BEFORE_ACTION; + if ( yy_act != YY_END_OF_BUFFER && yy_rule_can_match_eol[yy_act] ) + { + int yyl; + for ( yyl = 0; yyl < yyleng; ++yyl ) + if ( yytext[yyl] == '\n' ) + yylineno++; +; + } + do_action: /* This label is used only to access EOF actions. */ switch ( yy_act ) @@ -1168,6 +1221,10 @@ static int yy_get_next_buffer (void) *--yy_cp = (char) c; + if ( c == '\n' ){ + --yylineno; + } + (yytext_ptr) = yy_bp; (yy_hold_char) = *yy_cp; (yy_c_buf_p) = yy_cp; @@ -1245,6 +1302,10 @@ static int yy_get_next_buffer (void) *(yy_c_buf_p) = '\0'; /* preserve yytext */ (yy_hold_char) = *++(yy_c_buf_p); + if ( c == '\n' ) + yylineno++; +; + return c; } #endif /* ifndef YY_NO_INPUT */ @@ -1711,6 +1772,8 @@ static int yy_init_globals (void) * This function is called from yylex_destroy(), so don't allocate here. */ + /* We do not touch yylineno unless the option is enabled. */ + yylineno = 1; (yy_buffer_stack) = NULL; (yy_buffer_stack_top) = 0; (yy_buffer_stack_max) = 0; @@ -1838,3 +1901,7 @@ int copy_string(const char *src) return STRING; } +size_t min(size_t a, size_t b) { + return b < a ? b : a; +} + diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index 9d05c80d263..63cff6d0dd9 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -9,9 +9,30 @@ int parse_integer(char *src, int base); int copy_string(const char *src); + +char *lineptr = NULL; +size_t linebuffer_len = 0; +ssize_t consumed = 0; +ssize_t available = 0; + +size_t min(size_t a, size_t b); +#define YY_INPUT(buf,result,max_size) { \ + if(available <= 0) { \ + consumed = 0; \ + available = getline(&lineptr, &linebuffer_len, yyin); \ + if (available < 0) { \ + if (ferror(yyin)) { perror("read error:"); } \ + available = 0; \ + } \ + } \ + result = min(available, max_size); \ + strncpy(buf, lineptr + consumed, result); \ + consumed += result; \ + available -= result; \ + } %} -%option noyywrap +%option noyywrap yylineno noinput %s FLAGS MULTIPLIER [KMG] @@ -64,3 +85,7 @@ int copy_string(const char *src) yylval.strval = strdup(src); return STRING; } + +size_t min(size_t a, size_t b) { + return b < a ? b : a; +} diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c index 97fdd2e15b9..c440cc1df63 100644 --- a/util/cbfstool/platform_fixups.c +++ b/util/cbfstool/platform_fixups.c @@ -313,13 +313,13 @@ platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, const char *region_name) { if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK) || - !strcmp(region_name, SECTION_NAME_TOPSWAP)) { + !strcmp(region_name, SECTION_NAME_BOOTBLOCK_B)) { if (qualcomm_probe(buffer, offset)) return qualcomm_fixup; else if (mediatek_probe(buffer)) return mediatek_fixup; } else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS) || - !strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS)) { + !strcmp(region_name, SECTION_NAME_SECONDARY_CBFS)) { /* TODO: add fixups for primary CBFS bootblock platforms, if needed */ } else { ERROR("%s called for unexpected FMAP region %s!\n", __func__, region_name); diff --git a/util/cbfstool/test.c b/util/cbfstool/test.c new file mode 100644 index 00000000000..2426e3e7b18 --- /dev/null +++ b/util/cbfstool/test.c @@ -0,0 +1,342 @@ +/* fmap_from_fmd.c, simple launcher for fmap library unit test suite */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "flashmap/fmap.h" + +#include +#include +#include +#include + +static enum test_status { pass = EXIT_SUCCESS, fail = EXIT_FAILURE } status; + +static struct fmap *fmap_create_test(void) +{ + struct fmap *fmap; + uint64_t base = 0; + uint32_t size = 0x100000; + char name[] = "test_fmap"; + + status = fail; + + fmap = fmap_create(base, size, (uint8_t *)name); + if (!fmap) + return NULL; + + if (memcmp(&fmap->signature, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE))) { + printf("FAILURE: signature is incorrect\n"); + goto fmap_create_test_exit; + } + + if ((fmap->ver_major != FMAP_VER_MAJOR) || + (fmap->ver_minor != FMAP_VER_MINOR)) { + printf("FAILURE: version is incorrect\n"); + goto fmap_create_test_exit; + } + + if (le64toh(fmap->base) != base) { + printf("FAILURE: base is incorrect\n"); + goto fmap_create_test_exit; + } + + if (le32toh(fmap->size) != 0x100000) { + printf("FAILURE: size is incorrect\n"); + goto fmap_create_test_exit; + } + + if (strcmp((char *)fmap->name, "test_fmap")) { + printf("FAILURE: name is incorrect\n"); + goto fmap_create_test_exit; + } + + if (le16toh(fmap->nareas) != 0) { + printf("FAILURE: number of areas is incorrect\n"); + goto fmap_create_test_exit; + } + + status = pass; +fmap_create_test_exit: + /* preserve fmap if all went well */ + if (status == fail) { + fmap_destroy(fmap); + fmap = NULL; + } + return fmap; +} + +static int fmap_print_test(struct fmap *fmap) +{ + return fmap_print(fmap); +} + +static int fmap_size_test(void) +{ + status = fail; + + if (fmap_size(NULL) >= 0) { + printf("FAILURE: failed to abort on NULL pointer input\n"); + goto fmap_size_test_exit; + } + + status = pass; +fmap_size_test_exit: + return status; +} + +/* this test re-allocates the fmap, so it gets a double-pointer */ +static int fmap_append_area_test(struct fmap **fmap) +{ + int total_size; + uint16_t nareas_orig; + /* test_area will be used by fmap_csum_test and find_area_test */ + struct fmap_area test_area = { + .offset = htole32(0x400), + .size = htole32(0x10000), + .name = "test_area_1", + .flags = htole16(FMAP_AREA_STATIC), + }; + + status = fail; + + if ((fmap_append_area(NULL, 0, 0, test_area.name, 0) >= 0) || + (fmap_append_area(fmap, 0, 0, NULL, 0) >= 0)) { + printf("FAILURE: failed to abort on NULL pointer input\n"); + goto fmap_append_area_test_exit; + } + + nareas_orig = le16toh((*fmap)->nareas); + (*fmap)->nareas = htole16(~(0)); + if (fmap_append_area(fmap, 0, 0, (const uint8_t *)"foo", 0) >= 0) { + printf("FAILURE: failed to abort with too many areas\n"); + goto fmap_append_area_test_exit; + } + (*fmap)->nareas = htole16(nareas_orig); + + total_size = sizeof(**fmap) + sizeof(test_area); + if (fmap_append_area(fmap, + le32toh(test_area.offset), + le32toh(test_area.size), + test_area.name, + le16toh(test_area.flags) + ) != total_size) { + printf("failed to append area\n"); + goto fmap_append_area_test_exit; + } + + if (le16toh((*fmap)->nareas) != 1) { + printf("FAILURE: failed to increment number of areas\n"); + goto fmap_append_area_test_exit; + } + + status = pass; +fmap_append_area_test_exit: + return status; +} + +static int fmap_find_area_test(struct fmap *fmap) +{ + status = fail; + char area_name[] = "test_area_1"; + + if (fmap_find_area(NULL, area_name) || + fmap_find_area(fmap, NULL)) { + printf("FAILURE: failed to abort on NULL pointer input\n"); + goto fmap_find_area_test_exit; + } + + if (fmap_find_area(fmap, area_name) == NULL) { + printf("FAILURE: failed to find \"%s\"\n", area_name); + goto fmap_find_area_test_exit; + } + + status = pass; +fmap_find_area_test_exit: + return status; +} + +static int fmap_flags_to_string_test(void) +{ + char *str = NULL; + char *my_str = NULL; + unsigned int i; + uint16_t flags; + + status = fail; + + /* no area flag */ + str = fmap_flags_to_string(0); + if (!str || strcmp(str, "")) { + printf("FAILURE: failed to return empty string when no flag" + "are set"); + goto fmap_flags_to_string_test_exit; + } + free(str); + + /* single area flags */ + for (i = 0; i < ARRAY_SIZE(flag_lut); i++) { + if (!flag_lut[i].str) + continue; + + if ((str = fmap_flags_to_string(flag_lut[i].val)) == NULL) { + printf("FAILURE: failed to translate flag to string"); + goto fmap_flags_to_string_test_exit; + } + free(str); + } + + /* construct our own flags field and string using all available flags + * and compare output with fmap_flags_to_string() */ + my_str = calloc(256, 1); + flags = 0; + for (i = 0; i < ARRAY_SIZE(flag_lut); i++) { + if (!flag_lut[i].str) + continue; + else if (i > 0) + strcat(my_str, ","); + + flags |= flag_lut[i].val; + strcat(my_str, flag_lut[i].str); + } + + str = fmap_flags_to_string(flags); + if (strcmp(str, my_str)) { + printf("FAILURE: bad result from fmap_flags_to_string\n"); + goto fmap_flags_to_string_test_exit; + } + + status = pass; +fmap_flags_to_string_test_exit: + free(str); + free(my_str); + return status; + +} + +static int fmap_find_test(struct fmap *fmap) +{ + uint8_t *buf; + size_t total_size, offset; + + status = fail; + + /* + * Note: In these tests, we'll use fmap_find() and control usage of + * lsearch and bsearch by using a power-of-2 total_size. For lsearch, + * use total_size - 1. For bsearch, use total_size. + */ + + total_size = 0x100000; + buf = calloc(total_size, 1); + + /* test if image length is zero */ + if (fmap_find(buf, 0) >= 0) { + printf("FAILURE: failed to abort on zero-length image\n"); + goto fmap_find_test_exit; + } + + /* test if no fmap exists */ + if (fmap_find(buf, total_size - 1) >= 0) { + printf("FAILURE: lsearch returned false positive\n"); + goto fmap_find_test_exit; + } + if (fmap_find(buf, total_size) >= 0) { + printf("FAILURE: bsearch returned false positive\n"); + goto fmap_find_test_exit; + } + + /* simple test case: fmap at (total_size / 2) + 1 */ + offset = (total_size / 2) + 1; + memcpy(&buf[offset], fmap, fmap_size(fmap)); + + if ((unsigned)fmap_find(buf, total_size - 1) != offset) { + printf("FAILURE: lsearch failed to find fmap\n"); + goto fmap_find_test_exit; + } + if ((unsigned)fmap_find(buf, total_size) != offset) { + printf("FAILURE: bsearch failed to find fmap\n"); + goto fmap_find_test_exit; + } + + /* test bsearch if offset is at 0 */ + offset = 0; + memset(buf, 0, total_size); + memcpy(buf, fmap, fmap_size(fmap)); + if ((unsigned)fmap_find(buf, total_size) != offset) { + printf("FAILURE: bsearch failed to find fmap at offset 0\n"); + goto fmap_find_test_exit; + } + + /* test overrun detection */ + memset(buf, 0, total_size); + memcpy(&buf[total_size - fmap_size(fmap) + 1], + fmap, + fmap_size(fmap) - 1); + if (fmap_find(buf, total_size - 1) >= 0) { + printf("FAILURE: lsearch failed to catch overrun\n"); + goto fmap_find_test_exit; + } + if (fmap_find(buf, total_size) >= 0) { + printf("FAILURE: bsearch failed to catch overrun\n"); + goto fmap_find_test_exit; + } + + status = pass; +fmap_find_test_exit: + free(buf); + return status; +} + +int fmap_test(void) +{ + int rc = EXIT_SUCCESS; + struct fmap *my_fmap; + + /* + * This test has two parts: Creation of an fmap with one or more + * area(s), and other stuff. Since a valid fmap is required to run + * many tests, we abort if fmap creation fails in any way. + * + * Also, fmap_csum_test() makes some assumptions based on the areas + * appended. See fmap_append_area_test() for details. + */ + if ((my_fmap = fmap_create_test()) == NULL) { + rc = EXIT_FAILURE; + goto fmap_test_exit; + } + + if (fmap_find_test(my_fmap)) { + rc = EXIT_FAILURE; + goto fmap_test_exit; + } + + if (fmap_append_area_test(&my_fmap)) { + rc = EXIT_FAILURE; + goto fmap_test_exit; + } + + rc |= fmap_find_area_test(my_fmap); + rc |= fmap_size_test(); + rc |= fmap_flags_to_string_test(); + rc |= fmap_print_test(my_fmap); + +fmap_test_exit: + fmap_destroy(my_fmap); + if (rc) + printf("FAILED\n"); + return rc; +} + +int main(void) +{ + int result = fmap_test(); + + puts(""); + puts("==="); + puts(""); + if (!result) + puts("RESULT: All unit tests PASSED."); + else + puts("RESULT: One or more tests FAILED!"); + + return result; +} diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 3be613de195..52c9d13dbfd 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -5,6 +5,11 @@ # On some systems, `parted` and `debugfs` are located in /sbin. export PATH="$PATH:/sbin" +# external URLs +_url_primary=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery2.json +_url_enterprise=https://dl.google.com/dl/edgedl/chromeos/recovery/workspaceHardware_recovery2.json +_url_legacy=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf + exit_if_dependencies_are_missing() { local missing_deps=() local -A deps_map=( @@ -14,6 +19,7 @@ exit_if_dependencies_are_missing() { ["curl"]="curl" ["unzip"]="unzip" ["7z"]="p7zip" + ["python3"]="python3" ) # Check all dependencies at once @@ -36,19 +42,124 @@ exit_if_dependencies_are_missing() { fi } -get_inventory() { +get_inventory_legacy() { _conf=$1 - _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf + + echo "Downloading legacy recovery image inventory..." + curl -s "$_url_legacy" >"$_conf" +} + +get_inventory_json() { + _json_primary=$1 + _json_secondary=$2 echo "Downloading recovery image inventory..." + curl -s "$_url_primary" >"$_json_primary" + curl -s "$_url_enterprise" >"$_json_secondary" +} + +get_inventory_enterprise_json() { + _json_enterprise=$1 + _url_enterprise=https://dl.google.com/dl/edgedl/chromeos/recovery/workspaceHardware_recovery2.json + + echo "Downloading enterprise recovery image inventory..." + curl -s "$_url_enterprise" >"$_json_enterprise" +} + +lookup_recovery_from_json() { + _board=$1 + _json_primary=$2 + _json_secondary=$3 + + python3 - "$_board" "$_json_primary" "$_json_secondary" <<'PY' +import json +import re +import sys + +board = (sys.argv[1] or "").lower() +primary_path = sys.argv[2] +secondary_path = sys.argv[3] - curl -s "$_url" >$_conf +if not board: + sys.exit(2) + +preferred_channels = ["STABLE", "LTS", "LTC"] + +def load(path): + with open(path, "r", encoding="utf-8") as f: + return json.load(f) + +def normalize(s): + return str(s or "").strip() + +def match_entry(e): + """ + We treat the CLI argument as a HWID/board name (platform prefix), not the + recovery image codename embedded in the URL. + """ + hwidmatch = normalize(e.get("hwidmatch")) + hwids = e.get("hwids") or [] + + # 1) Exact hwids list (when present). + if isinstance(hwids, list): + for h in hwids: + h = normalize(h).lower() + if not h: + continue + # Accept either full HWID (GENESIS-FOO) or platform prefix (GENESIS). + if h == board or h.startswith(board + "-"): + return True + + # 2) hwidmatch regex string typically anchors the platform prefix. + if hwidmatch: + # Common patterns: ^GENESIS-.* , ^ATLAS .* , ^MORPHIUS[-| ].* , ... + # Require a word boundary after the board so we accept bracket/suffix + # forms without falsely matching a shorter prefix inside another name. + if re.match(rf"^\^?{re.escape(board)}\b", hwidmatch.strip(), re.IGNORECASE): + return True + + return False + +def pick(entries): + matches = [e for e in entries if isinstance(e, dict) and match_entry(e)] + if not matches: + return None + for ch in preferred_channels: + for e in matches: + if str(e.get("channel", "")).upper() == ch: + url = e.get("url") + file = e.get("file") + if url and file: + return (url, file) + for e in matches: + url = e.get("url") + file = e.get("file") + if url and file: + return (url, file) + return None + +primary = load(primary_path) +secondary = load(secondary_path) + +res = pick(primary) or pick(secondary) +if not res: + sys.exit(1) + +url, file = res +print(f"url={url}") +print(f"file={file}") +PY } download_image() { _url=$1 _file=$2 + if [ -z "$_url" ] || [ -z "$_file" ]; then + echo "Missing recovery URL or filename (url='$_url' file='$_file')" >&2 + exit 1 + fi + echo "Downloading recovery image" curl "$_url" >"$_file.zip" echo "Decompressing recovery image" @@ -160,36 +271,99 @@ do_one_board() { # Main # +LEGACY=0 +ENTERPRISE=0 + +usage() { + echo "Usage: $0 [--legacy] [--enterprise] " + echo + echo "Options:" + echo " --legacy Use legacy recovery image inventory (recovery.conf)" + echo " --enterprise Use enterprise recovery image inventory (workspaceHardware_recovery2.json) only" + echo + echo "Arguments:" + echo " boardname - Name of the board for which to extract the shellball firmware" + echo + echo "Examples:" + echo " $0 --legacy panther" + echo " $0 --enterprise genesis" + echo " $0 banshee" +} + +while [ $# -gt 0 ]; do + case "$1" in + --legacy) + LEGACY=1 + shift + ;; + --enterprise) + ENTERPRISE=1 + shift + ;; + -h|--help) + usage + exit 0 + ;; + --) + shift + break + ;; + -*) + echo "Unknown option: $1" >&2 + usage >&2 + exit 1 + ;; + *) + break + ;; + esac +done + BOARD=${1,,} exit_if_dependencies_are_missing -if [ "$BOARD" == "all" ]; then - CONF=$(mktemp) - get_inventory $CONF - - grep ^name= $CONF | while read _line; do - name=$(echo $_line | cut -f2 -d=) - echo Processing board $name - eval $(grep -v hwid= $CONF | grep -A11 "$_line" | - grep '\(url=\|file=\)') - BOARD=$(echo $url | cut -f3 -d_) - do_one_board $BOARD $url $file - done +if [ "$LEGACY" -eq 1 ] && [ "$ENTERPRISE" -eq 1 ]; then + echo "Options --legacy and --enterprise are mutually exclusive." >&2 + usage >&2 + exit 1 +fi + +if [ "$BOARD" != "" ]; then + if [ "$LEGACY" -eq 1 ]; then + CONF=$(mktemp) + get_inventory_legacy "$CONF" + + echo "Processing board $BOARD" + # shellcheck disable=SC2154 + eval "$(grep -i -w "$BOARD" -A8 "$CONF" | grep '\(url=\|file=\)')" + # shellcheck disable=SC2154 + do_one_board "$BOARD" "$url" "$file" - rm "$CONF" -elif [ "$BOARD" != "" ]; then - CONF=$(mktemp) - get_inventory $CONF + rm "$CONF" + else + JSON_SECONDARY=$(mktemp) + JSON_PRIMARY=$(mktemp) - echo Processing board $BOARD - eval $(grep -i -w $BOARD -A8 $CONF | grep '\(url=\|file=\)') - do_one_board $BOARD $url $file + if [ "$ENTERPRISE" -eq 1 ]; then + # Only use the enterprise inventory; provide an empty primary list. + printf '[]\n' >"$JSON_PRIMARY" + get_inventory_enterprise_json "$JSON_SECONDARY" + else + get_inventory_json "$JSON_PRIMARY" "$JSON_SECONDARY" + fi - rm "$CONF" + echo Processing board $BOARD + if ! eval "$(lookup_recovery_from_json "$BOARD" "$JSON_PRIMARY" "$JSON_SECONDARY")"; then + echo "Failed to find recovery image for board: $BOARD" >&2 + rm "$JSON_PRIMARY" "$JSON_SECONDARY" + exit 1 + fi + do_one_board "$BOARD" "$url" "$file" + + rm "$JSON_PRIMARY" "$JSON_SECONDARY" + fi else - echo "Usage: $0 " - echo " $0 all" - echo + usage exit 1 fi diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index cfcd44e8a7e..b719ad1bf6a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,19 +38,19 @@ COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources" # Math libraries (GCC dependencies) GMP_VERSION=6.3.0 MPFR_VERSION=4.2.2 -MPC_VERSION=1.3.1 +MPC_VERSION=1.4.1 # Core GCC components -GCC_VERSION=14.2.0 -BINUTILS_VERSION=2.45 +GCC_VERSION=15.2.0 +BINUTILS_VERSION=2.46.1 LIBSTDCXX_VERSION="${GCC_VERSION}" # GCC-specific C++ library # Low-level Tools (built after GCC) -NASM_VERSION=2.16.03 # x86 assembly -IASL_VERSION=20250807 # ACPI compiler +NASM_VERSION=3.01 # x86 assembly +IASL_VERSION=20251212 # ACPI compiler # Clang/LLVM Toolchain (alternative to GCC, built separately) CLANG_VERSION=21.1.8 -CMAKE_VERSION=4.0.3 # Required for building Clang +CMAKE_VERSION=4.3.4 # Required for building Clang # Architecture-specific options RISCV_ISA_SPEC=20191213 @@ -58,7 +58,7 @@ RISCV_ISA_SPEC=20191213 # Filename for each package GMP_ARCHIVE="gmp-${GMP_VERSION}.tar.xz" MPFR_ARCHIVE="mpfr-${MPFR_VERSION}.tar.xz" -MPC_ARCHIVE="mpc-${MPC_VERSION}.tar.gz" +MPC_ARCHIVE="mpc-${MPC_VERSION}.tar.xz" GCC_ARCHIVE="gcc-${GCC_VERSION}.tar.xz" LIBSTDCXX_ARCHIVE="${GCC_ARCHIVE}" BINUTILS_ARCHIVE="binutils-${BINUTILS_VERSION}.tar.xz" @@ -87,7 +87,7 @@ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" LIBSTDCXX_BASE_URL="${GCC_BASE_URL}" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" -IASL_BASE_URL="https://downloadmirror.intel.com/864114" +IASL_BASE_URL="https://github.com/acpica/acpica/releases/download/${IASL_VERSION}" # CLANG toolchain archive locations LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" diff --git a/util/crossgcc/patches/acpica-unix-20250807_iasl.patch b/util/crossgcc/patches/acpica-unix-20251212_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix-20250807_iasl.patch rename to util/crossgcc/patches/acpica-unix-20251212_iasl.patch diff --git a/util/crossgcc/patches/binutils-2.45_as-ipxe.patch b/util/crossgcc/patches/binutils-2.46.1_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.45_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.46.1_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.45_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.46.1_no-makeinfo.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.45_no-makeinfo.patch rename to util/crossgcc/patches/binutils-2.46.1_no-makeinfo.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-15.2.0_asan_shadow_offset_callback.patch similarity index 74% rename from util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch rename to util/crossgcc/patches/gcc-15.2.0_asan_shadow_offset_callback.patch index d446025a8ad..7e998772601 100644 --- a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch +++ b/util/crossgcc/patches/gcc-15.2.0_asan_shadow_offset_callback.patch @@ -37,17 +37,27 @@ diff --git a/gcc/asan.c b/gcc/asan.c index 235e21947..713bf994d 100644 --- a/gcc/asan.cc +++ b/gcc/asan.cc -@@ -1389,13 +1389,28 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, - TREE_ASM_WRITTEN (decl) = 1; +@@ -2086,23 +2086,27 @@ TREE_ASM_WRITTEN (id) = 1; + DECL_ALIGN_RAW (decl) = DECL_ALIGN_RAW (current_function_decl); emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); - shadow_base = expand_binop (Pmode, lshr_optab, base, - gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), - NULL_RTX, 1, OPTAB_DIRECT); -- shadow_base -- = plus_constant (Pmode, shadow_base, -- asan_shadow_offset () -- + (base_align_bias >> ASAN_SHADOW_SHIFT)); +- if (asan_dynamic_shadow_offset_p ()) +- { +- ret = expand_normal (get_asan_shadow_memory_dynamic_address_decl ()); +- shadow_base +- = expand_simple_binop (Pmode, PLUS, shadow_base, ret, NULL_RTX, +- /* unsignedp = */ 1, OPTAB_WIDEN); +- shadow_base = plus_constant (Pmode, shadow_base, +- (base_align_bias >> ASAN_SHADOW_SHIFT)); +- } +- else +- { +- shadow_base = plus_constant (Pmode, shadow_base, +- asan_shadow_offset () +- + (base_align_bias >> ASAN_SHADOW_SHIFT)); + if (param_asan_use_shadow_offset_callback) { + rtx addr, shadow_offset_rtx; + ret = init_one_libfunc ("__asan_shadow_offset"); @@ -56,25 +66,24 @@ index 235e21947..713bf994d 100644 + addr, ptr_mode); + shadow_offset_rtx = convert_memory_address (Pmode, ret); + shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); + shadow_base = expand_binop (Pmode, add_optab, shadow_base, -+ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); ++ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); + shadow_base = plus_constant (Pmode, shadow_base, -+ (base_align_bias >> ASAN_SHADOW_SHIFT)); ++ (base_align_bias >> ASAN_SHADOW_SHIFT)); + } else { + shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); + shadow_base = plus_constant (Pmode, shadow_base, -+ asan_shadow_offset () -+ + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } ++ asan_shadow_offset () ++ + (base_align_bias >> ASAN_SHADOW_SHIFT)); + } gcc_assert (asan_shadow_set != -1 && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); - shadow_mem = gen_rtx_MEM (SImode, shadow_base); ---- gcc-11.1.0/gcc/params.opt~ 2021-05-11 09:02:51.897508677 +0200 -+++ gcc-11.1.0/gcc/params.opt 2021-05-11 09:10:43.692610696 +0200 +--- gcc-15-20250112/gcc/params.opt~ ++++ gcc-15-20250112/gcc/params.opt @@ -50,6 +50,10 @@ Common Joined UInteger Var(param_asan_instrumentation_with_call_threshold) Init(7000) Param Optimization Use callbacks instead of inline code if number of accesses in function becomes greater or equal to this number. diff --git a/util/crossgcc/patches/gcc-14.2.0_gnat.patch b/util/crossgcc/patches/gcc-15.2.0_gnat.patch similarity index 66% rename from util/crossgcc/patches/gcc-14.2.0_gnat.patch rename to util/crossgcc/patches/gcc-15.2.0_gnat.patch index 2a37b155c42..e3862876ba5 100644 --- a/util/crossgcc/patches/gcc-14.2.0_gnat.patch +++ b/util/crossgcc/patches/gcc-15.2.0_gnat.patch @@ -9,18 +9,18 @@ like we do for a stage1 build. Signed-off-by: Nico Huber --- - gcc/ada/gcc-interface/Make-lang.in | 16 +++++++++++++--- - gcc/ada/init.c | 4 ++++ - 2 files changed, 17 insertions(+), 3 deletions(-) + gcc/ada/gcc-interface/Make-lang.in | 15 +++++++++++++-- + 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-interface/Make-lang.in index 9507f2f09203..cf7ec4cc1662 100644 --- a/gcc/ada/gcc-interface/Make-lang.in +++ b/gcc/ada/gcc-interface/Make-lang.in -@@ -57,18 +57,21 @@ WARN_ADAFLAGS= -W -Wall +@@ -56,19 +56,21 @@ + # need to be built by a recent/matching native so we might as well leave the # checks fully active. - STAGE1=False +-STAGE1=False +HOST_RT=False GNATBIND_FLAGS= GNATLIB= @@ -40,8 +40,8 @@ index 9507f2f09203..cf7ec4cc1662 100644 + HOST_RT=True endif - ALL_ADAFLAGS = \ -@@ -87,7 +89,7 @@ ifeq ($(strip $(filter-out hpux%,$(host_os))),) + ADA_CFLAGS = +@@ -88,7 +90,7 @@ STAGE1_LIBS=/usr/lib/libcl.a endif @@ -50,7 +50,7 @@ index 9507f2f09203..cf7ec4cc1662 100644 ADA_INCLUDES=$(COMMON_ADA_INCLUDES) adalib=$(dir $(shell $(CC) -print-libgcc-file-name))adalib GNATLIB=$(adalib)/$(if $(wildcard $(adalib)/libgnat.a),libgnat.a,libgnat.so) $(STAGE1_LIBS) -@@ -485,6 +487,7 @@ GNAT1_C_OBJS+= \ +@@ -506,6 +508,7 @@ ada/rtinit.o \ ada/seh_init.o @@ -58,7 +58,7 @@ index 9507f2f09203..cf7ec4cc1662 100644 GNAT_ADA_OBJS+= \ ada/gcc-interface/system.o \ ada/libgnat/a-assert.o \ -@@ -555,6 +558,7 @@ GNAT_ADA_OBJS+= \ +@@ -586,6 +589,7 @@ ada/libgnat/s-wchstw.o \ ada/libgnat/s-widuns.o endif @@ -66,17 +66,17 @@ index 9507f2f09203..cf7ec4cc1662 100644 # Object files for gnat executables GNAT1_ADA_OBJS = $(GNAT_ADA_OBJS) ada/back_end.o ada/gnat1drv.o -@@ -656,6 +660,9 @@ GNATBIND_OBJS += \ +@@ -692,6 +696,9 @@ ada/rtfinal.o \ ada/rtinit.o \ ada/seh_init.o \ -+ ++ +ifeq ($(HOST_RT),False) +GNATBIND_OBJS += \ ada/gcc-interface/system.o \ ada/libgnat/a-assert.o \ ada/libgnat/a-elchha.o \ -@@ -707,6 +714,9 @@ GNATBIND_OBJS += \ +@@ -746,6 +753,9 @@ ada/libgnat/s-wchjis.o \ ada/libgnat/s-wchstw.o \ ada/libgnat/s-widuns.o \ @@ -86,23 +86,5 @@ index 9507f2f09203..cf7ec4cc1662 100644 ada/adaint.o \ ada/argv.o \ ada/cio.o \ -diff --git a/gcc/ada/init.c b/gcc/ada/init.c -index 5212a38490d3..5ae2efd32ef3 100644 ---- a/gcc/ada/init.c -+++ b/gcc/ada/init.c -@@ -93,8 +93,12 @@ extern struct Exception_Data storage_error; - #ifdef CERT - #define Raise_From_Signal_Handler __gnat_raise_exception - #else -+#if __GNUC__ < 12 -+#define Raise_From_Signal_Handler ada__exceptions__raise_from_signal_handler -+#else - #define Raise_From_Signal_Handler __gnat_raise_from_signal_handler - #endif -+#endif - - extern void Raise_From_Signal_Handler (struct Exception_Data *, const void *) - ATTRIBUTE_NORETURN; -- -2.39.0 - +2.45.1 diff --git a/util/crossgcc/patches/gcc-15.2.0_libcody.patch b/util/crossgcc/patches/gcc-15.2.0_libcody.patch new file mode 100644 index 00000000000..9a9a9c89825 --- /dev/null +++ b/util/crossgcc/patches/gcc-15.2.0_libcody.patch @@ -0,0 +1,240 @@ +From 5780c7da817b67b99adc42f0e979858ebef38744 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sat, 23 May 2026 11:32:33 -0600 +Subject: [PATCH] Fix libcody build with host GCC 16 + +Applied the following patches from upstream to libcody: +- Commit b4a37c4b8caf ("GCC, meet C++20") +- Commit 07a767c7a50d ("libcody: Make it buildable by C++11 to C++26") +--- + libcody/client.cc | 36 +++++++++++++++++++----------------- + libcody/cody.hh | 22 ++++++++++++++++++++++ + libcody/server.cc | 28 ++++++++++++++-------------- + 3 files changed, 55 insertions(+), 31 deletions(-) + +diff --git a/libcody/client.cc b/libcody/client.cc +index ae69d19..147fecd 100644 +--- a/libcody/client.cc ++++ b/libcody/client.cc +@@ -97,7 +97,7 @@ int Client::CommunicateWithServer () + + static Packet CommunicationError (int err) + { +- std::string e {u8"communication error:"}; ++ std::string e {(const char *) u8"communication error:"}; + e.append (strerror (err)); + + return Packet (Client::PC_ERROR, std::move (e)); +@@ -110,33 +110,34 @@ Packet Client::ProcessResponse (std::vector &words, + { + if (e == EINVAL) + { +- std::string msg (u8"malformed string '"); ++ std::string msg ((const char *) u8"malformed string '"); + msg.append (words[0]); +- msg.append (u8"'"); ++ msg.append ((const char *) u8"'"); + return Packet (Client::PC_ERROR, std::move (msg)); + } + else +- return Packet (Client::PC_ERROR, u8"missing response"); ++ return Packet (Client::PC_ERROR, (const char *) u8"missing response"); + } + + Assert (!words.empty ()); +- if (words[0] == u8"ERROR") ++ if (words[0] == (const char *) u8"ERROR") + return Packet (Client::PC_ERROR, +- words.size () == 2 ? words[1]: u8"malformed error response"); ++ words.size () == 2 ? words[1] ++ : (const char *) u8"malformed error response"); + + if (isLast && !read.IsAtEnd ()) + return Packet (Client::PC_ERROR, +- std::string (u8"unexpected extra response")); ++ std::string ((const char *) u8"unexpected extra response")); + + Assert (code < Detail::RC_HWM); + Packet result (responseTable[code] (words)); + result.SetRequest (code); + if (result.GetCode () == Client::PC_ERROR && result.GetString ().empty ()) + { +- std::string msg {u8"malformed response '"}; ++ std::string msg {(const char *) u8"malformed response '"}; + + read.LexedLine (msg); +- msg.append (u8"'"); ++ msg.append ((const char *) u8"'"); + result.GetString () = std::move (msg); + } + else if (result.GetCode () == Client::PC_CONNECT) +@@ -199,7 +200,7 @@ Packet Client::Connect (char const *agent, char const *ident, + size_t alen, size_t ilen) + { + write.BeginLine (); +- write.AppendWord (u8"HELLO"); ++ write.AppendWord ((const char *) u8"HELLO"); + write.AppendInteger (Version); + write.AppendWord (agent, true, alen); + write.AppendWord (ident, true, ilen); +@@ -211,7 +212,8 @@ Packet Client::Connect (char const *agent, char const *ident, + // HELLO $version $agent [$flags] + Packet ConnectResponse (std::vector &words) + { +- if (words[0] == u8"HELLO" && (words.size () == 3 || words.size () == 4)) ++ if (words[0] == (const char *) u8"HELLO" ++ && (words.size () == 3 || words.size () == 4)) + { + char *eptr; + unsigned long val = strtoul (words[1].c_str (), &eptr, 10); +@@ -247,7 +249,7 @@ Packet Client::ModuleRepo () + // PATHNAME $dir | ERROR + Packet PathnameResponse (std::vector &words) + { +- if (words[0] == u8"PATHNAME" && words.size () == 2) ++ if (words[0] == (const char *) u8"PATHNAME" && words.size () == 2) + return Packet (Client::PC_PATHNAME, std::move (words[1])); + + return Packet (Client::PC_ERROR, u8""); +@@ -256,7 +258,7 @@ Packet PathnameResponse (std::vector &words) + // OK or ERROR + Packet OKResponse (std::vector &words) + { +- if (words[0] == u8"OK") ++ if (words[0] == (const char *) u8"OK") + return Packet (Client::PC_OK); + else + return Packet (Client::PC_ERROR, +@@ -319,11 +321,11 @@ Packet Client::IncludeTranslate (char const *include, Flags flags, size_t ilen) + // PATHNAME $cmifile + Packet IncludeTranslateResponse (std::vector &words) + { +- if (words[0] == u8"BOOL" && words.size () == 2) ++ if (words[0] == (const char *) u8"BOOL" && words.size () == 2) + { +- if (words[1] == u8"FALSE") +- return Packet (Client::PC_BOOL, 0); +- else if (words[1] == u8"TRUE") ++ if (words[1] == (const char *) u8"FALSE") ++ return Packet (Client::PC_BOOL); ++ else if (words[1] == (const char *) u8"TRUE") + return Packet (Client::PC_BOOL, 1); + else + return Packet (Client::PC_ERROR, u8""); +diff --git a/libcody/cody.hh b/libcody/cody.hh +index 789ce9e..93bce93 100644 +--- a/libcody/cody.hh ++++ b/libcody/cody.hh +@@ -47,12 +47,21 @@ namespace Detail { + + // C++11 doesn't have utf8 character literals :( + ++#if __cpp_char8_t >= 201811 ++template ++constexpr char S2C (char8_t const (&s)[I]) ++{ ++ static_assert (I == 2, "only single octet strings may be converted"); ++ return s[0]; ++} ++#else + template + constexpr char S2C (char const (&s)[I]) + { + static_assert (I == 2, "only single octet strings may be converted"); + return s[0]; + } ++#endif + + /// Internal buffering class. Used to concatenate outgoing messages + /// and Lex incoming ones. +@@ -123,6 +132,13 @@ public: + Space (); + Append (str, maybe_quote, len); + } ++#if __cpp_char8_t >= 201811 ++ void AppendWord (char8_t const *str, bool maybe_quote = false, ++ size_t len = ~size_t (0)) ++ { ++ AppendWord ((const char *) str, maybe_quote, len); ++ } ++#endif + /// Add a word as with AppendWord + /// @param str the string to append + /// @param maybe_quote string might need quoting, as for Append +@@ -264,6 +280,12 @@ public: + : string (s), cat (STRING), code (c) + { + } ++#if __cpp_char8_t >= 201811 ++ Packet (unsigned c, const char8_t *s) ++ : string ((const char *) s), cat (STRING), code (c) ++ { ++ } ++#endif + Packet (unsigned c, std::vector &&v) + : vector (std::move (v)), cat (VECTOR), code (c) + { +diff --git a/libcody/server.cc b/libcody/server.cc +index e2fa069..c18469f 100644 +--- a/libcody/server.cc ++++ b/libcody/server.cc +@@ -36,12 +36,12 @@ static RequestPair + const requestTable[Detail::RC_HWM] = + { + // Same order as enum RequestCode +- RequestPair {u8"HELLO", nullptr}, +- RequestPair {u8"MODULE-REPO", ModuleRepoRequest}, +- RequestPair {u8"MODULE-EXPORT", ModuleExportRequest}, +- RequestPair {u8"MODULE-IMPORT", ModuleImportRequest}, +- RequestPair {u8"MODULE-COMPILED", ModuleCompiledRequest}, +- RequestPair {u8"INCLUDE-TRANSLATE", IncludeTranslateRequest}, ++ RequestPair {(const char *) u8"HELLO", nullptr}, ++ RequestPair {(const char *) u8"MODULE-REPO", ModuleRepoRequest}, ++ RequestPair {(const char *) u8"MODULE-EXPORT", ModuleExportRequest}, ++ RequestPair {(const char *) u8"MODULE-IMPORT", ModuleImportRequest}, ++ RequestPair {(const char *) u8"MODULE-COMPILED", ModuleCompiledRequest}, ++ RequestPair {(const char *) u8"INCLUDE-TRANSLATE", IncludeTranslateRequest}, + }; + } + +@@ -135,21 +135,21 @@ void Server::ProcessRequests (void) + std::string msg; + + if (err > 0) +- msg = u8"error processing '"; ++ msg = (const char *) u8"error processing '"; + else if (ix >= Detail::RC_HWM) +- msg = u8"unrecognized '"; ++ msg = (const char *) u8"unrecognized '"; + else if (IsConnected () && ix == Detail::RC_CONNECT) +- msg = u8"already connected '"; ++ msg = (const char *) u8"already connected '"; + else if (!IsConnected () && ix != Detail::RC_CONNECT) +- msg = u8"not connected '"; ++ msg = (const char *) u8"not connected '"; + else +- msg = u8"malformed '"; ++ msg = (const char *) u8"malformed '"; + + read.LexedLine (msg); +- msg.append (u8"'"); ++ msg.append ((const char *) u8"'"); + if (err > 0) + { +- msg.append (u8" "); ++ msg.append ((const char *) u8" "); + msg.append (strerror (err)); + } + resolver->ErrorResponse (this, std::move (msg)); +@@ -176,7 +176,7 @@ Resolver *ConnectRequest (Server *s, Resolver *r, + return nullptr; + + if (words.size () == 3) +- words.emplace_back (u8""); ++ words.emplace_back ((const char *) u8""); + unsigned version = ParseUnsigned (words[1]); + if (version == ~0u) + return nullptr; +-- +2.54.0 + diff --git a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch b/util/crossgcc/patches/gcc-15.2.0_libcpp.patch similarity index 85% rename from util/crossgcc/patches/gcc-14.2.0_libcpp.patch rename to util/crossgcc/patches/gcc-15.2.0_libcpp.patch index 2b0c95338f3..ba60732f72e 100644 --- a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch +++ b/util/crossgcc/patches/gcc-15.2.0_libcpp.patch @@ -1,8 +1,8 @@ GCC with `-Wformat-security -Werror=format-security` hardening options enabled by default rejects some codes in libcpp. This patch fixes them. ---- gcc-8.3.0/libcpp/expr.cc.bak 2020-09-11 15:44:45.770000000 +0900 -+++ gcc-8.3.0/libcpp/expr.cc 2020-09-11 15:46:22.370000000 +0900 +--- gcc-15-20250112/libcpp/expr.cc.bak ++++ gcc-15-20250112/libcpp/expr.cc @@ -794,10 +794,10 @@ if (CPP_OPTION (pfile, c99)) @@ -16,8 +16,8 @@ by default rejects some codes in libcpp. This patch fixes them. } result |= CPP_N_INTEGER; ---- gcc-8.3.0/libcpp/macro.cc.bak 2020-09-11 16:01:42.550000000 +0900 -+++ gcc-8.3.0/libcpp/macro.cc 2020-09-11 16:03:47.850000000 +0900 +--- gcc-15-20250112/libcpp/macro.cc.bak ++++ gcc-15-20250112/libcpp/macro.cc @@ -160,7 +160,7 @@ if (m_state == 2 && token->type == CPP_PASTE) { diff --git a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch b/util/crossgcc/patches/gcc-15.2.0_libgcc.patch similarity index 89% rename from util/crossgcc/patches/gcc-14.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-15.2.0_libgcc.patch index 2f75c92b41f..8e93fa259fa 100644 --- a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch +++ b/util/crossgcc/patches/gcc-15.2.0_libgcc.patch @@ -1,9 +1,9 @@ This enables building on Mac OS and FreeBSD by adding support to their variants of the sed utility. -diff -urN gcc-5.2.0.orig/libgcc/config/t-hardfp gcc-5.2.0/libgcc/config/t-hardfp ---- gcc-5.2.0.orig/libgcc/config/t-hardfp 2015-01-05 04:33:28.000000000 -0800 -+++ gcc-8.1.0/libgcc/config/t-hardfp 2016-04-06 12:04:51.000000000 -0700 +diff -urN gcc-15-20250112.orig/libgcc/config/t-hardfp gcc-15-20250112/libgcc/config/t-hardfp +--- gcc-15-20250112.orig/libgcc/config/t-hardfp ++++ gcc-15-20250112/libgcc/config/t-hardfp @@ -59,21 +59,52 @@ hardfp_func_list := $(filter-out $(hardfp_exclusions),$(hardfp_func_list)) diff --git a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-15.2.0_musl_poisoned_calloc.patch similarity index 81% rename from util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch rename to util/crossgcc/patches/gcc-15.2.0_musl_poisoned_calloc.patch index b66380dad2b..dfbc02b91e8 100644 --- a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch +++ b/util/crossgcc/patches/gcc-15.2.0_musl_poisoned_calloc.patch @@ -2,8 +2,8 @@ Musl's uses calloc() which is marked as poisoned by GCC's "system.h". Work around that by making sure that gets included first. ---- gcc-13.2.0/gcc/ada/adaint.c -+++ gcc-13.2.0.musl/gcc/ada/adaint.c +--- gcc-15-20250112/gcc/ada/adaint.c ++++ gcc-15-20250112.musl/gcc/ada/adaint.c @@ -101,6 +101,10 @@ #include #endif @@ -23,8 +23,8 @@ included first. /* glibc versions earlier than 2.7 do not define the routines to handle dynamically allocated CPU sets. For these targets, we use the static ---- gcc-14-20240211/gcc/ada/argv.c -+++ gcc-14-20240211.musl/gcc/ada/argv.c +--- gcc-15-20250112/gcc/ada/argv.c ++++ gcc-15-20250112.musl/gcc/ada/argv.c @@ -51,10 +51,6 @@ #include "system.h" #endif @@ -36,8 +36,8 @@ included first. #ifdef __cplusplus extern "C" { #endif ---- gcc-13.2.0/gcc/ada/cio.c -+++ gcc-13.2.0.musl/gcc/ada/cio.c +--- gcc-15-20250112/gcc/ada/cio.c ++++ gcc-15-20250112.musl/gcc/ada/cio.c @@ -29,6 +29,8 @@ * * ****************************************************************************/ @@ -56,8 +56,8 @@ included first. /* We need L_tmpnam definition */ #include ---- gcc-13.2.0/gcc/ada/cstreams.c -+++ gcc-13.2.0.musl/gcc/ada/cstreams.c +--- gcc-15-20250112/gcc/ada/cstreams.c ++++ gcc-15-20250112.musl/gcc/ada/cstreams.c @@ -58,14 +58,14 @@ #include "vxWorks.h" #endif @@ -75,7 +75,7 @@ included first. #ifdef __cplusplus extern "C" { ---- gcc-13.2.0/gcc/ada/init.c +--- gcc-15-20250112/gcc/ada/init.c +++ gcc-13.2.0.musl/gcc/ada/init.c @@ -53,6 +53,8 @@ #undef __linux__ @@ -94,8 +94,8 @@ included first. #include "raise.h" #ifdef __cplusplus ---- gcc-13.2.0/gcc/ada/raise.c -+++ gcc-13.2.0.musl/gcc/ada/raise.c +--- gcc-15-20250112/gcc/ada/raise.c ++++ gcc-15-20250112.musl/gcc/ada/raise.c @@ -32,6 +32,8 @@ /* Shared routines to support exception handling. __gnat_unhandled_terminate is shared between all exception handling mechanisms. */ diff --git a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-15.2.0_rv32iafc.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch rename to util/crossgcc/patches/gcc-15.2.0_rv32iafc.patch diff --git a/util/crossgcc/patches/nasm-3.01_include-PROGOBJ-in-DIRS-dependency.patch b/util/crossgcc/patches/nasm-3.01_include-PROGOBJ-in-DIRS-dependency.patch new file mode 100644 index 00000000000..2487392905d --- /dev/null +++ b/util/crossgcc/patches/nasm-3.01_include-PROGOBJ-in-DIRS-dependency.patch @@ -0,0 +1,65 @@ +From fc56538bce4273f7d701647db4f81ae0c25004b0 Mon Sep 17 00:00:00 2001 +From: "H. Peter Anvin (Intel)" +Date: Wed, 15 Oct 2025 20:00:36 -0700 +Subject: [PATCH] Makefile: include $(PROGOBJ) in $(DIRS) dependency + +The $(DIRS) dependency didn't include $(PROGOBJ), which could cause +Make to try to build asm/nasm.o or disasm/ndisasm.o before the +corresponding object subdirectory had been created. + +Signed-off-by: H. Peter Anvin (Intel) +--- + Makefile.in | 4 ++-- + Mkfiles/msvc.mak | 2 +- + Mkfiles/openwcom.mak | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/Makefile.in b/Makefile.in +index 64e0cb2d..eb2adcd7 100644 +--- a/Makefile.in ++++ b/Makefile.in +@@ -224,7 +224,7 @@ ZLIBOBJ = \ + + LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB) + ALLOBJ_W = $(NASM) $(LIBOBJ_W) +-ALLOBJ = $(PROGOBJ) $(LIBOBJ) ++ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS) + SUBDIRS = stdlib nasmlib include config output asm disasm x86 \ + common zlib macros misc + XSUBDIRS = nsis win test doc editors +@@ -262,7 +262,7 @@ ndisasm$(X): $(NDISASM) $(MANIFEST) $(DISLIB) $(NASMLIB) + $(DISLIB) $(NASMLIB) $(LIBS) + + # Make sure we have subdirectories set up... +-$(LIBOBJ) $(LIBOBJ_DIS): $(DIRS) ++$(ALLOBJ): $(DIRS) + + #-- Begin Generated File Rules --# + +diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak +index 6d285011..a1e4404b 100644 +--- a/Mkfiles/msvc.mak ++++ b/Mkfiles/msvc.mak +@@ -175,7 +175,7 @@ ZLIBOBJ = \ + + LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB) + ALLOBJ_W = $(NASM) $(LIBOBJ_W) +-ALLOBJ = $(PROGOBJ) $(LIBOBJ) ++ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS) + SUBDIRS = stdlib nasmlib include config output asm disasm x86 \ + common zlib macros misc + XSUBDIRS = nsis win test doc editors +diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak +index f8f0069d..d752e24c 100644 +--- a/Mkfiles/openwcom.mak ++++ b/Mkfiles/openwcom.mak +@@ -161,7 +161,7 @@ ZLIBOBJ = & + + LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB) + ALLOBJ_W = $(NASM) $(LIBOBJ_W) +-ALLOBJ = $(PROGOBJ) $(LIBOBJ) ++ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS) + SUBDIRS = stdlib nasmlib include config output asm disasm x86 & + common zlib macros misc + XSUBDIRS = nsis win test doc editors + \ No newline at end of file diff --git a/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum deleted file mode 100644 index 188ab9995be..00000000000 --- a/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -76f0529964955679178714bc580eb560e52fab12 tarballs/acpica-unix-20250807.tar.gz diff --git a/util/crossgcc/sum/acpica-unix-20251212.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20251212.tar.gz.cksum new file mode 100644 index 00000000000..22f8aca3c11 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix-20251212.tar.gz.cksum @@ -0,0 +1 @@ +08128a2e0745500a42e6f1d6f3d1714e7ff5680e tarballs/acpica-unix-20251212.tar.gz diff --git a/util/crossgcc/sum/binutils-2.45.tar.xz.cksum b/util/crossgcc/sum/binutils-2.45.tar.xz.cksum deleted file mode 100644 index 05d55b3fc51..00000000000 --- a/util/crossgcc/sum/binutils-2.45.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -09fd8a50a95be4a94412fe3847d16280996679c5 tarballs/binutils-2.45.tar.xz diff --git a/util/crossgcc/sum/binutils-2.46.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.46.1.tar.xz.cksum new file mode 100644 index 00000000000..f3177435f33 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.46.1.tar.xz.cksum @@ -0,0 +1 @@ +1ddbae1e5c429bf32111c9343651e8fa28a9c2de tarballs/binutils-2.46.1.tar.xz diff --git a/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum b/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum deleted file mode 100644 index 627deeef6e8..00000000000 --- a/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -6899c8d69ba2bf1f24c6f27bcea4162e1488694b tarballs/cmake-4.0.3.tar.gz diff --git a/util/crossgcc/sum/cmake-4.3.4.tar.gz.cksum b/util/crossgcc/sum/cmake-4.3.4.tar.gz.cksum new file mode 100644 index 00000000000..a06878ffca6 --- /dev/null +++ b/util/crossgcc/sum/cmake-4.3.4.tar.gz.cksum @@ -0,0 +1 @@ +dd4a6f877f3864230896af561f4865d0034b834b tarballs/cmake-4.3.4.tar.gz diff --git a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum deleted file mode 100644 index f81c535d504..00000000000 --- a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d91ecc3d20ce6298bd95f9b09cc51dc6d3c73ae3 tarballs/gcc-14.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-15.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-15.2.0.tar.xz.cksum new file mode 100644 index 00000000000..a92b61ba61a --- /dev/null +++ b/util/crossgcc/sum/gcc-15.2.0.tar.xz.cksum @@ -0,0 +1 @@ +e9265c98ae18a6d952a636749d98c475ba2ca006 tarballs/gcc-15.2.0.tar.xz diff --git a/util/crossgcc/sum/mpc-1.3.1.tar.gz.cksum b/util/crossgcc/sum/mpc-1.3.1.tar.gz.cksum deleted file mode 100644 index 67962f61840..00000000000 --- a/util/crossgcc/sum/mpc-1.3.1.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -bac1c1fa79f5602df1e29e4684e103ad55714e02 tarballs/mpc-1.3.1.tar.gz diff --git a/util/crossgcc/sum/mpc-1.4.1.tar.xz.cksum b/util/crossgcc/sum/mpc-1.4.1.tar.xz.cksum new file mode 100644 index 00000000000..90df3021574 --- /dev/null +++ b/util/crossgcc/sum/mpc-1.4.1.tar.xz.cksum @@ -0,0 +1 @@ +3d9e196d973a822ae144d543c9d21023cef0870f tarballs/mpc-1.4.1.tar.xz diff --git a/util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum deleted file mode 100644 index 9ca23fb0c44..00000000000 --- a/util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -c63080347a5c1c8904456fe6c680b722558383b4 tarballs/nasm-2.16.03.tar.bz2 diff --git a/util/crossgcc/sum/nasm-3.01.tar.bz2.cksum b/util/crossgcc/sum/nasm-3.01.tar.bz2.cksum new file mode 100644 index 00000000000..4ef51c663dc --- /dev/null +++ b/util/crossgcc/sum/nasm-3.01.tar.bz2.cksum @@ -0,0 +1 @@ +4c7d481ea6ae0fc848a059f43ccee2bc2072a419 tarballs/nasm-3.01.tar.bz2 diff --git a/util/docker/Makefile b/util/docker/Makefile index 45562d7a7bc..5da9ec745d3 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -60,10 +60,11 @@ upload-coreboot-sdk: test-docker-login $(DOCKER) push coreboot/coreboot-sdk:$(COREBOOT_IMAGE_TAG) coreboot-jenkins-node: test-docker - cat coreboot-jenkins-node/Dockerfile | \ - sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/g" | \ - sed "s|{{SSH_KEY}}|$$(cat coreboot-jenkins-node/authorized_keys)|" | \ - $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) - + $(DOCKER) build \ + --build-arg=SDK_VERSION="$(COREBOOT_IMAGE_TAG)" \ + --build-arg=SSH_KEY="$(cat coreboot-jenkins-node/authorized_keys)" \ + --tag coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) \ + coreboot-jenkins-node upload-coreboot-jenkins-node: test-docker-login $(DOCKER) push coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 06a2defe19f..88058630c55 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -1,6 +1,4 @@ -# This dockerfile is not meant to be used directly by docker. The -# {{}} varibles are replaced with values by the makefile. Please generate -# the docker image for this file by running: +# Please generate the docker image for this file by running: # # make coreboot-jenkins-node # @@ -13,7 +11,10 @@ # Because we're piping the contents of the dockerfile into the # docker build command, the 'COPY' keyword isn't valid. -FROM coreboot/coreboot-sdk:{{SDK_VERSION}} +ARG SDK_VERSION +ARG SSH_KEY + +FROM coreboot/coreboot-sdk:${SDK_VERSION} USER root RUN apt-get -y update && \ @@ -84,7 +85,7 @@ RUN echo 'export PATH=$PATH:/opt/xgcc/bin' >> /home/coreboot/.bashrc && \ sphinx_autobuild===2024.2.4 \ sphinx_rtd_theme===2.0.0 \ && mkdir -p /home/coreboot/.ssh && \ - echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \ + echo "${SSH_KEY}" > /home/coreboot/.ssh/authorized_keys && \ chmod 0700 /home/coreboot/.ssh && \ chmod 0600 /home/coreboot/.ssh/authorized_keys USER root diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh index 47d13a92c0f..f7733a18426 100755 --- a/util/find_usbdebug/find_usbdebug.sh +++ b/util/find_usbdebug/find_usbdebug.sh @@ -55,7 +55,11 @@ find_devs_in_tree () { portstr=`printf "Port %03d" "$port"` fi - hubs_to_ignore="8087:0020 8087:0024 8087:8000 8087:8008" + hubs_to_ignore="" + hubs_to_ignore+="8087:0020 " # Intel 5 Series PCH + hubs_to_ignore+="8087:0024 " # Intel 6/7 Series PCH + hubs_to_ignore+="8087:8000 8087:8008 " # Intel 8/9 Series PCH + hubs_to_ignore+="8087:8001 8087:8009 " # Intel 9 Series PCH reqlvl=1 found= diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index c741e1d7c5d..a3b66fd4650 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -272,6 +272,8 @@ static enum ich_chipset ifd2_platform_to_chipset(const int pindex) return CHIPSET_800_SERIES_METEOR_LAKE; case PLATFORM_PTL: return CHIPSET_900_SERIES_PANTHER_LAKE; + case PLATFORM_NVL: + return CHIPSET_900_SERIES_NOVA_LAKE; case PLATFORM_ICL: return CHIPSET_400_SERIES_ICE_POINT; case PLATFORM_LBG: @@ -308,6 +310,7 @@ static int is_platform_ifd_2(void) PLATFORM_IFD2, PLATFORM_MTL, PLATFORM_PTL, + PLATFORM_NVL, PLATFORM_WBG, }; unsigned int i; @@ -565,6 +568,7 @@ static void decode_spi_frequency(unsigned int freq) case CHIPSET_500_600_SERIES_TIGER_ALDER_POINT: case CHIPSET_800_SERIES_METEOR_LAKE: case CHIPSET_900_SERIES_PANTHER_LAKE: + case CHIPSET_900_SERIES_NOVA_LAKE: _decode_spi_frequency_500_series(freq); break; default: @@ -649,6 +653,7 @@ static void decode_espi_frequency(unsigned int freq) break; case CHIPSET_800_SERIES_METEOR_LAKE: case CHIPSET_900_SERIES_PANTHER_LAKE: + case CHIPSET_900_SERIES_NOVA_LAKE: _decode_espi_frequency_800_series(freq); break; default: @@ -703,7 +708,7 @@ static int is_platform_with_pch(void) static int is_platform_with_100x_series_pch(void) { if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && - chipset <= CHIPSET_900_SERIES_PANTHER_LAKE) + chipset <= CHIPSET_900_SERIES_NOVA_LAKE) return 1; return 0; @@ -1041,7 +1046,8 @@ static void dump_fd(char *image, int size) if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT || chipset == CHIPSET_800_SERIES_METEOR_LAKE || - chipset == CHIPSET_900_SERIES_PANTHER_LAKE) { + chipset == CHIPSET_900_SERIES_PANTHER_LAKE || + chipset == CHIPSET_900_SERIES_NOVA_LAKE) { printf("FLMAP3: 0x%08x\n", fdb->flmap3); printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); @@ -1076,11 +1082,26 @@ static void dump_fd(char *image, int size) } } -/* Takes an image containing an IFD and creates a Flashmap .fmd file template. - * This flashmap will contain all IFD regions except the BIOS region. - * The BIOS region is created by coreboot itself and 'should' match the IFD region - * anyway (CONFIG_VALIDATE_INTEL_DESCRIPTOR should make sure). coreboot built system will use - * this template to generate the final Flashmap file. +static unsigned int ifd_image_size(const struct frba *frba) +{ + unsigned int end = 0; + + for (unsigned int i = 0; i < max_regions; i++) { + struct region region = get_region(frba, i); + + if (region.limit == 0 || region.base == 0x07FFF000) + continue; + + unsigned int region_end = (unsigned int)region.limit + 1; + if (region_end > end) + end = region_end; + } + + return end; +} + +/* Writes a complete .fmd for the IFD layout (valid input for fmaptool). + * coreboot replaces the SI_BIOS line with a top-aligned region and sub-layout. */ static void create_fmap_template(char *image, int size, const char *layout_fname) { @@ -1094,15 +1115,16 @@ static void create_fmap_template(char *image, int size, const char *layout_fname exit(EXIT_FAILURE); } - char *bbuf = "FLASH ##FLASH_SIZE## {\n"; - if (write(layout_fd, bbuf, strlen(bbuf)) < 0) { + unsigned int flash_size = ifd_image_size(frba); + char buf[LAYOUT_LINELEN]; + + snprintf(buf, LAYOUT_LINELEN, "FLASH 0x%X {\n", flash_size); + if (write(layout_fd, buf, strlen(buf)) < 0) { perror("Could not write to file"); exit(EXIT_FAILURE); } - /* fmaptool requires regions in .fmd to be sorted. - * => We need to sort the regions by base address before writing them in .fmd File - */ + /* fmaptool requires regions in .fmd to be sorted by base address. */ int count_regions = 0; struct region sorted_regions[MAX_REGIONS] = { 0 }; for (unsigned int i = 0; i < max_regions; i++) { @@ -1122,54 +1144,36 @@ static void create_fmap_template(char *image, int size, const char *layout_fname continue; } - /* Here we decide to use the coreboot generated FMAP BIOS region, instead of - * the one specified in the IFD. The case when IFD and FMAP BIOS region do not - * match cannot be caught here, therefore one should still validate IFD and - * FMAP via CONFIG_VALIDATE_INTEL_DESCRIPTOR - */ - if (i == REGION_BIOS) - continue; - sorted_regions[count_regions] = region; - // basically insertion sort - for (int i = count_regions - 1; i >= 0; i--) { - if (sorted_regions[i].base > sorted_regions[i + 1].base) { - struct region tmp = sorted_regions[i]; - sorted_regions[i] = sorted_regions[i + 1]; - sorted_regions[i + 1] = tmp; + /* insertion sort by base */ + for (int j = count_regions - 1; j >= 0; j--) { + if (sorted_regions[j].base > sorted_regions[j + 1].base) { + struct region tmp = sorted_regions[j]; + sorted_regions[j] = sorted_regions[j + 1]; + sorted_regions[j + 1] = tmp; } } count_regions++; } - // Now write regions sorted by base address in the fmap file for (int i = 0; i < count_regions; i++) { struct region region = sorted_regions[i]; - char buf[LAYOUT_LINELEN]; - snprintf(buf, LAYOUT_LINELEN, "\t%s@0x%X 0x%X\n", region_names[region.type].fmapname, region.base, region.size); + + snprintf(buf, LAYOUT_LINELEN, "\t%s@0x%X 0x%X\n", + region_names[region.type].fmapname, region.base, region.size); if (write(layout_fd, buf, strlen(buf)) < 0) { perror("Could not write to file"); exit(EXIT_FAILURE); } } - char *ebuf = "\tSI_BIOS@##BIOS_BASE## ##BIOS_SIZE## {\n" - "\t\t##CONSOLE_ENTRY##\n" - "\t\t##MRC_CACHE_ENTRY##\n" - "\t\t##SMMSTORE_ENTRY##\n" - "\t\t##SPD_CACHE_ENTRY##\n" - "\t\t##VPD_ENTRY##\n" - "\t\tFMAP@##FMAP_BASE## ##FMAP_SIZE##\n" - "\t\tCOREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##\n" - "\t}\n" - "}\n"; - if (write(layout_fd, ebuf, strlen(ebuf)) < 0) { + if (write(layout_fd, "}\n", 2) < 0) { perror("Could not write to file"); exit(EXIT_FAILURE); } close(layout_fd); - printf("Wrote layout to %s\n", layout_fname); + printf("Wrote IFD flashmap to %s\n", layout_fname); } static void write_regions(char *image, int size) @@ -1413,6 +1417,7 @@ static bool platform_has_extended_regions(void) case PLATFORM_ADL: case PLATFORM_MTL: case PLATFORM_PTL: + case PLATFORM_NVL: return true; default: return false; @@ -1478,6 +1483,7 @@ static void lock_descriptor(const char *filename, char *image, int size) case PLATFORM_IFD2: case PLATFORM_MTL: case PLATFORM_PTL: + case PLATFORM_NVL: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1632,6 +1638,7 @@ static uint8_t get_cse_data_partition_offset(void) case PLATFORM_ADL: case PLATFORM_MTL: case PLATFORM_PTL: + case PLATFORM_NVL: data_offset = 0x18; break; default: @@ -1663,6 +1670,9 @@ static uint32_t get_gpr0_offset(void) case PLATFORM_PTL: gpr0_offset = 0x76; break; + case PLATFORM_NVL: + gpr0_offset = 0x3C; + break; default: break; } @@ -2214,7 +2224,7 @@ static void print_usage(const char *name) printf("\n" " -d | --dump: dump intel firmware descriptor\n" " -f | --layout dump regions into a flashrom layout file\n" - " -F | --fmap-layout dump IFD regions into a fmap layout template (.fmd) file\n" + " -F | --fmap-layout write a complete .fmd from the IFD layout\n" " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" " -x | --extract: extract intel fd modules\n" " -i | --inject : inject file into region \n" @@ -2249,6 +2259,8 @@ static void print_usage(const char *name) " mtl - Meteor Lake\n" " sklkbl - Sky Lake/Kaby Lake\n" " tgl - Tiger Lake\n" + " ptl - Panther Lake\n" + " nvl - Nova Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" " -V | --newvalue The new value to write into PCH strap specified by -S\n" @@ -2549,6 +2561,8 @@ int main(int argc, char *argv[]) platform = PLATFORM_MTL; } else if (!strcmp(optarg, "ptl")) { platform = PLATFORM_PTL; + } else if (!strcmp(optarg, "nvl")) { + platform = PLATFORM_NVL; } else if (!strcmp(optarg, "wbg")) { platform = PLATFORM_WBG; } else { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index ef37ca72642..408b1eeed0c 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -40,6 +40,7 @@ enum ich_chipset { * variants onwards */ CHIPSET_800_SERIES_METEOR_LAKE, /* 14th gen Core i/o (LP) variants onwards */ CHIPSET_900_SERIES_PANTHER_LAKE, /* 16th gen Core i/o (LP) variants onwards */ + CHIPSET_900_SERIES_NOVA_LAKE, CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_DENVERTON, }; @@ -59,6 +60,7 @@ enum platform { PLATFORM_DNV, PLATFORM_MTL, PLATFORM_PTL, + PLATFORM_NVL, PLATFORM_WBG }; diff --git a/util/intelmetool/.gitignore b/util/intelmetool/.gitignore deleted file mode 100644 index ea65fca3118..00000000000 --- a/util/intelmetool/.gitignore +++ /dev/null @@ -1 +0,0 @@ -intelmetool diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile index 375118576aa..204490f5e51 100644 --- a/util/intelmetool/Makefile +++ b/util/intelmetool/Makefile @@ -2,15 +2,18 @@ PROGRAM = intelmetool -TOP ?= $(abspath ../..) -CC ?= gcc -INSTALL ?= /usr/bin/env install -PREFIX ?= /usr/local -CFLAGS ?= -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function \ +TOP ?= $(abspath ../..) +CC ?= gcc +INSTALL ?= /usr/bin/env install +PREFIX ?= /usr/local +CFLAGS ?= -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function \ -I $(TOP)/src/commonlib/bsd/include -LDFLAGS += -lpci -lz +LDFLAGS += -lpci -lz +SRCDIR ?= src +BUILDDIR ?= build OBJS = intelmetool.o me.o me_status.o mmap.o rcba.o msr.o +OBJS_P = $(addprefix $(BUILDDIR)/, $(OBJS)) OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) @@ -26,22 +29,30 @@ CFLAGS += -I/usr/pkg/include LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib -lz -lpciutils -lpci -l$(shell uname -p) endif -all: pciutils dep $(PROGRAM) +all: builddir pciutils dep $(PROGRAM) oldarc: CFLAGS += -DOLDARC oldarc: all -$(PROGRAM): $(OBJS) - $(CC) $(CFLAGS) -o $(PROGRAM) $(OBJS) $(LDFLAGS) +$(PROGRAM): $(OBJS_P) + $(CC) $(CFLAGS) -o $(BUILDDIR)/$(PROGRAM) $(OBJS_P) $(LDFLAGS) + +# Define build dir and src dirs here. Instead of overloading the default .o target, we're forced to prefix our targets with the build dir. This allows make to pick up on whether a target has been built in the past or not. +$(BUILDDIR)/%.o: $(SRCDIR)/%.c + $(CC) $(CFLAGS) -c -o $@ $< clean: - rm -f $(PROGRAM) *.o *~ junit.xml + rm -rf $(BUILDDIR) *~ junit.xml distclean: clean rm -f .dependencies dep: - @$(CC) $(CFLAGS) -MM *.c > .dependencies + @$(CC) $(CFLAGS) -MM $(SRCDIR)/*.c > .dependencies + +# Make sure the build directory exists. +builddir: + mkdir -p $(BUILDDIR) define LIBPCI_TEST /* Avoid a failing test due to libpci header symbol shadowing breakage */ @@ -64,18 +75,18 @@ export LIBPCI_TEST pciutils: @printf "\nChecking for development libraries: pci and zlib... " - @echo "$$LIBPCI_TEST" > .test.c - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ + @echo "$$LIBPCI_TEST" > $(BUILDDIR)/.test.c + @$(CC) $(CFLAGS) $(BUILDDIR)/.test.c -o $(BUILDDIR)/.test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "For RPM based distributions like Fedora, please install pciutils-devel and zlib-devel.\n"; \ printf "For DEB based distributions, please install libpci-dev and zlib1g-dev.\n"; \ - rm -f .test.c .test; exit 1) - @rm -rf .test.c .test .test.dSYM + rm -f $(BUILDDIR)/.test.c $(BUILDDIR)/.test; exit 1) + @rm -rf $(BUILDDIR)/.test.c $(BUILDDIR)/.test $(BUILDDIR)/.test.dSYM install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin - $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin + $(INSTALL) $(BUILDDIR)/$(PROGRAM) $(DESTDIR)$(PREFIX)/sbin -.PHONY: all clean distclean dep pciutils oldarc +.PHONY: all builddir clean distclean dep pciutils oldarc -include .dependencies diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/src/intelmetool.c similarity index 100% rename from util/intelmetool/intelmetool.c rename to util/intelmetool/src/intelmetool.c diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/src/intelmetool.h similarity index 99% rename from util/intelmetool/intelmetool.h rename to util/intelmetool/src/intelmetool.h index 3946f95d6f3..1ab4eaefd01 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/src/intelmetool.h @@ -454,6 +454,7 @@ extern int debug; #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */ #define PCI_DEVICE_ID_INTEL_CANNONLAKE 0xA360 /* Cannon Lake */ #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0F18 /* Bay Trail */ +#define PCI_DEVICE_ID_INTEL_ALDERLAKE 0x7AE8 /* Alder Lake */ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI1 0xA2BA /* Union Point MEI #1 */ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI2 0xA2BB /* Union Point MEI #2 */ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI3 0xA2BE /* Union Point MEI #3 */ @@ -512,6 +513,7 @@ extern int debug; ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \ ((x) == PCI_DEVICE_ID_INTEL_CANNONLAKE) || \ ((x) == PCI_DEVICE_ID_INTEL_BAYTRAIL) || \ + ((x) == PCI_DEVICE_ID_INTEL_ALDERLAKE) || \ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI1) || \ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI2) || \ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI3) || \ diff --git a/util/intelmetool/me.c b/util/intelmetool/src/me.c similarity index 100% rename from util/intelmetool/me.c rename to util/intelmetool/src/me.c diff --git a/util/intelmetool/me.h b/util/intelmetool/src/me.h similarity index 100% rename from util/intelmetool/me.h rename to util/intelmetool/src/me.h diff --git a/util/intelmetool/me_status.c b/util/intelmetool/src/me_status.c similarity index 100% rename from util/intelmetool/me_status.c rename to util/intelmetool/src/me_status.c diff --git a/util/intelmetool/mmap.c b/util/intelmetool/src/mmap.c similarity index 100% rename from util/intelmetool/mmap.c rename to util/intelmetool/src/mmap.c diff --git a/util/intelmetool/mmap.h b/util/intelmetool/src/mmap.h similarity index 100% rename from util/intelmetool/mmap.h rename to util/intelmetool/src/mmap.h diff --git a/util/intelmetool/msr.c b/util/intelmetool/src/msr.c similarity index 100% rename from util/intelmetool/msr.c rename to util/intelmetool/src/msr.c diff --git a/util/intelmetool/msr.h b/util/intelmetool/src/msr.h similarity index 100% rename from util/intelmetool/msr.h rename to util/intelmetool/src/msr.h diff --git a/util/intelmetool/rcba.c b/util/intelmetool/src/rcba.c similarity index 100% rename from util/intelmetool/rcba.c rename to util/intelmetool/src/rcba.c diff --git a/util/intelmetool/rcba.h b/util/intelmetool/src/rcba.h similarity index 100% rename from util/intelmetool/rcba.h rename to util/intelmetool/src/rcba.h diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 05d5c092fd5..d6a0422afc8 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -206,8 +206,64 @@ static const struct { "12th generation (Alder Lake N family) Intel Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1, "12th generation (Alder Lake N family) Intel Processor"}, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0, + "13th generation (Raptor Lake S family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2, + "13th generation (Raptor Lake HX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8, "13th generation (Raptor Lake H family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8, + "13th generation (Raptor Lake H family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4, + "13th generation (Raptor Lake H family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4, + "13th generation (Raptor Lake H family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8, + "13th generation (Raptor Lake PX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8, + "13th generation (Raptor Lake PX family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8, + "13th generation (Raptor Lake U family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4, + "13th generation (Raptor Lake U family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4, + "13th generation (Raptor Lake U family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0, + "13th generation (Raptor Lake E family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0, + "13th generation (Raptor Lake E family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0, + "13th generation (Raptor Lake E family) Core Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_MTL_ID_M, "14th generation (Meteor Lake M family) Core Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_1, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index e38fb190bb9..79561b0a602 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -442,7 +442,35 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3 0x7d14 /* Meteorlake P */ #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4 0x7d15 /* Meteorlake P */ #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5 0x7d16 /* Meteorlake P */ -#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16 0xa700 /* Raptorlake S/S Refresh 8P+16E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8 0xa703 /* Raptorlake S 8P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8 0xa704 /* Raptorlake S/S Refresh 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4 0xa705 /* Raptorlake S/S Refresh 6P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2 0x4640 /* Raptorlake S/S Refresh 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2 0x4648 /* Raptorlake S/S Refresh 6P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0 0x4630 /* Raptorlake S/S Refresh 4P+0E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12 0xa740 /* Raptorlake S Refresh 8P+12E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0 0x4610 /* Raptorlake S Refresh 2P+0E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16 0xa702 /* Raptorlake HX/HX Refresh 8P+16E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12 0xa729 /* Raptorlake HX/HX Refresh 8P+12E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8 0xa728 /* Raptorlake HX/HX Refresh 8P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8 0xa72a /* Raptorlake HX/HX Refresh 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4 0xa719 /* Raptorlake HX/HX Refresh 6P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2 0x4637 /* Raptorlake HX 8P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2 0x463b /* Raptorlake HX 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2 0x4647 /* Raptorlake HX 6P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8 0xa706 /* Raptorlake H/H Refresh/P 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8 0xa707 /* Raptorlake H/H Refresh/P 4P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4 0xa715 /* Raptorlake H/H Refresh 6P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4 0xa716 /* Raptorlake H/H Refresh 4P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8 0xa709 /* Raptorlake PX 6P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8 0xa70a /* Raptorlake PX 4P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8 0xa708 /* Raptorlake U/U Refresh 2P+8E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4 0xa71b /* Raptorlake U/U Refresh 2P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4 0xa71c /* Raptorlake U 1P+4E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0 0xa711 /* Raptorlake E/E Refresh 8P + 0E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0 0xa712 /* Raptorlake E/E Refresh 6P + 0E */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0 0xa713 /* Raptorlake E/E Refresh E 4P + 0E */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 0fb36aa38cc..7fcabcec9fb 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -123,10 +123,13 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s printf("Access to BAR6 is currently disabled, " "attempting to enable.\n"); pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); - if (pci_read_long(nb_device6, 0x04) & (1 << 1)) + if (pci_read_long(nb_device6, 0x04) & (1 << 1)) { printf("Enabled successfully.\n"); - else + } + else { printf("Enable FAILED!\n"); + return 1; + } } mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ break; @@ -165,14 +168,72 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s "attempting to enable.\n"); mchbar_phys |= 0x1; pci_write_long(nb, 0x48, mchbar_phys); - if(pci_read_long(nb, 0x48) & 1) + if(pci_read_long(nb, 0x48) & 1) { printf("Enabled successfully.\n"); - else + } + else { printf("Enable FAILED!\n"); + return 1; + } } mchbar_phys &= 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0: + mchbar_phys = pci_read_long(nb, 0x48); + + /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. + * If it isn't, try to set it. This may fail, because there is + * some bit that locks that bit, and isn't in the public + * datasheets. + */ + + if(!(mchbar_phys & 1)) + { + printf("Access to the MCHBAR is currently disabled, " + "attempting to enable.\n"); + mchbar_phys |= 0x1; + pci_write_long(nb, 0x48, mchbar_phys); + if(pci_read_long(nb, 0x48) & 1) { + printf("Enabled successfully.\n"); + } + else { + printf("Enable FAILED!\n"); + return 1; + } + } + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x000003fffffe0000UL; /* 42:17 */ + size = 128 * 1024; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 6544bac5a78..9e89a6057b1 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -256,6 +256,120 @@ static const io_register_t cometlake_dmi_registers[] = { { 0x9A, 2, "LSTS2" }, // Link Status 2 }; +static const io_register_t raptorlake_dmi_registers[] = { + { 0x000, 4, "ID" }, // Device Identifiers + { 0x004, 2, "CMD" }, // Device Command + { 0x006, 2, "PSTS" }, // Primary Status + { 0x008, 4, "RID_CC" }, // Revision ID + { 0x00e, 1, "HTYPE" }, // Header Type + { 0x01e, 2, "SSTS" }, // Secondary Status + { 0x02c, 4, "SVD" }, // Subsystem Vendor IDs + { 0x034, 1, "CAPP" }, // Capabilities List Pointer + { 0x03e, 1, "BCTRL" }, // Bridge Control + { 0x044, 1, "DCAP" }, // Device Capabilities + { 0x048, 2, "DCTL" }, // Device Control + { 0x04a, 2, "DSTS" }, // Device Status + { 0x04c, 4, "LCAP" }, // Link Capabilities + { 0x050, 2, "LCTL" }, // Link Control + { 0x052, 2, "LSTS" }, // Link Status + { 0x05c, 2, "RCTL" }, // Root Control + { 0x060, 4, "RSTS" }, // Root Status + { 0x064, 4, "DCAP2" }, // Device Capabilities 2 + { 0x068, 2, "DCTL2" }, // Device Control 2 + { 0x06a, 2, "DSTS2" }, // Device Status 2 + { 0x06c, 4, "LCAP2" }, // Link Capabilities 2 + { 0x070, 2, "LCTL2" }, // Link Control 2 + { 0x072, 2, "LSTS2" }, // Link Status 2 + { 0x074, 4, "SLCAP2" }, // Slot Capabilities 2 + { 0x078, 2, "SLCTL2" }, // Slot Control 2 + { 0x07a, 2, "SLSTS2" }, // Slot Status 2 + { 0x080, 2, "MID" }, // Message Signaled Interrupt Identifiers + { 0x082, 2, "MC" }, // Message Signaled Interrupt Message + { 0x084, 4, "MA" }, // Message Signaled Interrupt Message Address + { 0x088, 2, "MD" }, // Message Signaled Interrupt Message Data + { 0x090, 2, "SVCAP" }, // Subsystem Vendor Capability + { 0x094, 4, "SVID" }, // Subsystem Vendor IDs + { 0x0a0, 2, "PMCAP" }, // Power Management Capability + { 0x0a2, 2, "PMC" }, // PCI Power Management Capabilities + { 0x0a4, 4, "PMCS" }, // PCI Power Management Control + { 0x100, 4, "AECH" }, // Advanced Error Extended + { 0x104, 4, "UES" }, // Uncorrectable Error Status + { 0x108, 4, "UEM" }, // Uncorrectable Error Mask + { 0x10c, 4, "UEV" }, // Uncorrectable Error Severity + { 0x110, 4, "CES" }, // Correctable Error Status + { 0x114, 4, "CEM" }, // Correctable Error Mask + { 0x118, 4, "AECC" }, // Advanced Error Capabilities And Control + { 0x11c, 4, "HL_DW1" }, // Header Log + { 0x120, 4, "HL_DW2" }, // Header Log + { 0x124, 4, "HL_DW3" }, // Header Log + { 0x128, 4, "HL_DW4" }, // Header Log + { 0x12c, 4, "REC" }, // Root Error Command + { 0x130, 4, "RES" }, // Root Error Status + { 0x134, 4, "ESID" }, // Error Source Identification + { 0x150, 4, "PTMECH" }, // PTM Extended Capability Header + { 0x284, 4, "PVCCR1" }, // Port VC Capability Register 1 + { 0x288, 4, "PVCC2" }, // Port VC Capability 2 + { 0x28c, 2, "PVCC" }, // Port VC Control + { 0x28e, 2, "PVCS" }, // Port VC Status + { 0x290, 4, "V0VCRC" }, // Virtual Channel 0 Resource Capability + { 0x294, 4, "V0CTL" }, // Virtual Channel 0 Resource Control + { 0x29a, 2, "V0STS" }, // Virtual Channel 0 Resource Status + { 0x29c, 4, "V1VCRC" }, // Virtual Channel 1 Resource Capability + { 0x2a0, 4, "V1CTL" }, // Virtual Channel 1 Resource Control + { 0x2a6, 2, "V1STS" }, // Virtual Channel 1 Resource Status + { 0xa30, 4, "SPEECH" }, // Secondary PCI Express Extended Capability Header + { 0xa34, 4, "LCTL3" }, // Link Control 3 + { 0xa38, 4, "LES" }, // Lane Error Status + { 0xa3c, 4, "L01EC" }, // Lane 0 And Lane 1 Equalization Control + { 0xa40, 4, "L23EC" }, // Lane 2 And Lane 3 Equalization Control + { 0xa44, 4, "L45EC" }, // Lane 4 And Lane 5 Equalization Control + { 0xa48, 4, "L67EC" }, // Lane 6 And Lane 7 Equalization Control + { 0xa4c, 4, "L89EC" }, // Lane 8 And Lane 9 Equalization Control + { 0xa50, 4, "L1011EC" }, // Lane 10 And Lane 11 Equalization Control + { 0xa54, 4, "L1213EC" }, // Lane 12 And Lane 13 Equalization Control + { 0xa58, 4, "L1415EC" }, // Lane 14 And Lane 15 Equalization Control + { 0xa90, 4, "DLFECH" }, // Data Link Feature Extended Capability Header + { 0xa94, 4, "DLFCAP" }, // Data Link Feature Capabilities Register + { 0xa98, 4, "DLFSTS" }, // Data Link Feature Status Register + { 0xa9c, 4, "PL16GECH" }, // Physical Layer 16.0 GT/s Extended Capability Header + { 0xaa0, 4, "PL16CAP" }, // Physical Layer 16.0 GT/s Capability Register + { 0xaa4, 4, "PL16CTL" }, // Physical Layer 16.0 GT/s Control Register + { 0xaa8, 4, "PL16S" }, // Physical Layer 16.0 GT/s Status Register + { 0xaac, 4, "PL16LDPMS" }, // Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register + { 0xab0, 4, "PL16FRDPMS" }, // Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register + { 0xab4, 4, "PL16SRDPMS" }, // Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register + { 0xab8, 4, "PL16ES" }, // Physical Layer 16.0 GT/s Extra Status Register + { 0xabc, 2, "PL16L01EC" }, // Physical Layer 16.0 GT/s Lane 01 Equalization Control Register + { 0xabe, 2, "PL16L23EC" }, // Physical Layer 16.0 GT/s Lane 23 Equalization Control Register + { 0xac0, 2, "PL16L45EC" }, // Physical Layer 16.0 GT/s Lane 45 Equalization Control Register + { 0xac2, 2, "PL16L67EC" }, // Physical Layer 16.0 GT/s Lane 67 Equalization Control Register + { 0xac4, 2, "PL16L89EC" }, // Physical Layer 16.0 GT/s Lane 89 Equalization Control Register + { 0xac6, 2, "PL16L1011EC" }, // Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register + { 0xac8, 2, "PL16L1213EC" }, // Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register + { 0xaca, 2, "PL16L1415EC" }, // Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register + { 0xc70, 4, "VNNREMCTL" }, // VNN Removal Control + { 0xc74, 4, "VNNRSNRC1" }, // VNN Removal Save And Restore Hardware Contexts 1 + { 0xd00, 4, "DIDOVR" }, // Device ID Override + { 0xedc, 4, "PL16MECH" }, // Physical Layer 16.0 GT/s Margining Extended Capability Header + { 0xee0, 4, "PL16MPCPS" }, // Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status + { 0xee4, 4, "PL16L0MCS" }, // Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register + { 0xee8, 4, "PL16L1MCS" }, // Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register + { 0xeec, 4, "PL16L2MCS" }, // Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register + { 0xef0, 4, "PL16L3MCS" }, // Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register + { 0xef4, 4, "PL16L4MCS" }, // Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register + { 0xef8, 4, "PL16L5MCS" }, // Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register + { 0xefc, 4, "PL16L6MCS" }, // Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register + { 0xf00, 4, "PL16L7MCS" }, // Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register + { 0xf04, 4, "PL16L8MCS" }, // Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register + { 0xf08, 4, "PL16L9MCS" }, // Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register + { 0xf0c, 4, "PL16L10MCS" }, // Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register + { 0xf10, 4, "PL16L11MCS" }, // Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register + { 0xf14, 4, "PL16L12MCS" }, // Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register + { 0xf18, 4, "PL16L13MCS" }, // Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register + { 0xf1c, 4, "PL16L14MCS" }, // Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register + { 0xf20, 4, "PL16L15MCS" }, // Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register +}; + /* * Egress Port Root Complex MMIO configuration space */ @@ -321,6 +435,35 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0: case PCI_DEVICE_ID_INTEL_CORE_CML_U1: case PCI_DEVICE_ID_INTEL_CORE_CML_U2: case PCI_DEVICE_ID_INTEL_CORE_CML_U3: @@ -498,6 +641,40 @@ int print_dmibar(struct pci_dev *nb) dmi_registers = alderlake_dmi_registers; size = ARRAY_SIZE(alderlake_dmi_registers); break; + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmi_registers = raptorlake_dmi_registers; + size = ARRAY_SIZE(raptorlake_dmi_registers); + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; @@ -612,6 +789,35 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_4_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_S_2_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_16: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_12: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_8_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_8_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_HX_6_4_2: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_6_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_4_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_6_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_PX_4_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_8: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_2_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_U_1_4: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_8_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_6_0: + case PCI_DEVICE_ID_INTEL_CORE_RPL_ID_E_4_0: case PCI_DEVICE_ID_INTEL_CORE_CML_U1: case PCI_DEVICE_ID_INTEL_CORE_CML_U2: case PCI_DEVICE_ID_INTEL_CORE_CML_U3: diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 010591768df..ae6ae2b3d38 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -390,10 +390,10 @@ int conf_read_simple(const char *name, int def) FILE *in = NULL; char *line = NULL; size_t line_asize = 0; - char *p, *val; + char *p, *val, *sym_name; struct symbol *sym; int i, def_flags; - const char *warn_unknown, *sym_name; + const char *warn_unknown; warn_unknown = getenv("KCONFIG_WARN_UNKNOWN_SYMBOLS"); if (name) { diff --git a/util/kconfig/patches/0016-util-kconfig-confdata.c-fix-Werror-discarded-qualifi.patch b/util/kconfig/patches/0016-util-kconfig-confdata.c-fix-Werror-discarded-qualifi.patch new file mode 100644 index 00000000000..a367256102c --- /dev/null +++ b/util/kconfig/patches/0016-util-kconfig-confdata.c-fix-Werror-discarded-qualifi.patch @@ -0,0 +1,41 @@ +From 2a1a1d1b305ab276279234f70410bb6486a2049f Mon Sep 17 00:00:00 2001 +From: Mike Banon +Date: Tue, 10 Mar 2026 00:14:58 +0100 +Subject: [PATCH] util/kconfig/confdata.c: fix -Werror=discarded-qualifiers + +In conf_read_simple(), strchr() is called on 'sym_name', which is +declared const char. The function returns a char that discards the +const qualifier when assigned to 'p', possibly triggering a compiler +warning when building the kconfig tools (e.g. with "make menuconfig"). + +The data comes from the modifiable 'line' buffer, so the const qualifier +is misplaced. Removing it makes sym_name non-const, matching reality, +while all subsequent uses are read-only (passed to sym_find() and +conf_touch_dep() which expect const char*). This change is safe and +eliminates the warning without any downsides. + +Change-Id: I1ed6d033a97bd08b46bd6c9aebf29848560d573a +Signed-off-by: Mike Banon +--- + util/kconfig/confdata.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +Index: kconfig/confdata.c +=================================================================== +diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c +index 0105917..ae6ae2b 100644 +--- a/util/kconfig/confdata.c ++++ b/util/kconfig/confdata.c +@@ -390,10 +390,10 @@ + FILE *in = NULL; + char *line = NULL; + size_t line_asize = 0; +- char *p, *val; ++ char *p, *val, *sym_name; + struct symbol *sym; + int i, def_flags; +- const char *warn_unknown, *sym_name; ++ const char *warn_unknown; + + warn_unknown = getenv("KCONFIG_WARN_UNKNOWN_SYMBOLS"); + if (name) { diff --git a/util/kconfig/patches/series b/util/kconfig/patches/series index 6058fe7ac61..31d446ef81c 100644 --- a/util/kconfig/patches/series +++ b/util/kconfig/patches/series @@ -8,3 +8,4 @@ 0013-util-kconfig-detect-ncurses-on-FreeBSD.patch 0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch 0015-fix-incorrect-spdx-strings.patch +0016-util-kconfig-confdata.c-fix-Werror-discarded-qualifi.patch diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 3a28d104b15..5442e18d988 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -24,7 +24,7 @@ HEADER_EXCLUDED="\ ^src/drivers/net/ne2k.c\$|\ ^src/drivers/xgi/common/initdef.h\$|\ ^src/drivers/xgi/common/vstruct.h\$|\ -^src/lib/gnat/|\ +^src/commonlib/gnat/|\ ^src/lib/lzmadecode.[ch]\$|\ ^src/lib/stack.c\$|\ ^src/sbom/TAGS|\ diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index a772352b313..996fd782271 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -22,7 +22,7 @@ for mobodir in $(${FIND_FILES} src/mainboard | sed -n 's,^\(src/mainboard/[^/]*/ fi category="$(sed -n 's#^Category: \(.*\)$#\1#p' < "$board_info")" case "$category" in - desktop|server|laptop|half|mini|settop|"eval"|sbc|emulation|misc) + desktop|server|laptop|half|mini|settop|"eval"|sbc|emulation|misc|aio) ;; "") echo "$board_info doesn't contain 'Category' tag" diff --git a/util/lint/lint-stable-009-old-licenses b/util/lint/lint-stable-009-old-licenses index 202a1a9b5e6..73264845b4b 100755 --- a/util/lint/lint-stable-009-old-licenses +++ b/util/lint/lint-stable-009-old-licenses @@ -15,7 +15,7 @@ LINTDIR="$( . "${LINTDIR}/helper_functions.sh" HEADER_EXCLUDED="\ -^src/lib/gnat/|\ +^src/commonlib/gnat/|\ ^src/vendorcode/|\ ^util/kconfig/|\ \|\ diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 5be744570a5..d17b53cf90b 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -12,10 +12,13 @@ LINTDIR="$( # shellcheck source=helper_functions.sh . "${LINTDIR}/helper_functions.sh" -SYMBOLS='CONFIG_MAINBOARD_DIR\|CONFIG_MAINBOARD_HAS_' +# Full .config / defconfig files set these as their own symbols (or as +# "# CONFIG_* is not set"). Miniconfigs omit them; they are selected from the +# board Kconfig. Match only those line forms so using CONFIG_MAINBOARD_DIR in +# a path does not false-positive. +FULL_CFG_REGEX='^[[:space:]]*CONFIG_MAINBOARD_DIR=|^[[:space:]]*# CONFIG_MAINBOARD_DIR is not set|^[[:space:]]*CONFIG_MAINBOARD_HAS_[A-Za-z0-9_]+=|^[[:space:]]*# CONFIG_MAINBOARD_HAS_[A-Za-z0-9_]+ is not set' -#look for a couple of things that should only be set by select keywords for file in \ - $(${GREP_FILES} -l "$SYMBOLS" configs) ; do \ + $(${GREP_FILES} -l -E "${FULL_CFG_REGEX}" configs) ; do \ echo "Error: $file seems to be a full config"; \ done diff --git a/util/liveiso/nixos/build.sh b/util/liveiso/nixos/build.sh index 40e39b59db6..50d63eff293 100755 --- a/util/liveiso/nixos/build.sh +++ b/util/liveiso/nixos/build.sh @@ -11,4 +11,4 @@ fi nix-build '' \ -A config.system.build.isoImage \ -I nixos-config=$config \ - -I nixpkgs=https://github.com/NixOS/nixpkgs/archive/refs/heads/nixos-24.05.tar.gz + -I nixpkgs=https://github.com/NixOS/nixpkgs/archive/refs/heads/nixos-26.05.tar.gz diff --git a/util/liveiso/nixos/common.nix b/util/liveiso/nixos/common.nix index 4c906cab1c1..89ca64cfaac 100644 --- a/util/liveiso/nixos/common.nix +++ b/util/liveiso/nixos/common.nix @@ -8,13 +8,13 @@ ]; - system.stateVersion = "24.05"; + system.stateVersion = "26.05"; isoImage = { makeEfiBootable = true; makeUsbBootable = true; - isoName = "${config.isoImage.isoBaseName}-${config.system.nixos.label}-${pkgs.stdenv.hostPlatform.system}.iso"; }; + image.fileName = "${config.image.baseName}-${config.system.nixos.label}-${pkgs.stdenv.hostPlatform.system}.iso"; environment = { variables = { @@ -41,7 +41,6 @@ extraModulePackages = with config.boot.kernelPackages; [ acpi_call chipsec - zfs ]; # Make programs more likely to work in low memory # environments. The kernel's overcommit heustistics bite us @@ -124,8 +123,8 @@ fuse3 fwts gptfdisk - gitAndTools.gitFull - gitAndTools.tig + gitFull + tig gzip hdparm hexdump @@ -157,7 +156,7 @@ phoronix-test-suite powertop psmisc - python3Full + python3 rsync screen sdparm diff --git a/util/liveiso/nixos/graphical.nix b/util/liveiso/nixos/graphical.nix index 77df3cbc131..1ddecd1b872 100644 --- a/util/liveiso/nixos/graphical.nix +++ b/util/liveiso/nixos/graphical.nix @@ -38,22 +38,21 @@ }; }; - services.xserver = { - enable = true; - displayManager = { - gdm = { - enable = true; - autoSuspend = false; - }; - autoLogin = { - enable = true; - user = "user"; - }; + services.displayManager = { + gdm = { + enable = true; + autoSuspend = false; + }; + }; + services.desktopManager.gnome.enable = true; + services.displayManager = { + autoLogin = { + enable = true; + user = "user"; }; - desktopManager.gnome.enable = true; }; - hardware.pulseaudio.enable = false; + services.pulseaudio.enable = false; services.pipewire = { enable = true; pulse.enable = true; @@ -73,23 +72,21 @@ gnome = { evolution-data-server.enable = lib.mkForce false; gnome-online-accounts.enable = lib.mkForce false; - gnome-online-miners.enable = lib.mkForce false; gnome-initial-setup.enable = lib.mkForce false; gnome-browser-connector.enable = lib.mkForce false; }; telepathy.enable = lib.mkForce false; - dleyna-renderer.enable = lib.mkForce false; - dleyna-server.enable = lib.mkForce false; + dleyna.enable = lib.mkForce false; }; programs.geary.enable = lib.mkForce false; environment.gnome.excludePackages = with pkgs; [ - gnome.gnome-weather - gnome.epiphany - gnome.gnome-contacts + gnome-weather + epiphany + gnome-contacts gnome-photos - gnome.gnome-music + gnome-music yelp ]; } diff --git a/util/mec152x/Makefile b/util/mec152x/Makefile index 43b350145cb..fea5f364a0e 100644 --- a/util/mec152x/Makefile +++ b/util/mec152x/Makefile @@ -13,6 +13,7 @@ HOSTCFLAGS ?= $(CFLAGS) HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3 HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/ HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include +HOSTCFLAGS += -include $(TOP)/src/commonlib/bsd/include/commonlib/bsd/compiler.h HOSTLDFLAGS ?= $(LDFLAGS) diff --git a/util/release/get_new_authors b/util/release/get_new_authors new file mode 100755 index 00000000000..5fb979e0eb2 --- /dev/null +++ b/util/release/get_new_authors @@ -0,0 +1,208 @@ +#!/usr/bin/env bash +# +# SPDX-License-Identifier: GPL-2.0-only +# +# Identify new contributors between two git points in time. +# Optionally update the AUTHORS file with any newly found names. + +set -euo pipefail + +usage() { + echo + echo "Usage: $0 [--update] [--full] " + echo + echo "Examples:" + echo " $0 24.02 25.01" + echo " $0 --update 24.02 25.01" + echo " $0 --full 24.02 25.01" + echo + echo "Notes:" + echo " * 'old_version' and 'new_version' can be tags, branches, or commit IDs." + echo " * New contributors are names present in history up to new_version" + echo " that were not present in history up to old_version." + echo +} + +fail() { + echo "ERROR: $*" >&2 + exit 1 +} + +UPDATE=0 +FULL=0 + +while [ $# -gt 0 ]; do + case "$1" in + --update) + UPDATE=1 + shift + ;; + --full) + FULL=1 + shift + ;; + -h|--help) + usage + exit 0 + ;; + --) + shift + break + ;; + -*) + fail "Unknown option: $1" + ;; + *) + break + ;; + esac +done + +[ $# -eq 2 ] || { usage; exit 1; } + +OLD_GIT_VERSION="$1" +NEW_GIT_VERSION="$2" + +if ! { cdup="$(git rev-parse --show-cdup 2>/dev/null)" && [ -z "${cdup}" ]; }; then + fail "This is not the top directory of a git repo." +fi + +git rev-parse --verify "${OLD_GIT_VERSION}^{commit}" >/dev/null 2>&1 || \ + fail "Invalid old_version: ${OLD_GIT_VERSION}" +git rev-parse --verify "${NEW_GIT_VERSION}^{commit}" >/dev/null 2>&1 || \ + fail "Invalid new_version: ${NEW_GIT_VERSION}" + +before_emails="$(mktemp)" +after_emails="$(mktemp)" +new_emails_tmp="$(mktemp)" +new_names_tmp="$(mktemp)" +trap 'rm -f "$before_emails" "$after_emails" "$new_emails_tmp" "$new_names_tmp"' EXIT + +git log --pretty=%ae "${OLD_GIT_VERSION}" 2>/dev/null | \ + awk '{ print tolower($0) }' | sort -u > "$before_emails" +git log --pretty=%ae "${NEW_GIT_VERSION}" 2>/dev/null | \ + awk '{ print tolower($0) }' | sort -u > "$after_emails" + +grep -Fxv -f "$before_emails" "$after_emails" > "$new_emails_tmp" || true +NEW_AUTHOR_COUNT="$(wc -l < "$new_emails_tmp" | tr -d ' ')" + +# Map each newly seen email to the first author name observed in the target range. +git log --reverse --pretty=format:'%ae%x1f%an' "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" | \ + awk -F '\x1f' ' + NR == FNR { + new_emails[$1] = 1 + next + } + { + email = tolower($1) + if (new_emails[email] && !seen[email]) { + print $2 + seen[email] = 1 + } + } + ' "$new_emails_tmp" - > "$new_names_tmp" + +printf "New contributors between %s and %s:\n" "$OLD_GIT_VERSION" "$NEW_GIT_VERSION" +if [ "$NEW_AUTHOR_COUNT" -eq 0 ]; then + echo "(none)" +elif [ "$FULL" -eq 0 ]; then + cat "$new_names_tmp" +else + while IFS= read -r author_email; do + first_commit="$( + git log --reverse --date=short \ + --pretty=format:'%an%x1f%ae%x1f%ad%x1f%H%x1f%s' \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" | \ + awk -F '\x1f' -v author_email="$author_email" ' + !found && tolower($2) == author_email { + print $1 "\x1f" $2 "\x1f" $3 "\x1f" $4 "\x1f" $5 + found = 1 + } + ' + )" + if [ -z "$first_commit" ]; then + printf "* (unknown) | email: %s | date: (unknown) | hash: (unknown) | subject: (unknown)\n" \ + "$author_email" + continue + fi + IFS=$'\x1f' read -r author_name commit_email first_date first_hash first_subject < "$header_tmp" + + # Names start at the first non-comment, non-blank line. + awk ' + BEGIN { in_names = 0 } + !in_names && ($0 ~ /^#/ || $0 ~ /^[[:space:]]*$/) { next } + { in_names = 1; print } + ' "$AUTHORS_FILE" > "$existing_names_tmp" + + sed '/^[[:space:]]*$/d' "$new_names_tmp" | LC_ALL=C sort -fu > "$new_names_sorted_tmp" + cp "$existing_names_tmp" "$working_names_tmp" + + while IFS= read -r new_author; do + # Skip if a case-insensitive match already exists. + if awk -v new_author="$new_author" ' + BEGIN { found = 1; target = tolower(new_author) } + tolower($0) == target { found = 0; exit } + END { exit found } + ' "$working_names_tmp"; then + continue + fi + + # Insert at the first case-insensitive position that sorts after new_author. + awk -v new_author="$new_author" ' + BEGIN { inserted = 0; target = tolower(new_author) } + { + if (!inserted && tolower($0) > target) { + print new_author + inserted = 1 + } + print + } + END { + if (!inserted) + print new_author + } + ' "$working_names_tmp" > "$inserted_tmp" + mv "$inserted_tmp" "$working_names_tmp" + done < "$new_names_sorted_tmp" + + { + cat "$header_tmp" + cat "$working_names_tmp" + } > "$new_authors_file_tmp" + + mv "$new_authors_file_tmp" "$AUTHORS_FILE" + echo "Updated AUTHORS with ${NEW_AUTHOR_COUNT} new contributor(s)." +fi diff --git a/util/smmstoretool/Makefile b/util/smmstoretool/Makefile index d73c25165a1..bc977731a60 100644 --- a/util/smmstoretool/Makefile +++ b/util/smmstoretool/Makefile @@ -12,7 +12,9 @@ PREFIX ?= /usr/local HOSTCFLAGS ?= $(CFLAGS) HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3 +HOSTCFLAGS += -I $(ROOT)/commonlib/include HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include +HOSTCFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h HOSTCFLAGS += -I $(ROOT)/vendorcode/intel/edk2/ HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/ HOSTCFLAGS += -I $(MDE) diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index de92612b9ba..1ffa7bb7da9 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -44,6 +44,7 @@ var supportedPlatforms = [...]string{ "MTL", "PHX", "PTL", + "NVL", } var supportedMemTechs = [...]string{ diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index acb10abc660..2a46503afb1 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -176,7 +176,7 @@ const ( /* ------------------------------------------------------------------------------------------ */ var LP5PlatformSetMap = map[int][]int{ - 0: {PlatformPTL, PlatformMTL, PlatformADL}, + 0: {PlatformNVL, PlatformPTL, PlatformMTL, PlatformADL}, 1: {PlatformPHX, PlatformMDN}, } diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index a516b86337e..230966aa5cd 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -79,6 +79,7 @@ const ( PlatformMTL PlatformPHX PlatformPTL + PlatformNVL PlatformMax ) @@ -101,6 +102,7 @@ var platformNames = map[int]string{ PlatformMTL: "MTL", PlatformPHX: "PHX", PlatformPTL: "PTL", + PlatformNVL: "NVL", } var memTechMap = map[string]memTech{ diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 39839d9aa64..2dcfc9e929a 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -17,7 +17,7 @@ CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o exar.o fintek.o ite.o nsc.o \ - nuvoton.o smsc.o winbond.o infineon.o aspeed.o + nuvoton.o smsc.o winbond.o infineon.o aspeed.o microchip.o OS_ARCH ?= $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/superiotool/microchip.c b/util/superiotool/microchip.c new file mode 100644 index 00000000000..342dff6579d --- /dev/null +++ b/util/superiotool/microchip.c @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "superiotool.h" + +#define DEVICE_ID_MSB 0x1f +#define DEVICE_ID_LSB 0x1e +#define DEVICE_SUBID 0x1d +#define DEVICE_REVISION 0x1c + +// Always reads 0xfe with recent parts +#define DEVICE_ID_REG_LEGACY 0x20 + + +static const struct { + uint32_t devid_subdevid; + const char *name; +} chip_names[] = { + // MEC152x-Data-Sheet-DS00003427C.pdf, Table 1-1 "MEC152X FEATURE LIST BY PACKAGE" + {0x0023b4, "MEC1523-144 WFBGA"}, + {0x002334, "MEC1521-144 WFBGA"}, + {0x002374, "MEC1527-144 WFBGA"}, + {0x002333, "MEC1521-128 VTQFP/WFBGA"}, + {0x002373, "MEC1527-128 WFBGA"}, + + // MEC142x data sheet (00002343C.pdf), Table 7-3 "DEVICE IDENTIFICATION PER PRODUCT" + {0x001110, "MEC1424"}, + {0x001310, "MEC1426"}, + {0x001510, "MEC1428"}, + + // MEC172x-Data-Sheet-DS00003583D.pdf, Table 1-1 "MEC172X FEATURE LIST" + {0x002234, "MEC1723N B0-I/SZ"}, + {0x002274, "MEC1727N-B0-I/SZ"}, + {0x002227, "MEC1721N-B0-I/LJ"}, + {0x002237, "MEC1723N-B0-I/LJ"}, + {0x002277, "MEC1727N-B0-I/LJ"}, + + {EOT} +}; + +static const char *lookup_chip_name(uint16_t device_id, uint8_t subdevice_id) +{ + const uint32_t id = (((uint32_t)device_id) << 8) | subdevice_id; + for (size_t i = 0; chip_names[i].devid_subdevid != EOT; i++) { + if (chip_names[i].devid_subdevid == id) + return chip_names[i].name; + } + return "UNKNOWN"; +} + +// .superio_id holds only the device id, which indicates the family (e.g. +// MEC152x or MEC172x or ...) +// We do parse the subdevice id (which indicates the part, e.g. MEC1523 vs +// MEC1521) later. See also `chip_names`. +// We don't list the TEST and Reserved registers, because there are just too many of them. +static const struct superio_registers reg_table[] = { + {0x0023, "MEC152x", { /* Default I/O Address: 0x2e/0x2f */ + {NOLDN, NULL, + {0x1c,0x1d,0x1e,0x1f,0x20,EOT}, + {MISC,MISC,0x23,0x00,0xfe,EOT}}, + // refer to "MEC152x System BIOS Porting Guide" AN3622-Application-Note-DS00003622A.pdf + // Table 5-1 "HOST LOGICAL DEVICES ON MEC152X ESPI" + // or to MEC152x-Data-Sheet-DS00003427C.pdf, Table 9-6 + // (note that the BIOS Porting Guide seems to be wrong about LDN 2f / 32 byte Test Block) + {0x0d, "eSPI I/O Component", + {0x30, + 0x34,0x36,0x37, 0x38,0x3a,0x3b, 0x3c,0x3e,0x3f, // ldn _ d e 0 + 0x40,0x42,0x43, 0x44,0x46,0x47, 0x48,0x4a,0x4b, 0x4c,0x4e,0x4f, // ldn 1 2 3 4 + 0x50,0x52,0x53, 0x58,0x5a,0x5b, 0x5c,0x5e,0x5f, // ldn 5 _ 7 8 + 0x60,0x62,0x63, 0x64,0x66,0x67, 0x68,0x6a,0x6b, 0x6c,0x6e,0x6f, // ldn 9 a 10 11 + 0x74,0x76,0x77, 0x78,0x7a,0x7b, 0x7c,0x7e,0x7f, // ldn _ 20 21 14 + 0x84,0x86,0x87, 0x88,0x8a,0x8b, // ldn _ 2f b _ + 0xac,0xad,0xae,0xaf,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5, + 0xb6,0xb7,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf, + EOT}, + {0x00, + 0x00,0x2e,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x60,0x00, 0x00,0x62,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x92,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,RSVD,0xff, + 0xff,0xff,0xff,0xff,0xff,RSVD,RSVD,0xff,0xff,0xff, + EOT}}, + {0x0e, "eSPI Memory Component", {0x30,EOT}, {0x00,EOT}}, + {0x00, "Mailbox", {0x30,EOT}, {0x00,EOT}}, + {0x01, "8042 Emulated Keyboard Controller", {0x30,EOT}, {0x00,EOT}}, + {0x02, "ACPI EC0", {0x30,EOT}, {0x00,EOT}}, + {0x03, "ACPI EC1", {0x30,EOT}, {0x00,EOT}}, + {0x04, "ACPI EC2", {0x30,EOT}, {0x00,EOT}}, + {0x05, "ACPI EC3", {0x30,EOT}, {0x00,EOT}}, + {0x07, "ACPI PM1", {0x30,EOT}, {0x00,EOT}}, + {0x08, "Port 92-Legacy (Fast Keyboard)", {0x30,EOT}, {0x00,EOT}}, + {0x09, "UART 0", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, // c.f. Section 16 (UART) + {0x0a, "UART 1", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, // subsection 16.11 + {0x0b, "UART 2", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, // ("Configuration Registers") + {0x10, "EMI 0", {0x30,EOT}, {0x00,EOT}}, + {0x11, "EMI 1", {0x30,EOT}, {0x00,EOT}}, + {0x14, "Real Time Clock", {0x30,EOT}, {0x00,EOT}}, + {0x20, "Port 80 BIOS Debug Port 0", {0x30,EOT}, {0x00,EOT}}, + {0x21, "Port 80 BIOS Debug Port 1", {0x30,EOT}, {0x00,EOT}}, + {0x2f, "32 Byte Test Block", {0x30,EOT}, {0x00,EOT}}, + {EOT}}}, + + {0x0022, "MEC172x", { + {NOLDN, NULL, + {0x1c,0x1d,0x1e,0x1f,0x20,0x24,0x25,0x26,0x27,EOT}, + {MISC,MISC,0x22,0x00,0xfe,MISC,MISC,MISC,MISC,EOT}}, + // refer to "MEC172x System BIOS Porting Guide" AN3642-Application-Note-DS00003642A.pdf + // Table 5-1 "HOST LOGICAL DEVICES ON MEC172X ESPI" + // or to MEC152x-Data-Sheet-DS00003427C.pdf, Table 9-6 + // (note that the BIOS Porting Guide seems to be wrong about LDN 2f / 32 byte Test Block) + {0x0d, "eSPI I/O Component", + {0x30, + 0x34,0x36,0x37, 0x38,0x3a,0x3b, 0x3c,0x3e,0x3f, // ldn _ d e 0 + 0x40,0x42,0x43, 0x44,0x46,0x47, 0x48,0x4a,0x4b, 0x4c,0x4e,0x4f, // ldn 1 2 3 4 + 0x50,0x52,0x53, 0x54,0x56,0x57, 0x58,0x5a,0x5b, 0x5c,0x5e,0x5f, // ldn 5 6 7 8 + 0x60,0x62,0x63, 0x64,0x66,0x67, 0x68,0x6a,0x6b, 0x6c,0x6e,0x6f, // ldn 9 a 10 11 + 0x70,0x72,0x73, 0x74,0x76,0x77, 0x78,0x7a,0x7b, 0x7c,0x7e,0x7f, // ldn 12 20 21 14 + 0x88,0x8a,0x8b, 0x8c,0x8e,0x8f, // ldn _ 2f b _ + 0xac,0xad,0xae,0xaf,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5, + 0xb6,0xb7,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe, + EOT}, + {0x00, + 0x00,0x2e,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x60,0x00, 0x00,0x62,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x92,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + EOT}}, + {0x0e, "eSPI Memory Component", {0x30,EOT}, {0x00,EOT}}, + {0x00, "Mailbox", {0x30,EOT}, {0x00,EOT}}, + {0x01, "8042 Emulated Keyboard Controller", {0x30,EOT}, {0x00,EOT}}, + {0x02, "ACPI EC0", {0x30,EOT}, {0x00,EOT}}, + {0x03, "ACPI EC1", {0x30,EOT}, {0x00,EOT}}, + {0x04, "ACPI EC2", {0x30,EOT}, {0x00,EOT}}, + {0x05, "ACPI EC3", {0x30,EOT}, {0x00,EOT}}, + {0x06, "ACPI EC4", {0x30,EOT}, {0x00,EOT}}, + {0x07, "ACPI PM1", {0x30,EOT}, {0x00,EOT}}, + {0x08, "Port 92-Legacy (Fast Keyboard)", {0x30,EOT}, {0x00,EOT}}, + {0x09, "UART 0", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, // c.f. Section 18 (UART) + {0x0a, "UART 1", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, // 18.11 ("Configuration Registers") + {0x10, "EMI 0", {0x30,EOT}, {0x00,EOT}}, + {0x11, "EMI 1", {0x30,EOT}, {0x00,EOT}}, + {0x12, "EMI 2", {0x30,EOT}, {0x00,EOT}}, + {0x14, "Real Time Clock", {0x30,EOT}, {0x00,EOT}}, + {0x20, "Port 80 BIOS Debug Port 0", {0x30,EOT}, {0x00,EOT}}, + {0x21, "Port 80 BIOS Debug Port 1", {0x30,EOT}, {0x00,EOT}}, + {0x2f, "32 Byte Test Block", {0x30,EOT}, {0x00,EOT}}, + {0x0f, "glue", {0x30,EOT}, {0x00,EOT}}, + {EOT}}}, + + /* Note: There's some guesswork going on for MEC142x based on MEC152x and MEC172x. + This is only a "better-than-nothing" entry! */ + {0x0011, "MEC142x (missing registers!)", { /* Note: 0x0011, 0x0013 and 0x0015 all belong to this family. */ + {NOLDN, NULL, + {0x1c,0x1d,0x1e,0x1f,0x20,EOT}, + {MISC,MISC,0x11,0x00,0xfe,EOT}}, + // refer to MEC142x data sheet 00002343C.pdf Table 7-4 + // and Table 4-14 "I/O BASE ADDRESS REGISTERS" + {0x10, "eSPI I/O Component", + {0x30, + 0x34,0x36,0x37, 0x38,0x3a,0x3b, 0x3c,0x3e,0x3f, // ldn _ 10 12 9 + 0x40,0x42,0x43, 0x44,0x46,0x47, 0x48,0x4a,0x4b, 0x4c,0x4e,0x4f, // ldn 1 3 4 a + 0x50,0x52,0x53, 0x54,0x56,0x57, 0x58,0x5a,0x5b, 0x5c,0x5e,0x5f, // ldn b 5 7 6 + 0x60,0x62,0x63, 0x64,0x66,0x67, 0x68,0x6a,0x6b, 0x6c,0x6e,0x6f, // ldn 0 15 16 14 + EOT}, + {0x00, + 0x00,0x2e,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + 0x00,0x60,0x00, 0x00,0x62,0x00, 0x00,0x66,0x00, 0x00,0x00,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x92,0x00, + 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, + EOT}}, + {0x12, "eSPI Memory Component", {0x30,EOT}, {0x00,EOT}}, + {0x0c, "LPC Interface", {0x30,EOT}, {0x00,EOT}}, + {0x09, "Mailbox", {0x30,EOT}, {0x00,EOT}}, + {0x01, "8042 Emulated Keyboard Controller", {0x30,EOT}, {0x00,EOT}}, + {0x03, "ACPI EC0", {0x30,EOT}, {0x00,EOT}}, + {0x04, "ACPI EC1", {0x30,EOT}, {0x00,EOT}}, + {0x0a, "ACPI EC2", {0x30,EOT}, {0x00,EOT}}, + {0x0b, "ACPI EC3", {0x30,EOT}, {0x00,EOT}}, + {0x05, "ACPI PM1", {0x30,EOT}, {0x00,EOT}}, + {0x07, "UART 0", {0x30,0xf0,EOT}, {0x00,0x02,EOT}}, + {0x06, "Port 92-Legacy (Fast Keyboard)", {0x30,EOT}, {0x00,EOT}}, + {0x00, "EMI 0", {0x30,EOT}, {0x00,EOT}}, + {0x15, "Port 80 BIOS Debug Port 0", {0x30,EOT}, {0x00,EOT}}, + {0x16, "Port 80 BIOS Debug Port 1", {0x30,EOT}, {0x00,EOT}}, + {0x14, "32 Byte Test Block", {0x30,EOT}, {0x00,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_microchip(uint16_t port) +{ + OUTB(0x55, port); +} + +static void exit_conf_mode_microchip(uint16_t port) +{ + OUTB(0xaa, port); +} + +void probe_idregs_microchip(uint16_t port) +{ + probing_for("Microchip", "", port); + + enter_conf_mode_microchip(port); + + uint8_t legacy_id = regval(port, DEVICE_ID_REG_LEGACY); + if (legacy_id != 0xfe) { + if (verbose) + printf(NOTFOUND "legacy_id=0x%02x, expected 0xfe\n", legacy_id); + exit_conf_mode_microchip(port); + return; + } + + uint16_t id = (regval(port, DEVICE_ID_MSB) << 8) | regval(port, DEVICE_ID_LSB); + uint8_t subid = regval(port, DEVICE_SUBID); + uint8_t revision = regval(port, DEVICE_REVISION); + + uint16_t id_for_reg_table = id; + uint32_t id_subid = (id << 8) | subid; + // MEC142x parts use different numbers despite same family. + if (id_subid == 0x001310 || id_subid == 0x001510) + id_for_reg_table = 0x0011; // cheat a bit, they're compatible + + if (superio_unknown(reg_table, id_for_reg_table)) { + if (verbose) + printf(NOTFOUND "id=0x%04x, subid=0x%02x, rev=0x%02x\n", id, subid, revision); + exit_conf_mode_microchip(port); + return; + } + + printf("Found %s %s (id=0x%04x, subid=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, id_for_reg_table), lookup_chip_name(id, subid), + id, subid, revision, port); + chip_found = 1; + + dump_superio("Microchip", reg_table, port, id_for_reg_table, LDN_SEL); + + exit_conf_mode_microchip(port); +} + +void print_microchip_chips(void) +{ + print_vendor_chips("Microchip", reg_table); +} diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 8f9a029aea2..6429870d1f0 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -618,6 +618,76 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc563, "NCT6779D (undocumented ID)", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20, + 0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc5, + 0x62,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00, + 0x01,MISC,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x0f,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9, + 0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00, + 0x00,0x00,EOT}}, + {0x0d, "WDT1", + {0xf0,EOT}, + {0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff, + 0x9d,0x00,0x00,EOT}}, + {0x14, "Port 80 UART", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {0xc452, "NCT6102D / NCT6106D", { {NOLDN, NULL, {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, diff --git a/util/superiotool/superiotool.8 b/util/superiotool/superiotool.8 index 41d078026e0..aed9071a2a0 100644 --- a/util/superiotool/superiotool.8 +++ b/util/superiotool/superiotool.8 @@ -83,6 +83,18 @@ the output of the .B --dump option. .TP +.B "\-a, \-\-alternate-dump" +Use alternative dump format, more suitable for diff. +.TP +.B "\-u, \-\-unknown-regs" +Dump all registers in the known LDNs (displays only those unequal to 0x00 and 0xff). +Implies +.B \-\-alternate-dump +.TP +.B "\-U, \-\-unknown-ldns" +Dump all registers in all LDNs, probing through all of them. Implies +.B \-\-unknown-regs +.TP .B "\-l, \-\-list-supported" List all Super I/O chips recognized by .BR superiotool ". The phrase" diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index a62f49a0845..5a8cedaf540 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -9,6 +9,7 @@ /* Command line options. */ int dump = 0, verbose = 0, extra_dump = 0, alternate_dump = 0; +int dump_unknown_regs = 0, dump_unknown_ldns = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; @@ -106,28 +107,33 @@ static void set_extra_selector(uint16_t port, const struct extra_selector *esel) esel->val); } -static void dump_regs(const struct superio_registers reg_table[], - int i, int j, uint16_t port, uint8_t ldn_sel) +static void dump_regs(const struct superio_registers_ldn *reg_table_ldn, + uint16_t port, uint8_t ldn_sel) { int k; + uint8_t reg_dumped[256] = {0}; const int16_t *idx, *def; - if (reg_table[i].ldn[j].ldn != NOLDN) { - printf("LDN 0x%02x", reg_table[i].ldn[j].ldn); - if (reg_table[i].ldn[j].name != NULL) - printf(" (%s)", reg_table[i].ldn[j].name); - regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn); + // The LDN selector will never be listed as register in the reg_table_ldn, + // yet it should not be displayed as "unknown register" in the dump. + reg_dumped[ldn_sel] = 1; + + if (reg_table_ldn->ldn != NOLDN) { + printf("LDN 0x%02x", reg_table_ldn->ldn); + if (reg_table_ldn->name != NULL) + printf(" (%s)", reg_table_ldn->name); + regwrite(port, ldn_sel, reg_table_ldn->ldn); } else { - if (reg_table[i].ldn[j].name == NULL) + if (reg_table_ldn->name == NULL) printf("Register dump:"); else - printf("(%s)", reg_table[i].ldn[j].name); + printf("(%s)", reg_table_ldn->name); } - set_extra_selector(port, ®_table[i].ldn[j].esel); + set_extra_selector(port, ®_table_ldn->esel); - idx = reg_table[i].ldn[j].idx; - def = reg_table[i].ldn[j].def; + idx = reg_table_ldn->idx; + def = reg_table_ldn->def; if (alternate_dump) { int skip_def = 0; @@ -143,6 +149,7 @@ static void dump_regs(const struct superio_registers reg_table[], } printf("0x%02x: ", idx[k]); + reg_dumped[idx[k]] = 1; val = regval(port, idx[k]); if (def[k] == NANA) @@ -158,6 +165,20 @@ static void dump_regs(const struct superio_registers reg_table[], printf("0x%02x [0x%02x]\n", def[k], val); } } + + if (dump_unknown_regs) { + int reg_begin = reg_table_ldn->ldn == NOLDN ? 0 : 0x30; + int reg_limit = reg_table_ldn->ldn == NOLDN ? 0x30 : 256; + for (int reg = reg_begin; reg < reg_limit; reg++) { + if (!reg_dumped[reg]) { + val = regval(port, reg); + if (val != 0x00 && val != 0xff) { + printf("0x%02x: ", reg); + printf(" 0x%02x\n", val); + } + } + } + } } else { printf("\nidx"); for (k = 0; idx[k] != EOT; k++) { @@ -195,6 +216,7 @@ void dump_superio(const char *vendor, uint16_t port, uint16_t id, uint8_t ldn_sel) { int i, j, no_dump_available = 1; + uint8_t ldn_dumped[256] = {0}; if (!dump) return; @@ -210,7 +232,22 @@ void dump_superio(const char *vendor, if (reg_table[i].ldn[j].ldn == EOT) break; no_dump_available = 0; - dump_regs(reg_table, i, j, port, ldn_sel); + ldn_dumped[reg_table[i].ldn[j].ldn] = 1; + dump_regs(®_table[i].ldn[j], port, ldn_sel); + } + + if (dump_unknown_ldns) { + for (int ldn = 0; ldn < 128; ldn++) { + if (!ldn_dumped[ldn]) { + const struct superio_registers_ldn fake_ldn = { + .ldn = ldn, + .name = "?", + .idx = {EOT}, + .def = {EOT} + }; + dump_regs(&fake_ldn, port, ldn_sel); + } + } } if (no_dump_available) @@ -309,6 +346,8 @@ int main(int argc, char *argv[]) {"dump", no_argument, NULL, 'd'}, {"extra-dump", no_argument, NULL, 'e'}, {"alternate-dump", no_argument, NULL, 'a'}, + {"unknown-regs", no_argument, NULL, 'u'}, + {"unknown-ldns", no_argument, NULL, 'U'}, {"list-supported", no_argument, NULL, 'l'}, {"verbose", no_argument, NULL, 'V'}, {"version", no_argument, NULL, 'v'}, @@ -316,12 +355,21 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "dealVvh", + while ((opt = getopt_long(argc, argv, "dealVvhuU", long_options, &option_index)) != EOF) { switch (opt) { case 'd': dump = 1; break; + case 'u': + dump_unknown_regs = 1; + alternate_dump = 1; // only works in alternate display mode + break; + case 'U': + dump_unknown_ldns = 1; + dump_unknown_regs = 1; // only makes sense when also dumping unknown regs + alternate_dump = 1; // only works in alternate display mode + break; case 'e': extra_dump = 1; break; diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1d41e120237..1f1620b831a 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -95,6 +95,11 @@ static __inline__ uint32_t inl(uint16_t port) -d | --dump Dump Super I/O register contents\n\ -e | --extra-dump Dump secondary registers too (e.g. EC registers)\n\ -a | --alternate-dump Use alternative dump format, more suitable for diff\n\ + -u | --unknown-regs Dump all registers in the known LDNs (displays only\n\ + those unequal to 0x00 and 0xff).\n\ + Implies --alternate-dump.\n\ + -U | --unknown-ldns Dump all registers in all LDNs, probing through all\n\ + of them. Implies --unknown-regs.\n\ -l | --list-supported Show the list of supported Super I/O chips\n\ -V | --verbose Verbose mode\n\ -v | --version Show the superiotool version\n\ @@ -143,7 +148,7 @@ struct extra_selector { struct superio_registers { int32_t superio_id; /* Signed, as we need EOT. */ const char *name; /* Super I/O name */ - struct { + struct superio_registers_ldn { int8_t ldn; const char *name; /* LDN name */ int16_t idx[IDXSIZE]; @@ -209,6 +214,10 @@ void print_infineon_chips(void); void probe_idregs_ite(uint16_t port); void print_ite_chips(void); +/* microchip.c */ +void probe_idregs_microchip(uint16_t port); +void print_microchip_chips(void); + /* nsc.c */ void probe_idregs_nsc(uint16_t port); void print_nsc_chips(void); @@ -237,16 +246,17 @@ static const struct { int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */ } superio_ports_table[] = { {probe_idregs_ali, {0x3f0, 0x370, EOT}}, - {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, + {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, {probe_idregs_exar, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x20e, 0x25e, 0x2e, 0x4e, 0x370, 0x6e, EOT}}, + {probe_idregs_microchip,{0x2e, 0x4e, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}}, /* I/O pairs on Nuvoton EC chips can be configured by firmware in * addition to the following hardware strapping options. */ - {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}}, + {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, #ifdef PCI_SUPPORT @@ -266,6 +276,7 @@ static const struct { {print_exar_chips}, {print_fintek_chips}, {print_ite_chips}, + {print_microchip_chips}, {print_nsc_chips}, {print_nuvoton_chips}, {print_smsc_chips},