diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index f43287226a..2e937856ce 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -86,6 +86,8 @@
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
 #define CPUID_ARROWLAKE_H_A0		0xc0652
+#define CPUID_ARROWLAKE_S_A0		0xc0660
+#define CPUID_ARROWLAKE_S_B0		0xc0662
 #define CPUID_PANTHERLAKE		0xc06c0
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d990b86a02..75a68a9743 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4527,6 +4527,7 @@
 #define PCI_DID_INTEL_MTL_P_GT2_5			0x7dd5
 #define PCI_DID_INTEL_ARL_H_GT2_1			0x7d51
 #define PCI_DID_INTEL_ARL_H_GT2_2			0x7dd1
+#define PCI_DID_INTEL_ARL_HX_GT2			0x7d67
 #define PCI_DID_INTEL_RPL_HX_GT1			0xa788
 #define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
 #define PCI_DID_INTEL_RPL_HX_GT3			0x4688
@@ -4689,6 +4690,9 @@
 #define PCI_DID_INTEL_MTL_P_ID_5		0x7d16
 #define PCI_DID_INTEL_ARL_H_ID_1		0x7d06
 #define PCI_DID_INTEL_ARL_H_ID_2		0x7d20
+#define PCI_DID_INTEL_ARL_HX_ID_1		0x7d1c
+#define PCI_DID_INTEL_ARL_HX_ID_2		0x7d2d
+#define PCI_DID_INTEL_ARL_HX_ID_3		0x7d2f
 #define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
 #define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
 #define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index 9b1f369cd6..f7b6323cac 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -26,6 +26,16 @@ config BOARD_SYSTEM76_MTL_COMMON
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_SYSTEM76_BONW16
+	select BOARD_SYSTEM76_MTL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_INTEL_DTBT
+	select EC_SYSTEM76_EC_DGPU
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_METEORLAKE_U_H # TODO: Arrow Lake-HX
+	select SOC_INTEL_ARROWLAKE_PCH_S
+
 config BOARD_SYSTEM76_DARP10
 	select BOARD_SYSTEM76_MTL_COMMON
 	select EC_SYSTEM76_EC_FAN2
@@ -74,6 +84,7 @@ config MAINBOARD_DIR
 	default "system76/mtl"
 
 config VARIANT_DIR
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
@@ -82,6 +93,7 @@ config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11
@@ -90,10 +102,12 @@ config MAINBOARD_PART_NUMBER
 	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Bonobo WS" if BOARD_SYSTEM76_BONW16
 	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B || BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_VERSION
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11
diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name
index b0e214e866..a149835710 100644
--- a/src/mainboard/system76/mtl/Kconfig.name
+++ b/src/mainboard/system76/mtl/Kconfig.name
@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_SYSTEM76_BONW16
+	bool "bonw16"
+
 config BOARD_SYSTEM76_DARP10
 	bool "darp10"
 
diff --git a/src/mainboard/system76/mtl/variants/bonw16/board.fmd b/src/mainboard/system76/mtl/variants/bonw16/board.fmd
new file mode 100644
index 0000000000..0e3414bf24
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 10472K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/mtl/variants/bonw16/board_info.txt b/src/mainboard/system76/mtl/variants/bonw16/board_info.txt
new file mode 100644
index 0000000000..563fb41418
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/board_info.txt
@@ -0,0 +1,2 @@
+Board name: bonw16
+Release year: 2025
diff --git a/src/mainboard/system76/mtl/variants/bonw16/data.vbt b/src/mainboard/system76/mtl/variants/bonw16/data.vbt
new file mode 100644
index 0000000000..835d8b3498
Binary files /dev/null and b/src/mainboard/system76/mtl/variants/bonw16/data.vbt differ
diff --git a/src/mainboard/system76/mtl/variants/bonw16/gpio.c b/src/mainboard/system76/mtl/variants/bonw16/gpio.c
new file mode 100644
index 0000000000..e8930f2c89
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/gpio.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+//TODO
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c b/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c
new file mode 100644
index 0000000000..3533dd8403
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+//TODO
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c b/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c
new file mode 100644
index 0000000000..3bf991b84b
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15585802, /* Subsystem ID */
+	13, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585802),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60120),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41a7932d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb b/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb
new file mode 100644
index 0000000000..2b95c326e4
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	device domain 0 on
+		subsystemid 0x1558 0x5802 inherit
+
+		# TODO
+    end
+end
diff --git a/src/mainboard/system76/mtl/variants/bonw16/ramstage.c b/src/mainboard/system76/mtl/variants/bonw16/ramstage.c
new file mode 100644
index 0000000000..3402756ea1
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/ramstage.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	//TODO: TCP USB-A conversion?
+
+	// XXX: Enabling C10 reporting causes system to constantly enter and
+	// exit opportunistic suspend when idle.
+	params->PchEspiHostC10ReportEnable = 0;
+}
diff --git a/src/mainboard/system76/mtl/variants/bonw16/romstage.c b/src/mainboard/system76/mtl/variants/bonw16/romstage.c
new file mode 100644
index 0000000000..4c35d9149d
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/bonw16/romstage.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x51
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x53,
+			},
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 12d9b95cbd..0b6c73112c 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -42,6 +42,8 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 14893869a0..39ee055a40 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -392,6 +392,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_P_GT2_5,
 	PCI_DID_INTEL_ARL_H_GT2_1,
 	PCI_DID_INTEL_ARL_H_GT2_2,
+	PCI_DID_INTEL_ARL_HX_GT2,
 	PCI_DID_INTEL_APL_IGD_HD_505,
 	PCI_DID_INTEL_APL_IGD_HD_500,
 	PCI_DID_INTEL_CNL_GT2_ULX_1,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 7ea802ae06..84114889ab 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -456,6 +456,9 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_MTL_P_ID_5,
 	PCI_DID_INTEL_ARL_H_ID_1,
 	PCI_DID_INTEL_ARL_H_ID_2,
+	PCI_DID_INTEL_ARL_HX_ID_1,
+	PCI_DID_INTEL_ARL_HX_ID_2,
+	PCI_DID_INTEL_ARL_HX_ID_3,
 	PCI_DID_INTEL_GLK_NB,
 	PCI_DID_INTEL_APL_NB,
 	PCI_DID_INTEL_CNL_ID_U,
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index da41b8df61..ecdc3039eb 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -71,7 +71,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
-	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ARROWLAKE_PCH_S
 	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
 	select SOC_INTEL_COMMON_BLOCK_IRQ
 	select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18
@@ -150,6 +150,11 @@ config SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
 	  silicon. Typically known as engineering samples (like ES). This type
 	  of the silicon are very common for early platform development.
 
+config SOC_INTEL_ARROWLAKE_PCH_S
+	bool
+	help
+	  Choose this option if your mainboard has an Arrow Lake PCH-S chipset.
+
 if SOC_INTEL_METEORLAKE
 
 config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT
@@ -171,7 +176,7 @@ config METEORLAKE_CAR_ENHANCED_NEM
 
 config MAX_CPUS
 	int
-	default 22
+	default 24
 
 config DCACHE_RAM_BASE
 	default 0xfef00000
@@ -201,6 +206,7 @@ config FSP_TEMP_RAM_SIZE
 
 config CHIPSET_DEVICETREE
 	string
+	default "soc/intel/meteorlake/chipset_pch_s.cb" if SOC_INTEL_ARROWLAKE_PCH_S
 	default "soc/intel/meteorlake/chipset.cb"
 
 config EXT_BIOS_WIN_BASE
@@ -239,14 +245,17 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config MAX_TBT_ROOT_PORTS
 	int
+	default 2 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 4
 
 config MAX_ROOT_PORTS
 	int
+	default 24 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 12
 
 config MAX_PCIE_CLOCK_SRC
 	int
+	default 14 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 9
 
 config SMM_TSEG_SIZE
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 4744abb2c7..5d8ee694ba 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -23,6 +23,8 @@ static struct {
 	{ CPUID_METEORLAKE_B0,   "MeteorLake B0" },
 	{ CPUID_METEORLAKE_C0,   "MeteorLake C0" },
 	{ CPUID_ARROWLAKE_H_A0,   "ArrowLake-H A0" },
+	{ CPUID_ARROWLAKE_S_A0,   "ArrowLake-S A0" },
+	{ CPUID_ARROWLAKE_S_B0,   "ArrowLake-S B0" },
 };
 
 static struct {
@@ -37,6 +39,9 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" },
 	{ PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" },
 	{ PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" },
+	{ PCI_DID_INTEL_ARL_HX_ID_1, "ArrowLake-HX (8+16)" },
+	{ PCI_DID_INTEL_ARL_HX_ID_2, "ArrowLake-HX (8+12)" },
+	{ PCI_DID_INTEL_ARL_HX_ID_3, "ArrowLake-HX (6+8)" },
 };
 
 static struct {
@@ -54,6 +59,38 @@ static struct {
 	{ PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" },
 	{ PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" },
 	{ PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_0, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_1, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_2, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_3, "ArrowLake-S Q870" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_4, "ArrowLake-S Z890" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_5, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_6, "ArrowLake-S B860" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_7, "ArrowLake-S H810" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_8, "ArrowLake-S W880" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_9, "ArrowLake-S W890" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_10, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_11, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_12, "ArrowLake-S HM870" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_13, "ArrowLake-S WM880" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_14, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_15, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_16, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_17, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_18, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_19, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_20, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_21, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_22, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_23, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_24, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_25, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_26, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_27, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_28, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_29, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_30, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_31, "ArrowLake-S PCH" },
 };
 
 static struct {
@@ -68,6 +105,7 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" },
 	{ PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" },
 	{ PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" },
+	{ PCI_DID_INTEL_ARL_HX_GT2, "ArrowLake-HX GT2" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index c32bb74ade..dd778cda09 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -46,6 +46,9 @@ struct ibecc_config {
 enum soc_intel_meteorlake_power_limits {
 	MTL_P_282_242_CORE,
 	MTL_P_682_482_CORE,
+	ARL_HX_8_16_55W_CORE,
+	ARL_HX_8_12_55W_CORE,
+	ARL_HX_6_8_55W_CORE,
 	MTL_POWER_LIMITS_COUNT
 };
 
@@ -54,6 +57,7 @@ enum soc_intel_meteorlake_cpu_tdps {
 	TDP_15W = 15,
 	TDP_28W = 28,
 	TDP_45W = 45,
+	TDP_55W = 55,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -69,6 +73,9 @@ static const struct {
 	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ARL_HX_ID_1, ARL_HX_8_16_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_ARL_HX_ID_2, ARL_HX_8_12_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_ARL_HX_ID_3, ARL_HX_6_8_55W_CORE, TDP_55W },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/meteorlake/chipset_pch_s.cb b/src/soc/intel/meteorlake/chipset_pch_s.cb
new file mode 100644
index 0000000000..14f3386138
--- /dev/null
+++ b/src/soc/intel/meteorlake/chipset_pch_s.cb
@@ -0,0 +1,229 @@
+chip soc/intel/meteorlake
+
+	device cpu_cluster 0 on end
+
+	register "power_limits_config[ARL_HX_8_16_55W_CORE]" = "{
+		.tdp_pl1_override = 55,
+		.tdp_pl2_override = 160,
+		.tdp_pl4 = 266,
+	}"
+
+	register "power_limits_config[ARL_HX_8_12_55W_CORE]" = "{
+		.tdp_pl1_override = 55,
+		.tdp_pl2_override = 144,
+		.tdp_pl4 = 257,
+	}"
+
+	register "power_limits_config[ARL_HX_6_8_55W_CORE]" = "{
+		.tdp_pl1_override = 55,
+		.tdp_pl2_override = 108,
+		.tdp_pl4 = 204,
+	}"
+
+	# Reduce the size of BasicMemoryTests to speed up the boot time.
+	register "lower_basic_mem_test_size" = "true"
+
+	# The power state current threshold is defined in 1/4 A
+	# increments. A value of 400 = 100A.
+	register "ps_cur_2_threshold[VR_DOMAIN_SA]" = "40" # 10A
+
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
+	register "common_soc_config.pch_thermal_trip" = "130"
+
+	# Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
+	register "tcc_offset" = "20"
+
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"
+
+	device domain 0 on
+		device pci 00.0 alias system_agent on end
+		device pci 01.0 alias pcie_rp12 off end
+		device pci 02.0 alias igpu off end
+		device pci 04.0 alias dtt off end
+		device pci 05.0 alias ipu off end
+		device pci 06.0 alias pcie_rp13 off end
+		device pci 06.1 alias pcie_rp10 off end
+		device pci 06.3 alias pcie_rp14 off end
+		device pci 06.4 alias pcie_rp15 off end
+		device pci 07.0 alias tbt_pcie_rp0 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 0 on end
+			end
+		end
+		device pci 07.1 alias tbt_pcie_rp1 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 1 on end
+			end
+		end
+		device pci 08.0 alias gna off end
+		device pci 0a.0 alias crashlog on end
+		device pci 0b.0 alias vpu off end
+		device pci 0d.0 alias tcss_xhci off
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias tcss_root_hub off
+					chip drivers/usb/acpi
+						device usb 3.0 alias tcss_usb3_port0 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias tcss_usb3_port1 off end
+					end
+				end
+			end
+		end
+		device pci 0d.1 alias tcss_xdci off end
+		device pci 0d.2 alias tcss_dma0 off end
+		device pci 0e.0 alias vmd off end
+		device pci 10.0 alias thc0 off end
+		device pci 10.1 alias thc1 off end
+		device pci 12.0 alias ish off end
+		device pci 12.6 alias gspi2 off end
+		#TODO: conflict between gspi3 and ioe_p2sb
+		#TODO device pci 13.0 alias gspi3 off end
+		device pci 13.0 alias ioe_p2sb hidden end
+		device pci 13.1 alias uart3 off end
+		device pci 13.2 alias pmc2 hidden end
+		device pci 13.3 alias ioe_shared_sram off end
+		#TODO: conflict between soc_s_shared_sram and xhci!
+		#TODO device pci 14.0 alias soc_s_shared_sram off end
+		device pci 14.0 alias xhci off
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.8 alias usb2_port9 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.9 alias usb2_port10 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.a alias usb2_port11 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.b alias usb2_port12 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.c alias usb2_port13 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.d alias usb2_port14 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias usb3_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias usb3_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 alias usb3_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.5 alias usb3_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.6 alias usb3_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.7 alias usb3_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.8 alias usb3_port9 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.9 alias usb3_port10 off end
+					end
+				end
+			end
+		end
+		device pci 14.1 alias usb_otg off end
+		device pci 14.2 alias pmc_shared_sram off end
+		device pci 14.3 alias cnvi_wifi off end
+		device pci 15.0 alias i2c0 off end
+		device pci 15.1 alias i2c1 off end
+		device pci 15.2 alias i2c2 off end
+		device pci 15.3 alias i2c3 off end
+		device pci 15.4 alias i3c off end
+		device pci 16.0 alias heci1 on end
+		device pci 16.1 alias heci2 off end
+		device pci 16.4 alias heci3 off end
+		device pci 16.5 alias heci4 off end
+		device pci 17.0 alias sata off end
+		device pci 18.0 alias eheci1 off end
+		device pci 18.1 alias eheci2 off end
+		device pci 18.2 alias eheci3 off end
+		device pci 19.0 alias i2c4 off end
+		device pci 19.1 alias i2c5 off end
+		device pci 19.2 alias uart2 off end
+		device pci 1b.0 alias pcie_rp17 off end
+		device pci 1b.1 alias pcie_rp18 off end
+		device pci 1b.2 alias pcie_rp19 off end
+		device pci 1b.3 alias pcie_rp20 off end
+		device pci 1b.4 alias pcie_rp21 off end
+		device pci 1b.5 alias pcie_rp22 off end
+		device pci 1b.6 alias pcie_rp23 off end
+		device pci 1b.7 alias pcie_rp24 off end
+		device pci 1c.0 alias pcie_rp1 off end
+		device pci 1c.1 alias pcie_rp2 off end
+		device pci 1c.2 alias pcie_rp3 off end
+		device pci 1c.3 alias pcie_rp4 off end
+		device pci 1c.4 alias pcie_rp5 off end
+		device pci 1c.5 alias pcie_rp6 off end
+		device pci 1c.6 alias pcie_rp7 off end
+		device pci 1c.7 alias pcie_rp8 off end
+		device pci 1d.0 alias pcie_rp9 off end
+		device pci 1d.1 alias pcie_rp10 off end
+		device pci 1d.2 alias pcie_rp11 off end
+		device pci 1d.3 alias pcie_rp12 off end
+		device pci 1d.4 alias pcie_rp13 off end
+		device pci 1d.5 alias pcie_rp14 off end
+		device pci 1d.6 alias pcie_rp15 off end
+		device pci 1d.7 alias pcie_rp16 off end
+		device pci 1e.0 alias uart0 off end
+		device pci 1e.1 alias uart1 off end
+		device pci 1e.2 alias gspi0 off end
+		device pci 1e.3 alias gspi1 off end
+		device pci 1f.0 alias soc_espi on end
+		device pci 1f.1 alias p2sb hidden end
+		device pci 1f.2 alias pmc hidden end
+		device pci 1f.3 alias hda off end
+		device pci 1f.4 alias smbus off end
+		device pci 1f.5 alias fast_spi on end
+		device pci 1f.6 alias gbe off end
+		device pci 1f.7 alias npk off end
+	end
+end
diff --git a/src/soc/intel/meteorlake/include/soc/gpio.h b/src/soc/intel/meteorlake/include/soc/gpio.h
index 50a33a585e..3cd5c3a73c 100644
--- a/src/soc/intel/meteorlake/include/soc/gpio.h
+++ b/src/soc/intel/meteorlake/include/soc/gpio.h
@@ -3,11 +3,17 @@
 #ifndef _SOC_METEORLAKE_GPIO_H_
 #define _SOC_METEORLAKE_GPIO_H_
 
+#if CONFIG(SOC_INTEL_ARROWLAKE_PCH_S)
+#include <soc/gpio_defs_pch_s.h>
+#define CROS_GPIO_NAME		"INTC1084"
+#define CROS_GPIO_DEVICE_NAME	"INTC1084:00"
+#else
 #include <soc/gpio_defs.h>
-#include <intelblocks/gpio.h>
-
 #define CROS_GPIO_NAME		"INTC1083"
 #define CROS_GPIO_DEVICE_NAME	"INTC1083:00"
+#endif
+
+#include <intelblocks/gpio.h>
 
 /* Enable GPIO community power management configuration */
 #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \