From 38604d2b05885a24842db17eba618540a82f84b7 Mon Sep 17 00:00:00 2001 From: Yehonatan Avrahimi <48332126+yontank@users.noreply.github.com> Date: Mon, 24 Nov 2025 21:47:05 +0200 Subject: [PATCH 1/5] BUG: Detect Initial PC invalid input Fixes #47 --- src/context/SimulationContext.tsx | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/context/SimulationContext.tsx b/src/context/SimulationContext.tsx index 79406de..3a9b478 100644 --- a/src/context/SimulationContext.tsx +++ b/src/context/SimulationContext.tsx @@ -144,6 +144,15 @@ export function SimulationContextProvider({ children }: Props) { const startSimulation = () => { if (editorRef.current == undefined) throw Error("Undefined Reference to the editor") + + if (initialPC.length == 0 || initialPC === "0x") { + toast.error("Empty Initial PC", { + position: "bottom-left", + description: "Please enter a value inside the initial PC input bar.", + }) + return + } + const value = editorRef.current.getValue() const r = assemble(value, Number(initialPC)) From 564daf2de38b7256cf9102b6ad8531fa3c2ca86a Mon Sep 17 00:00:00 2001 From: Yehonatan Avrahimi <48332126+yontank@users.noreply.github.com> Date: Sun, 30 Nov 2025 00:01:46 +0200 Subject: [PATCH 2/5] WIP: began work on exam presets data --- src/context/SimulationContext.tsx | 2 +- src/data/exams/2021.ts | 41 ++++++++++++++++ src/data/exams/2022.ts | 78 +++++++++++++++++++++++++++++++ src/data/exams/2023.ts | 21 +++++++++ src/data/exams/2024.ts | 67 ++++++++++++++++++++++++++ src/data/exams/2025.ts | 65 ++++++++++++++++++++++++++ src/data/exams/types.ts | 29 ++++++++++++ 7 files changed, 302 insertions(+), 1 deletion(-) create mode 100644 src/data/exams/2021.ts create mode 100644 src/data/exams/2022.ts create mode 100644 src/data/exams/2023.ts create mode 100644 src/data/exams/2024.ts create mode 100644 src/data/exams/2025.ts create mode 100644 src/data/exams/types.ts diff --git a/src/context/SimulationContext.tsx b/src/context/SimulationContext.tsx index 3a9b478..085feb6 100644 --- a/src/context/SimulationContext.tsx +++ b/src/context/SimulationContext.tsx @@ -22,7 +22,7 @@ import { } from "react" import { toast } from "sonner" -type PlacedNode = { +export type PlacedNode = { /** * The X coordinate of the node on the diagram. */ diff --git a/src/data/exams/2021.ts b/src/data/exams/2021.ts new file mode 100644 index 0000000..67a8b66 --- /dev/null +++ b/src/data/exams/2021.ts @@ -0,0 +1,41 @@ +import type { SimulationTemplate } from "./types" + +export const Exams2021: Record = { + //TODO: this exam uses a modified diagram (signExtend is replaced with shift left 16) + "a-83": { + /** Note: This exam sets its register values as UNKNOWN. */ + PCAddr: 0x07700024, + code: "addi $16,$0,0x44\nsw $17,-0x4($16)\nadd $20,$16,$19\nsub $12,$16,$20\nand $19,$17,$20", + registerInit: [ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + ], + placedNodes: {}, + lineExecution: 2, + }, + + "a-89": { + PCAddr: 0x2855738c, + code: "lw $11, 256($8)\nadd $7,$11,$11\nsub $9,$7,$12\nsw $9,0(16$)\nbeq $7,$11,0x00000000", + registerInit: [ + 0, 48, 96, 144, 192, 240, 288, 336, 384, 432, 480, 528, 576, 624, 672, + 720, 768, 816, 864, 912, 960, 1008, 1056, 1104, 1152, 1200, 1248, 1296, + 1344, 1392, 1440, 1488, + ], + memoryInit: (address) => (address < 1000 ? -address : 0), + lineExecution: 1, + }, + + "c-83": { + PCAddr: 0x02d0005c, + code: "add $6, $7, $8\nlw $6,100($6)\nsub $10,$2,$6\nor $5, $7,$8", + registerInit: [ + 0, 3145728, 6291456, 9437184, 12582912, 15728640, 18874368, 22020096, + 25165824, 28311552, 31457280, 34603008, 37748736, 40894464, 44040192, + 47185920, 50331648, 53477376, 56623104, 59768832, 62914560, 66060288, + 69206016, 72351744, 75497472, 78643200, 81788928, 84934656, 88080384, + 91226112, 94371840, 97517568, + ], + lineExecution: 2, + }, +} diff --git a/src/data/exams/2022.ts b/src/data/exams/2022.ts new file mode 100644 index 0000000..9f28be4 --- /dev/null +++ b/src/data/exams/2022.ts @@ -0,0 +1,78 @@ +import { makeShifter } from "@/logic/nodeTypes/shift" +import type { SimulationTemplate } from "./types" + +export const Exams2021: Record = { + "a-82": { + PCAddr: 0x0000300c, + code: "sw $10,-0x100(10$)\naddi $10,$10,4\nadd $9,$10,$8\nlw $5,-0x100($10)\nor $3,$5,$10", + registerInit: [ + 0, 1904, 3808, 5712, 7616, 9520, 11424, 13328, 15232, 17136, 19040, 20944, + 22848, 24752, 26656, 28560, 30464, 32368, 34272, 36176, 38080, 39984, + 41888, 43792, 45696, 47600, 49504, 51408, 53312, 55216, 57120, 59024, + ], + placedNodes: { + "alu-in0": { + x: 673, + y: 406, + nodeType: makeShifter("right", 1), + }, + }, + lineExecution: 1, + }, + + "a-62": { + PCAddr: 0xad4aff00, + code: "sw $10,-0x100(10$)\naddi $10,$10,4\nadd $9,$10,$8\nlw $5,-0x100(10$)\nor $3,$5,$10", + registerInit: [ + 0, 1904, 3808, 5712, 7616, 9520, 11424, 13328, 15232, 17136, 19040, 20944, + 22848, 24752, 26656, 28560, 30464, 32368, 34272, 36176, 38080, 39984, + 41888, 43792, 45696, 47600, 49504, 51408, 53312, 55216, 57120, 59024, + ], + lineExecution: 1, + }, + + /** NOTE: Register Values Unknown. */ + "a-75": { + PCAddr: 0x00400000, + code: "addi $16,$0,10\nlw $11,32(16$)\nor $7,$16,$11\nsub $9,$7,$11\nsw $9,4(16$)\n", + registerInit: [ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + ], + placedNodes: { + "muxMemToReg-in0": { + x: 987, + y: 644, + nodeType: makeShifter("left", 5), + }, + }, + memoryInit: (address) => (address < 125 ? 0x3d3d3d : 0), + lineExecution: 3, + }, + + "c-65": { + PCAddr: 0x000020f4, + code: "and $13,$7,$8\nlw $10,0x100($6)\nor $12,$6,$10\nbeq $6,$12,2,0xfffffffc", + registerInit: [ + 0, 1536, 3072, 4608, 6144, 7680, 9216, 10752, 12288, 13824, 15360, 16896, + 18432, 19968, 21504, 23040, 24576, 26112, 27648, 29184, 30720, 32256, + 33792, 35328, 36864, 38400, 39936, 41472, 43008, 44544, 46080, 47616, + ], + lineExecution: 2, + }, + "c-92": { + /** + * TODO: Modified PC to PC+8 + all shiftLeft2 replaced with shiftLeft3 + * + */ + PCAddr: 0x00002000, + code: "sub $9,$8,$9\naddi $8,$9,0x100\naddi $8,$9,0x100\nbeq $1,$2,0x00000005\nlw $9,0x100($8)\nslt $1,$2,$1\nadd $17,$15,$9\nor $2,$6,$11\nsub $10,$4,$9", + registerInit: [ + 0, 272, 288, 304, 320, 336, 352, 368, 384, 400, 416, 432, 448, 464, 480, + 496, 512, 528, 544, 560, 576, 592, 608, 624, 640, 656, 672, 688, 704, 720, + 736, 752, + ], + memoryInit: (address) => (address < 0x1000 * 4 ? address / 4 : 0), + lineExecution: 5, + }, +} diff --git a/src/data/exams/2023.ts b/src/data/exams/2023.ts new file mode 100644 index 0000000..7ca1abc --- /dev/null +++ b/src/data/exams/2023.ts @@ -0,0 +1,21 @@ +import type { SimulationTemplate } from "./types" + +export const Exams2023: Record = { + // TODO: this exam uses a modified diagram (branchImmediateAdder becomes a Sub) + "a-89": { + PCAddr: 0x00aa889c, + code: "lw $9, 0x400($16)\nadd $12,$17,$9\nsub $10,$12,$9\nbeq $9,$8,0xfffffffe", + registerInit: [ + 0, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, + 960, 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, + 1728, 1792, 1856, 1920, 1984, + ], + memoryInit: (address) => (address < 0x1000 ? address : 0), + lineExecution: 1, + }, + + // This exam changes too many things for us to implement, so we'll ignore it for now + // "a-57": { + + // } +} diff --git a/src/data/exams/2024.ts b/src/data/exams/2024.ts new file mode 100644 index 0000000..211e2de --- /dev/null +++ b/src/data/exams/2024.ts @@ -0,0 +1,67 @@ +import { not } from "@/logic/nodeTypes/not" +import type { SimulationTemplate } from "./types" +import { makeShifter } from "@/logic/nodeTypes/shift" + +export const Exams2024: Record = { + "c-93": { + PCAddr: 0xaa573818, + code: "ori $9,$30,0x4000\n lw $9,0x100($18)\nor $4,$9,$9 \nslt $5,$8,$6 \n", + registerInit: [ + 0, 592, 1184, 1776, 2368, 2960, 3552, 4144, 4736, 5328, 5920, 6512, 7104, + 7696, 8288, 8880, 9472, 10064, 10656, 11248, 11840, 12432, 13024, 13616, + 14208, 14800, 15392, 15984, 16576, 17168, 17760, 18352, + ], + placedNodes: { + "registers-readRegister1": { + x: 409, + y: 383, + nodeType: makeShifter("rightLogical", 1), + }, + }, + memoryInit: (address) => + address < 2500 + ? 0xdededede + : address < 5000 + ? 0xfcfcfcfc + : address < 7500 + ? 0x575757 + : 0, + lineExecution: 3, + }, + + "a-91": { + PCAddr: 0x0acd8080, + code: "add $2,$2,$2 \nsub $2,$2,$1\nlw $3,0x2000($2)\n sub $30,$3,$2", + registerInit: [ + 0, 4194304, 8388608, 12582912, 16777216, 20971520, 25165824, 29360128, + 33554432, 37748736, 41943040, 46137344, 50331648, 54525952, 58720256, + 62914560, 67108864, 71303168, 75497472, 79691776, 83886080, 88080384, + 92274688, 96468992, 100663296, 104857600, 109051904, 113246208, 117440512, + 121634816, 125829120, 130023424, + ], + placedNodes: { + "splitterReadData2-in": { + x: 661, + y: 468, + nodeType: makeShifter("left", 3), + }, + }, + lineExecution: 2, + }, + + "c-84": { + PCAddr: 0x00001020, + code: "and $5,$4,$4\nor $9,$3,$3\nlw $5,0x1024($9)\nsw $5,0x1028($9)\nslt $9,$5,$3", + registerInit: [ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + ], + placedNodes: { + "alu-in0": { + x: 673, + y: 406, + nodeType: not, + }, + }, + }, +} diff --git a/src/data/exams/2025.ts b/src/data/exams/2025.ts new file mode 100644 index 0000000..f5256b9 --- /dev/null +++ b/src/data/exams/2025.ts @@ -0,0 +1,65 @@ +import { makeShifter } from "@/logic/nodeTypes/shift" +import type { SimulationTemplate } from "./types" +import { not } from "@/logic/nodeTypes/not" +import { neg } from "@/logic/nodeTypes/neg" + +export const Exams2025: Record = { + "a-94": { + PCAddr: 0x0000bf70, + code: "nop\nadd $4,$12,$6\nlw $4,-128($8)\naddi $4,$4,-128\nsw $6,-128($4)", + registerInit: [ + 0, 4096, 8192, 12288, 16384, 20480, 24576, 28672, 32768, 36864, 40960, + 45056, 49152, 53248, 57344, 61440, 65536, 69632, 73728, 77824, 81920, + 86016, 90112, 94208, 98304, 102400, 106496, 110592, 114688, 118784, + 122880, 126976, + ], + placedNodes: { + "registers-readRegister1": { + x: 409, + y: 383, + nodeType: makeShifter("rightLogical", 1), + }, + }, + lineExecution: 4, + }, + + "a-81": { + PCAddr: 0xaa00bb08, + code: "sub $9,$9,$8\nori $9,$9,0x88\nlw $1,0x200($9)\nadd $2,$1,$8\nslt $2,$7,$4", + registerInit: [ + 0, 128, 256, 384, 512, 640, 768, 896, 1024, 1152, 1280, 1408, 1536, 1664, + 1792, 1920, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, + 3328, 3456, 3584, 3712, 3840, 3968, + ], + placedNodes: { + "registers-writeData": { + x: 1033, + y: 701, + nodeType: not + }, + }, + memoryInit: (address) => + address < 0x400 + ? 0x17171717 + : address < 0x800 + ? 0x23232323 + : address < 0xc00 + ? 0xfefefefe + : 0, + lineExecution: 5, + }, + + "a-87": { + PCAddr: 0x00004af4, + code: "addi $3,$0,-2816\nsw $3,0x4000($3)\nlw $2,19200($0)\nslt $4,$3,$2", + registerInit: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], + placedNodes: { + "muxMemToReg-in0": { + x: 1046, + y: 648, + nodeType: neg + } + }, + lineExecution: 3 + } +} diff --git a/src/data/exams/types.ts b/src/data/exams/types.ts new file mode 100644 index 0000000..6c78332 --- /dev/null +++ b/src/data/exams/types.ts @@ -0,0 +1,29 @@ +import type { PlacedNode } from "@/context/SimulationContext" +import type { InputID } from "@/logic/simulation" + +export type SimulationTemplate = { + /** + * The address of the first instruction in the code. + */ + PCAddr: number + /** + * The assembly code. + */ + code: string + /** + * An optional function that, given an address (of a word), returns the value at that address. + */ + memoryInit?: (address: number) => number + /** + * Initial values of all registers. + */ + registerInit: number[] + /** + * Additional nodes that are placed on the diagram. + */ + placedNodes?: Record + /** + * The line that the question asks to examine (probably unused) + */ + lineExecution?: number +} From 7e9b95d855177a553f991ad0598f5632f3409275 Mon Sep 17 00:00:00 2001 From: yontank Date: Mon, 1 Dec 2025 00:15:36 +0200 Subject: [PATCH 3/5] BugFix: make sure PC Address is divisible by 4 --- src/context/SimulationContext.tsx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/context/SimulationContext.tsx b/src/context/SimulationContext.tsx index 085feb6..89796c7 100644 --- a/src/context/SimulationContext.tsx +++ b/src/context/SimulationContext.tsx @@ -145,7 +145,7 @@ export function SimulationContextProvider({ children }: Props) { if (editorRef.current == undefined) throw Error("Undefined Reference to the editor") - if (initialPC.length == 0 || initialPC === "0x") { + if (isNaN(parseInt(initialPC))) { toast.error("Empty Initial PC", { position: "bottom-left", description: "Please enter a value inside the initial PC input bar.", From a0ccefb21889f5d9d1f736c9359d9b4b50526d68 Mon Sep 17 00:00:00 2001 From: yontank Date: Mon, 1 Dec 2025 00:16:06 +0200 Subject: [PATCH 4/5] refactor: Make initialpc on invalud number error handle edgecases --- src/context/SimulationContext.tsx | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/context/SimulationContext.tsx b/src/context/SimulationContext.tsx index 89796c7..ffdac42 100644 --- a/src/context/SimulationContext.tsx +++ b/src/context/SimulationContext.tsx @@ -153,6 +153,15 @@ export function SimulationContextProvider({ children }: Props) { return } + if(parseInt(initialPC) % 4 != 0){ + toast.error("PC Address must be divisible by 4", { + position: "bottom-left", + description: "all MIPS addresses must be divisible by 4.", + }) + + return; + } + const value = editorRef.current.getValue() const r = assemble(value, Number(initialPC)) From 5f66ddd71a1fb5f4d44108d32052228a3c782bda Mon Sep 17 00:00:00 2001 From: yontank Date: Mon, 1 Dec 2025 00:16:40 +0200 Subject: [PATCH 5/5] BUG: Detect Initial PC invalid input Fixes #47 --- src/context/SimulationContext.tsx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/context/SimulationContext.tsx b/src/context/SimulationContext.tsx index ffdac42..a2f1ec0 100644 --- a/src/context/SimulationContext.tsx +++ b/src/context/SimulationContext.tsx @@ -152,7 +152,7 @@ export function SimulationContextProvider({ children }: Props) { }) return } - + if(parseInt(initialPC) % 4 != 0){ toast.error("PC Address must be divisible by 4", { position: "bottom-left",