Add complete bank support for CMIS transceivers

This PR extends the bank parameter support introduced in PR #632 to
fully enable multi-bank CMIS transceiver support throughout the stack.

Changes include:

1. **Memory Map Bank Awareness**:
   - Updated CmisFlatMemMap, CmisMemMap, and CCmisMemMap to accept bank parameter
   - Implemented bank-aware getaddr() method in CmisFlatMemMap that correctly
     calculates linear offsets using the formula from sonic-linux-kernel PR #473
   - Added bank property to CmisFlatMemMap for read-only access
   - Added constants: CMIS_EEPROM_PAGE_SIZE, CMIS_NUM_NON_BANKED_PAGES,
     CMIS_NUM_BANKED_PAGES, CMIS_ARCH_PAGES
   - Uses unified formula: linear_offset = (bank * CMIS_ARCH_PAGES + page) * page_size + offset
   - Each bank is treated as a full 256-page (32KB) architectural block for proper alignment

2. **API Factory Updates**:
   - Added bank parameter to create_xcvr_api() and _create_cmis_api()
   - Updated CMIS API instantiation to pass bank parameter to memory maps
   - Modified id_mapping to pass bank parameter for all CMIS module types
     (0x18, 0x19, 0x1b, 0x1e)

3. **SfpBase Integration**:
   - Updated refresh_xcvr_api() to pass bank parameter when creating xcvr_api

4. **Field Definitions**:
   - Added BANKS_SUPPORTED_FIELD constant to consts.py
   - Added BanksSupported field to MODULE_CHAR_ADVT in CmisMemMap

This enables proper support for CMIS modules with multiple memory banks,
allowing correct EEPROM access across all banks as defined in the CMIS
specification. The offset calculation formula matches the optoe kernel
driver implementation in sonic-linux-kernel PR #473.

Signed-off-by: Bobby McGonigle <bobby@nexthop.ai>

Author: bobby-nexthop

sonic_platform_base/sfp_base.py

@@ -473,7 +473,7 @@ def refresh_xcvr_api(self):
         """
         Updates the XcvrApi associated with this SFP
         """
-        self._xcvr_api = self._xcvr_api_factory.create_xcvr_api()
+        self._xcvr_api = self._xcvr_api_factory.create_xcvr_api(bank=self.bank)
 
     def get_xcvr_api(self):
         """

sonic_platform_base/sonic_xcvr/fields/consts.py

@@ -182,6 +182,7 @@
 MODULE_PWRDN_DURATION = "ModulePowerDownDuration"
 DP_TX_TURNON_DURATION = "DPTxTurnOnDuration"
 DP_TX_TURNOFF_DURATION = "DPTxTurnOffDuration"
+BANKS_SUPPORTED_FIELD = "BanksSupported"
 
 # DOM
 TRANS_DOM_FIELD = "TransceiverDom"

sonic_platform_base/sonic_xcvr/mem_maps/public/c_cmis.py

@@ -12,8 +12,8 @@
 from .cmis import CmisMemMap
 
 class CCmisMemMap(CmisMemMap):
-    def __init__(self, codes):
-        super(CCmisMemMap, self).__init__(codes)
+    def __init__(self, codes, bank=0):
+        super(CCmisMemMap, self).__init__(codes, bank=bank)
 
         self.MODULE_CONFIG_SUPPORT = RegGroupField(consts.MODULE_CONFIG_SUPPORT_FIELD,
             NumberRegField(consts.SUPPORT_GRID, self.getaddr(0x4, 128)),

sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py

@@ -19,11 +19,18 @@
 from ...fields.consts import *
 from ...fields.public.cmis import CableLenField
 
+# Constants matching optoe driver
+CMIS_EEPROM_PAGE_SIZE = 128
+CMIS_NUM_NON_BANKED_PAGES = 16   # pages 00h-0Fh
+CMIS_NUM_BANKED_PAGES = 240      # pages 10h-FFh
+CMIS_ARCH_PAGES = 256            # architectural pages per bank (matches OPTOE_ARCH_PAGES)
+
 class CmisFlatMemMap(XcvrMemMap):
     """
     Memory map for CMIS flat memory (Lower page and Upper page 0h ONLY)
     """
-    def __init__(self, codes):
+    def __init__(self, codes, bank=0):
+        self._bank = bank
         super(CmisFlatMemMap, self).__init__(codes)
 
         self.MGMT_CHARACTERISTICS = RegGroupField(consts.MGMT_CHAR_FIELD,
@@ -138,12 +145,41 @@ def __init__(self, codes):
             NumberRegField(consts.MODULE_LEVEL_CONTROL, self.getaddr(0x0, 26), size=1, ro=False),
         )
 
+    @property
+    def bank(self):
+        """Returns the bank number (read-only)."""
+        return self._bank
+
     def getaddr(self, page, offset, page_size=128):
-        return page * page_size + offset
+        """
+        Calculate linear offset for optoe driver using instance's bank.
+
+        For lower memory (page 0, offset < 128):
+            linear_offset = offset
+
+        For paged memory:
+            offset_in_paged_area = (page * page_size + offset) - 128
+            bytes_per_bank = CMIS_ARCH_PAGES * page_size  (256 * 128 = 32KB)
+            linear_offset = 128 + (bank * bytes_per_bank) + offset_in_paged_area
+
+        Simplified:
+            linear_offset = (bank * CMIS_ARCH_PAGES + page) * page_size + offset
+
+        Note: Each bank is treated as a full 256-page (32KB) architectural block,
+        even though only pages 10h-FFh (240 pages) are actually banked. This ensures
+        proper alignment and matches the kernel driver behavior.
+        """
+        if page == 0 and offset < 128:
+            # Lower memory - not affected by banking
+            return offset
+
+        # For all paged memory (including bank 0), use the unified formula
+        # that treats each bank as a 256-page (32KB) block
+        return (self.bank * CMIS_ARCH_PAGES + page) * page_size + offset
 
 class CmisMemMap(CmisFlatMemMap):
-    def __init__(self, codes):
-        super(CmisMemMap, self).__init__(codes)
+    def __init__(self, codes, bank=0):
+        super(CmisMemMap, self).__init__(codes, bank=bank)
 
         # This memmap should contain ONLY upper page >= 01h fields
         self.ADVERTISING = RegGroupField(consts.ADVERTISING_FIELD,
@@ -227,6 +263,9 @@ def __init__(self, codes):
                 RegBitField(consts.VDM_SUPPORTED, 6),
                 RegBitField(consts.DIAG_PAGE_SUPPORT_ADVT_FIELD, 5),
             ),
+            NumberRegField(consts.BANKS_SUPPORTED_FIELD, self.getaddr(0x1, 142),
+                *(RegBitField("Bit%d" % bit, bit) for bit in range(0, 2))
+            ),
             NumberRegField(consts.TX_INPUT_EQ_MAX, self.getaddr(0x1, 153),
                 *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4))
             ),
@@ -702,6 +741,3 @@ def __init__(self, codes):
         )
 
         # TODO: add remaining fields
-
-    def getaddr(self, page, offset, page_size=128):
-        return page * page_size + offset

sonic_platform_base/sonic_xcvr/xcvr_api_factory.py

@@ -75,7 +75,7 @@ def _get_vendor_part_num(self):
        vendor_pn = part_num.decode('utf-8', errors='ignore')
        return vendor_pn.strip()
 
-    def _create_cmis_api(self):
+    def _create_cmis_api(self, bank=0):
         api = None
         vendor_name = self._get_vendor_name()
         vendor_pn = self._get_vendor_part_num()
@@ -86,10 +86,10 @@ def _create_cmis_api(self):
              ('EOPTOLINK' in vendor_name and vendor_pn in EOP_800G_VENDOR_PN_LIST):
             api = self._create_api(CmisCodes, CmisMemMap, CmisFr800gApi)
         else:
-            xcvr_eeprom = XcvrEeprom(self.reader, self.writer, CmisMemMap(CmisCodes))
+            xcvr_eeprom = XcvrEeprom(self.reader, self.writer, CmisMemMap(CmisCodes, bank=bank))
             api = CmisApi(xcvr_eeprom, init_cdb_fw_handler=True)
             if api.is_coherent_module():
-                xcvr_eeprom = XcvrEeprom(self.reader, self.writer, CCmisMemMap(CmisCodes))
+                xcvr_eeprom = XcvrEeprom(self.reader, self.writer, CCmisMemMap(CmisCodes, bank=bank))
                 api = CCmisApi(xcvr_eeprom, init_cdb_fw_handler=True)
         return api
 
@@ -109,18 +109,18 @@ def _create_api(self, codes_class, mem_map_class, api_class):
         xcvr_eeprom = XcvrEeprom(self.reader, self.writer, mem_map)
         return api_class(xcvr_eeprom)
 
-    def create_xcvr_api(self):
+    def create_xcvr_api(self, bank=0):
         id = self._get_id()
 
         # Instantiate various Optics implementation based upon their respective ID as per SFF8024
         id_mapping = {
             0x03: (self._create_api, (Sff8472Codes, Sff8472MemMap, Sff8472Api)),
             0x0D: (self._create_qsfp_api, ()),
             0x11: (self._create_api, (Sff8636Codes, Sff8636MemMap, Sff8636Api)),
-            0x18: (self._create_cmis_api, ()),
-            0x19: (self._create_cmis_api, ()),
-            0x1b: (self._create_cmis_api, ()),
-            0x1e: (self._create_cmis_api, ()),
+            0x18: (self._create_cmis_api, (bank,)),
+            0x19: (self._create_cmis_api, (bank,)),
+            0x1b: (self._create_cmis_api, (bank,)),
+            0x1e: (self._create_cmis_api, (bank,)),
             0x7e: (self._create_api, (AmphBackplaneCodes,
                                      AmphBackplaneMemMap, AmphBackplaneImpl)),
         }