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s390x: add nnp-assist intrinsics
Because `qemu` does not support these (yet), I haven't added any runtime tests
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crates/core_arch/src/s390x/vector.rs

Lines changed: 74 additions & 0 deletions
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@@ -281,6 +281,12 @@ unsafe extern "unadjusted" {
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#[link_name = "llvm.s390.vfenezbs"] fn vfenezbs(a: i8x16, b: i8x16) -> PackedTuple<i8x16, i32>;
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#[link_name = "llvm.s390.vfenezhs"] fn vfenezhs(a: i16x8, b: i16x8) -> PackedTuple<i16x8, i32>;
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#[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
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#[link_name = "llvm.s390.vclfnhs"] fn vclfnhs(a: vector_signed_short, immarg: i32) -> vector_float;
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#[link_name = "llvm.s390.vclfnls"] fn vclfnls(a: vector_signed_short, immarg: i32) -> vector_float;
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#[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short;
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#[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short;
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#[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short;
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}
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impl_neg! { i8x16 : 0 }
@@ -5873,6 +5879,74 @@ pub unsafe fn vec_promote<T: sealed::VectorPromote>(a: T::ElementType, b: i32) -
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T::vec_promote(a, b)
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}
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/// Converts the left-most half of `a` to a vector of single-precision numbers.
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/// The format of the source vector elements is specified by `B`.
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#[inline]
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#[target_feature(enable = "nnp-assist")]
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#[cfg_attr(test, assert_instr(vclfnh, IMM2 = 0))]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_extend_to_fp32_hi<const B: i32>(a: vector_signed_short) -> vector_float {
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// On processors implementing the IBM z16 architecture, only the value 0 is supported.
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static_assert_uimm_bits!(B, 0);
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vclfnhs(a, B)
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}
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/// Converts the right-most half of `a` to a vector of single-precision numbers.
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/// The format of the source vector elements is specified by `B`.
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#[inline]
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#[target_feature(enable = "nnp-assist")]
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#[cfg_attr(test, assert_instr(vclfnl, B = 0))]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_extend_to_fp32_lo<const B: i32>(a: vector_signed_short) -> vector_float {
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// On processors implementing the IBM z16 architecture, only the value 0 is supported.
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static_assert_uimm_bits!(B, 0);
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vclfnls(a, B)
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}
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/// Converts the elements of vector `a` to the 16-bit IEEE floating point format.
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/// The format of the source vector elements is specified by `B`.
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#[inline]
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#[target_feature(enable = "nnp-assist")]
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#[cfg_attr(test, assert_instr(vcfn, B = 0))]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_convert_to_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
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// On processors implementing the IBM z16 architecture, only the value 0 is supported.
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static_assert_uimm_bits!(B, 0);
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vcfn(a, B)
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}
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/// Converts the elements of vector `a` to an internal floating point format.
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/// The format of the target vector elements is specified by `B`.
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#[inline]
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#[target_feature(enable = "nnp-assist")]
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#[cfg_attr(test, assert_instr(vcnf, B = 0))]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_convert_from_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
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// On processors implementing the IBM z16 architecture, only the value 0 is supported.
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static_assert_uimm_bits!(B, 0);
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vcnf(a, B)
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}
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/// Converts the elements of single-precision vectors `a` and `b` to an internal floating point
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/// format with 16-bit sized elements. The format of the target vector elements is specified by `C`.
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#[inline]
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#[target_feature(enable = "nnp-assist")]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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#[cfg_attr(test, assert_instr(vcrnf, C = 0))]
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pub unsafe fn vec_round_from_fp32<const C: i32>(
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a: vector_float,
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b: vector_float,
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) -> vector_signed_short {
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// On processors implementing the IBM z16 architecture, only the value 0 is supported.
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static_assert_uimm_bits!(C, 0);
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vcrnfs(a, b, C)
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}
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#[cfg(test)]
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mod tests {
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use super::*;

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