Decode HSR in HVC handler.

Author: jonathanpallant

aarch32-cpu/src/register/armv8r/hsr.rs

@@ -2,11 +2,64 @@
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
+use arbitrary_int::u25;
+
 /// HSR (*Hyp Syndrome Register*)
-#[derive(Debug, Copy, Clone)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
+pub struct Hsr {
+    /// Exception Class.
+    ///
+    /// Indicates the reason for the exception that this register holds
+    /// information about.
+    #[bits(26..=31, rw)]
+    ec: Option<ExceptionClass>,
+    /// Instruction length bit.
+    ///
+    /// Indicates the size of the instruction that has been trapped to Hyp mode.
+    #[bit(25, rw)]
+    il: InstructionLength,
+    /// Instruction Specific Syndrome.
+    ///
+    /// Architecturally, this field can be defined independently for each
+    /// defined Exception class. However, in practice, some ISS encodings are
+    /// used for more than one Exception class.
+    #[bits(0..=24, rw)]
+    iss: u25,
+}
+
+#[bitbybit::bitenum(u6, exhaustive = false)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
-pub struct Hsr(pub u32);
+#[derive(Debug, PartialEq, Eq)]
+pub enum ExceptionClass {
+    Unknown = 0b00_0000,
+    TrappedWfiWfe = 0b00_0001,
+    TrappedCp15McrMrc = 0b00_0011,
+    TrappedCp15McrrMrrc = 0b00_0100,
+    TrappedCp14McrMrc = 0b00_0101,
+    TrappedLdcStc = 0b00_0110,
+    TrappedFpu = 0b00_0111,
+    TrappedVmrs = 0b00_1000,
+    TrappedCp14McrrMrrc = 0b00_1100,
+    IllegalAArch32Eret = 0b00_1110,
+    Svc = 0b01_0001,
+    Hvc = 0b01_0010,
+    Smc = 0b01_0011,
+    PrefetchAbortFromLower = 0b10_0000,
+    PrefetchAbortFromCurrent = 0b10_0001,
+    PcAlignment = 0b10_0010,
+    DataAbortFromLower = 0b10_0100,
+    DataAbortFromCurrent = 0b10_0101,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+#[derive(Debug, PartialEq, Eq)]
+pub enum InstructionLength {
+    SixteenBit = 0b0,
+    ThirtyTwoBit = 0b1,
+}
 
 impl SysReg for Hsr {
     const CP: u32 = 15;
@@ -22,7 +75,7 @@ impl Hsr {
     #[inline]
     /// Reads HSR (*Hyp Syndrome Register*)
     pub fn read() -> Hsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
@@ -37,7 +90,7 @@ impl Hsr {
     /// Ensure that this value is appropriate for this register
     pub unsafe fn write(value: Self) {
         unsafe {
-            <Self as SysRegWrite>::write_raw(value.0);
+            <Self as SysRegWrite>::write_raw(value.raw_value());
         }
     }
 }

examples/mps3-an536/reference/hvc-a32-armv8r-none-eabihf.out

@@ -1,4 +1,4 @@
 x = 1, y = 2, z = 3.000
-In hvc_handler, with HSR=0x4a00abcd, frame=Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
+In hvc_handler, with Hsr { ec: Ok(Hvc), il: ThirtyTwoBit, iss: 0000abcd }, Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
 Got 12345678
 x = 1, y = 2, z = 3.000

examples/mps3-an536/reference/hvc-a32-thumbv8r-none-eabihf.out

@@ -1,4 +1,4 @@
 x = 1, y = 2, z = 3.000
-In hvc_handler, with HSR=0x4a00abcd, frame=Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
+In hvc_handler, with Hsr { ec: Ok(Hvc), il: ThirtyTwoBit, iss: 0000abcd }, Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
 Got 12345678
 x = 1, y = 2, z = 3.000

examples/mps3-an536/reference/hvc-t32-armv8r-none-eabihf.out

@@ -1,4 +1,4 @@
 x = 1, y = 2, z = 3.000
-In hvc_handler, with HSR=0x4a00abcd, frame=Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
+In hvc_handler, with Hsr { ec: Ok(Hvc), il: ThirtyTwoBit, iss: 0000abcd }, Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
 Got 12345678
 x = 1, y = 2, z = 3.000

examples/mps3-an536/reference/hvc-t32-thumbv8r-none-eabihf.out

@@ -1,4 +1,4 @@
 x = 1, y = 2, z = 3.000
-In hvc_handler, with HSR=0x4a00abcd, frame=Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
+In hvc_handler, with Hsr { ec: Ok(Hvc), il: ThirtyTwoBit, iss: 0000abcd }, Frame { r0: 10000000, r1: 10000001, r2: 10000002, r3: 10000003, r4: 10000004, r5: 10000005 }
 Got 12345678
 x = 1, y = 2, z = 3.000

examples/mps3-an536/src/bin/hvc-a32.rs

@@ -24,11 +24,9 @@ fn main() -> ! {
 
 /// This is our HVC exception handler
 #[exception(HypervisorCall)]
-fn hvc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 {
-    println!(
-        "In hvc_handler, with HSR=0x{:08x}, frame={:08x?}",
-        arg, frame
-    );
+fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
+    let hsr = aarch32_cpu::register::Hsr::new_with_raw_value(hsr);
+    println!("In hvc_handler, with {:08x?}, {:08x?}", hsr, frame);
     return 0x12345678;
 }
 

examples/mps3-an536/src/bin/hvc-t32.rs

@@ -24,11 +24,9 @@ fn main() -> ! {
 
 /// This is our HVC exception handler
 #[exception(HypervisorCall)]
-fn hvc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 {
-    println!(
-        "In hvc_handler, with HSR=0x{:08x}, frame={:08x?}",
-        arg, frame
-    );
+fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
+    let hsr = aarch32_cpu::register::Hsr::new_with_raw_value(hsr);
+    println!("In hvc_handler, with {:08x?}, {:08x?}", hsr, frame);
     return 0x12345678;
 }