Don't rely on CPSR contents.

thejpster · thejpster · commit 7f0a85b969df · 2026-01-02T22:10:52.000Z
You can't depend on the flags because they vary depending on what the
machine code does.
diff --git a/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out
@@ -3,8 +3,8 @@ Creating GIC driver @ 0xf0000000 / 0xf0100000
 Calling git.setup(0)
 Configure Timer Interrupt...
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
   > IRQ
     - Timer fired, resetting
   < IRQ
diff --git a/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out
@@ -3,8 +3,8 @@ Creating GIC driver @ 0xf0000000 / 0xf0100000
 Calling git.setup(0)
 Configure Timer Interrupt...
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
   > IRQ
     - Timer fired, resetting
   < IRQ
diff --git a/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=0 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs
@@ -44,11 +44,11 @@ fn main() -> ! {
     );
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     let mut count: u32 = 0;
     loop {
@@ -63,9 +63,9 @@ fn main() -> ! {
     }
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[irq]
diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs
@@ -80,11 +80,11 @@ fn main() -> ! {
     });
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -109,9 +109,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 /// Handles the low-prio SGI
diff --git a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
@@ -61,11 +61,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -90,9 +90,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[irq]
diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
@@ -58,11 +58,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -87,9 +87,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[unsafe(link_section = ".irq_entries")]
diff --git a/examples/mps3-an536/src/bin/gic-unified-irq.rs b/examples/mps3-an536/src/bin/gic-unified-irq.rs
@@ -58,11 +58,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -87,9 +87,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[irq]
