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micprogmicprog
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Fix lint and formatting
1 parent 8881796 commit 5e00485

3 files changed

Lines changed: 35 additions & 32 deletions

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‎src/geared_memory_island.sv‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ module geared_memory_island #(
4444

4545
parameter bit InternalCombRspReq = 1'b1,
4646

47+
// verilog_lint: waive explicit-parameter-storage-type
4748
parameter MemorySimInit = "none",
4849

4950
// Derived, DO NOT OVERRIDE
@@ -174,8 +175,8 @@ module geared_memory_island #(
174175
.data_o ( narrow_mem_req_geared[i] )
175176
);
176177

177-
for (genvar j = 0; j < GearRatio; j++) begin
178-
localparam id = i*GearRatio + j;
178+
for (genvar j = 0; j < GearRatio; j++) begin : gen_narrow_gearing_inner
179+
localparam int unsigned id = i*GearRatio + j;
179180
assign narrow_req_entry_geared [id] = narrow_req_geared [i][j];
180181
assign narrow_gnt_geared [i][j] = narrow_gnt_entry_geared [id];
181182
assign narrow_addr_entry_geared [id] = narrow_mem_req_geared [i][j].addr;
@@ -259,8 +260,8 @@ module geared_memory_island #(
259260
.data_o ( wide_mem_req_geared[i] )
260261
);
261262

262-
for (genvar j = 0; j < GearRatio; j++) begin
263-
localparam id = i*GearRatio + j;
263+
for (genvar j = 0; j < GearRatio; j++) begin : gen_wide_gearing_inner
264+
localparam int unsigned id = i*GearRatio + j;
264265
assign wide_req_entry_geared [id] = wide_req_geared [i][j];
265266
assign wide_gnt_geared [i][j] = wide_gnt_entry_geared [id];
266267
assign wide_addr_entry_geared [id] = wide_mem_req_geared [i][j].addr;

‎src/geared_stream_collect.sv‎

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -25,42 +25,44 @@ module geared_stream_collect #(
2525
input logic [GearRatio-1:0] selected_reg_i
2626
);
2727

28-
if (GearRatio < 1) begin
28+
if (GearRatio < 1) begin : gen_ratio_0_err
2929
$fatal(1, "Gear Ratio < 1 not supported!");
30-
end else if (GearRatio == 1) begin
30+
end else if (GearRatio == 1) begin : gen_ratio_1
3131
assign valid_o = valid_i;
3232
assign ready_o = ready_i;
33-
assign data_o = data_i;
34-
end else begin
33+
assign data_o = data_i;
34+
end else begin : gen_ratio_n
3535
logic last_cycle_in_gear;
3636

3737
logic [GearRatio-1:0] valid_in_d, valid_in_q;
3838
logic [GearRatio-1:0] ready_out_d, ready_out_q, ready_out_tmp;
3939

40-
T [GearRatio-1:0] data_out;
40+
T [ GearRatio-1:0] data_out;
4141
logic [$clog2(GearRatio)-1:0] sel_reg;
4242

4343
assign valid_o = |(valid_in_q & selected_reg_i);
4444

4545
onehot_to_bin #(
4646
.ONEHOT_WIDTH(GearRatio)
4747
) i_selected_reg (
48-
.onehot ( selected_reg_i ),
49-
.bin ( sel_reg )
48+
.onehot(selected_reg_i),
49+
.bin (sel_reg)
5050
);
51-
assign data_o = data_out[sel_reg];
51+
assign data_o = data_out[sel_reg];
5252

5353
assign ready_o = ready_out_q | ready_out_tmp;
5454

55-
for (genvar i = 0; i < GearRatio; i++) begin
55+
for (genvar i = 0; i < GearRatio; i++) begin : gen_gearing
5656

57-
assign valid_in_d[i] = last_cycle_in_gear ? valid_i[i] : 1'b0;
58-
assign ready_out_d[i] = last_cycle_in_gear ? 1'b0 : (ready_out_tmp | ready_out_q);
57+
assign valid_in_d[i] = last_cycle_in_gear ? valid_i[i] : 1'b0;
58+
assign ready_out_d[i] = last_cycle_in_gear ? 1'b0 : (ready_out_tmp | ready_out_q);
5959
assign ready_out_tmp[i] = selected_reg_i == i ? ready_i : 1'b0;
6060

6161
`FFLARNC(ready_out_q[i], ready_out_d[i], 1'b1, clr_i, 1'b0, clk_i, rst_ni)
62-
`FFLARNC(valid_in_q[i], valid_in_d[i], last_cycle_in_gear || (selected_reg_i[i] && ready_i), clr_i, 1'b0, clk_i, rst_ni)
63-
`FFLARNC(data_out[i], data_i[i], last_cycle_in_gear & valid_i[i] & ready_o[i], clr_i, '0, clk_i, rst_ni)
62+
`FFLARNC(valid_in_q[i], valid_in_d[i], last_cycle_in_gear || (selected_reg_i[i] && ready_i),
63+
clr_i, 1'b0, clk_i, rst_ni)
64+
`FFLARNC(data_out[i], data_i[i], last_cycle_in_gear & valid_i[i] & ready_o[i], clr_i, '0,
65+
clk_i, rst_ni)
6466
end
6567
end
6668

‎src/geared_stream_split.sv‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@ module geared_stream_split #(
1010
parameter int unsigned GearRatio = 1,
1111
parameter type T = logic // Vivado requires a default value for type parameters.
1212
) (
13-
input logic clk_i, // Clock
14-
input logic geared_clk_i, // Geared Clock
15-
input logic rst_ni, // Asynchronous active-low reset
16-
input logic clr_i, // Synchronous clear
13+
input logic clk_i, // Clock
14+
input logic geared_clk_i, // Geared Clock
15+
input logic rst_ni, // Asynchronous active-low reset
16+
input logic clr_i, // Synchronous clear
1717
// Input port
1818
input logic valid_i,
1919
output logic ready_o,
@@ -25,32 +25,32 @@ module geared_stream_split #(
2525
output T [GearRatio-1:0] data_o
2626
);
2727

28-
if (GearRatio < 1) begin
28+
if (GearRatio < 1) begin : gen_ratio_0_err
2929
$fatal(1, "Gear Ratio < 1 not supported!");
30-
end else if (GearRatio == 1) begin
31-
assign valid_o = valid_i;
32-
assign ready_o = ready_i;
33-
assign data_o = data_i;
30+
end else if (GearRatio == 1) begin : gen_ratio_1
31+
assign valid_o = valid_i;
32+
assign ready_o = ready_i;
33+
assign data_o = data_i;
3434
assign selected_reg_o = 1'b1;
35-
end else begin
35+
end else begin : gen_ration_n
3636
logic [GearRatio-1:0] reg_active_d, reg_active;
3737
logic [GearRatio-1:0] ready_out;
3838
logic [GearRatio-1:0] reg_ena;
3939

4040
// reg_active is high for one cycle for each position during a full geared_clk cycle
4141
assign reg_active_d[GearRatio-1:1] = reg_active[GearRatio-2:0];
42-
assign reg_active_d[0] = reg_active[GearRatio-1];
42+
assign reg_active_d[0] = reg_active[GearRatio-1];
4343

44-
`FF(reg_active, reg_active_d, {{(GearRatio-1){1'b0}}, 1'b1}, clk_i, rst_ni)
44+
`FF(reg_active, reg_active_d, {{(GearRatio - 1) {1'b0}}, 1'b1}, clk_i, rst_ni)
4545

4646
assign selected_reg_o = reg_active;
4747

48-
assign ready_o = |ready_out;
48+
assign ready_o = |ready_out;
4949

50-
for (genvar i = 0; i < GearRatio; i++) begin
50+
for (genvar i = 0; i < GearRatio; i++) begin : gen_gearing
5151

5252
assign ready_out[i] = (ready_i[i] | ~valid_o[i]) & reg_active[i];
53-
assign reg_ena[i] = valid_i & ready_out[i];
53+
assign reg_ena[i] = valid_i & ready_out[i];
5454

5555
// only active once during each geared_clk cycle
5656
`FFLARNC(valid_o[i], valid_i, ready_out[i], clr_i, 1'b0, clk_i, rst_ni)

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