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micprogmicprog
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WIP: add rready wrap
1 parent 024aba6 commit 58f7575

2 files changed

Lines changed: 335 additions & 12 deletions

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‎src/geared_memory_island.sv‎

Lines changed: 111 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,8 @@ module geared_memory_island #(
4242
parameter int unsigned SpillReqBank = 0,
4343
parameter int unsigned SpillRspBank = 0,
4444

45+
parameter bit InternalCombRspReq = 1'b1,
46+
4547
parameter MemorySimInit = "none",
4648

4749
// Derived, DO NOT OVERRIDE
@@ -94,6 +96,7 @@ module geared_memory_island #(
9496
logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_req_geared;
9597
logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_gnt_geared;
9698
logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_rvalid_geared;
99+
logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_rready_geared;
97100
logic [NumNarrowReq-1:0][GearRatio-1:0][NarrowDataWidth-1:0] narrow_rdata_geared;
98101

99102
logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_selected;
@@ -107,10 +110,16 @@ module geared_memory_island #(
107110
logic [GearRatio*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata_entry_geared;
108111
logic [GearRatio*NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb_entry_geared;
109112
logic [GearRatio*NumNarrowReq-1:0] narrow_rvalid_entry_geared;
113+
logic [GearRatio*NumNarrowReq-1:0] narrow_rready_entry_geared;
110114
logic [GearRatio*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata_entry_geared;
111115

112116
wide_mem_req_t [NumWideReq-1:0] wide_mem_req;
113117
wide_mem_req_t [NumWideReq-1:0][GearRatio-1:0] wide_mem_req_geared;
118+
logic [NumWideReq-1:0][GearRatio-1:0] wide_req_geared;
119+
logic [NumWideReq-1:0][GearRatio-1:0] wide_gnt_geared;
120+
logic [NumWideReq-1:0][GearRatio-1:0] wide_rvalid_geared;
121+
logic [NumWideReq-1:0][GearRatio-1:0] wide_rready_geared;
122+
logic [NumWideReq-1:0][GearRatio-1:0][WideDataWidth-1:0] wide_rdata_geared;
114123

115124
logic [GearRatio* NumWideReq-1:0] wide_req_entry_geared;
116125
logic [GearRatio* NumWideReq-1:0] wide_gnt_entry_geared;
@@ -119,6 +128,7 @@ module geared_memory_island #(
119128
logic [GearRatio* NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata_entry_geared;
120129
logic [GearRatio* NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb_entry_geared;
121130
logic [GearRatio* NumWideReq-1:0] wide_rvalid_entry_geared;
131+
logic [GearRatio* NumWideReq-1:0] wide_rready_entry_geared;
122132
logic [GearRatio* NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata_entry_geared;
123133

124134
clk_int_div #(
@@ -166,14 +176,15 @@ module geared_memory_island #(
166176

167177
for (genvar j = 0; j < GearRatio; j++) begin
168178
localparam id = i*GearRatio + j;
169-
assign narrow_req_entry_geared [id] = narrow_req_geared [i][j];
170-
assign narrow_gnt_geared [i][j] = narrow_gnt_entry_geared [id];
171-
assign narrow_addr_entry_geared [id] = narrow_mem_req_geared [i][j].addr;
172-
assign narrow_we_entry_geared [id] = narrow_mem_req_geared [i][j].we;
173-
assign narrow_wdata_entry_geared[id] = narrow_mem_req_geared [i][j].wdata;
174-
assign narrow_strb_entry_geared [id] = narrow_mem_req_geared [i][j].strb;
175-
assign narrow_rvalid_geared [i][j] = narrow_rvalid_entry_geared[id];
176-
assign narrow_rdata_geared [i][j] = narrow_rdata_entry_geared [id];
179+
assign narrow_req_entry_geared [id] = narrow_req_geared [i][j];
180+
assign narrow_gnt_geared [i][j] = narrow_gnt_entry_geared [id];
181+
assign narrow_addr_entry_geared [id] = narrow_mem_req_geared [i][j].addr;
182+
assign narrow_we_entry_geared [id] = narrow_mem_req_geared [i][j].we;
183+
assign narrow_wdata_entry_geared [id] = narrow_mem_req_geared [i][j].wdata;
184+
assign narrow_strb_entry_geared [id] = narrow_mem_req_geared [i][j].strb;
185+
assign narrow_rvalid_geared [i][j] = narrow_rvalid_entry_geared[id];
186+
assign narrow_rready_entry_geared[id] = narrow_rready_geared [i][j];
187+
assign narrow_rdata_geared [i][j] = narrow_rdata_entry_geared [id];
177188
end
178189

179190
onehot_to_bin #(
@@ -191,7 +202,7 @@ module geared_memory_island #(
191202
.clk_i,
192203
.rst_ni,
193204
.flush_i ('0),
194-
.testmode_i(),
205+
.testmode_i('0),
195206
.full_o (),
196207
.empty_o (),
197208
.usage_o (),
@@ -211,19 +222,103 @@ module geared_memory_island #(
211222
.clr_i ('0),
212223

213224
.valid_i ( narrow_rvalid_geared [i] ),
214-
.ready_o (), // This is a problem... -> fix it
225+
.ready_o ( narrow_rready_geared [i] ),
215226
.data_i ( narrow_rdata_geared [i] ),
216227

217228
.valid_o ( narrow_rvalid_o [i] ),
218229
.ready_i ( 1'b1 ),
219230
.data_o ( narrow_rdata_o [i] ),
220-
.selected_reg_i( 1<<narrow_selected_out[i]),
231+
.selected_reg_i( 1<<narrow_selected_out[i] ),
221232
);
222233
end
223234

235+
for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_gearing
236+
assign wide_mem_req[i] = '{
237+
addr: wide_addr_i [i],
238+
we: wide_we_i [i],
239+
wdata: wide_wdata_i [i],
240+
strb: wide_strb_i [i]
241+
};
242+
243+
geared_stream_split #(
244+
.GearRatio ( GearRatio ),
245+
.T ( wide_mem_req_t )
246+
) i_gear_split (
247+
.clk_i,
248+
.geared_clk_i ( geared_clk ),
249+
.rst_ni,
250+
.clr_i ( '0 ),
251+
252+
.valid_i ( wide_req_i [i] ),
253+
.ready_o ( wide_gnt_o [i] ),
254+
.data_i ( wide_mem_req [i] ),
255+
.selected_reg_o ( wide_selected [i] ),
224256

257+
.valid_o ( wide_req_geared [i] ),
258+
.ready_i ( wide_gnt_geared [i] ),
259+
.data_o ( wide_mem_req_geared[i] )
260+
);
225261

226-
memory_island_core #(
262+
for (genvar j = 0; j < GearRatio; j++) begin
263+
localparam id = i*GearRatio + j;
264+
assign wide_req_entry_geared [id] = wide_req_geared [i][j];
265+
assign wide_gnt_geared [i][j] = wide_gnt_entry_geared [id];
266+
assign wide_addr_entry_geared [id] = wide_mem_req_geared [i][j].addr;
267+
assign wide_we_entry_geared [id] = wide_mem_req_geared [i][j].we;
268+
assign wide_wdata_entry_geared [id] = wide_mem_req_geared [i][j].wdata;
269+
assign wide_strb_entry_geared [id] = wide_mem_req_geared [i][j].strb;
270+
assign wide_rvalid_geared [i][j] = wide_rvalid_entry_geared[id];
271+
assign wide_rready_entry_geared[id] = wide_rready_geared [i][j];
272+
assign wide_rdata_geared [i][j] = wide_rdata_entry_geared [id];
273+
end
274+
275+
onehot_to_bin #(
276+
.ONEHOT_WIDTH ( GearRatio )
277+
) i_gear_to_bin (
278+
.onehot ( wide_selected [i] ),
279+
.bin ( wide_selected_bin[i] )
280+
);
281+
282+
fifo_v3 #(
283+
.FALL_THROUGH(1'b0),
284+
.DATA_WIDTH ($clog2(GearRatio)),
285+
.DEPTH () // TODO: NumOutstanding * GearRatio
286+
) i_selection_fifo (
287+
.clk_i,
288+
.rst_ni,
289+
.flush_i ('0),
290+
.testmode_i('0),
291+
.full_o (),
292+
.empty_o (),
293+
.usage_o (),
294+
.data_i ( wide_selected_bin[i] ),
295+
.push_i ( |wide_selected [i] ),
296+
.data_o ( wide_selected_out[i] ),
297+
.pop_i ( wide_rvalid_o [i] )
298+
);
299+
300+
geared_stream_collect #(
301+
.GearRatio ( GearRatio ),
302+
.T ( logic [WideDataWidth-1:0] )
303+
) i_gear_collect (
304+
.clk_i,
305+
.geared_clk_i ( geared_clk ),
306+
.rst_ni,
307+
.clr_i ('0),
308+
309+
.valid_i ( wide_rvalid_geared [i] ),
310+
.ready_o ( wide_rready_geared [i] ),
311+
.data_i ( wide_rdata_geared [i] ),
312+
313+
.valid_o ( wide_rvalid_o [i] ),
314+
.ready_i ( 1'b1 ),
315+
.data_o ( wide_rdata_o [i] ),
316+
.selected_reg_i( 1<<wide_selected_out[i] ),
317+
);
318+
end
319+
320+
321+
memory_island_core_rready_wrap #(
227322
.AddrWidth ( AddrWidth ),
228323
.NarrowDataWidth ( NarrowDataWidth ),
229324
.WideDataWidth ( WideDataWidth ),
@@ -248,6 +343,8 @@ module geared_memory_island #(
248343
.SpillReqBank ( SpillReqBank ),
249344
.SpillRspBank ( SpillRspBank ),
250345

346+
.CombRspReq ( InternalCombRspReq ),
347+
251348
.MemorySimInit ( MemorySimInit )
252349
) i_memory_island_core (
253350
.clk_i ( geared_clk ),
@@ -259,6 +356,7 @@ module geared_memory_island #(
259356
.narrow_wdata_i ( narrow_wdata_entry_geared ),
260357
.narrow_strb_i ( narrow_strb_entry_geared ),
261358
.narrow_rvalid_o ( narrow_rvalid_entry_geared ),
359+
.narrow_rready_i ( narrow_rready_entry_geared ),
262360
.narrow_rdata_o ( narrow_rdata_entry_geared ),
263361
.wide_req_i ( wide_req_entry_geared ),
264362
.wide_gnt_o ( wide_gnt_entry_geared ),
@@ -267,6 +365,7 @@ module geared_memory_island #(
267365
.wide_wdata_i ( wide_wdata_entry_geared ),
268366
.wide_strb_i ( wide_strb_entry_geared ),
269367
.wide_rvalid_o ( wide_rvalid_entry_geared ),
368+
.wide_rready_i ( wide_rready_entry_geared ),
270369
.wide_rdata_o ( wide_rdata_entry_geared )
271370
);
272371

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