mpy-vreg.patch

From caa5430c35ec318ee4c1af1fa2225a40bfa1da8e Mon Sep 17 00:00:00 2001
From: "David (Pololu)" <dev-david@pololu.com>
Date: Tue, 27 Jan 2026 10:56:36 -0800
Subject: [PATCH] rp2/clocks_extra: Set VREG like the SDK does: needed for 200
 MHz.

The RP2040 now supports running at 200 MHz, but the datasheet says
that speed requires an elevated core supply of 1.15 V.  The SDK
implements that in runtime_clocks_init, but we do not call that
function because we override it in clocks_extra.c.

Signed-off-by: David (Pololu) <dev-david@pololu.com>
---
 ports/rp2/clocks_extra.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/ports/rp2/clocks_extra.c b/ports/rp2/clocks_extra.c
index ab3e6261f..db3643975 100644
--- a/ports/rp2/clocks_extra.c
+++ b/ports/rp2/clocks_extra.c
@@ -14,6 +14,7 @@
 #include "hardware/irq.h"
 #include "hardware/gpio.h"
 #include "hardware/ticks.h"
+#include "hardware/vreg.h"
 
 #if PICO_RP2040
 // The RTC clock frequency is 48MHz divided by power of 2 (to ensure an integer
@@ -86,6 +87,13 @@ void runtime_init_clocks_optional_usb(bool init_usb) {
         XOSC_HZ,
         XOSC_HZ);
 
+    #if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
+    if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
+        vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
+        busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
+    }
+    #endif
+
     /// \tag::configure_clk_sys[]
     // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz
     clock_configure(clk_sys,
-- 
2.52.0