test.sus

module fp_test {
    clock clk
    input float a
    input float b
    input float c
    output float d
    
    fp32_add add
    
    fp32_mul mul
   
    float tmp = add(a, b)
    d = mul(tmp, c)
}


module ComputeRoots {
    action compute_roots'0 : float a'0, float b'0, float c'0 {
        trigger roots_valid : float root_1, float root_2

        float half_b = fp32_mul_pow2(b, -1)

        float discriminant = fp32_sub(fp32_mul(half_b, half_b), fp32_mul(a, c))
        float discr_sqrt = fp32_sqrt(discriminant)

        float a_recip = fp32_rcp(a)
        float half_b_neg = fp32_neg(half_b)
        when fp32_ge(discriminant, 0.0) {
            float r1 = fp32_mul(fp32_add(half_b_neg, discr_sqrt), a_recip)
            float r2 = fp32_mul(fp32_sub(half_b_neg, discr_sqrt), a_recip)
            roots_valid(r1, r2)
        }
    }
}