From 56946dc657991d98dcb14a83fc5c14bfd87904df Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Mon, 9 Feb 2026 21:59:10 -0500 Subject: [PATCH] Adjust UART fifo backpressure thresholds- We really want to assert backpressure *before* we're full Change where we do the resizing for clarity --- hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd | 2 +- hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd | 2 +- hdl/ip/vhd/espi/txn_layer/response_processor.vhd | 2 +- .../cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd | 4 ++-- .../cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd | 4 +++- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd index 4f8b538a..afac2f4e 100644 --- a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd +++ b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd @@ -25,7 +25,7 @@ package uart_channel_pkg is type uart_resp_t is record st : st_uart_t; - avail_bytes : std_logic_vector(11 downto 0); + avail_bytes : std_logic_vector(12 downto 0); end record; view uart_resp_src of uart_resp_t is diff --git a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd index faf43e98..9c9f9e74 100644 --- a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd +++ b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd @@ -102,7 +102,7 @@ begin -- tx_rusedwds is potentially cycles behind the empty flag due to fifo latencies. -- since we're using it in the avail bytes, we need to ensure we're at least > 0 sp_to_host_espi.st.valid <= '1' when tx_rempty /= '1' and tx_rusedwds > 0 else '0'; - sp_to_host_espi.avail_bytes <= resize(tx_rusedwds, sp_to_host_espi.avail_bytes'length); + sp_to_host_espi.avail_bytes <= tx_rusedwds; to_sp_uart_valid <= not rx_rempty; fifo_read_by_espi <= sp_to_host_espi.st.valid and sp_to_host_espi.st.ready; diff --git a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd index 4771a13e..7dcabe82 100644 --- a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd +++ b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd @@ -125,7 +125,7 @@ begin -- to get this working well we're going to cap the payload at 61 bytes -- we can re-evaluate this later, but this will support the smallest OOB channel -- with 3 bytes of SMB headers - response_chan_mux.length <= minimum(sp_to_host_espi.avail_bytes, 61); -- cap to tx max + response_chan_mux.length <= resize(minimum(sp_to_host_espi.avail_bytes, 61), response_chan_mux.length'length); -- cap to tx max flash_resp.ready <= '0'; resp_data <= sp_to_host_espi.st.data; sp_to_host_espi.st.ready <= '1' when data_to_host.ready = '1' and r.cur_valid = '1' and r.state = RESPONSE_PAYLOAD else '0'; diff --git a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd index c333f58a..644d5273 100644 --- a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd +++ b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd @@ -133,7 +133,7 @@ begin parity => false, use_hw_handshake => true, fifo_depth => CONSOLE_FIFO_DEPTH, - full_threshold => CONSOLE_FIFO_DEPTH + full_threshold => CONSOLE_FIFO_ALMOST_FULL ) port map( clk => clk, @@ -180,7 +180,7 @@ begin parity => false, use_hw_handshake => true, fifo_depth => IPCC_FIFO_DEPTH, - full_threshold => IPCC_FIFO_DEPTH + full_threshold => IPCC_FIFO_ALMOST_FULL ) port map( clk => clk, diff --git a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd index c4cfd9de..0d8b7662 100644 --- a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd +++ b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd @@ -13,7 +13,9 @@ use work.calc_pkg.all; package sp5_uart_subsystem_pkg is constant CONSOLE_FIFO_DEPTH : integer := 256; -- FIFO depth for UARTs - constant IPCC_FIFO_DEPTH : integer := 16; -- FIFO depth for IPCC UART + constant CONSOLE_FIFO_ALMOST_FULL : integer := CONSOLE_FIFO_DEPTH - 8; -- Threshold for "almost full" status signal + constant IPCC_FIFO_DEPTH : integer := 32; -- FIFO depth for IPCC UART + constant IPCC_FIFO_ALMOST_FULL : integer := IPCC_FIFO_DEPTH - 8; -- Threshold for "almost full" status signal -- To the debug interface type console_uart_dbg_t is record