Adjust UART fifo backpressure thresholds-

We really want to assert backpressure *before* we're  full

Author: nathanaelhuffman

hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd

@@ -133,7 +133,7 @@ begin
         parity => false,
         use_hw_handshake => true,
         fifo_depth => CONSOLE_FIFO_DEPTH,
-        full_threshold => CONSOLE_FIFO_DEPTH
+        full_threshold => CONSOLE_FIFO_ALMOST_FULL
     )
      port map(
         clk => clk,
@@ -180,7 +180,7 @@ begin
         parity => false,
         use_hw_handshake => true,
         fifo_depth => IPCC_FIFO_DEPTH,
-        full_threshold => IPCC_FIFO_DEPTH
+        full_threshold => IPCC_FIFO_ALMOST_FULL
     )
      port map(
         clk => clk,

hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd

@@ -13,7 +13,9 @@ use work.calc_pkg.all;
 package sp5_uart_subsystem_pkg is
 
     constant CONSOLE_FIFO_DEPTH : integer := 256; -- FIFO depth for UARTs
-    constant IPCC_FIFO_DEPTH : integer := 16; -- FIFO depth for IPCC UART
+    constant CONSOLE_FIFO_ALMOST_FULL : integer := CONSOLE_FIFO_DEPTH - 8; -- Threshold for "almost full" status signal
+    constant IPCC_FIFO_DEPTH : integer := 32; -- FIFO depth for IPCC UART
+    constant IPCC_FIFO_ALMOST_FULL : integer := IPCC_FIFO_DEPTH - 8; -- Threshold for "almost full" status signal
 
     -- To the debug interface
     type console_uart_dbg_t is record