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WIP rendmp: add RAA229620A support
This contains a bunch of assumptions (marked with TODOs) and may not work. We are reaching out to Renesas for clarifications.
1 parent ab234d0 commit 13112e2

1 file changed

Lines changed: 76 additions & 2 deletions

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cmd/rendmp/src/lib.rs

Lines changed: 76 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -957,6 +957,7 @@ fn rendmp_ingest(subargs: &RendmpArgs) -> Result<()> {
957957
enum SupportedDevice {
958958
ISL68224,
959959
RAA229618,
960+
RAA229620A,
960961
}
961962

962963
impl SupportedDevice {
@@ -965,6 +966,7 @@ impl SupportedDevice {
965966
match self {
966967
SupportedDevice::ISL68224 => 3,
967968
SupportedDevice::RAA229618 => 2,
969+
SupportedDevice::RAA229620A => 2,
968970
}
969971
}
970972

@@ -991,6 +993,20 @@ impl SupportedDevice {
991993
}
992994
phases
993995
}
996+
SupportedDevice::RAA229620A => {
997+
let mut phases = vec![];
998+
for phase in 0..12 {
999+
phases.push((phase.to_string(), phase));
1000+
}
1001+
for i in 0..2 {
1002+
// The 20 here looks like a copy paste mistake from the
1003+
// '618, but is deliberate; we believe the bit offset here
1004+
// is the same as the '618 despite the smaller phase count.
1005+
// (TODO)
1006+
phases.push((format!("VSEN{i}"), i + 20));
1007+
}
1008+
phases
1009+
}
9941010
}
9951011
}
9961012
}
@@ -1130,6 +1146,10 @@ fn get_pin_states(
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0x00BE, 0x00BF, // open-pin
11311147
0xE904, 0xE905, // mask
11321148
],
1149+
SupportedDevice::RAA229620A => &[ // TODO unverified
1150+
0x00BE, 0x00BF, // open-pin
1151+
0xE904, 0xE905, // mask
1152+
],
11331153
};
11341154
let mut ops = vec![];
11351155
for &r in regs {
@@ -1156,7 +1176,8 @@ fn get_pin_states(
11561176
// experiments and discussion with Renesas.
11571177
let (open, mask) = match dev {
11581178
SupportedDevice::ISL68224 => (values[0] as u64, values[1] as u64),
1159-
SupportedDevice::RAA229618 => {
1179+
// TODO: RAA229620A support is untested/unverified
1180+
SupportedDevice::RAA229618 | SupportedDevice::RAA229620A => {
11601181
let open = values[0] as u64 | ((values[1] as u64) << 32);
11611182
let mask = values[2] as u64 | ((values[3] as u64) << 32);
11621183
(open, mask)
@@ -1696,6 +1717,7 @@ fn rendmp_phase_check<'a>(
16961717
let disable_fault_reg: u16 = match dev {
16971718
SupportedDevice::ISL68224 => 0xE952,
16981719
SupportedDevice::RAA229618 => 0xE932,
1720+
SupportedDevice::RAA229620A => 0xE932, // TODO may have changed
16991721
};
17001722

17011723
////////////////////////////////////////////////////////////////////////////
@@ -1722,7 +1744,13 @@ fn rendmp_phase_check<'a>(
17221744
worker.read_word32(index, true, LOOPCFG as u8)?;
17231745
worker.read_word(index, true, PEAK_OCUC_COUNT as u8)?;
17241746

1725-
// Set PMBus command codes 0xD0 and 0xD1 to 0x8000 (disable VMon)
1747+
// Set the appropriate device-specific PMBus command codes to input
1748+
// voltage thresholding, by setting the thresholds to a very negative
1749+
// value. This should ensure that it always thinks the input value is
1750+
// high enough.
1751+
//
1752+
// This is a 16-bit two's-complement register, so 0x8000 is the most
1753+
// negative value.
17261754
match dev {
17271755
SupportedDevice::ISL68224 => {
17281756
use pmbus::commands::isl68224::CommandCode;
@@ -1757,6 +1785,25 @@ fn rendmp_phase_check<'a>(
17571785
let reg = (0xEA5B + rail * 0x80) as u16;
17581786
worker.read_dma(addr, reg)?;
17591787
}
1788+
SupportedDevice::RAA229620A => {
1789+
use pmbus::commands::raa229620a::CommandCode;
1790+
worker.write_word(
1791+
index,
1792+
true,
1793+
CommandCode::VIN_ON as u8,
1794+
0x8000,
1795+
)?;
1796+
worker.write_word(
1797+
index,
1798+
true,
1799+
CommandCode::VIN_OFF as u8,
1800+
0x8000,
1801+
)?;
1802+
1803+
// TODO: we do this undocumented read of 0xEA5B on the '618.
1804+
let reg = (0xEA5B + rail * 0x80) as u16;
1805+
worker.read_dma(addr, reg)?;
1806+
}
17601807
}
17611808

17621809
worker.read_dma(addr, disable_fault_reg + rail as u16)?;
@@ -1849,6 +1896,26 @@ fn rendmp_phase_check<'a>(
18491896
bail!("failed to set VIN_OFF for {rail}: {e}",);
18501897
}
18511898

1899+
// Clear bit 0 of DMA register EA5B and write it back
1900+
// (the name part_fast_add comes from Power Navigator)
1901+
let mut part_fast_add = match next()? {
1902+
Ok(v) => v.expect_read_dma()?,
1903+
Err(e) => {
1904+
bail!("worker.failed to read EA5B for rail {rail}: {e}")
1905+
}
1906+
};
1907+
part_fast_add &= !1; // clear bit 0
1908+
let reg = (0xEA5B + rail * 0x80) as u16;
1909+
worker.write_dma(addr, reg, part_fast_add)?;
1910+
}
1911+
SupportedDevice::RAA229620A => {
1912+
if let Err(e) = next()? {
1913+
bail!("failed to set VIN_ON for {rail}: {e}",);
1914+
}
1915+
if let Err(e) = next()? {
1916+
bail!("failed to set VIN_OFF for {rail}: {e}",);
1917+
}
1918+
18521919
// Clear bit 0 of DMA register EA5B and write it back
18531920
// (the name part_fast_add comes from Power Navigator)
18541921
let mut part_fast_add = match next()? {
@@ -1919,6 +1986,12 @@ fn rendmp_phase_check<'a>(
19191986
bail!("failed to modify EA5B for rail {rail}: {e}")
19201987
}
19211988
},
1989+
SupportedDevice::RAA229620A => match next()? {
1990+
Ok(v) => v.expect_write_dma()?,
1991+
Err(e) => {
1992+
bail!("failed to modify EA5B for rail {rail}: {e}")
1993+
}
1994+
},
19221995
SupportedDevice::ISL68224 => {
19231996
// no changes were made specifically for the ISL68224
19241997
}
@@ -2079,6 +2152,7 @@ fn rendmp_phase_check<'a>(
20792152
};
20802153
let device = match dev {
20812154
SupportedDevice::RAA229618 => pmbus::Device::Raa229618,
2155+
SupportedDevice::RAA229620A => pmbus::Device::Raa229620A,
20822156
SupportedDevice::ISL68224 => pmbus::Device::Isl68224,
20832157
};
20842158

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