Users following catalyst-neuromorphic
Aditya Mittal
AdityaMCore
EEE @ VIT Vellore ’29 | Verilog • Digital Design • FPGA | Learning Japanese (JLPT N5) | Building toward VLSI/RTL
pgreendale
pgreendale
Engineer. Experience in analog electronics, C/ for AVR, MSP430 and Verilog/FPGA.