multi_port_example.sv

/**
 * NeoRAM Multi-Port Usage Example (Updated for v1.3.0)
 *
 * This example demonstrates how to use the NeoRAM controller in a
 * dual-port configuration with round-robin arbitration and proper
 * ready signal handling. Suitable for cache or shared memory systems.
 */
module neoram_multi_port_example (
    input         clk,              // System clock
    input         rst_n,            // Active-low reset
    
    // Port 0 interface (e.g., for CPU)
    input  [7:0]  cpu_addr,         // Address from CPU
    input  [31:0] cpu_data_in,      // Data from CPU
    input         cpu_write_req,    // Write request from CPU
    input         cpu_read_req,     // Read request from CPU
    output [31:0] cpu_data_out,     // Data to CPU
    output        cpu_ready,        // CPU operation complete
    
    // Port 1 interface (e.g., for DMA)
    input  [7:0]  dma_addr,         // Address from DMA
    input  [31:0] dma_data_in,      // Data from DMA
    input         dma_write_req,    // Write request from DMA
    input         dma_read_req,     // Read request from DMA
    output [31:0] dma_data_out,     // Data to DMA
    output        dma_ready,        // DMA operation complete
    
    // Common status signals
    output        error_detected    // Error detected on any port
);

    // Internal signals for NeoRAM interface
    logic [1:0][7:0]  neoram_addr;
    logic [1:0][31:0] neoram_write_data;
    logic [1:0]       neoram_write_en;
    logic [1:0][31:0] neoram_read_data;
    logic [1:0]       neoram_ready;
    logic             neoram_error;
    
    // State machine for each port
    typedef enum {IDLE, WRITING, READING, WAIT_READY} state_t;
    state_t cpu_state, next_cpu_state;
    state_t dma_state, next_dma_state;
    
    // CPU port state registers
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cpu_state <= IDLE;
        end else begin
            cpu_state <= next_cpu_state;
        end
    end
    
    // DMA port state registers
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            dma_state <= IDLE;
        end else begin
            dma_state <= next_dma_state;
        end
    end
    
    // CPU port next state logic
    always_comb begin
        next_cpu_state = cpu_state; // Default: stay in current state
        
        case (cpu_state)
            IDLE: begin
                if (cpu_write_req) begin
                    next_cpu_state = WRITING;
                end else if (cpu_read_req) begin
                    next_cpu_state = READING;
                end
            end
            
            WRITING, READING: begin
                next_cpu_state = WAIT_READY;
            end
            
            WAIT_READY: begin
                if (neoram_ready[0]) begin
                    next_cpu_state = IDLE;
                end
            end
            
            default: next_cpu_state = IDLE;
        endcase
    end
    
    // DMA port next state logic
    always_comb begin
        next_dma_state = dma_state; // Default: stay in current state
        
        case (dma_state)
            IDLE: begin
                if (dma_write_req) begin
                    next_dma_state = WRITING;
                end else if (dma_read_req) begin
                    next_dma_state = READING;
                end
            end
            
            WRITING, READING: begin
                next_dma_state = WAIT_READY;
            end
            
            WAIT_READY: begin
                if (neoram_ready[1]) begin
                    next_dma_state = IDLE;
                end
            end
            
            default: next_dma_state = IDLE;
        endcase
    end
    
    // CPU port output logic
    always_comb begin
        // Default values
        neoram_addr[0] = 8'd0;
        neoram_write_data[0] = 32'd0;
        neoram_write_en[0] = 1'b0;
        
        case (cpu_state)
            IDLE: begin
                // Idle state, no signals active
            end
            
            WRITING: begin
                neoram_addr[0] = cpu_addr;
                neoram_write_data[0] = cpu_data_in;
                neoram_write_en[0] = 1'b1;
            end
            
            READING: begin
                neoram_addr[0] = cpu_addr;
                neoram_write_en[0] = 1'b0;
            end
            
            WAIT_READY: begin
                // Hold signals steady while waiting
                if (cpu_write_req) begin
                    neoram_addr[0] = cpu_addr;
                    neoram_write_data[0] = cpu_data_in;
                    neoram_write_en[0] = 1'b1;
                end else if (cpu_read_req) begin
                    neoram_addr[0] = cpu_addr;
                    neoram_write_en[0] = 1'b0;
                end
            end
        endcase
    end
    
    // DMA port output logic
    always_comb begin
        // Default values
        neoram_addr[1] = 8'd0;
        neoram_write_data[1] = 32'd0;
        neoram_write_en[1] = 1'b0;
        
        case (dma_state)
            IDLE: begin
                // Idle state, no signals active
            end
            
            WRITING: begin
                neoram_addr[1] = dma_addr;
                neoram_write_data[1] = dma_data_in;
                neoram_write_en[1] = 1'b1;
            end
            
            READING: begin
                neoram_addr[1] = dma_addr;
                neoram_write_en[1] = 1'b0;
            end
            
            WAIT_READY: begin
                // Hold signals steady while waiting
                if (dma_write_req) begin
                    neoram_addr[1] = dma_addr;
                    neoram_write_data[1] = dma_data_in;
                    neoram_write_en[1] = 1'b1;
                end else if (dma_read_req) begin
                    neoram_addr[1] = dma_addr;
                    neoram_write_en[1] = 1'b0;
                end
            end
        endcase
    end
    
    // Output assignments
    assign cpu_data_out = neoram_read_data[0];
    assign cpu_ready = (cpu_state == IDLE);
    
    assign dma_data_out = neoram_read_data[1];
    assign dma_ready = (dma_state == IDLE);
    
    assign error_detected = neoram_error;
    
    // Instantiate NeoRAM controller with 2 ports
    neoram_controller #(
        .ADDR_WIDTH(8),       // 8-bit address
        .DATA_WIDTH(32),      // 32-bit data
        .NUM_PORTS(2)         // Dual port configuration
    ) neoram_inst (
        .clk            (clk),
        .rst_n          (rst_n),
        .addr           (neoram_addr),       // Connect your address buses
        .write_data     (neoram_write_data), // Connect your write data buses
        .write_en       (neoram_write_en),   // Connect your write enable signals
        .read_data      (neoram_read_data),  // Connect to your read data outputs
        .ready          (neoram_ready),      // Connect to your ready signals
        .error          (neoram_error)       // Connect to error handling logic
    );
    
    // Performance monitoring (optional) - Enhanced for v1.3.0
    logic [31:0] access_count [1:0];
    logic [31:0] conflict_count;
    logic [31:0] arbitration_cycles;
    
    // Count accesses, conflicts, and arbitration fairness
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            access_count[0] <= 32'd0;
            access_count[1] <= 32'd0;
            conflict_count <= 32'd0;
            arbitration_cycles <= 32'd0;
        end else begin
            // Count CPU access
            if ((cpu_state == WRITING || cpu_state == READING) && 
                next_cpu_state == WAIT_READY) begin
                access_count[0] <= access_count[0] + 1;
            end
            
            // Count DMA access
            if ((dma_state == WRITING || dma_state == READING) && 
                next_dma_state == WAIT_READY) begin
                access_count[1] <= access_count[1] + 1;
            end
            
            // Count conflicts (both ports accessing same address simultaneously)
            // Note: v1.3.0 uses round-robin arbitration for fair conflict resolution
            if ((cpu_state == WRITING || cpu_state == READING) && 
                (dma_state == WRITING || dma_state == READING) &&
                (cpu_addr == dma_addr)) begin
                conflict_count <= conflict_count + 1;
            end
            
            // Monitor arbitration cycles for performance analysis
            if ((cpu_state != IDLE) || (dma_state != IDLE)) begin
                arbitration_cycles <= arbitration_cycles + 1;
            end
        end
    end
    
    // v1.3.0 Features demonstration
    initial begin
        $display("NeoRAM Multi-Port Example - v1.3.0");
        $display("Features:");
        $display("  - Round-robin arbitration for fair port access");
        $display("  - Proper ready signal initialization (no 'x' states)");
        $display("  - 32-bit data width consistency");
        $display("  - Enhanced conflict resolution");
    end

endmodule