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NeoRAM: Intelligent Multi-Port Memory System Architecture

This document describes the architecture of the NeoRAM system.

Overview

NeoRAM is a cutting-edge, configurable multi-port memory system with advanced features such as error correction capabilities and power management. It is designed to be highly flexible and suitable for various applications requiring reliable and efficient memory access in modern SoC designs.

Key Components

  1. NeoRAM Wrapper

    • Encapsulates the Sky130 SRAM macro
    • Provides a unified interface for multiple ports

  2. NeoRAM Controller

    • Orchestrates read and write operations
    • Implements error correction coding (ECC)
    • Coordinates with the power manager for efficient operation

  3. ECC Encoder/Decoder

    • Implements SECDED (Single Error Correction, Double Error Detection) using Hamming code
    • Enhances data integrity and reliability

  4. Power Manager

    • Monitors NeoRAM usage patterns
    • Implements advanced power-saving features to reduce energy consumption

  5. Multi-Port Arbiter

    • Manages concurrent access to the NeoRAM for multiple ports
    • Implements round-robin arbitration for fair port access
    • Provides proper ready signal management and initialization

Features

  • Configurable number of ports for versatile integration
  • Consistent 32-bit data width architecture with proper signal initialization
  • Robust error correction using SECDED with both ECC and bypass modes
  • Round-robin arbitration ensuring fair access across multiple ports
  • Intelligent power management for improved energy efficiency
  • Comprehensive verification suite using Cocotb with 100% test pass rate
  • Proper ready signal management eliminating undefined states

Design Considerations

  • Modularity: Each component is designed as a separate module, promoting easy maintenance and reusability.
  • Configurability: Parameterized design allows for easy adaptation to different use cases.
  • Reliability: Advanced ECC implementation significantly improves data integrity.
  • Efficiency: Sophisticated power management features help reduce overall system energy consumption.
  • Scalability: The architecture is designed to scale with increasing demands on memory subsystems.

Recent Improvements (v1.3.0)

  • Round-Robin Arbitration: Implemented fair scheduling algorithm ensuring equal access opportunity for all ports
  • Signal Initialization: Eliminated undefined 'x' states in ready signals and other control signals
  • Data Width Consistency: Standardized on 32-bit data width throughout the system for optimal compatibility
  • Dual-Mode Operation: Enhanced support for both ECC and bypass modes with seamless switching
  • Test Coverage: Achieved 100% test pass rate across all verification scenarios

Future Improvements

  • Implementation of weighted round-robin arbitration for QoS-aware port scheduling
  • Support for different types of memory macros beyond Sky130
  • Enhanced power management features, including fine-grained power gating
  • Implementation of additional error correction schemes (e.g., BCH codes) for even higher reliability
  • Integration with popular SoC bus protocols (e.g., AXI, Wishbone) for seamless system integration
  • Performance monitoring and analytics capabilities