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topology1: sof-hda-generic: enable Waves playback
Create eq_iir + waves pipeline: pipe-eq-iir-waves-codec-playback.m4 and enable this pipeline on HDA0 for speaker/headphone playaback. HDA0.OUT dai pipeline is included for codec adapter widget connection. Signed-off-by: Mac Chiang <mac.chiang@intel.com>
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Lines changed: 133 additions & 5 deletions

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‎tools/topology/topology1/CMakeLists.txt‎

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@@ -29,6 +29,7 @@ set(TPLGS
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"sof-hda-generic\;sof-hda-generic-4ch\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1"
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"sof-hda-generic\;sof-hda-generic-4ch-bt\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DBT_OFFLOAD"
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"sof-hda-generic\;sof-hda-generic-4ch-dts\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DDTS=`DTS'"
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"sof-hda-generic\;sof-hda-generic-4ch-waves\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DWAVES"
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## end HDaudio codec topologies
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"sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0\;-DDYNAMIC=1"

‎tools/topology/topology1/sof-hda-generic.m4‎

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@@ -46,6 +46,10 @@ define(`BT_PCM_ID', `8')
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define(`HW_CONFIG_ID', 8)
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include(`platform/intel/intel-generic-bt.m4')')
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# define HDA0_OUT DAI pipeline if the codec adapter is included.
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ifdef(`DTS',`define(PIPELINE_HDA0_OUT)')
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ifdef(`WAVES',`define(PIPELINE_HDA0_OUT)')
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# The pipeline naming notation is pipe-mixer-PROCESSING-dai-DIRECTION.m4
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# HSPROC is set by makefile, if not the default above is applied
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define(PIPE_HEADSET_PLAYBACK, `sof/pipe-mixer-`HSPROC'-dai-playback.m4')
@@ -107,18 +111,19 @@ DAI_ADD(PIPE_HEADSET_PLAYBACK,
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# Low Latency playback pipeline 1 on PCM 30 using max 2 channels of s32le.
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# 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(
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ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4, sof/pipe-host-volume-playback.m4),
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ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4,
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ifdef(`WAVES', sof/pipe-eq-iir-waves-codec-playback.m4, sof/pipe-host-volume-playback.m4)),
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30, 0, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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ifdef(`DTS',
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ifdef(`PIPELINE_HDA0_OUT',
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`
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# Because there is no dai pipeline.30 for HDA0.OUT in pipe-eq-iir-dts-codec-playback.m4, so
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# using macro defined W_PIPELINE_TOP() to add missing dai pipeline back. Instead of
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# modifying in pipe-eq-iir-dts-codec-playback.m4, these changes are not necessary for all others.
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# Because there is no dai pipeline.30 for HDA0.OUT in corresponding m4 file, so
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# using macro defined W_PIPELINE_TOP() to add missing dai pipeline back.
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# The changes are applying to connect codec adapter widget configuration.
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W_PIPELINE_TOP(30, HDA0.OUT, 1000, 0, 0, 1, pipe_dai_schedule_plat)
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')
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‎tools/topology/topology1/sof/pipe-eq-iir-waves-codec-playback.m4‎

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# Low Latency Passthrough with EQIIR and Waves codec Pipeline
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#
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# Pipeline Endpoints for connection are :
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#
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# host PCM_P -- B0 --> EQIIR0 -> B1 --> Waves -- B2 --> sink DAI0
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# |
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DECLARE_SOF_RT_UUID("Waves codec", waves_codec_uuid, 0xd944281a, 0xafe9,
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0x4695, 0xa0, 0x43, 0xd7, 0xf6, 0x2b, 0x89, 0x53, 0x8e);
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define(`CA_UUID', waves_codec_uuid)
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`pga.m4')
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include(`bytecontrol.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`codec_adapter.m4')
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include(`eq_iir.m4')
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ifelse(PLATFORM, `tgl', `
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define(SETUP_PARAMS_NAME, `MaxxChrome Setup' PIPELINE_ID)', `
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define(SETUP_PARAMS_NAME, `Waves Codec Setup' PIPELINE_ID)')
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CONTROLBYTES_PRIV(PP_SETUP_CONFIG,
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` bytes "0x53,0x4f,0x46,0x00,'
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` 0x00,0x00,0x00,0x00,'
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` 0x0c,0x00,0x00,0x00,'
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` 0x00,0x10,0x00,0x03,'
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` 0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,'
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` 0x0c,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00"'
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)
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# Post process Bytes control for setup config
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C_CONTROLBYTES(SETUP_PARAMS_NAME, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes),
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CONTROLBYTES_EXTOPS(void, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 8192),
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,
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PP_SETUP_CONFIG)
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#
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# EQIIR
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#
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define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
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define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
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# define filter. eq_iir_coef_flat.m4 is set by default
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ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_flat.m4)')
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include(PIPELINE_FILTER1)
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# EQ Bytes control with max value of 255
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C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
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CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 1024),
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,
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DEF_EQIIR_PRIV)
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#
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# Components and Buffers
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#
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# Host "Low latency Playback" PCM
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# with 2 sink and 0 source periods
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W_PCM_PLAYBACK(PCM_ID, Low Latency Playback, 2, 0, SCHEDULE_CORE)
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W_CODEC_ADAPTER(0, PIPELINE_FORMAT, DAI_PERIODS, DAI_PERIODS, SCHEDULE_CORE,
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LIST(` ', "SETUP_PARAMS_NAME"))
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# "EQIIR0" has 2 sink period and 2 source periods
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W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, SCHEDULE_CORE,
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LIST(` ', "DEF_EQIIR_COEF"))
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# Low Latency Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_HOST_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_COMP_MEM_CAP)
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W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_COMP_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM_P --> B0 --> EQ_IIR 0 --> B1 --> Waves Codec --> B2 --> sink DAI0
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P_GRAPH(pipe-eq-iir-waves-codec-playback, PIPELINE_ID,
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LIST(` ',
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`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
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`dapm(N_EQ_IIR(0), N_BUFFER(0))',
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`dapm(N_BUFFER(1), N_EQ_IIR(0))',
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`dapm(N_CODEC_ADAPTER(0), N_BUFFER(1))',
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`dapm(N_BUFFER(2), N_CODEC_ADAPTER(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Low Latency Playback PCM_ID)
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#
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# PCM Configuration
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#
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# PCM capabilities supported by FW
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PCM_CAPABILITIES(Low Latency Playback PCM_ID, CAPABILITY_FORMAT_NAME(PIPELINE_FORMAT), 48000, 48000, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
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undefine(`DEF_EQIIR_COEF')
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undefine(`DEF_EQIIR_PRIV')

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