hardware: M5Stack PoE-P4 + Display Out add-on (LT8912B), 3 separate boards tested (rev 1.3).?ref=chat.m5stack.com
symptom: LT8912B input-detect registers report H=0/V=0 on all 3 boards %E2%80%94 the DSI receiver never locks, so HDMI is never emitted (display reports "out of range"). DSI DMA underrun was present and has been genuinely fixed; the remaining failure is the lock itself.?ref=chat.m5stack.com
Exhaustively verified against published driver source and factory build — all confirmed matched and eliminated:
Register content, order, timing, VIC, polarity, pixel clock — byte-identical to real Panel_LT8912B.cpp
I2C port, SWRESET, DBI creation, engineering_sample flag — matched Bus_DSI.cpp/M5UnitPoEP4HDMI exactly
PSRAM mode/speed + sdkconfig — confirmed against the real factory config
Exact validated ESP-IDF version — confirmed running, no change
Chip-revision/bootloader flag — confirmed correct
Lane rate 500–1500 Mbps/lane — no effect (identical H=0/V=0; note the validated build needs ~891 Mbps/lane for 1080p RGB888 over 2 lanes, squarely inside the tested sweep)
IDF × board-revision matrix — the esp_clk_init assert on 5.5.2/rev1.3 documented, working version confirmed
conclusion:No software variable remains untested. The failure must be either (a) unpublished D-PHY TX calibration / esp_lcd DSI bus+panel config (computed lane_mbps, DSI clock source, PHY settings) in M5's validated build, or (b) a hardware defect on the Display Out add-on.
request: Please provide the exact D-PHY/DSI configuration from the validated build, or confirm hardware defect with RMA/replacement guidance.?ref=chat.m5stack.com
Attachments available on request: byte-diff records, H=0/V=0 captures across 3 boards (board IDs + timestamps), IDF/board-revision matrix, lane-rate sweep log, sdkconfig, M5Unified/M5GFX versions.
hardware: M5Stack PoE-P4 + Display Out add-on (LT8912B), 3 separate boards tested (rev 1.3).?ref=chat.m5stack.com
symptom: LT8912B input-detect registers report H=0/V=0 on all 3 boards %E2%80%94 the DSI receiver never locks, so HDMI is never emitted (display reports "out of range"). DSI DMA underrun was present and has been genuinely fixed; the remaining failure is the lock itself.?ref=chat.m5stack.com
Exhaustively verified against published driver source and factory build — all confirmed matched and eliminated:
Register content, order, timing, VIC, polarity, pixel clock — byte-identical to real Panel_LT8912B.cpp
I2C port, SWRESET, DBI creation, engineering_sample flag — matched Bus_DSI.cpp/M5UnitPoEP4HDMI exactly
PSRAM mode/speed + sdkconfig — confirmed against the real factory config
Exact validated ESP-IDF version — confirmed running, no change
Chip-revision/bootloader flag — confirmed correct
Lane rate 500–1500 Mbps/lane — no effect (identical H=0/V=0; note the validated build needs ~891 Mbps/lane for 1080p RGB888 over 2 lanes, squarely inside the tested sweep)
IDF × board-revision matrix — the esp_clk_init assert on 5.5.2/rev1.3 documented, working version confirmed
conclusion:No software variable remains untested. The failure must be either (a) unpublished D-PHY TX calibration / esp_lcd DSI bus+panel config (computed lane_mbps, DSI clock source, PHY settings) in M5's validated build, or (b) a hardware defect on the Display Out add-on.
request: Please provide the exact D-PHY/DSI configuration from the validated build, or confirm hardware defect with RMA/replacement guidance.?ref=chat.m5stack.com
Attachments available on request: byte-diff records, H=0/V=0 captures across 3 boards (board IDs + timestamps), IDF/board-revision matrix, lane-rate sweep log, sdkconfig, M5Unified/M5GFX versions.