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C88.ucf
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81 lines (70 loc) · 4.77 KB
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# UCF file for the Papilio One board
# Generated by pin_converter, written by Kevin Lindsey
# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
# Main board wing pin [] to FPGA pin Pxx map
# -------C------- -------B------- -------A-------
# [GND] [C00] P91 [GND] [B00] P85 P86 [A15]
# [2V5] [C01] P92 [2V5] [B01] P83 P84 [A14]
# [3V3] [C02] P94 [3V3] [B02] P78 P79 [A13]
# [5V0] [C03] P95 [5V0] [B03] P71 P70 [A12]
# [C04] P98 [B04] P68 P67 [A11] [5V0]
# [C05] P2 [B05] P66 P65 [A10] [3V3]
# [C06] P3 [B06] P63 P62 [A09] [2V5]
# [C07] P4 [B07] P61 P60 [A08] [GND]
# [GND] [C08] P5 [GND] [B08] P58 P57 [A07]
# [2V5] [C09] P9 [2V5] [B09] P54 P53 [A06]
# [3V3] [C10] P10 [3V3] [B10] P41 P40 [A05]
# [5V0] [C11] P11 [5V0] [B11] P36 P35 [A04]
# [C12] P12 [B12] P34 P33 [A03] [5V0]
# [C13] P15 [B13] P32 P26 [A02] [3V3]
# [C14] P16 [B14] P25 P23 [A01] [2V5]
# [C15] P17 [B15] P22 P18 [A00] [GND]
## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
CONFIG PROHIBIT=P99;
CONFIG PROHIBIT=P43;
CONFIG PROHIBIT=P42;
CONFIG PROHIBIT=P39;
CONFIG PROHIBIT=P49;
CONFIG PROHIBIT=P48;
CONFIG PROHIBIT=P47;
DEFAULT PULLDOWN = TRUE;
NET CLK LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; # CLK
NET MOSI LOC="P91" | PULLDOWN = false | IOSTANDARD=LVTTL; # C0
NET SCK LOC="P92" | PULLDOWN = false | IOSTANDARD=LVTTL; # C1
NET SS LOC="P94" | PULLDOWN = false | IOSTANDARD=LVTTL; # C2
NET view_reg LOC="P95" | IOSTANDARD=LVTTL; # C3
NET view_pc LOC="P98" | IOSTANDARD=LVTTL; # C4
NET is_clock_full LOC="P2" | IOSTANDARD=LVTTL; # C5
NET is_clock_slow LOC="P3" | IOSTANDARD=LVTTL; # C6
NET RUN LOC="P18" | IOSTANDARD=LVTTL; # A0
NET STEP LOC="P23" | IOSTANDARD=LVTTL; # A1
NET RST LOC="P26" | IOSTANDARD=LVTTL; # A2
NET USER_MODE LOC="P33" | IOSTANDARD=LVTTL; # A3
NET USER_WRITE LOC="P35" | IOSTANDARD=LVTTL; # A4
NET USER_ADDR(0) LOC="P40" | IOSTANDARD=LVTTL; # A5
NET USER_ADDR(1) LOC="P53" | IOSTANDARD=LVTTL; # A6
NET USER_ADDR(2) LOC="P57" | IOSTANDARD=LVTTL; # A7
NET USER_DATA(0) LOC="P60" | IOSTANDARD=LVTTL; # A8
NET USER_DATA(1) LOC="P62" | IOSTANDARD=LVTTL; # A9
NET USER_DATA(2) LOC="P65" | IOSTANDARD=LVTTL; # A10
NET USER_DATA(3) LOC="P67" | IOSTANDARD=LVTTL; # A11
NET USER_DATA(4) LOC="P70" | IOSTANDARD=LVTTL; # A12
NET USER_DATA(5) LOC="P79" | IOSTANDARD=LVTTL; # A13
NET USER_DATA(6) LOC="P84" | IOSTANDARD=LVTTL; # A14
NET USER_DATA(7) LOC="P86" | IOSTANDARD=LVTTL; # A15
NET gpinput(0) LOC="P85" | IOSTANDARD=LVTTL; # B0
NET gpinput(1) LOC="P83" | IOSTANDARD=LVTTL; # B1
NET gpinput(2) LOC="P78" | IOSTANDARD=LVTTL; # B2
NET gpinput(3) LOC="P71" | IOSTANDARD=LVTTL; # B3
NET gpinput(4) LOC="P68" | IOSTANDARD=LVTTL; # B4
NET gpinput(5) LOC="P66" | IOSTANDARD=LVTTL; # B5
NET gpinput(6) LOC="P63" | IOSTANDARD=LVTTL; # B6
NET gpinput(7) LOC="P61" | IOSTANDARD=LVTTL; # B7
NET gpoutput(0) LOC="P58" | PULLDOWN = false | IOSTANDARD=LVTTL; # B8
NET gpoutput(1) LOC="P54" | PULLDOWN = false | IOSTANDARD=LVTTL; # B9
NET gpoutput(2) LOC="P41" | PULLDOWN = false | IOSTANDARD=LVTTL; # B10
NET gpoutput(3) LOC="P36" | PULLDOWN = false | IOSTANDARD=LVTTL; # B11
NET gpoutput(4) LOC="P34" | PULLDOWN = false | IOSTANDARD=LVTTL; # B12
NET gpoutput(5) LOC="P32" | PULLDOWN = false | IOSTANDARD=LVTTL; # B13
NET gpoutput(6) LOC="P25" | PULLDOWN = false | IOSTANDARD=LVTTL; # B14
NET gpoutput(7) LOC="P22" | PULLDOWN = false | IOSTANDARD=LVTTL; # B15