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Rollup merge of rust-lang#150556 - thejpster:add-thumbv7a-thumbv7r-thumbv8r, r=petrochenkov
Add Tier 3 Thumb-mode targets for Armv7-A, Armv7-R and Armv8-R We currently have targets for bare-metal Armv7-R, Armv7-A and Armv8-R, but only in Arm mode. This PR adds five new targets enabling bare-metal support on these architectures in Thumb mode. This has been tested using https://github.com/rust-embedded/aarch32/compare/main...thejpster:aarch32:support-thumb-mode-v7-v8?expand=1 and they all seem to work as expected. However, I wasn't sure what to do with the maintainer lists as these are five new targets, but they share the docs page with the existing Arm versions. I can ask the Embedded Devices WG Arm Team about taking on these ones too, but whether Arm themselves want to take them on I guess is a bigger question.
2 parents d222ddc + fa526c4 commit c5e4d9e

18 files changed

Lines changed: 231 additions & 125 deletions

‎compiler/rustc_target/src/spec/mod.rs‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1596,8 +1596,11 @@ supported_targets! {
15961596
("armebv7r-none-eabi", armebv7r_none_eabi),
15971597
("armebv7r-none-eabihf", armebv7r_none_eabihf),
15981598
("armv7r-none-eabi", armv7r_none_eabi),
1599+
("thumbv7r-none-eabi", thumbv7r_none_eabi),
15991600
("armv7r-none-eabihf", armv7r_none_eabihf),
1601+
("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
16001602
("armv8r-none-eabihf", armv8r_none_eabihf),
1603+
("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
16011604

16021605
("armv7-rtems-eabihf", armv7_rtems_eabihf),
16031606

@@ -1649,7 +1652,9 @@ supported_targets! {
16491652
("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
16501653

16511654
("armv7a-none-eabi", armv7a_none_eabi),
1655+
("thumbv7a-none-eabi", thumbv7a_none_eabi),
16521656
("armv7a-none-eabihf", armv7a_none_eabihf),
1657+
("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
16531658
("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
16541659
("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
16551660
("armv7a-vex-v5", armv7a_vex_v5),

‎compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs‎

Lines changed: 10 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1,40 +1,8 @@
1-
// Generic ARMv7-A target for bare-metal code - floating point disabled
2-
//
3-
// This is basically the `armv7-unknown-linux-gnueabi` target with some changes
4-
// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64`
5-
// targets:
6-
//
7-
// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned
8-
// memory access is disabled on boot on these cores
9-
// - linker changed to LLD. rationale: C is not strictly needed to build
10-
// bare-metal binaries (the `gcc` linker has the advantage that it knows where C
11-
// libraries and crt*.o are but it's not much of an advantage here); LLD is also
12-
// faster
13-
// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets
14-
// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic
15-
// linking. rationale: matches `thumb` targets
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
162

17-
use crate::spec::{
18-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
19-
TargetOptions,
20-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
214

225
pub(crate) fn target() -> Target {
23-
let opts = TargetOptions {
24-
abi: Abi::Eabi,
25-
llvm_floatabi: Some(FloatAbi::Soft),
26-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
27-
linker: Some("rust-lld".into()),
28-
features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
29-
relocation_model: RelocModel::Static,
30-
disable_redzone: true,
31-
max_atomic_width: Some(64),
32-
panic_strategy: PanicStrategy::Abort,
33-
emit_debug_gdb_scripts: false,
34-
c_enum_min_bits: Some(8),
35-
has_thumb_interworking: true,
36-
..Default::default()
37-
};
386
Target {
397
llvm_target: "armv7a-none-eabi".into(),
408
metadata: TargetMetadata {
@@ -46,6 +14,13 @@ pub(crate) fn target() -> Target {
4614
pointer_width: 32,
4715
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
4816
arch: Arch::Arm,
49-
options: opts,
17+
options: TargetOptions {
18+
abi: Abi::Eabi,
19+
llvm_floatabi: Some(FloatAbi::Soft),
20+
features: "+soft-float,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
5025
}
5126
}

‎compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs‎

Lines changed: 10 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,8 @@
1-
// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes
2-
// FPU is present and emits FPU instructions)
3-
//
4-
// This is basically the `armv7-unknown-linux-gnueabihf` target with some
5-
// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal
6-
// `thumb` & `aarch64` targets.
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
72

8-
use crate::spec::{
9-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
10-
TargetOptions,
11-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
124

135
pub(crate) fn target() -> Target {
14-
let opts = TargetOptions {
15-
abi: Abi::EabiHf,
16-
llvm_floatabi: Some(FloatAbi::Hard),
17-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
18-
linker: Some("rust-lld".into()),
19-
features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
20-
relocation_model: RelocModel::Static,
21-
disable_redzone: true,
22-
max_atomic_width: Some(64),
23-
panic_strategy: PanicStrategy::Abort,
24-
emit_debug_gdb_scripts: false,
25-
// GCC defaults to 8 for arm-none here.
26-
c_enum_min_bits: Some(8),
27-
has_thumb_interworking: true,
28-
..Default::default()
29-
};
306
Target {
317
llvm_target: "armv7a-none-eabihf".into(),
328
metadata: TargetMetadata {
@@ -38,6 +14,13 @@ pub(crate) fn target() -> Target {
3814
pointer_width: 32,
3915
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
4016
arch: Arch::Arm,
41-
options: opts,
17+
options: TargetOptions {
18+
abi: Abi::EabiHf,
19+
llvm_floatabi: Some(FloatAbi::Hard),
20+
features: "+vfp3d16,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
4225
}
4326
}

‎compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs‎

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,25 @@
11
// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
107
llvm_target: "armv7r-none-eabi".into(),
118
metadata: TargetMetadata {
12-
description: Some("Armv7-R".into()),
9+
description: Some("Bare Armv7-R".into()),
1310
tier: Some(2),
1411
host_tools: Some(false),
1512
std: Some(false),
1613
},
1714
pointer_width: 32,
1815
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
1916
arch: Arch::Arm,
20-
2117
options: TargetOptions {
2218
abi: Abi::Eabi,
2319
llvm_floatabi: Some(FloatAbi::Soft),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2820
max_atomic_width: Some(64),
29-
emit_debug_gdb_scripts: false,
30-
// GCC defaults to 8 for arm-none here.
31-
c_enum_min_bits: Some(8),
3221
has_thumb_interworking: true,
33-
..Default::default()
22+
..base::arm_none::opts()
3423
},
3524
}
3625
}

‎compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs‎

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,26 @@
11
// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
107
llvm_target: "armv7r-none-eabihf".into(),
118
metadata: TargetMetadata {
12-
description: Some("Armv7-R, hardfloat".into()),
9+
description: Some("Bare Armv7-R, hardfloat".into()),
1310
tier: Some(2),
1411
host_tools: Some(false),
1512
std: Some(false),
1613
},
1714
pointer_width: 32,
1815
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
1916
arch: Arch::Arm,
20-
2117
options: TargetOptions {
2218
abi: Abi::EabiHf,
2319
llvm_floatabi: Some(FloatAbi::Hard),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2820
features: "+vfp3d16".into(),
2921
max_atomic_width: Some(64),
30-
emit_debug_gdb_scripts: false,
31-
// GCC defaults to 8 for arm-none here.
32-
c_enum_min_bits: Some(8),
3322
has_thumb_interworking: true,
34-
..Default::default()
23+
..base::arm_none::opts()
3524
},
3625
}
3726
}

‎compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
11
// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
@@ -21,10 +18,6 @@ pub(crate) fn target() -> Target {
2118
options: TargetOptions {
2219
abi: Abi::EabiHf,
2320
llvm_floatabi: Some(FloatAbi::Hard),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2821
// Armv8-R requires a minimum set of floating-point features equivalent to:
2922
// fp-armv8, SP-only, with 16 DP (32 SP) registers
3023
// LLVM defines Armv8-R to include these features automatically.
@@ -36,11 +29,8 @@ pub(crate) fn target() -> Target {
3629
// Arm Cortex-R52 Processor Technical Reference Manual
3730
// - Chapter 15 Advanced SIMD and floating-point support
3831
max_atomic_width: Some(64),
39-
emit_debug_gdb_scripts: false,
40-
// GCC defaults to 8 for arm-none here.
41-
c_enum_min_bits: Some(8),
4232
has_thumb_interworking: true,
43-
..Default::default()
33+
..base::arm_none::opts()
4434
},
4535
}
4636
}

‎compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
2+
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
4+
5+
pub(crate) fn target() -> Target {
6+
Target {
7+
llvm_target: "thumbv7a-none-eabi".into(),
8+
metadata: TargetMetadata {
9+
description: Some("Thumb-mode Bare Armv7-A".into()),
10+
tier: Some(2),
11+
host_tools: Some(false),
12+
std: Some(false),
13+
},
14+
pointer_width: 32,
15+
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
16+
arch: Arch::Arm,
17+
options: TargetOptions {
18+
abi: Abi::Eabi,
19+
llvm_floatabi: Some(FloatAbi::Soft),
20+
features: "+soft-float,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
25+
}
26+
}

‎compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
2+
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
4+
5+
pub(crate) fn target() -> Target {
6+
Target {
7+
llvm_target: "thumbv7a-none-eabihf".into(),
8+
metadata: TargetMetadata {
9+
description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
10+
tier: Some(2),
11+
host_tools: Some(false),
12+
std: Some(false),
13+
},
14+
pointer_width: 32,
15+
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
16+
arch: Arch::Arm,
17+
options: TargetOptions {
18+
abi: Abi::EabiHf,
19+
llvm_floatabi: Some(FloatAbi::Hard),
20+
features: "+vfp3d16,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
25+
}
26+
}

‎compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
2+
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
4+
5+
pub(crate) fn target() -> Target {
6+
Target {
7+
llvm_target: "thumbv7r-none-eabi".into(),
8+
metadata: TargetMetadata {
9+
description: Some("Thumb-mode Bare Armv7-R".into()),
10+
tier: Some(2),
11+
host_tools: Some(false),
12+
std: Some(false),
13+
},
14+
pointer_width: 32,
15+
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
16+
arch: Arch::Arm,
17+
options: TargetOptions {
18+
abi: Abi::Eabi,
19+
llvm_floatabi: Some(FloatAbi::Soft),
20+
max_atomic_width: Some(64),
21+
has_thumb_interworking: true,
22+
..base::arm_none::opts()
23+
},
24+
}
25+
}

‎compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
2+
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
4+
5+
pub(crate) fn target() -> Target {
6+
Target {
7+
llvm_target: "thumbv7r-none-eabihf".into(),
8+
metadata: TargetMetadata {
9+
description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
10+
tier: Some(2),
11+
host_tools: Some(false),
12+
std: Some(false),
13+
},
14+
pointer_width: 32,
15+
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
16+
arch: Arch::Arm,
17+
options: TargetOptions {
18+
abi: Abi::EabiHf,
19+
llvm_floatabi: Some(FloatAbi::Hard),
20+
features: "+vfp3d16".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
25+
}
26+
}

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