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Fix some tests
Signed-off-by: Ludvig Liljenberg <4257730+ludfjig@users.noreply.github.com>
1 parent cf09f95 commit 65f6fc6

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4 files changed

+60
-14
lines changed

4 files changed

+60
-14
lines changed

src/hyperlight_host/src/hypervisor/virtual_machine/mod.rs

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,39 @@ pub(crate) const VIRTUALIZED_MSRS: &[(u32, u64, bool)] = &[
173173
(0x26D, 0, true), // MTRRfix4K_E8000
174174
(0x26E, 0, true), // MTRRfix4K_F0000
175175
(0x26F, 0, true), // MTRRfix4K_F8000
176+
177+
// ── MSHV/WHP additional virtualizations ─────────────────────────
178+
// These MSRs are handled internally by the Microsoft Hypervisor
179+
// without generating VM exits, even when MSR intercepts are enabled.
180+
// On KVM, the deny-all MSR filter traps them instead.
181+
182+
// Read-only MSRs (no reset needed)
183+
(0x17, 0, false), // IA32_PLATFORM_ID (read-only)
184+
(0x8B, 0, false), // IA32_BIOS_SIGN_ID (read-only)
185+
(0x10A, 0, false), // IA32_ARCH_CAPABILITIES (read-only)
186+
(0x179, 0, false), // IA32_MCG_CAP (read-only)
187+
(0x17A, 0, false), // IA32_MCG_STATUS (read-only in guest)
188+
(0x4D0, 0, false), // Platform-specific (read-only in guest)
189+
190+
// Speculative execution control
191+
(0x48, 0, true), // IA32_SPEC_CTRL
192+
193+
// CET (Control-flow Enforcement Technology) MSRs
194+
(0x6A0, 0, true), // IA32_U_CET
195+
(0x6A2, 0, true), // IA32_S_CET
196+
(0x6A4, 0, true), // IA32_PL0_SSP
197+
(0x6A5, 0, true), // IA32_PL1_SSP
198+
(0x6A6, 0, true), // IA32_PL2_SSP
199+
(0x6A7, 0, true), // IA32_PL3_SSP
200+
(0x6A8, 0, true), // IA32_INTERRUPT_SSP_TABLE_ADDR
201+
202+
// Extended supervisor state
203+
(0xDA0, 0, true), // IA32_XSS
204+
205+
// AMD-specific MSRs (read-only in guest context under MSHV)
206+
(0xC001_0010, 0, false), // AMD SYSCFG
207+
(0xC001_0114, 0, false), // AMD VM_CR
208+
(0xC001_0131, 0, false), // AMD (platform-specific)
176209
];
177210

178211
/// Returns `true` if the given MSR index is in [`VIRTUALIZED_MSRS`].

src/hyperlight_host/src/hypervisor/virtual_machine/mshv.rs

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ use mshv_bindings::{
3030
hv_partition_property_code_HV_PARTITION_PROPERTY_SYNTHETIC_PROC_FEATURES,
3131
hv_partition_synthetic_processor_features, hv_register_assoc,
3232
hv_register_name_HV_X64_REGISTER_RIP, hv_register_value, mshv_install_intercept,
33-
msr_to_hv_reg_name, mshv_user_mem_region,
33+
mshv_user_mem_region, msr_to_hv_reg_name,
3434
};
3535
use mshv_ioctls::{Mshv, VcpuFd, VmFd};
3636
use tracing::{Span, instrument};
@@ -390,13 +390,27 @@ impl VirtualMachine for MshvVm {
390390
}
391391

392392
fn reset_msrs(&self) -> std::result::Result<(), RegisterError> {
393+
use mshv_bindings::{hv_register_name, hv_register_name_HV_X64_REGISTER_U_XSS};
394+
393395
use super::MSRS_TO_RESET;
394396

397+
/// Extends `msr_to_hv_reg_name` with mappings missing from
398+
/// mshv-bindings (e.g. IA32_XSS 0xDA0, whose constant is
399+
/// incorrectly set to the HV register name value 0x8008B).
400+
fn msr_to_hv_reg(msr_index: u32) -> hv_register_name {
401+
msr_to_hv_reg_name(msr_index).unwrap_or_else(|_| match msr_index {
402+
0xDA0 => hv_register_name_HV_X64_REGISTER_U_XSS,
403+
_ => panic!(
404+
"MSR 0x{:X} in MSRS_TO_RESET has no HV register mapping",
405+
msr_index
406+
),
407+
})
408+
}
409+
395410
let regs: Vec<hv_register_assoc> = MSRS_TO_RESET
396411
.iter()
397412
.map(|&(msr_index, value)| hv_register_assoc {
398-
name: msr_to_hv_reg_name(msr_index)
399-
.expect("all MSR indices in MSRS_TO_RESET must have valid HV register mappings"),
413+
name: msr_to_hv_reg(msr_index),
400414
value: hv_register_value { reg64: value },
401415
..Default::default()
402416
})

src/hyperlight_host/src/hypervisor/virtual_machine/whp.rs

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -688,7 +688,9 @@ impl VirtualMachine for WhpVm {
688688
while i < MSRS_TO_RESET.len() {
689689
result[i] = (
690690
msr_index_to_whv_name(MSRS_TO_RESET[i].0),
691-
Align16(WHV_REGISTER_VALUE { Reg64: MSRS_TO_RESET[i].1 }),
691+
Align16(WHV_REGISTER_VALUE {
692+
Reg64: MSRS_TO_RESET[i].1,
693+
}),
692694
);
693695
i += 1;
694696
}

src/hyperlight_host/src/sandbox/initialized_multi_use.rs

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,8 +1438,7 @@ mod tests {
14381438
fn test_read_write_msr() {
14391439
use rand::seq::IteratorRandom;
14401440

1441-
use crate::hypervisor::virtual_machine::is_virtualized_msr;
1442-
use crate::hypervisor::virtual_machine::MSR_TEST_RANGES;
1441+
use crate::hypervisor::virtual_machine::{MSR_TEST_RANGES, is_virtualized_msr};
14431442

14441443
let value: u64 = 0x0;
14451444
const N: usize = 100;
@@ -1523,8 +1522,7 @@ mod tests {
15231522
/// will cause a deterministic failure.
15241523
#[test]
15251524
fn test_all_msr_indices_trapped_or_virtualized() {
1526-
use crate::hypervisor::virtual_machine::is_virtualized_msr;
1527-
use crate::hypervisor::virtual_machine::MSR_TEST_RANGES;
1525+
use crate::hypervisor::virtual_machine::{MSR_TEST_RANGES, is_virtualized_msr};
15281526

15291527
let mut sbox = UninitializedSandbox::new(
15301528
GuestBinary::FilePath(simple_guest_as_string().expect("Guest Binary Missing")),
@@ -1535,9 +1533,7 @@ mod tests {
15351533
.unwrap();
15361534
let snapshot = sbox.snapshot().unwrap();
15371535

1538-
let all_msr_indices = MSR_TEST_RANGES
1539-
.iter()
1540-
.flat_map(|&(start, end)| start..end);
1536+
let all_msr_indices = MSR_TEST_RANGES.iter().flat_map(|&(start, end)| start..end);
15411537

15421538
let mut untapped_not_in_list = Vec::new();
15431539

@@ -1554,9 +1550,10 @@ mod tests {
15541550
Err(err) => {
15551551
// Expected: the MSR was trapped. Verify it's the right error.
15561552
assert!(
1557-
matches!(err,
1558-
HyperlightError::MsrReadViolation(_) |
1559-
HyperlightError::GuestAborted(_, _)
1553+
matches!(
1554+
err,
1555+
HyperlightError::MsrReadViolation(_)
1556+
| HyperlightError::GuestAborted(_, _)
15601557
),
15611558
"MSR 0x{:X}: unexpected error variant: {:?}",
15621559
msr_index,

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