fix: initialize all segment registers and XSAVE state for MSHV/WHP compatibility

MSHV and WHP reject vCPU state with zeroed segment registers (ES, SS,
FS, GS, LDT) and uninitialized XSAVE areas.  Properly initialize all
segment registers in standard_real_mode_defaults() and add reset_xsave()
call after set_sregs() to ensure FPU state (FCW, MXCSR) is valid.

Signed-off-by: danbugs <danilochiarlone@gmail.com>

Author: danbugs

src/hyperlight_host/src/hypervisor/hyperlight_vm.rs

@@ -439,6 +439,12 @@ impl HyperlightVm {
         vm.set_sregs(&CommonSpecialRegisters::standard_real_mode_defaults())
             .map_err(VmError::Register)?;
 
+        // Initialize XSAVE state with proper FPU defaults (FCW, MXCSR).
+        // MSHV (unlike KVM) does not provide sane defaults for the XSAVE
+        // area on a freshly created vCPU, and will reject the VP state
+        // on the first run if it is left uninitialized.
+        vm.reset_xsave().map_err(VmError::Register)?;
+
         #[cfg(any(kvm, mshv3))]
         let interrupt_handle: Arc<dyn InterruptHandleImpl> = Arc::new(LinuxInterruptHandle {
             state: AtomicU8::new(0),

src/hyperlight_host/src/hypervisor/regs/special_regs.rs

@@ -106,34 +106,55 @@ impl CommonSpecialRegisters {
 
     #[cfg(not(feature = "init-paging"))]
     pub(crate) fn standard_real_mode_defaults() -> Self {
+        // In real mode, all data/code segment registers must have valid
+        // limit, present, type_, and s fields.  MSHV (unlike KVM) rejects
+        // the vCPU state if any segment has limit=0 / present=0.
+        let data_seg = CommonSegmentRegister {
+            base: 0,
+            selector: 0,
+            limit: 0xFFFF,
+            type_: 3, // data, read/write, accessed
+            present: 1,
+            s: 1, // non-system
+            ..Default::default()
+        };
+
         CommonSpecialRegisters {
             cs: CommonSegmentRegister {
                 base: 0,
                 selector: 0,
                 limit: 0xFFFF,
-                type_: 11,
+                type_: 11, // code, readable, accessed
                 present: 1,
-                s: 1,
+                s: 1, // non-system
                 ..Default::default()
             },
-            ds: CommonSegmentRegister {
+            ds: data_seg,
+            es: data_seg,
+            ss: data_seg,
+            fs: data_seg,
+            gs: data_seg,
+            tr: CommonSegmentRegister {
                 base: 0,
                 selector: 0,
                 limit: 0xFFFF,
-                type_: 3,
+                type_: 11, // 32-bit busy TSS
                 present: 1,
-                s: 1,
+                s: 0, // system segment
                 ..Default::default()
             },
-            tr: CommonSegmentRegister {
+            ldt: CommonSegmentRegister {
                 base: 0,
                 selector: 0,
                 limit: 0xFFFF,
-                type_: 11,
+                type_: 2, // LDT descriptor
                 present: 1,
-                s: 0,
+                s: 0, // system segment
                 ..Default::default()
             },
+            // CR0.ET (bit 4) is hardwired to 1 on modern x86 CPUs.
+            // MSHV rejects the vCPU state if ET is not set.
+            cr0: 1 << 4,
             ..Default::default()
         }
     }