FPGA_UART_Module/UART_usage.xml at master · davidParraga/FPGA_UART_Module · GitHub

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<DeviceUsageSummary rev="3">
<DesignStatistics TimeStamp="Tue Jul 09 08:51:14 2019"><group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="3">
<attrib name="value" value="23"/></item>
<item name="AGG_IO" rev="3">
<attrib name="value" value="23"/></item>
<item name="AGG_SLICE" rev="3">
<attrib name="value" value="51"/></item>
<item name="NUM_4_INPUT_LUT" rev="3">
<attrib name="value" value="74"/></item>
<item name="NUM_BONDED_IOB" rev="3">
<attrib name="value" value="23"/></item>
<item name="NUM_BUFGMUX" rev="3">
<attrib name="value" value="1"/></item>
<item name="NUM_CARRY_SKIP" rev="3">
<attrib name="value" value="2"/></item>
<item name="NUM_CYMUX" rev="3">
<attrib name="value" value="44"/></item>
<item name="NUM_LUT_RT" rev="3">
<attrib name="value" value="8"/></item>
<item name="NUM_SLICEL" rev="3">
<attrib name="value" value="51"/></item>
<item name="NUM_SLICE_FF" rev="3">
<attrib name="value" value="71"/></item>
<item name="NUM_XOR" rev="3">
<attrib name="value" value="26"/></item>
</group>
</DesignStatistics>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>