Cranelift: update regalloc2 to 0.15.0 to permit more VRegs. (#12611)

* Cranelift: update regalloc2 to 0.15.0 to permit more VRegs.

This pulls in bytecodealliance/regalloc2#257 to permit more VRegs to
be used in a single function body, addressing #12229 and our followup
discussions about supporting function body sizes up to the Wasm
implementation limit standard.

In addition to the RA2 upgrade, this also includes a bit more explicit
limit-checking on the Cranelift side: note that we don't directly use
`regalloc2::VReg` but instead we further bitpack it into `Reg`, which
is logically a sum type of `VReg`, `PReg` and `SpillSlot` (the last
one needed to represent stack allocation locations on defs, e.g. on
callsites with many returns). `PReg`s are packed into the beginning of
the `VReg` index space but `SpillSlot`s are distinguished by stealing
the upper bit of a `u32`. This was previously not a problem given the
smaller `VReg` index space but now we need to check explicitly; hence
`Reg::from_virtual_reg_checked` and its use in the lowering vreg
allocator. Because the `VReg` index packs the class into the bottom
two bits, and index into the upper 30, but we steal one bit at the
top, the true limit for VReg count is thus actually 2^29, or
512M.

Fixes #12229.

* Drop `code_too_large` test.

Author: cfallin

Cargo.lock

@@ -322,7 +322,7 @@ component-async-tests = { path = "crates/misc/component-async-tests" }
 
 # Bytecode Alliance maintained dependencies:
 # ---------------------------
-regalloc2 = "0.14.0"
+regalloc2 = "0.15.0"
 wasip1 = { version = "1.0.0", default-features = false }
 
 # cap-std family:

Cargo.toml

@@ -54,12 +54,28 @@ const REG_SPILLSLOT_MASK: u32 = !REG_SPILLSLOT_BIT;
 impl Reg {
     /// Const constructor: create a new Reg from a regalloc2 VReg.
     pub const fn from_virtual_reg(vreg: regalloc2::VReg) -> Reg {
-        Reg(vreg.bits() as u32)
+        let bits = vreg.bits() as u32;
+        debug_assert!(bits <= REG_SPILLSLOT_MASK);
+        Reg(bits)
     }
 
     /// Const constructor: create a new Reg from a regalloc2 PReg.
     pub const fn from_real_reg(preg: regalloc2::PReg) -> Reg {
-        Reg(preg_to_pinned_vreg(preg).bits() as u32)
+        let vreg = preg_to_pinned_vreg(preg);
+        let bits = vreg.bits() as u32;
+        debug_assert!(bits <= REG_SPILLSLOT_MASK);
+        Reg(bits)
+    }
+
+    /// Maybe construct from a `regalloc2::VReg`, checking if the
+    /// index is in-range for our bit-packing.
+    pub fn from_virtual_reg_checked(vreg: regalloc2::VReg) -> Option<Reg> {
+        let bits = vreg.bits() as u32;
+        if bits <= REG_SPILLSLOT_MASK {
+            Some(Reg(bits))
+        } else {
+            None
+        }
     }
 
     /// Get the physical register (`RealReg`), if this register is

cranelift/codegen/src/machinst/reg.rs

@@ -1780,13 +1780,23 @@ impl<I: VCodeInst> VRegAllocator<I> {
         }
         let v = self.vreg_types.len();
         let (regclasses, tys) = I::rc_for_type(ty)?;
-        if v + regclasses.len() >= VReg::MAX {
+
+        // Check that new indices are in-bounds for regalloc2's
+        // VReg/Operand representation.
+        if v + regclasses.len() > VReg::MAX {
             return Err(CodegenError::CodeTooLarge);
         }
 
+        // Check that new indices are in-bounds for our Reg
+        // bit-packing on top of the RA2 types, which represents
+        // spillslots as well.
+        let check = |vreg: regalloc2::VReg| -> CodegenResult<Reg> {
+            Reg::from_virtual_reg_checked(vreg).ok_or(CodegenError::CodeTooLarge)
+        };
+
         let regs: ValueRegs<Reg> = match regclasses {
-            &[rc0] => ValueRegs::one(VReg::new(v, rc0).into()),
-            &[rc0, rc1] => ValueRegs::two(VReg::new(v, rc0).into(), VReg::new(v + 1, rc1).into()),
+            &[rc0] => ValueRegs::one(check(VReg::new(v, rc0))?),
+            &[rc0, rc1] => ValueRegs::two(check(VReg::new(v, rc0))?, check(VReg::new(v + 1, rc1))?),
             // We can extend this if/when we support 32-bit targets; e.g.,
             // an i128 on a 32-bit machine will need up to four machine regs
             // for a `Value`.

cranelift/codegen/src/machinst/vcode.rs

@@ -1112,8 +1112,8 @@ user-login = "dtolnay"
 user-name = "David Tolnay"
 
 [[publisher.regalloc2]]
-version = "0.14.0"
-when = "2026-02-14"
+version = "0.15.0"
+when = "2026-02-17"
 user-id = 3726
 user-login = "cfallin"
 user-name = "Chris Fallin"

supply-chain/imports.lock

@@ -6,7 +6,6 @@ mod arrays;
 mod async_functions;
 mod call_hook;
 mod cli_tests;
-mod code_too_large;
 mod compile_time_builtins;
 mod component_model;
 mod coredump;